1 /* $OpenBSD: if_txp.c,v 1.128 2020/07/10 13:26:38 patrick Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include "bpfilter.h" 35 #include "vlan.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/sockio.h> 40 #include <sys/mbuf.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/device.h> 45 #include <sys/timeout.h> 46 47 #include <net/if.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net/if_media.h> 53 54 #if NBPFILTER > 0 55 #include <net/bpf.h> 56 #endif 57 58 #include <machine/bus.h> 59 60 #include <dev/mii/mii.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/if_txpreg.h> 66 67 /* 68 * These currently break the 3c990 firmware, hopefully will be resolved 69 * at some point. 70 */ 71 #undef TRY_TX_UDP_CSUM 72 #undef TRY_TX_TCP_CSUM 73 74 int txp_probe(struct device *, void *, void *); 75 void txp_attach(struct device *, struct device *, void *); 76 void txp_attachhook(struct device *); 77 int txp_intr(void *); 78 void txp_tick(void *); 79 int txp_ioctl(struct ifnet *, u_long, caddr_t); 80 void txp_start(struct ifnet *); 81 void txp_stop(struct txp_softc *); 82 void txp_init(struct txp_softc *); 83 void txp_watchdog(struct ifnet *); 84 85 int txp_chip_init(struct txp_softc *); 86 int txp_reset_adapter(struct txp_softc *); 87 int txp_download_fw(struct txp_softc *); 88 int txp_download_fw_wait(struct txp_softc *); 89 int txp_download_fw_section(struct txp_softc *, 90 struct txp_fw_section_header *, int, u_char *, size_t); 91 int txp_alloc_rings(struct txp_softc *); 92 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 93 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 94 void txp_set_filter(struct txp_softc *); 95 96 int txp_cmd_desc_numfree(struct txp_softc *); 97 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 98 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 99 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 100 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 101 struct txp_rsp_desc **, int); 102 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 103 struct txp_rsp_desc **); 104 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 105 struct txp_rsp_desc *); 106 void txp_capabilities(struct txp_softc *); 107 108 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 int txp_ifmedia_upd(struct ifnet *); 110 void txp_show_descriptor(void *); 111 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 112 struct txp_dma_alloc *); 113 void txp_rxbuf_reclaim(struct txp_softc *); 114 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 115 struct txp_dma_alloc *); 116 117 struct cfattach txp_ca = { 118 sizeof(struct txp_softc), txp_probe, txp_attach, 119 }; 120 121 struct cfdriver txp_cd = { 122 NULL, "txp", DV_IFNET 123 }; 124 125 const struct pci_matchid txp_devices[] = { 126 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990 }, 127 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX }, 128 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95 }, 129 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97 }, 130 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95 }, 131 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97 }, 132 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BTXM }, 133 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR }, 134 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX }, 135 }; 136 137 int 138 txp_probe(struct device *parent, void *match, void *aux) 139 { 140 return (pci_matchbyid((struct pci_attach_args *)aux, txp_devices, 141 nitems(txp_devices))); 142 } 143 144 void 145 txp_attachhook(struct device *self) 146 { 147 struct txp_softc *sc = (struct txp_softc *)self; 148 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 149 u_int16_t p1; 150 u_int32_t p2; 151 int s; 152 153 s = splnet(); 154 printf("%s: ", sc->sc_dev.dv_xname); 155 156 if (txp_chip_init(sc)) { 157 printf("failed chip init\n"); 158 splx(s); 159 return; 160 } 161 162 if (txp_download_fw(sc)) { 163 splx(s); 164 return; 165 } 166 167 if (txp_alloc_rings(sc)) { 168 splx(s); 169 return; 170 } 171 172 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 173 NULL, NULL, NULL, 1)) { 174 splx(s); 175 return; 176 } 177 178 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 179 &p1, &p2, NULL, 1)) { 180 splx(s); 181 return; 182 } 183 184 p1 = htole16(p1); 185 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 186 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 187 p2 = htole32(p2); 188 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 189 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 190 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 191 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 192 193 printf("address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 194 sc->sc_cold = 0; 195 196 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 197 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 198 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 199 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 200 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 201 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 202 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 203 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 204 205 sc->sc_xcvr = TXP_XCVR_AUTO; 206 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 207 NULL, NULL, NULL, 0); 208 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 209 210 ifp->if_softc = sc; 211 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 212 ifp->if_ioctl = txp_ioctl; 213 ifp->if_start = txp_start; 214 ifp->if_watchdog = txp_watchdog; 215 ifp->if_baudrate = IF_Mbps(10); 216 ifq_set_maxlen(&ifp->if_snd, TX_ENTRIES); 217 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 218 219 txp_capabilities(sc); 220 221 timeout_set(&sc->sc_tick, txp_tick, sc); 222 223 /* 224 * Attach us everywhere 225 */ 226 if_attach(ifp); 227 ether_ifattach(ifp); 228 229 splx(s); 230 } 231 232 void 233 txp_attach(struct device *parent, struct device *self, void *aux) 234 { 235 struct txp_softc *sc = (struct txp_softc *)self; 236 struct pci_attach_args *pa = aux; 237 pci_chipset_tag_t pc = pa->pa_pc; 238 pci_intr_handle_t ih; 239 const char *intrstr = NULL; 240 bus_size_t iosize; 241 242 sc->sc_cold = 1; 243 244 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 245 &sc->sc_bt, &sc->sc_bh, NULL, &iosize, 0)) { 246 printf(": can't map mem space %d\n", 0); 247 return; 248 } 249 250 sc->sc_dmat = pa->pa_dmat; 251 252 /* 253 * Allocate our interrupt. 254 */ 255 if (pci_intr_map(pa, &ih)) { 256 printf(": couldn't map interrupt\n"); 257 return; 258 } 259 260 intrstr = pci_intr_string(pc, ih); 261 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc, 262 self->dv_xname); 263 if (sc->sc_ih == NULL) { 264 printf(": couldn't establish interrupt"); 265 if (intrstr != NULL) 266 printf(" at %s", intrstr); 267 printf("\n"); 268 return; 269 } 270 printf(": %s\n", intrstr); 271 272 config_mountroot(self, txp_attachhook); 273 274 } 275 276 int 277 txp_chip_init(struct txp_softc *sc) 278 { 279 /* disable interrupts */ 280 WRITE_REG(sc, TXP_IER, 0); 281 WRITE_REG(sc, TXP_IMR, 282 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 283 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 284 TXP_INT_LATCH); 285 286 /* ack all interrupts */ 287 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 288 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 289 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 290 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 291 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 292 293 if (txp_reset_adapter(sc)) 294 return (-1); 295 296 /* disable interrupts */ 297 WRITE_REG(sc, TXP_IER, 0); 298 WRITE_REG(sc, TXP_IMR, 299 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 300 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 301 TXP_INT_LATCH); 302 303 /* ack all interrupts */ 304 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 305 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 306 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 307 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 308 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 309 310 return (0); 311 } 312 313 int 314 txp_reset_adapter(struct txp_softc *sc) 315 { 316 u_int32_t r; 317 int i; 318 319 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 320 DELAY(1000); 321 WRITE_REG(sc, TXP_SRR, 0); 322 323 /* Should wait max 6 seconds */ 324 for (i = 0; i < 6000; i++) { 325 r = READ_REG(sc, TXP_A2H_0); 326 if (r == STAT_WAITING_FOR_HOST_REQUEST) 327 break; 328 DELAY(1000); 329 } 330 331 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 332 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 333 return (-1); 334 } 335 336 return (0); 337 } 338 339 int 340 txp_download_fw(struct txp_softc *sc) 341 { 342 struct txp_fw_file_header *fileheader; 343 struct txp_fw_section_header *secthead; 344 u_int32_t r, i, ier, imr; 345 size_t buflen; 346 int sect, err; 347 u_char *buf; 348 349 ier = READ_REG(sc, TXP_IER); 350 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 351 352 imr = READ_REG(sc, TXP_IMR); 353 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 354 355 for (i = 0; i < 10000; i++) { 356 r = READ_REG(sc, TXP_A2H_0); 357 if (r == STAT_WAITING_FOR_HOST_REQUEST) 358 break; 359 DELAY(50); 360 } 361 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 362 printf("not waiting for host request\n"); 363 return (-1); 364 } 365 366 /* Ack the status */ 367 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 368 369 err = loadfirmware("3c990", &buf, &buflen); 370 if (err) { 371 printf("failed loadfirmware of file 3c990: errno %d\n", 372 err); 373 return (err); 374 } 375 376 fileheader = (struct txp_fw_file_header *)buf; 377 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 378 printf("firmware invalid magic\n"); 379 goto fail; 380 } 381 382 /* Tell boot firmware to get ready for image */ 383 WRITE_REG(sc, TXP_H2A_1, letoh32(fileheader->addr)); 384 WRITE_REG(sc, TXP_H2A_2, letoh32(fileheader->hmac[0])); 385 WRITE_REG(sc, TXP_H2A_3, letoh32(fileheader->hmac[1])); 386 WRITE_REG(sc, TXP_H2A_4, letoh32(fileheader->hmac[2])); 387 WRITE_REG(sc, TXP_H2A_5, letoh32(fileheader->hmac[3])); 388 WRITE_REG(sc, TXP_H2A_6, letoh32(fileheader->hmac[4])); 389 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 390 391 if (txp_download_fw_wait(sc)) { 392 printf("fw wait failed, initial\n"); 393 goto fail; 394 } 395 396 secthead = (struct txp_fw_section_header *)(buf + 397 sizeof(struct txp_fw_file_header)); 398 399 for (sect = 0; sect < letoh32(fileheader->nsections); sect++) { 400 if (txp_download_fw_section(sc, secthead, sect, buf, buflen)) 401 goto fail; 402 secthead = (struct txp_fw_section_header *) 403 (((u_int8_t *)secthead) + letoh32(secthead->nbytes) + 404 sizeof(*secthead)); 405 } 406 407 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 408 409 for (i = 0; i < 10000; i++) { 410 r = READ_REG(sc, TXP_A2H_0); 411 if (r == STAT_WAITING_FOR_BOOT) 412 break; 413 DELAY(50); 414 } 415 if (r != STAT_WAITING_FOR_BOOT) { 416 printf("not waiting for boot\n"); 417 goto fail; 418 } 419 420 WRITE_REG(sc, TXP_IER, ier); 421 WRITE_REG(sc, TXP_IMR, imr); 422 423 free(buf, M_DEVBUF, 0); 424 return (0); 425 fail: 426 free(buf, M_DEVBUF, 0); 427 return (-1); 428 } 429 430 int 431 txp_download_fw_wait(struct txp_softc *sc) 432 { 433 u_int32_t i, r; 434 435 for (i = 0; i < 10000; i++) { 436 r = READ_REG(sc, TXP_ISR); 437 if (r & TXP_INT_A2H_0) 438 break; 439 DELAY(50); 440 } 441 442 if (!(r & TXP_INT_A2H_0)) { 443 printf("fw wait failed comm0\n"); 444 return (-1); 445 } 446 447 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 448 449 r = READ_REG(sc, TXP_A2H_0); 450 if (r != STAT_WAITING_FOR_SEGMENT) { 451 printf("fw not waiting for segment\n"); 452 return (-1); 453 } 454 return (0); 455 } 456 457 int 458 txp_download_fw_section(struct txp_softc *sc, 459 struct txp_fw_section_header *sect, int sectnum, u_char *buf, 460 size_t buflen) 461 { 462 struct txp_dma_alloc dma; 463 int rseg, err = 0; 464 struct mbuf m; 465 u_int16_t csum; 466 467 /* Skip zero length sections */ 468 if (sect->nbytes == 0) 469 return (0); 470 471 /* Make sure we aren't past the end of the image */ 472 rseg = ((u_int8_t *)sect) - ((u_int8_t *)buf); 473 if (rseg >= buflen) { 474 printf("fw invalid section address, section %d\n", sectnum); 475 return (-1); 476 } 477 478 /* Make sure this section doesn't go past the end */ 479 rseg += letoh32(sect->nbytes); 480 if (rseg >= buflen) { 481 printf("fw truncated section %d\n", sectnum); 482 return (-1); 483 } 484 485 /* map a buffer, copy segment to it, get physaddr */ 486 if (txp_dma_malloc(sc, letoh32(sect->nbytes), &dma, 0)) { 487 printf("fw dma malloc failed, section %d\n", sectnum); 488 return (-1); 489 } 490 491 bcopy(((u_int8_t *)sect) + sizeof(*sect), dma.dma_vaddr, 492 letoh32(sect->nbytes)); 493 494 /* 495 * dummy up mbuf and verify section checksum 496 */ 497 m.m_type = MT_DATA; 498 m.m_next = m.m_nextpkt = NULL; 499 m.m_len = letoh32(sect->nbytes); 500 m.m_data = dma.dma_vaddr; 501 m.m_flags = 0; 502 csum = in_cksum(&m, letoh32(sect->nbytes)); 503 if (csum != sect->cksum) { 504 printf("fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 505 sectnum, sect->cksum, csum); 506 err = -1; 507 goto bail; 508 } 509 510 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 511 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 512 513 WRITE_REG(sc, TXP_H2A_1, letoh32(sect->nbytes)); 514 WRITE_REG(sc, TXP_H2A_2, letoh16(sect->cksum)); 515 WRITE_REG(sc, TXP_H2A_3, letoh32(sect->addr)); 516 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 517 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 518 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 519 520 if (txp_download_fw_wait(sc)) { 521 printf("%s: fw wait failed, section %d\n", 522 sc->sc_dev.dv_xname, sectnum); 523 err = -1; 524 } 525 526 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 527 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 528 529 bail: 530 txp_dma_free(sc, &dma); 531 532 return (err); 533 } 534 535 int 536 txp_intr(void *vsc) 537 { 538 struct txp_softc *sc = vsc; 539 struct txp_hostvar *hv = sc->sc_hostvar; 540 u_int32_t isr; 541 int claimed = 0; 542 543 /* mask all interrupts */ 544 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 545 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 546 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 547 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 548 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 549 550 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 551 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 552 553 isr = READ_REG(sc, TXP_ISR); 554 while (isr) { 555 claimed = 1; 556 WRITE_REG(sc, TXP_ISR, isr); 557 558 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 559 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 560 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 561 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 562 563 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 564 txp_rxbuf_reclaim(sc); 565 566 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 567 TXP_OFFSET2IDX(letoh32(*(sc->sc_txhir.r_off))))) 568 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 569 570 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 571 TXP_OFFSET2IDX(letoh32(*(sc->sc_txlor.r_off))))) 572 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 573 574 isr = READ_REG(sc, TXP_ISR); 575 } 576 577 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 578 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 579 580 /* unmask all interrupts */ 581 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 582 583 txp_start(&sc->sc_arpcom.ac_if); 584 585 return (claimed); 586 } 587 588 void 589 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 590 struct txp_dma_alloc *dma) 591 { 592 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 593 struct txp_rx_desc *rxd; 594 struct mbuf *m; 595 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 596 struct txp_swdesc *sd; 597 u_int32_t roff, woff; 598 int idx; 599 u_int16_t sumflags = 0; 600 601 roff = letoh32(*r->r_roff); 602 woff = letoh32(*r->r_woff); 603 idx = roff / sizeof(struct txp_rx_desc); 604 rxd = r->r_desc + idx; 605 606 while (roff != woff) { 607 608 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 609 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 610 BUS_DMASYNC_POSTREAD); 611 612 if (rxd->rx_flags & RX_FLAGS_ERROR) { 613 printf("%s: error 0x%x\n", sc->sc_dev.dv_xname, 614 letoh32(rxd->rx_stat)); 615 ifp->if_ierrors++; 616 goto next; 617 } 618 619 /* retrieve stashed pointer */ 620 bcopy((u_long *)&rxd->rx_vaddrlo, &sd, sizeof(sd)); 621 622 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 623 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 624 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 625 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 626 m = sd->sd_mbuf; 627 free(sd, M_DEVBUF, 0); 628 m->m_pkthdr.len = m->m_len = letoh16(rxd->rx_len); 629 630 #ifdef __STRICT_ALIGNMENT 631 { 632 /* 633 * XXX Nice chip, except it won't accept "off by 2" 634 * buffers, so we're force to copy. Supposedly 635 * this will be fixed in a newer firmware rev 636 * and this will be temporary. 637 */ 638 struct mbuf *mnew; 639 640 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 641 if (mnew == NULL) { 642 m_freem(m); 643 goto next; 644 } 645 if (m->m_len > (MHLEN - 2)) { 646 MCLGET(mnew, M_DONTWAIT); 647 if (!(mnew->m_flags & M_EXT)) { 648 m_freem(mnew); 649 m_freem(m); 650 goto next; 651 } 652 } 653 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 654 mnew->m_data += 2; 655 bcopy(m->m_data, mnew->m_data, m->m_len); 656 m_freem(m); 657 m = mnew; 658 } 659 #endif 660 661 #if NVLAN > 0 662 /* 663 * XXX Another firmware bug: the vlan encapsulation 664 * is always removed, even when we tell the card not 665 * to do that. Restore the vlan encapsulation below. 666 */ 667 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 668 m->m_pkthdr.ether_vtag = ntohs(rxd->rx_vlan >> 16); 669 m->m_flags |= M_VLANTAG; 670 } 671 #endif 672 673 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 674 sumflags |= M_IPV4_CSUM_IN_BAD; 675 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 676 sumflags |= M_IPV4_CSUM_IN_OK; 677 678 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 679 sumflags |= M_TCP_CSUM_IN_BAD; 680 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 681 sumflags |= M_TCP_CSUM_IN_OK; 682 683 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 684 sumflags |= M_UDP_CSUM_IN_BAD; 685 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 686 sumflags |= M_UDP_CSUM_IN_OK; 687 688 m->m_pkthdr.csum_flags = sumflags; 689 690 ml_enqueue(&ml, m); 691 692 next: 693 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 694 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 695 BUS_DMASYNC_PREREAD); 696 697 roff += sizeof(struct txp_rx_desc); 698 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 699 idx = 0; 700 roff = 0; 701 rxd = r->r_desc; 702 } else { 703 idx++; 704 rxd++; 705 } 706 woff = letoh32(*r->r_woff); 707 } 708 709 if_input(ifp, &ml); 710 711 *r->r_roff = htole32(woff); 712 } 713 714 void 715 txp_rxbuf_reclaim(struct txp_softc *sc) 716 { 717 struct txp_hostvar *hv = sc->sc_hostvar; 718 struct txp_rxbuf_desc *rbd; 719 struct txp_swdesc *sd; 720 u_int32_t i, end; 721 722 end = TXP_OFFSET2IDX(letoh32(hv->hv_rx_buf_read_idx)); 723 i = TXP_OFFSET2IDX(letoh32(hv->hv_rx_buf_write_idx)); 724 725 if (++i == RXBUF_ENTRIES) 726 i = 0; 727 728 rbd = sc->sc_rxbufs + i; 729 730 while (i != end) { 731 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 732 M_DEVBUF, M_NOWAIT); 733 if (sd == NULL) 734 break; 735 736 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 737 if (sd->sd_mbuf == NULL) 738 goto err_sd; 739 740 MCLGET(sd->sd_mbuf, M_DONTWAIT); 741 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 742 goto err_mbuf; 743 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 744 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 745 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 746 goto err_mbuf; 747 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 748 BUS_DMA_NOWAIT)) { 749 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 750 goto err_mbuf; 751 } 752 753 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 754 i * sizeof(struct txp_rxbuf_desc), 755 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 756 757 /* stash away pointer */ 758 bcopy(&sd, (u_long *)&rbd->rb_vaddrlo, sizeof(sd)); 759 760 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 761 & 0xffffffff; 762 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 763 >> 32; 764 765 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 766 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 767 768 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 769 i * sizeof(struct txp_rxbuf_desc), 770 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 771 772 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 773 774 if (++i == RXBUF_ENTRIES) { 775 i = 0; 776 rbd = sc->sc_rxbufs; 777 } else 778 rbd++; 779 } 780 return; 781 782 err_mbuf: 783 m_freem(sd->sd_mbuf); 784 err_sd: 785 free(sd, M_DEVBUF, 0); 786 } 787 788 /* 789 * Reclaim mbufs and entries from a transmit ring. 790 */ 791 void 792 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 793 struct txp_dma_alloc *dma) 794 { 795 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 796 u_int32_t idx = TXP_OFFSET2IDX(letoh32(*(r->r_off))); 797 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 798 struct txp_tx_desc *txd = r->r_desc + cons; 799 struct txp_swdesc *sd = sc->sc_txd + cons; 800 struct mbuf *m; 801 802 while (cons != idx) { 803 if (cnt == 0) 804 break; 805 806 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 807 cons * sizeof(struct txp_tx_desc), 808 sizeof(struct txp_tx_desc), 809 BUS_DMASYNC_POSTWRITE); 810 811 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 812 TX_FLAGS_TYPE_DATA) { 813 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 814 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 815 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 816 m = sd->sd_mbuf; 817 if (m != NULL) { 818 m_freem(m); 819 txd->tx_addrlo = 0; 820 txd->tx_addrhi = 0; 821 } 822 } 823 ifq_clr_oactive(&ifp->if_snd); 824 825 if (++cons == TX_ENTRIES) { 826 txd = r->r_desc; 827 cons = 0; 828 sd = sc->sc_txd; 829 } else { 830 txd++; 831 sd++; 832 } 833 834 cnt--; 835 } 836 837 r->r_cons = cons; 838 r->r_cnt = cnt; 839 if (cnt == 0) 840 ifp->if_timer = 0; 841 } 842 843 int 844 txp_alloc_rings(struct txp_softc *sc) 845 { 846 struct txp_boot_record *boot; 847 struct txp_swdesc *sd; 848 u_int32_t r; 849 int i, j; 850 851 /* boot record */ 852 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 853 BUS_DMA_COHERENT)) { 854 printf("can't allocate boot record\n"); 855 return (-1); 856 } 857 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 858 bzero(boot, sizeof(*boot)); 859 sc->sc_boot = boot; 860 861 /* host variables */ 862 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 863 BUS_DMA_COHERENT)) { 864 printf("can't allocate host ring\n"); 865 goto bail_boot; 866 } 867 bzero(sc->sc_host_dma.dma_vaddr, sizeof(struct txp_hostvar)); 868 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 869 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 870 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 871 872 /* high priority tx ring */ 873 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 874 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 875 printf("can't allocate high tx ring\n"); 876 goto bail_host; 877 } 878 bzero(sc->sc_txhiring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 879 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 880 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 881 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 882 sc->sc_txhir.r_reg = TXP_H2A_1; 883 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 884 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 885 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 886 for (i = 0; i < TX_ENTRIES; i++) { 887 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 888 TXP_MAXTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 889 &sc->sc_txd[i].sd_map) != 0) { 890 for (j = 0; j < i; j++) { 891 bus_dmamap_destroy(sc->sc_dmat, 892 sc->sc_txd[j].sd_map); 893 sc->sc_txd[j].sd_map = NULL; 894 } 895 goto bail_txhiring; 896 } 897 } 898 899 /* low priority tx ring */ 900 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 901 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 902 printf("can't allocate low tx ring\n"); 903 goto bail_txhiring; 904 } 905 bzero(sc->sc_txloring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 906 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 907 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 908 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 909 sc->sc_txlor.r_reg = TXP_H2A_3; 910 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 911 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 912 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 913 914 /* high priority rx ring */ 915 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 916 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 917 printf("can't allocate high rx ring\n"); 918 goto bail_txloring; 919 } 920 bzero(sc->sc_rxhiring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 921 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 922 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 923 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 924 sc->sc_rxhir.r_desc = 925 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 926 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 927 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 928 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 929 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 930 931 /* low priority ring */ 932 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 933 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 934 printf("can't allocate low rx ring\n"); 935 goto bail_rxhiring; 936 } 937 bzero(sc->sc_rxloring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 938 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 939 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 940 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 941 sc->sc_rxlor.r_desc = 942 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 943 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 944 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 945 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 946 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 947 948 /* command ring */ 949 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 950 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 951 printf("can't allocate command ring\n"); 952 goto bail_rxloring; 953 } 954 bzero(sc->sc_cmdring_dma.dma_vaddr, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 955 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 956 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 957 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 958 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 959 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 960 sc->sc_cmdring.lastwrite = 0; 961 962 /* response ring */ 963 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 964 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 965 printf("can't allocate response ring\n"); 966 goto bail_cmdring; 967 } 968 bzero(sc->sc_rspring_dma.dma_vaddr, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 969 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 970 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 971 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 972 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 973 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 974 sc->sc_rspring.lastwrite = 0; 975 976 /* receive buffer ring */ 977 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 978 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 979 printf("can't allocate rx buffer ring\n"); 980 goto bail_rspring; 981 } 982 bzero(sc->sc_rxbufring_dma.dma_vaddr, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 983 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 984 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 985 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 986 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 987 for (i = 0; i < RXBUF_ENTRIES; i++) { 988 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 989 M_DEVBUF, M_NOWAIT); 990 991 /* stash away pointer */ 992 bcopy(&sd, (u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, sizeof(sd)); 993 994 if (sd == NULL) 995 break; 996 997 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 998 if (sd->sd_mbuf == NULL) { 999 goto bail_rxbufring; 1000 } 1001 1002 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1003 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1004 goto bail_rxbufring; 1005 } 1006 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1007 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1008 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1009 goto bail_rxbufring; 1010 } 1011 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1012 BUS_DMA_NOWAIT)) { 1013 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1014 goto bail_rxbufring; 1015 } 1016 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1017 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1018 1019 sc->sc_rxbufs[i].rb_paddrlo = 1020 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1021 sc->sc_rxbufs[i].rb_paddrhi = 1022 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1023 } 1024 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1025 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1026 BUS_DMASYNC_PREWRITE); 1027 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1028 sizeof(struct txp_rxbuf_desc)); 1029 1030 /* zero dma */ 1031 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1032 BUS_DMA_COHERENT)) { 1033 printf("can't allocate response ring\n"); 1034 goto bail_rxbufring; 1035 } 1036 bzero(sc->sc_zero_dma.dma_vaddr, sizeof(u_int32_t)); 1037 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1038 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1039 1040 /* See if it's waiting for boot, and try to boot it */ 1041 for (i = 0; i < 10000; i++) { 1042 r = READ_REG(sc, TXP_A2H_0); 1043 if (r == STAT_WAITING_FOR_BOOT) 1044 break; 1045 DELAY(50); 1046 } 1047 if (r != STAT_WAITING_FOR_BOOT) { 1048 printf("not waiting for boot\n"); 1049 goto bail; 1050 } 1051 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1052 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1053 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1054 1055 /* See if it booted */ 1056 for (i = 0; i < 10000; i++) { 1057 r = READ_REG(sc, TXP_A2H_0); 1058 if (r == STAT_RUNNING) 1059 break; 1060 DELAY(50); 1061 } 1062 if (r != STAT_RUNNING) { 1063 printf("fw not running\n"); 1064 goto bail; 1065 } 1066 1067 /* Clear TX and CMD ring write registers */ 1068 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1069 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1070 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1071 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1072 1073 return (0); 1074 1075 bail: 1076 txp_dma_free(sc, &sc->sc_zero_dma); 1077 bail_rxbufring: 1078 for (i = 0; i < RXBUF_ENTRIES; i++) { 1079 bcopy((u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, &sd, sizeof(sd)); 1080 if (sd) 1081 free(sd, M_DEVBUF, 0); 1082 } 1083 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1084 bail_rspring: 1085 txp_dma_free(sc, &sc->sc_rspring_dma); 1086 bail_cmdring: 1087 txp_dma_free(sc, &sc->sc_cmdring_dma); 1088 bail_rxloring: 1089 txp_dma_free(sc, &sc->sc_rxloring_dma); 1090 bail_rxhiring: 1091 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1092 bail_txloring: 1093 txp_dma_free(sc, &sc->sc_txloring_dma); 1094 bail_txhiring: 1095 txp_dma_free(sc, &sc->sc_txhiring_dma); 1096 bail_host: 1097 txp_dma_free(sc, &sc->sc_host_dma); 1098 bail_boot: 1099 txp_dma_free(sc, &sc->sc_boot_dma); 1100 return (-1); 1101 } 1102 1103 int 1104 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1105 struct txp_dma_alloc *dma, int mapflags) 1106 { 1107 int r; 1108 1109 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1110 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1111 goto fail_0; 1112 1113 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1114 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1115 goto fail_1; 1116 1117 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1118 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1119 goto fail_2; 1120 1121 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1122 size, NULL, BUS_DMA_NOWAIT)) != 0) 1123 goto fail_3; 1124 1125 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1126 return (0); 1127 1128 fail_3: 1129 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1130 fail_2: 1131 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1132 fail_1: 1133 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1134 fail_0: 1135 return (r); 1136 } 1137 1138 void 1139 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1140 { 1141 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1142 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1143 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1144 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1145 } 1146 1147 int 1148 txp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1149 { 1150 struct txp_softc *sc = ifp->if_softc; 1151 struct ifreq *ifr = (struct ifreq *) data; 1152 int s, error = 0; 1153 1154 s = splnet(); 1155 1156 switch(command) { 1157 case SIOCSIFADDR: 1158 ifp->if_flags |= IFF_UP; 1159 txp_init(sc); 1160 break; 1161 1162 case SIOCSIFFLAGS: 1163 if (ifp->if_flags & IFF_UP) { 1164 txp_init(sc); 1165 } else { 1166 if (ifp->if_flags & IFF_RUNNING) 1167 txp_stop(sc); 1168 } 1169 break; 1170 1171 case SIOCGIFMEDIA: 1172 case SIOCSIFMEDIA: 1173 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1174 break; 1175 1176 default: 1177 error = ether_ioctl(ifp, &sc->sc_arpcom, command, data); 1178 } 1179 1180 if (error == ENETRESET) { 1181 if (ifp->if_flags & IFF_RUNNING) 1182 txp_set_filter(sc); 1183 error = 0; 1184 } 1185 1186 splx(s); 1187 return(error); 1188 } 1189 1190 void 1191 txp_init(struct txp_softc *sc) 1192 { 1193 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1194 int s; 1195 1196 txp_stop(sc); 1197 1198 s = splnet(); 1199 1200 txp_set_filter(sc); 1201 1202 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1203 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1204 1205 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1206 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1207 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1208 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1209 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1210 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1211 1212 ifp->if_flags |= IFF_RUNNING; 1213 ifq_clr_oactive(&ifp->if_snd); 1214 1215 if (!timeout_pending(&sc->sc_tick)) 1216 timeout_add_sec(&sc->sc_tick, 1); 1217 1218 splx(s); 1219 } 1220 1221 void 1222 txp_tick(void *vsc) 1223 { 1224 struct txp_softc *sc = vsc; 1225 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1226 struct txp_rsp_desc *rsp = NULL; 1227 struct txp_ext_desc *ext; 1228 int s; 1229 1230 s = splnet(); 1231 txp_rxbuf_reclaim(sc); 1232 1233 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1234 &rsp, 1)) 1235 goto out; 1236 if (rsp->rsp_numdesc != 6) 1237 goto out; 1238 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1239 NULL, NULL, NULL, 1)) 1240 goto out; 1241 ext = (struct txp_ext_desc *)(rsp + 1); 1242 1243 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1244 ext[4].ext_1 + ext[4].ext_4; 1245 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1246 ext[2].ext_1; 1247 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1248 ext[1].ext_3; 1249 1250 out: 1251 if (rsp != NULL) 1252 free(rsp, M_DEVBUF, 0); 1253 1254 splx(s); 1255 timeout_add_sec(&sc->sc_tick, 1); 1256 } 1257 1258 void 1259 txp_start(struct ifnet *ifp) 1260 { 1261 struct txp_softc *sc = ifp->if_softc; 1262 struct txp_tx_ring *r = &sc->sc_txhir; 1263 struct txp_tx_desc *txd; 1264 int txdidx; 1265 struct txp_frag_desc *fxd; 1266 struct mbuf *m; 1267 struct txp_swdesc *sd; 1268 u_int32_t prod, cnt, i; 1269 1270 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1271 return; 1272 1273 prod = r->r_prod; 1274 cnt = r->r_cnt; 1275 1276 while (1) { 1277 if (cnt >= TX_ENTRIES - TXP_MAXTXSEGS - 4) 1278 goto oactive; 1279 1280 m = ifq_dequeue(&ifp->if_snd); 1281 if (m == NULL) 1282 break; 1283 1284 sd = sc->sc_txd + prod; 1285 sd->sd_mbuf = m; 1286 1287 switch (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1288 BUS_DMA_NOWAIT)) { 1289 case 0: 1290 break; 1291 case EFBIG: 1292 if (m_defrag(m, M_DONTWAIT) == 0 && 1293 bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1294 BUS_DMA_NOWAIT) == 0) 1295 break; 1296 default: 1297 m_freem(m); 1298 continue; 1299 } 1300 1301 txd = r->r_desc + prod; 1302 txdidx = prod; 1303 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1304 txd->tx_numdesc = 0; 1305 txd->tx_addrlo = 0; 1306 txd->tx_addrhi = 0; 1307 txd->tx_totlen = m->m_pkthdr.len; 1308 txd->tx_pflags = 0; 1309 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1310 1311 if (++prod == TX_ENTRIES) 1312 prod = 0; 1313 1314 #if NVLAN > 0 1315 if (m->m_flags & M_VLANTAG) { 1316 txd->tx_pflags = TX_PFLAGS_VLAN | 1317 (htons(m->m_pkthdr.ether_vtag) << TX_PFLAGS_VLANTAG_S); 1318 } 1319 #endif 1320 1321 if (m->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1322 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1323 #ifdef TRY_TX_TCP_CSUM 1324 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1325 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1326 #endif 1327 #ifdef TRY_TX_UDP_CSUM 1328 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1329 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1330 #endif 1331 1332 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1333 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1334 1335 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1336 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1337 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1338 FRAG_FLAGS_VALID; 1339 fxd->frag_rsvd1 = 0; 1340 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1341 fxd->frag_addrlo = 1342 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1343 0xffffffff; 1344 fxd->frag_addrhi = 1345 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1346 32; 1347 fxd->frag_rsvd2 = 0; 1348 1349 bus_dmamap_sync(sc->sc_dmat, 1350 sc->sc_txhiring_dma.dma_map, 1351 prod * sizeof(struct txp_frag_desc), 1352 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1353 1354 if (++prod == TX_ENTRIES) { 1355 fxd = (struct txp_frag_desc *)r->r_desc; 1356 prod = 0; 1357 } else 1358 fxd++; 1359 1360 } 1361 1362 ifp->if_timer = 5; 1363 1364 #if NBPFILTER > 0 1365 if (ifp->if_bpf) 1366 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1367 #endif 1368 1369 txd->tx_flags |= TX_FLAGS_VALID; 1370 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1371 txdidx * sizeof(struct txp_tx_desc), 1372 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1373 1374 #if 0 1375 { 1376 struct mbuf *mx; 1377 int i; 1378 1379 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1380 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1381 txd->tx_pflags); 1382 for (mx = m; mx != NULL; mx = mx->m_next) { 1383 for (i = 0; i < mx->m_len; i++) { 1384 printf(":%02x", 1385 (u_int8_t)m->m_data[i]); 1386 } 1387 } 1388 printf("\n"); 1389 } 1390 #endif 1391 1392 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1393 } 1394 1395 r->r_prod = prod; 1396 r->r_cnt = cnt; 1397 return; 1398 1399 oactive: 1400 ifq_set_oactive(&ifp->if_snd); 1401 r->r_prod = prod; 1402 r->r_cnt = cnt; 1403 } 1404 1405 /* 1406 * Handle simple commands sent to the typhoon 1407 */ 1408 int 1409 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, 1410 u_int32_t in2, u_int32_t in3, u_int16_t *out1, u_int32_t *out2, 1411 u_int32_t *out3, int wait) 1412 { 1413 struct txp_rsp_desc *rsp = NULL; 1414 1415 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1416 return (-1); 1417 1418 if (!wait) 1419 return (0); 1420 1421 if (out1 != NULL) 1422 *out1 = letoh16(rsp->rsp_par1); 1423 if (out2 != NULL) 1424 *out2 = letoh32(rsp->rsp_par2); 1425 if (out3 != NULL) 1426 *out3 = letoh32(rsp->rsp_par3); 1427 free(rsp, M_DEVBUF, 0); 1428 return (0); 1429 } 1430 1431 int 1432 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, 1433 u_int32_t in2, u_int32_t in3, struct txp_ext_desc *in_extp, 1434 u_int8_t in_extn,struct txp_rsp_desc **rspp, int wait) 1435 { 1436 struct txp_hostvar *hv = sc->sc_hostvar; 1437 struct txp_cmd_desc *cmd; 1438 struct txp_ext_desc *ext; 1439 u_int32_t idx, i; 1440 u_int16_t seq; 1441 1442 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1443 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1444 return (-1); 1445 } 1446 1447 idx = sc->sc_cmdring.lastwrite; 1448 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1449 bzero(cmd, sizeof(*cmd)); 1450 1451 cmd->cmd_numdesc = in_extn; 1452 seq = sc->sc_seq++; 1453 cmd->cmd_seq = htole16(seq); 1454 cmd->cmd_id = htole16(id); 1455 cmd->cmd_par1 = htole16(in1); 1456 cmd->cmd_par2 = htole32(in2); 1457 cmd->cmd_par3 = htole32(in3); 1458 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1459 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1460 1461 idx += sizeof(struct txp_cmd_desc); 1462 if (idx == sc->sc_cmdring.size) 1463 idx = 0; 1464 1465 for (i = 0; i < in_extn; i++) { 1466 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1467 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1468 in_extp++; 1469 idx += sizeof(struct txp_cmd_desc); 1470 if (idx == sc->sc_cmdring.size) 1471 idx = 0; 1472 } 1473 1474 sc->sc_cmdring.lastwrite = idx; 1475 1476 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1477 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1478 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1479 1480 if (!wait) 1481 return (0); 1482 1483 for (i = 0; i < 10000; i++) { 1484 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1485 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1486 idx = letoh32(hv->hv_resp_read_idx); 1487 if (idx != letoh32(hv->hv_resp_write_idx)) { 1488 *rspp = NULL; 1489 if (txp_response(sc, idx, id, seq, rspp)) 1490 return (-1); 1491 if (*rspp != NULL) 1492 break; 1493 } 1494 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1495 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1496 DELAY(50); 1497 } 1498 if (i == 1000 || (*rspp) == NULL) { 1499 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1500 return (-1); 1501 } 1502 1503 return (0); 1504 } 1505 1506 int 1507 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, 1508 u_int16_t seq, struct txp_rsp_desc **rspp) 1509 { 1510 struct txp_hostvar *hv = sc->sc_hostvar; 1511 struct txp_rsp_desc *rsp; 1512 1513 while (ridx != letoh32(hv->hv_resp_write_idx)) { 1514 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1515 1516 if (id == letoh16(rsp->rsp_id) && letoh16(rsp->rsp_seq) == seq) { 1517 *rspp = mallocarray(rsp->rsp_numdesc + 1, 1518 sizeof(struct txp_rsp_desc), M_DEVBUF, M_NOWAIT); 1519 if ((*rspp) == NULL) 1520 return (-1); 1521 txp_rsp_fixup(sc, rsp, *rspp); 1522 return (0); 1523 } 1524 1525 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1526 printf("%s: response error: id 0x%x\n", 1527 TXP_DEVNAME(sc), letoh16(rsp->rsp_id)); 1528 txp_rsp_fixup(sc, rsp, NULL); 1529 ridx = letoh32(hv->hv_resp_read_idx); 1530 continue; 1531 } 1532 1533 switch (letoh16(rsp->rsp_id)) { 1534 case TXP_CMD_CYCLE_STATISTICS: 1535 case TXP_CMD_MEDIA_STATUS_READ: 1536 break; 1537 case TXP_CMD_HELLO_RESPONSE: 1538 printf("%s: hello\n", TXP_DEVNAME(sc)); 1539 break; 1540 default: 1541 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1542 letoh16(rsp->rsp_id)); 1543 } 1544 1545 txp_rsp_fixup(sc, rsp, NULL); 1546 ridx = letoh32(hv->hv_resp_read_idx); 1547 hv->hv_resp_read_idx = letoh32(ridx); 1548 } 1549 1550 return (0); 1551 } 1552 1553 void 1554 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1555 struct txp_rsp_desc *dst) 1556 { 1557 struct txp_rsp_desc *src = rsp; 1558 struct txp_hostvar *hv = sc->sc_hostvar; 1559 u_int32_t i, ridx; 1560 1561 ridx = letoh32(hv->hv_resp_read_idx); 1562 1563 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1564 if (dst != NULL) 1565 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1566 ridx += sizeof(struct txp_rsp_desc); 1567 if (ridx == sc->sc_rspring.size) { 1568 src = sc->sc_rspring.base; 1569 ridx = 0; 1570 } else 1571 src++; 1572 sc->sc_rspring.lastwrite = ridx; 1573 hv->hv_resp_read_idx = htole32(ridx); 1574 } 1575 1576 hv->hv_resp_read_idx = htole32(ridx); 1577 } 1578 1579 int 1580 txp_cmd_desc_numfree(struct txp_softc *sc) 1581 { 1582 struct txp_hostvar *hv = sc->sc_hostvar; 1583 struct txp_boot_record *br = sc->sc_boot; 1584 u_int32_t widx, ridx, nfree; 1585 1586 widx = sc->sc_cmdring.lastwrite; 1587 ridx = letoh32(hv->hv_cmd_read_idx); 1588 1589 if (widx == ridx) { 1590 /* Ring is completely free */ 1591 nfree = letoh32(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1592 } else { 1593 if (widx > ridx) 1594 nfree = letoh32(br->br_cmd_siz) - 1595 (widx - ridx + sizeof(struct txp_cmd_desc)); 1596 else 1597 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1598 } 1599 1600 return (nfree / sizeof(struct txp_cmd_desc)); 1601 } 1602 1603 void 1604 txp_stop(struct txp_softc *sc) 1605 { 1606 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1607 1608 timeout_del(&sc->sc_tick); 1609 1610 /* Mark the interface as down and cancel the watchdog timer. */ 1611 ifp->if_flags &= ~IFF_RUNNING; 1612 ifq_clr_oactive(&ifp->if_snd); 1613 ifp->if_timer = 0; 1614 1615 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1616 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1617 } 1618 1619 void 1620 txp_watchdog(struct ifnet *ifp) 1621 { 1622 } 1623 1624 int 1625 txp_ifmedia_upd(struct ifnet *ifp) 1626 { 1627 struct txp_softc *sc = ifp->if_softc; 1628 struct ifmedia *ifm = &sc->sc_ifmedia; 1629 u_int16_t new_xcvr; 1630 1631 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1632 return (EINVAL); 1633 1634 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1635 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1636 new_xcvr = TXP_XCVR_10_FDX; 1637 else 1638 new_xcvr = TXP_XCVR_10_HDX; 1639 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1640 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1641 new_xcvr = TXP_XCVR_100_FDX; 1642 else 1643 new_xcvr = TXP_XCVR_100_HDX; 1644 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1645 new_xcvr = TXP_XCVR_AUTO; 1646 } else 1647 return (EINVAL); 1648 1649 /* nothing to do */ 1650 if (sc->sc_xcvr == new_xcvr) 1651 return (0); 1652 1653 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1654 NULL, NULL, NULL, 0); 1655 sc->sc_xcvr = new_xcvr; 1656 1657 return (0); 1658 } 1659 1660 void 1661 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1662 { 1663 struct txp_softc *sc = ifp->if_softc; 1664 struct ifmedia *ifm = &sc->sc_ifmedia; 1665 u_int16_t bmsr, bmcr, anar, anlpar; 1666 1667 ifmr->ifm_status = IFM_AVALID; 1668 ifmr->ifm_active = IFM_ETHER; 1669 1670 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1671 &bmsr, NULL, NULL, 1)) 1672 goto bail; 1673 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1674 &bmsr, NULL, NULL, 1)) 1675 goto bail; 1676 1677 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1678 &bmcr, NULL, NULL, 1)) 1679 goto bail; 1680 1681 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANAR, 0, 1682 &anar, NULL, NULL, 1)) 1683 goto bail; 1684 1685 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1686 &anlpar, NULL, NULL, 1)) 1687 goto bail; 1688 1689 if (bmsr & BMSR_LINK) 1690 ifmr->ifm_status |= IFM_ACTIVE; 1691 1692 if (bmcr & BMCR_ISO) { 1693 ifmr->ifm_active |= IFM_NONE; 1694 ifmr->ifm_status = 0; 1695 return; 1696 } 1697 1698 if (bmcr & BMCR_LOOP) 1699 ifmr->ifm_active |= IFM_LOOP; 1700 1701 if (bmcr & BMCR_AUTOEN) { 1702 if ((bmsr & BMSR_ACOMP) == 0) { 1703 ifmr->ifm_active |= IFM_NONE; 1704 return; 1705 } 1706 1707 anlpar &= anar; 1708 if (anlpar & ANLPAR_TX_FD) 1709 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1710 else if (anlpar & ANLPAR_T4) 1711 ifmr->ifm_active |= IFM_100_T4|IFM_HDX; 1712 else if (anlpar & ANLPAR_TX) 1713 ifmr->ifm_active |= IFM_100_TX|IFM_HDX; 1714 else if (anlpar & ANLPAR_10_FD) 1715 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1716 else if (anlpar & ANLPAR_10) 1717 ifmr->ifm_active |= IFM_10_T|IFM_HDX; 1718 else 1719 ifmr->ifm_active |= IFM_NONE; 1720 } else 1721 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1722 return; 1723 1724 bail: 1725 ifmr->ifm_active |= IFM_NONE; 1726 ifmr->ifm_status &= ~IFM_AVALID; 1727 } 1728 1729 void 1730 txp_show_descriptor(void *d) 1731 { 1732 struct txp_cmd_desc *cmd = d; 1733 struct txp_rsp_desc *rsp = d; 1734 struct txp_tx_desc *txd = d; 1735 struct txp_frag_desc *frgd = d; 1736 1737 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1738 case CMD_FLAGS_TYPE_CMD: 1739 /* command descriptor */ 1740 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1741 cmd->cmd_flags, cmd->cmd_numdesc, letoh16(cmd->cmd_id), 1742 letoh16(cmd->cmd_seq), letoh16(cmd->cmd_par1), 1743 letoh32(cmd->cmd_par2), letoh32(cmd->cmd_par3)); 1744 break; 1745 case CMD_FLAGS_TYPE_RESP: 1746 /* response descriptor */ 1747 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1748 rsp->rsp_flags, rsp->rsp_numdesc, letoh16(rsp->rsp_id), 1749 letoh16(rsp->rsp_seq), letoh16(rsp->rsp_par1), 1750 letoh32(rsp->rsp_par2), letoh32(rsp->rsp_par3)); 1751 break; 1752 case CMD_FLAGS_TYPE_DATA: 1753 /* data header (assuming tx for now) */ 1754 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1755 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1756 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1757 break; 1758 case CMD_FLAGS_TYPE_FRAG: 1759 /* fragment descriptor */ 1760 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1761 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1762 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1763 break; 1764 default: 1765 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1766 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1767 cmd->cmd_flags, cmd->cmd_numdesc, letoh16(cmd->cmd_id), 1768 letoh16(cmd->cmd_seq), letoh16(cmd->cmd_par1), 1769 letoh32(cmd->cmd_par2), letoh32(cmd->cmd_par3)); 1770 break; 1771 } 1772 } 1773 1774 void 1775 txp_set_filter(struct txp_softc *sc) 1776 { 1777 struct arpcom *ac = &sc->sc_arpcom; 1778 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1779 u_int32_t hashbit, hash[2]; 1780 u_int16_t filter; 1781 int mcnt = 0; 1782 struct ether_multi *enm; 1783 struct ether_multistep step; 1784 1785 if (ifp->if_flags & IFF_PROMISC) { 1786 filter = TXP_RXFILT_PROMISC; 1787 goto setit; 1788 } 1789 1790 if (ac->ac_multirangecnt > 0) 1791 ifp->if_flags |= IFF_ALLMULTI; 1792 1793 filter = TXP_RXFILT_DIRECT; 1794 1795 if (ifp->if_flags & IFF_BROADCAST) 1796 filter |= TXP_RXFILT_BROADCAST; 1797 1798 if (ifp->if_flags & IFF_ALLMULTI) 1799 filter |= TXP_RXFILT_ALLMULTI; 1800 else { 1801 hash[0] = hash[1] = 0; 1802 1803 ETHER_FIRST_MULTI(step, ac, enm); 1804 while (enm != NULL) { 1805 mcnt++; 1806 hashbit = (u_int16_t)(ether_crc32_be(enm->enm_addrlo, 1807 ETHER_ADDR_LEN) & (64 - 1)); 1808 hash[hashbit / 32] |= (1 << hashbit % 32); 1809 ETHER_NEXT_MULTI(step, enm); 1810 } 1811 1812 if (mcnt > 0) { 1813 filter |= TXP_RXFILT_HASHMULTI; 1814 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1815 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1816 } 1817 } 1818 1819 setit: 1820 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1821 NULL, NULL, NULL, 1); 1822 } 1823 1824 void 1825 txp_capabilities(struct txp_softc *sc) 1826 { 1827 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1828 struct txp_rsp_desc *rsp = NULL; 1829 struct txp_ext_desc *ext; 1830 1831 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1832 goto out; 1833 1834 if (rsp->rsp_numdesc != 1) 1835 goto out; 1836 ext = (struct txp_ext_desc *)(rsp + 1); 1837 1838 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1839 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1840 1841 ifp->if_capabilities = IFCAP_VLAN_MTU; 1842 1843 #if NVLAN > 0 1844 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1845 sc->sc_tx_capability |= OFFLOAD_VLAN; 1846 sc->sc_rx_capability |= OFFLOAD_VLAN; 1847 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1848 } 1849 #endif 1850 1851 #if 0 1852 /* not ready yet */ 1853 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1854 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1855 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1856 ifp->if_capabilities |= IFCAP_IPSEC; 1857 } 1858 #endif 1859 1860 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1861 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1862 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1863 ifp->if_capabilities |= IFCAP_CSUM_IPv4; 1864 } 1865 1866 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1867 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1868 #ifdef TRY_TX_TCP_CSUM 1869 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1870 ifp->if_capabilities |= IFCAP_CSUM_TCPv4; 1871 #endif 1872 } 1873 1874 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1875 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1876 #ifdef TRY_TX_UDP_CSUM 1877 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1878 ifp->if_capabilities |= IFCAP_CSUM_UDPv4; 1879 #endif 1880 } 1881 1882 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1883 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1884 goto out; 1885 1886 out: 1887 if (rsp != NULL) 1888 free(rsp, M_DEVBUF, 0); 1889 } 1890