1 /* $OpenBSD: if_tl.c,v 1.69 2016/04/13 10:34:32 mpi Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_tl.c,v 1.64 2001/02/06 10:11:48 phk Exp $ 35 */ 36 37 /* 38 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 39 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 40 * the National Semiconductor DP83840A physical interface and the 41 * Microchip Technology 24Cxx series serial EEPROM. 42 * 43 * Written using the following four documents: 44 * 45 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 46 * National Semiconductor DP83840A data sheet (www.national.com) 47 * Microchip Technology 24C02C data sheet (www.microchip.com) 48 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 49 * 50 * Written by Bill Paul <wpaul@ctr.columbia.edu> 51 * Electrical Engineering Department 52 * Columbia University, New York City 53 */ 54 55 /* 56 * Some notes about the ThunderLAN: 57 * 58 * The ThunderLAN controller is a single chip containing PCI controller 59 * logic, approximately 3K of on-board SRAM, a LAN controller, and media 60 * independent interface (MII) bus. The MII allows the ThunderLAN chip to 61 * control up to 32 different physical interfaces (PHYs). The ThunderLAN 62 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 63 * to act as a complete ethernet interface. 64 * 65 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 66 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 67 * in full or half duplex. Some of the Compaq Deskpro machines use a 68 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 69 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 70 * concert with the ThunderLAN's internal PHY to provide full 10/100 71 * support. This is cheaper than using a standalone external PHY for both 72 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 73 * A serial EEPROM is also attached to the ThunderLAN chip to provide 74 * power-up default register settings and for storing the adapter's 75 * station address. Although not supported by this driver, the ThunderLAN 76 * chip can also be connected to token ring PHYs. 77 * 78 * The ThunderLAN has a set of registers which can be used to issue 79 * commands, acknowledge interrupts, and to manipulate other internal 80 * registers on its DIO bus. The primary registers can be accessed 81 * using either programmed I/O (inb/outb) or via PCI memory mapping, 82 * depending on how the card is configured during the PCI probing 83 * phase. It is even possible to have both PIO and memory mapped 84 * access turned on at the same time. 85 * 86 * Frame reception and transmission with the ThunderLAN chip is done 87 * using frame 'lists.' A list structure looks more or less like this: 88 * 89 * struct tl_frag { 90 * u_int32_t fragment_address; 91 * u_int32_t fragment_size; 92 * }; 93 * struct tl_list { 94 * u_int32_t forward_pointer; 95 * u_int16_t cstat; 96 * u_int16_t frame_size; 97 * struct tl_frag fragments[10]; 98 * }; 99 * 100 * The forward pointer in the list header can be either a 0 or the address 101 * of another list, which allows several lists to be linked together. Each 102 * list contains up to 10 fragment descriptors. This means the chip allows 103 * ethernet frames to be broken up into up to 10 chunks for transfer to 104 * and from the SRAM. Note that the forward pointer and fragment buffer 105 * addresses are physical memory addresses, not virtual. Note also that 106 * a single ethernet frame can not span lists: if the host wants to 107 * transmit a frame and the frame data is split up over more than 10 108 * buffers, the frame has to collapsed before it can be transmitted. 109 * 110 * To receive frames, the driver sets up a number of lists and populates 111 * the fragment descriptors, then it sends an RX GO command to the chip. 112 * When a frame is received, the chip will DMA it into the memory regions 113 * specified by the fragment descriptors and then trigger an RX 'end of 114 * frame interrupt' when done. The driver may choose to use only one 115 * fragment per list; this may result is slighltly less efficient use 116 * of memory in exchange for improving performance. 117 * 118 * To transmit frames, the driver again sets up lists and fragment 119 * descriptors, only this time the buffers contain frame data that 120 * is to be DMA'ed into the chip instead of out of it. Once the chip 121 * has transferred the data into its on-board SRAM, it will trigger a 122 * TX 'end of frame' interrupt. It will also generate an 'end of channel' 123 * interrupt when it reaches the end of the list. 124 */ 125 126 /* 127 * Some notes about this driver: 128 * 129 * The ThunderLAN chip provides a couple of different ways to organize 130 * reception, transmission and interrupt handling. The simplest approach 131 * is to use one list each for transmission and reception. In this mode, 132 * the ThunderLAN will generate two interrupts for every received frame 133 * (one RX EOF and one RX EOC) and two for each transmitted frame (one 134 * TX EOF and one TX EOC). This may make the driver simpler but it hurts 135 * performance to have to handle so many interrupts. 136 * 137 * Initially I wanted to create a circular list of receive buffers so 138 * that the ThunderLAN chip would think there was an infinitely long 139 * receive channel and never deliver an RXEOC interrupt. However this 140 * doesn't work correctly under heavy load: while the manual says the 141 * chip will trigger an RXEOF interrupt each time a frame is copied into 142 * memory, you can't count on the chip waiting around for you to acknowledge 143 * the interrupt before it starts trying to DMA the next frame. The result 144 * is that the chip might traverse the entire circular list and then wrap 145 * around before you have a chance to do anything about it. Consequently, 146 * the receive list is terminated (with a 0 in the forward pointer in the 147 * last element). Each time an RXEOF interrupt arrives, the used list 148 * is shifted to the end of the list. This gives the appearance of an 149 * infinitely large RX chain so long as the driver doesn't fall behind 150 * the chip and allow all of the lists to be filled up. 151 * 152 * If all the lists are filled, the adapter will deliver an RX 'end of 153 * channel' interrupt when it hits the 0 forward pointer at the end of 154 * the chain. The RXEOC handler then cleans out the RX chain and resets 155 * the list head pointer in the ch_parm register and restarts the receiver. 156 * 157 * For frame transmission, it is possible to program the ThunderLAN's 158 * transmit interrupt threshold so that the chip can acknowledge multiple 159 * lists with only a single TX EOF interrupt. This allows the driver to 160 * queue several frames in one shot, and only have to handle a total 161 * two interrupts (one TX EOF and one TX EOC) no matter how many frames 162 * are transmitted. Frame transmission is done directly out of the 163 * mbufs passed to the tl_start() routine via the interface send queue. 164 * The driver simply sets up the fragment descriptors in the transmit 165 * lists to point to the mbuf data regions and sends a TX GO command. 166 * 167 * Note that since the RX and TX lists themselves are always used 168 * only by the driver, the are malloc()ed once at driver initialization 169 * time and never free()ed. 170 * 171 * Also, in order to remain as platform independent as possible, this 172 * driver uses memory mapped register access to manipulate the card 173 * as opposed to programmed I/O. This avoids the use of the inb/outb 174 * (and related) instructions which are specific to the i386 platform. 175 * 176 * Using these techniques, this driver achieves very high performance 177 * by minimizing the amount of interrupts generated during large 178 * transfers and by completely avoiding buffer copies. Frame transfer 179 * to and from the ThunderLAN chip is performed entirely by the chip 180 * itself thereby reducing the load on the host CPU. 181 */ 182 183 #include "bpfilter.h" 184 185 #include <sys/param.h> 186 #include <sys/systm.h> 187 #include <sys/sockio.h> 188 #include <sys/mbuf.h> 189 #include <sys/malloc.h> 190 #include <sys/kernel.h> 191 #include <sys/socket.h> 192 #include <sys/device.h> 193 #include <sys/timeout.h> 194 195 #include <net/if.h> 196 197 #include <netinet/in.h> 198 #include <netinet/if_ether.h> 199 200 #include <net/if_media.h> 201 202 #if NBPFILTER > 0 203 #include <net/bpf.h> 204 #endif 205 206 #include <uvm/uvm_extern.h> /* for vtophys */ 207 #define VTOPHYS(v) vtophys((vaddr_t)(v)) 208 209 #include <dev/mii/mii.h> 210 #include <dev/mii/miivar.h> 211 212 #include <dev/pci/pcireg.h> 213 #include <dev/pci/pcivar.h> 214 #include <dev/pci/pcidevs.h> 215 216 /* 217 * Default to using PIO register access mode to pacify certain 218 * laptop docking stations with built-in ThunderLAN chips that 219 * don't seem to handle memory mapped mode properly. 220 */ 221 #define TL_USEIOSPACE 222 223 #include <dev/pci/if_tlreg.h> 224 #include <dev/mii/tlphyvar.h> 225 226 const struct tl_products tl_prods[] = { 227 { PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T }, 228 { PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5 }, 229 { PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2 }, 230 { PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T }, 231 { PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T }, 232 { PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T }, 233 { PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2 }, 234 { PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5 }, 235 { PCI_VENDOR_TI, PCI_PRODUCT_TI_TLAN, 0 }, 236 { 0, 0, 0 } 237 }; 238 239 int tl_probe(struct device *, void *, void *); 240 void tl_attach(struct device *, struct device *, void *); 241 void tl_wait_up(void *); 242 int tl_intvec_rxeoc(void *, u_int32_t); 243 int tl_intvec_txeoc(void *, u_int32_t); 244 int tl_intvec_txeof(void *, u_int32_t); 245 int tl_intvec_rxeof(void *, u_int32_t); 246 int tl_intvec_adchk(void *, u_int32_t); 247 int tl_intvec_netsts(void *, u_int32_t); 248 249 int tl_newbuf(struct tl_softc *, struct tl_chain_onefrag *); 250 void tl_stats_update(void *); 251 int tl_encap(struct tl_softc *, struct tl_chain *, struct mbuf *); 252 253 int tl_intr(void *); 254 void tl_start(struct ifnet *); 255 int tl_ioctl(struct ifnet *, u_long, caddr_t); 256 void tl_init(void *); 257 void tl_stop(struct tl_softc *); 258 void tl_watchdog(struct ifnet *); 259 int tl_ifmedia_upd(struct ifnet *); 260 void tl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 261 262 u_int8_t tl_eeprom_putbyte(struct tl_softc *, int); 263 u_int8_t tl_eeprom_getbyte(struct tl_softc *, int, u_int8_t *); 264 int tl_read_eeprom(struct tl_softc *, caddr_t, int, int); 265 266 void tl_mii_sync(struct tl_softc *); 267 void tl_mii_send(struct tl_softc *, u_int32_t, int); 268 int tl_mii_readreg(struct tl_softc *, struct tl_mii_frame *); 269 int tl_mii_writereg(struct tl_softc *, struct tl_mii_frame *); 270 int tl_miibus_readreg(struct device *, int, int); 271 void tl_miibus_writereg(struct device *, int, int, int); 272 void tl_miibus_statchg(struct device *); 273 274 void tl_setmode(struct tl_softc *, uint64_t); 275 int tl_calchash(caddr_t); 276 void tl_iff(struct tl_softc *); 277 void tl_setfilt(struct tl_softc *, caddr_t, int); 278 void tl_softreset(struct tl_softc *, int); 279 void tl_hardreset(struct device *); 280 int tl_list_rx_init(struct tl_softc *); 281 int tl_list_tx_init(struct tl_softc *); 282 283 u_int8_t tl_dio_read8(struct tl_softc *, int); 284 u_int16_t tl_dio_read16(struct tl_softc *, int); 285 u_int32_t tl_dio_read32(struct tl_softc *, int); 286 void tl_dio_write8(struct tl_softc *, int, int); 287 void tl_dio_write16(struct tl_softc *, int, int); 288 void tl_dio_write32(struct tl_softc *, int, int); 289 void tl_dio_setbit(struct tl_softc *, int, int); 290 void tl_dio_clrbit(struct tl_softc *, int, int); 291 void tl_dio_setbit16(struct tl_softc *, int, int); 292 void tl_dio_clrbit16(struct tl_softc *, int, int); 293 294 u_int8_t 295 tl_dio_read8(struct tl_softc *sc, int reg) 296 { 297 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 298 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 299 } 300 301 u_int16_t 302 tl_dio_read16(struct tl_softc *sc, int reg) 303 { 304 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 305 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 306 } 307 308 u_int32_t 309 tl_dio_read32(struct tl_softc *sc, int reg) 310 { 311 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 312 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 313 } 314 315 void 316 tl_dio_write8(struct tl_softc *sc, int reg, int val) 317 { 318 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 319 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 320 } 321 322 void 323 tl_dio_write16(struct tl_softc *sc, int reg, int val) 324 { 325 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 326 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 327 } 328 329 void 330 tl_dio_write32(struct tl_softc *sc, int reg, int val) 331 { 332 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 333 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 334 } 335 336 void 337 tl_dio_setbit(struct tl_softc *sc, int reg, int bit) 338 { 339 u_int8_t f; 340 341 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 342 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 343 f |= bit; 344 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 345 } 346 347 void 348 tl_dio_clrbit(struct tl_softc *sc, int reg, int bit) 349 { 350 u_int8_t f; 351 352 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 353 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 354 f &= ~bit; 355 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 356 } 357 358 void 359 tl_dio_setbit16(struct tl_softc *sc, int reg, int bit) 360 { 361 u_int16_t f; 362 363 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 364 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 365 f |= bit; 366 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 367 } 368 369 void 370 tl_dio_clrbit16(struct tl_softc *sc, int reg, int bit) 371 { 372 u_int16_t f; 373 374 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 375 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 376 f &= ~bit; 377 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 378 } 379 380 /* 381 * Send an instruction or address to the EEPROM, check for ACK. 382 */ 383 u_int8_t 384 tl_eeprom_putbyte(struct tl_softc *sc, int byte) 385 { 386 int i, ack = 0; 387 388 /* 389 * Make sure we're in TX mode. 390 */ 391 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 392 393 /* 394 * Feed in each bit and strobe the clock. 395 */ 396 for (i = 0x80; i; i >>= 1) { 397 if (byte & i) 398 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 399 else 400 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 401 DELAY(1); 402 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 403 DELAY(1); 404 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 405 } 406 407 /* 408 * Turn off TX mode. 409 */ 410 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 411 412 /* 413 * Check for ack. 414 */ 415 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 416 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 417 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 418 419 return(ack); 420 } 421 422 /* 423 * Read a byte of data stored in the EEPROM at address 'addr.' 424 */ 425 u_int8_t 426 tl_eeprom_getbyte(struct tl_softc *sc, int addr, u_int8_t *dest) 427 { 428 int i; 429 u_int8_t byte = 0; 430 431 tl_dio_write8(sc, TL_NETSIO, 0); 432 433 EEPROM_START; 434 435 /* 436 * Send write control code to EEPROM. 437 */ 438 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 439 printf("%s: failed to send write command, status: %x\n", 440 sc->sc_dev.dv_xname, tl_dio_read8(sc, TL_NETSIO)); 441 return(1); 442 } 443 444 /* 445 * Send address of byte we want to read. 446 */ 447 if (tl_eeprom_putbyte(sc, addr)) { 448 printf("%s: failed to send address, status: %x\n", 449 sc->sc_dev.dv_xname, tl_dio_read8(sc, TL_NETSIO)); 450 return(1); 451 } 452 453 EEPROM_STOP; 454 EEPROM_START; 455 /* 456 * Send read control code to EEPROM. 457 */ 458 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 459 printf("%s: failed to send write command, status: %x\n", 460 sc->sc_dev.dv_xname, tl_dio_read8(sc, TL_NETSIO)); 461 return(1); 462 } 463 464 /* 465 * Start reading bits from EEPROM. 466 */ 467 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 468 for (i = 0x80; i; i >>= 1) { 469 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 470 DELAY(1); 471 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 472 byte |= i; 473 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 474 DELAY(1); 475 } 476 477 EEPROM_STOP; 478 479 /* 480 * No ACK generated for read, so just return byte. 481 */ 482 483 *dest = byte; 484 485 return(0); 486 } 487 488 /* 489 * Read a sequence of bytes from the EEPROM. 490 */ 491 int 492 tl_read_eeprom(struct tl_softc *sc, caddr_t dest, int off, int cnt) 493 { 494 int err = 0, i; 495 u_int8_t byte = 0; 496 497 for (i = 0; i < cnt; i++) { 498 err = tl_eeprom_getbyte(sc, off + i, &byte); 499 if (err) 500 break; 501 *(dest + i) = byte; 502 } 503 504 return(err ? 1 : 0); 505 } 506 507 void 508 tl_mii_sync(struct tl_softc *sc) 509 { 510 int i; 511 512 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 513 514 for (i = 0; i < 32; i++) { 515 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 516 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 517 } 518 } 519 520 void 521 tl_mii_send(struct tl_softc *sc, u_int32_t bits, int cnt) 522 { 523 int i; 524 525 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 526 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 527 if (bits & i) 528 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 529 else 530 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 531 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 532 } 533 } 534 535 int 536 tl_mii_readreg(struct tl_softc *sc, struct tl_mii_frame *frame) 537 { 538 int i, ack, s; 539 int minten = 0; 540 541 s = splnet(); 542 543 tl_mii_sync(sc); 544 545 /* 546 * Set up frame for RX. 547 */ 548 frame->mii_stdelim = TL_MII_STARTDELIM; 549 frame->mii_opcode = TL_MII_READOP; 550 frame->mii_turnaround = 0; 551 frame->mii_data = 0; 552 553 /* 554 * Turn off MII interrupt by forcing MINTEN low. 555 */ 556 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 557 if (minten) 558 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 559 560 /* 561 * Turn on data xmit. 562 */ 563 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 564 565 /* 566 * Send command/address info. 567 */ 568 tl_mii_send(sc, frame->mii_stdelim, 2); 569 tl_mii_send(sc, frame->mii_opcode, 2); 570 tl_mii_send(sc, frame->mii_phyaddr, 5); 571 tl_mii_send(sc, frame->mii_regaddr, 5); 572 573 /* 574 * Turn off xmit. 575 */ 576 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 577 578 /* Idle bit */ 579 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 580 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 581 582 /* Check for ack */ 583 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 584 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 585 586 /* Complete the cycle */ 587 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 588 589 /* 590 * Now try reading data bits. If the ack failed, we still 591 * need to clock through 16 cycles to keep the PHYs in sync. 592 */ 593 if (ack) { 594 for(i = 0; i < 16; i++) { 595 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 596 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 597 } 598 goto fail; 599 } 600 601 for (i = 0x8000; i; i >>= 1) { 602 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 603 if (!ack) { 604 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 605 frame->mii_data |= i; 606 } 607 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 608 } 609 610 fail: 611 612 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 613 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 614 615 /* Reenable interrupts */ 616 if (minten) 617 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 618 619 splx(s); 620 621 if (ack) 622 return(1); 623 return(0); 624 } 625 626 int 627 tl_mii_writereg(struct tl_softc *sc, struct tl_mii_frame *frame) 628 { 629 int s; 630 int minten; 631 632 tl_mii_sync(sc); 633 634 s = splnet(); 635 /* 636 * Set up frame for TX. 637 */ 638 639 frame->mii_stdelim = TL_MII_STARTDELIM; 640 frame->mii_opcode = TL_MII_WRITEOP; 641 frame->mii_turnaround = TL_MII_TURNAROUND; 642 643 /* 644 * Turn off MII interrupt by forcing MINTEN low. 645 */ 646 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 647 if (minten) 648 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 649 650 /* 651 * Turn on data output. 652 */ 653 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 654 655 tl_mii_send(sc, frame->mii_stdelim, 2); 656 tl_mii_send(sc, frame->mii_opcode, 2); 657 tl_mii_send(sc, frame->mii_phyaddr, 5); 658 tl_mii_send(sc, frame->mii_regaddr, 5); 659 tl_mii_send(sc, frame->mii_turnaround, 2); 660 tl_mii_send(sc, frame->mii_data, 16); 661 662 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 663 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 664 665 /* 666 * Turn off xmit. 667 */ 668 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 669 670 /* Reenable interrupts */ 671 if (minten) 672 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 673 674 splx(s); 675 676 return(0); 677 } 678 679 int 680 tl_miibus_readreg(struct device *dev, int phy, int reg) 681 { 682 struct tl_softc *sc = (struct tl_softc *)dev; 683 struct tl_mii_frame frame; 684 685 bzero(&frame, sizeof(frame)); 686 687 frame.mii_phyaddr = phy; 688 frame.mii_regaddr = reg; 689 tl_mii_readreg(sc, &frame); 690 691 return(frame.mii_data); 692 } 693 694 void 695 tl_miibus_writereg(struct device *dev, int phy, int reg, int data) 696 { 697 struct tl_softc *sc = (struct tl_softc *)dev; 698 struct tl_mii_frame frame; 699 700 bzero(&frame, sizeof(frame)); 701 702 frame.mii_phyaddr = phy; 703 frame.mii_regaddr = reg; 704 frame.mii_data = data; 705 706 tl_mii_writereg(sc, &frame); 707 } 708 709 void 710 tl_miibus_statchg(struct device *dev) 711 { 712 struct tl_softc *sc = (struct tl_softc *)dev; 713 714 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) 715 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 716 else 717 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 718 } 719 720 /* 721 * Set modes for bitrate devices. 722 */ 723 void 724 tl_setmode(struct tl_softc *sc, uint64_t media) 725 { 726 if (IFM_SUBTYPE(media) == IFM_10_5) 727 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 728 if (IFM_SUBTYPE(media) == IFM_10_T) { 729 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 730 if ((media & IFM_GMASK) == IFM_FDX) { 731 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 732 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 733 } else { 734 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 735 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 736 } 737 } 738 } 739 740 /* 741 * Calculate the hash of a MAC address for programming the multicast hash 742 * table. This hash is simply the address split into 6-bit chunks 743 * XOR'd, e.g. 744 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 745 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 746 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 747 * the folded 24-bit value is split into 6-bit portions and XOR'd. 748 */ 749 int 750 tl_calchash(caddr_t addr) 751 { 752 int t; 753 754 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 755 (addr[2] ^ addr[5]); 756 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 757 } 758 759 /* 760 * The ThunderLAN has a perfect MAC address filter in addition to 761 * the multicast hash filter. The perfect filter can be programmed 762 * with up to four MAC addresses. The first one is always used to 763 * hold the station address, which leaves us free to use the other 764 * three for multicast addresses. 765 */ 766 void 767 tl_setfilt(struct tl_softc *sc, caddr_t addr, int slot) 768 { 769 int i; 770 u_int16_t regaddr; 771 772 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 773 774 for (i = 0; i < ETHER_ADDR_LEN; i++) 775 tl_dio_write8(sc, regaddr + i, *(addr + i)); 776 } 777 778 /* 779 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 780 * linked list. This is fine, except addresses are added from the head 781 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 782 * group to always be in the perfect filter, but as more groups are added, 783 * the 224.0.0.1 entry (which is always added first) gets pushed down 784 * the list and ends up at the tail. So after 3 or 4 multicast groups 785 * are added, the all-hosts entry gets pushed out of the perfect filter 786 * and into the hash table. 787 * 788 * Because the multicast list is a doubly-linked list as opposed to a 789 * circular queue, we don't have the ability to just grab the tail of 790 * the list and traverse it backwards. Instead, we have to traverse 791 * the list once to find the tail, then traverse it again backwards to 792 * update the multicast filter. 793 */ 794 void 795 tl_iff(struct tl_softc *sc) 796 { 797 struct ifnet *ifp = &sc->arpcom.ac_if; 798 struct arpcom *ac = &sc->arpcom; 799 struct ether_multistep step; 800 struct ether_multi *enm; 801 u_int32_t hashes[2]; 802 int h = 0; 803 804 tl_dio_clrbit(sc, TL_NETCMD, (TL_CMD_CAF | TL_CMD_NOBRX)); 805 bzero(hashes, sizeof(hashes)); 806 ifp->if_flags &= ~IFF_ALLMULTI; 807 808 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 809 ifp->if_flags |= IFF_ALLMULTI; 810 if (ifp->if_flags & IFF_PROMISC) 811 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 812 else 813 hashes[0] = hashes[1] = 0xffffffff; 814 } else { 815 ETHER_FIRST_MULTI(step, ac, enm); 816 while (enm != NULL) { 817 h = tl_calchash(enm->enm_addrlo); 818 819 if (h < 32) 820 hashes[0] |= (1 << h); 821 else 822 hashes[1] |= (1 << (h - 32)); 823 824 ETHER_NEXT_MULTI(step, enm); 825 } 826 } 827 828 tl_dio_write32(sc, TL_HASH1, hashes[0]); 829 tl_dio_write32(sc, TL_HASH2, hashes[1]); 830 } 831 832 /* 833 * This routine is recommended by the ThunderLAN manual to insure that 834 * the internal PHY is powered up correctly. It also recommends a one 835 * second pause at the end to 'wait for the clocks to start' but in my 836 * experience this isn't necessary. 837 */ 838 void 839 tl_hardreset(struct device *dev) 840 { 841 struct tl_softc *sc = (struct tl_softc *)dev; 842 int i; 843 u_int16_t flags; 844 845 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 846 847 for (i =0 ; i < MII_NPHY; i++) 848 tl_miibus_writereg(dev, i, MII_BMCR, flags); 849 850 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 851 tl_mii_sync(sc); 852 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 853 854 DELAY(5000); 855 } 856 857 void 858 tl_softreset(struct tl_softc *sc, int internal) 859 { 860 u_int32_t cmd, dummy, i; 861 862 /* Assert the adapter reset bit. */ 863 CMD_SET(sc, TL_CMD_ADRST); 864 /* Turn off interrupts */ 865 CMD_SET(sc, TL_CMD_INTSOFF); 866 867 /* First, clear the stats registers. */ 868 for (i = 0; i < 5; i++) 869 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 870 871 /* Clear Areg and Hash registers */ 872 for (i = 0; i < 8; i++) 873 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 874 875 /* 876 * Set up Netconfig register. Enable one channel and 877 * one fragment mode. 878 */ 879 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 880 if (internal && !sc->tl_bitrate) { 881 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 882 } else { 883 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 884 } 885 886 /* Handle cards with bitrate devices. */ 887 if (sc->tl_bitrate) 888 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 889 890 /* 891 * Load adapter irq pacing timer and tx threshold. 892 * We make the transmit threshold 1 initially but we may 893 * change that later. 894 */ 895 cmd = CSR_READ_4(sc, TL_HOSTCMD); 896 cmd |= TL_CMD_NES; 897 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 898 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 899 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 900 901 /* Unreset the MII */ 902 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 903 904 /* Take the adapter out of reset */ 905 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 906 907 /* Wait for things to settle down a little. */ 908 DELAY(500); 909 } 910 911 /* 912 * Initialize the transmit lists. 913 */ 914 int 915 tl_list_tx_init(struct tl_softc *sc) 916 { 917 struct tl_chain_data *cd; 918 struct tl_list_data *ld; 919 int i; 920 921 cd = &sc->tl_cdata; 922 ld = sc->tl_ldata; 923 for (i = 0; i < TL_TX_LIST_CNT; i++) { 924 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 925 if (i == (TL_TX_LIST_CNT - 1)) 926 cd->tl_tx_chain[i].tl_next = NULL; 927 else 928 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 929 } 930 931 cd->tl_tx_free = &cd->tl_tx_chain[0]; 932 cd->tl_tx_tail = cd->tl_tx_head = NULL; 933 sc->tl_txeoc = 1; 934 935 return(0); 936 } 937 938 /* 939 * Initialize the RX lists and allocate mbufs for them. 940 */ 941 int 942 tl_list_rx_init(struct tl_softc *sc) 943 { 944 struct tl_chain_data *cd; 945 struct tl_list_data *ld; 946 int i; 947 948 cd = &sc->tl_cdata; 949 ld = sc->tl_ldata; 950 951 for (i = 0; i < TL_RX_LIST_CNT; i++) { 952 cd->tl_rx_chain[i].tl_ptr = 953 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 954 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 955 return(ENOBUFS); 956 if (i == (TL_RX_LIST_CNT - 1)) { 957 cd->tl_rx_chain[i].tl_next = NULL; 958 ld->tl_rx_list[i].tlist_fptr = 0; 959 } else { 960 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 961 ld->tl_rx_list[i].tlist_fptr = 962 VTOPHYS(&ld->tl_rx_list[i + 1]); 963 } 964 } 965 966 cd->tl_rx_head = &cd->tl_rx_chain[0]; 967 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 968 969 return(0); 970 } 971 972 int 973 tl_newbuf(struct tl_softc *sc, struct tl_chain_onefrag *c) 974 { 975 struct mbuf *m_new = NULL; 976 977 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 978 if (m_new == NULL) { 979 return(ENOBUFS); 980 } 981 982 MCLGET(m_new, M_DONTWAIT); 983 if (!(m_new->m_flags & M_EXT)) { 984 m_freem(m_new); 985 return(ENOBUFS); 986 } 987 988 #ifdef __alpha__ 989 m_new->m_data += 2; 990 #endif 991 992 c->tl_mbuf = m_new; 993 c->tl_next = NULL; 994 c->tl_ptr->tlist_frsize = MCLBYTES; 995 c->tl_ptr->tlist_fptr = 0; 996 c->tl_ptr->tl_frag.tlist_dadr = VTOPHYS(mtod(m_new, caddr_t)); 997 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 998 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 999 1000 return(0); 1001 } 1002 /* 1003 * Interrupt handler for RX 'end of frame' condition (EOF). This 1004 * tells us that a full ethernet frame has been captured and we need 1005 * to handle it. 1006 * 1007 * Reception is done using 'lists' which consist of a header and a 1008 * series of 10 data count/data address pairs that point to buffers. 1009 * Initially you're supposed to create a list, populate it with pointers 1010 * to buffers, then load the physical address of the list into the 1011 * ch_parm register. The adapter is then supposed to DMA the received 1012 * frame into the buffers for you. 1013 * 1014 * To make things as fast as possible, we have the chip DMA directly 1015 * into mbufs. This saves us from having to do a buffer copy: we can 1016 * just hand the mbufs directly to the network stack. Once the frame 1017 * has been sent on its way, the 'list' structure is assigned a new 1018 * buffer and moved to the end of the RX chain. As long we we stay 1019 * ahead of the chip, it will always think it has an endless receive 1020 * channel. 1021 * 1022 * If we happen to fall behind and the chip manages to fill up all of 1023 * the buffers, it will generate an end of channel interrupt and wait 1024 * for us to empty the chain and restart the receiver. 1025 */ 1026 int 1027 tl_intvec_rxeof(void *xsc, u_int32_t type) 1028 { 1029 struct tl_softc *sc; 1030 int r = 0, total_len = 0; 1031 struct ether_header *eh; 1032 struct mbuf *m; 1033 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1034 struct ifnet *ifp; 1035 struct tl_chain_onefrag *cur_rx; 1036 1037 sc = xsc; 1038 ifp = &sc->arpcom.ac_if; 1039 1040 while(sc->tl_cdata.tl_rx_head != NULL) { 1041 cur_rx = sc->tl_cdata.tl_rx_head; 1042 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1043 break; 1044 r++; 1045 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1046 m = cur_rx->tl_mbuf; 1047 total_len = cur_rx->tl_ptr->tlist_frsize; 1048 1049 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1050 ifp->if_ierrors++; 1051 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1052 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1053 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1054 continue; 1055 } 1056 1057 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1058 VTOPHYS(cur_rx->tl_ptr); 1059 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1060 sc->tl_cdata.tl_rx_tail = cur_rx; 1061 1062 eh = mtod(m, struct ether_header *); 1063 1064 /* 1065 * Note: when the ThunderLAN chip is in 'capture all 1066 * frames' mode, it will receive its own transmissions. 1067 * We drop don't need to process our own transmissions, 1068 * so we drop them here and continue. 1069 */ 1070 /*if (ifp->if_flags & IFF_PROMISC && */ 1071 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 1072 ETHER_ADDR_LEN)) { 1073 m_freem(m); 1074 continue; 1075 } 1076 1077 m->m_pkthdr.len = m->m_len = total_len; 1078 ml_enqueue(&ml, m); 1079 } 1080 1081 if_input(ifp, &ml); 1082 1083 return(r); 1084 } 1085 1086 /* 1087 * The RX-EOC condition hits when the ch_parm address hasn't been 1088 * initialized or the adapter reached a list with a forward pointer 1089 * of 0 (which indicates the end of the chain). In our case, this means 1090 * the card has hit the end of the receive buffer chain and we need to 1091 * empty out the buffers and shift the pointer back to the beginning again. 1092 */ 1093 int 1094 tl_intvec_rxeoc(void *xsc, u_int32_t type) 1095 { 1096 struct tl_softc *sc; 1097 int r; 1098 struct tl_chain_data *cd; 1099 1100 sc = xsc; 1101 cd = &sc->tl_cdata; 1102 1103 /* Flush out the receive queue and ack RXEOF interrupts. */ 1104 r = tl_intvec_rxeof(xsc, type); 1105 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 1106 r = 1; 1107 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1108 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1109 CSR_WRITE_4(sc, TL_CH_PARM, VTOPHYS(sc->tl_cdata.tl_rx_head->tl_ptr)); 1110 r |= (TL_CMD_GO|TL_CMD_RT); 1111 return(r); 1112 } 1113 1114 int 1115 tl_intvec_txeof(void *xsc, u_int32_t type) 1116 { 1117 struct tl_softc *sc; 1118 int r = 0; 1119 struct tl_chain *cur_tx; 1120 1121 sc = xsc; 1122 1123 /* 1124 * Go through our tx list and free mbufs for those 1125 * frames that have been sent. 1126 */ 1127 while (sc->tl_cdata.tl_tx_head != NULL) { 1128 cur_tx = sc->tl_cdata.tl_tx_head; 1129 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1130 break; 1131 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 1132 1133 r++; 1134 m_freem(cur_tx->tl_mbuf); 1135 cur_tx->tl_mbuf = NULL; 1136 1137 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 1138 sc->tl_cdata.tl_tx_free = cur_tx; 1139 if (!cur_tx->tl_ptr->tlist_fptr) 1140 break; 1141 } 1142 1143 return(r); 1144 } 1145 1146 /* 1147 * The transmit end of channel interrupt. The adapter triggers this 1148 * interrupt to tell us it hit the end of the current transmit list. 1149 * 1150 * A note about this: it's possible for a condition to arise where 1151 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 1152 * You have to avoid this since the chip expects things to go in a 1153 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 1154 * When the TXEOF handler is called, it will free all of the transmitted 1155 * frames and reset the tx_head pointer to NULL. However, a TXEOC 1156 * interrupt should be received and acknowledged before any more frames 1157 * are queued for transmission. If tl_statrt() is called after TXEOF 1158 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 1159 * it could attempt to issue a transmit command prematurely. 1160 * 1161 * To guard against this, tl_start() will only issue transmit commands 1162 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 1163 * can set this flag once tl_start() has cleared it. 1164 */ 1165 int 1166 tl_intvec_txeoc(void *xsc, u_int32_t type) 1167 { 1168 struct tl_softc *sc; 1169 struct ifnet *ifp; 1170 u_int32_t cmd; 1171 1172 sc = xsc; 1173 ifp = &sc->arpcom.ac_if; 1174 1175 /* Clear the timeout timer. */ 1176 ifp->if_timer = 0; 1177 1178 if (sc->tl_cdata.tl_tx_head == NULL) { 1179 ifq_clr_oactive(&ifp->if_snd); 1180 sc->tl_cdata.tl_tx_tail = NULL; 1181 sc->tl_txeoc = 1; 1182 } else { 1183 sc->tl_txeoc = 0; 1184 /* First we have to ack the EOC interrupt. */ 1185 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 1186 /* Then load the address of the next TX list. */ 1187 CSR_WRITE_4(sc, TL_CH_PARM, 1188 VTOPHYS(sc->tl_cdata.tl_tx_head->tl_ptr)); 1189 /* Restart TX channel. */ 1190 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1191 cmd &= ~TL_CMD_RT; 1192 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1193 CMD_PUT(sc, cmd); 1194 return(0); 1195 } 1196 1197 return(1); 1198 } 1199 1200 int 1201 tl_intvec_adchk(void *xsc, u_int32_t type) 1202 { 1203 struct tl_softc *sc; 1204 1205 sc = xsc; 1206 1207 if (type) 1208 printf("%s: adapter check: %x\n", sc->sc_dev.dv_xname, 1209 (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 1210 1211 tl_softreset(sc, 1); 1212 tl_stop(sc); 1213 tl_init(sc); 1214 CMD_SET(sc, TL_CMD_INTSON); 1215 1216 return(0); 1217 } 1218 1219 int 1220 tl_intvec_netsts(void *xsc, u_int32_t type) 1221 { 1222 struct tl_softc *sc; 1223 u_int16_t netsts; 1224 1225 sc = xsc; 1226 1227 netsts = tl_dio_read16(sc, TL_NETSTS); 1228 tl_dio_write16(sc, TL_NETSTS, netsts); 1229 1230 printf("%s: network status: %x\n", sc->sc_dev.dv_xname, netsts); 1231 1232 return(1); 1233 } 1234 1235 int 1236 tl_intr(void *xsc) 1237 { 1238 struct tl_softc *sc; 1239 struct ifnet *ifp; 1240 int r = 0; 1241 u_int32_t type = 0; 1242 u_int16_t ints = 0; 1243 u_int8_t ivec = 0; 1244 1245 sc = xsc; 1246 1247 /* Disable interrupts */ 1248 ints = CSR_READ_2(sc, TL_HOST_INT); 1249 CSR_WRITE_2(sc, TL_HOST_INT, ints); 1250 type = (ints << 16) & 0xFFFF0000; 1251 ivec = (ints & TL_VEC_MASK) >> 5; 1252 ints = (ints & TL_INT_MASK) >> 2; 1253 1254 ifp = &sc->arpcom.ac_if; 1255 1256 switch(ints) { 1257 case (TL_INTR_INVALID): 1258 /* Re-enable interrupts but don't ack this one. */ 1259 CMD_PUT(sc, type); 1260 r = 0; 1261 break; 1262 case (TL_INTR_TXEOF): 1263 r = tl_intvec_txeof((void *)sc, type); 1264 break; 1265 case (TL_INTR_TXEOC): 1266 r = tl_intvec_txeoc((void *)sc, type); 1267 break; 1268 case (TL_INTR_STATOFLOW): 1269 tl_stats_update(sc); 1270 r = 1; 1271 break; 1272 case (TL_INTR_RXEOF): 1273 r = tl_intvec_rxeof((void *)sc, type); 1274 break; 1275 case (TL_INTR_DUMMY): 1276 printf("%s: got a dummy interrupt\n", sc->sc_dev.dv_xname); 1277 r = 1; 1278 break; 1279 case (TL_INTR_ADCHK): 1280 if (ivec) 1281 r = tl_intvec_adchk((void *)sc, type); 1282 else 1283 r = tl_intvec_netsts((void *)sc, type); 1284 break; 1285 case (TL_INTR_RXEOC): 1286 r = tl_intvec_rxeoc((void *)sc, type); 1287 break; 1288 default: 1289 printf("%s: bogus interrupt type\n", sc->sc_dev.dv_xname); 1290 break; 1291 } 1292 1293 /* Re-enable interrupts */ 1294 if (r) { 1295 CMD_PUT(sc, TL_CMD_ACK | r | type); 1296 } 1297 1298 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1299 tl_start(ifp); 1300 1301 return r; 1302 } 1303 1304 void 1305 tl_stats_update(void *xsc) 1306 { 1307 struct tl_softc *sc; 1308 struct ifnet *ifp; 1309 struct tl_stats tl_stats; 1310 u_int32_t *p; 1311 int s; 1312 1313 s = splnet(); 1314 1315 bzero(&tl_stats, sizeof(struct tl_stats)); 1316 1317 sc = xsc; 1318 ifp = &sc->arpcom.ac_if; 1319 1320 p = (u_int32_t *)&tl_stats; 1321 1322 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 1323 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1324 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1325 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1326 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1327 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1328 1329 ifp->if_opackets += tl_tx_goodframes(tl_stats); 1330 ifp->if_collisions += tl_stats.tl_tx_single_collision + 1331 tl_stats.tl_tx_multi_collision; 1332 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 1333 tl_rx_overrun(tl_stats); 1334 ifp->if_oerrors += tl_tx_underrun(tl_stats); 1335 1336 if (tl_tx_underrun(tl_stats)) { 1337 u_int8_t tx_thresh; 1338 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 1339 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 1340 tx_thresh >>= 4; 1341 tx_thresh++; 1342 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1343 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 1344 } 1345 } 1346 1347 timeout_add_sec(&sc->tl_stats_tmo, 1); 1348 1349 if (!sc->tl_bitrate) 1350 mii_tick(&sc->sc_mii); 1351 1352 splx(s); 1353 } 1354 1355 /* 1356 * Encapsulate an mbuf chain in a list by coupling the mbuf data 1357 * pointers to the fragment pointers. 1358 */ 1359 int 1360 tl_encap(struct tl_softc *sc, struct tl_chain *c, struct mbuf *m_head) 1361 { 1362 int frag = 0; 1363 struct tl_frag *f = NULL; 1364 int total_len; 1365 struct mbuf *m; 1366 1367 /* 1368 * Start packing the mbufs in this chain into 1369 * the fragment pointers. Stop when we run out 1370 * of fragments or hit the end of the mbuf chain. 1371 */ 1372 m = m_head; 1373 total_len = 0; 1374 1375 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1376 if (m->m_len != 0) { 1377 if (frag == TL_MAXFRAGS) 1378 break; 1379 total_len+= m->m_len; 1380 c->tl_ptr->tl_frag[frag].tlist_dadr = 1381 VTOPHYS(mtod(m, vaddr_t)); 1382 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 1383 frag++; 1384 } 1385 } 1386 1387 /* 1388 * Handle special cases. 1389 * Special case #1: we used up all 10 fragments, but 1390 * we have more mbufs left in the chain. Copy the 1391 * data into an mbuf cluster. Note that we don't 1392 * bother clearing the values in the other fragment 1393 * pointers/counters; it wouldn't gain us anything, 1394 * and would waste cycles. 1395 */ 1396 if (m != NULL) { 1397 struct mbuf *m_new = NULL; 1398 1399 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1400 if (m_new == NULL) 1401 return(1); 1402 if (m_head->m_pkthdr.len > MHLEN) { 1403 MCLGET(m_new, M_DONTWAIT); 1404 if (!(m_new->m_flags & M_EXT)) { 1405 m_freem(m_new); 1406 return(1); 1407 } 1408 } 1409 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1410 mtod(m_new, caddr_t)); 1411 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1412 m_freem(m_head); 1413 m_head = m_new; 1414 f = &c->tl_ptr->tl_frag[0]; 1415 f->tlist_dadr = VTOPHYS(mtod(m_new, caddr_t)); 1416 f->tlist_dcnt = total_len = m_new->m_len; 1417 frag = 1; 1418 } 1419 1420 /* 1421 * Special case #2: the frame is smaller than the minimum 1422 * frame size. We have to pad it to make the chip happy. 1423 */ 1424 if (total_len < TL_MIN_FRAMELEN) { 1425 f = &c->tl_ptr->tl_frag[frag]; 1426 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 1427 f->tlist_dadr = VTOPHYS(&sc->tl_ldata->tl_pad); 1428 total_len += f->tlist_dcnt; 1429 frag++; 1430 } 1431 1432 c->tl_mbuf = m_head; 1433 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 1434 c->tl_ptr->tlist_frsize = total_len; 1435 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1436 c->tl_ptr->tlist_fptr = 0; 1437 1438 return(0); 1439 } 1440 1441 /* 1442 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1443 * to the mbuf data regions directly in the transmit lists. We also save a 1444 * copy of the pointers since the transmit list fragment pointers are 1445 * physical addresses. 1446 */ 1447 void 1448 tl_start(struct ifnet *ifp) 1449 { 1450 struct tl_softc *sc; 1451 struct mbuf *m_head = NULL; 1452 u_int32_t cmd; 1453 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1454 1455 sc = ifp->if_softc; 1456 1457 /* 1458 * Check for an available queue slot. If there are none, 1459 * punt. 1460 */ 1461 if (sc->tl_cdata.tl_tx_free == NULL) { 1462 ifq_set_oactive(&ifp->if_snd); 1463 return; 1464 } 1465 1466 start_tx = sc->tl_cdata.tl_tx_free; 1467 1468 while(sc->tl_cdata.tl_tx_free != NULL) { 1469 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1470 if (m_head == NULL) 1471 break; 1472 1473 /* Pick a chain member off the free list. */ 1474 cur_tx = sc->tl_cdata.tl_tx_free; 1475 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 1476 1477 cur_tx->tl_next = NULL; 1478 1479 /* Pack the data into the list. */ 1480 tl_encap(sc, cur_tx, m_head); 1481 1482 /* Chain it together */ 1483 if (prev != NULL) { 1484 prev->tl_next = cur_tx; 1485 prev->tl_ptr->tlist_fptr = VTOPHYS(cur_tx->tl_ptr); 1486 } 1487 prev = cur_tx; 1488 1489 /* 1490 * If there's a BPF listener, bounce a copy of this frame 1491 * to him. 1492 */ 1493 #if NBPFILTER > 0 1494 if (ifp->if_bpf) 1495 bpf_mtap(ifp->if_bpf, cur_tx->tl_mbuf, 1496 BPF_DIRECTION_OUT); 1497 #endif 1498 } 1499 1500 /* 1501 * If there are no packets queued, bail. 1502 */ 1503 if (cur_tx == NULL) 1504 return; 1505 1506 /* 1507 * That's all we can stands, we can't stands no more. 1508 * If there are no other transfers pending, then issue the 1509 * TX GO command to the adapter to start things moving. 1510 * Otherwise, just leave the data in the queue and let 1511 * the EOF/EOC interrupt handler send. 1512 */ 1513 if (sc->tl_cdata.tl_tx_head == NULL) { 1514 sc->tl_cdata.tl_tx_head = start_tx; 1515 sc->tl_cdata.tl_tx_tail = cur_tx; 1516 1517 if (sc->tl_txeoc) { 1518 sc->tl_txeoc = 0; 1519 CSR_WRITE_4(sc, TL_CH_PARM, VTOPHYS(start_tx->tl_ptr)); 1520 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1521 cmd &= ~TL_CMD_RT; 1522 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1523 CMD_PUT(sc, cmd); 1524 } 1525 } else { 1526 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 1527 sc->tl_cdata.tl_tx_tail = cur_tx; 1528 } 1529 1530 /* 1531 * Set a timeout in case the chip goes out to lunch. 1532 */ 1533 ifp->if_timer = 10; 1534 } 1535 1536 void 1537 tl_init(void *xsc) 1538 { 1539 struct tl_softc *sc = xsc; 1540 struct ifnet *ifp = &sc->arpcom.ac_if; 1541 int s; 1542 1543 s = splnet(); 1544 1545 /* 1546 * Cancel pending I/O. 1547 */ 1548 tl_stop(sc); 1549 1550 /* Initialize TX FIFO threshold */ 1551 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1552 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 1553 1554 /* Set PCI burst size */ 1555 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 1556 1557 tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 1558 1559 /* Init our MAC address */ 1560 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 1561 1562 /* Program promiscuous mode and multicast filters. */ 1563 tl_iff(sc); 1564 1565 /* Init circular RX list. */ 1566 if (tl_list_rx_init(sc) == ENOBUFS) { 1567 printf("%s: initialization failed: no memory for rx buffers\n", 1568 sc->sc_dev.dv_xname); 1569 tl_stop(sc); 1570 splx(s); 1571 return; 1572 } 1573 1574 /* Init TX pointers. */ 1575 tl_list_tx_init(sc); 1576 1577 /* Enable PCI interrupts. */ 1578 CMD_SET(sc, TL_CMD_INTSON); 1579 1580 /* Load the address of the rx list */ 1581 CMD_SET(sc, TL_CMD_RT); 1582 CSR_WRITE_4(sc, TL_CH_PARM, VTOPHYS(&sc->tl_ldata->tl_rx_list[0])); 1583 1584 if (!sc->tl_bitrate) 1585 mii_mediachg(&sc->sc_mii); 1586 else 1587 tl_ifmedia_upd(ifp); 1588 1589 /* Send the RX go command */ 1590 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 1591 1592 splx(s); 1593 1594 /* Start the stats update counter */ 1595 timeout_set(&sc->tl_stats_tmo, tl_stats_update, sc); 1596 timeout_add_sec(&sc->tl_stats_tmo, 1); 1597 timeout_set(&sc->tl_wait_tmo, tl_wait_up, sc); 1598 timeout_add_sec(&sc->tl_wait_tmo, 2); 1599 } 1600 1601 /* 1602 * Set media options. 1603 */ 1604 int 1605 tl_ifmedia_upd(struct ifnet *ifp) 1606 { 1607 struct tl_softc *sc = ifp->if_softc; 1608 1609 if (sc->tl_bitrate) 1610 tl_setmode(sc, sc->ifmedia.ifm_media); 1611 else 1612 mii_mediachg(&sc->sc_mii); 1613 1614 return(0); 1615 } 1616 1617 /* 1618 * Report current media status. 1619 */ 1620 void 1621 tl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1622 { 1623 struct tl_softc *sc; 1624 struct mii_data *mii; 1625 1626 sc = ifp->if_softc; 1627 mii = &sc->sc_mii; 1628 1629 ifmr->ifm_active = IFM_ETHER; 1630 if (sc->tl_bitrate) { 1631 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 1632 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 1633 else 1634 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 1635 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 1636 ifmr->ifm_active |= IFM_HDX; 1637 else 1638 ifmr->ifm_active |= IFM_FDX; 1639 return; 1640 } else { 1641 mii_pollstat(mii); 1642 ifmr->ifm_active = mii->mii_media_active; 1643 ifmr->ifm_status = mii->mii_media_status; 1644 } 1645 } 1646 1647 int 1648 tl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1649 { 1650 struct tl_softc *sc = ifp->if_softc; 1651 struct ifreq *ifr = (struct ifreq *) data; 1652 int s, error = 0; 1653 1654 s = splnet(); 1655 1656 switch(command) { 1657 case SIOCSIFADDR: 1658 ifp->if_flags |= IFF_UP; 1659 if (!(ifp->if_flags & IFF_RUNNING)) 1660 tl_init(sc); 1661 break; 1662 1663 case SIOCSIFFLAGS: 1664 if (ifp->if_flags & IFF_UP) { 1665 if (ifp->if_flags & IFF_RUNNING) 1666 error = ENETRESET; 1667 else 1668 tl_init(sc); 1669 } else { 1670 if (ifp->if_flags & IFF_RUNNING) 1671 tl_stop(sc); 1672 } 1673 break; 1674 1675 case SIOCSIFMEDIA: 1676 case SIOCGIFMEDIA: 1677 if (sc->tl_bitrate) 1678 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1679 else 1680 error = ifmedia_ioctl(ifp, ifr, 1681 &sc->sc_mii.mii_media, command); 1682 break; 1683 1684 default: 1685 error = ether_ioctl(ifp, &sc->arpcom, command, data); 1686 } 1687 1688 if (error == ENETRESET) { 1689 if (ifp->if_flags & IFF_RUNNING) 1690 tl_iff(sc); 1691 error = 0; 1692 } 1693 1694 splx(s); 1695 return(error); 1696 } 1697 1698 void 1699 tl_watchdog(struct ifnet *ifp) 1700 { 1701 struct tl_softc *sc; 1702 1703 sc = ifp->if_softc; 1704 1705 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1706 1707 ifp->if_oerrors++; 1708 1709 tl_softreset(sc, 1); 1710 tl_init(sc); 1711 } 1712 1713 /* 1714 * Stop the adapter and free any mbufs allocated to the 1715 * RX and TX lists. 1716 */ 1717 void 1718 tl_stop(struct tl_softc *sc) 1719 { 1720 int i; 1721 struct ifnet *ifp; 1722 1723 ifp = &sc->arpcom.ac_if; 1724 1725 /* Stop the stats updater. */ 1726 timeout_del(&sc->tl_stats_tmo); 1727 timeout_del(&sc->tl_wait_tmo); 1728 1729 /* Stop the transmitter */ 1730 CMD_CLR(sc, TL_CMD_RT); 1731 CMD_SET(sc, TL_CMD_STOP); 1732 CSR_WRITE_4(sc, TL_CH_PARM, 0); 1733 1734 /* Stop the receiver */ 1735 CMD_SET(sc, TL_CMD_RT); 1736 CMD_SET(sc, TL_CMD_STOP); 1737 CSR_WRITE_4(sc, TL_CH_PARM, 0); 1738 1739 /* 1740 * Disable host interrupts. 1741 */ 1742 CMD_SET(sc, TL_CMD_INTSOFF); 1743 1744 /* 1745 * Clear list pointer. 1746 */ 1747 CSR_WRITE_4(sc, TL_CH_PARM, 0); 1748 1749 /* 1750 * Free the RX lists. 1751 */ 1752 for (i = 0; i < TL_RX_LIST_CNT; i++) { 1753 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 1754 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 1755 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 1756 } 1757 } 1758 bzero(&sc->tl_ldata->tl_rx_list, sizeof(sc->tl_ldata->tl_rx_list)); 1759 1760 /* 1761 * Free the TX list buffers. 1762 */ 1763 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1764 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 1765 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 1766 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 1767 } 1768 } 1769 bzero(&sc->tl_ldata->tl_tx_list, sizeof(sc->tl_ldata->tl_tx_list)); 1770 1771 ifp->if_flags &= ~IFF_RUNNING; 1772 ifq_clr_oactive(&ifp->if_snd); 1773 } 1774 1775 int 1776 tl_probe(struct device *parent, void *match, void *aux) 1777 { 1778 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 1779 1780 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TI) { 1781 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TI_TLAN) 1782 return 1; 1783 return 0; 1784 } 1785 1786 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_COMPAQ) { 1787 switch (PCI_PRODUCT(pa->pa_id)) { 1788 case PCI_PRODUCT_COMPAQ_N100TX: 1789 case PCI_PRODUCT_COMPAQ_N10T: 1790 case PCI_PRODUCT_COMPAQ_IntNF3P: 1791 case PCI_PRODUCT_COMPAQ_DPNet100TX: 1792 case PCI_PRODUCT_COMPAQ_IntPL100TX: 1793 case PCI_PRODUCT_COMPAQ_DP4000: 1794 case PCI_PRODUCT_COMPAQ_N10T2: 1795 case PCI_PRODUCT_COMPAQ_N10_TX_UTP: 1796 case PCI_PRODUCT_COMPAQ_NF3P: 1797 case PCI_PRODUCT_COMPAQ_NF3P_BNC: 1798 return 1; 1799 } 1800 return 0; 1801 } 1802 1803 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_OLICOM) { 1804 switch (PCI_PRODUCT(pa->pa_id)) { 1805 case PCI_PRODUCT_OLICOM_OC2183: 1806 case PCI_PRODUCT_OLICOM_OC2325: 1807 case PCI_PRODUCT_OLICOM_OC2326: 1808 return 1; 1809 } 1810 return 0; 1811 } 1812 1813 return 0; 1814 } 1815 1816 void 1817 tl_attach(struct device *parent, struct device *self, void *aux) 1818 { 1819 struct tl_softc *sc = (struct tl_softc *)self; 1820 struct pci_attach_args *pa = aux; 1821 pci_chipset_tag_t pc = pa->pa_pc; 1822 pci_intr_handle_t ih; 1823 const char *intrstr = NULL; 1824 struct ifnet *ifp = &sc->arpcom.ac_if; 1825 bus_size_t iosize; 1826 u_int32_t command; 1827 int i, rseg; 1828 bus_dma_segment_t seg; 1829 bus_dmamap_t dmamap; 1830 caddr_t kva; 1831 1832 /* 1833 * Map control/status registers. 1834 */ 1835 1836 #ifdef TL_USEIOSPACE 1837 if (pci_mapreg_map(pa, TL_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1838 &sc->tl_btag, &sc->tl_bhandle, NULL, &iosize, 0)) { 1839 if (pci_mapreg_map(pa, TL_PCI_LOMEM, PCI_MAPREG_TYPE_IO, 0, 1840 &sc->tl_btag, &sc->tl_bhandle, NULL, &iosize, 0)) { 1841 printf(": can't map i/o space\n"); 1842 return; 1843 } 1844 } 1845 #else 1846 if (pci_mapreg_map(pa, TL_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 1847 &sc->tl_btag, &sc->tl_bhandle, NULL, &iosize, 0)){ 1848 if (pci_mapreg_map(pa, TL_PCI_LOIO, PCI_MAPREG_TYPE_MEM, 0, 1849 &sc->tl_btag, &sc->tl_bhandle, NULL, &iosize, 0)){ 1850 printf(": can't map mem space\n"); 1851 return; 1852 } 1853 } 1854 #endif 1855 1856 /* 1857 * Manual wants the PCI latency timer jacked up to 0xff 1858 */ 1859 command = pci_conf_read(pa->pa_pc, pa->pa_tag, TL_PCI_LATENCY_TIMER); 1860 command |= 0x0000ff00; 1861 pci_conf_write(pa->pa_pc, pa->pa_tag, TL_PCI_LATENCY_TIMER, command); 1862 1863 /* 1864 * Allocate our interrupt. 1865 */ 1866 if (pci_intr_map(pa, &ih)) { 1867 printf(": couldn't map interrupt\n"); 1868 bus_space_unmap(sc->tl_btag, sc->tl_bhandle, iosize); 1869 return; 1870 } 1871 intrstr = pci_intr_string(pc, ih); 1872 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, tl_intr, sc, 1873 self->dv_xname); 1874 if (sc->sc_ih == NULL) { 1875 printf(": could not establish interrupt"); 1876 if (intrstr != NULL) 1877 printf(" at %s", intrstr); 1878 printf("\n"); 1879 bus_space_unmap(sc->tl_btag, sc->tl_bhandle, iosize); 1880 return; 1881 } 1882 printf(": %s", intrstr); 1883 1884 sc->sc_dmat = pa->pa_dmat; 1885 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct tl_list_data), 1886 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 1887 printf("%s: can't alloc list\n", sc->sc_dev.dv_xname); 1888 bus_space_unmap(sc->tl_btag, sc->tl_bhandle, iosize); 1889 return; 1890 } 1891 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, sizeof(struct tl_list_data), 1892 &kva, BUS_DMA_NOWAIT)) { 1893 printf("%s: can't map dma buffers (%zd bytes)\n", 1894 sc->sc_dev.dv_xname, sizeof(struct tl_list_data)); 1895 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1896 return; 1897 } 1898 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct tl_list_data), 1, 1899 sizeof(struct tl_list_data), 0, BUS_DMA_NOWAIT, &dmamap)) { 1900 printf("%s: can't create dma map\n", sc->sc_dev.dv_xname); 1901 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct tl_list_data)); 1902 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1903 bus_space_unmap(sc->tl_btag, sc->tl_bhandle, iosize); 1904 return; 1905 } 1906 if (bus_dmamap_load(sc->sc_dmat, dmamap, kva, 1907 sizeof(struct tl_list_data), NULL, BUS_DMA_NOWAIT)) { 1908 printf("%s: can't load dma map\n", sc->sc_dev.dv_xname); 1909 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1910 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct tl_list_data)); 1911 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1912 bus_space_unmap(sc->tl_btag, sc->tl_bhandle, iosize); 1913 return; 1914 } 1915 sc->tl_ldata = (struct tl_list_data *)kva; 1916 1917 for (sc->tl_product = tl_prods; sc->tl_product->tp_vend; 1918 sc->tl_product++) { 1919 if (sc->tl_product->tp_vend == PCI_VENDOR(pa->pa_id) && 1920 sc->tl_product->tp_prod == PCI_PRODUCT(pa->pa_id)) 1921 break; 1922 } 1923 1924 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_COMPAQ || 1925 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TI) 1926 sc->tl_eeaddr = TL_EEPROM_EADDR; 1927 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_OLICOM) 1928 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1929 1930 /* 1931 * Reset adapter. 1932 */ 1933 tl_softreset(sc, 1); 1934 tl_hardreset(self); 1935 DELAY(1000000); 1936 tl_softreset(sc, 1); 1937 1938 /* 1939 * Get station address from the EEPROM. 1940 */ 1941 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1942 sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1943 printf("\n%s: failed to read station address\n", 1944 sc->sc_dev.dv_xname); 1945 bus_space_unmap(sc->tl_btag, sc->tl_bhandle, iosize); 1946 return; 1947 } 1948 1949 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_OLICOM) { 1950 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1951 u_int16_t *p; 1952 1953 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 1954 *p = ntohs(*p); 1955 } 1956 } 1957 1958 printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); 1959 1960 ifp = &sc->arpcom.ac_if; 1961 ifp->if_softc = sc; 1962 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1963 ifp->if_ioctl = tl_ioctl; 1964 ifp->if_start = tl_start; 1965 ifp->if_watchdog = tl_watchdog; 1966 IFQ_SET_MAXLEN(&ifp->if_snd, TL_TX_LIST_CNT - 1); 1967 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1968 1969 ifp->if_capabilities = IFCAP_VLAN_MTU; 1970 1971 /* 1972 * Reset adapter (again). 1973 */ 1974 tl_softreset(sc, 1); 1975 tl_hardreset(self); 1976 DELAY(1000000); 1977 tl_softreset(sc, 1); 1978 1979 /* 1980 * Do MII setup. If no PHYs are found, then this is a 1981 * bitrate ThunderLAN chip that only supports 10baseT 1982 * and AUI/BNC. 1983 */ 1984 sc->sc_mii.mii_ifp = ifp; 1985 sc->sc_mii.mii_readreg = tl_miibus_readreg; 1986 sc->sc_mii.mii_writereg = tl_miibus_writereg; 1987 sc->sc_mii.mii_statchg = tl_miibus_statchg; 1988 ifmedia_init(&sc->sc_mii.mii_media, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1989 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 1990 0); 1991 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1992 struct ifmedia *ifm; 1993 sc->tl_bitrate = 1; 1994 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1995 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1996 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1997 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1998 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1999 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 2000 /* Reset again, this time setting bitrate mode. */ 2001 tl_softreset(sc, 1); 2002 ifm = &sc->ifmedia; 2003 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2004 tl_ifmedia_upd(ifp); 2005 } else 2006 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2007 2008 /* 2009 * Attach us everywhere. 2010 */ 2011 if_attach(ifp); 2012 ether_ifattach(ifp); 2013 } 2014 2015 void 2016 tl_wait_up(void *xsc) 2017 { 2018 struct tl_softc *sc = xsc; 2019 struct ifnet *ifp = &sc->arpcom.ac_if; 2020 2021 ifp->if_flags |= IFF_RUNNING; 2022 ifq_clr_oactive(&ifp->if_snd); 2023 } 2024 2025 struct cfattach tl_ca = { 2026 sizeof(struct tl_softc), tl_probe, tl_attach 2027 }; 2028 2029 struct cfdriver tl_cd = { 2030 NULL, "tl", DV_IFNET 2031 }; 2032