1 /* $OpenBSD: if_tht.c,v 1.139 2016/04/13 10:34:32 mpi Exp $ */ 2 3 /* 4 * Copyright (c) 2007 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Driver for the Tehuti TN30xx multi port 10Gb Ethernet chipsets, 21 * see http://www.tehutinetworks.net/. 22 * 23 * This driver was made possible because Tehuti networks provided 24 * hardware and documentation. Thanks! 25 */ 26 27 #include "bpfilter.h" 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/sockio.h> 32 #include <sys/mbuf.h> 33 #include <sys/kernel.h> 34 #include <sys/socket.h> 35 #include <sys/malloc.h> 36 #include <sys/device.h> 37 #include <sys/timeout.h> 38 #include <sys/queue.h> 39 #include <sys/rwlock.h> 40 #include <sys/time.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #include <net/if.h> 49 #include <net/if_media.h> 50 51 #if NBPFILTER > 0 52 #include <net/bpf.h> 53 #endif 54 55 #include <netinet/in.h> 56 #include <netinet/if_ether.h> 57 58 #ifdef THT_DEBUG 59 #define THT_D_FIFO (1<<0) 60 #define THT_D_TX (1<<1) 61 #define THT_D_RX (1<<2) 62 #define THT_D_INTR (1<<3) 63 64 int thtdebug = THT_D_TX | THT_D_RX | THT_D_INTR; 65 66 #define DPRINTF(l, f...) do { if (thtdebug & (l)) printf(f); } while (0) 67 #else 68 #define DPRINTF(l, f...) 69 #endif 70 71 /* registers */ 72 73 #define THT_PCI_BAR 0x10 74 75 #define _Q(_q) ((_q) * 4) 76 77 /* General Configuration */ 78 #define THT_REG_END_SEL 0x5448 /* PCI Endian Select */ 79 #define THT_REG_CLKPLL 0x5000 80 #define THT_REG_CLKPLL_PLLLK (1<<9) /* PLL is locked */ 81 #define THT_REG_CLKPLL_RSTEND (1<<8) /* Reset ended */ 82 #define THT_REG_CLKPLL_TXF_DIS (1<<3) /* TX Free disabled */ 83 #define THT_REG_CLKPLL_VNT_STOP (1<<2) /* VENETO Stop */ 84 #define THT_REG_CLKPLL_PLLRST (1<<1) /* PLL Reset */ 85 #define THT_REG_CLKPLL_SFTRST (1<<0) /* Software Reset */ 86 /* Descriptors and FIFO Registers */ 87 #define THT_REG_TXT_CFG0(_q) (0x4040 + _Q(_q)) /* CFG0 TX Task queues */ 88 #define THT_REG_RXF_CFG0(_q) (0x4050 + _Q(_q)) /* CFG0 RX Free queues */ 89 #define THT_REG_RXD_CFG0(_q) (0x4060 + _Q(_q)) /* CFG0 RX DSC queues */ 90 #define THT_REG_TXF_CFG0(_q) (0x4070 + _Q(_q)) /* CFG0 TX Free queues */ 91 #define THT_REG_TXT_CFG1(_q) (0x4000 + _Q(_q)) /* CFG1 TX Task queues */ 92 #define THT_REG_RXF_CFG1(_q) (0x4010 + _Q(_q)) /* CFG1 RX Free queues */ 93 #define THT_REG_RXD_CFG1(_q) (0x4020 + _Q(_q)) /* CFG1 RX DSC queues */ 94 #define THT_REG_TXF_CFG1(_q) (0x4030 + _Q(_q)) /* CFG1 TX Free queues */ 95 #define THT_REG_TXT_RPTR(_q) (0x40c0 + _Q(_q)) /* TX Task read ptr */ 96 #define THT_REG_RXF_RPTR(_q) (0x40d0 + _Q(_q)) /* RX Free read ptr */ 97 #define THT_REG_RXD_RPTR(_q) (0x40e0 + _Q(_q)) /* RX DSC read ptr */ 98 #define THT_REG_TXF_RPTR(_q) (0x40f0 + _Q(_q)) /* TX Free read ptr */ 99 #define THT_REG_TXT_WPTR(_q) (0x4080 + _Q(_q)) /* TX Task write ptr */ 100 #define THT_REG_RXF_WPTR(_q) (0x4090 + _Q(_q)) /* RX Free write ptr */ 101 #define THT_REG_RXD_WPTR(_q) (0x40a0 + _Q(_q)) /* RX DSC write ptr */ 102 #define THT_REG_TXF_WPTR(_q) (0x40b0 + _Q(_q)) /* TX Free write ptr */ 103 #define THT_REG_HTB_ADDR 0x4100 /* HTB Addressing Mechanism enable */ 104 #define THT_REG_HTB_ADDR_HI 0x4110 /* High HTB Address */ 105 #define THT_REG_HTB_ST_TMR 0x3290 /* HTB Timer */ 106 #define THT_REG_RDINTCM(_q) (0x5120 + _Q(_q)) /* RX DSC Intr Coalescing */ 107 #define THT_REG_RDINTCM_PKT_TH(_c) ((_c)<<20) /* pkt count threshold */ 108 #define THT_REG_RDINTCM_RXF_TH(_c) ((_c)<<16) /* rxf intr req thresh */ 109 #define THT_REG_RDINTCM_COAL_RC (1<<15) /* coalescing timer recharge */ 110 #define THT_REG_RDINTCM_COAL(_c) (_c) /* coalescing timer */ 111 #define THT_REG_TDINTCM(_q) (0x5130 + _Q(_q)) /* TX DSC Intr Coalescing */ 112 #define THT_REG_TDINTCM_PKT_TH(_c) ((_c)<<20) /* pkt count threshold */ 113 #define THT_REG_TDINTCM_COAL_RC (1<<15) /* coalescing timer recharge */ 114 #define THT_REG_TDINTCM_COAL(_c) (_c) /* coalescing timer */ 115 /* 10G Ethernet MAC */ 116 #define THT_REG_10G_REV 0x6000 /* Revision */ 117 #define THT_REG_10G_SCR 0x6004 /* Scratch */ 118 #define THT_REG_10G_CTL 0x6008 /* Control/Status */ 119 #define THT_REG_10G_CTL_CMD_FRAME_EN (1<<13) /* cmd frame enable */ 120 #define THT_REG_10G_CTL_SW_RESET (1<<12) /* sw reset */ 121 #define THT_REG_10G_CTL_STATS_AUTO_CLR (1<<11) /* auto clear statistics */ 122 #define THT_REG_10G_CTL_LOOPBACK (1<<10) /* enable loopback */ 123 #define THT_REG_10G_CTL_TX_ADDR_INS (1<<9) /* set mac on tx */ 124 #define THT_REG_10G_CTL_PAUSE_IGNORE (1<<8) /* ignore pause */ 125 #define THT_REG_10G_CTL_PAUSE_FWD (1<<7) /* forward pause */ 126 #define THT_REG_10G_CTL_CRC_FWD (1<<6) /* crc forward */ 127 #define THT_REG_10G_CTL_PAD (1<<5) /* frame padding */ 128 #define THT_REG_10G_CTL_PROMISC (1<<4) /* promiscuous mode */ 129 #define THT_REG_10G_CTL_WAN_MODE (1<<3) /* WAN mode */ 130 #define THT_REG_10G_CTL_RX_EN (1<<1) /* RX enable */ 131 #define THT_REG_10G_CTL_TX_EN (1<<0) /* TX enable */ 132 #define THT_REG_10G_FRM_LEN 0x6014 /* Frame Length */ 133 #define THT_REG_10G_PAUSE 0x6018 /* Pause Quanta */ 134 #define THT_REG_10G_RX_SEC 0x601c /* RX Section */ 135 #define THT_REG_10G_TX_SEC 0x6020 /* TX Section */ 136 #define THT_REG_10G_SEC_AVAIL(_t) (_t) /* section available thresh*/ 137 #define THT_REG_10G_SEC_EMPTY(_t) ((_t)<<16) /* section empty avail */ 138 #define THT_REG_10G_RFIFO_AEF 0x6024 /* RX FIFO Almost Empty/Full */ 139 #define THT_REG_10G_TFIFO_AEF 0x6028 /* TX FIFO Almost Empty/Full */ 140 #define THT_REG_10G_FIFO_AE(_t) (_t) /* almost empty */ 141 #define THT_REG_10G_FIFO_AF(_t) ((_t)<<16) /* almost full */ 142 #define THT_REG_10G_SM_STAT 0x6030 /* MDIO Status */ 143 #define THT_REG_10G_SM_CMD 0x6034 /* MDIO Command */ 144 #define THT_REG_10G_SM_DAT 0x6038 /* MDIO Data */ 145 #define THT_REG_10G_SM_ADD 0x603c /* MDIO Address */ 146 #define THT_REG_10G_STAT 0x6040 /* Status */ 147 /* Statistic Counters */ 148 /* XXX todo */ 149 /* Status Registers */ 150 #define THT_REG_MAC_LNK_STAT 0x0200 /* Link Status */ 151 #define THT_REG_MAC_LNK_STAT_DIS (1<<4) /* Mac Stats read disable */ 152 #define THT_REG_MAC_LNK_STAT_LINK (1<<2) /* Link State */ 153 #define THT_REG_MAC_LNK_STAT_REM_FAULT (1<<1) /* Remote Fault */ 154 #define THT_REG_MAC_LNK_STAT_LOC_FAULT (1<<0) /* Local Fault */ 155 /* Interrupt Registers */ 156 #define THT_REG_ISR 0x5100 /* Interrupt Status */ 157 #define THT_REG_ISR_LINKCHG(_p) (1<<(27+(_p))) /* link changed */ 158 #define THT_REG_ISR_GPIO (1<<26) /* GPIO */ 159 #define THT_REG_ISR_RFRSH (1<<25) /* DDR Refresh */ 160 #define THT_REG_ISR_SWI (1<<23) /* software interrupt */ 161 #define THT_REG_ISR_RXF(_q) (1<<(19+(_q))) /* rx free fifo */ 162 #define THT_REG_ISR_TXF(_q) (1<<(15+(_q))) /* tx free fifo */ 163 #define THT_REG_ISR_RXD(_q) (1<<(11+(_q))) /* rx desc fifo */ 164 #define THT_REG_ISR_TMR(_t) (1<<(6+(_t))) /* timer */ 165 #define THT_REG_ISR_VNT (1<<5) /* optistrata */ 166 #define THT_REG_ISR_RxFL (1<<4) /* RX Full */ 167 #define THT_REG_ISR_TR (1<<2) /* table read */ 168 #define THT_REG_ISR_PCIE_LNK_INT (1<<1) /* pcie link fail */ 169 #define THT_REG_ISR_GPLE_CLR (1<<0) /* pcie timeout */ 170 #define THT_FMT_ISR "\020" "\035LINKCHG1" "\034LINKCHG0" \ 171 "\033GPIO" "\032RFRSH" "\030SWI" \ 172 "\027RXF3" "\026RXF2" "\025RXF1" \ 173 "\024RXF0" "\023TXF3" "\022TXF2" \ 174 "\021TXF1" "\020TXF0" "\017RXD3" \ 175 "\016RXD2" "\015RXD1" "\014RXD0" \ 176 "\012TMR3" "\011TMR2" "\010TMR1" \ 177 "\007TMR0" "\006VNT" "\005RxFL" \ 178 "\003TR" "\002PCI_LNK_INT" \ 179 "\001GPLE_CLR" 180 #define THT_REG_ISR_GTI 0x5080 /* GTI Interrupt Status */ 181 #define THT_REG_IMR 0x5110 /* Interrupt Mask */ 182 #define THT_REG_IMR_LINKCHG(_p) (1<<(27+(_p))) /* link changed */ 183 #define THT_REG_IMR_GPIO (1<<26) /* GPIO */ 184 #define THT_REG_IMR_RFRSH (1<<25) /* DDR Refresh */ 185 #define THT_REG_IMR_SWI (1<<23) /* software interrupt */ 186 #define THT_REG_IMR_RXF(_q) (1<<(19+(_q))) /* rx free fifo */ 187 #define THT_REG_IMR_TXF(_q) (1<<(15+(_q))) /* tx free fifo */ 188 #define THT_REG_IMR_RXD(_q) (1<<(11+(_q))) /* rx desc fifo */ 189 #define THT_REG_IMR_TMR(_t) (1<<(6+(_t))) /* timer */ 190 #define THT_REG_IMR_VNT (1<<5) /* optistrata */ 191 #define THT_REG_IMR_RxFL (1<<4) /* RX Full */ 192 #define THT_REG_IMR_TR (1<<2) /* table read */ 193 #define THT_REG_IMR_PCIE_LNK_INT (1<<1) /* pcie link fail */ 194 #define THT_REG_IMR_GPLE_CLR (1<<0) /* pcie timeout */ 195 #define THT_REG_IMR_GTI 0x5090 /* GTI Interrupt Mask */ 196 #define THT_REG_ISR_MSK 0x5140 /* ISR Masked */ 197 /* Global Counters */ 198 /* XXX todo */ 199 /* DDR2 SDRAM Controller Registers */ 200 /* XXX TBD */ 201 /* EEPROM Registers */ 202 /* XXX todo */ 203 /* Init arbitration and status registers */ 204 #define THT_REG_INIT_SEMAPHORE 0x5170 /* Init Semaphore */ 205 #define THT_REG_INIT_STATUS 0x5180 /* Init Status */ 206 /* PCI Credits Registers */ 207 /* XXX todo */ 208 /* TX Arbitration Registers */ 209 #define THT_REG_TXTSK_PR(_q) (0x41b0 + _Q(_q)) /* TX Queue Priority */ 210 /* RX Part Registers */ 211 #define THT_REG_RX_FLT 0x1240 /* RX Filter Configuration */ 212 #define THT_REG_RX_FLT_ATXER (1<<15) /* accept with xfer err */ 213 #define THT_REG_RX_FLT_ATRM (1<<14) /* accept with term err */ 214 #define THT_REG_RX_FLT_AFTSQ (1<<13) /* accept with fault seq */ 215 #define THT_REG_RX_FLT_OSEN (1<<12) /* enable pkts */ 216 #define THT_REG_RX_FLT_APHER (1<<11) /* accept with phy err */ 217 #define THT_REG_RX_FLT_TXFC (1<<10) /* TX flow control */ 218 #define THT_REG_RX_FLT_FDA (1<<8) /* filter direct address */ 219 #define THT_REG_RX_FLT_AOF (1<<7) /* accept overflow frame */ 220 #define THT_REG_RX_FLT_ACF (1<<6) /* accept control frame */ 221 #define THT_REG_RX_FLT_ARUNT (1<<5) /* accept runt */ 222 #define THT_REG_RX_FLT_ACRC (1<<4) /* accept crc error */ 223 #define THT_REG_RX_FLT_AM (1<<3) /* accept multicast */ 224 #define THT_REG_RX_FLT_AB (1<<2) /* accept broadcast */ 225 #define THT_REG_RX_FLT_PRM_MASK 0x3 /* promiscuous mode */ 226 #define THT_REG_RX_FLT_PRM_NORMAL 0x0 /* normal mode */ 227 #define THT_REG_RX_FLT_PRM_ALL 0x1 /* pass all incoming frames */ 228 #define THT_REG_RX_MAX_FRAME 0x12c0 /* Max Frame Size */ 229 #define THT_REG_RX_UNC_MAC0 0x1250 /* MAC Address low word */ 230 #define THT_REG_RX_UNC_MAC1 0x1260 /* MAC Address mid word */ 231 #define THT_REG_RX_UNC_MAC2 0x1270 /* MAC Address high word */ 232 #define THT_REG_RX_MAC_MCST0(_m) (0x1a80 + (_m)*8) 233 #define THT_REG_RX_MAC_MCST1(_m) (0x1a84 + (_m)*8) 234 #define THT_REG_RX_MAC_MCST_CNT 15 235 #define THT_REG_RX_MCST_HASH 0x1a00 /* imperfect multicast filter hash */ 236 #define THT_REG_RX_MCST_HASH_SIZE (256 / NBBY) 237 /* OptiStrata Debug Registers */ 238 #define THT_REG_VPC 0x2300 /* Program Counter */ 239 #define THT_REG_VLI 0x2310 /* Last Interrupt */ 240 #define THT_REG_VIC 0x2320 /* Interrupts Count */ 241 #define THT_REG_VTMR 0x2330 /* Timer */ 242 #define THT_REG_VGLB 0x2340 /* Global */ 243 /* SW Reset Registers */ 244 #define THT_REG_RST_PRT 0x7000 /* Reset Port */ 245 #define THT_REG_RST_PRT_ACTIVE 0x1 /* port reset is active */ 246 #define THT_REG_DIS_PRT 0x7010 /* Disable Port */ 247 #define THT_REG_RST_QU_0 0x7020 /* Reset Queue 0 */ 248 #define THT_REG_RST_QU_1 0x7028 /* Reset Queue 1 */ 249 #define THT_REG_DIS_QU_0 0x7030 /* Disable Queue 0 */ 250 #define THT_REG_DIS_QU_1 0x7038 /* Disable Queue 1 */ 251 252 #define THT_PORT_SIZE 0x8000 253 #define THT_PORT_REGION(_p) ((_p) * THT_PORT_SIZE) 254 #define THT_NQUEUES 4 255 256 #define THT_FIFO_ALIGN 4096 257 #define THT_FIFO_SIZE_4k 0x0 258 #define THT_FIFO_SIZE_8k 0x1 259 #define THT_FIFO_SIZE_16k 0x2 260 #define THT_FIFO_SIZE_32k 0x3 261 #define THT_FIFO_SIZE(_r) (4096 * (1<<(_r))) 262 #define THT_FIFO_GAP 8 /* keep 8 bytes between ptrs */ 263 #define THT_FIFO_PTR_MASK 0x00007ff8 /* rptr/wptr mask */ 264 265 #define THT_FIFO_DESC_LEN 208 /* a descriptor cant be bigger than this */ 266 267 #define THT_IMR_DOWN(_p) (THT_REG_IMR_LINKCHG(_p)) 268 #define THT_IMR_UP(_p) (THT_REG_IMR_LINKCHG(_p) | \ 269 THT_REG_IMR_RXF(0) | THT_REG_IMR_TXF(0) | \ 270 THT_REG_IMR_RXD(0)) 271 272 /* hardware structures (we're using the 64 bit variants) */ 273 274 /* physical buffer descriptor */ 275 struct tht_pbd { 276 u_int32_t addr_lo; 277 u_int32_t addr_hi; 278 u_int32_t len; 279 } __packed; 280 #define THT_PBD_PKTLEN (64 * 1024) 281 282 /* rx free fifo */ 283 struct tht_rx_free { 284 u_int16_t bc; /* buffer count (0:4) */ 285 u_int16_t type; 286 287 u_int64_t uid; 288 289 /* followed by a pdb list */ 290 } __packed; 291 #define THT_RXF_TYPE 1 292 #define THT_RXF_1ST_PDB_LEN 128 293 #define THT_RXF_SGL_LEN ((THT_FIFO_DESC_LEN - \ 294 sizeof(struct tht_rx_free)) / \ 295 sizeof(struct tht_pbd)) 296 #define THT_RXF_PKT_NUM 128 297 298 /* rx descriptor */ 299 struct tht_rx_desc { 300 u_int32_t flags; 301 #define THT_RXD_FLAGS_BC(_f) ((_f) & 0x1f) /* buffer count */ 302 #define THT_RXD_FLAGS_RXFQ(_f) (((_f)>>8) & 0x3) /* rxf queue id */ 303 #define THT_RXD_FLAGS_TO (1<<15) 304 #define THT_RXD_FLAGS_TYPE(_f) (((_f)>>16) & 0xf) /* desc type */ 305 #define THT_RXD_FLAGS_OVF (1<<21) /* overflow error */ 306 #define THT_RXD_FLAGS_RUNT (1<<22) /* runt error */ 307 #define THT_RXD_FLAGS_CRC (1<<23) /* crc error */ 308 #define THT_RXD_FLAGS_UDPCS (1<<24) /* udp checksum error */ 309 #define THT_RXD_FLAGS_TCPCS (1<<25) /* tcp checksum error */ 310 #define THT_RXD_FLAGS_IPCS (1<<26) /* ip checksum error */ 311 #define THT_RXD_FLAGS_PKT_ID 0x70000000 312 #define THT_RXD_FLAGS_PKT_ID_NONIP 0x00000000 313 #define THT_RXD_FLAGS_PKT_ID_TCP4 0x10000000 314 #define THT_RXD_FLAGS_PKT_ID_UDP4 0x20000000 315 #define THT_RXD_FLAGS_PKT_ID_IPV4 0x30000000 316 #define THT_RXD_FLAGS_PKT_ID_TCP6 0x50000000 317 #define THT_RXD_FLAGS_PKT_ID_UDP6 0x60000000 318 #define THT_RXD_FLAGS_PKT_ID_IPV6 0x70000000 319 #define THT_RXD_FLAGS_VTAG (1<<31) 320 u_int16_t len; 321 u_int16_t vlan; 322 #define THT_RXD_VLAN_ID(_v) ((_v) & 0xfff) 323 #define THT_RXD_VLAN_CFI (1<<12) 324 #define THT_RXD_VLAN_PRI(_v) ((_v) & 0x7) >> 13) 325 326 u_int64_t uid; 327 } __packed; 328 #define THT_RXD_TYPE 2 329 330 /* rx decriptor type 3: data chain instruction */ 331 struct tht_rx_desc_dc { 332 /* preceded by tht_rx_desc */ 333 334 u_int16_t cd_offset; 335 u_int16_t flags; 336 337 u_int8_t data[4]; 338 } __packed; 339 #define THT_RXD_TYPE_DC 3 340 341 /* rx descriptor type 4: rss (recv side scaling) information */ 342 struct tht_rx_desc_rss { 343 /* preceded by tht_rx_desc */ 344 345 u_int8_t rss_hft; 346 u_int8_t rss_type; 347 u_int8_t rss_tcpu; 348 u_int8_t reserved; 349 350 u_int32_t rss_hash; 351 } __packed; 352 #define THT_RXD_TYPE_RSS 4 353 354 /* tx task fifo */ 355 struct tht_tx_task { 356 u_int32_t flags; 357 #define THT_TXT_FLAGS_BC(_f) (_f) /* buffer count */ 358 #define THT_TXT_FLAGS_UDPCS (1<<5) /* udp checksum */ 359 #define THT_TXT_FLAGS_TCPCS (1<<6) /* tcp checksum */ 360 #define THT_TXT_FLAGS_IPCS (1<<7) /* ip checksum */ 361 #define THT_TXT_FLAGS_VTAG (1<<8) /* insert vlan tag */ 362 #define THT_TXT_FLAGS_LGSND (1<<9) /* tcp large send enabled */ 363 #define THT_TXT_FLAGS_FRAG (1<<10) /* ip fragmentation enabled */ 364 #define THT_TXT_FLAGS_CFI (1<<12) /* canonical format indicator */ 365 #define THT_TXT_FLAGS_PRIO(_f) ((_f)<<13) /* vlan priority */ 366 #define THT_TXT_FLAGS_VLAN(_f) ((_f)<<20) /* vlan id */ 367 u_int16_t mss_mtu; 368 u_int16_t len; 369 370 u_int64_t uid; 371 372 /* followed by a pbd list */ 373 } __packed; 374 #define THT_TXT_TYPE (3<<16) 375 #define THT_TXT_SGL_LEN ((THT_FIFO_DESC_LEN - \ 376 sizeof(struct tht_tx_task)) / \ 377 sizeof(struct tht_pbd)) 378 #define THT_TXT_PKT_NUM 128 379 380 /* tx free fifo */ 381 struct tht_tx_free { 382 u_int32_t status; 383 384 u_int64_t uid; 385 386 u_int32_t pad; 387 } __packed; 388 389 /* pci controller autoconf glue */ 390 391 struct thtc_softc { 392 struct device sc_dev; 393 394 bus_dma_tag_t sc_dmat; 395 396 bus_space_tag_t sc_memt; 397 bus_space_handle_t sc_memh; 398 bus_size_t sc_mems; 399 void *sc_ih; 400 }; 401 402 int thtc_match(struct device *, void *, void *); 403 void thtc_attach(struct device *, struct device *, void *); 404 int thtc_print(void *, const char *); 405 406 struct cfattach thtc_ca = { 407 sizeof(struct thtc_softc), thtc_match, thtc_attach 408 }; 409 410 struct cfdriver thtc_cd = { 411 NULL, "thtc", DV_DULL 412 }; 413 414 /* glue between the controller and the port */ 415 416 struct tht_attach_args { 417 int taa_port; 418 419 struct pci_attach_args *taa_pa; 420 }; 421 422 /* tht itself */ 423 424 struct tht_dmamem { 425 bus_dmamap_t tdm_map; 426 bus_dma_segment_t tdm_seg; 427 size_t tdm_size; 428 caddr_t tdm_kva; 429 }; 430 #define THT_DMA_MAP(_tdm) ((_tdm)->tdm_map) 431 #define THT_DMA_DVA(_tdm) ((_tdm)->tdm_map->dm_segs[0].ds_addr) 432 #define THT_DMA_KVA(_tdm) ((void *)(_tdm)->tdm_kva) 433 434 struct tht_fifo_desc { 435 bus_size_t tfd_cfg0; 436 bus_size_t tfd_cfg1; 437 bus_size_t tfd_rptr; 438 bus_size_t tfd_wptr; 439 u_int32_t tfd_size; 440 int tfd_write; 441 }; 442 #define THT_FIFO_PRE_SYNC(_d) ((_d)->tfd_write ? \ 443 BUS_DMASYNC_PREWRITE : \ 444 BUS_DMASYNC_PREREAD) 445 #define THT_FIFO_POST_SYNC(_d) ((_d)->tfd_write ? \ 446 BUS_DMASYNC_POSTWRITE : \ 447 BUS_DMASYNC_POSTREAD) 448 449 struct tht_fifo { 450 struct tht_fifo_desc *tf_desc; 451 struct tht_dmamem *tf_mem; 452 int tf_len; 453 int tf_rptr; 454 int tf_wptr; 455 int tf_ready; 456 }; 457 458 struct tht_pkt { 459 u_int64_t tp_id; 460 461 bus_dmamap_t tp_dmap; 462 struct mbuf *tp_m; 463 464 TAILQ_ENTRY(tht_pkt) tp_link; 465 }; 466 467 struct tht_pkt_list { 468 struct tht_pkt *tpl_pkts; 469 TAILQ_HEAD(, tht_pkt) tpl_free; 470 TAILQ_HEAD(, tht_pkt) tpl_used; 471 }; 472 473 struct tht_softc { 474 struct device sc_dev; 475 struct thtc_softc *sc_thtc; 476 int sc_port; 477 478 bus_space_handle_t sc_memh; 479 480 struct arpcom sc_ac; 481 struct ifmedia sc_media; 482 struct timeval sc_mediacheck; 483 484 u_int16_t sc_lladdr[3]; 485 486 struct tht_pkt_list sc_tx_list; 487 struct tht_pkt_list sc_rx_list; 488 489 struct tht_fifo sc_txt; 490 struct tht_fifo sc_rxf; 491 struct tht_fifo sc_rxd; 492 struct tht_fifo sc_txf; 493 494 u_int32_t sc_imr; 495 496 struct rwlock sc_lock; 497 }; 498 499 int tht_match(struct device *, void *, void *); 500 void tht_attach(struct device *, struct device *, void *); 501 void tht_mountroot(struct device *); 502 int tht_intr(void *); 503 504 struct cfattach tht_ca = { 505 sizeof(struct tht_softc), tht_match, tht_attach 506 }; 507 508 struct cfdriver tht_cd = { 509 NULL, "tht", DV_IFNET 510 }; 511 512 /* pkts */ 513 int tht_pkt_alloc(struct tht_softc *, 514 struct tht_pkt_list *, int, int); 515 void tht_pkt_free(struct tht_softc *, 516 struct tht_pkt_list *); 517 void tht_pkt_put(struct tht_pkt_list *, struct tht_pkt *); 518 struct tht_pkt *tht_pkt_get(struct tht_pkt_list *); 519 struct tht_pkt *tht_pkt_used(struct tht_pkt_list *); 520 521 /* fifos */ 522 523 struct tht_fifo_desc tht_txt_desc = { 524 THT_REG_TXT_CFG0(0), 525 THT_REG_TXT_CFG1(0), 526 THT_REG_TXT_RPTR(0), 527 THT_REG_TXT_WPTR(0), 528 THT_FIFO_SIZE_16k, 529 1 530 }; 531 532 struct tht_fifo_desc tht_rxf_desc = { 533 THT_REG_RXF_CFG0(0), 534 THT_REG_RXF_CFG1(0), 535 THT_REG_RXF_RPTR(0), 536 THT_REG_RXF_WPTR(0), 537 THT_FIFO_SIZE_16k, 538 1 539 }; 540 541 struct tht_fifo_desc tht_rxd_desc = { 542 THT_REG_RXD_CFG0(0), 543 THT_REG_RXD_CFG1(0), 544 THT_REG_RXD_RPTR(0), 545 THT_REG_RXD_WPTR(0), 546 THT_FIFO_SIZE_16k, 547 0 548 }; 549 550 struct tht_fifo_desc tht_txf_desc = { 551 THT_REG_TXF_CFG0(0), 552 THT_REG_TXF_CFG1(0), 553 THT_REG_TXF_RPTR(0), 554 THT_REG_TXF_WPTR(0), 555 THT_FIFO_SIZE_4k, 556 0 557 }; 558 559 int tht_fifo_alloc(struct tht_softc *, struct tht_fifo *, 560 struct tht_fifo_desc *); 561 void tht_fifo_free(struct tht_softc *, struct tht_fifo *); 562 563 size_t tht_fifo_readable(struct tht_softc *, 564 struct tht_fifo *); 565 size_t tht_fifo_writable(struct tht_softc *, 566 struct tht_fifo *); 567 void tht_fifo_pre(struct tht_softc *, 568 struct tht_fifo *); 569 void tht_fifo_read(struct tht_softc *, struct tht_fifo *, 570 void *, size_t); 571 void tht_fifo_write(struct tht_softc *, struct tht_fifo *, 572 void *, size_t); 573 void tht_fifo_write_dmap(struct tht_softc *, 574 struct tht_fifo *, bus_dmamap_t); 575 void tht_fifo_write_pad(struct tht_softc *, 576 struct tht_fifo *, int); 577 void tht_fifo_post(struct tht_softc *, 578 struct tht_fifo *); 579 580 /* port operations */ 581 void tht_lladdr_read(struct tht_softc *); 582 void tht_lladdr_write(struct tht_softc *); 583 int tht_sw_reset(struct tht_softc *); 584 int tht_fw_load(struct tht_softc *); 585 void tht_fw_tick(void *arg); 586 void tht_link_state(struct tht_softc *); 587 588 /* interface operations */ 589 int tht_ioctl(struct ifnet *, u_long, caddr_t); 590 void tht_watchdog(struct ifnet *); 591 void tht_start(struct ifnet *); 592 int tht_load_pkt(struct tht_softc *, struct tht_pkt *, 593 struct mbuf *); 594 void tht_txf(struct tht_softc *sc); 595 596 void tht_rxf_fill(struct tht_softc *, int); 597 void tht_rxf_drain(struct tht_softc *); 598 void tht_rxd(struct tht_softc *); 599 600 void tht_up(struct tht_softc *); 601 void tht_iff(struct tht_softc *); 602 void tht_down(struct tht_softc *); 603 604 /* ifmedia operations */ 605 int tht_media_change(struct ifnet *); 606 void tht_media_status(struct ifnet *, struct ifmediareq *); 607 608 /* wrapper around dma memory */ 609 struct tht_dmamem *tht_dmamem_alloc(struct tht_softc *, bus_size_t, 610 bus_size_t); 611 void tht_dmamem_free(struct tht_softc *, 612 struct tht_dmamem *); 613 614 /* bus space operations */ 615 u_int32_t tht_read(struct tht_softc *, bus_size_t); 616 void tht_write(struct tht_softc *, bus_size_t, u_int32_t); 617 void tht_write_region(struct tht_softc *, bus_size_t, 618 void *, size_t); 619 int tht_wait_eq(struct tht_softc *, bus_size_t, u_int32_t, 620 u_int32_t, int); 621 int tht_wait_ne(struct tht_softc *, bus_size_t, u_int32_t, 622 u_int32_t, int); 623 624 #define tht_set(_s, _r, _b) tht_write((_s), (_r), \ 625 tht_read((_s), (_r)) | (_b)) 626 #define tht_clr(_s, _r, _b) tht_write((_s), (_r), \ 627 tht_read((_s), (_r)) & ~(_b)) 628 #define tht_wait_set(_s, _r, _b, _t) tht_wait_eq((_s), (_r), \ 629 (_b), (_b), (_t)) 630 631 632 /* misc */ 633 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) 634 #define LWORDS(_b) (((_b) + 7) >> 3) 635 636 637 struct thtc_device { 638 pci_vendor_id_t td_vendor; 639 pci_vendor_id_t td_product; 640 u_int td_nports; 641 }; 642 643 const struct thtc_device *thtc_lookup(struct pci_attach_args *); 644 645 static const struct thtc_device thtc_devices[] = { 646 { PCI_VENDOR_TEHUTI, PCI_PRODUCT_TEHUTI_TN3009, 1 }, 647 { PCI_VENDOR_TEHUTI, PCI_PRODUCT_TEHUTI_TN3010, 1 }, 648 { PCI_VENDOR_TEHUTI, PCI_PRODUCT_TEHUTI_TN3014, 2 } 649 }; 650 651 const struct thtc_device * 652 thtc_lookup(struct pci_attach_args *pa) 653 { 654 int i; 655 const struct thtc_device *td; 656 657 for (i = 0; i < nitems(thtc_devices); i++) { 658 td = &thtc_devices[i]; 659 if (td->td_vendor == PCI_VENDOR(pa->pa_id) && 660 td->td_product == PCI_PRODUCT(pa->pa_id)) 661 return (td); 662 } 663 664 return (NULL); 665 } 666 667 int 668 thtc_match(struct device *parent, void *match, void *aux) 669 { 670 struct pci_attach_args *pa = aux; 671 672 if (thtc_lookup(pa) != NULL) 673 return (1); 674 675 return (0); 676 } 677 678 void 679 thtc_attach(struct device *parent, struct device *self, void *aux) 680 { 681 struct thtc_softc *sc = (struct thtc_softc *)self; 682 struct pci_attach_args *pa = aux; 683 pcireg_t memtype; 684 const struct thtc_device *td; 685 struct tht_attach_args taa; 686 pci_intr_handle_t ih; 687 int i; 688 689 bzero(&taa, sizeof(taa)); 690 td = thtc_lookup(pa); 691 692 sc->sc_dmat = pa->pa_dmat; 693 694 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, THT_PCI_BAR); 695 if (pci_mapreg_map(pa, THT_PCI_BAR, memtype, 0, &sc->sc_memt, 696 &sc->sc_memh, NULL, &sc->sc_mems, 0) != 0) { 697 printf(": unable to map host registers\n"); 698 return; 699 } 700 701 if (pci_intr_map(pa, &ih) != 0) { 702 printf(": unable to map interrupt\n"); 703 goto unmap; 704 } 705 706 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, 707 IPL_NET, tht_intr, sc, DEVNAME(sc)); 708 if (sc->sc_ih == NULL) { 709 printf(": unable to establish interrupt\n"); 710 return; 711 } 712 printf(": %s\n", pci_intr_string(pa->pa_pc, ih)); 713 714 taa.taa_pa = pa; 715 for (i = 0; i < td->td_nports; i++) { 716 taa.taa_port = i; 717 718 config_found(self, &taa, thtc_print); 719 } 720 721 return; 722 723 unmap: 724 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 725 sc->sc_mems = 0; 726 } 727 728 int 729 thtc_print(void *aux, const char *pnp) 730 { 731 struct tht_attach_args *taa = aux; 732 733 if (pnp != NULL) 734 printf("\"%s\" at %s", tht_cd.cd_name, pnp); 735 736 printf(" port %d", taa->taa_port); 737 738 return (UNCONF); 739 } 740 741 int 742 tht_match(struct device *parent, void *match, void *aux) 743 { 744 return (1); 745 } 746 747 void 748 tht_attach(struct device *parent, struct device *self, void *aux) 749 { 750 struct thtc_softc *csc = (struct thtc_softc *)parent; 751 struct tht_softc *sc = (struct tht_softc *)self; 752 struct tht_attach_args *taa = aux; 753 struct ifnet *ifp; 754 755 sc->sc_thtc = csc; 756 sc->sc_port = taa->taa_port; 757 sc->sc_imr = THT_IMR_DOWN(sc->sc_port); 758 rw_init(&sc->sc_lock, "thtioc"); 759 760 if (bus_space_subregion(csc->sc_memt, csc->sc_memh, 761 THT_PORT_REGION(sc->sc_port), THT_PORT_SIZE, 762 &sc->sc_memh) != 0) { 763 printf(": unable to map port registers\n"); 764 return; 765 } 766 767 if (tht_sw_reset(sc) != 0) { 768 printf(": unable to reset port\n"); 769 /* bus_space(9) says we dont have to free subregions */ 770 return; 771 } 772 773 tht_lladdr_read(sc); 774 bcopy(sc->sc_lladdr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 775 776 ifp = &sc->sc_ac.ac_if; 777 ifp->if_softc = sc; 778 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 779 ifp->if_capabilities = IFCAP_VLAN_MTU; 780 ifp->if_ioctl = tht_ioctl; 781 ifp->if_start = tht_start; 782 ifp->if_watchdog = tht_watchdog; 783 ifp->if_hardmtu = MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN; /* XXX */ 784 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 785 IFQ_SET_MAXLEN(&ifp->if_snd, 400); 786 787 ifmedia_init(&sc->sc_media, 0, tht_media_change, tht_media_status); 788 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_AUTO, 0, NULL); 789 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 790 791 if_attach(ifp); 792 ether_ifattach(ifp); 793 794 printf(": address %s\n", ether_sprintf(sc->sc_ac.ac_enaddr)); 795 796 config_mountroot(self, tht_mountroot); 797 } 798 799 void 800 tht_mountroot(struct device *self) 801 { 802 struct tht_softc *sc = (struct tht_softc *)self; 803 804 if (tht_fifo_alloc(sc, &sc->sc_txt, &tht_txt_desc) != 0) 805 return; 806 807 if (tht_fw_load(sc) != 0) 808 printf("%s: firmware load failed\n", DEVNAME(sc)); 809 810 tht_sw_reset(sc); 811 812 tht_fifo_free(sc, &sc->sc_txt); 813 814 tht_link_state(sc); 815 tht_write(sc, THT_REG_IMR, sc->sc_imr); 816 } 817 818 int 819 tht_intr(void *arg) 820 { 821 struct thtc_softc *thtc = arg; 822 struct tht_softc *sc = arg; 823 struct device *d; 824 struct ifnet *ifp; 825 u_int32_t isr; 826 int rv = 0; 827 828 for (d = TAILQ_NEXT(&thtc->sc_dev, dv_list); d != NULL; 829 d = TAILQ_NEXT(d, dv_list)) { 830 sc = (struct tht_softc *)d; 831 832 isr = tht_read(sc, THT_REG_ISR); 833 if (isr == 0x0) { 834 tht_write(sc, THT_REG_IMR, sc->sc_imr); 835 continue; 836 } 837 rv = 1; 838 839 DPRINTF(THT_D_INTR, "%s: isr: 0x%b\n", DEVNAME(sc), isr, THT_FMT_ISR); 840 841 if (ISSET(isr, THT_REG_ISR_LINKCHG(0) | THT_REG_ISR_LINKCHG(1))) 842 tht_link_state(sc); 843 844 ifp = &sc->sc_ac.ac_if; 845 if (ifp->if_flags & IFF_RUNNING) { 846 if (ISSET(isr, THT_REG_ISR_RXD(0))) 847 tht_rxd(sc); 848 849 if (ISSET(isr, THT_REG_ISR_RXF(0))) 850 tht_rxf_fill(sc, 0); 851 852 if (ISSET(isr, THT_REG_ISR_TXF(0))) 853 tht_txf(sc); 854 855 tht_start(ifp); 856 } 857 tht_write(sc, THT_REG_IMR, sc->sc_imr); 858 } 859 return (rv); 860 } 861 862 int 863 tht_ioctl(struct ifnet *ifp, u_long cmd, caddr_t addr) 864 { 865 struct tht_softc *sc = ifp->if_softc; 866 struct ifreq *ifr = (struct ifreq *)addr; 867 int s, error = 0; 868 869 rw_enter_write(&sc->sc_lock); 870 s = splnet(); 871 872 switch (cmd) { 873 case SIOCSIFADDR: 874 ifp->if_flags |= IFF_UP; 875 /* FALLTHROUGH */ 876 877 case SIOCSIFFLAGS: 878 if (ifp->if_flags & IFF_UP) { 879 if (ifp->if_flags & IFF_RUNNING) 880 error = ENETRESET; 881 else 882 tht_up(sc); 883 } else { 884 if (ifp->if_flags & IFF_RUNNING) 885 tht_down(sc); 886 } 887 break; 888 889 case SIOCGIFMEDIA: 890 case SIOCSIFMEDIA: 891 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 892 break; 893 894 default: 895 error = ether_ioctl(ifp, &sc->sc_ac, cmd, addr); 896 } 897 898 if (error == ENETRESET) { 899 if (ifp->if_flags & IFF_RUNNING) 900 tht_iff(sc); 901 error = 0; 902 } 903 904 splx(s); 905 rw_exit_write(&sc->sc_lock); 906 907 return (error); 908 } 909 910 void 911 tht_up(struct tht_softc *sc) 912 { 913 struct ifnet *ifp = &sc->sc_ac.ac_if; 914 915 if (ISSET(ifp->if_flags, IFF_RUNNING)) { 916 return; 917 } 918 919 if (tht_pkt_alloc(sc, &sc->sc_tx_list, THT_TXT_PKT_NUM, 920 THT_TXT_SGL_LEN) != 0) 921 return; 922 if (tht_pkt_alloc(sc, &sc->sc_rx_list, THT_RXF_PKT_NUM, 923 THT_RXF_SGL_LEN) != 0) 924 goto free_tx_list; 925 926 if (tht_fifo_alloc(sc, &sc->sc_txt, &tht_txt_desc) != 0) 927 goto free_rx_list; 928 if (tht_fifo_alloc(sc, &sc->sc_rxf, &tht_rxf_desc) != 0) 929 goto free_txt; 930 if (tht_fifo_alloc(sc, &sc->sc_rxd, &tht_rxd_desc) != 0) 931 goto free_rxf; 932 if (tht_fifo_alloc(sc, &sc->sc_txf, &tht_txf_desc) != 0) 933 goto free_rxd; 934 935 tht_write(sc, THT_REG_10G_FRM_LEN, MCLBYTES - ETHER_ALIGN); 936 tht_write(sc, THT_REG_10G_PAUSE, 0x96); 937 tht_write(sc, THT_REG_10G_RX_SEC, THT_REG_10G_SEC_AVAIL(0x10) | 938 THT_REG_10G_SEC_EMPTY(0x80)); 939 tht_write(sc, THT_REG_10G_TX_SEC, THT_REG_10G_SEC_AVAIL(0x10) | 940 THT_REG_10G_SEC_EMPTY(0xe0)); 941 tht_write(sc, THT_REG_10G_RFIFO_AEF, THT_REG_10G_FIFO_AE(0x0) | 942 THT_REG_10G_FIFO_AF(0x0)); 943 tht_write(sc, THT_REG_10G_TFIFO_AEF, THT_REG_10G_FIFO_AE(0x0) | 944 THT_REG_10G_FIFO_AF(0x0)); 945 tht_write(sc, THT_REG_10G_CTL, THT_REG_10G_CTL_TX_EN | 946 THT_REG_10G_CTL_RX_EN | THT_REG_10G_CTL_PAD | 947 THT_REG_10G_CTL_PROMISC); 948 949 tht_write(sc, THT_REG_VGLB, 0); 950 951 tht_write(sc, THT_REG_RX_MAX_FRAME, MCLBYTES - ETHER_ALIGN); 952 953 tht_write(sc, THT_REG_RDINTCM(0), THT_REG_RDINTCM_PKT_TH(12) | 954 THT_REG_RDINTCM_RXF_TH(4) | THT_REG_RDINTCM_COAL_RC | 955 THT_REG_RDINTCM_COAL(0x20)); 956 tht_write(sc, THT_REG_TDINTCM(0), THT_REG_TDINTCM_PKT_TH(12) | 957 THT_REG_TDINTCM_COAL_RC | THT_REG_TDINTCM_COAL(0x20)); 958 959 bcopy(sc->sc_ac.ac_enaddr, sc->sc_lladdr, ETHER_ADDR_LEN); 960 tht_lladdr_write(sc); 961 962 /* populate rxf fifo */ 963 tht_rxf_fill(sc, 1); 964 965 /* program promiscuous mode and multicast filters */ 966 tht_iff(sc); 967 968 ifp->if_flags |= IFF_RUNNING; 969 ifq_clr_oactive(&ifp->if_snd); 970 971 /* enable interrupts */ 972 sc->sc_imr = THT_IMR_UP(sc->sc_port); 973 tht_write(sc, THT_REG_IMR, sc->sc_imr); 974 975 return; 976 977 free_rxd: 978 tht_fifo_free(sc, &sc->sc_rxd); 979 free_rxf: 980 tht_fifo_free(sc, &sc->sc_rxf); 981 free_txt: 982 tht_fifo_free(sc, &sc->sc_txt); 983 984 tht_sw_reset(sc); 985 986 free_rx_list: 987 tht_pkt_free(sc, &sc->sc_rx_list); 988 free_tx_list: 989 tht_pkt_free(sc, &sc->sc_tx_list); 990 } 991 992 void 993 tht_iff(struct tht_softc *sc) 994 { 995 struct ifnet *ifp = &sc->sc_ac.ac_if; 996 struct ether_multi *enm; 997 struct ether_multistep step; 998 u_int32_t rxf; 999 u_int8_t imf[THT_REG_RX_MCST_HASH_SIZE]; 1000 u_int8_t hash; 1001 int i; 1002 1003 ifp->if_flags &= ~IFF_ALLMULTI; 1004 1005 rxf = THT_REG_RX_FLT_OSEN | THT_REG_RX_FLT_AM | THT_REG_RX_FLT_AB; 1006 for (i = 0; i < THT_REG_RX_MAC_MCST_CNT; i++) { 1007 tht_write(sc, THT_REG_RX_MAC_MCST0(i), 0); 1008 tht_write(sc, THT_REG_RX_MAC_MCST1(i), 0); 1009 } 1010 memset(imf, 0x00, sizeof(imf)); 1011 1012 if (ifp->if_flags & IFF_PROMISC) { 1013 ifp->if_flags |= IFF_ALLMULTI; 1014 rxf |= THT_REG_RX_FLT_PRM_ALL; 1015 } else if (sc->sc_ac.ac_multirangecnt > 0) { 1016 ifp->if_flags |= IFF_ALLMULTI; 1017 memset(imf, 0xff, sizeof(imf)); 1018 } else { 1019 ETHER_FIRST_MULTI(step, &sc->sc_ac, enm); 1020 1021 #if 0 1022 /* fill the perfect multicast filters */ 1023 for (i = 0; i < THT_REG_RX_MAC_MCST_CNT; i++) { 1024 if (enm == NULL) 1025 break; 1026 1027 tht_write(sc, THT_REG_RX_MAC_MCST0(i), 1028 (enm->enm_addrlo[0] << 0) | 1029 (enm->enm_addrlo[1] << 8) | 1030 (enm->enm_addrlo[2] << 16) | 1031 (enm->enm_addrlo[3] << 24)); 1032 tht_write(sc, THT_REG_RX_MAC_MCST1(i), 1033 (enm->enm_addrlo[4] << 0) | 1034 (enm->enm_addrlo[5] << 8)); 1035 1036 ETHER_NEXT_MULTI(step, enm); 1037 } 1038 #endif 1039 1040 /* fill the imperfect multicast filter with whats left */ 1041 while (enm != NULL) { 1042 hash = 0x00; 1043 for (i = 0; i < ETHER_ADDR_LEN; i++) 1044 hash ^= enm->enm_addrlo[i]; 1045 setbit(imf, hash); 1046 1047 ETHER_NEXT_MULTI(step, enm); 1048 } 1049 } 1050 1051 tht_write_region(sc, THT_REG_RX_MCST_HASH, imf, sizeof(imf)); 1052 tht_write(sc, THT_REG_RX_FLT, rxf); 1053 } 1054 1055 void 1056 tht_down(struct tht_softc *sc) 1057 { 1058 struct ifnet *ifp = &sc->sc_ac.ac_if; 1059 1060 if (!ISSET(ifp->if_flags, IFF_RUNNING)) { 1061 return; 1062 } 1063 1064 ifp->if_flags &= ~(IFF_RUNNING | IFF_ALLMULTI); 1065 ifq_clr_oactive(&ifp->if_snd); 1066 1067 while (tht_fifo_writable(sc, &sc->sc_txt) < sc->sc_txt.tf_len && 1068 tht_fifo_readable(sc, &sc->sc_txf) > 0) 1069 tsleep(sc, 0, "thtdown", hz); 1070 1071 sc->sc_imr = THT_IMR_DOWN(sc->sc_port); 1072 tht_write(sc, THT_REG_IMR, sc->sc_imr); 1073 1074 tht_sw_reset(sc); 1075 1076 tht_fifo_free(sc, &sc->sc_txf); 1077 tht_fifo_free(sc, &sc->sc_rxd); 1078 tht_fifo_free(sc, &sc->sc_rxf); 1079 tht_fifo_free(sc, &sc->sc_txt); 1080 1081 /* free mbufs that were on the rxf fifo */ 1082 tht_rxf_drain(sc); 1083 1084 tht_pkt_free(sc, &sc->sc_rx_list); 1085 tht_pkt_free(sc, &sc->sc_tx_list); 1086 } 1087 1088 void 1089 tht_start(struct ifnet *ifp) 1090 { 1091 struct tht_softc *sc = ifp->if_softc; 1092 struct tht_pkt *pkt; 1093 struct tht_tx_task txt; 1094 u_int32_t flags; 1095 struct mbuf *m; 1096 int bc; 1097 1098 if (!(ifp->if_flags & IFF_RUNNING)) 1099 return; 1100 if (ifq_is_oactive(&ifp->if_snd)) 1101 return; 1102 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1103 return; 1104 1105 if (tht_fifo_writable(sc, &sc->sc_txt) <= THT_FIFO_DESC_LEN) 1106 return; 1107 1108 bzero(&txt, sizeof(txt)); 1109 1110 tht_fifo_pre(sc, &sc->sc_txt); 1111 1112 do { 1113 m = ifq_deq_begin(&ifp->if_snd); 1114 if (m == NULL) 1115 break; 1116 1117 pkt = tht_pkt_get(&sc->sc_tx_list); 1118 if (pkt == NULL) { 1119 ifq_deq_rollback(&ifp->if_snd, m); 1120 ifq_set_oactive(&ifp->if_snd); 1121 break; 1122 } 1123 1124 ifq_deq_commit(&ifp->if_snd, m); 1125 if (tht_load_pkt(sc, pkt, m) != 0) { 1126 m_freem(m); 1127 tht_pkt_put(&sc->sc_tx_list, pkt); 1128 ifp->if_oerrors++; 1129 break; 1130 } 1131 /* thou shalt not use m after this point, only pkt->tp_m */ 1132 1133 #if NBPFILTER > 0 1134 if (ifp->if_bpf) 1135 bpf_mtap(ifp->if_bpf, pkt->tp_m, BPF_DIRECTION_OUT); 1136 #endif 1137 1138 bc = sizeof(txt) + 1139 sizeof(struct tht_pbd) * pkt->tp_dmap->dm_nsegs; 1140 1141 flags = THT_TXT_TYPE | LWORDS(bc); 1142 txt.flags = htole32(flags); 1143 txt.len = htole16(pkt->tp_m->m_pkthdr.len); 1144 txt.uid = pkt->tp_id; 1145 1146 DPRINTF(THT_D_TX, "%s: txt uid 0x%llx flags 0x%08x len %d\n", 1147 DEVNAME(sc), pkt->tp_id, flags, pkt->tp_m->m_pkthdr.len); 1148 1149 tht_fifo_write(sc, &sc->sc_txt, &txt, sizeof(txt)); 1150 tht_fifo_write_dmap(sc, &sc->sc_txt, pkt->tp_dmap); 1151 tht_fifo_write_pad(sc, &sc->sc_txt, bc); 1152 1153 bus_dmamap_sync(sc->sc_thtc->sc_dmat, pkt->tp_dmap, 0, 1154 pkt->tp_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1155 1156 ifp->if_opackets++; 1157 1158 } while (sc->sc_txt.tf_ready > THT_FIFO_DESC_LEN); 1159 1160 tht_fifo_post(sc, &sc->sc_txt); 1161 } 1162 1163 int 1164 tht_load_pkt(struct tht_softc *sc, struct tht_pkt *pkt, struct mbuf *m) 1165 { 1166 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1167 bus_dmamap_t dmap = pkt->tp_dmap; 1168 struct mbuf *m0 = NULL; 1169 1170 switch(bus_dmamap_load_mbuf(dmat, dmap, m, BUS_DMA_NOWAIT)) { 1171 case 0: 1172 pkt->tp_m = m; 1173 break; 1174 1175 case EFBIG: /* mbuf chain is too fragmented */ 1176 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1177 if (m0 == NULL) 1178 return (ENOBUFS); 1179 if (m->m_pkthdr.len > MHLEN) { 1180 MCLGET(m0, M_DONTWAIT); 1181 if (!(m0->m_flags & M_EXT)) { 1182 m_freem(m0); 1183 return (ENOBUFS); 1184 } 1185 } 1186 m_copydata(m, 0, m->m_pkthdr.len, mtod(m0, caddr_t)); 1187 m0->m_pkthdr.len = m0->m_len = m->m_pkthdr.len; 1188 if (bus_dmamap_load_mbuf(dmat, dmap, m0, BUS_DMA_NOWAIT)) { 1189 m_freem(m0); 1190 return (ENOBUFS); 1191 } 1192 1193 m_freem(m); 1194 pkt->tp_m = m0; 1195 break; 1196 1197 default: 1198 return (ENOBUFS); 1199 } 1200 1201 return (0); 1202 } 1203 1204 void 1205 tht_txf(struct tht_softc *sc) 1206 { 1207 struct ifnet *ifp = &sc->sc_ac.ac_if; 1208 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1209 bus_dmamap_t dmap; 1210 struct tht_tx_free txf; 1211 struct tht_pkt *pkt; 1212 1213 if (tht_fifo_readable(sc, &sc->sc_txf) < sizeof(txf)) 1214 return; 1215 1216 tht_fifo_pre(sc, &sc->sc_txf); 1217 1218 do { 1219 tht_fifo_read(sc, &sc->sc_txf, &txf, sizeof(txf)); 1220 1221 DPRINTF(THT_D_TX, "%s: txf uid 0x%llx\n", DEVNAME(sc), txf.uid); 1222 1223 pkt = &sc->sc_tx_list.tpl_pkts[txf.uid]; 1224 dmap = pkt->tp_dmap; 1225 1226 bus_dmamap_sync(dmat, dmap, 0, dmap->dm_mapsize, 1227 BUS_DMASYNC_POSTWRITE); 1228 bus_dmamap_unload(dmat, dmap); 1229 1230 m_freem(pkt->tp_m); 1231 1232 tht_pkt_put(&sc->sc_tx_list, pkt); 1233 1234 } while (sc->sc_txf.tf_ready >= sizeof(txf)); 1235 1236 ifq_clr_oactive(&ifp->if_snd); 1237 1238 tht_fifo_post(sc, &sc->sc_txf); 1239 } 1240 1241 void 1242 tht_rxf_fill(struct tht_softc *sc, int wait) 1243 { 1244 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1245 bus_dmamap_t dmap; 1246 struct tht_rx_free rxf; 1247 struct tht_pkt *pkt; 1248 struct mbuf *m; 1249 int bc; 1250 1251 if (tht_fifo_writable(sc, &sc->sc_rxf) <= THT_FIFO_DESC_LEN) 1252 return; 1253 1254 tht_fifo_pre(sc, &sc->sc_rxf); 1255 1256 for (;;) { 1257 if ((pkt = tht_pkt_get(&sc->sc_rx_list)) == NULL) 1258 goto done; 1259 1260 MGETHDR(m, wait ? M_WAIT : M_DONTWAIT, MT_DATA); 1261 if (m == NULL) 1262 goto put_pkt; 1263 1264 MCLGET(m, wait ? M_WAIT : M_DONTWAIT); 1265 if (!ISSET(m->m_flags, M_EXT)) 1266 goto free_m; 1267 1268 m->m_data += ETHER_ALIGN; 1269 m->m_len = m->m_pkthdr.len = MCLBYTES - ETHER_ALIGN; 1270 1271 dmap = pkt->tp_dmap; 1272 if (bus_dmamap_load_mbuf(dmat, dmap, m, 1273 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT) != 0) 1274 goto free_m; 1275 1276 pkt->tp_m = m; 1277 1278 bc = sizeof(rxf) + sizeof(struct tht_pbd) * dmap->dm_nsegs; 1279 1280 rxf.bc = htole16(LWORDS(bc)); 1281 rxf.type = htole16(THT_RXF_TYPE); 1282 rxf.uid = pkt->tp_id; 1283 1284 tht_fifo_write(sc, &sc->sc_rxf, &rxf, sizeof(rxf)); 1285 tht_fifo_write_dmap(sc, &sc->sc_rxf, dmap); 1286 tht_fifo_write_pad(sc, &sc->sc_rxf, bc); 1287 1288 bus_dmamap_sync(dmat, dmap, 0, dmap->dm_mapsize, 1289 BUS_DMASYNC_PREREAD); 1290 1291 if (sc->sc_rxf.tf_ready <= THT_FIFO_DESC_LEN) 1292 goto done; 1293 } 1294 1295 free_m: 1296 m_freem(m); 1297 put_pkt: 1298 tht_pkt_put(&sc->sc_rx_list, pkt); 1299 done: 1300 tht_fifo_post(sc, &sc->sc_rxf); 1301 } 1302 1303 void 1304 tht_rxf_drain(struct tht_softc *sc) 1305 { 1306 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1307 bus_dmamap_t dmap; 1308 struct tht_pkt *pkt; 1309 1310 while ((pkt = tht_pkt_used(&sc->sc_rx_list)) != NULL) { 1311 dmap = pkt->tp_dmap; 1312 1313 bus_dmamap_sync(dmat, dmap, 0, dmap->dm_mapsize, 1314 BUS_DMASYNC_POSTREAD); 1315 bus_dmamap_unload(dmat, dmap); 1316 1317 m_freem(pkt->tp_m); 1318 1319 tht_pkt_put(&sc->sc_rx_list, pkt); 1320 } 1321 } 1322 1323 void 1324 tht_rxd(struct tht_softc *sc) 1325 { 1326 struct ifnet *ifp = &sc->sc_ac.ac_if; 1327 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1328 bus_dmamap_t dmap; 1329 struct tht_rx_desc rxd; 1330 struct tht_pkt *pkt; 1331 struct mbuf *m; 1332 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1333 int bc; 1334 u_int32_t flags; 1335 1336 if (tht_fifo_readable(sc, &sc->sc_rxd) < sizeof(rxd)) 1337 return; 1338 1339 tht_fifo_pre(sc, &sc->sc_rxd); 1340 1341 do { 1342 tht_fifo_read(sc, &sc->sc_rxd, &rxd, sizeof(rxd)); 1343 1344 flags = letoh32(rxd.flags); 1345 bc = THT_RXD_FLAGS_BC(flags) * 8; 1346 bc -= sizeof(rxd); 1347 pkt = &sc->sc_rx_list.tpl_pkts[rxd.uid]; 1348 1349 dmap = pkt->tp_dmap; 1350 1351 bus_dmamap_sync(dmat, dmap, 0, dmap->dm_mapsize, 1352 BUS_DMASYNC_POSTREAD); 1353 bus_dmamap_unload(dmat, dmap); 1354 1355 m = pkt->tp_m; 1356 m->m_pkthdr.len = m->m_len = letoh16(rxd.len); 1357 1358 /* XXX process type 3 rx descriptors */ 1359 1360 ml_enqueue(&ml, m); 1361 1362 tht_pkt_put(&sc->sc_rx_list, pkt); 1363 1364 while (bc > 0) { 1365 static u_int32_t pad; 1366 1367 tht_fifo_read(sc, &sc->sc_rxd, &pad, sizeof(pad)); 1368 bc -= sizeof(pad); 1369 } 1370 } while (sc->sc_rxd.tf_ready >= sizeof(rxd)); 1371 1372 tht_fifo_post(sc, &sc->sc_rxd); 1373 1374 if_input(ifp, &ml); 1375 1376 /* put more pkts on the fifo */ 1377 tht_rxf_fill(sc, 0); 1378 } 1379 1380 void 1381 tht_watchdog(struct ifnet *ifp) 1382 { 1383 /* do nothing */ 1384 } 1385 1386 int 1387 tht_media_change(struct ifnet *ifp) 1388 { 1389 /* ignore */ 1390 return (0); 1391 } 1392 1393 void 1394 tht_media_status(struct ifnet *ifp, struct ifmediareq *imr) 1395 { 1396 struct tht_softc *sc = ifp->if_softc; 1397 1398 imr->ifm_active = IFM_ETHER | IFM_AUTO; 1399 imr->ifm_status = IFM_AVALID; 1400 1401 tht_link_state(sc); 1402 1403 if (LINK_STATE_IS_UP(ifp->if_link_state)) 1404 imr->ifm_status |= IFM_ACTIVE; 1405 } 1406 1407 int 1408 tht_fifo_alloc(struct tht_softc *sc, struct tht_fifo *tf, 1409 struct tht_fifo_desc *tfd) 1410 { 1411 u_int64_t dva; 1412 1413 tf->tf_len = THT_FIFO_SIZE(tfd->tfd_size); 1414 tf->tf_mem = tht_dmamem_alloc(sc, tf->tf_len, THT_FIFO_ALIGN); 1415 if (tf->tf_mem == NULL) 1416 return (1); 1417 1418 tf->tf_desc = tfd; 1419 tf->tf_rptr = tf->tf_wptr = 0; 1420 1421 bus_dmamap_sync(sc->sc_thtc->sc_dmat, THT_DMA_MAP(tf->tf_mem), 1422 0, tf->tf_len, THT_FIFO_PRE_SYNC(tfd)); 1423 1424 dva = THT_DMA_DVA(tf->tf_mem); 1425 tht_write(sc, tfd->tfd_cfg0, (u_int32_t)dva | tfd->tfd_size); 1426 tht_write(sc, tfd->tfd_cfg1, (u_int32_t)(dva >> 32)); 1427 1428 return (0); 1429 } 1430 1431 void 1432 tht_fifo_free(struct tht_softc *sc, struct tht_fifo *tf) 1433 { 1434 bus_dmamap_sync(sc->sc_thtc->sc_dmat, THT_DMA_MAP(tf->tf_mem), 1435 0, tf->tf_len, THT_FIFO_POST_SYNC(tf->tf_desc)); 1436 tht_dmamem_free(sc, tf->tf_mem); 1437 } 1438 1439 size_t 1440 tht_fifo_readable(struct tht_softc *sc, struct tht_fifo *tf) 1441 { 1442 tf->tf_wptr = tht_read(sc, tf->tf_desc->tfd_wptr); 1443 tf->tf_wptr &= THT_FIFO_PTR_MASK; 1444 tf->tf_ready = tf->tf_wptr - tf->tf_rptr; 1445 if (tf->tf_ready < 0) 1446 tf->tf_ready += tf->tf_len; 1447 1448 DPRINTF(THT_D_FIFO, "%s: fifo rdable wptr: %d rptr: %d ready: %d\n", 1449 DEVNAME(sc), tf->tf_wptr, tf->tf_rptr, tf->tf_ready); 1450 1451 return (tf->tf_ready); 1452 } 1453 1454 size_t 1455 tht_fifo_writable(struct tht_softc *sc, struct tht_fifo *tf) 1456 { 1457 tf->tf_rptr = tht_read(sc, tf->tf_desc->tfd_rptr); 1458 tf->tf_rptr &= THT_FIFO_PTR_MASK; 1459 tf->tf_ready = tf->tf_rptr - tf->tf_wptr; 1460 if (tf->tf_ready <= 0) 1461 tf->tf_ready += tf->tf_len; 1462 1463 DPRINTF(THT_D_FIFO, "%s: fifo wrable wptr: %d rptr: %d ready: %d\n", 1464 DEVNAME(sc), tf->tf_wptr, tf->tf_rptr, tf->tf_ready); 1465 1466 return (tf->tf_ready); 1467 } 1468 1469 void 1470 tht_fifo_pre(struct tht_softc *sc, struct tht_fifo *tf) 1471 { 1472 bus_dmamap_sync(sc->sc_thtc->sc_dmat, THT_DMA_MAP(tf->tf_mem), 1473 0, tf->tf_len, THT_FIFO_POST_SYNC(tf->tf_desc)); 1474 } 1475 1476 void 1477 tht_fifo_read(struct tht_softc *sc, struct tht_fifo *tf, 1478 void *buf, size_t buflen) 1479 { 1480 u_int8_t *fifo = THT_DMA_KVA(tf->tf_mem); 1481 u_int8_t *desc = buf; 1482 size_t len; 1483 1484 tf->tf_ready -= buflen; 1485 1486 len = tf->tf_len - tf->tf_rptr; 1487 1488 if (len < buflen) { 1489 memcpy(desc, fifo + tf->tf_rptr, len); 1490 1491 buflen -= len; 1492 desc += len; 1493 1494 tf->tf_rptr = 0; 1495 } 1496 1497 memcpy(desc, fifo + tf->tf_rptr, buflen); 1498 tf->tf_rptr += buflen; 1499 1500 DPRINTF(THT_D_FIFO, "%s: fifo rd wptr: %d rptr: %d ready: %d\n", 1501 DEVNAME(sc), tf->tf_wptr, tf->tf_rptr, tf->tf_ready); 1502 } 1503 1504 void 1505 tht_fifo_write(struct tht_softc *sc, struct tht_fifo *tf, 1506 void *buf, size_t buflen) 1507 { 1508 u_int8_t *fifo = THT_DMA_KVA(tf->tf_mem); 1509 u_int8_t *desc = buf; 1510 size_t len; 1511 1512 tf->tf_ready -= buflen; 1513 1514 len = tf->tf_len - tf->tf_wptr; 1515 1516 if (len < buflen) { 1517 memcpy(fifo + tf->tf_wptr, desc, len); 1518 1519 buflen -= len; 1520 desc += len; 1521 1522 tf->tf_wptr = 0; 1523 } 1524 1525 memcpy(fifo + tf->tf_wptr, desc, buflen); 1526 tf->tf_wptr += buflen; 1527 tf->tf_wptr %= tf->tf_len; 1528 1529 DPRINTF(THT_D_FIFO, "%s: fifo wr wptr: %d rptr: %d ready: %d\n", 1530 DEVNAME(sc), tf->tf_wptr, tf->tf_rptr, tf->tf_ready); 1531 } 1532 1533 void 1534 tht_fifo_write_dmap(struct tht_softc *sc, struct tht_fifo *tf, 1535 bus_dmamap_t dmap) 1536 { 1537 struct tht_pbd pbd; 1538 u_int64_t dva; 1539 int i; 1540 1541 for (i = 0; i < dmap->dm_nsegs; i++) { 1542 dva = dmap->dm_segs[i].ds_addr; 1543 1544 pbd.addr_lo = htole32(dva); 1545 pbd.addr_hi = htole32(dva >> 32); 1546 pbd.len = htole32(dmap->dm_segs[i].ds_len); 1547 1548 tht_fifo_write(sc, tf, &pbd, sizeof(pbd)); 1549 } 1550 } 1551 1552 void 1553 tht_fifo_write_pad(struct tht_softc *sc, struct tht_fifo *tf, int bc) 1554 { 1555 const static u_int32_t pad = 0x0; 1556 1557 /* this assumes you'll only ever be writing multiples of 4 bytes */ 1558 if (bc % 8) 1559 tht_fifo_write(sc, tf, (void *)&pad, sizeof(pad)); 1560 } 1561 1562 void 1563 tht_fifo_post(struct tht_softc *sc, struct tht_fifo *tf) 1564 { 1565 bus_dmamap_sync(sc->sc_thtc->sc_dmat, THT_DMA_MAP(tf->tf_mem), 1566 0, tf->tf_len, THT_FIFO_PRE_SYNC(tf->tf_desc)); 1567 if (tf->tf_desc->tfd_write) 1568 tht_write(sc, tf->tf_desc->tfd_wptr, tf->tf_wptr); 1569 else 1570 tht_write(sc, tf->tf_desc->tfd_rptr, tf->tf_rptr); 1571 1572 DPRINTF(THT_D_FIFO, "%s: fifo post wptr: %d rptr: %d\n", DEVNAME(sc), 1573 tf->tf_wptr, tf->tf_rptr); 1574 } 1575 1576 const static bus_size_t tht_mac_regs[3] = { 1577 THT_REG_RX_UNC_MAC2, THT_REG_RX_UNC_MAC1, THT_REG_RX_UNC_MAC0 1578 }; 1579 1580 void 1581 tht_lladdr_read(struct tht_softc *sc) 1582 { 1583 int i; 1584 1585 for (i = 0; i < nitems(tht_mac_regs); i++) 1586 sc->sc_lladdr[i] = betoh16(tht_read(sc, tht_mac_regs[i])); 1587 } 1588 1589 void 1590 tht_lladdr_write(struct tht_softc *sc) 1591 { 1592 int i; 1593 1594 for (i = 0; i < nitems(tht_mac_regs); i++) 1595 tht_write(sc, tht_mac_regs[i], htobe16(sc->sc_lladdr[i])); 1596 } 1597 1598 #define tht_swrst_set(_s, _r) tht_write((_s), (_r), 0x1) 1599 #define tht_swrst_clr(_s, _r) tht_write((_s), (_r), 0x0) 1600 int 1601 tht_sw_reset(struct tht_softc *sc) 1602 { 1603 int i; 1604 1605 /* this follows SW Reset process in 8.8 of the doco */ 1606 1607 /* 1. disable rx */ 1608 tht_clr(sc, THT_REG_RX_FLT, THT_REG_RX_FLT_OSEN); 1609 1610 /* 2. initiate port disable */ 1611 tht_swrst_set(sc, THT_REG_DIS_PRT); 1612 1613 /* 3. initiate queue disable */ 1614 tht_swrst_set(sc, THT_REG_DIS_QU_0); 1615 tht_swrst_set(sc, THT_REG_DIS_QU_1); 1616 1617 /* 4. wait for successful finish of previous tasks */ 1618 if (!tht_wait_set(sc, THT_REG_RST_PRT, THT_REG_RST_PRT_ACTIVE, 1000)) 1619 return (1); 1620 1621 /* 5. Reset interrupt registers */ 1622 tht_write(sc, THT_REG_IMR, 0x0); /* 5.a */ 1623 tht_read(sc, THT_REG_ISR); /* 5.b */ 1624 for (i = 0; i < THT_NQUEUES; i++) { 1625 tht_write(sc, THT_REG_RDINTCM(i), 0x0); /* 5.c/5.d */ 1626 tht_write(sc, THT_REG_TDINTCM(i), 0x0); /* 5.e */ 1627 } 1628 1629 /* 6. initiate queue reset */ 1630 tht_swrst_set(sc, THT_REG_RST_QU_0); 1631 tht_swrst_set(sc, THT_REG_RST_QU_1); 1632 1633 /* 7. initiate port reset */ 1634 tht_swrst_set(sc, THT_REG_RST_PRT); 1635 1636 /* 8. clear txt/rxf/rxd/txf read and write ptrs */ 1637 for (i = 0; i < THT_NQUEUES; i++) { 1638 tht_write(sc, THT_REG_TXT_RPTR(i), 0); 1639 tht_write(sc, THT_REG_RXF_RPTR(i), 0); 1640 tht_write(sc, THT_REG_RXD_RPTR(i), 0); 1641 tht_write(sc, THT_REG_TXF_RPTR(i), 0); 1642 1643 tht_write(sc, THT_REG_TXT_WPTR(i), 0); 1644 tht_write(sc, THT_REG_RXF_WPTR(i), 0); 1645 tht_write(sc, THT_REG_RXD_WPTR(i), 0); 1646 tht_write(sc, THT_REG_TXF_WPTR(i), 0); 1647 } 1648 1649 /* 9. unset port disable */ 1650 tht_swrst_clr(sc, THT_REG_DIS_PRT); 1651 1652 /* 10. unset queue disable */ 1653 tht_swrst_clr(sc, THT_REG_DIS_QU_0); 1654 tht_swrst_clr(sc, THT_REG_DIS_QU_1); 1655 1656 /* 11. unset queue reset */ 1657 tht_swrst_clr(sc, THT_REG_RST_QU_0); 1658 tht_swrst_clr(sc, THT_REG_RST_QU_1); 1659 1660 /* 12. unset port reset */ 1661 tht_swrst_clr(sc, THT_REG_RST_PRT); 1662 1663 /* 13. enable rx */ 1664 tht_set(sc, THT_REG_RX_FLT, THT_REG_RX_FLT_OSEN); 1665 1666 return (0); 1667 } 1668 1669 int 1670 tht_fw_load(struct tht_softc *sc) 1671 { 1672 struct timeout ticker; 1673 volatile int ok = 1; 1674 u_int8_t *fw, *buf; 1675 size_t fwlen, wrlen; 1676 int error = 1; 1677 1678 if (loadfirmware("tht", &fw, &fwlen) != 0) 1679 return (1); 1680 1681 if ((fwlen % 8) != 0) 1682 goto err; 1683 1684 buf = fw; 1685 while (fwlen > 0) { 1686 while (tht_fifo_writable(sc, &sc->sc_txt) <= THT_FIFO_GAP) { 1687 if (tsleep(sc, PCATCH, "thtfw", 1) == EINTR) 1688 goto err; 1689 } 1690 1691 wrlen = MIN(sc->sc_txt.tf_ready - THT_FIFO_GAP, fwlen); 1692 tht_fifo_pre(sc, &sc->sc_txt); 1693 tht_fifo_write(sc, &sc->sc_txt, buf, wrlen); 1694 tht_fifo_post(sc, &sc->sc_txt); 1695 1696 fwlen -= wrlen; 1697 buf += wrlen; 1698 } 1699 1700 timeout_set(&ticker, tht_fw_tick, (void *)&ok); 1701 timeout_add_sec(&ticker, 2); 1702 while (ok) { 1703 if (tht_read(sc, THT_REG_INIT_STATUS) != 0) { 1704 error = 0; 1705 break; 1706 } 1707 1708 if (tsleep(sc, PCATCH, "thtinit", 1) == EINTR) 1709 goto err; 1710 } 1711 timeout_del(&ticker); 1712 1713 tht_write(sc, THT_REG_INIT_SEMAPHORE, 0x1); 1714 1715 err: 1716 free(fw, M_DEVBUF, fwlen); 1717 return (error); 1718 } 1719 1720 void 1721 tht_fw_tick(void *arg) 1722 { 1723 volatile int *ok = arg; 1724 1725 *ok = 0; 1726 } 1727 1728 void 1729 tht_link_state(struct tht_softc *sc) 1730 { 1731 static const struct timeval interval = { 0, 10000 }; 1732 struct ifnet *ifp = &sc->sc_ac.ac_if; 1733 int link_state = LINK_STATE_DOWN; 1734 1735 if (!ratecheck(&sc->sc_mediacheck, &interval)) 1736 return; 1737 1738 if (tht_read(sc, THT_REG_MAC_LNK_STAT) & THT_REG_MAC_LNK_STAT_LINK) 1739 link_state = LINK_STATE_FULL_DUPLEX; 1740 1741 if (ifp->if_link_state != link_state) { 1742 ifp->if_link_state = link_state; 1743 if_link_state_change(ifp); 1744 } 1745 1746 if (LINK_STATE_IS_UP(ifp->if_link_state)) 1747 ifp->if_baudrate = IF_Gbps(10); 1748 else 1749 ifp->if_baudrate = 0; 1750 } 1751 1752 u_int32_t 1753 tht_read(struct tht_softc *sc, bus_size_t r) 1754 { 1755 bus_space_barrier(sc->sc_thtc->sc_memt, sc->sc_memh, r, 4, 1756 BUS_SPACE_BARRIER_READ); 1757 return (bus_space_read_4(sc->sc_thtc->sc_memt, sc->sc_memh, r)); 1758 } 1759 1760 void 1761 tht_write(struct tht_softc *sc, bus_size_t r, u_int32_t v) 1762 { 1763 bus_space_write_4(sc->sc_thtc->sc_memt, sc->sc_memh, r, v); 1764 bus_space_barrier(sc->sc_thtc->sc_memt, sc->sc_memh, r, 4, 1765 BUS_SPACE_BARRIER_WRITE); 1766 } 1767 1768 void 1769 tht_write_region(struct tht_softc *sc, bus_size_t r, void *buf, size_t len) 1770 { 1771 bus_space_write_raw_region_4(sc->sc_thtc->sc_memt, sc->sc_memh, r, 1772 buf, len); 1773 bus_space_barrier(sc->sc_thtc->sc_memt, sc->sc_memh, r, len, 1774 BUS_SPACE_BARRIER_WRITE); 1775 } 1776 1777 int 1778 tht_wait_eq(struct tht_softc *sc, bus_size_t r, u_int32_t m, u_int32_t v, 1779 int timeout) 1780 { 1781 while ((tht_read(sc, r) & m) != v) { 1782 if (timeout == 0) 1783 return (0); 1784 1785 delay(1000); 1786 timeout--; 1787 } 1788 1789 return (1); 1790 } 1791 1792 int 1793 tht_wait_ne(struct tht_softc *sc, bus_size_t r, u_int32_t m, u_int32_t v, 1794 int timeout) 1795 { 1796 while ((tht_read(sc, r) & m) == v) { 1797 if (timeout == 0) 1798 return (0); 1799 1800 delay(1000); 1801 timeout--; 1802 } 1803 1804 return (1); 1805 } 1806 1807 struct tht_dmamem * 1808 tht_dmamem_alloc(struct tht_softc *sc, bus_size_t size, bus_size_t align) 1809 { 1810 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1811 struct tht_dmamem *tdm; 1812 int nsegs; 1813 1814 tdm = malloc(sizeof(struct tht_dmamem), M_DEVBUF, M_WAITOK | M_ZERO); 1815 tdm->tdm_size = size; 1816 1817 if (bus_dmamap_create(dmat, size, 1, size, 0, 1818 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &tdm->tdm_map) != 0) 1819 goto tdmfree; 1820 1821 if (bus_dmamem_alloc(dmat, size, align, 0, &tdm->tdm_seg, 1, &nsegs, 1822 BUS_DMA_WAITOK | BUS_DMA_ZERO) != 0) 1823 goto destroy; 1824 1825 if (bus_dmamem_map(dmat, &tdm->tdm_seg, nsegs, size, &tdm->tdm_kva, 1826 BUS_DMA_WAITOK) != 0) 1827 goto free; 1828 1829 if (bus_dmamap_load(dmat, tdm->tdm_map, tdm->tdm_kva, size, 1830 NULL, BUS_DMA_WAITOK) != 0) 1831 goto unmap; 1832 1833 return (tdm); 1834 1835 unmap: 1836 bus_dmamem_unmap(dmat, tdm->tdm_kva, size); 1837 free: 1838 bus_dmamem_free(dmat, &tdm->tdm_seg, 1); 1839 destroy: 1840 bus_dmamap_destroy(dmat, tdm->tdm_map); 1841 tdmfree: 1842 free(tdm, M_DEVBUF, 0); 1843 1844 return (NULL); 1845 } 1846 1847 void 1848 tht_dmamem_free(struct tht_softc *sc, struct tht_dmamem *tdm) 1849 { 1850 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1851 1852 bus_dmamap_unload(dmat, tdm->tdm_map); 1853 bus_dmamem_unmap(dmat, tdm->tdm_kva, tdm->tdm_size); 1854 bus_dmamem_free(dmat, &tdm->tdm_seg, 1); 1855 bus_dmamap_destroy(dmat, tdm->tdm_map); 1856 free(tdm, M_DEVBUF, 0); 1857 } 1858 1859 int 1860 tht_pkt_alloc(struct tht_softc *sc, struct tht_pkt_list *tpl, int npkts, 1861 int nsegs) 1862 { 1863 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1864 struct tht_pkt *pkt; 1865 int i; 1866 1867 tpl->tpl_pkts = mallocarray(npkts, sizeof(struct tht_pkt), 1868 M_DEVBUF, M_WAITOK | M_ZERO); 1869 1870 TAILQ_INIT(&tpl->tpl_free); 1871 TAILQ_INIT(&tpl->tpl_used); 1872 for (i = 0; i < npkts; i++) { 1873 pkt = &tpl->tpl_pkts[i]; 1874 1875 pkt->tp_id = i; 1876 if (bus_dmamap_create(dmat, THT_PBD_PKTLEN, nsegs, 1877 THT_PBD_PKTLEN, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1878 &pkt->tp_dmap) != 0) { 1879 tht_pkt_free(sc, tpl); 1880 return (1); 1881 } 1882 1883 TAILQ_INSERT_TAIL(&tpl->tpl_free, pkt, tp_link); 1884 } 1885 1886 return (0); 1887 } 1888 1889 void 1890 tht_pkt_free(struct tht_softc *sc, struct tht_pkt_list *tpl) 1891 { 1892 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1893 struct tht_pkt *pkt; 1894 1895 while ((pkt = tht_pkt_get(tpl)) != NULL) 1896 bus_dmamap_destroy(dmat, pkt->tp_dmap); 1897 free(tpl->tpl_pkts, M_DEVBUF, 0); 1898 tpl->tpl_pkts = NULL; 1899 } 1900 1901 void 1902 tht_pkt_put(struct tht_pkt_list *tpl, struct tht_pkt *pkt) 1903 { 1904 TAILQ_REMOVE(&tpl->tpl_used, pkt, tp_link); 1905 TAILQ_INSERT_TAIL(&tpl->tpl_free, pkt, tp_link); 1906 } 1907 1908 struct tht_pkt * 1909 tht_pkt_get(struct tht_pkt_list *tpl) 1910 { 1911 struct tht_pkt *pkt; 1912 1913 pkt = TAILQ_FIRST(&tpl->tpl_free); 1914 if (pkt != NULL) { 1915 TAILQ_REMOVE(&tpl->tpl_free, pkt, tp_link); 1916 TAILQ_INSERT_TAIL(&tpl->tpl_used, pkt, tp_link); 1917 1918 } 1919 1920 return (pkt); 1921 } 1922 1923 struct tht_pkt * 1924 tht_pkt_used(struct tht_pkt_list *tpl) 1925 { 1926 return (TAILQ_FIRST(&tpl->tpl_used)); 1927 } 1928