1 /* $OpenBSD: if_stge.c,v 1.53 2011/04/05 18:01:21 henning Exp $ */ 2 /* $NetBSD: if_stge.c,v 1.27 2005/05/16 21:35:32 bouyer Exp $ */ 3 4 /*- 5 * Copyright (c) 2001 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Device driver for the Sundance Tech. TC9021 10/100/1000 35 * Ethernet controller. 36 */ 37 38 #include "bpfilter.h" 39 #include "vlan.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/timeout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_ether.h> 62 #endif 63 64 #include <net/if_media.h> 65 66 #if NVLAN > 0 67 #include <net/if_types.h> 68 #include <net/if_vlan_var.h> 69 #endif 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #include <machine/bus.h> 76 #include <machine/intr.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <dev/mii/mii_bitbang.h> 81 82 #include <dev/pci/pcireg.h> 83 #include <dev/pci/pcivar.h> 84 #include <dev/pci/pcidevs.h> 85 86 #include <dev/pci/if_stgereg.h> 87 88 void stge_start(struct ifnet *); 89 void stge_watchdog(struct ifnet *); 90 int stge_ioctl(struct ifnet *, u_long, caddr_t); 91 int stge_init(struct ifnet *); 92 void stge_stop(struct ifnet *, int); 93 94 void stge_reset(struct stge_softc *); 95 void stge_rxdrain(struct stge_softc *); 96 int stge_add_rxbuf(struct stge_softc *, int); 97 void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 98 void stge_tick(void *); 99 100 void stge_stats_update(struct stge_softc *); 101 102 void stge_iff(struct stge_softc *); 103 104 int stge_intr(void *); 105 void stge_txintr(struct stge_softc *); 106 void stge_rxintr(struct stge_softc *); 107 108 int stge_mii_readreg(struct device *, int, int); 109 void stge_mii_writereg(struct device *, int, int, int); 110 void stge_mii_statchg(struct device *); 111 112 int stge_mediachange(struct ifnet *); 113 void stge_mediastatus(struct ifnet *, struct ifmediareq *); 114 115 int stge_match(struct device *, void *, void *); 116 void stge_attach(struct device *, struct device *, void *); 117 118 int stge_copy_small = 0; 119 120 struct cfattach stge_ca = { 121 sizeof(struct stge_softc), stge_match, stge_attach, 122 }; 123 124 struct cfdriver stge_cd = { 125 NULL, "stge", DV_IFNET 126 }; 127 128 uint32_t stge_mii_bitbang_read(struct device *); 129 void stge_mii_bitbang_write(struct device *, uint32_t); 130 131 const struct mii_bitbang_ops stge_mii_bitbang_ops = { 132 stge_mii_bitbang_read, 133 stge_mii_bitbang_write, 134 { 135 PC_MgmtData, /* MII_BIT_MDO */ 136 PC_MgmtData, /* MII_BIT_MDI */ 137 PC_MgmtClk, /* MII_BIT_MDC */ 138 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 139 0, /* MII_BIT_DIR_PHY_HOST */ 140 } 141 }; 142 143 /* 144 * Devices supported by this driver. 145 */ 146 const struct pci_matchid stge_devices[] = { 147 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021 }, 148 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T }, 149 { PCI_VENDOR_SUNDANCE, PCI_PRODUCT_SUNDANCE_ST1023 }, 150 { PCI_VENDOR_SUNDANCE, PCI_PRODUCT_SUNDANCE_ST2021 }, 151 { PCI_VENDOR_SUNDANCE, PCI_PRODUCT_SUNDANCE_TC9021 }, 152 { PCI_VENDOR_SUNDANCE, PCI_PRODUCT_SUNDANCE_TC9021_ALT }, 153 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021 }, 154 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT } 155 }; 156 157 int 158 stge_match(struct device *parent, void *match, void *aux) 159 { 160 return (pci_matchbyid((struct pci_attach_args *)aux, stge_devices, 161 sizeof(stge_devices) / sizeof(stge_devices[0]))); 162 } 163 164 void 165 stge_attach(struct device *parent, struct device *self, void *aux) 166 { 167 struct stge_softc *sc = (struct stge_softc *) self; 168 struct pci_attach_args *pa = aux; 169 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 170 pci_chipset_tag_t pc = pa->pa_pc; 171 pci_intr_handle_t ih; 172 const char *intrstr = NULL; 173 bus_space_tag_t iot, memt; 174 bus_space_handle_t ioh, memh; 175 bus_dma_segment_t seg; 176 bus_size_t iosize; 177 int ioh_valid, memh_valid; 178 int i, rseg, error; 179 int state; 180 181 timeout_set(&sc->sc_timeout, stge_tick, sc); 182 183 sc->sc_rev = PCI_REVISION(pa->pa_class); 184 185 /* 186 * Map the device. 187 */ 188 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 189 PCI_MAPREG_TYPE_IO, 0, 190 &iot, &ioh, NULL, &iosize, 0) == 0); 191 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 192 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 193 &memt, &memh, NULL, &iosize, 0) == 0); 194 195 if (memh_valid) { 196 sc->sc_st = memt; 197 sc->sc_sh = memh; 198 } else if (ioh_valid) { 199 sc->sc_st = iot; 200 sc->sc_sh = ioh; 201 } else { 202 printf(": unable to map device registers\n"); 203 return; 204 } 205 206 sc->sc_dmat = pa->pa_dmat; 207 208 /* Get it out of power save mode if needed. */ 209 state = pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 210 if (state == PCI_PMCSR_STATE_D3) { 211 /* 212 * The card has lost all configuration data in 213 * this state, so punt. 214 */ 215 printf(": unable to wake up from power state D3, " 216 "reboot required.\n"); 217 return; 218 } 219 220 /* 221 * Map and establish our interrupt. 222 */ 223 if (pci_intr_map(pa, &ih)) { 224 printf(": unable to map interrupt\n"); 225 goto fail_0; 226 } 227 intrstr = pci_intr_string(pc, ih); 228 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc, 229 sc->sc_dev.dv_xname); 230 if (sc->sc_ih == NULL) { 231 printf(": unable to establish interrupt"); 232 if (intrstr != NULL) 233 printf(" at %s", intrstr); 234 printf("\n"); 235 goto fail_0; 236 } 237 printf(": %s", intrstr); 238 239 /* 240 * Allocate the control data structures, and create and load the 241 * DMA map for it. 242 */ 243 if ((error = bus_dmamem_alloc(sc->sc_dmat, 244 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 245 0)) != 0) { 246 printf("%s: unable to allocate control data, error = %d\n", 247 sc->sc_dev.dv_xname, error); 248 goto fail_0; 249 } 250 251 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 252 sizeof(struct stge_control_data), (caddr_t *)&sc->sc_control_data, 253 BUS_DMA_COHERENT)) != 0) { 254 printf("%s: unable to map control data, error = %d\n", 255 sc->sc_dev.dv_xname, error); 256 goto fail_1; 257 } 258 259 if ((error = bus_dmamap_create(sc->sc_dmat, 260 sizeof(struct stge_control_data), 1, 261 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 262 printf("%s: unable to create control data DMA map, " 263 "error = %d\n", sc->sc_dev.dv_xname, error); 264 goto fail_2; 265 } 266 267 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 268 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 269 0)) != 0) { 270 printf("%s: unable to load control data DMA map, error = %d\n", 271 sc->sc_dev.dv_xname, error); 272 goto fail_3; 273 } 274 275 /* 276 * Create the transmit buffer DMA maps. Note that rev B.3 277 * and earlier seem to have a bug regarding multi-fragment 278 * packets. We need to limit the number of Tx segments on 279 * such chips to 1. 280 */ 281 for (i = 0; i < STGE_NTXDESC; i++) { 282 if ((error = bus_dmamap_create(sc->sc_dmat, 283 STGE_JUMBO_FRAMELEN, STGE_NTXFRAGS, MCLBYTES, 0, 0, 284 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 285 printf("%s: unable to create tx DMA map %d, " 286 "error = %d\n", sc->sc_dev.dv_xname, i, error); 287 goto fail_4; 288 } 289 } 290 291 /* 292 * Create the receive buffer DMA maps. 293 */ 294 for (i = 0; i < STGE_NRXDESC; i++) { 295 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 296 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 297 printf("%s: unable to create rx DMA map %d, " 298 "error = %d\n", sc->sc_dev.dv_xname, i, error); 299 goto fail_5; 300 } 301 sc->sc_rxsoft[i].ds_mbuf = NULL; 302 } 303 304 /* 305 * Determine if we're copper or fiber. It affects how we 306 * reset the card. 307 */ 308 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) 309 sc->sc_usefiber = 1; 310 else 311 sc->sc_usefiber = 0; 312 313 /* 314 * Reset the chip to a known state. 315 */ 316 stge_reset(sc); 317 318 /* 319 * Reading the station address from the EEPROM doesn't seem 320 * to work, at least on my sample boards. Instead, since 321 * the reset sequence does AutoInit, read it from the station 322 * address registers. For Sundance 1023 you can only read it 323 * from EEPROM. 324 */ 325 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_SUNDANCE_ST1023) { 326 sc->sc_arpcom.ac_enaddr[0] = CSR_READ_2(sc, 327 STGE_StationAddress0) & 0xff; 328 sc->sc_arpcom.ac_enaddr[1] = CSR_READ_2(sc, 329 STGE_StationAddress0) >> 8; 330 sc->sc_arpcom.ac_enaddr[2] = CSR_READ_2(sc, 331 STGE_StationAddress1) & 0xff; 332 sc->sc_arpcom.ac_enaddr[3] = CSR_READ_2(sc, 333 STGE_StationAddress1) >> 8; 334 sc->sc_arpcom.ac_enaddr[4] = CSR_READ_2(sc, 335 STGE_StationAddress2) & 0xff; 336 sc->sc_arpcom.ac_enaddr[5] = CSR_READ_2(sc, 337 STGE_StationAddress2) >> 8; 338 sc->sc_stge1023 = 0; 339 } else { 340 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 341 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 342 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 343 &myaddr[i]); 344 myaddr[i] = letoh16(myaddr[i]); 345 } 346 (void)memcpy(sc->sc_arpcom.ac_enaddr, myaddr, 347 sizeof(sc->sc_arpcom.ac_enaddr)); 348 sc->sc_stge1023 = 1; 349 } 350 351 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 352 353 /* 354 * Read some important bits from the PhyCtrl register. 355 */ 356 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & 357 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 358 359 /* 360 * Initialize our media structures and probe the MII. 361 */ 362 sc->sc_mii.mii_ifp = ifp; 363 sc->sc_mii.mii_readreg = stge_mii_readreg; 364 sc->sc_mii.mii_writereg = stge_mii_writereg; 365 sc->sc_mii.mii_statchg = stge_mii_statchg; 366 ifmedia_init(&sc->sc_mii.mii_media, 0, stge_mediachange, 367 stge_mediastatus); 368 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 369 MII_OFFSET_ANY, MIIF_DOPAUSE); 370 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 371 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 372 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 373 } else 374 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 375 376 ifp = &sc->sc_arpcom.ac_if; 377 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname); 378 ifp->if_softc = sc; 379 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 380 ifp->if_ioctl = stge_ioctl; 381 ifp->if_start = stge_start; 382 ifp->if_watchdog = stge_watchdog; 383 #ifdef STGE_JUMBO 384 ifp->if_hardmtu = STGE_JUMBO_MTU; 385 #endif 386 IFQ_SET_MAXLEN(&ifp->if_snd, STGE_NTXDESC - 1); 387 IFQ_SET_READY(&ifp->if_snd); 388 389 ifp->if_capabilities = IFCAP_VLAN_MTU; 390 391 #if NVLAN > 0 392 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 393 #endif 394 395 /* 396 * The manual recommends disabling early transmit, so we 397 * do. It's disabled anyway, if using IP checksumming, 398 * since the entire packet must be in the FIFO in order 399 * for the chip to perform the checksum. 400 */ 401 sc->sc_txthresh = 0x0fff; 402 403 /* 404 * Disable MWI if the PCI layer tells us to. 405 */ 406 sc->sc_DMACtrl = 0; 407 #ifdef fake 408 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 409 sc->sc_DMACtrl |= DMAC_MWIDisable; 410 #endif 411 412 #ifdef STGE_CHECKSUM 413 /* 414 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 415 */ 416 sc->sc_arpcom.ac_if.if_capabilities |= IFCAP_CSUM_IPv4 | 417 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 418 #endif 419 420 /* 421 * Attach the interface. 422 */ 423 if_attach(ifp); 424 ether_ifattach(ifp); 425 return; 426 427 /* 428 * Free any resources we've allocated during the failed attach 429 * attempt. Do this in reverse order and fall through. 430 */ 431 fail_5: 432 for (i = 0; i < STGE_NRXDESC; i++) { 433 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 434 bus_dmamap_destroy(sc->sc_dmat, 435 sc->sc_rxsoft[i].ds_dmamap); 436 } 437 fail_4: 438 for (i = 0; i < STGE_NTXDESC; i++) { 439 if (sc->sc_txsoft[i].ds_dmamap != NULL) 440 bus_dmamap_destroy(sc->sc_dmat, 441 sc->sc_txsoft[i].ds_dmamap); 442 } 443 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 444 fail_3: 445 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 446 fail_2: 447 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 448 sizeof(struct stge_control_data)); 449 fail_1: 450 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 451 fail_0: 452 bus_space_unmap(sc->sc_st, sc->sc_sh, iosize); 453 return; 454 } 455 456 static void 457 stge_dma_wait(struct stge_softc *sc) 458 { 459 int i; 460 461 for (i = 0; i < STGE_TIMEOUT; i++) { 462 delay(2); 463 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) 464 break; 465 } 466 467 if (i == STGE_TIMEOUT) 468 printf("%s: DMA wait timed out\n", sc->sc_dev.dv_xname); 469 } 470 471 /* 472 * stge_start: [ifnet interface function] 473 * 474 * Start packet transmission on the interface. 475 */ 476 void 477 stge_start(struct ifnet *ifp) 478 { 479 struct stge_softc *sc = ifp->if_softc; 480 struct mbuf *m0; 481 struct stge_descsoft *ds; 482 struct stge_tfd *tfd; 483 bus_dmamap_t dmamap; 484 int error, firsttx, nexttx, opending, seg, totlen; 485 uint64_t csum_flags = 0, tfc; 486 487 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 488 return; 489 490 /* 491 * Remember the previous number of pending transmissions 492 * and the first descriptor we will use. 493 */ 494 opending = sc->sc_txpending; 495 firsttx = STGE_NEXTTX(sc->sc_txlast); 496 497 /* 498 * Loop through the send queue, setting up transmit descriptors 499 * until we drain the queue, or use up all available transmit 500 * descriptors. 501 */ 502 for (;;) { 503 /* 504 * Grab a packet off the queue. 505 */ 506 IFQ_POLL(&ifp->if_snd, m0); 507 if (m0 == NULL) 508 break; 509 510 /* 511 * Leave one unused descriptor at the end of the 512 * list to prevent wrapping completely around. 513 */ 514 if (sc->sc_txpending == (STGE_NTXDESC - 1)) 515 break; 516 517 /* 518 * Get the last and next available transmit descriptor. 519 */ 520 nexttx = STGE_NEXTTX(sc->sc_txlast); 521 tfd = &sc->sc_txdescs[nexttx]; 522 ds = &sc->sc_txsoft[nexttx]; 523 524 dmamap = ds->ds_dmamap; 525 526 /* 527 * Load the DMA map. If this fails, the packet either 528 * didn't fit in the alloted number of segments, or we 529 * were short on resources. For the too-many-segments 530 * case, we simply report an error and drop the packet, 531 * since we can't sanely copy a jumbo packet to a single 532 * buffer. 533 */ 534 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 535 BUS_DMA_NOWAIT); 536 if (error) { 537 if (error == EFBIG) { 538 printf("%s: Tx packet consumes too many " 539 "DMA segments (%u), dropping...\n", 540 sc->sc_dev.dv_xname, dmamap->dm_nsegs); 541 IFQ_DEQUEUE(&ifp->if_snd, m0); 542 m_freem(m0); 543 continue; 544 } 545 /* 546 * Short on resources, just stop for now. 547 */ 548 break; 549 } 550 551 IFQ_DEQUEUE(&ifp->if_snd, m0); 552 553 /* 554 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 555 */ 556 557 /* Sync the DMA map. */ 558 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 559 BUS_DMASYNC_PREWRITE); 560 561 /* Initialize the fragment list. */ 562 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 563 tfd->tfd_frags[seg].frag_word0 = 564 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 565 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 566 totlen += dmamap->dm_segs[seg].ds_len; 567 } 568 569 #ifdef STGE_CHECKSUM 570 /* 571 * Initialize checksumming flags in the descriptor. 572 * Byte-swap constants so the compiler can optimize. 573 */ 574 if (m0->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 575 csum_flags |= TFD_IPChecksumEnable; 576 577 if (m0->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 578 csum_flags |= TFD_TCPChecksumEnable; 579 else if (m0->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 580 csum_flags |= TFD_UDPChecksumEnable; 581 #endif 582 583 /* 584 * Initialize the descriptor and give it to the chip. 585 */ 586 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 587 TFD_FragCount(seg) | csum_flags; 588 if ((nexttx & STGE_TXINTR_SPACING_MASK) == 0) 589 tfc |= TFD_TxDMAIndicate; 590 591 #if NVLAN > 0 592 /* Check if we have a VLAN tag to insert. */ 593 if (m0->m_flags & M_VLANTAG) 594 tfc |= (TFD_VLANTagInsert | 595 TFD_VID(m0->m_pkthdr.ether_vtag)); 596 #endif 597 598 tfd->tfd_control = htole64(tfc); 599 600 /* Sync the descriptor. */ 601 STGE_CDTXSYNC(sc, nexttx, 602 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 603 604 /* 605 * Kick the transmit DMA logic. 606 */ 607 CSR_WRITE_4(sc, STGE_DMACtrl, 608 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 609 610 /* 611 * Store a pointer to the packet so we can free it later. 612 */ 613 ds->ds_mbuf = m0; 614 615 /* Advance the tx pointer. */ 616 sc->sc_txpending++; 617 sc->sc_txlast = nexttx; 618 619 #if NBPFILTER > 0 620 /* 621 * Pass the packet to any BPF listeners. 622 */ 623 if (ifp->if_bpf) 624 bpf_mtap_ether(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 625 #endif /* NBPFILTER > 0 */ 626 } 627 628 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 629 /* No more slots left; notify upper layer. */ 630 ifp->if_flags |= IFF_OACTIVE; 631 } 632 633 if (sc->sc_txpending != opending) { 634 /* 635 * We enqueued packets. If the transmitter was idle, 636 * reset the txdirty pointer. 637 */ 638 if (opending == 0) 639 sc->sc_txdirty = firsttx; 640 641 /* Set a watchdog timer in case the chip flakes out. */ 642 ifp->if_timer = 5; 643 } 644 } 645 646 /* 647 * stge_watchdog: [ifnet interface function] 648 * 649 * Watchdog timer handler. 650 */ 651 void 652 stge_watchdog(struct ifnet *ifp) 653 { 654 struct stge_softc *sc = ifp->if_softc; 655 656 /* 657 * Sweep up first, since we don't interrupt every frame. 658 */ 659 stge_txintr(sc); 660 if (sc->sc_txpending != 0) { 661 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 662 ifp->if_oerrors++; 663 664 (void) stge_init(ifp); 665 666 /* Try to get more packets going. */ 667 stge_start(ifp); 668 } 669 } 670 671 /* 672 * stge_ioctl: [ifnet interface function] 673 * 674 * Handle control requests from the operator. 675 */ 676 int 677 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 678 { 679 struct stge_softc *sc = ifp->if_softc; 680 struct ifaddr *ifa = (struct ifaddr *)data; 681 struct ifreq *ifr = (struct ifreq *)data; 682 int s, error = 0; 683 684 s = splnet(); 685 686 switch (cmd) { 687 case SIOCSIFADDR: 688 ifp->if_flags |= IFF_UP; 689 if (!(ifp->if_flags & IFF_RUNNING)) 690 stge_init(ifp); 691 692 #ifdef INET 693 if (ifa->ifa_addr->sa_family == AF_INET) 694 arp_ifinit(&sc->sc_arpcom, ifa); 695 #endif 696 break; 697 698 case SIOCSIFFLAGS: 699 if (ifp->if_flags & IFF_UP) { 700 if (ifp->if_flags & IFF_RUNNING) 701 error = ENETRESET; 702 else 703 stge_init(ifp); 704 } else { 705 if (ifp->if_flags & IFF_RUNNING) 706 stge_stop(ifp, 1); 707 } 708 break; 709 710 case SIOCSIFMEDIA: 711 case SIOCGIFMEDIA: 712 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 713 break; 714 715 default: 716 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 717 } 718 719 if (error == ENETRESET) { 720 if (ifp->if_flags & IFF_RUNNING) 721 stge_iff(sc); 722 error = 0; 723 } 724 725 /* Try to get more packets going. */ 726 stge_start(ifp); 727 728 splx(s); 729 return (error); 730 } 731 732 /* 733 * stge_intr: 734 * 735 * Interrupt service routine. 736 */ 737 int 738 stge_intr(void *arg) 739 { 740 struct stge_softc *sc = arg; 741 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 742 uint32_t txstat; 743 int wantinit; 744 uint16_t isr; 745 746 if ((CSR_READ_2(sc, STGE_IntStatus) & IS_InterruptStatus) == 0) 747 return (0); 748 749 for (wantinit = 0; wantinit == 0;) { 750 isr = CSR_READ_2(sc, STGE_IntStatusAck); 751 if ((isr & sc->sc_IntEnable) == 0) 752 break; 753 754 /* Host interface errors. */ 755 if (isr & IS_HostError) { 756 printf("%s: Host interface error\n", 757 sc->sc_dev.dv_xname); 758 wantinit = 1; 759 continue; 760 } 761 762 /* Receive interrupts. */ 763 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) { 764 stge_rxintr(sc); 765 if (isr & IS_RFDListEnd) { 766 printf("%s: receive ring overflow\n", 767 sc->sc_dev.dv_xname); 768 /* 769 * XXX Should try to recover from this 770 * XXX more gracefully. 771 */ 772 wantinit = 1; 773 } 774 } 775 776 /* Transmit interrupts. */ 777 if (isr & (IS_TxDMAComplete|IS_TxComplete)) 778 stge_txintr(sc); 779 780 /* Statistics overflow. */ 781 if (isr & IS_UpdateStats) 782 stge_stats_update(sc); 783 784 /* Transmission errors. */ 785 if (isr & IS_TxComplete) { 786 for (;;) { 787 txstat = CSR_READ_4(sc, STGE_TxStatus); 788 if ((txstat & TS_TxComplete) == 0) 789 break; 790 if (txstat & TS_TxUnderrun) { 791 sc->sc_txthresh++; 792 if (sc->sc_txthresh > 0x0fff) 793 sc->sc_txthresh = 0x0fff; 794 printf("%s: transmit underrun, new " 795 "threshold: %d bytes\n", 796 sc->sc_dev.dv_xname, 797 sc->sc_txthresh << 5); 798 } 799 if (txstat & TS_MaxCollisions) 800 printf("%s: excessive collisions\n", 801 sc->sc_dev.dv_xname); 802 } 803 wantinit = 1; 804 } 805 806 } 807 808 if (wantinit) 809 stge_init(ifp); 810 811 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 812 813 /* Try to get more packets going. */ 814 stge_start(ifp); 815 816 return (1); 817 } 818 819 /* 820 * stge_txintr: 821 * 822 * Helper; handle transmit interrupts. 823 */ 824 void 825 stge_txintr(struct stge_softc *sc) 826 { 827 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 828 struct stge_descsoft *ds; 829 uint64_t control; 830 int i; 831 832 ifp->if_flags &= ~IFF_OACTIVE; 833 834 /* 835 * Go through our Tx list and free mbufs for those 836 * frames which have been transmitted. 837 */ 838 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 839 i = STGE_NEXTTX(i), sc->sc_txpending--) { 840 ds = &sc->sc_txsoft[i]; 841 842 STGE_CDTXSYNC(sc, i, 843 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 844 845 control = letoh64(sc->sc_txdescs[i].tfd_control); 846 if ((control & TFD_TFDDone) == 0) 847 break; 848 849 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 850 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 851 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 852 m_freem(ds->ds_mbuf); 853 ds->ds_mbuf = NULL; 854 } 855 856 /* Update the dirty transmit buffer pointer. */ 857 sc->sc_txdirty = i; 858 859 /* 860 * If there are no more pending transmissions, cancel the watchdog 861 * timer. 862 */ 863 if (sc->sc_txpending == 0) 864 ifp->if_timer = 0; 865 } 866 867 /* 868 * stge_rxintr: 869 * 870 * Helper; handle receive interrupts. 871 */ 872 void 873 stge_rxintr(struct stge_softc *sc) 874 { 875 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 876 struct stge_descsoft *ds; 877 struct mbuf *m, *tailm; 878 uint64_t status; 879 int i, len; 880 881 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 882 ds = &sc->sc_rxsoft[i]; 883 884 STGE_CDRXSYNC(sc, i, 885 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 886 887 status = letoh64(sc->sc_rxdescs[i].rfd_status); 888 889 if ((status & RFD_RFDDone) == 0) 890 break; 891 892 if (__predict_false(sc->sc_rxdiscard)) { 893 STGE_INIT_RXDESC(sc, i); 894 if (status & RFD_FrameEnd) { 895 /* Reset our state. */ 896 sc->sc_rxdiscard = 0; 897 } 898 continue; 899 } 900 901 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 902 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 903 904 m = ds->ds_mbuf; 905 906 /* 907 * Add a new receive buffer to the ring. 908 */ 909 if (stge_add_rxbuf(sc, i) != 0) { 910 /* 911 * Failed, throw away what we've done so 912 * far, and discard the rest of the packet. 913 */ 914 ifp->if_ierrors++; 915 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 916 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 917 STGE_INIT_RXDESC(sc, i); 918 if ((status & RFD_FrameEnd) == 0) 919 sc->sc_rxdiscard = 1; 920 if (sc->sc_rxhead != NULL) 921 m_freem(sc->sc_rxhead); 922 STGE_RXCHAIN_RESET(sc); 923 continue; 924 } 925 926 #ifdef DIAGNOSTIC 927 if (status & RFD_FrameStart) { 928 KASSERT(sc->sc_rxhead == NULL); 929 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 930 } 931 #endif 932 933 STGE_RXCHAIN_LINK(sc, m); 934 935 /* 936 * If this is not the end of the packet, keep 937 * looking. 938 */ 939 if ((status & RFD_FrameEnd) == 0) { 940 sc->sc_rxlen += m->m_len; 941 continue; 942 } 943 944 /* 945 * Okay, we have the entire packet now... 946 */ 947 *sc->sc_rxtailp = NULL; 948 m = sc->sc_rxhead; 949 tailm = sc->sc_rxtail; 950 951 STGE_RXCHAIN_RESET(sc); 952 953 /* 954 * If the packet had an error, drop it. Note we 955 * count the error later in the periodic stats update. 956 */ 957 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 958 RFD_RxAlignmentError | RFD_RxFCSError | 959 RFD_RxLengthError)) { 960 m_freem(m); 961 continue; 962 } 963 964 /* 965 * No errors. 966 * 967 * Note we have configured the chip to not include 968 * the CRC at the end of the packet. 969 */ 970 len = RFD_RxDMAFrameLen(status); 971 tailm->m_len = len - sc->sc_rxlen; 972 973 /* 974 * If the packet is small enough to fit in a 975 * single header mbuf, allocate one and copy 976 * the data into it. This greatly reduces 977 * memory consumption when we receive lots 978 * of small packets. 979 */ 980 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 981 struct mbuf *nm; 982 MGETHDR(nm, M_DONTWAIT, MT_DATA); 983 if (nm == NULL) { 984 ifp->if_ierrors++; 985 m_freem(m); 986 continue; 987 } 988 nm->m_data += 2; 989 nm->m_pkthdr.len = nm->m_len = len; 990 m_copydata(m, 0, len, mtod(nm, caddr_t)); 991 m_freem(m); 992 m = nm; 993 } 994 995 /* 996 * Set the incoming checksum information for the packet. 997 */ 998 if ((status & RFD_IPDetected) && 999 (!(status & RFD_IPError))) 1000 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1001 if ((status & RFD_TCPDetected) && 1002 (!(status & RFD_TCPError))) 1003 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 1004 else if ((status & RFD_UDPDetected) && 1005 (!(status & RFD_UDPError))) 1006 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 1007 1008 #if NVLAN > 0 1009 /* Check for VLAN tagged packets. */ 1010 if (status & RFD_VLANDetected) { 1011 m->m_pkthdr.ether_vtag = RFD_TCI(status); 1012 m->m_flags |= M_VLANTAG; 1013 } 1014 #endif 1015 1016 m->m_pkthdr.rcvif = ifp; 1017 m->m_pkthdr.len = len; 1018 1019 #if NBPFILTER > 0 1020 /* 1021 * Pass this up to any BPF listeners, but only 1022 * pass if up the stack if it's for us. 1023 */ 1024 if (ifp->if_bpf) 1025 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 1026 #endif /* NBPFILTER > 0 */ 1027 1028 /* Pass it on. */ 1029 ether_input_mbuf(ifp, m); 1030 } 1031 1032 /* Update the receive pointer. */ 1033 sc->sc_rxptr = i; 1034 } 1035 1036 /* 1037 * stge_tick: 1038 * 1039 * One second timer, used to tick the MII. 1040 */ 1041 void 1042 stge_tick(void *arg) 1043 { 1044 struct stge_softc *sc = arg; 1045 int s; 1046 1047 s = splnet(); 1048 mii_tick(&sc->sc_mii); 1049 stge_stats_update(sc); 1050 splx(s); 1051 1052 timeout_add_sec(&sc->sc_timeout, 1); 1053 } 1054 1055 /* 1056 * stge_stats_update: 1057 * 1058 * Read the TC9021 statistics counters. 1059 */ 1060 void 1061 stge_stats_update(struct stge_softc *sc) 1062 { 1063 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1064 1065 (void) CSR_READ_4(sc, STGE_OctetRcvOk); 1066 1067 ifp->if_ipackets += 1068 CSR_READ_4(sc, STGE_FramesRcvdOk); 1069 1070 ifp->if_ierrors += 1071 (u_int) CSR_READ_2(sc, STGE_FramesLostRxErrors); 1072 1073 (void) CSR_READ_4(sc, STGE_OctetXmtdOk); 1074 1075 ifp->if_opackets += 1076 CSR_READ_4(sc, STGE_FramesXmtdOk); 1077 1078 ifp->if_collisions += 1079 CSR_READ_4(sc, STGE_LateCollisions) + 1080 CSR_READ_4(sc, STGE_MultiColFrames) + 1081 CSR_READ_4(sc, STGE_SingleColFrames); 1082 1083 ifp->if_oerrors += 1084 (u_int) CSR_READ_2(sc, STGE_FramesAbortXSColls) + 1085 (u_int) CSR_READ_2(sc, STGE_FramesWEXDeferal); 1086 } 1087 1088 /* 1089 * stge_reset: 1090 * 1091 * Perform a soft reset on the TC9021. 1092 */ 1093 void 1094 stge_reset(struct stge_softc *sc) 1095 { 1096 uint32_t ac; 1097 int i; 1098 1099 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1100 1101 /* 1102 * Only assert RstOut if we're fiber. We need GMII clocks 1103 * to be present in order for the reset to complete on fiber 1104 * cards. 1105 */ 1106 CSR_WRITE_4(sc, STGE_AsicCtrl, 1107 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1108 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1109 (sc->sc_usefiber ? AC_RstOut : 0)); 1110 1111 delay(50000); 1112 1113 for (i = 0; i < STGE_TIMEOUT; i++) { 1114 delay(5000); 1115 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1116 break; 1117 } 1118 1119 if (i == STGE_TIMEOUT) 1120 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1121 1122 delay(1000); 1123 } 1124 1125 /* 1126 * stge_init: [ ifnet interface function ] 1127 * 1128 * Initialize the interface. Must be called at splnet(). 1129 */ 1130 int 1131 stge_init(struct ifnet *ifp) 1132 { 1133 struct stge_softc *sc = ifp->if_softc; 1134 struct stge_descsoft *ds; 1135 int i, error = 0; 1136 1137 /* 1138 * Cancel any pending I/O. 1139 */ 1140 stge_stop(ifp, 0); 1141 1142 /* 1143 * Reset the chip to a known state. 1144 */ 1145 stge_reset(sc); 1146 1147 /* 1148 * Initialize the transmit descriptor ring. 1149 */ 1150 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1151 for (i = 0; i < STGE_NTXDESC; i++) { 1152 sc->sc_txdescs[i].tfd_next = htole64( 1153 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1154 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1155 } 1156 sc->sc_txpending = 0; 1157 sc->sc_txdirty = 0; 1158 sc->sc_txlast = STGE_NTXDESC - 1; 1159 1160 /* 1161 * Initialize the receive descriptor and receive job 1162 * descriptor rings. 1163 */ 1164 for (i = 0; i < STGE_NRXDESC; i++) { 1165 ds = &sc->sc_rxsoft[i]; 1166 if (ds->ds_mbuf == NULL) { 1167 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1168 printf("%s: unable to allocate or map rx " 1169 "buffer %d, error = %d\n", 1170 sc->sc_dev.dv_xname, i, error); 1171 /* 1172 * XXX Should attempt to run with fewer receive 1173 * XXX buffers instead of just failing. 1174 */ 1175 stge_rxdrain(sc); 1176 goto out; 1177 } 1178 } else 1179 STGE_INIT_RXDESC(sc, i); 1180 } 1181 sc->sc_rxptr = 0; 1182 sc->sc_rxdiscard = 0; 1183 STGE_RXCHAIN_RESET(sc); 1184 1185 /* Set the station address. */ 1186 if (sc->sc_stge1023) { 1187 CSR_WRITE_2(sc, STGE_StationAddress0, 1188 sc->sc_arpcom.ac_enaddr[0] | sc->sc_arpcom.ac_enaddr[1] << 8); 1189 CSR_WRITE_2(sc, STGE_StationAddress1, 1190 sc->sc_arpcom.ac_enaddr[2] | sc->sc_arpcom.ac_enaddr[3] << 8); 1191 CSR_WRITE_2(sc, STGE_StationAddress2, 1192 sc->sc_arpcom.ac_enaddr[4] | sc->sc_arpcom.ac_enaddr[5] << 8); 1193 } else { 1194 for (i = 0; i < ETHER_ADDR_LEN; i++) 1195 CSR_WRITE_1(sc, STGE_StationAddress0 + i, 1196 sc->sc_arpcom.ac_enaddr[i]); 1197 } 1198 1199 /* 1200 * Set the statistics masks. Disable all the RMON stats, 1201 * and disable selected stats in the non-RMON stats registers. 1202 */ 1203 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); 1204 CSR_WRITE_4(sc, STGE_StatisticsMask, 1205 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1206 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1207 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1208 (1U << 21)); 1209 1210 /* Program promiscuous mode and multicast filters. */ 1211 stge_iff(sc); 1212 1213 /* 1214 * Give the transmit and receive ring to the chip. 1215 */ 1216 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1217 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 1218 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1219 1220 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1221 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 1222 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1223 1224 /* 1225 * Initialize the Tx auto-poll period. It's OK to make this number 1226 * large (255 is the max, but we use 127) -- we explicitly kick the 1227 * transmit engine when there's actually a packet. 1228 */ 1229 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 1230 1231 /* ..and the Rx auto-poll period. */ 1232 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 64); 1233 1234 /* Initialize the Tx start threshold. */ 1235 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); 1236 1237 /* RX DMA thresholds, from linux */ 1238 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); 1239 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); 1240 1241 /* Rx early threhold, from Linux */ 1242 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); 1243 1244 /* Tx DMA thresholds, from Linux */ 1245 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); 1246 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); 1247 1248 /* 1249 * Initialize the Rx DMA interrupt control register. We 1250 * request an interrupt after every incoming packet, but 1251 * defer it for 32us (64 * 512 ns). When the number of 1252 * interrupts pending reaches 8, we stop deferring the 1253 * interrupt, and signal it immediately. 1254 */ 1255 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, 1256 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1257 1258 /* 1259 * Initialize the interrupt mask. 1260 */ 1261 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1262 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1263 CSR_WRITE_2(sc, STGE_IntStatus, 0xffff); 1264 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1265 1266 /* 1267 * Configure the DMA engine. 1268 * XXX Should auto-tune TxBurstLimit. 1269 */ 1270 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | 1271 DMAC_TxBurstLimit(3)); 1272 1273 /* 1274 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1275 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes 1276 * in the Rx FIFO. 1277 */ 1278 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16); 1279 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16); 1280 1281 /* 1282 * Set the maximum frame size. 1283 */ 1284 #ifdef STGE_JUMBO 1285 CSR_WRITE_2(sc, STGE_MaxFrameSize, STGE_JUMBO_FRAMELEN); 1286 #else 1287 CSR_WRITE_2(sc, STGE_MaxFrameSize, ETHER_MAX_LEN); 1288 #endif 1289 1290 /* 1291 * Initialize MacCtrl -- do it before setting the media, 1292 * as setting the media will actually program the register. 1293 * 1294 * Note: We have to poke the IFS value before poking 1295 * anything else. 1296 */ 1297 sc->sc_MACCtrl = MC_IFSSelect(0); 1298 CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl); 1299 1300 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1301 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1302 1303 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1304 1305 if (sc->sc_rev >= 6) { /* >= B.2 */ 1306 /* Multi-frag frame bug work-around. */ 1307 CSR_WRITE_2(sc, STGE_DebugCtrl, 1308 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200); 1309 1310 /* Tx Poll Now bug work-around. */ 1311 CSR_WRITE_2(sc, STGE_DebugCtrl, 1312 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010); 1313 1314 /* Rx Poll Now bug work-around. */ 1315 CSR_WRITE_2(sc, STGE_DebugCtrl, 1316 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020); 1317 } 1318 1319 /* 1320 * Set the current media. 1321 */ 1322 mii_mediachg(&sc->sc_mii); 1323 1324 /* 1325 * Start the one second MII clock. 1326 */ 1327 timeout_add_sec(&sc->sc_timeout, 1); 1328 1329 /* 1330 * ...all done! 1331 */ 1332 ifp->if_flags |= IFF_RUNNING; 1333 ifp->if_flags &= ~IFF_OACTIVE; 1334 1335 out: 1336 if (error) 1337 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1338 return (error); 1339 } 1340 1341 /* 1342 * stge_drain: 1343 * 1344 * Drain the receive queue. 1345 */ 1346 void 1347 stge_rxdrain(struct stge_softc *sc) 1348 { 1349 struct stge_descsoft *ds; 1350 int i; 1351 1352 for (i = 0; i < STGE_NRXDESC; i++) { 1353 ds = &sc->sc_rxsoft[i]; 1354 if (ds->ds_mbuf != NULL) { 1355 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1356 ds->ds_mbuf->m_next = NULL; 1357 m_freem(ds->ds_mbuf); 1358 ds->ds_mbuf = NULL; 1359 } 1360 } 1361 } 1362 1363 /* 1364 * stge_stop: [ ifnet interface function ] 1365 * 1366 * Stop transmission on the interface. 1367 */ 1368 void 1369 stge_stop(struct ifnet *ifp, int disable) 1370 { 1371 struct stge_softc *sc = ifp->if_softc; 1372 struct stge_descsoft *ds; 1373 int i; 1374 1375 /* 1376 * Stop the one second clock. 1377 */ 1378 timeout_del(&sc->sc_timeout); 1379 1380 /* 1381 * Mark the interface down and cancel the watchdog timer. 1382 */ 1383 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1384 ifp->if_timer = 0; 1385 1386 /* Down the MII. */ 1387 mii_down(&sc->sc_mii); 1388 1389 /* 1390 * Disable interrupts. 1391 */ 1392 CSR_WRITE_2(sc, STGE_IntEnable, 0); 1393 1394 /* 1395 * Stop receiver, transmitter, and stats update. 1396 */ 1397 CSR_WRITE_4(sc, STGE_MACCtrl, 1398 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1399 1400 /* 1401 * Stop the transmit and receive DMA. 1402 */ 1403 stge_dma_wait(sc); 1404 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); 1405 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0); 1406 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); 1407 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0); 1408 1409 /* 1410 * Release any queued transmit buffers. 1411 */ 1412 for (i = 0; i < STGE_NTXDESC; i++) { 1413 ds = &sc->sc_txsoft[i]; 1414 if (ds->ds_mbuf != NULL) { 1415 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1416 m_freem(ds->ds_mbuf); 1417 ds->ds_mbuf = NULL; 1418 } 1419 } 1420 1421 if (disable) 1422 stge_rxdrain(sc); 1423 } 1424 1425 static int 1426 stge_eeprom_wait(struct stge_softc *sc) 1427 { 1428 int i; 1429 1430 for (i = 0; i < STGE_TIMEOUT; i++) { 1431 delay(1000); 1432 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0) 1433 return (0); 1434 } 1435 return (1); 1436 } 1437 1438 /* 1439 * stge_read_eeprom: 1440 * 1441 * Read data from the serial EEPROM. 1442 */ 1443 void 1444 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1445 { 1446 1447 if (stge_eeprom_wait(sc)) 1448 printf("%s: EEPROM failed to come ready\n", 1449 sc->sc_dev.dv_xname); 1450 1451 CSR_WRITE_2(sc, STGE_EepromCtrl, 1452 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1453 if (stge_eeprom_wait(sc)) 1454 printf("%s: EEPROM read timed out\n", 1455 sc->sc_dev.dv_xname); 1456 *data = CSR_READ_2(sc, STGE_EepromData); 1457 } 1458 1459 /* 1460 * stge_add_rxbuf: 1461 * 1462 * Add a receive buffer to the indicated descriptor. 1463 */ 1464 int 1465 stge_add_rxbuf(struct stge_softc *sc, int idx) 1466 { 1467 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1468 struct mbuf *m; 1469 int error; 1470 1471 MGETHDR(m, M_DONTWAIT, MT_DATA); 1472 if (m == NULL) 1473 return (ENOBUFS); 1474 1475 MCLGET(m, M_DONTWAIT); 1476 if ((m->m_flags & M_EXT) == 0) { 1477 m_freem(m); 1478 return (ENOBUFS); 1479 } 1480 1481 m->m_data = m->m_ext.ext_buf + 2; 1482 m->m_len = MCLBYTES - 2; 1483 1484 if (ds->ds_mbuf != NULL) 1485 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1486 1487 ds->ds_mbuf = m; 1488 1489 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1490 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1491 if (error) { 1492 printf("%s: can't load rx DMA map %d, error = %d\n", 1493 sc->sc_dev.dv_xname, idx, error); 1494 panic("stge_add_rxbuf"); /* XXX */ 1495 } 1496 1497 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1498 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1499 1500 STGE_INIT_RXDESC(sc, idx); 1501 1502 return (0); 1503 } 1504 1505 /* 1506 * stge_iff: 1507 * 1508 * Set up the receive filter. 1509 */ 1510 void 1511 stge_iff(struct stge_softc *sc) 1512 { 1513 struct arpcom *ac = &sc->sc_arpcom; 1514 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1515 struct ether_multi *enm; 1516 struct ether_multistep step; 1517 uint32_t crc; 1518 uint32_t mchash[2]; 1519 1520 memset(mchash, 0, sizeof(mchash)); 1521 ifp->if_flags &= ~IFF_ALLMULTI; 1522 1523 /* 1524 * Always accept broadcast packets. 1525 * Always accept frames destined to our station address. 1526 */ 1527 sc->sc_ReceiveMode = RM_ReceiveBroadcast | RM_ReceiveUnicast; 1528 1529 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 1530 ifp->if_flags |= IFF_ALLMULTI; 1531 if (ifp->if_flags & IFF_PROMISC) 1532 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1533 else 1534 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1535 } else { 1536 /* 1537 * Set up the multicast address filter by passing all 1538 * multicast addresses through a CRC generator, and then 1539 * using the low-order 6 bits as an index into the 64 bit 1540 * multicast hash table. The high order bits select the 1541 * register, while the rest of the bits select the bit 1542 * within the register. 1543 */ 1544 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1545 1546 ETHER_FIRST_MULTI(step, ac, enm); 1547 while (enm != NULL) { 1548 crc = ether_crc32_be(enm->enm_addrlo, 1549 ETHER_ADDR_LEN); 1550 1551 /* Just want the 6 least significant bits. */ 1552 crc &= 0x3f; 1553 1554 /* Set the corresponding bit in the hash table. */ 1555 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1556 1557 ETHER_NEXT_MULTI(step, enm); 1558 } 1559 } 1560 1561 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]); 1562 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]); 1563 CSR_WRITE_2(sc, STGE_ReceiveMode, sc->sc_ReceiveMode); 1564 } 1565 1566 /* 1567 * stge_mii_readreg: [mii interface function] 1568 * 1569 * Read a PHY register on the MII of the TC9021. 1570 */ 1571 int 1572 stge_mii_readreg(struct device *self, int phy, int reg) 1573 { 1574 1575 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1576 } 1577 1578 /* 1579 * stge_mii_writereg: [mii interface function] 1580 * 1581 * Write a PHY register on the MII of the TC9021. 1582 */ 1583 void 1584 stge_mii_writereg(struct device *self, int phy, int reg, int val) 1585 { 1586 1587 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1588 } 1589 1590 /* 1591 * stge_mii_statchg: [mii interface function] 1592 * 1593 * Callback from MII layer when media changes. 1594 */ 1595 void 1596 stge_mii_statchg(struct device *self) 1597 { 1598 struct stge_softc *sc = (struct stge_softc *) self; 1599 struct mii_data *mii = &sc->sc_mii; 1600 1601 sc->sc_MACCtrl &= ~(MC_DuplexSelect | MC_RxFlowControlEnable | 1602 MC_TxFlowControlEnable); 1603 1604 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 1605 sc->sc_MACCtrl |= MC_DuplexSelect; 1606 1607 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_RXPAUSE) != 0) 1608 sc->sc_MACCtrl |= MC_RxFlowControlEnable; 1609 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_TXPAUSE) != 0) 1610 sc->sc_MACCtrl |= MC_TxFlowControlEnable; 1611 1612 CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl); 1613 } 1614 1615 /* 1616 * sste_mii_bitbang_read: [mii bit-bang interface function] 1617 * 1618 * Read the MII serial port for the MII bit-bang module. 1619 */ 1620 uint32_t 1621 stge_mii_bitbang_read(struct device *self) 1622 { 1623 struct stge_softc *sc = (void *) self; 1624 1625 return (CSR_READ_1(sc, STGE_PhyCtrl)); 1626 } 1627 1628 /* 1629 * stge_mii_bitbang_write: [mii big-bang interface function] 1630 * 1631 * Write the MII serial port for the MII bit-bang module. 1632 */ 1633 void 1634 stge_mii_bitbang_write(struct device *self, uint32_t val) 1635 { 1636 struct stge_softc *sc = (void *) self; 1637 1638 CSR_WRITE_1(sc, STGE_PhyCtrl, val | sc->sc_PhyCtrl); 1639 } 1640 1641 /* 1642 * stge_mediastatus: [ifmedia interface function] 1643 * 1644 * Get the current interface media status. 1645 */ 1646 void 1647 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1648 { 1649 struct stge_softc *sc = ifp->if_softc; 1650 1651 mii_pollstat(&sc->sc_mii); 1652 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1653 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1654 } 1655 1656 /* 1657 * stge_mediachange: [ifmedia interface function] 1658 * 1659 * Set hardware to newly-selected media. 1660 */ 1661 int 1662 stge_mediachange(struct ifnet *ifp) 1663 { 1664 struct stge_softc *sc = ifp->if_softc; 1665 1666 if (ifp->if_flags & IFF_UP) 1667 mii_mediachg(&sc->sc_mii); 1668 return (0); 1669 } 1670