1 /* $OpenBSD: if_stereg.h,v 1.4 2001/02/03 05:56:14 mickey Exp $ */ 2 /* 3 * Copyright (c) 1997, 1998, 1999 4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/pci/if_stereg.h,v 1.5 1999/12/07 20:14:42 wpaul Exp $ 34 */ 35 36 /* 37 * Sundance PCI device/vendor ID for the 38 * ST201 chip. 39 */ 40 #define ST_VENDORID 0x13F0 41 #define ST_DEVICEID_ST201 0x0201 42 43 /* 44 * D-Link PCI device/vendor ID for the DFE-550TX. 45 */ 46 #define DL_VENDORID 0x1186 47 #define DL_DEVICEID_550TX 0x1002 48 49 /* 50 * Register definitions for the Sundance Technologies ST201 PCI 51 * fast ethernet controller. The register space is 128 bytes long and 52 * can be accessed using either PCI I/O space or PCI memory mapping. 53 * There are 32-bit, 16-bit and 8-bit registers. 54 */ 55 56 #define STE_DMACTL 0x00 57 #define STE_TX_DMALIST_PTR 0x04 58 #define STE_TX_DMABURST_THRESH 0x08 59 #define STE_TX_DMAURG_THRESH 0x09 60 #define STE_TX_DMAPOLL_PERIOD 0x0A 61 #define STE_RX_DMASTATUS 0x0C 62 #define STE_RX_DMALIST_PTR 0x10 63 #define STE_RX_DMABURST_THRESH 0x14 64 #define STE_RX_DMAURG_THRESH 0x15 65 #define STE_RX_DMAPOLL_PERIOD 0x16 66 #define STE_DEBUGCTL 0x1A 67 #define STE_ASICCTL 0x30 68 #define STE_EEPROM_DATA 0x34 69 #define STE_EEPROM_CTL 0x36 70 #define STE_FIFOCTL 0x3A 71 #define STE_TX_STARTTHRESH 0x3C 72 #define STE_RX_EARLYTHRESH 0x3E 73 #define STE_EXT_ROMADDR 0x40 74 #define STE_EXT_ROMDATA 0x44 75 #define STE_WAKE_EVENT 0x45 76 #define STE_TX_STATUS 0x46 77 #define STE_TX_FRAMEID 0x47 78 #define STE_COUNTDOWN 0x48 79 #define STE_ISR_ACK 0x4A 80 #define STE_IMR 0x4C 81 #define STE_ISR 0x4E 82 #define STE_MACCTL0 0x50 83 #define STE_MACCTL1 0x52 84 #define STE_PAR0 0x54 85 #define STE_PAR1 0x56 86 #define STE_PAR2 0x58 87 #define STE_MAX_FRAMELEN 0x5A 88 #define STE_RX_MODE 0x5C 89 #define STE_TX_RECLAIM_THRESH 0x5D 90 #define STE_PHYCTL 0x5E 91 #define STE_MAR0 0x60 92 #define STE_MAR1 0x64 93 #define STE_STATS 0x68 94 95 #define STE_DMACTL_RXDMA_STOPPED 0x00000001 96 #define STE_DMACTL_TXDMA_CMPREQ 0x00000002 97 #define STE_DMACTL_TXDMA_STOPPED 0x00000004 98 #define STE_DMACTL_RXDMA_COMPLETE 0x00000008 99 #define STE_DMACTL_TXDMA_COMPLETE 0x00000010 100 #define STE_DMACTL_RXDMA_STALL 0x00000100 101 #define STE_DMACTL_RXDMA_UNSTALL 0x00000200 102 #define STE_DMACTL_TXDMA_STALL 0x00000400 103 #define STE_DMACTL_TXDMA_UNSTALL 0x00000800 104 #define STE_DMACTL_TXDMA_INPROG 0x00004000 105 #define STE_DMACTL_DMA_HALTINPROG 0x00008000 106 #define STE_DMACTL_RXEARLY_ENABLE 0x00020000 107 #define STE_DMACTL_COUNTDOWN_SPEED 0x00040000 108 #define STE_DMACTL_COUNTDOWN_MODE 0x00080000 109 #define STE_DMACTL_MWI_DISABLE 0x00100000 110 #define STE_DMACTL_RX_DISCARD_OFLOWS 0x00400000 111 #define STE_DMACTL_COUNTDOWN_ENABLE 0x00800000 112 #define STE_DMACTL_TARGET_ABORT 0x40000000 113 #define STE_DMACTL_MASTER_ABORT 0x80000000 114 115 /* 116 * TX DMA burst thresh is the number of 32-byte blocks that 117 * must be loaded into the TX Fifo before a TXDMA burst request 118 * will be issued. 119 */ 120 #define STE_TXDMABURST_THRESH 0x1F 121 122 /* 123 * The number of 32-byte blocks in the TX FIFO falls below the 124 * TX DMA urgent threshold, a TX DMA urgent request will be 125 * generated. 126 */ 127 #define STE_TXDMAURG_THRESH 0x3F 128 129 /* 130 * Number of 320ns intervals between polls of the TXDMA next 131 * descriptor pointer (if we're using polling mode). 132 */ 133 #define STE_TXDMA_POLL_PERIOD 0x7F 134 135 #define STE_RX_DMASTATUS_FRAMELEN 0x00001FFF 136 #define STE_RX_DMASTATUS_RXERR 0x00004000 137 #define STE_RX_DMASTATUS_DMADONE 0x00008000 138 #define STE_RX_DMASTATUS_FIFO_OFLOW 0x00010000 139 #define STE_RX_DMASTATUS_RUNT 0x00020000 140 #define STE_RX_DMASTATUS_ALIGNERR 0x00040000 141 #define STE_RX_DMASTATUS_CRCERR 0x00080000 142 #define STE_RX_DMASTATUS_GIANT 0x00100000 143 #define STE_RX_DMASTATUS_DRIBBLE 0x00800000 144 #define STE_RX_DMASTATUS_DMA_OFLOW 0x01000000 145 146 /* 147 * RX DMA burst thresh is the number of 32-byte blocks that 148 * must be present in the RX FIFO before a RXDMA bus master 149 * request will be issued. 150 */ 151 #define STE_RXDMABURST_THRESH 0xFF 152 153 /* 154 * The number of 32-byte blocks in the RX FIFO falls below the 155 * RX DMA urgent threshold, a RX DMA urgent request will be 156 * generated. 157 */ 158 #define STE_RXDMAURG_THRESH 0x1F 159 160 /* 161 * Number of 320ns intervals between polls of the RXDMA complete 162 * bit in the status field on the current RX descriptor (if we're 163 * using polling mode). 164 */ 165 #define STE_RXDMA_POLL_PERIOD 0x7F 166 167 #define STE_DEBUGCTL_GPIO0_CTL 0x0001 168 #define STE_DEBUGCTL_GPIO1_CTL 0x0002 169 #define STE_DEBUGCTL_GPIO0_DATA 0x0004 170 #define STE_DEBUGCTL_GPIO1_DATA 0x0008 171 172 #define STE_ASICCTL_ROMSIZE 0x00000002 173 #define STE_ASICCTL_TX_LARGEPKTS 0x00000004 174 #define STE_ASICCTL_RX_LARGEPKTS 0x00000008 175 #define STE_ASICCTL_EXTROM_DISABLE 0x00000010 176 #define STE_ASICCTL_PHYSPEED_10 0x00000020 177 #define STE_ASICCTL_PHYSPEED_100 0x00000040 178 #define STE_ASICCTL_PHYMEDIA 0x00000080 179 #define STE_ASICCTL_FORCEDCONFIG 0x00000700 180 #define STE_ASICCTL_D3RESET_DISABLE 0x00000800 181 #define STE_ASICCTL_SPEEDUPMODE 0x00002000 182 #define STE_ASICCTL_LEDMODE 0x00004000 183 #define STE_ASICCTL_RSTOUT_POLARITY 0x00008000 184 #define STE_ASICCTL_GLOBAL_RESET 0x00010000 185 #define STE_ASICCTL_RX_RESET 0x00020000 186 #define STE_ASICCTL_TX_RESET 0x00040000 187 #define STE_ASICCTL_DMA_RESET 0x00080000 188 #define STE_ASICCTL_FIFO_RESET 0x00100000 189 #define STE_ASICCTL_NETWORK_RESET 0x00200000 190 #define STE_ASICCTL_HOST_RESET 0x00400000 191 #define STE_ASICCTL_AUTOINIT_RESET 0x00800000 192 #define STE_ASICCTL_EXTRESET_RESET 0x01000000 193 #define STE_ASICCTL_SOFTINTR 0x02000000 194 #define STE_ASICCTL_RESET_BUSY 0x04000000 195 196 #define STE_ASICCTL1_GLOBAL_RESET 0x0001 197 #define STE_ASICCTL1_RX_RESET 0x0002 198 #define STE_ASICCTL1_TX_RESET 0x0004 199 #define STE_ASICCTL1_DMA_RESET 0x0008 200 #define STE_ASICCTL1_FIFO_RESET 0x0010 201 #define STE_ASICCTL1_NETWORK_RESET 0x0020 202 #define STE_ASICCTL1_HOST_RESET 0x0040 203 #define STE_ASICCTL1_AUTOINIT_RESET 0x0080 204 #define STE_ASICCTL1_EXTRESET_RESET 0x0100 205 #define STE_ASICCTL1_SOFTINTR 0x0200 206 #define STE_ASICCTL1_RESET_BUSY 0x0400 207 208 #define STE_EECTL_ADDR 0x00FF 209 #define STE_EECTL_OPCODE 0x0300 210 #define STE_EECTL_BUSY 0x1000 211 212 #define STE_EEOPCODE_WRITE 0x0100 213 #define STE_EEOPCODE_READ 0x0200 214 #define STE_EEOPCODE_ERASE 0x0300 215 216 #define STE_FIFOCTL_RAMTESTMODE 0x0001 217 #define STE_FIFOCTL_OVERRUNMODE 0x0200 218 #define STE_FIFOCTL_RXFIFOFULL 0x0800 219 #define STE_FIFOCTL_TX_BUSY 0x4000 220 #define STE_FIFOCTL_RX_BUSY 0x8000 221 222 /* 223 * The number of bytes that must in present in the TX FIFO before 224 * transmission begins. Value should be in increments of 4 bytes. 225 */ 226 #define STE_TXSTART_THRESH 0x1FFF 227 228 /* 229 * Number of bytes that must be present in the RX FIFO before 230 * an RX EARLY interrupt is generated. 231 */ 232 #define STE_RXEARLY_THRESH 0x1FFF 233 234 #define STE_WAKEEVENT_WAKEPKT_ENB 0x01 235 #define STE_WAKEEVENT_MAGICPKT_ENB 0x02 236 #define STE_WAKEEVENT_LINKEVT_ENB 0x04 237 #define STE_WAKEEVENT_WAKEPOLARITY 0x08 238 #define STE_WAKEEVENT_WAKEPKTEVENT 0x10 239 #define STE_WAKEEVENT_MAGICPKTEVENT 0x20 240 #define STE_WAKEEVENT_LINKEVENT 0x40 241 #define STE_WAKEEVENT_WAKEONLAN_ENB 0x80 242 243 #define STE_TXSTATUS_RECLAIMERR 0x02 244 #define STE_TXSTATUS_STATSOFLOW 0x04 245 #define STE_TXSTATUS_EXCESSCOLLS 0x08 246 #define STE_TXSTATUS_UNDERRUN 0x10 247 #define STE_TXSTATUS_TXINTR_REQ 0x40 248 #define STE_TXSTATUS_TXDONE 0x80 249 250 #define STE_ISRACK_INTLATCH 0x0001 251 #define STE_ISRACK_HOSTERR 0x0002 252 #define STE_ISRACK_TX_DONE 0x0004 253 #define STE_ISRACK_MACCTL_FRAME 0x0008 254 #define STE_ISRACK_RX_DONE 0x0010 255 #define STE_ISRACK_RX_EARLY 0x0020 256 #define STE_ISRACK_SOFTINTR 0x0040 257 #define STE_ISRACK_STATS_OFLOW 0x0080 258 #define STE_ISRACK_LINKEVENT 0x0100 259 #define STE_ISRACK_TX_DMADONE 0x0200 260 #define STE_ISRACK_RX_DMADONE 0x0400 261 262 #define STE_IMR_HOSTERR 0x0002 263 #define STE_IMR_TX_DONE 0x0004 264 #define STE_IMR_MACCTL_FRAME 0x0008 265 #define STE_IMR_RX_DONE 0x0010 266 #define STE_IMR_RX_EARLY 0x0020 267 #define STE_IMR_SOFTINTR 0x0040 268 #define STE_IMR_STATS_OFLOW 0x0080 269 #define STE_IMR_LINKEVENT 0x0100 270 #define STE_IMR_TX_DMADONE 0x0200 271 #define STE_IMR_RX_DMADONE 0x0400 272 273 #define STE_INTRS \ 274 (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE|STE_IMR_STATS_OFLOW| \ 275 STE_IMR_TX_DONE|STE_IMR_HOSTERR|STE_IMR_RX_EARLY) 276 277 #define STE_ISR_INTLATCH 0x0001 278 #define STE_ISR_HOSTERR 0x0002 279 #define STE_ISR_TX_DONE 0x0004 280 #define STE_ISR_MACCTL_FRAME 0x0008 281 #define STE_ISR_RX_DONE 0x0010 282 #define STE_ISR_RX_EARLY 0x0020 283 #define STE_ISR_SOFTINTR 0x0040 284 #define STE_ISR_STATS_OFLOW 0x0080 285 #define STE_ISR_LINKEVENT 0x0100 286 #define STE_ISR_TX_DMADONE 0x0200 287 #define STE_ISR_RX_DMADONE 0x0400 288 289 /* 290 * Note: the Sundance manual gives the impression that the's 291 * only one 32-bit MACCTL register. In fact, there are two 292 * 16-bit registers side by side, and you have to access them 293 * separately. 294 */ 295 #define STE_MACCTL0_IPG 0x0003 296 #define STE_MACCTL0_FULLDUPLEX 0x0020 297 #define STE_MACCTL0_RX_GIANTS 0x0040 298 #define STE_MACCTL0_FLOWCTL_ENABLE 0x0100 299 #define STE_MACCTL0_RX_FCS 0x0200 300 #define STE_MACCTL0_FIFOLOOPBK 0x0400 301 #define STE_MACCTL0_MACLOOPBK 0x0800 302 303 #define STE_MACCTL1_COLLDETECT 0x0001 304 #define STE_MACCTL1_CARRSENSE 0x0002 305 #define STE_MACCTL1_TX_BUSY 0x0004 306 #define STE_MACCTL1_TX_ERROR 0x0008 307 #define STE_MACCTL1_STATS_ENABLE 0x0020 308 #define STE_MACCTL1_STATS_DISABLE 0x0040 309 #define STE_MACCTL1_STATS_ENABLED 0x0080 310 #define STE_MACCTL1_TX_ENABLE 0x0100 311 #define STE_MACCTL1_TX_DISABLE 0x0200 312 #define STE_MACCTL1_TX_ENABLED 0x0400 313 #define STE_MACCTL1_RX_ENABLE 0x0800 314 #define STE_MACCTL1_RX_DISABLE 0x1000 315 #define STE_MACCTL1_RX_ENABLED 0x2000 316 #define STE_MACCTL1_PAUSED 0x4000 317 318 #define STE_IPG_96BT 0x00000000 319 #define STE_IPG_128BT 0x00000001 320 #define STE_IPG_224BT 0x00000002 321 #define STE_IPG_544BT 0x00000003 322 323 #define STE_RXMODE_UNICAST 0x01 324 #define STE_RXMODE_ALLMULTI 0x02 325 #define STE_RXMODE_BROADCAST 0x04 326 #define STE_RXMODE_PROMISC 0x08 327 #define STE_RXMODE_MULTIHASH 0x10 328 #define STE_RXMODE_ALLIPMULTI 0x20 329 330 #define STE_PHYCTL_MCLK 0x01 331 #define STE_PHYCTL_MDATA 0x02 332 #define STE_PHYCTL_MDIR 0x04 333 #define STE_PHYCTL_CLK25_DISABLE 0x08 334 #define STE_PHYCTL_DUPLEXPOLARITY 0x10 335 #define STE_PHYCTL_DUPLEXSTAT 0x20 336 #define STE_PHYCTL_SPEEDSTAT 0x40 337 #define STE_PHYCTL_LINKSTAT 0x80 338 339 /* 340 * EEPROM offsets. 341 */ 342 #define STE_EEADDR_CONFIGPARM 0x00 343 #define STE_EEADDR_ASICCTL 0x02 344 #define STE_EEADDR_SUBSYS_ID 0x04 345 #define STE_EEADDR_SUBVEN_ID 0x08 346 347 #define STE_EEADDR_NODE0 0x10 348 #define STE_EEADDR_NODE1 0x12 349 #define STE_EEADDR_NODE2 0x14 350 351 /* PCI registers */ 352 #define STE_PCI_VENDOR_ID 0x00 353 #define STE_PCI_DEVICE_ID 0x02 354 #define STE_PCI_COMMAND 0x04 355 #define STE_PCI_STATUS 0x06 356 #define STE_PCI_CLASSCODE 0x09 357 #define STE_PCI_LATENCY_TIMER 0x0D 358 #define STE_PCI_HEADER_TYPE 0x0E 359 #define STE_PCI_LOIO 0x10 360 #define STE_PCI_LOMEM 0x14 361 #define STE_PCI_BIOSROM 0x30 362 #define STE_PCI_INTLINE 0x3C 363 #define STE_PCI_INTPIN 0x3D 364 #define STE_PCI_MINGNT 0x3E 365 #define STE_PCI_MINLAT 0x0F 366 367 #define STE_PCI_CAPID 0x50 /* 8 bits */ 368 #define STE_PCI_NEXTPTR 0x51 /* 8 bits */ 369 #define STE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 370 #define STE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 371 372 #define STE_PSTATE_MASK 0x0003 373 #define STE_PSTATE_D0 0x0000 374 #define STE_PSTATE_D1 0x0002 375 #define STE_PSTATE_D2 0x0002 376 #define STE_PSTATE_D3 0x0003 377 #define STE_PME_EN 0x0010 378 #define STE_PME_STATUS 0x8000 379 380 381 struct ste_stats { 382 u_int32_t ste_rx_bytes; 383 u_int32_t ste_tx_bytes; 384 u_int16_t ste_tx_frames; 385 u_int16_t ste_rx_frames; 386 u_int8_t ste_carrsense_errs; 387 u_int8_t ste_late_colls; 388 u_int8_t ste_multi_colls; 389 u_int8_t ste_single_colls; 390 u_int8_t ste_tx_frames_defered; 391 u_int8_t ste_rx_lost_frames; 392 u_int8_t ste_tx_excess_defers; 393 u_int8_t ste_tx_abort_excess_colls; 394 u_int8_t ste_tx_bcast_frames; 395 u_int8_t ste_rx_bcast_frames; 396 u_int8_t ste_tx_mcast_frames; 397 u_int8_t ste_rx_mcast_frames; 398 }; 399 400 struct ste_frag { 401 u_int32_t ste_addr; 402 u_int32_t ste_len; 403 }; 404 405 #define STE_FRAG_LAST 0x80000000 406 #define STE_FRAG_LEN 0x00001FFF 407 408 #define STE_MAXFRAGS 63 409 410 struct ste_desc { 411 u_int32_t ste_next; 412 u_int32_t ste_ctl; 413 struct ste_frag ste_frags[STE_MAXFRAGS]; 414 }; 415 416 struct ste_desc_onefrag { 417 u_int32_t ste_next; 418 u_int32_t ste_status; 419 struct ste_frag ste_frag; 420 }; 421 422 #define STE_TXCTL_WORDALIGN 0x00000003 423 #define STE_TXCTL_FRAMEID 0x000003FC 424 #define STE_TXCTL_NOCRC 0x00002000 425 #define STE_TXCTL_TXINTR 0x00008000 426 #define STE_TXCTL_DMADONE 0x00010000 427 #define STE_TXCTL_DMAINTR 0x80000000 428 429 #define STE_RXSTAT_FRAMELEN 0x00001FFF 430 #define STE_RXSTAT_FRAME_ERR 0x00004000 431 #define STE_RXSTAT_DMADONE 0x00008000 432 #define STE_RXSTAT_FIFO_OFLOW 0x00010000 433 #define STE_RXSTAT_RUNT 0x00020000 434 #define STE_RXSTAT_ALIGNERR 0x00040000 435 #define STE_RXSTAT_CRCERR 0x00080000 436 #define STE_RXSTAT_GIANT 0x00100000 437 #define STE_RXSTAT_DRIBBLEBITS 0x00800000 438 #define STE_RXSTAT_DMA_OFLOW 0x01000000 439 #define STE_RXATAT_ONEBUF 0x10000000 440 441 /* 442 * register space access macros 443 */ 444 #define CSR_WRITE_4(sc, reg, val) \ 445 bus_space_write_4(sc->ste_btag, sc->ste_bhandle, reg, val) 446 #define CSR_WRITE_2(sc, reg, val) \ 447 bus_space_write_2(sc->ste_btag, sc->ste_bhandle, reg, val) 448 #define CSR_WRITE_1(sc, reg, val) \ 449 bus_space_write_1(sc->ste_btag, sc->ste_bhandle, reg, val) 450 451 #define CSR_READ_4(sc, reg) \ 452 bus_space_read_4(sc->ste_btag, sc->ste_bhandle, reg) 453 #define CSR_READ_2(sc, reg) \ 454 bus_space_read_2(sc->ste_btag, sc->ste_bhandle, reg) 455 #define CSR_READ_1(sc, reg) \ 456 bus_space_read_1(sc->ste_btag, sc->ste_bhandle, reg) 457 458 #define STE_TIMEOUT 1000 459 #define STE_MIN_FRAMELEN 60 460 #define STE_PACKET_SIZE 1536 461 #define ETHER_ALIGN 2 462 #define STE_RX_LIST_CNT 128 463 #define STE_TX_LIST_CNT 256 464 #define STE_INC(x, y) (x) = (x + 1) % y 465 466 struct ste_type { 467 u_int16_t ste_vid; 468 u_int16_t ste_did; 469 char *ste_name; 470 }; 471 472 struct ste_list_data { 473 struct ste_desc_onefrag ste_rx_list[STE_RX_LIST_CNT]; 474 struct ste_desc ste_tx_list[STE_TX_LIST_CNT]; 475 u_int8_t ste_pad[STE_MIN_FRAMELEN]; 476 }; 477 478 struct ste_chain { 479 struct ste_desc *ste_ptr; 480 struct mbuf *ste_mbuf; 481 struct ste_chain *ste_next; 482 struct ste_chain *ste_prev; 483 u_int32_t ste_phys; 484 }; 485 486 struct ste_chain_onefrag { 487 struct ste_desc_onefrag *ste_ptr; 488 struct mbuf *ste_mbuf; 489 struct ste_chain_onefrag *ste_next; 490 }; 491 492 struct ste_chain_data { 493 struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT]; 494 struct ste_chain ste_tx_chain[STE_TX_LIST_CNT]; 495 struct ste_chain_onefrag *ste_rx_head; 496 497 int ste_tx_prod; 498 int ste_tx_cons; 499 int ste_tx_cnt; 500 }; 501 502 struct ste_softc { 503 struct device sc_dev; 504 void *sc_ih; 505 struct arpcom arpcom; 506 struct timeout sc_stats_tmo; 507 mii_data_t sc_mii; 508 bus_space_tag_t ste_btag; 509 bus_space_handle_t ste_bhandle; 510 int ste_unit; 511 int ste_tx_thresh; 512 u_int8_t ste_link; 513 int ste_if_flags; 514 struct ste_list_data *ste_ldata; 515 caddr_t ste_ldata_ptr; 516 struct ste_chain_data ste_cdata; 517 }; 518 519 struct ste_mii_frame { 520 u_int8_t mii_stdelim; 521 u_int8_t mii_opcode; 522 u_int8_t mii_phyaddr; 523 u_int8_t mii_regaddr; 524 u_int8_t mii_turnaround; 525 u_int16_t mii_data; 526 }; 527 528 /* 529 * MII constants 530 */ 531 #define STE_MII_STARTDELIM 0x01 532 #define STE_MII_READOP 0x02 533 #define STE_MII_WRITEOP 0x01 534 #define STE_MII_TURNAROUND 0x02 535 536 #ifdef __alpha__ 537 #undef vtophys 538 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 539 #endif 540