1 /* $OpenBSD: if_ste.c,v 1.38 2006/07/08 19:56:38 brad Exp $ */ 2 /* 3 * Copyright (c) 1997, 1998, 1999 4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14 1999/12/07 20:14:42 wpaul Exp $ 34 */ 35 36 #include "bpfilter.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/mbuf.h> 41 #include <sys/protosw.h> 42 #include <sys/socket.h> 43 #include <sys/ioctl.h> 44 #include <sys/errno.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/timeout.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_types.h> 52 53 #ifdef INET 54 #include <netinet/in.h> 55 #include <netinet/in_systm.h> 56 #include <netinet/in_var.h> 57 #include <netinet/ip.h> 58 #include <netinet/if_ether.h> 59 #endif 60 61 #include <net/if_media.h> 62 63 #if NBPFILTER > 0 64 #include <net/bpf.h> 65 #endif 66 67 #include <uvm/uvm_extern.h> /* for vtophys */ 68 69 #include <sys/device.h> 70 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcidevs.h> 77 78 #define STE_USEIOSPACE 79 80 #include <dev/pci/if_stereg.h> 81 82 int ste_probe(struct device *, void *, void *); 83 void ste_attach(struct device *, struct device *, void *); 84 int ste_intr(void *); 85 void ste_shutdown(void *); 86 void ste_init(void *); 87 void ste_rxeoc(struct ste_softc *); 88 void ste_rxeof(struct ste_softc *); 89 void ste_txeoc(struct ste_softc *); 90 void ste_txeof(struct ste_softc *); 91 void ste_stats_update(void *); 92 void ste_stop(struct ste_softc *); 93 void ste_reset(struct ste_softc *); 94 int ste_ioctl(struct ifnet *, u_long, caddr_t); 95 int ste_encap(struct ste_softc *, struct ste_chain *, 96 struct mbuf *); 97 void ste_start(struct ifnet *); 98 void ste_watchdog(struct ifnet *); 99 int ste_newbuf(struct ste_softc *, 100 struct ste_chain_onefrag *, 101 struct mbuf *); 102 int ste_ifmedia_upd(struct ifnet *); 103 void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 104 105 void ste_mii_sync(struct ste_softc *); 106 void ste_mii_send(struct ste_softc *, u_int32_t, int); 107 int ste_mii_readreg(struct ste_softc *, 108 struct ste_mii_frame *); 109 int ste_mii_writereg(struct ste_softc *, 110 struct ste_mii_frame *); 111 int ste_miibus_readreg(struct device *, int, int); 112 void ste_miibus_writereg(struct device *, int, int, int); 113 void ste_miibus_statchg(struct device *); 114 115 int ste_eeprom_wait(struct ste_softc *); 116 int ste_read_eeprom(struct ste_softc *, caddr_t, int, 117 int, int); 118 void ste_wait(struct ste_softc *); 119 void ste_setmulti(struct ste_softc *); 120 int ste_init_rx_list(struct ste_softc *); 121 void ste_init_tx_list(struct ste_softc *); 122 123 #define STE_SETBIT4(sc, reg, x) \ 124 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 125 126 #define STE_CLRBIT4(sc, reg, x) \ 127 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 128 129 #define STE_SETBIT2(sc, reg, x) \ 130 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 131 132 #define STE_CLRBIT2(sc, reg, x) \ 133 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 134 135 #define STE_SETBIT1(sc, reg, x) \ 136 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 137 138 #define STE_CLRBIT1(sc, reg, x) \ 139 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 140 141 142 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 143 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 144 145 /* 146 * Sync the PHYs by setting data bit and strobing the clock 32 times. 147 */ 148 void ste_mii_sync(sc) 149 struct ste_softc *sc; 150 { 151 register int i; 152 153 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 154 155 for (i = 0; i < 32; i++) { 156 MII_SET(STE_PHYCTL_MCLK); 157 DELAY(1); 158 MII_CLR(STE_PHYCTL_MCLK); 159 DELAY(1); 160 } 161 162 return; 163 } 164 165 /* 166 * Clock a series of bits through the MII. 167 */ 168 void ste_mii_send(sc, bits, cnt) 169 struct ste_softc *sc; 170 u_int32_t bits; 171 int cnt; 172 { 173 int i; 174 175 MII_CLR(STE_PHYCTL_MCLK); 176 177 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 178 if (bits & i) { 179 MII_SET(STE_PHYCTL_MDATA); 180 } else { 181 MII_CLR(STE_PHYCTL_MDATA); 182 } 183 DELAY(1); 184 MII_CLR(STE_PHYCTL_MCLK); 185 DELAY(1); 186 MII_SET(STE_PHYCTL_MCLK); 187 } 188 } 189 190 /* 191 * Read an PHY register through the MII. 192 */ 193 int ste_mii_readreg(sc, frame) 194 struct ste_softc *sc; 195 struct ste_mii_frame *frame; 196 197 { 198 int i, ack, s; 199 200 s = splnet(); 201 202 /* 203 * Set up frame for RX. 204 */ 205 frame->mii_stdelim = STE_MII_STARTDELIM; 206 frame->mii_opcode = STE_MII_READOP; 207 frame->mii_turnaround = 0; 208 frame->mii_data = 0; 209 210 CSR_WRITE_2(sc, STE_PHYCTL, 0); 211 /* 212 * Turn on data xmit. 213 */ 214 MII_SET(STE_PHYCTL_MDIR); 215 216 ste_mii_sync(sc); 217 218 /* 219 * Send command/address info. 220 */ 221 ste_mii_send(sc, frame->mii_stdelim, 2); 222 ste_mii_send(sc, frame->mii_opcode, 2); 223 ste_mii_send(sc, frame->mii_phyaddr, 5); 224 ste_mii_send(sc, frame->mii_regaddr, 5); 225 226 /* Turn off xmit. */ 227 MII_CLR(STE_PHYCTL_MDIR); 228 229 /* Idle bit */ 230 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 231 DELAY(1); 232 MII_SET(STE_PHYCTL_MCLK); 233 DELAY(1); 234 235 /* Check for ack */ 236 MII_CLR(STE_PHYCTL_MCLK); 237 DELAY(1); 238 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 239 MII_SET(STE_PHYCTL_MCLK); 240 DELAY(1); 241 242 /* 243 * Now try reading data bits. If the ack failed, we still 244 * need to clock through 16 cycles to keep the PHY(s) in sync. 245 */ 246 if (ack) { 247 for(i = 0; i < 16; i++) { 248 MII_CLR(STE_PHYCTL_MCLK); 249 DELAY(1); 250 MII_SET(STE_PHYCTL_MCLK); 251 DELAY(1); 252 } 253 goto fail; 254 } 255 256 for (i = 0x8000; i; i >>= 1) { 257 MII_CLR(STE_PHYCTL_MCLK); 258 DELAY(1); 259 if (!ack) { 260 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 261 frame->mii_data |= i; 262 DELAY(1); 263 } 264 MII_SET(STE_PHYCTL_MCLK); 265 DELAY(1); 266 } 267 268 fail: 269 270 MII_CLR(STE_PHYCTL_MCLK); 271 DELAY(1); 272 MII_SET(STE_PHYCTL_MCLK); 273 DELAY(1); 274 275 splx(s); 276 277 if (ack) 278 return(1); 279 return(0); 280 } 281 282 /* 283 * Write to a PHY register through the MII. 284 */ 285 int ste_mii_writereg(sc, frame) 286 struct ste_softc *sc; 287 struct ste_mii_frame *frame; 288 289 { 290 int s; 291 292 s = splnet(); 293 /* 294 * Set up frame for TX. 295 */ 296 297 frame->mii_stdelim = STE_MII_STARTDELIM; 298 frame->mii_opcode = STE_MII_WRITEOP; 299 frame->mii_turnaround = STE_MII_TURNAROUND; 300 301 /* 302 * Turn on data output. 303 */ 304 MII_SET(STE_PHYCTL_MDIR); 305 306 ste_mii_sync(sc); 307 308 ste_mii_send(sc, frame->mii_stdelim, 2); 309 ste_mii_send(sc, frame->mii_opcode, 2); 310 ste_mii_send(sc, frame->mii_phyaddr, 5); 311 ste_mii_send(sc, frame->mii_regaddr, 5); 312 ste_mii_send(sc, frame->mii_turnaround, 2); 313 ste_mii_send(sc, frame->mii_data, 16); 314 315 /* Idle bit. */ 316 MII_SET(STE_PHYCTL_MCLK); 317 DELAY(1); 318 MII_CLR(STE_PHYCTL_MCLK); 319 DELAY(1); 320 321 /* 322 * Turn off xmit. 323 */ 324 MII_CLR(STE_PHYCTL_MDIR); 325 326 splx(s); 327 328 return(0); 329 } 330 331 int ste_miibus_readreg(self, phy, reg) 332 struct device *self; 333 int phy, reg; 334 { 335 struct ste_softc *sc = (struct ste_softc *)self; 336 struct ste_mii_frame frame; 337 338 if (sc->ste_one_phy && phy != 0) 339 return (0); 340 341 bzero((char *)&frame, sizeof(frame)); 342 343 frame.mii_phyaddr = phy; 344 frame.mii_regaddr = reg; 345 ste_mii_readreg(sc, &frame); 346 347 return(frame.mii_data); 348 } 349 350 void ste_miibus_writereg(self, phy, reg, data) 351 struct device *self; 352 int phy, reg, data; 353 { 354 struct ste_softc *sc = (struct ste_softc *)self; 355 struct ste_mii_frame frame; 356 357 bzero((char *)&frame, sizeof(frame)); 358 359 frame.mii_phyaddr = phy; 360 frame.mii_regaddr = reg; 361 frame.mii_data = data; 362 363 ste_mii_writereg(sc, &frame); 364 365 return; 366 } 367 368 void ste_miibus_statchg(self) 369 struct device *self; 370 { 371 struct ste_softc *sc = (struct ste_softc *)self; 372 struct mii_data *mii; 373 int fdx, fcur; 374 375 mii = &sc->sc_mii; 376 377 fcur = CSR_READ_2(sc, STE_MACCTL0) & STE_MACCTL0_FULLDUPLEX; 378 fdx = (mii->mii_media_active & IFM_GMASK) == IFM_FDX; 379 380 if ((fcur && fdx) || (! fcur && ! fdx)) 381 return; 382 383 STE_SETBIT4(sc, STE_DMACTL, 384 STE_DMACTL_RXDMA_STALL |STE_DMACTL_TXDMA_STALL); 385 ste_wait(sc); 386 387 if (fdx) 388 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 389 else 390 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 391 392 STE_SETBIT4(sc, STE_DMACTL, 393 STE_DMACTL_RXDMA_UNSTALL | STE_DMACTL_TXDMA_UNSTALL); 394 395 return; 396 } 397 398 int ste_ifmedia_upd(ifp) 399 struct ifnet *ifp; 400 { 401 struct ste_softc *sc; 402 struct mii_data *mii; 403 404 sc = ifp->if_softc; 405 mii = &sc->sc_mii; 406 sc->ste_link = 0; 407 if (mii->mii_instance) { 408 struct mii_softc *miisc; 409 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 410 mii_phy_reset(miisc); 411 } 412 mii_mediachg(mii); 413 414 return(0); 415 } 416 417 void ste_ifmedia_sts(ifp, ifmr) 418 struct ifnet *ifp; 419 struct ifmediareq *ifmr; 420 { 421 struct ste_softc *sc; 422 struct mii_data *mii; 423 424 sc = ifp->if_softc; 425 mii = &sc->sc_mii; 426 427 mii_pollstat(mii); 428 ifmr->ifm_active = mii->mii_media_active; 429 ifmr->ifm_status = mii->mii_media_status; 430 431 return; 432 } 433 434 void ste_wait(sc) 435 struct ste_softc *sc; 436 { 437 register int i; 438 439 for (i = 0; i < STE_TIMEOUT; i++) { 440 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 441 break; 442 } 443 444 if (i == STE_TIMEOUT) 445 printf("%s: command never completed!\n", sc->sc_dev.dv_xname); 446 447 return; 448 } 449 450 /* 451 * The EEPROM is slow: give it time to come ready after issuing 452 * it a command. 453 */ 454 int ste_eeprom_wait(sc) 455 struct ste_softc *sc; 456 { 457 int i; 458 459 DELAY(1000); 460 461 for (i = 0; i < 100; i++) { 462 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 463 DELAY(1000); 464 else 465 break; 466 } 467 468 if (i == 100) { 469 printf("%s: eeprom failed to come ready\n", 470 sc->sc_dev.dv_xname); 471 return(1); 472 } 473 474 return(0); 475 } 476 477 /* 478 * Read a sequence of words from the EEPROM. Note that ethernet address 479 * data is stored in the EEPROM in network byte order. 480 */ 481 int ste_read_eeprom(sc, dest, off, cnt, swap) 482 struct ste_softc *sc; 483 caddr_t dest; 484 int off; 485 int cnt; 486 int swap; 487 { 488 int err = 0, i; 489 u_int16_t word = 0, *ptr; 490 491 if (ste_eeprom_wait(sc)) 492 return(1); 493 494 for (i = 0; i < cnt; i++) { 495 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 496 err = ste_eeprom_wait(sc); 497 if (err) 498 break; 499 word = CSR_READ_2(sc, STE_EEPROM_DATA); 500 ptr = (u_int16_t *)(dest + (i * 2)); 501 if (swap) 502 *ptr = ntohs(word); 503 else 504 *ptr = word; 505 } 506 507 return(err ? 1 : 0); 508 } 509 510 void ste_setmulti(sc) 511 struct ste_softc *sc; 512 { 513 struct ifnet *ifp; 514 struct arpcom *ac = &sc->arpcom; 515 struct ether_multi *enm; 516 struct ether_multistep step; 517 int h = 0; 518 u_int32_t hashes[2] = { 0, 0 }; 519 520 ifp = &sc->arpcom.ac_if; 521 allmulti: 522 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 523 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 524 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 525 return; 526 } 527 528 /* first, zot all the existing hash bits */ 529 CSR_WRITE_2(sc, STE_MAR0, 0); 530 CSR_WRITE_2(sc, STE_MAR1, 0); 531 CSR_WRITE_2(sc, STE_MAR2, 0); 532 CSR_WRITE_2(sc, STE_MAR3, 0); 533 534 /* now program new ones */ 535 ETHER_FIRST_MULTI(step, ac, enm); 536 while (enm != NULL) { 537 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 538 ifp->if_flags |= IFF_ALLMULTI; 539 goto allmulti; 540 } 541 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3F; 542 if (h < 32) 543 hashes[0] |= (1 << h); 544 else 545 hashes[1] |= (1 << (h - 32)); 546 ETHER_NEXT_MULTI(step, enm); 547 } 548 549 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 550 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 551 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 552 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 553 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 554 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 555 556 return; 557 } 558 559 int ste_intr(xsc) 560 void *xsc; 561 { 562 struct ste_softc *sc; 563 struct ifnet *ifp; 564 u_int16_t status; 565 int claimed = 0; 566 567 sc = xsc; 568 ifp = &sc->arpcom.ac_if; 569 570 /* See if this is really our interrupt. */ 571 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 572 return claimed; 573 574 for (;;) { 575 status = CSR_READ_2(sc, STE_ISR_ACK); 576 577 if (!(status & STE_INTRS)) 578 break; 579 580 claimed = 1; 581 582 if (status & STE_ISR_RX_DMADONE) { 583 ste_rxeoc(sc); 584 ste_rxeof(sc); 585 } 586 587 if (status & STE_ISR_TX_DMADONE) 588 ste_txeof(sc); 589 590 if (status & STE_ISR_TX_DONE) 591 ste_txeoc(sc); 592 593 if (status & STE_ISR_STATS_OFLOW) { 594 timeout_del(&sc->sc_stats_tmo); 595 ste_stats_update(sc); 596 } 597 598 if (status & STE_ISR_LINKEVENT) 599 mii_pollstat(&sc->sc_mii); 600 601 if (status & STE_ISR_HOSTERR) { 602 ste_reset(sc); 603 ste_init(sc); 604 } 605 } 606 607 /* Re-enable interrupts */ 608 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 609 610 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 611 ste_start(ifp); 612 613 return claimed; 614 } 615 616 void 617 ste_rxeoc(struct ste_softc *sc) 618 { 619 struct ste_chain_onefrag *cur_rx; 620 621 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 622 cur_rx = sc->ste_cdata.ste_rx_head; 623 do { 624 cur_rx = cur_rx->ste_next; 625 /* If the ring is empty, just return. */ 626 if (cur_rx == sc->ste_cdata.ste_rx_head) 627 return; 628 } while (cur_rx->ste_ptr->ste_status == 0); 629 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 630 /* We've fallen behind the chip: catch it. */ 631 sc->ste_cdata.ste_rx_head = cur_rx; 632 } 633 } 634 } 635 636 /* 637 * A frame has been uploaded: pass the resulting mbuf chain up to 638 * the higher level protocols. 639 */ 640 void ste_rxeof(sc) 641 struct ste_softc *sc; 642 { 643 struct mbuf *m; 644 struct ifnet *ifp; 645 struct ste_chain_onefrag *cur_rx; 646 int total_len = 0, count=0; 647 u_int32_t rxstat; 648 649 ifp = &sc->arpcom.ac_if; 650 651 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 652 & STE_RXSTAT_DMADONE) { 653 if ((STE_RX_LIST_CNT - count) < 3) 654 break; 655 656 cur_rx = sc->ste_cdata.ste_rx_head; 657 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 658 659 /* 660 * If an error occurs, update stats, clear the 661 * status word and leave the mbuf cluster in place: 662 * it should simply get re-used next time this descriptor 663 * comes up in the ring. 664 */ 665 if (rxstat & STE_RXSTAT_FRAME_ERR) { 666 ifp->if_ierrors++; 667 cur_rx->ste_ptr->ste_status = 0; 668 continue; 669 } 670 671 /* 672 * If there error bit was not set, the upload complete 673 * bit should be set which means we have a valid packet. 674 * If not, something truly strange has happened. 675 */ 676 if (!(rxstat & STE_RXSTAT_DMADONE)) { 677 printf("%s: bad receive status -- packet dropped", 678 sc->sc_dev.dv_xname); 679 ifp->if_ierrors++; 680 cur_rx->ste_ptr->ste_status = 0; 681 continue; 682 } 683 684 /* No errors; receive the packet. */ 685 m = cur_rx->ste_mbuf; 686 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 687 688 /* 689 * Try to conjure up a new mbuf cluster. If that 690 * fails, it means we have an out of memory condition and 691 * should leave the buffer in place and continue. This will 692 * result in a lost packet, but there's little else we 693 * can do in this situation. 694 */ 695 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 696 ifp->if_ierrors++; 697 cur_rx->ste_ptr->ste_status = 0; 698 continue; 699 } 700 701 m->m_pkthdr.rcvif = ifp; 702 m->m_pkthdr.len = m->m_len = total_len; 703 704 ifp->if_ipackets++; 705 706 #if NBPFILTER > 0 707 if (ifp->if_bpf) 708 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 709 #endif 710 711 /* pass it on. */ 712 ether_input_mbuf(ifp, m); 713 714 cur_rx->ste_ptr->ste_status = 0; 715 count++; 716 } 717 718 return; 719 } 720 721 void ste_txeoc(sc) 722 struct ste_softc *sc; 723 { 724 u_int8_t txstat; 725 struct ifnet *ifp; 726 727 ifp = &sc->arpcom.ac_if; 728 729 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 730 STE_TXSTATUS_TXDONE) { 731 if (txstat & STE_TXSTATUS_UNDERRUN || 732 txstat & STE_TXSTATUS_EXCESSCOLLS || 733 txstat & STE_TXSTATUS_RECLAIMERR) { 734 ifp->if_oerrors++; 735 printf("%s: transmission error: %x\n", 736 sc->sc_dev.dv_xname, txstat); 737 738 ste_reset(sc); 739 ste_init(sc); 740 741 if (txstat & STE_TXSTATUS_UNDERRUN && 742 sc->ste_tx_thresh < ETHER_MAX_DIX_LEN) { 743 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 744 printf("%s: tx underrun, increasing tx" 745 " start threshold to %d bytes\n", 746 sc->sc_dev.dv_xname, sc->ste_tx_thresh); 747 } 748 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 749 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 750 (ETHER_MAX_DIX_LEN >> 4)); 751 } 752 ste_init(sc); 753 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 754 } 755 756 return; 757 } 758 759 void ste_txeof(sc) 760 struct ste_softc *sc; 761 { 762 struct ste_chain *cur_tx = NULL; 763 struct ifnet *ifp; 764 int idx; 765 766 ifp = &sc->arpcom.ac_if; 767 768 idx = sc->ste_cdata.ste_tx_cons; 769 while(idx != sc->ste_cdata.ste_tx_prod) { 770 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 771 772 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 773 break; 774 775 m_freem(cur_tx->ste_mbuf); 776 cur_tx->ste_mbuf = NULL; 777 ifp->if_flags &= ~IFF_OACTIVE; 778 ifp->if_opackets++; 779 780 STE_INC(idx, STE_TX_LIST_CNT); 781 } 782 783 sc->ste_cdata.ste_tx_cons = idx; 784 if (idx == sc->ste_cdata.ste_tx_prod) 785 ifp->if_timer = 0; 786 787 return; 788 } 789 790 void ste_stats_update(xsc) 791 void *xsc; 792 { 793 struct ste_softc *sc; 794 struct ifnet *ifp; 795 struct mii_data *mii; 796 int s; 797 798 s = splnet(); 799 800 sc = xsc; 801 ifp = &sc->arpcom.ac_if; 802 mii = &sc->sc_mii; 803 804 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 805 + CSR_READ_1(sc, STE_MULTI_COLLS) 806 + CSR_READ_1(sc, STE_SINGLE_COLLS); 807 808 if (!sc->ste_link) { 809 mii_pollstat(mii); 810 if (mii->mii_media_status & IFM_ACTIVE && 811 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 812 sc->ste_link++; 813 /* 814 * we don't get a call-back on re-init so do it 815 * otherwise we get stuck in the wrong link state 816 */ 817 ste_miibus_statchg((struct device *)sc); 818 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 819 ste_start(ifp); 820 } 821 } 822 823 timeout_add(&sc->sc_stats_tmo, hz); 824 splx(s); 825 826 return; 827 } 828 829 const struct pci_matchid ste_devices[] = { 830 { PCI_VENDOR_SUNDANCE, PCI_PRODUCT_SUNDANCE_ST201_1 }, 831 { PCI_VENDOR_SUNDANCE, PCI_PRODUCT_SUNDANCE_ST201_2 }, 832 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_550TX } 833 }; 834 835 /* 836 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 837 * IDs against our list and return a device name if we find a match. 838 */ 839 int ste_probe(parent, match, aux) 840 struct device *parent; 841 void *match, *aux; 842 { 843 return (pci_matchbyid((struct pci_attach_args *)aux, ste_devices, 844 sizeof(ste_devices)/sizeof(ste_devices[0]))); 845 } 846 847 /* 848 * Attach the interface. Allocate softc structures, do ifmedia 849 * setup and ethernet/BPF attach. 850 */ 851 void ste_attach(parent, self, aux) 852 struct device *parent, *self; 853 void *aux; 854 { 855 const char *intrstr = NULL; 856 pcireg_t command; 857 struct ste_softc *sc = (struct ste_softc *)self; 858 struct pci_attach_args *pa = aux; 859 pci_chipset_tag_t pc = pa->pa_pc; 860 pci_intr_handle_t ih; 861 struct ifnet *ifp; 862 bus_size_t size; 863 864 /* 865 * Handle power management nonsense. 866 */ 867 command = pci_conf_read(pc, pa->pa_tag, STE_PCI_CAPID) & 0x000000FF; 868 if (command == 0x01) { 869 870 command = pci_conf_read(pc, pa->pa_tag, STE_PCI_PWRMGMTCTRL); 871 if (command & STE_PSTATE_MASK) { 872 u_int32_t iobase, membase, irq; 873 874 /* Save important PCI config data. */ 875 iobase = pci_conf_read(pc, pa->pa_tag, STE_PCI_LOIO); 876 membase = pci_conf_read(pc, pa->pa_tag, STE_PCI_LOMEM); 877 irq = pci_conf_read(pc, pa->pa_tag, STE_PCI_INTLINE); 878 879 /* Reset the power state. */ 880 printf("%s: chip is in D%d power mode -- setting to D0\n", 881 sc->sc_dev.dv_xname, command & STE_PSTATE_MASK); 882 command &= 0xFFFFFFFC; 883 pci_conf_write(pc, pa->pa_tag, STE_PCI_PWRMGMTCTRL, command); 884 885 /* Restore PCI config data. */ 886 pci_conf_write(pc, pa->pa_tag, STE_PCI_LOIO, iobase); 887 pci_conf_write(pc, pa->pa_tag, STE_PCI_LOMEM, membase); 888 pci_conf_write(pc, pa->pa_tag, STE_PCI_INTLINE, irq); 889 } 890 } 891 892 /* 893 * Only use one PHY since this chip reports multiple 894 * Note on the DFE-550 the PHY is at 1 on the DFE-580 895 * it is at 0 & 1. It is rev 0x12. 896 */ 897 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_DLINK && 898 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_DLINK_550TX && 899 PCI_REVISION(pa->pa_class) == 0x12) 900 sc->ste_one_phy = 1; 901 902 /* 903 * Map control/status registers. 904 */ 905 906 #ifdef STE_USEIOSPACE 907 if (pci_mapreg_map(pa, STE_PCI_LOIO, 908 PCI_MAPREG_TYPE_IO, 0, 909 &sc->ste_btag, &sc->ste_bhandle, NULL, &size, 0)) { 910 printf(": can't map i/o space\n"); 911 return; 912 } 913 #else 914 if (pci_mapreg_map(pa, STE_PCI_LOMEM, 915 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 916 &sc->ste_btag, &sc->ste_bhandle, NULL, &size, 0)) { 917 printf(": can't map mem space\n"); 918 return; 919 } 920 #endif 921 922 /* Allocate interrupt */ 923 if (pci_intr_map(pa, &ih)) { 924 printf(": couldn't map interrupt\n"); 925 goto fail_1; 926 } 927 intrstr = pci_intr_string(pc, ih); 928 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc, 929 self->dv_xname); 930 if (sc->sc_ih == NULL) { 931 printf(": couldn't establish interrupt"); 932 if (intrstr != NULL) 933 printf(" at %s", intrstr); 934 printf("\n"); 935 goto fail_1; 936 } 937 printf(": %s", intrstr); 938 939 /* Reset the adapter. */ 940 ste_reset(sc); 941 942 /* 943 * Get station address from the EEPROM. 944 */ 945 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 946 STE_EEADDR_NODE0, 3, 0)) { 947 printf(": failed to read station address\n"); 948 goto fail_2; 949 } 950 951 printf(", address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); 952 953 sc->ste_ldata_ptr = malloc(sizeof(struct ste_list_data) + 8, 954 M_DEVBUF, M_DONTWAIT); 955 if (sc->ste_ldata_ptr == NULL) { 956 printf(": no memory for list buffers!\n"); 957 goto fail_2; 958 } 959 960 sc->ste_ldata = (struct ste_list_data *)sc->ste_ldata_ptr; 961 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 962 963 ifp = &sc->arpcom.ac_if; 964 ifp->if_softc = sc; 965 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 966 ifp->if_ioctl = ste_ioctl; 967 ifp->if_start = ste_start; 968 ifp->if_watchdog = ste_watchdog; 969 ifp->if_baudrate = 10000000; 970 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 971 IFQ_SET_READY(&ifp->if_snd); 972 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 973 ifp->if_capabilities = IFCAP_VLAN_MTU; 974 975 sc->ste_tx_thresh = STE_TXSTART_THRESH; 976 977 sc->sc_mii.mii_ifp = ifp; 978 sc->sc_mii.mii_readreg = ste_miibus_readreg; 979 sc->sc_mii.mii_writereg = ste_miibus_writereg; 980 sc->sc_mii.mii_statchg = ste_miibus_statchg; 981 ifmedia_init(&sc->sc_mii.mii_media, 0, ste_ifmedia_upd,ste_ifmedia_sts); 982 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 983 0); 984 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 985 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 986 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 987 } else 988 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 989 990 /* 991 * Call MI attach routines. 992 */ 993 if_attach(ifp); 994 ether_ifattach(ifp); 995 996 shutdownhook_establish(ste_shutdown, sc); 997 return; 998 999 fail_2: 1000 pci_intr_disestablish(pc, sc->sc_ih); 1001 1002 fail_1: 1003 bus_space_unmap(sc->ste_btag, sc->ste_bhandle, size); 1004 } 1005 1006 int ste_newbuf(sc, c, m) 1007 struct ste_softc *sc; 1008 struct ste_chain_onefrag *c; 1009 struct mbuf *m; 1010 { 1011 struct mbuf *m_new = NULL; 1012 1013 if (m == NULL) { 1014 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1015 if (m_new == NULL) 1016 return(ENOBUFS); 1017 MCLGET(m_new, M_DONTWAIT); 1018 if (!(m_new->m_flags & M_EXT)) { 1019 m_freem(m_new); 1020 return(ENOBUFS); 1021 } 1022 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1023 } else { 1024 m_new = m; 1025 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1026 m_new->m_data = m_new->m_ext.ext_buf; 1027 } 1028 1029 m_adj(m_new, ETHER_ALIGN); 1030 1031 c->ste_mbuf = m_new; 1032 c->ste_ptr->ste_status = 0; 1033 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, vaddr_t)); 1034 c->ste_ptr->ste_frag.ste_len = (ETHER_MAX_DIX_LEN + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1035 1036 return(0); 1037 } 1038 1039 int ste_init_rx_list(sc) 1040 struct ste_softc *sc; 1041 { 1042 struct ste_chain_data *cd; 1043 struct ste_list_data *ld; 1044 int i; 1045 1046 cd = &sc->ste_cdata; 1047 ld = sc->ste_ldata; 1048 1049 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1050 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1051 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1052 return(ENOBUFS); 1053 if (i == (STE_RX_LIST_CNT - 1)) { 1054 cd->ste_rx_chain[i].ste_next = 1055 &cd->ste_rx_chain[0]; 1056 ld->ste_rx_list[i].ste_next = 1057 vtophys((vaddr_t)&ld->ste_rx_list[0]); 1058 } else { 1059 cd->ste_rx_chain[i].ste_next = 1060 &cd->ste_rx_chain[i + 1]; 1061 ld->ste_rx_list[i].ste_next = 1062 vtophys((vaddr_t)&ld->ste_rx_list[i + 1]); 1063 } 1064 ld->ste_rx_list[i].ste_status = 0; 1065 } 1066 1067 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1068 1069 return(0); 1070 } 1071 1072 void ste_init_tx_list(sc) 1073 struct ste_softc *sc; 1074 { 1075 struct ste_chain_data *cd; 1076 struct ste_list_data *ld; 1077 int i; 1078 1079 cd = &sc->ste_cdata; 1080 ld = sc->ste_ldata; 1081 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1082 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1083 cd->ste_tx_chain[i].ste_phys = vtophys((vaddr_t)&ld->ste_tx_list[i]); 1084 if (i == (STE_TX_LIST_CNT - 1)) 1085 cd->ste_tx_chain[i].ste_next = 1086 &cd->ste_tx_chain[0]; 1087 else 1088 cd->ste_tx_chain[i].ste_next = 1089 &cd->ste_tx_chain[i + 1]; 1090 } 1091 1092 bzero((char *)ld->ste_tx_list, 1093 sizeof(struct ste_desc) * STE_TX_LIST_CNT); 1094 1095 cd->ste_tx_prod = 0; 1096 cd->ste_tx_cons = 0; 1097 1098 return; 1099 } 1100 1101 void ste_init(xsc) 1102 void *xsc; 1103 { 1104 struct ste_softc *sc = (struct ste_softc *)xsc; 1105 struct ifnet *ifp = &sc->arpcom.ac_if; 1106 struct mii_data *mii; 1107 int i, s; 1108 1109 s = splnet(); 1110 1111 ste_stop(sc); 1112 1113 mii = &sc->sc_mii; 1114 1115 /* Init our MAC address */ 1116 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1117 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1118 } 1119 1120 /* Init RX list */ 1121 if (ste_init_rx_list(sc) == ENOBUFS) { 1122 printf("%s: initialization failed: no " 1123 "memory for RX buffers\n", sc->sc_dev.dv_xname); 1124 ste_stop(sc); 1125 splx(s); 1126 return; 1127 } 1128 1129 /* Set RX polling interval */ 1130 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1131 1132 /* Init TX descriptors */ 1133 ste_init_tx_list(sc); 1134 1135 /* Set the TX freethresh value */ 1136 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, ETHER_MAX_DIX_LEN >> 8); 1137 1138 /* Set the TX start threshold for best performance. */ 1139 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1140 1141 /* Set the TX reclaim threshold. */ 1142 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (ETHER_MAX_DIX_LEN >> 4)); 1143 1144 /* Set up the RX filter. */ 1145 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1146 1147 /* If we want promiscuous mode, set the allframes bit. */ 1148 if (ifp->if_flags & IFF_PROMISC) { 1149 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1150 } else { 1151 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1152 } 1153 1154 /* Set capture broadcast bit to accept broadcast frames. */ 1155 if (ifp->if_flags & IFF_BROADCAST) { 1156 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1157 } else { 1158 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1159 } 1160 1161 ste_setmulti(sc); 1162 1163 /* Load the address of the RX list. */ 1164 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1165 ste_wait(sc); 1166 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1167 vtophys((vaddr_t)&sc->ste_ldata->ste_rx_list[0])); 1168 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1169 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1170 1171 /* Set TX polling interval (defer until we TX first packet) */ 1172 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1173 1174 /* Load address of the TX list */ 1175 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1176 ste_wait(sc); 1177 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1178 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1179 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1180 ste_wait(sc); 1181 sc->ste_tx_prev=NULL; 1182 1183 /* Enable receiver and transmitter */ 1184 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1185 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1186 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1187 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1188 1189 /* Enable stats counters. */ 1190 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1191 1192 /* Enable interrupts. */ 1193 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1194 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1195 1196 /* Accept VLAN length packets */ 1197 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, 1198 ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1199 1200 ste_ifmedia_upd(ifp); 1201 1202 ifp->if_flags |= IFF_RUNNING; 1203 ifp->if_flags &= ~IFF_OACTIVE; 1204 1205 splx(s); 1206 1207 timeout_set(&sc->sc_stats_tmo, ste_stats_update, sc); 1208 timeout_add(&sc->sc_stats_tmo, hz); 1209 1210 return; 1211 } 1212 1213 void ste_stop(sc) 1214 struct ste_softc *sc; 1215 { 1216 int i; 1217 struct ifnet *ifp; 1218 1219 ifp = &sc->arpcom.ac_if; 1220 1221 timeout_del(&sc->sc_stats_tmo); 1222 1223 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1224 1225 CSR_WRITE_2(sc, STE_IMR, 0); 1226 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1227 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1228 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1229 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1230 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1231 ste_wait(sc); 1232 /* 1233 * Try really hard to stop the RX engine or under heavy RX 1234 * data chip will write into de-allocated memory. 1235 */ 1236 ste_reset(sc); 1237 1238 sc->ste_link = 0; 1239 1240 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1241 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1242 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1243 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1244 } 1245 } 1246 1247 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1248 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1249 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1250 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1251 } 1252 } 1253 1254 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1255 1256 return; 1257 } 1258 1259 void ste_reset(sc) 1260 struct ste_softc *sc; 1261 { 1262 int i; 1263 1264 STE_SETBIT4(sc, STE_ASICCTL, 1265 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1266 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1267 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1268 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1269 STE_ASICCTL_EXTRESET_RESET); 1270 1271 DELAY(100000); 1272 1273 for (i = 0; i < STE_TIMEOUT; i++) { 1274 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1275 break; 1276 } 1277 1278 if (i == STE_TIMEOUT) 1279 printf("%s: global reset never completed\n", 1280 sc->sc_dev.dv_xname); 1281 } 1282 1283 int ste_ioctl(ifp, command, data) 1284 struct ifnet *ifp; 1285 u_long command; 1286 caddr_t data; 1287 { 1288 struct ste_softc *sc = ifp->if_softc; 1289 struct ifreq *ifr = (struct ifreq *) data; 1290 struct ifaddr *ifa = (struct ifaddr *)data; 1291 struct mii_data *mii; 1292 int s, error = 0; 1293 1294 s = splnet(); 1295 1296 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 1297 splx(s); 1298 return error; 1299 } 1300 1301 switch(command) { 1302 case SIOCSIFADDR: 1303 ifp->if_flags |= IFF_UP; 1304 switch (ifa->ifa_addr->sa_family) { 1305 case AF_INET: 1306 ste_init(sc); 1307 arp_ifinit(&sc->arpcom, ifa); 1308 break; 1309 default: 1310 ste_init(sc); 1311 break; 1312 } 1313 break; 1314 case SIOCSIFFLAGS: 1315 if (ifp->if_flags & IFF_UP) { 1316 if (ifp->if_flags & IFF_RUNNING && 1317 ifp->if_flags & IFF_PROMISC && 1318 !(sc->ste_if_flags & IFF_PROMISC)) { 1319 STE_SETBIT1(sc, STE_RX_MODE, 1320 STE_RXMODE_PROMISC); 1321 } else if (ifp->if_flags & IFF_RUNNING && 1322 !(ifp->if_flags & IFF_PROMISC) && 1323 sc->ste_if_flags & IFF_PROMISC) { 1324 STE_CLRBIT1(sc, STE_RX_MODE, 1325 STE_RXMODE_PROMISC); 1326 } 1327 if (ifp->if_flags & IFF_RUNNING && 1328 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1329 ste_setmulti(sc); 1330 if (!(ifp->if_flags & IFF_RUNNING)) { 1331 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1332 ste_init(sc); 1333 } 1334 } else { 1335 if (ifp->if_flags & IFF_RUNNING) 1336 ste_stop(sc); 1337 } 1338 sc->ste_if_flags = ifp->if_flags; 1339 error = 0; 1340 break; 1341 case SIOCADDMULTI: 1342 case SIOCDELMULTI: 1343 error = (command == SIOCADDMULTI) ? 1344 ether_addmulti(ifr, &sc->arpcom) : 1345 ether_delmulti(ifr, &sc->arpcom); 1346 1347 if (error == ENETRESET) { 1348 /* 1349 * Multicast list has changed; set the hardware 1350 * filter accordingly. 1351 */ 1352 if (ifp->if_flags & IFF_RUNNING) 1353 ste_setmulti(sc); 1354 error = 0; 1355 } 1356 break; 1357 case SIOCGIFMEDIA: 1358 case SIOCSIFMEDIA: 1359 mii = &sc->sc_mii; 1360 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1361 break; 1362 default: 1363 error = ENOTTY; 1364 break; 1365 } 1366 1367 splx(s); 1368 1369 return(error); 1370 } 1371 1372 int ste_encap(sc, c, m_head) 1373 struct ste_softc *sc; 1374 struct ste_chain *c; 1375 struct mbuf *m_head; 1376 { 1377 int frag = 0; 1378 struct ste_frag *f = NULL; 1379 struct mbuf *m; 1380 struct ste_desc *d; 1381 1382 d = c->ste_ptr; 1383 d->ste_ctl = 0; 1384 1385 encap_retry: 1386 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1387 if (m->m_len != 0) { 1388 if (frag == STE_MAXFRAGS) 1389 break; 1390 f = &d->ste_frags[frag]; 1391 f->ste_addr = vtophys(mtod(m, vaddr_t)); 1392 f->ste_len = m->m_len; 1393 frag++; 1394 } 1395 } 1396 1397 if (m != NULL) { 1398 struct mbuf *mn; 1399 1400 /* 1401 * We ran out of segments. We have to recopy this 1402 * mbuf chain first. Bail out if we can't get the 1403 * new buffers. 1404 */ 1405 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1406 if (mn == NULL) { 1407 m_freem(m_head); 1408 return ENOMEM; 1409 } 1410 if (m_head->m_pkthdr.len > MHLEN) { 1411 MCLGET(mn, M_DONTWAIT); 1412 if ((mn->m_flags & M_EXT) == 0) { 1413 m_freem(mn); 1414 m_freem(m_head); 1415 return ENOMEM; 1416 } 1417 } 1418 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1419 mtod(mn, caddr_t)); 1420 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1421 m_freem(m_head); 1422 m_head = mn; 1423 goto encap_retry; 1424 } 1425 1426 c->ste_mbuf = m_head; 1427 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1428 d->ste_ctl = 1; 1429 1430 return(0); 1431 } 1432 1433 void ste_start(ifp) 1434 struct ifnet *ifp; 1435 { 1436 struct ste_softc *sc; 1437 struct mbuf *m_head = NULL; 1438 struct ste_chain *cur_tx; 1439 int idx; 1440 1441 sc = ifp->if_softc; 1442 1443 if (!sc->ste_link) 1444 return; 1445 1446 if (ifp->if_flags & IFF_OACTIVE) 1447 return; 1448 1449 idx = sc->ste_cdata.ste_tx_prod; 1450 1451 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1452 /* 1453 * We cannot re-use the last (free) descriptor; 1454 * the chip may not have read its ste_next yet. 1455 */ 1456 if (STE_NEXT(idx, STE_TX_LIST_CNT) == 1457 sc->ste_cdata.ste_tx_cons) { 1458 ifp->if_flags |= IFF_OACTIVE; 1459 break; 1460 } 1461 1462 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1463 if (m_head == NULL) 1464 break; 1465 1466 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1467 1468 if (ste_encap(sc, cur_tx, m_head) != 0) 1469 break; 1470 1471 cur_tx->ste_ptr->ste_next = 0; 1472 1473 if (sc->ste_tx_prev == NULL) { 1474 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1475 /* Load address of the TX list */ 1476 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1477 ste_wait(sc); 1478 1479 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1480 vtophys((vaddr_t)&sc->ste_ldata->ste_tx_list[0])); 1481 1482 /* Set TX polling interval to start TX engine */ 1483 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1484 1485 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1486 ste_wait(sc); 1487 }else{ 1488 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1489 sc->ste_tx_prev->ste_ptr->ste_next 1490 = cur_tx->ste_phys; 1491 } 1492 1493 sc->ste_tx_prev = cur_tx; 1494 1495 #if NBPFILTER > 0 1496 /* 1497 * If there's a BPF listener, bounce a copy of this frame 1498 * to him. 1499 */ 1500 if (ifp->if_bpf) 1501 bpf_mtap(ifp->if_bpf, cur_tx->ste_mbuf, 1502 BPF_DIRECTION_OUT); 1503 #endif 1504 1505 STE_INC(idx, STE_TX_LIST_CNT); 1506 ifp->if_timer = 5; 1507 } 1508 sc->ste_cdata.ste_tx_prod = idx; 1509 1510 return; 1511 } 1512 1513 void ste_watchdog(ifp) 1514 struct ifnet *ifp; 1515 { 1516 struct ste_softc *sc; 1517 1518 sc = ifp->if_softc; 1519 1520 ifp->if_oerrors++; 1521 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1522 1523 ste_txeoc(sc); 1524 ste_txeof(sc); 1525 ste_rxeoc(sc); 1526 ste_rxeof(sc); 1527 ste_reset(sc); 1528 ste_init(sc); 1529 1530 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1531 ste_start(ifp); 1532 1533 return; 1534 } 1535 1536 void ste_shutdown(v) 1537 void *v; 1538 { 1539 struct ste_softc *sc = (struct ste_softc *)v; 1540 1541 ste_stop(sc); 1542 } 1543 1544 struct cfattach ste_ca = { 1545 sizeof(struct ste_softc), ste_probe, ste_attach 1546 }; 1547 1548 struct cfdriver ste_cd = { 1549 0, "ste", DV_IFNET 1550 }; 1551 1552