1 /* $OpenBSD: if_sk.c,v 1.31 2003/05/14 01:54:15 nate Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 39 * the SK-984x series adapters, both single port and dual port. 40 * References: 41 * The XaQti XMAC II datasheet, 42 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 43 * The SysKonnect GEnesis manual, http://www.syskonnect.com 44 * 45 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 46 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 47 * convenience to others until Vitesse corrects this problem: 48 * 49 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 50 * 51 * Written by Bill Paul <wpaul@ee.columbia.edu> 52 * Department of Electrical Engineering 53 * Columbia University, New York City 54 */ 55 56 /* 57 * The SysKonnect gigabit ethernet adapters consist of two main 58 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 59 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 60 * components and a PHY while the GEnesis controller provides a PCI 61 * interface with DMA support. Each card may have between 512K and 62 * 2MB of SRAM on board depending on the configuration. 63 * 64 * The SysKonnect GEnesis controller can have either one or two XMAC 65 * chips connected to it, allowing single or dual port NIC configurations. 66 * SysKonnect has the distinction of being the only vendor on the market 67 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 68 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 69 * XMAC registers. This driver takes advantage of these features to allow 70 * both XMACs to operate as independent interfaces. 71 */ 72 73 #include "bpfilter.h" 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/sockio.h> 78 #include <sys/mbuf.h> 79 #include <sys/malloc.h> 80 #include <sys/kernel.h> 81 #include <sys/socket.h> 82 #include <sys/device.h> 83 #include <sys/queue.h> 84 85 #include <net/if.h> 86 #include <net/if_dl.h> 87 #include <net/if_types.h> 88 89 #ifdef INET 90 #include <netinet/in.h> 91 #include <netinet/in_systm.h> 92 #include <netinet/in_var.h> 93 #include <netinet/ip.h> 94 #include <netinet/if_ether.h> 95 #endif 96 97 #include <net/if_media.h> 98 99 #if NBPFILTER > 0 100 #include <net/bpf.h> 101 #endif 102 103 #include <dev/mii/mii.h> 104 #include <dev/mii/miivar.h> 105 #include <dev/mii/brgphyreg.h> 106 107 #include <dev/pci/pcireg.h> 108 #include <dev/pci/pcivar.h> 109 #include <dev/pci/pcidevs.h> 110 111 #define SK_USEIOSPACE 112 #define SK_VERBOSE 113 114 #include <dev/pci/if_skreg.h> 115 #include <dev/pci/xmaciireg.h> 116 117 int skc_probe(struct device *, void *, void *); 118 void skc_attach(struct device *, struct device *self, void *aux); 119 int sk_probe(struct device *, void *, void *); 120 void sk_attach(struct device *, struct device *self, void *aux); 121 int skcprint(void *, const char *); 122 int sk_attach_xmac(struct sk_softc *, int); 123 int sk_intr(void *); 124 void sk_intr_bcom(struct sk_if_softc *); 125 void sk_intr_xmac(struct sk_if_softc *); 126 void sk_rxeof(struct sk_if_softc *); 127 void sk_txeof(struct sk_if_softc *); 128 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 129 void sk_start(struct ifnet *); 130 int sk_ioctl(struct ifnet *, u_long, caddr_t); 131 void sk_init(void *); 132 void sk_init_xmac(struct sk_if_softc *); 133 void sk_stop(struct sk_if_softc *); 134 void sk_watchdog(struct ifnet *); 135 void sk_shutdown(void *); 136 int sk_ifmedia_upd(struct ifnet *); 137 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 138 void sk_reset(struct sk_softc *); 139 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 140 int sk_init_rx_ring(struct sk_if_softc *); 141 int sk_init_tx_ring(struct sk_if_softc *); 142 u_int32_t sk_win_read_4(struct sk_softc *, int); 143 u_int16_t sk_win_read_2(struct sk_softc *, int); 144 u_int8_t sk_win_read_1(struct sk_softc *, int); 145 void sk_win_write_4(struct sk_softc *, int, u_int32_t); 146 void sk_win_write_2(struct sk_softc *, int, u_int32_t); 147 void sk_win_write_1(struct sk_softc *, int, u_int32_t); 148 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 149 void sk_vpd_read_res(struct sk_softc *, 150 struct vpd_res *, int); 151 void sk_vpd_read(struct sk_softc *); 152 153 int sk_miibus_readreg(struct device *, int, int); 154 void sk_miibus_writereg(struct device *, int, int, int); 155 void sk_miibus_statchg(struct device *); 156 157 u_int32_t sk_calchash(caddr_t); 158 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 159 void sk_setmulti(struct sk_if_softc *); 160 void sk_tick(void *); 161 162 #define SK_SETBIT(sc, reg, x) \ 163 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 164 165 #define SK_CLRBIT(sc, reg, x) \ 166 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 167 168 #define SK_WIN_SETBIT_4(sc, reg, x) \ 169 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 170 171 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 172 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 173 174 #define SK_WIN_SETBIT_2(sc, reg, x) \ 175 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 176 177 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 178 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 179 180 u_int32_t 181 sk_win_read_4(struct sk_softc *sc, int reg) 182 { 183 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 184 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 185 } 186 187 u_int16_t 188 sk_win_read_2(struct sk_softc *sc, int reg) 189 { 190 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 191 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 192 } 193 194 u_int8_t 195 sk_win_read_1(struct sk_softc *sc, int reg) 196 { 197 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 198 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 199 } 200 201 void 202 sk_win_write_4(struct sk_softc *sc, int reg, u_int32_t val) 203 { 204 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 205 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 206 } 207 208 void 209 sk_win_write_2(struct sk_softc *sc, int reg, u_int32_t val) 210 { 211 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 212 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), (u_int32_t)val); 213 } 214 215 void 216 sk_win_write_1(struct sk_softc *sc, int reg, u_int32_t val) 217 { 218 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 219 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 220 } 221 222 /* 223 * The VPD EEPROM contains Vital Product Data, as suggested in 224 * the PCI 2.1 specification. The VPD data is separared into areas 225 * denoted by resource IDs. The SysKonnect VPD contains an ID string 226 * resource (the name of the adapter), a read-only area resource 227 * containing various key/data fields and a read/write area which 228 * can be used to store asset management information or log messages. 229 * We read the ID string and read-only into buffers attached to 230 * the controller softc structure for later use. At the moment, 231 * we only use the ID string during sk_attach(). 232 */ 233 u_int8_t 234 sk_vpd_readbyte(struct sk_softc *sc, int addr) 235 { 236 int i; 237 238 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 239 for (i = 0; i < SK_TIMEOUT; i++) { 240 DELAY(1); 241 if (sk_win_read_2(sc, 242 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 243 break; 244 } 245 246 if (i == SK_TIMEOUT) 247 return(0); 248 249 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 250 } 251 252 void 253 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 254 { 255 int i; 256 u_int8_t *ptr; 257 258 ptr = (u_int8_t *)res; 259 for (i = 0; i < sizeof(struct vpd_res); i++) 260 ptr[i] = sk_vpd_readbyte(sc, i + addr); 261 } 262 263 void 264 sk_vpd_read(struct sk_softc *sc) 265 { 266 int pos = 0, i; 267 struct vpd_res res; 268 269 if (sc->sk_vpd_prodname != NULL) 270 free(sc->sk_vpd_prodname, M_DEVBUF); 271 if (sc->sk_vpd_readonly != NULL) 272 free(sc->sk_vpd_readonly, M_DEVBUF); 273 sc->sk_vpd_prodname = NULL; 274 sc->sk_vpd_readonly = NULL; 275 276 sk_vpd_read_res(sc, &res, pos); 277 278 if (res.vr_id != VPD_RES_ID) { 279 printf("%s: bad VPD resource id: expected %x got %x\n", 280 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 281 return; 282 } 283 284 pos += sizeof(res); 285 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 286 if (sc->sk_vpd_prodname == NULL) 287 panic("sk_vpd_read"); 288 for (i = 0; i < res.vr_len; i++) 289 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 290 sc->sk_vpd_prodname[i] = '\0'; 291 pos += i; 292 293 sk_vpd_read_res(sc, &res, pos); 294 295 if (res.vr_id != VPD_RES_READ) { 296 printf("%s: bad VPD resource id: expected %x got %x\n", 297 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 298 return; 299 } 300 301 pos += sizeof(res); 302 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 303 if (sc->sk_vpd_readonly == NULL) 304 panic("sk_vpd_read"); 305 for (i = 0; i < res.vr_len + 1; i++) 306 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 307 } 308 309 int 310 sk_miibus_readreg(struct device *dev, int phy, int reg) 311 { 312 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 313 int i; 314 315 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 316 return(0); 317 318 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 319 SK_XM_READ_2(sc_if, XM_PHY_DATA); 320 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 321 for (i = 0; i < SK_TIMEOUT; i++) { 322 DELAY(1); 323 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 324 XM_MMUCMD_PHYDATARDY) 325 break; 326 } 327 328 if (i == SK_TIMEOUT) { 329 printf("%s: phy failed to come ready\n", 330 sc_if->sk_dev.dv_xname); 331 return(0); 332 } 333 } 334 DELAY(1); 335 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 336 } 337 338 void 339 sk_miibus_writereg(struct device *dev, int phy, int reg, int val) 340 { 341 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 342 int i; 343 344 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 345 for (i = 0; i < SK_TIMEOUT; i++) { 346 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 347 break; 348 } 349 350 if (i == SK_TIMEOUT) { 351 printf("%s: phy failed to come ready\n", 352 sc_if->sk_dev.dv_xname); 353 return; 354 } 355 356 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 357 for (i = 0; i < SK_TIMEOUT; i++) { 358 DELAY(1); 359 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 360 break; 361 } 362 363 if (i == SK_TIMEOUT) 364 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 365 } 366 367 void 368 sk_miibus_statchg(struct device *dev) 369 { 370 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 371 struct mii_data *mii = &sc_if->sk_mii; 372 373 /* 374 * If this is a GMII PHY, manually set the XMAC's 375 * duplex mode accordingly. 376 */ 377 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 378 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 379 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 380 } else { 381 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 382 } 383 } 384 } 385 386 #define SK_POLY 0xEDB88320 387 #define SK_BITS 6 388 389 u_int32_t 390 sk_calchash(caddr_t addr) 391 { 392 u_int32_t idx, bit, data, crc; 393 394 /* Compute CRC for the address value. */ 395 crc = 0xFFFFFFFF; /* initial value */ 396 397 for (idx = 0; idx < 6; idx++) { 398 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 399 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0); 400 } 401 402 return (~crc & ((1 << SK_BITS) - 1)); 403 } 404 405 void 406 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 407 { 408 int base = XM_RXFILT_ENTRY(slot); 409 410 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 411 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 412 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 413 } 414 415 void 416 sk_setmulti(struct sk_if_softc *sc_if) 417 { 418 struct ifnet *ifp = &sc_if->arpcom.ac_if; 419 u_int32_t hashes[2] = { 0, 0 }; 420 int h, i; 421 struct arpcom *ac = &sc_if->arpcom; 422 struct ether_multi *enm; 423 struct ether_multistep step; 424 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 425 426 /* First, zot all the existing filters. */ 427 for (i = 1; i < XM_RXFILT_MAX; i++) 428 sk_setfilt(sc_if, (caddr_t)&dummy, i); 429 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 430 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 431 432 /* Now program new ones. */ 433 allmulti: 434 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 435 hashes[0] = 0xFFFFFFFF; 436 hashes[1] = 0xFFFFFFFF; 437 } else { 438 i = 1; 439 /* First find the tail of the list. */ 440 ETHER_FIRST_MULTI(step, ac, enm); 441 while (enm != NULL) { 442 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 443 ifp->if_flags |= IFF_ALLMULTI; 444 goto allmulti; 445 } 446 /* 447 * Program the first XM_RXFILT_MAX multicast groups 448 * into the perfect filter. For all others, 449 * use the hash table. 450 */ 451 if (i < XM_RXFILT_MAX) { 452 sk_setfilt(sc_if, enm->enm_addrlo, i); 453 i++; 454 } 455 else { 456 h = sk_calchash(enm->enm_addrlo); 457 if (h < 32) 458 hashes[0] |= (1 << h); 459 else 460 hashes[1] |= (1 << (h - 32)); 461 } 462 463 ETHER_NEXT_MULTI(step, enm); 464 } 465 } 466 467 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 468 XM_MODE_RX_USE_PERFECT); 469 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 470 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 471 } 472 473 int 474 sk_init_rx_ring(struct sk_if_softc *sc_if) 475 { 476 struct sk_chain_data *cd = &sc_if->sk_cdata; 477 struct sk_ring_data *rd = sc_if->sk_rdata; 478 int i; 479 480 bzero((char *)rd->sk_rx_ring, 481 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 482 483 for (i = 0; i < SK_RX_RING_CNT; i++) { 484 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 485 if (i == (SK_RX_RING_CNT - 1)) { 486 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 487 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 488 } else { 489 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 490 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 491 } 492 } 493 494 for (i = 0; i < SK_RX_RING_CNT; i++) { 495 if (sk_newbuf(sc_if, i, NULL, NULL) == ENOBUFS) { 496 printf("%s: failed alloc of %dth mbuf\n", 497 sc_if->sk_dev.dv_xname, i); 498 return(ENOBUFS); 499 } 500 } 501 sc_if->sk_cdata.sk_rx_prod = 0; 502 sc_if->sk_cdata.sk_rx_cons = 0; 503 504 return(0); 505 } 506 507 int 508 sk_init_tx_ring(struct sk_if_softc *sc_if) 509 { 510 struct sk_softc *sc = sc_if->sk_softc; 511 struct sk_chain_data *cd = &sc_if->sk_cdata; 512 struct sk_ring_data *rd = sc_if->sk_rdata; 513 bus_dmamap_t dmamap; 514 struct sk_txmap_entry *entry; 515 int i; 516 517 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 518 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 519 520 SLIST_INIT(&sc_if->sk_txmap_listhead); 521 for (i = 0; i < SK_TX_RING_CNT; i++) { 522 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 523 if (i == (SK_TX_RING_CNT - 1)) { 524 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 525 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 526 } else { 527 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 528 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 529 } 530 531 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, SK_NTXSEG, 532 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap)) 533 return (ENOBUFS); 534 535 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 536 if (!entry) { 537 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 538 return (ENOBUFS); 539 } 540 entry->dmamap = dmamap; 541 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, link); 542 } 543 544 sc_if->sk_cdata.sk_tx_prod = 0; 545 sc_if->sk_cdata.sk_tx_cons = 0; 546 sc_if->sk_cdata.sk_tx_cnt = 0; 547 548 return (0); 549 } 550 551 int 552 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 553 bus_dmamap_t dmamap) 554 { 555 struct sk_softc *sc = sc_if->sk_softc; 556 struct mbuf *m_new = NULL; 557 struct sk_chain *c; 558 struct sk_rx_desc *r; 559 560 if (dmamap == NULL) { 561 /* if (m) panic() */ 562 563 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 564 0, BUS_DMA_NOWAIT, &dmamap)) { 565 printf("%s: can't create recv map\n", 566 sc_if->sk_dev.dv_xname); 567 return(ENOMEM); 568 } 569 } else if (m == NULL) 570 bus_dmamap_unload(sc->sc_dmatag, dmamap); 571 572 sc_if->sk_cdata.sk_rx_map[i] = dmamap; 573 574 if (m == NULL) { 575 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 576 if (m_new == NULL) { 577 printf("%s: no memory for rx list -- " 578 "packet dropped!\n", sc_if->sk_dev.dv_xname); 579 return(ENOBUFS); 580 } 581 582 /* Allocate the jumbo buffer */ 583 MCLGET(m_new, M_DONTWAIT); 584 if (!(m_new->m_flags & M_EXT)) { 585 m_freem(m_new); 586 return (ENOBUFS); 587 } 588 589 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 590 591 m_adj(m_new, ETHER_ALIGN); 592 593 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 594 BUS_DMA_NOWAIT)) 595 return(ENOBUFS); 596 } else { 597 /* 598 * We're re-using a previously allocated mbuf; 599 * be sure to re-init pointers and lengths to 600 * default values. 601 */ 602 m_new = m; 603 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 604 m_adj(m_new, ETHER_ALIGN); 605 m_new->m_data = m_new->m_ext.ext_buf; 606 } 607 608 c = &sc_if->sk_cdata.sk_rx_chain[i]; 609 r = c->sk_desc; 610 c->sk_mbuf = m_new; 611 r->sk_data_lo = dmamap->dm_segs[0].ds_addr; 612 r->sk_ctl = dmamap->dm_segs[0].ds_len | SK_RXSTAT; 613 614 return(0); 615 } 616 617 /* 618 * Set media options. 619 */ 620 int 621 sk_ifmedia_upd(struct ifnet *ifp) 622 { 623 struct sk_if_softc *sc_if = ifp->if_softc; 624 625 sk_init(sc_if); 626 mii_mediachg(&sc_if->sk_mii); 627 return(0); 628 } 629 630 /* 631 * Report current media status. 632 */ 633 void 634 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 635 { 636 struct sk_if_softc *sc_if = ifp->if_softc; 637 638 mii_pollstat(&sc_if->sk_mii); 639 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 640 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 641 } 642 643 int 644 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 645 { 646 struct sk_if_softc *sc_if = ifp->if_softc; 647 struct ifreq *ifr = (struct ifreq *) data; 648 struct ifaddr *ifa = (struct ifaddr *) data; 649 struct mii_data *mii; 650 int s, error = 0; 651 652 s = splimp(); 653 654 if ((error = ether_ioctl(ifp, &sc_if->arpcom, command, data)) > 0) { 655 splx(s); 656 return error; 657 } 658 659 switch(command) { 660 case SIOCSIFADDR: 661 ifp->if_flags |= IFF_UP; 662 switch (ifa->ifa_addr->sa_family) { 663 #ifdef INET 664 case AF_INET: 665 sk_init(sc_if); 666 arp_ifinit(&sc_if->arpcom, ifa); 667 break; 668 #endif /* INET */ 669 default: 670 sk_init(sc_if); 671 break; 672 } 673 break; 674 case SIOCSIFMTU: 675 if (ifr->ifr_mtu > SK_JUMBO_MTU) 676 error = EINVAL; 677 else 678 ifp->if_mtu = ifr->ifr_mtu; 679 sk_init(sc_if); 680 break; 681 case SIOCSIFFLAGS: 682 if (ifp->if_flags & IFF_UP) { 683 if (ifp->if_flags & IFF_RUNNING && 684 ifp->if_flags & IFF_PROMISC && 685 !(sc_if->sk_if_flags & IFF_PROMISC)) { 686 SK_XM_SETBIT_4(sc_if, XM_MODE, 687 XM_MODE_RX_PROMISC); 688 sk_setmulti(sc_if); 689 } else if (ifp->if_flags & IFF_RUNNING && 690 !(ifp->if_flags & IFF_PROMISC) && 691 sc_if->sk_if_flags & IFF_PROMISC) { 692 SK_XM_CLRBIT_4(sc_if, XM_MODE, 693 XM_MODE_RX_PROMISC); 694 sk_setmulti(sc_if); 695 } else 696 sk_init(sc_if); 697 } else { 698 if (ifp->if_flags & IFF_RUNNING) 699 sk_stop(sc_if); 700 } 701 sc_if->sk_if_flags = ifp->if_flags; 702 error = 0; 703 break; 704 case SIOCADDMULTI: 705 case SIOCDELMULTI: 706 error = (command == SIOCADDMULTI) ? 707 ether_addmulti(ifr, &sc_if->arpcom) : 708 ether_delmulti(ifr, &sc_if->arpcom); 709 710 if (error == ENETRESET) { 711 /* 712 * Multicast list has changed; set the hardware 713 * filter accordingly. 714 */ 715 sk_setmulti(sc_if); 716 error = 0; 717 } 718 break; 719 case SIOCGIFMEDIA: 720 case SIOCSIFMEDIA: 721 mii = &sc_if->sk_mii; 722 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 723 break; 724 default: 725 error = EINVAL; 726 break; 727 } 728 729 splx(s); 730 731 return(error); 732 } 733 734 /* 735 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 736 * IDs against our list and return a device name if we find a match. 737 */ 738 int 739 skc_probe(struct device *parent, void *match, void *aux) 740 { 741 struct pci_attach_args *pa = aux; 742 743 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SCHNEIDERKOCH && 744 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SCHNEIDERKOCH_GE) 745 return (1); 746 747 return (0); 748 } 749 750 /* 751 * Force the GEnesis into reset, then bring it out of reset. 752 */ 753 void sk_reset(struct sk_softc *sc) 754 { 755 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_RESET); 756 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_RESET); 757 DELAY(1000); 758 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_UNRESET); 759 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 760 761 /* Configure packet arbiter */ 762 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 763 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 764 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 765 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 766 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 767 768 /* Enable RAM interface */ 769 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 770 771 /* 772 * Configure interrupt moderation. The moderation timer 773 * defers interrupts specified in the interrupt moderation 774 * timer mask based on the timeout specified in the interrupt 775 * moderation timer init register. Each bit in the timer 776 * register represents 18.825ns, so to specify a timeout in 777 * microseconds, we have to multiply by 54. 778 */ 779 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 780 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 781 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 782 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 783 } 784 785 int 786 sk_probe(struct device *parent, void *match, void *aux) 787 { 788 struct skc_attach_args *sa = aux; 789 790 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 791 return(0); 792 793 return (1); 794 } 795 796 /* 797 * Each XMAC chip is attached as a separate logical IP interface. 798 * Single port cards will have only one logical interface of course. 799 */ 800 void 801 sk_attach(struct device *parent, struct device *self, void *aux) 802 { 803 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 804 struct sk_softc *sc = (struct sk_softc *)parent; 805 struct skc_attach_args *sa = aux; 806 struct ifnet *ifp; 807 caddr_t kva; 808 bus_dma_segment_t seg; 809 int i, rseg; 810 811 sc_if->sk_port = sa->skc_port; 812 sc_if->sk_softc = sc; 813 sc->sk_if[sa->skc_port] = sc_if; 814 815 if (sa->skc_port == SK_PORT_A) 816 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 817 if (sa->skc_port == SK_PORT_B) 818 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 819 820 /* 821 * Get station address for this interface. Note that 822 * dual port cards actually come with three station 823 * addresses: one for each port, plus an extra. The 824 * extra one is used by the SysKonnect driver software 825 * as a 'virtual' station address for when both ports 826 * are operating in failover mode. Currently we don't 827 * use this extra address. 828 */ 829 for (i = 0; i < ETHER_ADDR_LEN; i++) 830 sc_if->arpcom.ac_enaddr[i] = 831 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 832 833 834 printf(": address %s\n", 835 ether_sprintf(sc_if->arpcom.ac_enaddr)); 836 837 /* 838 * Set up RAM buffer addresses. The NIC will have a certain 839 * amount of SRAM on it, somewhere between 512K and 2MB. We 840 * need to divide this up a) between the transmitter and 841 * receiver and b) between the two XMACs, if this is a 842 * dual port NIC. Our algotithm is to divide up the memory 843 * evenly so that everyone gets a fair share. 844 */ 845 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 846 u_int32_t chunk, val; 847 848 chunk = sc->sk_ramsize / 2; 849 val = sc->sk_rboff / sizeof(u_int64_t); 850 sc_if->sk_rx_ramstart = val; 851 val += (chunk / sizeof(u_int64_t)); 852 sc_if->sk_rx_ramend = val - 1; 853 sc_if->sk_tx_ramstart = val; 854 val += (chunk / sizeof(u_int64_t)); 855 sc_if->sk_tx_ramend = val - 1; 856 } else { 857 u_int32_t chunk, val; 858 859 chunk = sc->sk_ramsize / 4; 860 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 861 sizeof(u_int64_t); 862 sc_if->sk_rx_ramstart = val; 863 val += (chunk / sizeof(u_int64_t)); 864 sc_if->sk_rx_ramend = val - 1; 865 sc_if->sk_tx_ramstart = val; 866 val += (chunk / sizeof(u_int64_t)); 867 sc_if->sk_tx_ramend = val - 1; 868 } 869 870 /* Read and save PHY type and set PHY address */ 871 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 872 switch (sc_if->sk_phytype) { 873 case SK_PHYTYPE_XMAC: 874 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 875 break; 876 case SK_PHYTYPE_BCOM: 877 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 878 break; 879 default: 880 printf("%s: unsupported PHY type: %d\n", 881 sc->sk_dev.dv_xname, sc_if->sk_phytype); 882 return; 883 } 884 885 /* Allocate the descriptor queues. */ 886 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 887 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 888 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 889 goto fail; 890 } 891 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 892 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 893 printf("%s: can't map dma buffers (%d bytes)\n", 894 sc_if->sk_dev.dv_xname, sizeof(struct sk_ring_data)); 895 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 896 goto fail; 897 } 898 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 899 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 900 &sc_if->sk_ring_map)) { 901 printf("%s: can't create dma map\n", sc_if->sk_dev.dv_xname); 902 bus_dmamem_unmap(sc->sc_dmatag, kva, 903 sizeof(struct sk_ring_data)); 904 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 905 goto fail; 906 } 907 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 908 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 909 printf("%s: can't load dma map\n", sc_if->sk_dev.dv_xname); 910 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 911 bus_dmamem_unmap(sc->sc_dmatag, kva, 912 sizeof(struct sk_ring_data)); 913 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 914 goto fail; 915 } 916 sc_if->sk_rdata = (struct sk_ring_data *)kva; 917 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 918 919 ifp = &sc_if->arpcom.ac_if; 920 ifp->if_softc = sc_if; 921 ifp->if_mtu = ETHERMTU; 922 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 923 ifp->if_ioctl = sk_ioctl; 924 ifp->if_output = ether_output; 925 ifp->if_start = sk_start; 926 ifp->if_watchdog = sk_watchdog; 927 ifp->if_baudrate = 1000000000; 928 ifp->if_capabilities |= IFCAP_VLAN_MTU; 929 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 930 IFQ_SET_READY(&ifp->if_snd); 931 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 932 933 /* 934 * Do miibus setup. 935 */ 936 sk_init_xmac(sc_if); 937 sc_if->sk_mii.mii_ifp = ifp; 938 sc_if->sk_mii.mii_readreg = sk_miibus_readreg; 939 sc_if->sk_mii.mii_writereg = sk_miibus_writereg; 940 sc_if->sk_mii.mii_statchg = sk_miibus_statchg; 941 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 942 sk_ifmedia_upd, sk_ifmedia_sts); 943 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 944 MII_OFFSET_ANY, 0); 945 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 946 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 947 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 948 0, NULL); 949 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 950 } 951 else 952 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 953 954 timeout_set(&sc_if->sk_tick_ch, sk_tick, sc_if); 955 timeout_add(&sc_if->sk_tick_ch, hz); 956 957 /* 958 * Call MI attach routines. 959 */ 960 if_attach(ifp); 961 ether_ifattach(ifp); 962 963 return; 964 965 fail: 966 sc->sk_if[sa->skc_port] = NULL; 967 } 968 969 int 970 skcprint(void *aux, const char *pnp) 971 { 972 struct skc_attach_args *sa = aux; 973 974 if (pnp) 975 printf("sk port %c at %s", 976 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 977 else 978 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 979 return (UNCONF); 980 } 981 982 /* 983 * Attach the interface. Allocate softc structures, do ifmedia 984 * setup and ethernet/BPF attach. 985 */ 986 void 987 skc_attach(struct device *parent, struct device *self, void *aux) 988 { 989 struct sk_softc *sc = (struct sk_softc *)self; 990 struct pci_attach_args *pa = aux; 991 struct skc_attach_args skca; 992 pci_chipset_tag_t pc = pa->pa_pc; 993 pci_intr_handle_t ih; 994 const char *intrstr = NULL; 995 bus_addr_t iobase; 996 bus_size_t iosize; 997 int s; 998 u_int32_t command; 999 1000 s = splimp(); 1001 1002 /* 1003 * Handle power management nonsense. 1004 */ 1005 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1006 if (command == 0x01) { 1007 1008 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1009 if (command & SK_PSTATE_MASK) { 1010 u_int32_t iobase, membase, irq; 1011 1012 /* Save important PCI config data. */ 1013 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1014 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1015 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1016 1017 /* Reset the power state. */ 1018 printf("%s chip is in D%d power mode " 1019 "-- setting to D0\n", sc->sk_dev.dv_xname, 1020 command & SK_PSTATE_MASK); 1021 command &= 0xFFFFFFFC; 1022 pci_conf_write(pc, pa->pa_tag, 1023 SK_PCI_PWRMGMTCTRL, command); 1024 1025 /* Restore PCI config data. */ 1026 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1027 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1028 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1029 } 1030 } 1031 1032 /* 1033 * Map control/status registers. 1034 */ 1035 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1036 command |= PCI_COMMAND_IO_ENABLE | 1037 PCI_COMMAND_MEM_ENABLE | 1038 PCI_COMMAND_MASTER_ENABLE; 1039 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1040 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1041 1042 #ifdef SK_USEIOSPACE 1043 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1044 printf(": failed to enable I/O ports!\n"); 1045 goto fail; 1046 } 1047 /* 1048 * Map control/status registers. 1049 */ 1050 if (pci_io_find(pc, pa->pa_tag, SK_PCI_LOIO, &iobase, &iosize)) { 1051 printf(": can't find i/o space\n"); 1052 goto fail; 1053 } 1054 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->sk_bhandle)) { 1055 printf(": can't map i/o space\n"); 1056 goto fail; 1057 } 1058 sc->sk_btag = pa->pa_iot; 1059 #else 1060 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1061 printf(": failed to enable memory mapping!\n"); 1062 goto fail; 1063 } 1064 if (pci_mem_find(pc, pa->pa_tag, SK_PCI_LOMEM, &iobase, &iosize, NULL)){ 1065 printf(": can't find mem space\n"); 1066 goto fail; 1067 } 1068 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->sk_bhandle)) { 1069 printf(": can't map mem space\n"); 1070 goto fail; 1071 } 1072 sc->sk_btag = pa->pa_memt; 1073 #endif 1074 sc->sc_dmatag = pa->pa_dmat; 1075 1076 /* Allocate interrupt */ 1077 if (pci_intr_map(pa, &ih)) { 1078 printf(": couldn't map interrupt\n"); 1079 goto fail; 1080 } 1081 1082 intrstr = pci_intr_string(pc, ih); 1083 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc, 1084 self->dv_xname); 1085 if (sc->sk_intrhand == NULL) { 1086 printf(": couldn't establish interrupt"); 1087 if (intrstr != NULL) 1088 printf(" at %s", intrstr); 1089 goto fail; 1090 } 1091 printf(": %s\n", intrstr); 1092 1093 /* Reset the adapter. */ 1094 sk_reset(sc); 1095 1096 /* Read and save vital product data from EEPROM. */ 1097 sk_vpd_read(sc); 1098 1099 /* Read and save RAM size and RAMbuffer offset */ 1100 switch(sk_win_read_1(sc, SK_EPROM0)) { 1101 case SK_RAMSIZE_512K_64: 1102 sc->sk_ramsize = 0x80000; 1103 sc->sk_rboff = SK_RBOFF_0; 1104 break; 1105 case SK_RAMSIZE_1024K_64: 1106 sc->sk_ramsize = 0x100000; 1107 sc->sk_rboff = SK_RBOFF_80000; 1108 break; 1109 case SK_RAMSIZE_1024K_128: 1110 sc->sk_ramsize = 0x100000; 1111 sc->sk_rboff = SK_RBOFF_0; 1112 break; 1113 case SK_RAMSIZE_2048K_128: 1114 sc->sk_ramsize = 0x200000; 1115 sc->sk_rboff = SK_RBOFF_0; 1116 break; 1117 default: 1118 printf("%s: unknown ram size: %d\n", 1119 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_EPROM0)); 1120 goto fail; 1121 break; 1122 } 1123 1124 /* Read and save physical media type */ 1125 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1126 case SK_PMD_1000BASESX: 1127 sc->sk_pmd = IFM_1000_SX; 1128 break; 1129 case SK_PMD_1000BASELX: 1130 sc->sk_pmd = IFM_1000_LX; 1131 break; 1132 case SK_PMD_1000BASECX: 1133 sc->sk_pmd = IFM_1000_CX; 1134 break; 1135 case SK_PMD_1000BASETX: 1136 sc->sk_pmd = IFM_1000_T; 1137 break; 1138 default: 1139 printf("%s: unknown media type: 0x%x\n", 1140 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1141 goto fail; 1142 } 1143 1144 /* Announce the product name. */ 1145 printf("%s: %s\n", sc->sk_dev.dv_xname, sc->sk_vpd_prodname); 1146 1147 skca.skc_port = SK_PORT_A; 1148 (void)config_found(&sc->sk_dev, &skca, skcprint); 1149 1150 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1151 skca.skc_port = SK_PORT_B; 1152 (void)config_found(&sc->sk_dev, &skca, skcprint); 1153 } 1154 1155 /* Turn on the 'driver is loaded' LED. */ 1156 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1157 1158 fail: 1159 splx(s); 1160 } 1161 1162 int 1163 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1164 { 1165 struct sk_softc *sc = sc_if->sk_softc; 1166 struct sk_tx_desc *f = NULL; 1167 u_int32_t frag, cur, cnt = 0; 1168 int i; 1169 struct sk_txmap_entry *entry; 1170 bus_dmamap_t txmap; 1171 1172 entry = SLIST_FIRST(&sc_if->sk_txmap_listhead); 1173 if (entry == NULL) 1174 return (ENOBUFS); 1175 txmap = entry->dmamap; 1176 1177 cur = frag = *txidx; 1178 1179 /* 1180 * Start packing the mbufs in this chain into 1181 * the fragment pointers. Stop when we run out 1182 * of fragments or hit the end of the mbuf chain. 1183 */ 1184 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, BUS_DMA_NOWAIT)) 1185 return(ENOBUFS); 1186 1187 for (i = 0; i < txmap->dm_nsegs; i++) { 1188 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1189 return(ENOBUFS); 1190 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1191 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1192 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1193 if (cnt == 0) 1194 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1195 else 1196 f->sk_ctl |= SK_TXCTL_OWN; 1197 cur = frag; 1198 SK_INC(frag, SK_TX_RING_CNT); 1199 cnt++; 1200 } 1201 1202 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1203 SLIST_REMOVE_HEAD(&sc_if->sk_txmap_listhead, link); 1204 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1205 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1206 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1207 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1208 sc_if->sk_cdata.sk_tx_cnt += cnt; 1209 1210 *txidx = frag; 1211 1212 return(0); 1213 } 1214 1215 void 1216 sk_start(struct ifnet *ifp) 1217 { 1218 struct sk_if_softc *sc_if = ifp->if_softc; 1219 struct sk_softc *sc = sc_if->sk_softc; 1220 struct mbuf *m_head = NULL; 1221 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1222 int pkts = 0; 1223 1224 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1225 IFQ_POLL(&ifp->if_snd, m_head); 1226 if (m_head == NULL) 1227 break; 1228 1229 /* 1230 * Pack the data into the transmit ring. If we 1231 * don't have room, set the OACTIVE flag and wait 1232 * for the NIC to drain the ring. 1233 */ 1234 if (sk_encap(sc_if, m_head, &idx)) { 1235 ifp->if_flags |= IFF_OACTIVE; 1236 break; 1237 } 1238 1239 /* now we are committed to transmit the packet */ 1240 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1241 pkts++; 1242 1243 /* 1244 * If there's a BPF listener, bounce a copy of this frame 1245 * to him. 1246 */ 1247 #if NBPFILTER > 0 1248 if (ifp->if_bpf) 1249 bpf_mtap(ifp->if_bpf, m_head); 1250 #endif 1251 } 1252 if (pkts == 0) 1253 return; 1254 1255 /* Transmit */ 1256 sc_if->sk_cdata.sk_tx_prod = idx; 1257 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1258 1259 /* Set a timeout in case the chip goes out to lunch. */ 1260 ifp->if_timer = 5; 1261 } 1262 1263 1264 void 1265 sk_watchdog(struct ifnet *ifp) 1266 { 1267 struct sk_if_softc *sc_if = ifp->if_softc; 1268 1269 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1270 sk_init(sc_if); 1271 } 1272 1273 void 1274 sk_shutdown(void *v) 1275 { 1276 struct sk_softc *sc = v; 1277 1278 /* Turn off the 'driver is loaded' LED. */ 1279 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1280 1281 /* 1282 * Reset the GEnesis controller. Doing this should also 1283 * assert the resets on the attached XMAC(s). 1284 */ 1285 sk_reset(sc); 1286 } 1287 1288 void 1289 sk_rxeof(struct sk_if_softc *sc_if) 1290 { 1291 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1292 struct mbuf *m; 1293 struct sk_chain *cur_rx; 1294 struct sk_rx_desc *cur_desc; 1295 int i, cur, total_len = 0; 1296 u_int32_t rxstat; 1297 bus_dmamap_t dmamap; 1298 1299 i = sc_if->sk_cdata.sk_rx_prod; 1300 1301 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1302 cur = i; 1303 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1304 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1305 1306 rxstat = cur_desc->sk_xmac_rxstat; 1307 m = cur_rx->sk_mbuf; 1308 cur_rx->sk_mbuf = NULL; 1309 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1310 1311 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1312 sc_if->sk_cdata.sk_rx_map[cur] = 0; 1313 1314 SK_INC(i, SK_RX_RING_CNT); 1315 1316 if (rxstat & XM_RXSTAT_ERRFRAME) { 1317 ifp->if_ierrors++; 1318 sk_newbuf(sc_if, cur, m, dmamap); 1319 continue; 1320 } 1321 1322 /* 1323 * Try to allocate a new jumbo buffer. If that 1324 * fails, copy the packet to mbufs and put the 1325 * jumbo buffer back in the ring so it can be 1326 * re-used. If allocating mbufs fails, then we 1327 * have to drop the packet. 1328 */ 1329 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1330 struct mbuf *m0; 1331 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1332 total_len + ETHER_ALIGN, 0, ifp, NULL); 1333 sk_newbuf(sc_if, cur, m, dmamap); 1334 if (m0 == NULL) { 1335 printf("%s: no receive buffers " 1336 "available -- packet dropped!\n", 1337 sc_if->sk_dev.dv_xname); 1338 ifp->if_ierrors++; 1339 continue; 1340 } 1341 m_adj(m0, ETHER_ALIGN); 1342 m = m0; 1343 } else { 1344 m->m_pkthdr.rcvif = ifp; 1345 m->m_pkthdr.len = m->m_len = total_len; 1346 } 1347 1348 ifp->if_ipackets++; 1349 1350 #if NBPFILTER > 0 1351 if (ifp->if_bpf) 1352 bpf_mtap(ifp->if_bpf, m); 1353 #endif 1354 /* pass it on. */ 1355 ether_input_mbuf(ifp, m); 1356 } 1357 1358 sc_if->sk_cdata.sk_rx_prod = i; 1359 } 1360 1361 void 1362 sk_txeof(struct sk_if_softc *sc_if) 1363 { 1364 struct sk_softc *sc = sc_if->sk_softc; 1365 struct sk_tx_desc *cur_tx = NULL; 1366 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1367 u_int32_t idx; 1368 struct sk_txmap_entry *entry; 1369 1370 /* 1371 * Go through our tx ring and free mbufs for those 1372 * frames that have been sent. 1373 */ 1374 idx = sc_if->sk_cdata.sk_tx_cons; 1375 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1376 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1377 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1378 break; 1379 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1380 ifp->if_opackets++; 1381 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1382 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1383 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1384 1385 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1386 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1387 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1388 1389 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1390 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, 1391 link); 1392 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1393 } 1394 sc_if->sk_cdata.sk_tx_cnt--; 1395 SK_INC(idx, SK_TX_RING_CNT); 1396 ifp->if_timer = 0; 1397 } 1398 1399 sc_if->sk_cdata.sk_tx_cons = idx; 1400 1401 if (cur_tx != NULL) 1402 ifp->if_flags &= ~IFF_OACTIVE; 1403 } 1404 1405 void 1406 sk_tick(void *xsc_if) 1407 { 1408 struct sk_if_softc *sc_if = xsc_if; 1409 struct mii_data *mii = &sc_if->sk_mii; 1410 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1411 int i; 1412 1413 if (!(ifp->if_flags & IFF_UP)) 1414 return; 1415 1416 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1417 sk_intr_bcom(sc_if); 1418 return; 1419 } 1420 1421 /* 1422 * According to SysKonnect, the correct way to verify that 1423 * the link has come back up is to poll bit 0 of the GPIO 1424 * register three times. This pin has the signal from the 1425 * link sync pin connected to it; if we read the same link 1426 * state 3 times in a row, we know the link is up. 1427 */ 1428 for (i = 0; i < 3; i++) { 1429 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1430 break; 1431 } 1432 1433 if (i != 3) { 1434 timeout_add(&sc_if->sk_tick_ch, hz); 1435 return; 1436 } 1437 1438 /* Turn the GP0 interrupt back on. */ 1439 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1440 SK_XM_READ_2(sc_if, XM_ISR); 1441 mii_tick(mii); 1442 mii_pollstat(mii); 1443 timeout_del(&sc_if->sk_tick_ch); 1444 } 1445 1446 void 1447 sk_intr_bcom(struct sk_if_softc *sc_if) 1448 { 1449 struct mii_data *mii = &sc_if->sk_mii; 1450 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1451 int status; 1452 1453 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1454 1455 /* 1456 * Read the PHY interrupt register to make sure 1457 * we clear any pending interrupts. 1458 */ 1459 status = sk_miibus_readreg((struct device *)sc_if, 1460 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1461 1462 if (!(ifp->if_flags & IFF_RUNNING)) { 1463 sk_init_xmac(sc_if); 1464 return; 1465 } 1466 1467 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1468 int lstat; 1469 lstat = sk_miibus_readreg((struct device *)sc_if, 1470 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 1471 1472 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1473 mii_mediachg(mii); 1474 /* Turn off the link LED. */ 1475 SK_IF_WRITE_1(sc_if, 0, 1476 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1477 sc_if->sk_link = 0; 1478 } else if (status & BRGPHY_ISR_LNK_CHG) { 1479 sk_miibus_writereg((struct device *)sc_if, 1480 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 1481 mii_tick(mii); 1482 sc_if->sk_link = 1; 1483 /* Turn on the link LED. */ 1484 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1485 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1486 SK_LINKLED_BLINK_OFF); 1487 mii_pollstat(mii); 1488 } else { 1489 mii_tick(mii); 1490 timeout_add(&sc_if->sk_tick_ch, hz); 1491 } 1492 } 1493 1494 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1495 } 1496 1497 void 1498 sk_intr_xmac(struct sk_if_softc *sc_if) 1499 { 1500 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 1501 1502 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1503 if (status & XM_ISR_GP0_SET) { 1504 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1505 timeout_add(&sc_if->sk_tick_ch, hz); 1506 } 1507 1508 if (status & XM_ISR_AUTONEG_DONE) { 1509 timeout_add(&sc_if->sk_tick_ch, hz); 1510 } 1511 } 1512 1513 if (status & XM_IMR_TX_UNDERRUN) 1514 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1515 1516 if (status & XM_IMR_RX_OVERRUN) 1517 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1518 } 1519 1520 int 1521 sk_intr(void *xsc) 1522 { 1523 struct sk_softc *sc = xsc; 1524 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1525 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1526 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1527 u_int32_t status; 1528 int claimed = 0; 1529 1530 if (sc_if0 != NULL) 1531 ifp0 = &sc_if0->arpcom.ac_if; 1532 if (sc_if1 != NULL) 1533 ifp1 = &sc_if1->arpcom.ac_if; 1534 1535 for (;;) { 1536 status = CSR_READ_4(sc, SK_ISSR); 1537 if (!(status & sc->sk_intrmask)) 1538 break; 1539 1540 claimed = 1; 1541 1542 /* Handle receive interrupts first. */ 1543 if (status & SK_ISR_RX1_EOF) { 1544 sk_rxeof(sc_if0); 1545 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1546 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1547 } 1548 if (status & SK_ISR_RX2_EOF) { 1549 sk_rxeof(sc_if1); 1550 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1551 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1552 } 1553 1554 /* Then transmit interrupts. */ 1555 if (status & SK_ISR_TX1_S_EOF) { 1556 sk_txeof(sc_if0); 1557 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1558 SK_TXBMU_CLR_IRQ_EOF); 1559 } 1560 if (status & SK_ISR_TX2_S_EOF) { 1561 sk_txeof(sc_if1); 1562 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1563 SK_TXBMU_CLR_IRQ_EOF); 1564 } 1565 1566 /* Then MAC interrupts. */ 1567 if (status & SK_ISR_MAC1 && 1568 ifp0->if_flags & IFF_RUNNING) 1569 sk_intr_xmac(sc_if0); 1570 1571 if (status & SK_ISR_MAC2 && 1572 ifp1->if_flags & IFF_RUNNING) 1573 sk_intr_xmac(sc_if1); 1574 1575 if (status & SK_ISR_EXTERNAL_REG) { 1576 if (ifp0 != NULL) 1577 sk_intr_bcom(sc_if0); 1578 if (ifp1 != NULL) 1579 sk_intr_bcom(sc_if1); 1580 } 1581 } 1582 1583 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1584 1585 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1586 sk_start(ifp0); 1587 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1588 sk_start(ifp1); 1589 1590 return (claimed); 1591 } 1592 1593 void 1594 sk_init_xmac(struct sk_if_softc *sc_if) 1595 { 1596 struct sk_softc *sc = sc_if->sk_softc; 1597 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1598 struct sk_bcom_hack bhack[] = { 1599 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 1600 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 1601 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 1602 { 0, 0 } }; 1603 1604 /* Unreset the XMAC. */ 1605 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 1606 DELAY(1000); 1607 1608 /* Reset the XMAC's internal state. */ 1609 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 1610 1611 /* Save the XMAC II revision */ 1612 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 1613 1614 /* 1615 * Perform additional initialization for external PHYs, 1616 * namely for the 1000baseTX cards that use the XMAC's 1617 * GMII mode. 1618 */ 1619 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1620 int i = 0; 1621 u_int32_t val; 1622 1623 /* Take PHY out of reset. */ 1624 val = sk_win_read_4(sc, SK_GPIO); 1625 if (sc_if->sk_port == SK_PORT_A) 1626 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 1627 else 1628 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 1629 sk_win_write_4(sc, SK_GPIO, val); 1630 1631 /* Enable GMII mode on the XMAC. */ 1632 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 1633 1634 sk_miibus_writereg((struct device *)sc_if, SK_PHYADDR_BCOM, 1635 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 1636 DELAY(10000); 1637 sk_miibus_writereg((struct device *)sc_if, SK_PHYADDR_BCOM, 1638 BRGPHY_MII_IMR, 0xFFF0); 1639 1640 /* 1641 * Early versions of the BCM5400 apparently have 1642 * a bug that requires them to have their reserved 1643 * registers initialized to some magic values. I don't 1644 * know what the numbers do, I'm just the messenger. 1645 */ 1646 if (sk_miibus_readreg((struct device *)sc_if, 1647 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 1648 while(bhack[i].reg) { 1649 sk_miibus_writereg((struct device *)sc_if, 1650 SK_PHYADDR_BCOM, bhack[i].reg, 1651 bhack[i].val); 1652 i++; 1653 } 1654 } 1655 } 1656 1657 /* Set station address */ 1658 SK_XM_WRITE_2(sc_if, XM_PAR0, 1659 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 1660 SK_XM_WRITE_2(sc_if, XM_PAR1, 1661 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 1662 SK_XM_WRITE_2(sc_if, XM_PAR2, 1663 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 1664 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 1665 1666 if (ifp->if_flags & IFF_PROMISC) { 1667 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1668 } else { 1669 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1670 } 1671 1672 if (ifp->if_flags & IFF_BROADCAST) { 1673 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 1674 } else { 1675 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 1676 } 1677 1678 /* We don't need the FCS appended to the packet. */ 1679 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 1680 1681 /* We want short frames padded to 60 bytes. */ 1682 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 1683 1684 /* 1685 * Enable the reception of all error frames. This is is 1686 * a necessary evil due to the design of the XMAC. The 1687 * XMAC's receive FIFO is only 8K in size, however jumbo 1688 * frames can be up to 9000 bytes in length. When bad 1689 * frame filtering is enabled, the XMAC's RX FIFO operates 1690 * in 'store and forward' mode. For this to work, the 1691 * entire frame has to fit into the FIFO, but that means 1692 * that jumbo frames larger than 8192 bytes will be 1693 * truncated. Disabling all bad frame filtering causes 1694 * the RX FIFO to operate in streaming mode, in which 1695 * case the XMAC will start transfering frames out of the 1696 * RX FIFO as soon as the FIFO threshold is reached. 1697 */ 1698 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 1699 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 1700 XM_MODE_RX_INRANGELEN); 1701 1702 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1703 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 1704 else 1705 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 1706 1707 /* 1708 * Bump up the transmit threshold. This helps hold off transmit 1709 * underruns when we're blasting traffic from both ports at once. 1710 */ 1711 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 1712 1713 /* Set multicast filter */ 1714 sk_setmulti(sc_if); 1715 1716 /* Clear and enable interrupts */ 1717 SK_XM_READ_2(sc_if, XM_ISR); 1718 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 1719 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 1720 else 1721 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 1722 1723 /* Configure MAC arbiter */ 1724 switch(sc_if->sk_xmac_rev) { 1725 case XM_XMAC_REV_B2: 1726 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 1727 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 1728 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 1729 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 1730 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 1731 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 1732 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 1733 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 1734 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 1735 break; 1736 case XM_XMAC_REV_C1: 1737 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 1738 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 1739 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 1740 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 1741 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 1742 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 1743 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 1744 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 1745 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 1746 break; 1747 default: 1748 break; 1749 } 1750 sk_win_write_2(sc, SK_MACARB_CTL, 1751 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 1752 1753 sc_if->sk_link = 1; 1754 } 1755 1756 /* 1757 * Note that to properly initialize any part of the GEnesis chip, 1758 * you first have to take it out of reset mode. 1759 */ 1760 void 1761 sk_init(void *xsc_if) 1762 { 1763 struct sk_if_softc *sc_if = xsc_if; 1764 struct sk_softc *sc = sc_if->sk_softc; 1765 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1766 struct mii_data *mii = &sc_if->sk_mii; 1767 int s; 1768 1769 s = splimp(); 1770 1771 /* Cancel pending I/O and free all RX/TX buffers. */ 1772 sk_stop(sc_if); 1773 1774 /* Configure LINK_SYNC LED */ 1775 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 1776 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_ON); 1777 1778 /* Configure RX LED */ 1779 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_START); 1780 1781 /* Configure TX LED */ 1782 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_START); 1783 1784 /* Configure I2C registers */ 1785 1786 /* Configure XMAC(s) */ 1787 sk_init_xmac(sc_if); 1788 mii_mediachg(mii); 1789 1790 /* Configure MAC FIFOs */ 1791 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 1792 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 1793 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 1794 1795 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 1796 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 1797 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 1798 1799 /* Configure transmit arbiter(s) */ 1800 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 1801 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 1802 1803 /* Configure RAMbuffers */ 1804 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 1805 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 1806 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 1807 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 1808 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 1809 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 1810 1811 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 1812 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 1813 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 1814 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 1815 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 1816 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 1817 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 1818 1819 /* Configure BMUs */ 1820 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 1821 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 1822 SK_RX_RING_ADDR(sc_if, 0)); 1823 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 1824 1825 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 1826 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 1827 SK_TX_RING_ADDR(sc_if, 0)); 1828 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 1829 1830 /* Init descriptors */ 1831 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 1832 printf("%s: initialization failed: no " 1833 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 1834 sk_stop(sc_if); 1835 splx(s); 1836 return; 1837 } 1838 1839 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 1840 printf("%s: initialization failed: no " 1841 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 1842 sk_stop(sc_if); 1843 splx(s); 1844 return; 1845 } 1846 1847 /* Configure interrupt handling */ 1848 CSR_READ_4(sc, SK_ISSR); 1849 if (sc_if->sk_port == SK_PORT_A) 1850 sc->sk_intrmask |= SK_INTRS1; 1851 else 1852 sc->sk_intrmask |= SK_INTRS2; 1853 1854 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 1855 1856 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1857 1858 /* Start BMUs. */ 1859 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 1860 1861 /* Enable XMACs TX and RX state machines */ 1862 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 1863 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1864 1865 ifp->if_flags |= IFF_RUNNING; 1866 ifp->if_flags &= ~IFF_OACTIVE; 1867 1868 splx(s); 1869 } 1870 1871 void 1872 sk_stop(struct sk_if_softc *sc_if) 1873 { 1874 struct sk_softc *sc = sc_if->sk_softc; 1875 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1876 int i; 1877 1878 timeout_del(&sc_if->sk_tick_ch); 1879 1880 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1881 u_int32_t val; 1882 1883 /* Put PHY back into reset. */ 1884 val = sk_win_read_4(sc, SK_GPIO); 1885 if (sc_if->sk_port == SK_PORT_A) { 1886 val |= SK_GPIO_DIR0; 1887 val &= ~SK_GPIO_DAT0; 1888 } else { 1889 val |= SK_GPIO_DIR2; 1890 val &= ~SK_GPIO_DAT2; 1891 } 1892 sk_win_write_4(sc, SK_GPIO, val); 1893 } 1894 1895 /* Turn off various components of this interface. */ 1896 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 1897 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 1898 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 1899 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 1900 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 1901 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 1902 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 1903 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 1904 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 1905 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 1906 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 1907 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 1908 1909 /* Disable interrupts */ 1910 if (sc_if->sk_port == SK_PORT_A) 1911 sc->sk_intrmask &= ~SK_INTRS1; 1912 else 1913 sc->sk_intrmask &= ~SK_INTRS2; 1914 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1915 1916 SK_XM_READ_2(sc_if, XM_ISR); 1917 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 1918 1919 /* Free RX and TX mbufs still in the queues. */ 1920 for (i = 0; i < SK_RX_RING_CNT; i++) { 1921 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 1922 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 1923 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1924 } 1925 } 1926 1927 for (i = 0; i < SK_TX_RING_CNT; i++) { 1928 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 1929 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 1930 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1931 } 1932 } 1933 1934 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1935 } 1936 1937 struct cfattach skc_ca = { 1938 sizeof(struct sk_softc), skc_probe, skc_attach, 1939 }; 1940 1941 struct cfdriver skc_cd = { 1942 0, "skc", DV_DULL 1943 }; 1944 1945 struct cfattach sk_ca = { 1946 sizeof(struct sk_if_softc), sk_probe, sk_attach, 1947 }; 1948 1949 struct cfdriver sk_cd = { 1950 0, "sk", DV_IFNET 1951 }; 1952