1 /* $OpenBSD: if_sk.c,v 1.160 2011/06/22 16:44:27 tedu Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include "bpfilter.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/timeout.h> 99 #include <sys/device.h> 100 #include <sys/queue.h> 101 102 #include <net/if.h> 103 #include <net/if_dl.h> 104 #include <net/if_types.h> 105 106 #ifdef INET 107 #include <netinet/in.h> 108 #include <netinet/in_systm.h> 109 #include <netinet/in_var.h> 110 #include <netinet/ip.h> 111 #include <netinet/udp.h> 112 #include <netinet/tcp.h> 113 #include <netinet/if_ether.h> 114 #endif 115 116 #include <net/if_media.h> 117 #include <net/if_vlan_var.h> 118 119 #if NBPFILTER > 0 120 #include <net/bpf.h> 121 #endif 122 123 #include <dev/mii/mii.h> 124 #include <dev/mii/miivar.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/pcidevs.h> 130 131 #include <dev/pci/if_skreg.h> 132 #include <dev/pci/if_skvar.h> 133 134 int skc_probe(struct device *, void *, void *); 135 void skc_attach(struct device *, struct device *self, void *aux); 136 int skc_detach(struct device *, int); 137 int sk_probe(struct device *, void *, void *); 138 void sk_attach(struct device *, struct device *self, void *aux); 139 int sk_detach(struct device *, int); 140 int skcprint(void *, const char *); 141 int sk_intr(void *); 142 void sk_intr_bcom(struct sk_if_softc *); 143 void sk_intr_xmac(struct sk_if_softc *); 144 void sk_intr_yukon(struct sk_if_softc *); 145 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 146 void sk_rxeof(struct sk_if_softc *); 147 void sk_txeof(struct sk_if_softc *); 148 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 149 void sk_start(struct ifnet *); 150 int sk_ioctl(struct ifnet *, u_long, caddr_t); 151 void sk_init(void *); 152 void sk_init_xmac(struct sk_if_softc *); 153 void sk_init_yukon(struct sk_if_softc *); 154 void sk_stop(struct sk_if_softc *, int softonly); 155 void sk_watchdog(struct ifnet *); 156 int sk_ifmedia_upd(struct ifnet *); 157 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 158 void sk_reset(struct sk_softc *); 159 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 160 int sk_alloc_jumbo_mem(struct sk_if_softc *); 161 void *sk_jalloc(struct sk_if_softc *); 162 void sk_jfree(caddr_t, u_int, void *); 163 int sk_init_rx_ring(struct sk_if_softc *); 164 int sk_init_tx_ring(struct sk_if_softc *); 165 166 int sk_xmac_miibus_readreg(struct device *, int, int); 167 void sk_xmac_miibus_writereg(struct device *, int, int, int); 168 void sk_xmac_miibus_statchg(struct device *); 169 170 int sk_marv_miibus_readreg(struct device *, int, int); 171 void sk_marv_miibus_writereg(struct device *, int, int, int); 172 void sk_marv_miibus_statchg(struct device *); 173 174 u_int32_t sk_xmac_hash(caddr_t); 175 u_int32_t sk_yukon_hash(caddr_t); 176 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 177 void sk_setmulti(struct sk_if_softc *); 178 void sk_setpromisc(struct sk_if_softc *); 179 void sk_tick(void *); 180 void sk_yukon_tick(void *); 181 void sk_rxcsum(struct ifnet *, struct mbuf *, const u_int16_t, const u_int16_t); 182 183 #ifdef SK_DEBUG 184 #define DPRINTF(x) if (skdebug) printf x 185 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 186 int skdebug = 0; 187 188 void sk_dump_txdesc(struct sk_tx_desc *, int); 189 void sk_dump_mbuf(struct mbuf *); 190 void sk_dump_bytes(const char *, int); 191 #else 192 #define DPRINTF(x) 193 #define DPRINTFN(n,x) 194 #endif 195 196 /* supported device vendors */ 197 const struct pci_matchid skc_devices[] = { 198 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940 }, 199 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940B }, 200 { PCI_VENDOR_CNET, PCI_PRODUCT_CNET_GIGACARD }, 201 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_A1 }, 202 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_B1 }, 203 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064 }, 204 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON }, 205 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_BELKIN }, 206 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK98XX }, 207 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK98XX2 }, 208 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821 }, 209 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9843 } 210 }; 211 212 #define SK_LINKSYS_EG1032_SUBID 0x00151737 213 214 static inline u_int32_t 215 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 216 { 217 return CSR_READ_4(sc, reg); 218 } 219 220 static inline u_int16_t 221 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 222 { 223 return CSR_READ_2(sc, reg); 224 } 225 226 static inline u_int8_t 227 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 228 { 229 return CSR_READ_1(sc, reg); 230 } 231 232 static inline void 233 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 234 { 235 CSR_WRITE_4(sc, reg, x); 236 } 237 238 static inline void 239 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 240 { 241 CSR_WRITE_2(sc, reg, x); 242 } 243 244 static inline void 245 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 246 { 247 CSR_WRITE_1(sc, reg, x); 248 } 249 250 int 251 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 252 { 253 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 254 int i; 255 256 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 257 258 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 259 return (0); 260 261 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 262 SK_XM_READ_2(sc_if, XM_PHY_DATA); 263 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 264 for (i = 0; i < SK_TIMEOUT; i++) { 265 DELAY(1); 266 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 267 XM_MMUCMD_PHYDATARDY) 268 break; 269 } 270 271 if (i == SK_TIMEOUT) { 272 printf("%s: phy failed to come ready\n", 273 sc_if->sk_dev.dv_xname); 274 return (0); 275 } 276 } 277 DELAY(1); 278 return (SK_XM_READ_2(sc_if, XM_PHY_DATA)); 279 } 280 281 void 282 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 283 { 284 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 285 int i; 286 287 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 288 289 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 290 for (i = 0; i < SK_TIMEOUT; i++) { 291 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 292 break; 293 } 294 295 if (i == SK_TIMEOUT) { 296 printf("%s: phy failed to come ready\n", 297 sc_if->sk_dev.dv_xname); 298 return; 299 } 300 301 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 302 for (i = 0; i < SK_TIMEOUT; i++) { 303 DELAY(1); 304 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 305 break; 306 } 307 308 if (i == SK_TIMEOUT) 309 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 310 } 311 312 void 313 sk_xmac_miibus_statchg(struct device *dev) 314 { 315 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 316 struct mii_data *mii = &sc_if->sk_mii; 317 318 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 319 320 /* 321 * If this is a GMII PHY, manually set the XMAC's 322 * duplex mode accordingly. 323 */ 324 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 325 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 326 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 327 else 328 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 329 } 330 } 331 332 int 333 sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 334 { 335 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 336 u_int16_t val; 337 int i; 338 339 if (phy != 0 || 340 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 341 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 342 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 343 phy, reg)); 344 return (0); 345 } 346 347 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 348 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 349 350 for (i = 0; i < SK_TIMEOUT; i++) { 351 DELAY(1); 352 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 353 if (val & YU_SMICR_READ_VALID) 354 break; 355 } 356 357 if (i == SK_TIMEOUT) { 358 printf("%s: phy failed to come ready\n", 359 sc_if->sk_dev.dv_xname); 360 return (0); 361 } 362 363 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 364 SK_TIMEOUT)); 365 366 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 367 368 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 369 phy, reg, val)); 370 371 return (val); 372 } 373 374 void 375 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 376 { 377 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 378 int i; 379 380 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 381 phy, reg, val)); 382 383 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 384 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 385 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 386 387 for (i = 0; i < SK_TIMEOUT; i++) { 388 DELAY(1); 389 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 390 break; 391 } 392 393 if (i == SK_TIMEOUT) 394 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 395 } 396 397 void 398 sk_marv_miibus_statchg(struct device *dev) 399 { 400 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 401 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 402 } 403 404 u_int32_t 405 sk_xmac_hash(caddr_t addr) 406 { 407 u_int32_t crc; 408 409 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 410 return (~crc & ((1 << SK_HASH_BITS) - 1)); 411 } 412 413 u_int32_t 414 sk_yukon_hash(caddr_t addr) 415 { 416 u_int32_t crc; 417 418 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 419 return (crc & ((1 << SK_HASH_BITS) - 1)); 420 } 421 422 void 423 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 424 { 425 int base = XM_RXFILT_ENTRY(slot); 426 427 SK_XM_WRITE_2(sc_if, base, letoh16(*(u_int16_t *)(&addr[0]))); 428 SK_XM_WRITE_2(sc_if, base + 2, letoh16(*(u_int16_t *)(&addr[2]))); 429 SK_XM_WRITE_2(sc_if, base + 4, letoh16(*(u_int16_t *)(&addr[4]))); 430 } 431 432 void 433 sk_setmulti(struct sk_if_softc *sc_if) 434 { 435 struct sk_softc *sc = sc_if->sk_softc; 436 struct ifnet *ifp= &sc_if->arpcom.ac_if; 437 u_int32_t hashes[2] = { 0, 0 }; 438 int h, i; 439 struct arpcom *ac = &sc_if->arpcom; 440 struct ether_multi *enm; 441 struct ether_multistep step; 442 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 443 444 /* First, zot all the existing filters. */ 445 switch(sc->sk_type) { 446 case SK_GENESIS: 447 for (i = 1; i < XM_RXFILT_MAX; i++) 448 sk_setfilt(sc_if, (caddr_t)&dummy, i); 449 450 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 451 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 452 break; 453 case SK_YUKON: 454 case SK_YUKON_LITE: 455 case SK_YUKON_LP: 456 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 457 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 458 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 459 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 460 break; 461 } 462 463 /* Now program new ones. */ 464 allmulti: 465 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 466 hashes[0] = 0xFFFFFFFF; 467 hashes[1] = 0xFFFFFFFF; 468 } else { 469 i = 1; 470 /* First find the tail of the list. */ 471 ETHER_FIRST_MULTI(step, ac, enm); 472 while (enm != NULL) { 473 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 474 ETHER_ADDR_LEN)) { 475 ifp->if_flags |= IFF_ALLMULTI; 476 goto allmulti; 477 } 478 /* 479 * Program the first XM_RXFILT_MAX multicast groups 480 * into the perfect filter. For all others, 481 * use the hash table. 482 */ 483 if (SK_IS_GENESIS(sc) && i < XM_RXFILT_MAX) { 484 sk_setfilt(sc_if, enm->enm_addrlo, i); 485 i++; 486 } 487 else { 488 switch(sc->sk_type) { 489 case SK_GENESIS: 490 h = sk_xmac_hash(enm->enm_addrlo); 491 break; 492 493 case SK_YUKON: 494 case SK_YUKON_LITE: 495 case SK_YUKON_LP: 496 h = sk_yukon_hash(enm->enm_addrlo); 497 break; 498 } 499 if (h < 32) 500 hashes[0] |= (1 << h); 501 else 502 hashes[1] |= (1 << (h - 32)); 503 } 504 505 ETHER_NEXT_MULTI(step, enm); 506 } 507 } 508 509 switch(sc->sk_type) { 510 case SK_GENESIS: 511 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 512 XM_MODE_RX_USE_PERFECT); 513 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 514 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 515 break; 516 case SK_YUKON: 517 case SK_YUKON_LITE: 518 case SK_YUKON_LP: 519 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 520 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 521 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 522 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 523 break; 524 } 525 } 526 527 void 528 sk_setpromisc(struct sk_if_softc *sc_if) 529 { 530 struct sk_softc *sc = sc_if->sk_softc; 531 struct ifnet *ifp= &sc_if->arpcom.ac_if; 532 533 switch(sc->sk_type) { 534 case SK_GENESIS: 535 if (ifp->if_flags & IFF_PROMISC) 536 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 537 else 538 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 539 break; 540 case SK_YUKON: 541 case SK_YUKON_LITE: 542 case SK_YUKON_LP: 543 if (ifp->if_flags & IFF_PROMISC) { 544 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 545 YU_RCR_UFLEN | YU_RCR_MUFLEN); 546 } else { 547 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 548 YU_RCR_UFLEN | YU_RCR_MUFLEN); 549 } 550 break; 551 } 552 } 553 554 int 555 sk_init_rx_ring(struct sk_if_softc *sc_if) 556 { 557 struct sk_chain_data *cd = &sc_if->sk_cdata; 558 struct sk_ring_data *rd = sc_if->sk_rdata; 559 int i, nexti; 560 561 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 562 563 for (i = 0; i < SK_RX_RING_CNT; i++) { 564 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 565 if (i == (SK_RX_RING_CNT - 1)) 566 nexti = 0; 567 else 568 nexti = i + 1; 569 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 570 rd->sk_rx_ring[i].sk_next = htole32(SK_RX_RING_ADDR(sc_if, nexti)); 571 rd->sk_rx_ring[i].sk_csum1_start = htole16(ETHER_HDR_LEN); 572 rd->sk_rx_ring[i].sk_csum2_start = htole16(ETHER_HDR_LEN + 573 sizeof(struct ip)); 574 } 575 576 for (i = 0; i < SK_RX_RING_CNT; i++) { 577 if (sk_newbuf(sc_if, i, NULL, 578 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 579 printf("%s: failed alloc of %dth mbuf\n", 580 sc_if->sk_dev.dv_xname, i); 581 return (ENOBUFS); 582 } 583 } 584 585 sc_if->sk_cdata.sk_rx_prod = 0; 586 sc_if->sk_cdata.sk_rx_cons = 0; 587 588 return (0); 589 } 590 591 int 592 sk_init_tx_ring(struct sk_if_softc *sc_if) 593 { 594 struct sk_softc *sc = sc_if->sk_softc; 595 struct sk_chain_data *cd = &sc_if->sk_cdata; 596 struct sk_ring_data *rd = sc_if->sk_rdata; 597 bus_dmamap_t dmamap; 598 struct sk_txmap_entry *entry; 599 int i, nexti; 600 601 bzero(sc_if->sk_rdata->sk_tx_ring, 602 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 603 604 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 605 for (i = 0; i < SK_TX_RING_CNT; i++) { 606 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 607 if (i == (SK_TX_RING_CNT - 1)) 608 nexti = 0; 609 else 610 nexti = i + 1; 611 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 612 rd->sk_tx_ring[i].sk_next = htole32(SK_TX_RING_ADDR(sc_if, nexti)); 613 614 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 615 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 616 return (ENOBUFS); 617 618 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 619 if (!entry) { 620 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 621 return (ENOBUFS); 622 } 623 entry->dmamap = dmamap; 624 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 625 } 626 627 sc_if->sk_cdata.sk_tx_prod = 0; 628 sc_if->sk_cdata.sk_tx_cons = 0; 629 sc_if->sk_cdata.sk_tx_cnt = 0; 630 631 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 632 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 633 634 return (0); 635 } 636 637 int 638 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 639 bus_dmamap_t dmamap) 640 { 641 struct mbuf *m_new = NULL; 642 struct sk_chain *c; 643 struct sk_rx_desc *r; 644 645 if (m == NULL) { 646 caddr_t buf = NULL; 647 648 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 649 if (m_new == NULL) 650 return (ENOBUFS); 651 652 /* Allocate the jumbo buffer */ 653 buf = sk_jalloc(sc_if); 654 if (buf == NULL) { 655 m_freem(m_new); 656 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 657 "dropped!\n", sc_if->arpcom.ac_if.if_xname)); 658 return (ENOBUFS); 659 } 660 661 /* Attach the buffer to the mbuf */ 662 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 663 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 664 } else { 665 /* 666 * We're re-using a previously allocated mbuf; 667 * be sure to re-init pointers and lengths to 668 * default values. 669 */ 670 m_new = m; 671 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 672 m_new->m_data = m_new->m_ext.ext_buf; 673 } 674 m_adj(m_new, ETHER_ALIGN); 675 676 c = &sc_if->sk_cdata.sk_rx_chain[i]; 677 r = c->sk_desc; 678 c->sk_mbuf = m_new; 679 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 680 (((vaddr_t)m_new->m_data 681 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 682 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 683 684 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 685 686 return (0); 687 } 688 689 /* 690 * Memory management for jumbo frames. 691 */ 692 693 int 694 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 695 { 696 struct sk_softc *sc = sc_if->sk_softc; 697 caddr_t ptr, kva; 698 bus_dma_segment_t seg; 699 int i, rseg, state, error; 700 struct sk_jpool_entry *entry; 701 702 state = error = 0; 703 704 /* Grab a big chunk o' storage. */ 705 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 706 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 707 printf(": can't alloc rx buffers"); 708 return (ENOBUFS); 709 } 710 711 state = 1; 712 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, &kva, 713 BUS_DMA_NOWAIT)) { 714 printf(": can't map dma buffers (%d bytes)", SK_JMEM); 715 error = ENOBUFS; 716 goto out; 717 } 718 719 state = 2; 720 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 721 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 722 printf(": can't create dma map"); 723 error = ENOBUFS; 724 goto out; 725 } 726 727 state = 3; 728 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 729 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 730 printf(": can't load dma map"); 731 error = ENOBUFS; 732 goto out; 733 } 734 735 state = 4; 736 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 737 DPRINTFN(1,("sk_jumbo_buf = 0x%08X\n", sc_if->sk_cdata.sk_jumbo_buf)); 738 739 LIST_INIT(&sc_if->sk_jfree_listhead); 740 LIST_INIT(&sc_if->sk_jinuse_listhead); 741 742 /* 743 * Now divide it up into 9K pieces and save the addresses 744 * in an array. 745 */ 746 ptr = sc_if->sk_cdata.sk_jumbo_buf; 747 for (i = 0; i < SK_JSLOTS; i++) { 748 sc_if->sk_cdata.sk_jslots[i] = ptr; 749 ptr += SK_JLEN; 750 entry = malloc(sizeof(struct sk_jpool_entry), 751 M_DEVBUF, M_NOWAIT); 752 if (entry == NULL) { 753 sc_if->sk_cdata.sk_jumbo_buf = NULL; 754 printf(": no memory for jumbo buffer queue!"); 755 error = ENOBUFS; 756 goto out; 757 } 758 entry->slot = i; 759 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 760 entry, jpool_entries); 761 } 762 out: 763 if (error != 0) { 764 switch (state) { 765 case 4: 766 bus_dmamap_unload(sc->sc_dmatag, 767 sc_if->sk_cdata.sk_rx_jumbo_map); 768 case 3: 769 bus_dmamap_destroy(sc->sc_dmatag, 770 sc_if->sk_cdata.sk_rx_jumbo_map); 771 case 2: 772 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 773 case 1: 774 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 775 break; 776 default: 777 break; 778 } 779 } 780 781 return (error); 782 } 783 784 /* 785 * Allocate a jumbo buffer. 786 */ 787 void * 788 sk_jalloc(struct sk_if_softc *sc_if) 789 { 790 struct sk_jpool_entry *entry; 791 792 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 793 794 if (entry == NULL) 795 return (NULL); 796 797 LIST_REMOVE(entry, jpool_entries); 798 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 799 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 800 } 801 802 /* 803 * Release a jumbo buffer. 804 */ 805 void 806 sk_jfree(caddr_t buf, u_int size, void *arg) 807 { 808 struct sk_jpool_entry *entry; 809 struct sk_if_softc *sc; 810 int i; 811 812 /* Extract the softc struct pointer. */ 813 sc = (struct sk_if_softc *)arg; 814 815 if (sc == NULL) 816 panic("sk_jfree: can't find softc pointer!"); 817 818 /* calculate the slot this buffer belongs to */ 819 i = ((vaddr_t)buf 820 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 821 822 if ((i < 0) || (i >= SK_JSLOTS)) 823 panic("sk_jfree: asked to free buffer that we don't manage!"); 824 825 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 826 if (entry == NULL) 827 panic("sk_jfree: buffer not in use!"); 828 entry->slot = i; 829 LIST_REMOVE(entry, jpool_entries); 830 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 831 } 832 833 /* 834 * Set media options. 835 */ 836 int 837 sk_ifmedia_upd(struct ifnet *ifp) 838 { 839 struct sk_if_softc *sc_if = ifp->if_softc; 840 841 mii_mediachg(&sc_if->sk_mii); 842 return (0); 843 } 844 845 /* 846 * Report current media status. 847 */ 848 void 849 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 850 { 851 struct sk_if_softc *sc_if = ifp->if_softc; 852 853 mii_pollstat(&sc_if->sk_mii); 854 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 855 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 856 } 857 858 int 859 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 860 { 861 struct sk_if_softc *sc_if = ifp->if_softc; 862 struct ifaddr *ifa = (struct ifaddr *) data; 863 struct ifreq *ifr = (struct ifreq *) data; 864 struct mii_data *mii; 865 int s, error = 0; 866 867 s = splnet(); 868 869 switch(command) { 870 case SIOCSIFADDR: 871 ifp->if_flags |= IFF_UP; 872 if (!(ifp->if_flags & IFF_RUNNING)) 873 sk_init(sc_if); 874 #ifdef INET 875 if (ifa->ifa_addr->sa_family == AF_INET) 876 arp_ifinit(&sc_if->arpcom, ifa); 877 #endif /* INET */ 878 break; 879 880 case SIOCSIFFLAGS: 881 if (ifp->if_flags & IFF_UP) { 882 if (ifp->if_flags & IFF_RUNNING && 883 (ifp->if_flags ^ sc_if->sk_if_flags) 884 & IFF_PROMISC) { 885 sk_setpromisc(sc_if); 886 sk_setmulti(sc_if); 887 } else { 888 if (!(ifp->if_flags & IFF_RUNNING)) 889 sk_init(sc_if); 890 } 891 } else { 892 if (ifp->if_flags & IFF_RUNNING) 893 sk_stop(sc_if, 0); 894 } 895 sc_if->sk_if_flags = ifp->if_flags; 896 break; 897 898 case SIOCGIFMEDIA: 899 case SIOCSIFMEDIA: 900 mii = &sc_if->sk_mii; 901 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 902 break; 903 904 default: 905 error = ether_ioctl(ifp, &sc_if->arpcom, command, data); 906 } 907 908 if (error == ENETRESET) { 909 if (ifp->if_flags & IFF_RUNNING) 910 sk_setmulti(sc_if); 911 error = 0; 912 } 913 914 splx(s); 915 return (error); 916 } 917 918 /* 919 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 920 * IDs against our list and return a device name if we find a match. 921 */ 922 int 923 skc_probe(struct device *parent, void *match, void *aux) 924 { 925 struct pci_attach_args *pa = aux; 926 pci_chipset_tag_t pc = pa->pa_pc; 927 pcireg_t subid; 928 929 subid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 930 931 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 932 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 933 subid == SK_LINKSYS_EG1032_SUBID) 934 return (1); 935 936 return (pci_matchbyid((struct pci_attach_args *)aux, skc_devices, 937 nitems(skc_devices))); 938 } 939 940 /* 941 * Force the GEnesis into reset, then bring it out of reset. 942 */ 943 void 944 sk_reset(struct sk_softc *sc) 945 { 946 u_int32_t imtimer_ticks; 947 948 DPRINTFN(2, ("sk_reset\n")); 949 950 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 951 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 952 if (SK_IS_YUKON(sc)) 953 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 954 955 DELAY(1000); 956 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 957 DELAY(2); 958 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 959 if (SK_IS_YUKON(sc)) 960 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 961 962 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 963 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 964 CSR_READ_2(sc, SK_LINK_CTRL))); 965 966 if (SK_IS_GENESIS(sc)) { 967 /* Configure packet arbiter */ 968 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 969 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 970 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 971 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 972 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 973 } 974 975 /* Enable RAM interface */ 976 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 977 978 /* 979 * Configure interrupt moderation. The moderation timer 980 * defers interrupts specified in the interrupt moderation 981 * timer mask based on the timeout specified in the interrupt 982 * moderation timer init register. Each bit in the timer 983 * register represents one tick, so to specify a timeout in 984 * microseconds, we have to multiply by the correct number of 985 * ticks-per-microsecond. 986 */ 987 switch (sc->sk_type) { 988 case SK_GENESIS: 989 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 990 break; 991 default: 992 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 993 } 994 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(100)); 995 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 996 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 997 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 998 } 999 1000 int 1001 sk_probe(struct device *parent, void *match, void *aux) 1002 { 1003 struct skc_attach_args *sa = aux; 1004 1005 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1006 return (0); 1007 1008 switch (sa->skc_type) { 1009 case SK_GENESIS: 1010 case SK_YUKON: 1011 case SK_YUKON_LITE: 1012 case SK_YUKON_LP: 1013 return (1); 1014 } 1015 1016 return (0); 1017 } 1018 1019 /* 1020 * Each XMAC chip is attached as a separate logical IP interface. 1021 * Single port cards will have only one logical interface of course. 1022 */ 1023 void 1024 sk_attach(struct device *parent, struct device *self, void *aux) 1025 { 1026 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1027 struct sk_softc *sc = (struct sk_softc *)parent; 1028 struct skc_attach_args *sa = aux; 1029 struct ifnet *ifp; 1030 caddr_t kva; 1031 int i; 1032 1033 sc_if->sk_port = sa->skc_port; 1034 sc_if->sk_softc = sc; 1035 sc->sk_if[sa->skc_port] = sc_if; 1036 1037 if (sa->skc_port == SK_PORT_A) 1038 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1039 if (sa->skc_port == SK_PORT_B) 1040 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1041 1042 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1043 1044 /* 1045 * Get station address for this interface. Note that 1046 * dual port cards actually come with three station 1047 * addresses: one for each port, plus an extra. The 1048 * extra one is used by the SysKonnect driver software 1049 * as a 'virtual' station address for when both ports 1050 * are operating in failover mode. Currently we don't 1051 * use this extra address. 1052 */ 1053 for (i = 0; i < ETHER_ADDR_LEN; i++) 1054 sc_if->arpcom.ac_enaddr[i] = 1055 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1056 1057 printf(": address %s\n", 1058 ether_sprintf(sc_if->arpcom.ac_enaddr)); 1059 1060 /* 1061 * Set up RAM buffer addresses. The NIC will have a certain 1062 * amount of SRAM on it, somewhere between 512K and 2MB. We 1063 * need to divide this up a) between the transmitter and 1064 * receiver and b) between the two XMACs, if this is a 1065 * dual port NIC. Our algorithm is to divide up the memory 1066 * evenly so that everyone gets a fair share. 1067 */ 1068 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1069 u_int32_t chunk, val; 1070 1071 chunk = sc->sk_ramsize / 2; 1072 val = sc->sk_rboff / sizeof(u_int64_t); 1073 sc_if->sk_rx_ramstart = val; 1074 val += (chunk / sizeof(u_int64_t)); 1075 sc_if->sk_rx_ramend = val - 1; 1076 sc_if->sk_tx_ramstart = val; 1077 val += (chunk / sizeof(u_int64_t)); 1078 sc_if->sk_tx_ramend = val - 1; 1079 } else { 1080 u_int32_t chunk, val; 1081 1082 chunk = sc->sk_ramsize / 4; 1083 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1084 sizeof(u_int64_t); 1085 sc_if->sk_rx_ramstart = val; 1086 val += (chunk / sizeof(u_int64_t)); 1087 sc_if->sk_rx_ramend = val - 1; 1088 sc_if->sk_tx_ramstart = val; 1089 val += (chunk / sizeof(u_int64_t)); 1090 sc_if->sk_tx_ramend = val - 1; 1091 } 1092 1093 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1094 " tx_ramstart=%#x tx_ramend=%#x\n", 1095 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1096 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1097 1098 /* Read and save PHY type */ 1099 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1100 1101 /* Set PHY address */ 1102 if (SK_IS_GENESIS(sc)) { 1103 switch (sc_if->sk_phytype) { 1104 case SK_PHYTYPE_XMAC: 1105 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1106 break; 1107 case SK_PHYTYPE_BCOM: 1108 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1109 break; 1110 default: 1111 printf("%s: unsupported PHY type: %d\n", 1112 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1113 return; 1114 } 1115 } 1116 1117 if (SK_IS_YUKON(sc)) { 1118 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1119 sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) { 1120 /* not initialized, punt */ 1121 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1122 1123 sc->sk_coppertype = 1; 1124 } 1125 1126 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1127 1128 if (!(sc->sk_coppertype)) 1129 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 1130 } 1131 1132 /* Allocate the descriptor queues. */ 1133 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1134 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1135 BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 1136 printf(": can't alloc rx buffers\n"); 1137 goto fail; 1138 } 1139 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg, 1140 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1141 printf(": can't map dma buffers (%lu bytes)\n", 1142 (ulong)sizeof(struct sk_ring_data)); 1143 goto fail_1; 1144 } 1145 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1146 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1147 &sc_if->sk_ring_map)) { 1148 printf(": can't create dma map\n"); 1149 goto fail_2; 1150 } 1151 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1152 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1153 printf(": can't load dma map\n"); 1154 goto fail_3; 1155 } 1156 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1157 1158 /* Try to allocate memory for jumbo buffers. */ 1159 if (sk_alloc_jumbo_mem(sc_if)) { 1160 printf(": jumbo buffer allocation failed\n"); 1161 goto fail_3; 1162 } 1163 1164 ifp = &sc_if->arpcom.ac_if; 1165 ifp->if_softc = sc_if; 1166 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1167 ifp->if_ioctl = sk_ioctl; 1168 ifp->if_start = sk_start; 1169 ifp->if_watchdog = sk_watchdog; 1170 ifp->if_baudrate = 1000000000; 1171 ifp->if_hardmtu = SK_JUMBO_MTU; 1172 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1173 IFQ_SET_READY(&ifp->if_snd); 1174 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1175 1176 ifp->if_capabilities = IFCAP_VLAN_MTU; 1177 1178 /* 1179 * Do miibus setup. 1180 */ 1181 switch (sc->sk_type) { 1182 case SK_GENESIS: 1183 sk_init_xmac(sc_if); 1184 break; 1185 case SK_YUKON: 1186 case SK_YUKON_LITE: 1187 case SK_YUKON_LP: 1188 sk_init_yukon(sc_if); 1189 break; 1190 default: 1191 printf(": unknown device type %d\n", sc->sk_type); 1192 /* dealloc jumbo on error */ 1193 goto fail_3; 1194 } 1195 1196 DPRINTFN(2, ("sk_attach: 1\n")); 1197 1198 sc_if->sk_mii.mii_ifp = ifp; 1199 if (SK_IS_GENESIS(sc)) { 1200 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1201 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1202 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1203 } else { 1204 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1205 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1206 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1207 } 1208 1209 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1210 sk_ifmedia_upd, sk_ifmedia_sts); 1211 if (SK_IS_GENESIS(sc)) { 1212 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1213 MII_OFFSET_ANY, 0); 1214 } else { 1215 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1216 MII_OFFSET_ANY, MIIF_DOPAUSE); 1217 } 1218 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1219 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1220 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1221 0, NULL); 1222 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1223 } else 1224 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1225 1226 if (SK_IS_GENESIS(sc)) { 1227 timeout_set(&sc_if->sk_tick_ch, sk_tick, sc_if); 1228 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1229 } else 1230 timeout_set(&sc_if->sk_tick_ch, sk_yukon_tick, sc_if); 1231 1232 /* 1233 * Call MI attach routines. 1234 */ 1235 if_attach(ifp); 1236 ether_ifattach(ifp); 1237 1238 DPRINTFN(2, ("sk_attach: end\n")); 1239 return; 1240 1241 fail_2: 1242 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct sk_ring_data)); 1243 fail_1: 1244 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1245 fail_3: 1246 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1247 fail: 1248 sc->sk_if[sa->skc_port] = NULL; 1249 } 1250 1251 int 1252 sk_detach(struct device *self, int flags) 1253 { 1254 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 1255 struct sk_softc *sc = sc_if->sk_softc; 1256 struct ifnet *ifp= &sc_if->arpcom.ac_if; 1257 1258 if (sc->sk_if[sc_if->sk_port] == NULL) 1259 return (0); 1260 1261 sk_stop(sc_if, 1); 1262 1263 /* Detach any PHYs we might have. */ 1264 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1265 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1266 1267 /* Delete any remaining media. */ 1268 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1269 1270 ether_ifdetach(ifp); 1271 if_detach(ifp); 1272 1273 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc_if->sk_rdata, 1274 sizeof(struct sk_ring_data)); 1275 bus_dmamem_free(sc->sc_dmatag, 1276 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1277 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1278 sc->sk_if[sc_if->sk_port] = NULL; 1279 1280 return (0); 1281 } 1282 1283 int 1284 skcprint(void *aux, const char *pnp) 1285 { 1286 struct skc_attach_args *sa = aux; 1287 1288 if (pnp) 1289 printf("sk port %c at %s", 1290 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1291 else 1292 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1293 return (UNCONF); 1294 } 1295 1296 /* 1297 * Attach the interface. Allocate softc structures, do ifmedia 1298 * setup and ethernet/BPF attach. 1299 */ 1300 void 1301 skc_attach(struct device *parent, struct device *self, void *aux) 1302 { 1303 struct sk_softc *sc = (struct sk_softc *)self; 1304 struct pci_attach_args *pa = aux; 1305 struct skc_attach_args skca; 1306 pci_chipset_tag_t pc = pa->pa_pc; 1307 pcireg_t command, memtype; 1308 pci_intr_handle_t ih; 1309 const char *intrstr = NULL; 1310 u_int8_t skrs; 1311 char *revstr = NULL; 1312 1313 DPRINTFN(2, ("begin skc_attach\n")); 1314 1315 /* 1316 * Handle power management nonsense. 1317 */ 1318 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1319 1320 if (command == 0x01) { 1321 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1322 if (command & SK_PSTATE_MASK) { 1323 u_int32_t iobase, membase, irq; 1324 1325 /* Save important PCI config data. */ 1326 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1327 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1328 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1329 1330 /* Reset the power state. */ 1331 printf("%s chip is in D%d power mode " 1332 "-- setting to D0\n", sc->sk_dev.dv_xname, 1333 command & SK_PSTATE_MASK); 1334 command &= 0xFFFFFFFC; 1335 pci_conf_write(pc, pa->pa_tag, 1336 SK_PCI_PWRMGMTCTRL, command); 1337 1338 /* Restore PCI config data. */ 1339 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1340 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1341 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1342 } 1343 } 1344 1345 /* 1346 * Map control/status registers. 1347 */ 1348 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1349 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1350 &sc->sk_bhandle, NULL, &sc->sk_bsize, 0)) { 1351 printf(": can't map mem space\n"); 1352 return; 1353 } 1354 1355 sc->sc_dmatag = pa->pa_dmat; 1356 1357 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1358 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1359 sc->sk_pc = pc; 1360 1361 /* bail out here if chip is not recognized */ 1362 if (! SK_IS_GENESIS(sc) && ! SK_IS_YUKON(sc)) { 1363 printf(": unknown chip type: %d\n", sc->sk_type); 1364 goto fail_1; 1365 } 1366 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1367 1368 /* Allocate interrupt */ 1369 if (pci_intr_map(pa, &ih)) { 1370 printf(": couldn't map interrupt\n"); 1371 goto fail_1; 1372 } 1373 1374 intrstr = pci_intr_string(pc, ih); 1375 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc, 1376 self->dv_xname); 1377 if (sc->sk_intrhand == NULL) { 1378 printf(": couldn't establish interrupt"); 1379 if (intrstr != NULL) 1380 printf(" at %s", intrstr); 1381 printf("\n"); 1382 goto fail_1; 1383 } 1384 1385 /* Reset the adapter. */ 1386 sk_reset(sc); 1387 1388 skrs = sk_win_read_1(sc, SK_EPROM0); 1389 if (SK_IS_GENESIS(sc)) { 1390 /* Read and save RAM size and RAMbuffer offset */ 1391 switch(skrs) { 1392 case SK_RAMSIZE_512K_64: 1393 sc->sk_ramsize = 0x80000; 1394 sc->sk_rboff = SK_RBOFF_0; 1395 break; 1396 case SK_RAMSIZE_1024K_64: 1397 sc->sk_ramsize = 0x100000; 1398 sc->sk_rboff = SK_RBOFF_80000; 1399 break; 1400 case SK_RAMSIZE_1024K_128: 1401 sc->sk_ramsize = 0x100000; 1402 sc->sk_rboff = SK_RBOFF_0; 1403 break; 1404 case SK_RAMSIZE_2048K_128: 1405 sc->sk_ramsize = 0x200000; 1406 sc->sk_rboff = SK_RBOFF_0; 1407 break; 1408 default: 1409 printf(": unknown ram size: %d\n", skrs); 1410 goto fail_2; 1411 break; 1412 } 1413 } else { 1414 if (skrs == 0x00) 1415 sc->sk_ramsize = 0x20000; 1416 else 1417 sc->sk_ramsize = skrs * (1<<12); 1418 sc->sk_rboff = SK_RBOFF_0; 1419 } 1420 1421 DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n", 1422 sc->sk_ramsize, sc->sk_ramsize / 1024, 1423 sc->sk_rboff)); 1424 1425 /* Read and save physical media type */ 1426 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1427 1428 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1') 1429 sc->sk_coppertype = 1; 1430 else 1431 sc->sk_coppertype = 0; 1432 1433 switch (sc->sk_type) { 1434 case SK_GENESIS: 1435 sc->sk_name = "GEnesis"; 1436 break; 1437 case SK_YUKON: 1438 sc->sk_name = "Yukon"; 1439 break; 1440 case SK_YUKON_LITE: 1441 sc->sk_name = "Yukon Lite"; 1442 break; 1443 case SK_YUKON_LP: 1444 sc->sk_name = "Yukon LP"; 1445 break; 1446 default: 1447 sc->sk_name = "Yukon (Unknown)"; 1448 } 1449 1450 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1451 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1452 u_int32_t flashaddr; 1453 u_int8_t testbyte; 1454 1455 flashaddr = sk_win_read_4(sc, SK_EP_ADDR); 1456 1457 /* test Flash-Address Register */ 1458 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff); 1459 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1460 1461 if (testbyte != 0) { 1462 /* This is a Yukon Lite Rev A0 */ 1463 sc->sk_type = SK_YUKON_LITE; 1464 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1465 /* restore Flash-Address Register */ 1466 sk_win_write_4(sc, SK_EP_ADDR, flashaddr); 1467 } 1468 } 1469 1470 if (sc->sk_type == SK_YUKON_LITE) { 1471 switch (sc->sk_rev) { 1472 case SK_YUKON_LITE_REV_A0: 1473 revstr = "A0"; 1474 break; 1475 case SK_YUKON_LITE_REV_A1: 1476 revstr = "A1"; 1477 break; 1478 case SK_YUKON_LITE_REV_A3: 1479 revstr = "A3"; 1480 break; 1481 default: 1482 ; 1483 } 1484 } 1485 1486 /* Announce the product name. */ 1487 printf(", %s", sc->sk_name); 1488 if (revstr != NULL) 1489 printf(" rev. %s", revstr); 1490 printf(" (0x%x): %s\n", sc->sk_rev, intrstr); 1491 1492 sc->sk_macs = 1; 1493 1494 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) 1495 sc->sk_macs++; 1496 1497 skca.skc_port = SK_PORT_A; 1498 skca.skc_type = sc->sk_type; 1499 skca.skc_rev = sc->sk_rev; 1500 (void)config_found(&sc->sk_dev, &skca, skcprint); 1501 1502 if (sc->sk_macs > 1) { 1503 skca.skc_port = SK_PORT_B; 1504 skca.skc_type = sc->sk_type; 1505 skca.skc_rev = sc->sk_rev; 1506 (void)config_found(&sc->sk_dev, &skca, skcprint); 1507 } 1508 1509 /* Turn on the 'driver is loaded' LED. */ 1510 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1511 1512 return; 1513 1514 fail_2: 1515 pci_intr_disestablish(pc, sc->sk_intrhand); 1516 fail_1: 1517 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1518 } 1519 1520 int 1521 skc_detach(struct device *self, int flags) 1522 { 1523 struct sk_softc *sc = (struct sk_softc *)self; 1524 int rv; 1525 1526 if (sc->sk_intrhand) 1527 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1528 1529 rv = config_detach_children(self, flags); 1530 if (rv != 0) 1531 return (rv); 1532 1533 if (sc->sk_bsize > 0) 1534 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1535 1536 return(0); 1537 } 1538 1539 int 1540 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1541 { 1542 struct sk_softc *sc = sc_if->sk_softc; 1543 struct sk_tx_desc *f = NULL; 1544 u_int32_t frag, cur, sk_ctl; 1545 int i; 1546 struct sk_txmap_entry *entry; 1547 bus_dmamap_t txmap; 1548 1549 DPRINTFN(2, ("sk_encap\n")); 1550 1551 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1552 if (entry == NULL) { 1553 DPRINTFN(2, ("sk_encap: no txmap available\n")); 1554 return (ENOBUFS); 1555 } 1556 txmap = entry->dmamap; 1557 1558 cur = frag = *txidx; 1559 1560 #ifdef SK_DEBUG 1561 if (skdebug >= 2) 1562 sk_dump_mbuf(m_head); 1563 #endif 1564 1565 /* 1566 * Start packing the mbufs in this chain into 1567 * the fragment pointers. Stop when we run out 1568 * of fragments or hit the end of the mbuf chain. 1569 */ 1570 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1571 BUS_DMA_NOWAIT)) { 1572 DPRINTFN(2, ("sk_encap: dmamap failed\n")); 1573 return (ENOBUFS); 1574 } 1575 1576 if (txmap->dm_nsegs > (SK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1577 DPRINTFN(2, ("sk_encap: too few descriptors free\n")); 1578 bus_dmamap_unload(sc->sc_dmatag, txmap); 1579 return (ENOBUFS); 1580 } 1581 1582 DPRINTFN(2, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1583 1584 /* Sync the DMA map. */ 1585 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1586 BUS_DMASYNC_PREWRITE); 1587 1588 for (i = 0; i < txmap->dm_nsegs; i++) { 1589 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1590 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1591 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1592 if (i == 0) 1593 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1594 else 1595 sk_ctl |= SK_TXCTL_OWN; 1596 f->sk_ctl = htole32(sk_ctl); 1597 cur = frag; 1598 SK_INC(frag, SK_TX_RING_CNT); 1599 } 1600 1601 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1602 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1603 1604 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1605 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1606 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1607 1608 /* Sync descriptors before handing to chip */ 1609 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1610 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1611 1612 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1613 htole32(SK_TXCTL_OWN); 1614 1615 /* Sync first descriptor to hand it off */ 1616 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1617 1618 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1619 1620 #ifdef SK_DEBUG 1621 if (skdebug >= 2) { 1622 struct sk_tx_desc *desc; 1623 u_int32_t idx; 1624 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1625 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1626 sk_dump_txdesc(desc, idx); 1627 } 1628 } 1629 #endif 1630 1631 *txidx = frag; 1632 1633 DPRINTFN(2, ("sk_encap: completed successfully\n")); 1634 1635 return (0); 1636 } 1637 1638 void 1639 sk_start(struct ifnet *ifp) 1640 { 1641 struct sk_if_softc *sc_if = ifp->if_softc; 1642 struct sk_softc *sc = sc_if->sk_softc; 1643 struct mbuf *m_head = NULL; 1644 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1645 int pkts = 0; 1646 1647 DPRINTFN(2, ("sk_start\n")); 1648 1649 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1650 IFQ_POLL(&ifp->if_snd, m_head); 1651 if (m_head == NULL) 1652 break; 1653 1654 /* 1655 * Pack the data into the transmit ring. If we 1656 * don't have room, set the OACTIVE flag and wait 1657 * for the NIC to drain the ring. 1658 */ 1659 if (sk_encap(sc_if, m_head, &idx)) { 1660 ifp->if_flags |= IFF_OACTIVE; 1661 break; 1662 } 1663 1664 /* now we are committed to transmit the packet */ 1665 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1666 pkts++; 1667 1668 /* 1669 * If there's a BPF listener, bounce a copy of this frame 1670 * to him. 1671 */ 1672 #if NBPFILTER > 0 1673 if (ifp->if_bpf) 1674 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1675 #endif 1676 } 1677 if (pkts == 0) 1678 return; 1679 1680 /* Transmit */ 1681 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1682 sc_if->sk_cdata.sk_tx_prod = idx; 1683 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1684 1685 /* Set a timeout in case the chip goes out to lunch. */ 1686 ifp->if_timer = 5; 1687 } 1688 } 1689 1690 1691 void 1692 sk_watchdog(struct ifnet *ifp) 1693 { 1694 struct sk_if_softc *sc_if = ifp->if_softc; 1695 1696 /* 1697 * Reclaim first as there is a possibility of losing Tx completion 1698 * interrupts. 1699 */ 1700 sk_txeof(sc_if); 1701 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1702 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1703 1704 ifp->if_oerrors++; 1705 1706 sk_init(sc_if); 1707 } 1708 } 1709 1710 static __inline int 1711 sk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1712 { 1713 if (sc->sk_type == SK_GENESIS) { 1714 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 1715 XM_RXSTAT_BYTES(stat) != len) 1716 return (0); 1717 } else { 1718 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1719 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1720 YU_RXSTAT_JABBER)) != 0 || 1721 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1722 YU_RXSTAT_BYTES(stat) != len) 1723 return (0); 1724 } 1725 1726 return (1); 1727 } 1728 1729 void 1730 sk_rxeof(struct sk_if_softc *sc_if) 1731 { 1732 struct sk_softc *sc = sc_if->sk_softc; 1733 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1734 struct mbuf *m; 1735 struct sk_chain *cur_rx; 1736 struct sk_rx_desc *cur_desc; 1737 int i, cur, total_len = 0; 1738 u_int32_t rxstat, sk_ctl; 1739 bus_dmamap_t dmamap; 1740 u_int16_t csum1, csum2; 1741 1742 DPRINTFN(2, ("sk_rxeof\n")); 1743 1744 i = sc_if->sk_cdata.sk_rx_prod; 1745 1746 for (;;) { 1747 cur = i; 1748 1749 /* Sync the descriptor */ 1750 SK_CDRXSYNC(sc_if, cur, 1751 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1752 1753 sk_ctl = letoh32(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1754 if ((sk_ctl & SK_RXCTL_OWN) != 0) { 1755 /* Invalidate the descriptor -- it's not ready yet */ 1756 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 1757 sc_if->sk_cdata.sk_rx_prod = i; 1758 break; 1759 } 1760 1761 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1762 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1763 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1764 1765 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1766 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1767 1768 rxstat = letoh32(cur_desc->sk_xmac_rxstat); 1769 m = cur_rx->sk_mbuf; 1770 cur_rx->sk_mbuf = NULL; 1771 total_len = SK_RXBYTES(letoh32(cur_desc->sk_ctl)); 1772 1773 csum1 = letoh16(sc_if->sk_rdata->sk_rx_ring[i].sk_csum1); 1774 csum2 = letoh16(sc_if->sk_rdata->sk_rx_ring[i].sk_csum2); 1775 1776 SK_INC(i, SK_RX_RING_CNT); 1777 1778 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 1779 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 1780 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 1781 total_len < SK_MIN_FRAMELEN || 1782 total_len > SK_JUMBO_FRAMELEN || 1783 sk_rxvalid(sc, rxstat, total_len) == 0) { 1784 ifp->if_ierrors++; 1785 sk_newbuf(sc_if, cur, m, dmamap); 1786 continue; 1787 } 1788 1789 /* 1790 * Try to allocate a new jumbo buffer. If that 1791 * fails, copy the packet to mbufs and put the 1792 * jumbo buffer back in the ring so it can be 1793 * re-used. If allocating mbufs fails, then we 1794 * have to drop the packet. 1795 */ 1796 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1797 struct mbuf *m0; 1798 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 1799 ifp, NULL); 1800 sk_newbuf(sc_if, cur, m, dmamap); 1801 if (m0 == NULL) { 1802 ifp->if_ierrors++; 1803 continue; 1804 } 1805 m = m0; 1806 } else { 1807 m->m_pkthdr.rcvif = ifp; 1808 m->m_pkthdr.len = m->m_len = total_len; 1809 } 1810 1811 ifp->if_ipackets++; 1812 1813 sk_rxcsum(ifp, m, csum1, csum2); 1814 1815 #if NBPFILTER > 0 1816 if (ifp->if_bpf) 1817 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1818 #endif 1819 1820 /* pass it on. */ 1821 ether_input_mbuf(ifp, m); 1822 } 1823 } 1824 1825 void 1826 sk_rxcsum(struct ifnet *ifp, struct mbuf *m, const u_int16_t csum1, const u_int16_t csum2) 1827 { 1828 struct ether_header *eh; 1829 struct ip *ip; 1830 u_int8_t *pp; 1831 int hlen, len, plen; 1832 u_int16_t iph_csum, ipo_csum, ipd_csum, csum; 1833 1834 pp = mtod(m, u_int8_t *); 1835 plen = m->m_pkthdr.len; 1836 if (plen < sizeof(*eh)) 1837 return; 1838 eh = (struct ether_header *)pp; 1839 iph_csum = in_cksum_addword(csum1, (~csum2 & 0xffff)); 1840 1841 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1842 u_int16_t *xp = (u_int16_t *)pp; 1843 1844 xp = (u_int16_t *)pp; 1845 if (xp[1] != htons(ETHERTYPE_IP)) 1846 return; 1847 iph_csum = in_cksum_addword(iph_csum, (~xp[0] & 0xffff)); 1848 iph_csum = in_cksum_addword(iph_csum, (~xp[1] & 0xffff)); 1849 xp = (u_int16_t *)(pp + sizeof(struct ip)); 1850 iph_csum = in_cksum_addword(iph_csum, xp[0]); 1851 iph_csum = in_cksum_addword(iph_csum, xp[1]); 1852 pp += EVL_ENCAPLEN; 1853 } else if (eh->ether_type != htons(ETHERTYPE_IP)) 1854 return; 1855 1856 pp += sizeof(*eh); 1857 plen -= sizeof(*eh); 1858 1859 ip = (struct ip *)pp; 1860 1861 if (ip->ip_v != IPVERSION) 1862 return; 1863 1864 hlen = ip->ip_hl << 2; 1865 if (hlen < sizeof(struct ip)) 1866 return; 1867 if (hlen > ntohs(ip->ip_len)) 1868 return; 1869 1870 /* Don't deal with truncated or padded packets. */ 1871 if (plen != ntohs(ip->ip_len)) 1872 return; 1873 1874 len = hlen - sizeof(struct ip); 1875 if (len > 0) { 1876 u_int16_t *p; 1877 1878 p = (u_int16_t *)(ip + 1); 1879 ipo_csum = 0; 1880 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++) 1881 ipo_csum = in_cksum_addword(ipo_csum, *p); 1882 iph_csum = in_cksum_addword(iph_csum, ipo_csum); 1883 ipd_csum = in_cksum_addword(csum2, (~ipo_csum & 0xffff)); 1884 } else 1885 ipd_csum = csum2; 1886 1887 if (iph_csum != 0xffff) 1888 return; 1889 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1890 1891 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1892 return; /* ip frag, we're done for now */ 1893 1894 pp += hlen; 1895 1896 /* Only know checksum protocol for udp/tcp */ 1897 if (ip->ip_p == IPPROTO_UDP) { 1898 struct udphdr *uh = (struct udphdr *)pp; 1899 1900 if (uh->uh_sum == 0) /* udp with no checksum */ 1901 return; 1902 } else if (ip->ip_p != IPPROTO_TCP) 1903 return; 1904 1905 csum = in_cksum_phdr(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1906 htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum); 1907 if (csum == 0xffff) { 1908 m->m_pkthdr.csum_flags |= (ip->ip_p == IPPROTO_TCP) ? 1909 M_TCP_CSUM_IN_OK : M_UDP_CSUM_IN_OK; 1910 } 1911 } 1912 1913 void 1914 sk_txeof(struct sk_if_softc *sc_if) 1915 { 1916 struct sk_softc *sc = sc_if->sk_softc; 1917 struct sk_tx_desc *cur_tx; 1918 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1919 u_int32_t idx, sk_ctl; 1920 struct sk_txmap_entry *entry; 1921 1922 DPRINTFN(2, ("sk_txeof\n")); 1923 1924 /* 1925 * Go through our tx ring and free mbufs for those 1926 * frames that have been sent. 1927 */ 1928 idx = sc_if->sk_cdata.sk_tx_cons; 1929 while (idx != sc_if->sk_cdata.sk_tx_prod) { 1930 SK_CDTXSYNC(sc_if, idx, 1, 1931 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1932 1933 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1934 sk_ctl = letoh32(cur_tx->sk_ctl); 1935 #ifdef SK_DEBUG 1936 if (skdebug >= 2) 1937 sk_dump_txdesc(cur_tx, idx); 1938 #endif 1939 if (sk_ctl & SK_TXCTL_OWN) { 1940 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 1941 break; 1942 } 1943 if (sk_ctl & SK_TXCTL_LASTFRAG) 1944 ifp->if_opackets++; 1945 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1946 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1947 1948 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1949 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1950 1951 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1952 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1953 1954 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1955 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1956 link); 1957 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1958 } 1959 sc_if->sk_cdata.sk_tx_cnt--; 1960 SK_INC(idx, SK_TX_RING_CNT); 1961 } 1962 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1963 1964 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 1965 ifp->if_flags &= ~IFF_OACTIVE; 1966 1967 sc_if->sk_cdata.sk_tx_cons = idx; 1968 } 1969 1970 void 1971 sk_tick(void *xsc_if) 1972 { 1973 struct sk_if_softc *sc_if = xsc_if; 1974 struct mii_data *mii = &sc_if->sk_mii; 1975 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1976 int i; 1977 1978 DPRINTFN(2, ("sk_tick\n")); 1979 1980 if (!(ifp->if_flags & IFF_UP)) 1981 return; 1982 1983 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1984 sk_intr_bcom(sc_if); 1985 return; 1986 } 1987 1988 /* 1989 * According to SysKonnect, the correct way to verify that 1990 * the link has come back up is to poll bit 0 of the GPIO 1991 * register three times. This pin has the signal from the 1992 * link sync pin connected to it; if we read the same link 1993 * state 3 times in a row, we know the link is up. 1994 */ 1995 for (i = 0; i < 3; i++) { 1996 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1997 break; 1998 } 1999 2000 if (i != 3) { 2001 timeout_add_sec(&sc_if->sk_tick_ch, 1); 2002 return; 2003 } 2004 2005 /* Turn the GP0 interrupt back on. */ 2006 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2007 SK_XM_READ_2(sc_if, XM_ISR); 2008 mii_tick(mii); 2009 timeout_del(&sc_if->sk_tick_ch); 2010 } 2011 2012 void 2013 sk_yukon_tick(void *xsc_if) 2014 { 2015 struct sk_if_softc *sc_if = xsc_if; 2016 struct mii_data *mii = &sc_if->sk_mii; 2017 int s; 2018 2019 s = splnet(); 2020 mii_tick(mii); 2021 splx(s); 2022 timeout_add_sec(&sc_if->sk_tick_ch, 1); 2023 } 2024 2025 void 2026 sk_intr_bcom(struct sk_if_softc *sc_if) 2027 { 2028 struct mii_data *mii = &sc_if->sk_mii; 2029 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2030 int status; 2031 2032 DPRINTFN(2, ("sk_intr_bcom\n")); 2033 2034 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2035 2036 /* 2037 * Read the PHY interrupt register to make sure 2038 * we clear any pending interrupts. 2039 */ 2040 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2041 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2042 2043 if (!(ifp->if_flags & IFF_RUNNING)) { 2044 sk_init_xmac(sc_if); 2045 return; 2046 } 2047 2048 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2049 int lstat; 2050 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2051 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2052 2053 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2054 mii_mediachg(mii); 2055 /* Turn off the link LED. */ 2056 SK_IF_WRITE_1(sc_if, 0, 2057 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2058 sc_if->sk_link = 0; 2059 } else if (status & BRGPHY_ISR_LNK_CHG) { 2060 sk_xmac_miibus_writereg((struct device *)sc_if, 2061 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2062 mii_tick(mii); 2063 sc_if->sk_link = 1; 2064 /* Turn on the link LED. */ 2065 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2066 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2067 SK_LINKLED_BLINK_OFF); 2068 } else { 2069 mii_tick(mii); 2070 timeout_add_sec(&sc_if->sk_tick_ch, 1); 2071 } 2072 } 2073 2074 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2075 } 2076 2077 void 2078 sk_intr_xmac(struct sk_if_softc *sc_if) 2079 { 2080 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2081 2082 DPRINTFN(2, ("sk_intr_xmac\n")); 2083 2084 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2085 if (status & XM_ISR_GP0_SET) { 2086 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2087 timeout_add_sec(&sc_if->sk_tick_ch, 1); 2088 } 2089 2090 if (status & XM_ISR_AUTONEG_DONE) { 2091 timeout_add_sec(&sc_if->sk_tick_ch, 1); 2092 } 2093 } 2094 2095 if (status & XM_IMR_TX_UNDERRUN) 2096 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2097 2098 if (status & XM_IMR_RX_OVERRUN) 2099 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2100 } 2101 2102 void 2103 sk_intr_yukon(struct sk_if_softc *sc_if) 2104 { 2105 u_int8_t status; 2106 2107 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2108 /* RX overrun */ 2109 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2110 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2111 SK_RFCTL_RX_FIFO_OVER); 2112 } 2113 /* TX underrun */ 2114 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2115 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2116 SK_TFCTL_TX_FIFO_UNDER); 2117 } 2118 2119 DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status)); 2120 } 2121 2122 int 2123 sk_intr(void *xsc) 2124 { 2125 struct sk_softc *sc = xsc; 2126 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2127 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2128 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2129 u_int32_t status; 2130 int claimed = 0; 2131 2132 status = CSR_READ_4(sc, SK_ISSR); 2133 if (status == 0 || status == 0xffffffff) 2134 return (0); 2135 2136 if (sc_if0 != NULL) 2137 ifp0 = &sc_if0->arpcom.ac_if; 2138 if (sc_if1 != NULL) 2139 ifp1 = &sc_if1->arpcom.ac_if; 2140 2141 for (; (status &= sc->sk_intrmask) != 0;) { 2142 claimed = 1; 2143 2144 /* Handle receive interrupts first. */ 2145 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2146 sk_rxeof(sc_if0); 2147 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2148 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2149 } 2150 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2151 sk_rxeof(sc_if1); 2152 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2153 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2154 } 2155 2156 /* Then transmit interrupts. */ 2157 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2158 sk_txeof(sc_if0); 2159 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2160 SK_TXBMU_CLR_IRQ_EOF); 2161 } 2162 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2163 sk_txeof(sc_if1); 2164 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2165 SK_TXBMU_CLR_IRQ_EOF); 2166 } 2167 2168 /* Then MAC interrupts. */ 2169 if (sc_if0 && (status & SK_ISR_MAC1) && 2170 (ifp0->if_flags & IFF_RUNNING)) { 2171 if (SK_IS_GENESIS(sc)) 2172 sk_intr_xmac(sc_if0); 2173 else 2174 sk_intr_yukon(sc_if0); 2175 } 2176 2177 if (sc_if1 && (status & SK_ISR_MAC2) && 2178 (ifp1->if_flags & IFF_RUNNING)) { 2179 if (SK_IS_GENESIS(sc)) 2180 sk_intr_xmac(sc_if1); 2181 else 2182 sk_intr_yukon(sc_if1); 2183 2184 } 2185 2186 if (status & SK_ISR_EXTERNAL_REG) { 2187 if (sc_if0 != NULL && 2188 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2189 sk_intr_bcom(sc_if0); 2190 2191 if (sc_if1 != NULL && 2192 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2193 sk_intr_bcom(sc_if1); 2194 } 2195 status = CSR_READ_4(sc, SK_ISSR); 2196 } 2197 2198 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2199 2200 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2201 sk_start(ifp0); 2202 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2203 sk_start(ifp1); 2204 2205 return (claimed); 2206 } 2207 2208 void 2209 sk_init_xmac(struct sk_if_softc *sc_if) 2210 { 2211 struct sk_softc *sc = sc_if->sk_softc; 2212 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2213 struct sk_bcom_hack bhack[] = { 2214 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2215 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2216 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2217 { 0, 0 } }; 2218 2219 DPRINTFN(2, ("sk_init_xmac\n")); 2220 2221 /* Unreset the XMAC. */ 2222 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2223 DELAY(1000); 2224 2225 /* Reset the XMAC's internal state. */ 2226 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2227 2228 /* Save the XMAC II revision */ 2229 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2230 2231 /* 2232 * Perform additional initialization for external PHYs, 2233 * namely for the 1000baseTX cards that use the XMAC's 2234 * GMII mode. 2235 */ 2236 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2237 int i = 0; 2238 u_int32_t val; 2239 2240 /* Take PHY out of reset. */ 2241 val = sk_win_read_4(sc, SK_GPIO); 2242 if (sc_if->sk_port == SK_PORT_A) 2243 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2244 else 2245 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2246 sk_win_write_4(sc, SK_GPIO, val); 2247 2248 /* Enable GMII mode on the XMAC. */ 2249 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2250 2251 sk_xmac_miibus_writereg((struct device *)sc_if, 2252 SK_PHYADDR_BCOM, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2253 DELAY(10000); 2254 sk_xmac_miibus_writereg((struct device *)sc_if, 2255 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2256 2257 /* 2258 * Early versions of the BCM5400 apparently have 2259 * a bug that requires them to have their reserved 2260 * registers initialized to some magic values. I don't 2261 * know what the numbers do, I'm just the messenger. 2262 */ 2263 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2264 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2265 while(bhack[i].reg) { 2266 sk_xmac_miibus_writereg((struct device *)sc_if, 2267 SK_PHYADDR_BCOM, bhack[i].reg, 2268 bhack[i].val); 2269 i++; 2270 } 2271 } 2272 } 2273 2274 /* Set station address */ 2275 SK_XM_WRITE_2(sc_if, XM_PAR0, 2276 letoh16(*(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0]))); 2277 SK_XM_WRITE_2(sc_if, XM_PAR1, 2278 letoh16(*(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2]))); 2279 SK_XM_WRITE_2(sc_if, XM_PAR2, 2280 letoh16(*(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4]))); 2281 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2282 2283 if (ifp->if_flags & IFF_BROADCAST) 2284 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2285 else 2286 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2287 2288 /* We don't need the FCS appended to the packet. */ 2289 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2290 2291 /* We want short frames padded to 60 bytes. */ 2292 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2293 2294 /* 2295 * Enable the reception of all error frames. This is 2296 * a necessary evil due to the design of the XMAC. The 2297 * XMAC's receive FIFO is only 8K in size, however jumbo 2298 * frames can be up to 9000 bytes in length. When bad 2299 * frame filtering is enabled, the XMAC's RX FIFO operates 2300 * in 'store and forward' mode. For this to work, the 2301 * entire frame has to fit into the FIFO, but that means 2302 * that jumbo frames larger than 8192 bytes will be 2303 * truncated. Disabling all bad frame filtering causes 2304 * the RX FIFO to operate in streaming mode, in which 2305 * case the XMAC will start transfering frames out of the 2306 * RX FIFO as soon as the FIFO threshold is reached. 2307 */ 2308 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2309 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2310 XM_MODE_RX_INRANGELEN); 2311 2312 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2313 2314 /* 2315 * Bump up the transmit threshold. This helps hold off transmit 2316 * underruns when we're blasting traffic from both ports at once. 2317 */ 2318 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2319 2320 /* Set promiscuous mode */ 2321 sk_setpromisc(sc_if); 2322 2323 /* Set multicast filter */ 2324 sk_setmulti(sc_if); 2325 2326 /* Clear and enable interrupts */ 2327 SK_XM_READ_2(sc_if, XM_ISR); 2328 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2329 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2330 else 2331 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2332 2333 /* Configure MAC arbiter */ 2334 switch(sc_if->sk_xmac_rev) { 2335 case XM_XMAC_REV_B2: 2336 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2337 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2338 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2339 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2340 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2341 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2342 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2343 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2344 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2345 break; 2346 case XM_XMAC_REV_C1: 2347 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2348 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2349 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2350 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2351 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2352 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2353 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2354 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2355 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2356 break; 2357 default: 2358 break; 2359 } 2360 sk_win_write_2(sc, SK_MACARB_CTL, 2361 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2362 2363 sc_if->sk_link = 1; 2364 } 2365 2366 void sk_init_yukon(struct sk_if_softc *sc_if) 2367 { 2368 u_int32_t phy, v; 2369 u_int16_t reg; 2370 struct sk_softc *sc; 2371 int i; 2372 2373 sc = sc_if->sk_softc; 2374 2375 DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n", 2376 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2377 2378 if (sc->sk_type == SK_YUKON_LITE && 2379 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2380 /* 2381 * Workaround code for COMA mode, set PHY reset. 2382 * Otherwise it will not correctly take chip out of 2383 * powerdown (coma) 2384 */ 2385 v = sk_win_read_4(sc, SK_GPIO); 2386 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 2387 sk_win_write_4(sc, SK_GPIO, v); 2388 } 2389 2390 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2391 2392 /* GMAC and GPHY Reset */ 2393 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2394 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2395 DELAY(1000); 2396 2397 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2398 2399 if (sc->sk_type == SK_YUKON_LITE && 2400 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2401 /* 2402 * Workaround code for COMA mode, clear PHY reset 2403 */ 2404 v = sk_win_read_4(sc, SK_GPIO); 2405 v |= SK_GPIO_DIR9; 2406 v &= ~SK_GPIO_DAT9; 2407 sk_win_write_4(sc, SK_GPIO, v); 2408 } 2409 2410 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2411 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2412 2413 if (sc->sk_coppertype) 2414 phy |= SK_GPHY_COPPER; 2415 else 2416 phy |= SK_GPHY_FIBER; 2417 2418 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2419 2420 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2421 DELAY(1000); 2422 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2423 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2424 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2425 2426 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2427 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2428 2429 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2430 2431 /* unused read of the interrupt source register */ 2432 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2433 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2434 2435 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2436 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2437 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2438 2439 /* MIB Counter Clear Mode set */ 2440 reg |= YU_PAR_MIB_CLR; 2441 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2442 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2443 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2444 2445 /* MIB Counter Clear Mode clear */ 2446 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2447 reg &= ~YU_PAR_MIB_CLR; 2448 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2449 2450 /* receive control reg */ 2451 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2452 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2453 2454 /* transmit parameter register */ 2455 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2456 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2457 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2458 2459 /* serial mode register */ 2460 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2461 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2462 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2463 YU_SMR_IPG_DATA(0x1e)); 2464 2465 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2466 /* Setup Yukon's address */ 2467 for (i = 0; i < 3; i++) { 2468 /* Write Source Address 1 (unicast filter) */ 2469 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2470 sc_if->arpcom.ac_enaddr[i * 2] | 2471 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2472 } 2473 2474 for (i = 0; i < 3; i++) { 2475 reg = sk_win_read_2(sc_if->sk_softc, 2476 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2477 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2478 } 2479 2480 /* Set promiscuous mode */ 2481 sk_setpromisc(sc_if); 2482 2483 /* Set multicast filter */ 2484 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2485 sk_setmulti(sc_if); 2486 2487 /* enable interrupt mask for counter overflows */ 2488 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2489 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2490 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2491 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2492 2493 /* Configure RX MAC FIFO Flush Mask */ 2494 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2495 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2496 YU_RXSTAT_JABBER; 2497 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2498 2499 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 2500 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 2501 v = SK_TFCTL_OPERATION_ON; 2502 else 2503 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 2504 /* Configure RX MAC FIFO */ 2505 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2506 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 2507 2508 /* Increase flush threshould to 64 bytes */ 2509 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2510 SK_RFCTL_FIFO_THRESHOLD + 1); 2511 2512 /* Configure TX MAC FIFO */ 2513 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2514 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2515 2516 DPRINTFN(6, ("sk_init_yukon: end\n")); 2517 } 2518 2519 /* 2520 * Note that to properly initialize any part of the GEnesis chip, 2521 * you first have to take it out of reset mode. 2522 */ 2523 void 2524 sk_init(void *xsc_if) 2525 { 2526 struct sk_if_softc *sc_if = xsc_if; 2527 struct sk_softc *sc = sc_if->sk_softc; 2528 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2529 struct mii_data *mii = &sc_if->sk_mii; 2530 int s; 2531 2532 DPRINTFN(2, ("sk_init\n")); 2533 2534 s = splnet(); 2535 2536 /* Cancel pending I/O and free all RX/TX buffers. */ 2537 sk_stop(sc_if, 0); 2538 2539 if (SK_IS_GENESIS(sc)) { 2540 /* Configure LINK_SYNC LED */ 2541 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2542 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2543 SK_LINKLED_LINKSYNC_ON); 2544 2545 /* Configure RX LED */ 2546 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2547 SK_RXLEDCTL_COUNTER_START); 2548 2549 /* Configure TX LED */ 2550 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2551 SK_TXLEDCTL_COUNTER_START); 2552 } 2553 2554 /* 2555 * Configure descriptor poll timer 2556 * 2557 * SK-NET GENESIS data sheet says that possibility of losing Start 2558 * transmit command due to CPU/cache related interim storage problems 2559 * under certain conditions. The document recommends a polling 2560 * mechanism to send a Start transmit command to initiate transfer 2561 * of ready descriptors regulary. To cope with this issue sk(4) now 2562 * enables descriptor poll timer to initiate descriptor processing 2563 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 2564 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 2565 * command instead of waiting for next descriptor polling time. 2566 * The same rule may apply to Rx side too but it seems that is not 2567 * needed at the moment. 2568 * Since sk(4) uses descriptor polling as a last resort there is no 2569 * need to set smaller polling time than maximum allowable one. 2570 */ 2571 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 2572 2573 /* Configure I2C registers */ 2574 2575 /* Configure XMAC(s) */ 2576 switch (sc->sk_type) { 2577 case SK_GENESIS: 2578 sk_init_xmac(sc_if); 2579 break; 2580 case SK_YUKON: 2581 case SK_YUKON_LITE: 2582 case SK_YUKON_LP: 2583 sk_init_yukon(sc_if); 2584 break; 2585 } 2586 mii_mediachg(mii); 2587 2588 if (SK_IS_GENESIS(sc)) { 2589 /* Configure MAC FIFOs */ 2590 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2591 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2592 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2593 2594 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2595 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2596 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2597 } 2598 2599 /* Configure transmit arbiter(s) */ 2600 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2601 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2602 2603 /* Configure RAMbuffers */ 2604 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2605 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2606 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2607 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2608 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2609 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2610 2611 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2612 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2613 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2614 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2615 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2616 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2617 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2618 2619 /* Configure BMUs */ 2620 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2621 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2622 SK_RX_RING_ADDR(sc_if, 0)); 2623 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2624 2625 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2626 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2627 SK_TX_RING_ADDR(sc_if, 0)); 2628 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2629 2630 /* Init descriptors */ 2631 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2632 printf("%s: initialization failed: no " 2633 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2634 sk_stop(sc_if, 0); 2635 splx(s); 2636 return; 2637 } 2638 2639 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2640 printf("%s: initialization failed: no " 2641 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2642 sk_stop(sc_if, 0); 2643 splx(s); 2644 return; 2645 } 2646 2647 /* Configure interrupt handling */ 2648 CSR_READ_4(sc, SK_ISSR); 2649 if (sc_if->sk_port == SK_PORT_A) 2650 sc->sk_intrmask |= SK_INTRS1; 2651 else 2652 sc->sk_intrmask |= SK_INTRS2; 2653 2654 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2655 2656 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2657 2658 /* Start BMUs. */ 2659 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2660 2661 if (SK_IS_GENESIS(sc)) { 2662 /* Enable XMACs TX and RX state machines */ 2663 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2664 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2665 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2666 } 2667 2668 if (SK_IS_YUKON(sc)) { 2669 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2670 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2671 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2672 } 2673 2674 /* Activate descriptor polling timer */ 2675 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 2676 /* start transfer of Tx descriptors */ 2677 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2678 2679 ifp->if_flags |= IFF_RUNNING; 2680 ifp->if_flags &= ~IFF_OACTIVE; 2681 2682 if (SK_IS_YUKON(sc)) 2683 timeout_add_sec(&sc_if->sk_tick_ch, 1); 2684 2685 splx(s); 2686 } 2687 2688 void 2689 sk_stop(struct sk_if_softc *sc_if, int softonly) 2690 { 2691 struct sk_softc *sc = sc_if->sk_softc; 2692 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2693 struct sk_txmap_entry *dma; 2694 int i; 2695 u_int32_t val; 2696 2697 DPRINTFN(2, ("sk_stop\n")); 2698 2699 timeout_del(&sc_if->sk_tick_ch); 2700 2701 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2702 2703 if (!softonly) { 2704 /* stop Tx descriptor polling timer */ 2705 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 2706 /* stop transfer of Tx descriptors */ 2707 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 2708 for (i = 0; i < SK_TIMEOUT; i++) { 2709 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 2710 if (!(val & SK_TXBMU_TX_STOP)) 2711 break; 2712 DELAY(1); 2713 } 2714 if (i == SK_TIMEOUT) 2715 printf("%s: cannot stop transfer of Tx descriptors\n", 2716 sc_if->sk_dev.dv_xname); 2717 /* stop transfer of Rx descriptors */ 2718 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 2719 for (i = 0; i < SK_TIMEOUT; i++) { 2720 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 2721 if (!(val & SK_RXBMU_RX_STOP)) 2722 break; 2723 DELAY(1); 2724 } 2725 if (i == SK_TIMEOUT) 2726 printf("%s: cannot stop transfer of Rx descriptors\n", 2727 sc_if->sk_dev.dv_xname); 2728 2729 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2730 u_int32_t val; 2731 2732 /* Put PHY back into reset. */ 2733 val = sk_win_read_4(sc, SK_GPIO); 2734 if (sc_if->sk_port == SK_PORT_A) { 2735 val |= SK_GPIO_DIR0; 2736 val &= ~SK_GPIO_DAT0; 2737 } else { 2738 val |= SK_GPIO_DIR2; 2739 val &= ~SK_GPIO_DAT2; 2740 } 2741 sk_win_write_4(sc, SK_GPIO, val); 2742 } 2743 2744 /* Turn off various components of this interface. */ 2745 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2746 switch (sc->sk_type) { 2747 case SK_GENESIS: 2748 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2749 SK_TXMACCTL_XMAC_RESET); 2750 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2751 break; 2752 case SK_YUKON: 2753 case SK_YUKON_LITE: 2754 case SK_YUKON_LP: 2755 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2756 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2757 break; 2758 } 2759 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2760 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2761 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2762 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2763 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2764 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2765 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2766 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2767 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2768 2769 /* Disable interrupts */ 2770 if (sc_if->sk_port == SK_PORT_A) 2771 sc->sk_intrmask &= ~SK_INTRS1; 2772 else 2773 sc->sk_intrmask &= ~SK_INTRS2; 2774 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2775 2776 SK_XM_READ_2(sc_if, XM_ISR); 2777 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2778 } 2779 2780 /* Free RX and TX mbufs still in the queues. */ 2781 for (i = 0; i < SK_RX_RING_CNT; i++) { 2782 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2783 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2784 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2785 } 2786 } 2787 2788 for (i = 0; i < SK_TX_RING_CNT; i++) { 2789 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2790 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2791 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2792 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2793 sc_if->sk_cdata.sk_tx_map[i], link); 2794 sc_if->sk_cdata.sk_tx_map[i] = 0; 2795 } 2796 } 2797 2798 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2799 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2800 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2801 free(dma, M_DEVBUF); 2802 } 2803 } 2804 2805 struct cfattach skc_ca = { 2806 sizeof(struct sk_softc), skc_probe, skc_attach, skc_detach 2807 }; 2808 2809 struct cfdriver skc_cd = { 2810 0, "skc", DV_DULL 2811 }; 2812 2813 struct cfattach sk_ca = { 2814 sizeof(struct sk_if_softc), sk_probe, sk_attach, sk_detach 2815 }; 2816 2817 struct cfdriver sk_cd = { 2818 NULL, "sk", DV_IFNET 2819 }; 2820 2821 #ifdef SK_DEBUG 2822 void 2823 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2824 { 2825 #define DESC_PRINT(X) \ 2826 if (X) \ 2827 printf("txdesc[%d]." #X "=%#x\n", \ 2828 idx, X); 2829 2830 DESC_PRINT(letoh32(desc->sk_ctl)); 2831 DESC_PRINT(letoh32(desc->sk_next)); 2832 DESC_PRINT(letoh32(desc->sk_data_lo)); 2833 DESC_PRINT(letoh32(desc->sk_data_hi)); 2834 DESC_PRINT(letoh32(desc->sk_xmac_txstat)); 2835 DESC_PRINT(letoh16(desc->sk_rsvd0)); 2836 DESC_PRINT(letoh16(desc->sk_csum_startval)); 2837 DESC_PRINT(letoh16(desc->sk_csum_startpos)); 2838 DESC_PRINT(letoh16(desc->sk_csum_writepos)); 2839 DESC_PRINT(letoh16(desc->sk_rsvd1)); 2840 #undef PRINT 2841 } 2842 2843 void 2844 sk_dump_bytes(const char *data, int len) 2845 { 2846 int c, i, j; 2847 2848 for (i = 0; i < len; i += 16) { 2849 printf("%08x ", i); 2850 c = len - i; 2851 if (c > 16) c = 16; 2852 2853 for (j = 0; j < c; j++) { 2854 printf("%02x ", data[i + j] & 0xff); 2855 if ((j & 0xf) == 7 && j > 0) 2856 printf(" "); 2857 } 2858 2859 for (; j < 16; j++) 2860 printf(" "); 2861 printf(" "); 2862 2863 for (j = 0; j < c; j++) { 2864 int ch = data[i + j] & 0xff; 2865 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2866 } 2867 2868 printf("\n"); 2869 2870 if (c < 16) 2871 break; 2872 } 2873 } 2874 2875 void 2876 sk_dump_mbuf(struct mbuf *m) 2877 { 2878 int count = m->m_pkthdr.len; 2879 2880 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2881 2882 while (count > 0 && m) { 2883 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2884 m, m->m_data, m->m_len); 2885 sk_dump_bytes(mtod(m, char *), m->m_len); 2886 2887 count -= m->m_len; 2888 m = m->m_next; 2889 } 2890 } 2891 #endif 2892