1 /* $OpenBSD: if_sk.c,v 1.14 2001/08/12 20:03:49 mickey Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 39 * the SK-984x series adapters, both single port and dual port. 40 * References: 41 * The XaQti XMAC II datasheet, 42 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 43 * The SysKonnect GEnesis manual, http://www.syskonnect.com 44 * 45 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 46 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 47 * convience to others until Vitesse corrects this problem: 48 * 49 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 50 * 51 * Written by Bill Paul <wpaul@ee.columbia.edu> 52 * Department of Electrical Engineering 53 * Columbia University, New York City 54 */ 55 56 /* 57 * The SysKonnect gigabit ethernet adapters consist of two main 58 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 59 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 60 * components and a PHY while the GEnesis controller provides a PCI 61 * interface with DMA support. Each card may have between 512K and 62 * 2MB of SRAM on board depending on the configuration. 63 * 64 * The SysKonnect GEnesis controller can have either one or two XMAC 65 * chips connected to it, allowing single or dual port NIC configurations. 66 * SysKonnect has the distinction of being the only vendor on the market 67 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 68 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 69 * XMAC registers. This driver takes advantage of these features to allow 70 * both XMACs to operate as independent interfaces. 71 */ 72 73 #include "bpfilter.h" 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/sockio.h> 78 #include <sys/mbuf.h> 79 #include <sys/malloc.h> 80 #include <sys/kernel.h> 81 #include <sys/socket.h> 82 #include <sys/device.h> 83 #include <sys/queue.h> 84 85 #include <net/if.h> 86 #include <net/if_dl.h> 87 #include <net/if_types.h> 88 89 #ifdef INET 90 #include <netinet/in.h> 91 #include <netinet/in_systm.h> 92 #include <netinet/in_var.h> 93 #include <netinet/ip.h> 94 #include <netinet/if_ether.h> 95 #endif 96 97 #include <net/if_media.h> 98 99 #if NBPFILTER > 0 100 #include <net/bpf.h> 101 #endif 102 103 #include <vm/vm.h> /* for vtophys */ 104 #include <vm/vm_kern.h> 105 #include <machine/bus.h> 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 #include <dev/mii/brgphyreg.h> 110 111 #include <dev/pci/pcireg.h> 112 #include <dev/pci/pcivar.h> 113 #include <dev/pci/pcidevs.h> 114 115 #define SK_USEIOSPACE 116 #define SK_VERBOSE 117 118 #include <dev/pci/if_skreg.h> 119 #include <dev/pci/xmaciireg.h> 120 121 int skc_probe __P((struct device *, void *, void *)); 122 void skc_attach __P((struct device *, struct device *self, void *aux)); 123 int sk_probe __P((struct device *, void *, void *)); 124 void sk_attach __P((struct device *, struct device *self, void *aux)); 125 int skcprint __P((void *, const char *)); 126 int sk_attach_xmac __P((struct sk_softc *, int)); 127 int sk_intr __P((void *)); 128 void sk_intr_bcom __P((struct sk_if_softc *)); 129 void sk_intr_xmac __P((struct sk_if_softc *)); 130 void sk_rxeof __P((struct sk_if_softc *)); 131 void sk_txeof __P((struct sk_if_softc *)); 132 int sk_encap __P((struct sk_if_softc *, struct mbuf *, u_int32_t *)); 133 void sk_start __P((struct ifnet *)); 134 int sk_ioctl __P((struct ifnet *, u_long, caddr_t)); 135 void sk_init __P((void *)); 136 void sk_init_xmac __P((struct sk_if_softc *)); 137 void sk_stop __P((struct sk_if_softc *)); 138 void sk_watchdog __P((struct ifnet *)); 139 void sk_shutdown __P((void *)); 140 int sk_ifmedia_upd __P((struct ifnet *)); 141 void sk_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 142 void sk_reset __P((struct sk_softc *)); 143 int sk_newbuf __P((struct sk_if_softc *, struct sk_chain *, 144 struct mbuf *)); 145 int sk_init_rx_ring __P((struct sk_if_softc *)); 146 void sk_init_tx_ring __P((struct sk_if_softc *)); 147 u_int32_t sk_win_read_4 __P((struct sk_softc *, int)); 148 u_int16_t sk_win_read_2 __P((struct sk_softc *, int)); 149 u_int8_t sk_win_read_1 __P((struct sk_softc *, int)); 150 void sk_win_write_4 __P((struct sk_softc *, int, u_int32_t)); 151 void sk_win_write_2 __P((struct sk_softc *, int, u_int32_t)); 152 void sk_win_write_1 __P((struct sk_softc *, int, u_int32_t)); 153 u_int8_t sk_vpd_readbyte __P((struct sk_softc *, int)); 154 void sk_vpd_read_res __P((struct sk_softc *, 155 struct vpd_res *, int)); 156 void sk_vpd_read __P((struct sk_softc *)); 157 158 int sk_miibus_readreg __P((struct device *, int, int)); 159 void sk_miibus_writereg __P((struct device *, int, int, int)); 160 void sk_miibus_statchg __P((struct device *)); 161 162 u_int32_t sk_calchash __P((caddr_t)); 163 void sk_setfilt __P((struct sk_if_softc *, caddr_t, int)); 164 void sk_setmulti __P((struct sk_if_softc *)); 165 void sk_tick __P((void *)); 166 167 #define SK_SETBIT(sc, reg, x) \ 168 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 169 170 #define SK_CLRBIT(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 172 173 #define SK_WIN_SETBIT_4(sc, reg, x) \ 174 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 175 176 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 177 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 178 179 #define SK_WIN_SETBIT_2(sc, reg, x) \ 180 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 181 182 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 183 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 184 185 u_int32_t sk_win_read_4(sc, reg) 186 struct sk_softc *sc; 187 int reg; 188 { 189 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 190 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 191 } 192 193 u_int16_t sk_win_read_2(sc, reg) 194 struct sk_softc *sc; 195 int reg; 196 { 197 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 198 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 199 } 200 201 u_int8_t sk_win_read_1(sc, reg) 202 struct sk_softc *sc; 203 int reg; 204 { 205 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 206 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 207 } 208 209 void sk_win_write_4(sc, reg, val) 210 struct sk_softc *sc; 211 int reg; 212 u_int32_t val; 213 { 214 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 215 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 216 return; 217 } 218 219 void sk_win_write_2(sc, reg, val) 220 struct sk_softc *sc; 221 int reg; 222 u_int32_t val; 223 { 224 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 225 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), (u_int32_t)val); 226 return; 227 } 228 229 void sk_win_write_1(sc, reg, val) 230 struct sk_softc *sc; 231 int reg; 232 u_int32_t val; 233 { 234 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 235 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 236 return; 237 } 238 239 /* 240 * The VPD EEPROM contains Vital Product Data, as suggested in 241 * the PCI 2.1 specification. The VPD data is separared into areas 242 * denoted by resource IDs. The SysKonnect VPD contains an ID string 243 * resource (the name of the adapter), a read-only area resource 244 * containing various key/data fields and a read/write area which 245 * can be used to store asset management information or log messages. 246 * We read the ID string and read-only into buffers attached to 247 * the controller softc structure for later use. At the moment, 248 * we only use the ID string during sk_attach(). 249 */ 250 u_int8_t sk_vpd_readbyte(sc, addr) 251 struct sk_softc *sc; 252 int addr; 253 { 254 int i; 255 256 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 257 for (i = 0; i < SK_TIMEOUT; i++) { 258 DELAY(1); 259 if (sk_win_read_2(sc, 260 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 261 break; 262 } 263 264 if (i == SK_TIMEOUT) 265 return(0); 266 267 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 268 } 269 270 void sk_vpd_read_res(sc, res, addr) 271 struct sk_softc *sc; 272 struct vpd_res *res; 273 int addr; 274 { 275 int i; 276 u_int8_t *ptr; 277 278 ptr = (u_int8_t *)res; 279 for (i = 0; i < sizeof(struct vpd_res); i++) 280 ptr[i] = sk_vpd_readbyte(sc, i + addr); 281 282 return; 283 } 284 285 void sk_vpd_read(sc) 286 struct sk_softc *sc; 287 { 288 int pos = 0, i; 289 struct vpd_res res; 290 291 if (sc->sk_vpd_prodname != NULL) 292 free(sc->sk_vpd_prodname, M_DEVBUF); 293 if (sc->sk_vpd_readonly != NULL) 294 free(sc->sk_vpd_readonly, M_DEVBUF); 295 sc->sk_vpd_prodname = NULL; 296 sc->sk_vpd_readonly = NULL; 297 298 sk_vpd_read_res(sc, &res, pos); 299 300 if (res.vr_id != VPD_RES_ID) { 301 printf("%s: bad VPD resource id: expected %x got %x\n", 302 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 303 return; 304 } 305 306 pos += sizeof(res); 307 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 308 for (i = 0; i < res.vr_len; i++) 309 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 310 sc->sk_vpd_prodname[i] = '\0'; 311 pos += i; 312 313 sk_vpd_read_res(sc, &res, pos); 314 315 if (res.vr_id != VPD_RES_READ) { 316 printf("%s: bad VPD resource id: expected %x got %x\n", 317 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 318 return; 319 } 320 321 pos += sizeof(res); 322 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 323 for (i = 0; i < res.vr_len + 1; i++) 324 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 325 326 return; 327 } 328 329 int 330 sk_miibus_readreg(dev, phy, reg) 331 struct device *dev; 332 int phy, reg; 333 { 334 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 335 int i; 336 337 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 338 return(0); 339 340 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 341 SK_XM_READ_2(sc_if, XM_PHY_DATA); 342 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 343 for (i = 0; i < SK_TIMEOUT; i++) { 344 DELAY(1); 345 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 346 XM_MMUCMD_PHYDATARDY) 347 break; 348 } 349 350 if (i == SK_TIMEOUT) { 351 printf("%s: phy failed to come ready\n", 352 sc_if->sk_dev.dv_xname); 353 return(0); 354 } 355 } 356 DELAY(1); 357 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 358 } 359 360 void 361 sk_miibus_writereg(dev, phy, reg, val) 362 struct device *dev; 363 int phy, reg, val; 364 { 365 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 366 int i; 367 368 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 369 for (i = 0; i < SK_TIMEOUT; i++) { 370 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 371 break; 372 } 373 374 if (i == SK_TIMEOUT) { 375 printf("%s: phy failed to come ready\n", 376 sc_if->sk_dev.dv_xname); 377 return; 378 } 379 380 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 381 for (i = 0; i < SK_TIMEOUT; i++) { 382 DELAY(1); 383 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 384 break; 385 } 386 387 if (i == SK_TIMEOUT) 388 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 389 390 return; 391 } 392 393 void 394 sk_miibus_statchg(dev) 395 struct device *dev; 396 { 397 struct sk_if_softc *sc_if; 398 struct mii_data *mii; 399 400 sc_if = (struct sk_if_softc *)dev; 401 mii = &sc_if->sk_mii; 402 403 /* 404 * If this is a GMII PHY, manually set the XMAC's 405 * duplex mode accordingly. 406 */ 407 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 408 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 409 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 410 } else { 411 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 412 } 413 } 414 415 return; 416 } 417 418 #define SK_POLY 0xEDB88320 419 #define SK_BITS 6 420 421 u_int32_t sk_calchash(addr) 422 caddr_t addr; 423 { 424 u_int32_t idx, bit, data, crc; 425 426 /* Compute CRC for the address value. */ 427 crc = 0xFFFFFFFF; /* initial value */ 428 429 for (idx = 0; idx < 6; idx++) { 430 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 431 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0); 432 } 433 434 return (~crc & ((1 << SK_BITS) - 1)); 435 } 436 437 void sk_setfilt(sc_if, addr, slot) 438 struct sk_if_softc *sc_if; 439 caddr_t addr; 440 int slot; 441 { 442 int base; 443 444 base = XM_RXFILT_ENTRY(slot); 445 446 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 447 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 448 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 449 450 return; 451 } 452 453 void 454 sk_setmulti(sc_if) 455 struct sk_if_softc *sc_if; 456 { 457 struct ifnet *ifp; 458 u_int32_t hashes[2] = { 0, 0 }; 459 int h, i; 460 struct arpcom *ac = &sc_if->arpcom; 461 struct ether_multi *enm; 462 struct ether_multistep step; 463 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 464 465 ifp = &sc_if->arpcom.ac_if; 466 467 /* First, zot all the existing filters. */ 468 for (i = 1; i < XM_RXFILT_MAX; i++) 469 sk_setfilt(sc_if, (caddr_t)&dummy, i); 470 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 471 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 472 473 /* Now program new ones. */ 474 allmulti: 475 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 476 hashes[0] = 0xFFFFFFFF; 477 hashes[1] = 0xFFFFFFFF; 478 } else { 479 i = 1; 480 /* First find the tail of the list. */ 481 ETHER_FIRST_MULTI(step, ac, enm); 482 while (enm != NULL) { 483 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 484 ifp->if_flags |= IFF_ALLMULTI; 485 goto allmulti; 486 } 487 /* 488 * Program the first XM_RXFILT_MAX multicast groups 489 * into the perfect filter. For all others, 490 * use the hash table. 491 */ 492 if (i < XM_RXFILT_MAX) { 493 sk_setfilt(sc_if, enm->enm_addrlo, i); 494 i++; 495 } 496 else { 497 h = sk_calchash(enm->enm_addrlo); 498 if (h < 32) 499 hashes[0] |= (1 << h); 500 else 501 hashes[1] |= (1 << (h - 32)); 502 } 503 504 ETHER_NEXT_MULTI(step, enm); 505 } 506 } 507 508 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 509 XM_MODE_RX_USE_PERFECT); 510 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 511 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 512 513 return; 514 } 515 516 int sk_init_rx_ring(sc_if) 517 struct sk_if_softc *sc_if; 518 { 519 struct sk_chain_data *cd; 520 struct sk_ring_data *rd; 521 int i; 522 523 cd = &sc_if->sk_cdata; 524 rd = sc_if->sk_rdata; 525 526 bzero((char *)rd->sk_rx_ring, 527 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 528 529 for (i = 0; i < SK_RX_RING_CNT; i++) { 530 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 531 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) { 532 printf("%s: failed alloc of %dth mbuf\n", 533 sc_if->sk_dev.dv_xname, i); 534 return(ENOBUFS); 535 } 536 if (i == (SK_RX_RING_CNT - 1)) { 537 cd->sk_rx_chain[i].sk_next = 538 &cd->sk_rx_chain[0]; 539 rd->sk_rx_ring[i].sk_next = 540 vtophys(&rd->sk_rx_ring[0]); 541 } else { 542 cd->sk_rx_chain[i].sk_next = 543 &cd->sk_rx_chain[i + 1]; 544 rd->sk_rx_ring[i].sk_next = 545 vtophys(&rd->sk_rx_ring[i + 1]); 546 } 547 } 548 549 sc_if->sk_cdata.sk_rx_prod = 0; 550 sc_if->sk_cdata.sk_rx_cons = 0; 551 552 return(0); 553 } 554 555 void sk_init_tx_ring(sc_if) 556 struct sk_if_softc *sc_if; 557 { 558 struct sk_chain_data *cd; 559 struct sk_ring_data *rd; 560 int i; 561 562 cd = &sc_if->sk_cdata; 563 rd = sc_if->sk_rdata; 564 565 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 566 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 567 568 for (i = 0; i < SK_TX_RING_CNT; i++) { 569 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 570 if (i == (SK_TX_RING_CNT - 1)) { 571 cd->sk_tx_chain[i].sk_next = 572 &cd->sk_tx_chain[0]; 573 rd->sk_tx_ring[i].sk_next = 574 vtophys(&rd->sk_tx_ring[0]); 575 } else { 576 cd->sk_tx_chain[i].sk_next = 577 &cd->sk_tx_chain[i + 1]; 578 rd->sk_tx_ring[i].sk_next = 579 vtophys(&rd->sk_tx_ring[i + 1]); 580 } 581 } 582 583 sc_if->sk_cdata.sk_tx_prod = 0; 584 sc_if->sk_cdata.sk_tx_cons = 0; 585 sc_if->sk_cdata.sk_tx_cnt = 0; 586 587 return; 588 } 589 590 int sk_newbuf(sc_if, c, m) 591 struct sk_if_softc *sc_if; 592 struct sk_chain *c; 593 struct mbuf *m; 594 { 595 struct mbuf *m_new = NULL; 596 struct sk_rx_desc *r; 597 598 if (m == NULL) { 599 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 600 if (m_new == NULL) { 601 printf("%s: no memory for rx list -- " 602 "packet dropped!\n", sc_if->sk_dev.dv_xname); 603 return(ENOBUFS); 604 } 605 606 /* Allocate the jumbo buffer */ 607 MCLGET(m_new, M_DONTWAIT); 608 if (!(m_new->m_flags & M_EXT)) { 609 m_freem(m_new); 610 return (ENOBUFS); 611 } 612 } else { 613 /* 614 * We're re-using a previously allocated mbuf; 615 * be sure to re-init pointers and lengths to 616 * default values. 617 */ 618 m_new = m; 619 m_new->m_data = m_new->m_ext.ext_buf; 620 } 621 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 622 623 /* 624 * Adjust alignment so packet payload begins on a 625 * longword boundary. Mandatory for Alpha, useful on 626 * x86 too. 627 */ 628 m_adj(m_new, ETHER_ALIGN); 629 630 r = c->sk_desc; 631 c->sk_mbuf = m_new; 632 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 633 r->sk_ctl = m_new->m_len | SK_RXSTAT; 634 635 return(0); 636 } 637 638 /* 639 * Set media options. 640 */ 641 int 642 sk_ifmedia_upd(ifp) 643 struct ifnet *ifp; 644 { 645 struct sk_if_softc *sc_if = ifp->if_softc; 646 647 sk_init(sc_if); 648 mii_mediachg(&sc_if->sk_mii); 649 return(0); 650 } 651 652 /* 653 * Report current media status. 654 */ 655 void 656 sk_ifmedia_sts(ifp, ifmr) 657 struct ifnet *ifp; 658 struct ifmediareq *ifmr; 659 { 660 struct sk_if_softc *sc_if = ifp->if_softc; 661 662 mii_pollstat(&sc_if->sk_mii); 663 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 664 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 665 } 666 667 int 668 sk_ioctl(ifp, command, data) 669 struct ifnet *ifp; 670 u_long command; 671 caddr_t data; 672 { 673 struct sk_if_softc *sc_if = ifp->if_softc; 674 struct ifreq *ifr = (struct ifreq *) data; 675 struct ifaddr *ifa = (struct ifaddr *) data; 676 struct mii_data *mii; 677 int s, error = 0; 678 679 s = splimp(); 680 681 if ((error = ether_ioctl(ifp, &sc_if->arpcom, command, data)) > 0) { 682 splx(s); 683 return error; 684 } 685 686 switch(command) { 687 case SIOCSIFADDR: 688 ifp->if_flags |= IFF_UP; 689 switch (ifa->ifa_addr->sa_family) { 690 #ifdef INET 691 case AF_INET: 692 sk_init(sc_if); 693 arp_ifinit(&sc_if->arpcom, ifa); 694 break; 695 #endif /* INET */ 696 default: 697 sk_init(sc_if); 698 break; 699 } 700 break; 701 case SIOCSIFFLAGS: 702 if (ifp->if_flags & IFF_UP) { 703 if (ifp->if_flags & IFF_RUNNING && 704 ifp->if_flags & IFF_PROMISC && 705 !(sc_if->sk_if_flags & IFF_PROMISC)) { 706 SK_XM_SETBIT_4(sc_if, XM_MODE, 707 XM_MODE_RX_PROMISC); 708 sk_setmulti(sc_if); 709 } else if (ifp->if_flags & IFF_RUNNING && 710 !(ifp->if_flags & IFF_PROMISC) && 711 sc_if->sk_if_flags & IFF_PROMISC) { 712 SK_XM_CLRBIT_4(sc_if, XM_MODE, 713 XM_MODE_RX_PROMISC); 714 sk_setmulti(sc_if); 715 } else 716 sk_init(sc_if); 717 } else { 718 if (ifp->if_flags & IFF_RUNNING) 719 sk_stop(sc_if); 720 } 721 sc_if->sk_if_flags = ifp->if_flags; 722 error = 0; 723 break; 724 case SIOCADDMULTI: 725 case SIOCDELMULTI: 726 error = (command == SIOCADDMULTI) ? 727 ether_addmulti(ifr, &sc_if->arpcom) : 728 ether_delmulti(ifr, &sc_if->arpcom); 729 730 if (error == ENETRESET) { 731 /* 732 * Multicast list has changed; set the hardware 733 * filter accordingly. 734 */ 735 sk_setmulti(sc_if); 736 error = 0; 737 } 738 break; 739 case SIOCGIFMEDIA: 740 case SIOCSIFMEDIA: 741 mii = &sc_if->sk_mii; 742 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 743 break; 744 default: 745 error = EINVAL; 746 break; 747 } 748 749 (void)splx(s); 750 751 return(error); 752 } 753 754 /* 755 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 756 * IDs against our list and return a device name if we find a match. 757 */ 758 int 759 skc_probe(parent, match, aux) 760 struct device *parent; 761 void *match, *aux; 762 { 763 struct pci_attach_args *pa = aux; 764 765 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SCHNEIDERKOCH) 766 return (0); 767 768 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_SCHNEIDERKOCH_GE) 769 return (0); 770 771 return (1); 772 } 773 774 /* 775 * Force the GEnesis into reset, then bring it out of reset. 776 */ 777 void sk_reset(sc) 778 struct sk_softc *sc; 779 { 780 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_RESET); 781 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_RESET); 782 DELAY(1000); 783 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_UNRESET); 784 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 785 786 /* Configure packet arbiter */ 787 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 788 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 789 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 790 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 791 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 792 793 /* Enable RAM interface */ 794 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 795 796 /* 797 * Configure interrupt moderation. The moderation timer 798 * defers interrupts specified in the interrupt moderation 799 * timer mask based on the timeout specified in the interrupt 800 * moderation timer init register. Each bit in the timer 801 * register represents 18.825ns, so to specify a timeout in 802 * microseconds, we have to multiply by 54. 803 */ 804 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 805 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 806 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 807 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 808 809 return; 810 } 811 812 int 813 sk_probe(parent, match, aux) 814 struct device *parent; 815 void *match, *aux; 816 { 817 struct skc_attach_args *sa = aux; 818 819 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 820 return(0); 821 822 return (1); 823 } 824 825 /* 826 * Each XMAC chip is attached as a separate logical IP interface. 827 * Single port cards will have only one logical interface of course. 828 */ 829 void 830 sk_attach(parent, self, aux) 831 struct device *parent, *self; 832 void *aux; 833 { 834 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 835 struct sk_softc *sc = (struct sk_softc *)parent; 836 struct skc_attach_args *sa = aux; 837 struct ifnet *ifp; 838 caddr_t kva; 839 bus_dma_segment_t seg; 840 bus_dmamap_t dmamap; 841 int i, rseg; 842 843 sc_if->sk_port = sa->skc_port; 844 sc_if->sk_softc = sc; 845 sc->sk_if[sa->skc_port] = sc_if; 846 847 if (sa->skc_port == SK_PORT_A) 848 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 849 if (sa->skc_port == SK_PORT_B) 850 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 851 852 /* 853 * Get station address for this interface. Note that 854 * dual port cards actually come with three station 855 * addresses: one for each port, plus an extra. The 856 * extra one is used by the SysKonnect driver software 857 * as a 'virtual' station address for when both ports 858 * are operating in failover mode. Currently we don't 859 * use this extra address. 860 */ 861 for (i = 0; i < ETHER_ADDR_LEN; i++) 862 sc_if->arpcom.ac_enaddr[i] = 863 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 864 865 866 printf(": address %s\n", 867 ether_sprintf(sc_if->arpcom.ac_enaddr)); 868 869 /* 870 * Set up RAM buffer addresses. The NIC will have a certain 871 * amount of SRAM on it, somewhere between 512K and 2MB. We 872 * need to divide this up a) between the transmitter and 873 * receiver and b) between the two XMACs, if this is a 874 * dual port NIC. Our algotithm is to divide up the memory 875 * evenly so that everyone gets a fair share. 876 */ 877 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 878 u_int32_t chunk, val; 879 880 chunk = sc->sk_ramsize / 2; 881 val = sc->sk_rboff / sizeof(u_int64_t); 882 sc_if->sk_rx_ramstart = val; 883 val += (chunk / sizeof(u_int64_t)); 884 sc_if->sk_rx_ramend = val - 1; 885 sc_if->sk_tx_ramstart = val; 886 val += (chunk / sizeof(u_int64_t)); 887 sc_if->sk_tx_ramend = val - 1; 888 } else { 889 u_int32_t chunk, val; 890 891 chunk = sc->sk_ramsize / 4; 892 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 893 sizeof(u_int64_t); 894 sc_if->sk_rx_ramstart = val; 895 val += (chunk / sizeof(u_int64_t)); 896 sc_if->sk_rx_ramend = val - 1; 897 sc_if->sk_tx_ramstart = val; 898 val += (chunk / sizeof(u_int64_t)); 899 sc_if->sk_tx_ramend = val - 1; 900 } 901 902 /* Read and save PHY type and set PHY address */ 903 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 904 switch (sc_if->sk_phytype) { 905 case SK_PHYTYPE_XMAC: 906 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 907 break; 908 case SK_PHYTYPE_BCOM: 909 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 910 break; 911 default: 912 printf("%s: unsupported PHY type: %d\n", 913 sc->sk_dev.dv_xname, sc_if->sk_phytype); 914 return; 915 } 916 917 /* Allocate the descriptor queues. */ 918 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 919 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 920 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 921 goto fail; 922 } 923 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 924 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 925 printf("%s: can't map dma buffers (%d bytes)\n", 926 sc_if->sk_dev.dv_xname, sizeof(struct sk_ring_data)); 927 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 928 goto fail; 929 } 930 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 931 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, &dmamap)) { 932 printf("%s: can't create dma map\n", sc_if->sk_dev.dv_xname); 933 bus_dmamem_unmap(sc->sc_dmatag, kva, 934 sizeof(struct sk_ring_data)); 935 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 936 goto fail; 937 } 938 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, 939 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 940 printf("%s: can't load dma map\n", sc_if->sk_dev.dv_xname); 941 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 942 bus_dmamem_unmap(sc->sc_dmatag, kva, 943 sizeof(struct sk_ring_data)); 944 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 945 goto fail; 946 } 947 sc_if->sk_rdata = (struct sk_ring_data *)kva; 948 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 949 950 ifp = &sc_if->arpcom.ac_if; 951 ifp->if_softc = sc_if; 952 ifp->if_mtu = ETHERMTU; 953 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 954 ifp->if_ioctl = sk_ioctl; 955 ifp->if_output = ether_output; 956 ifp->if_start = sk_start; 957 ifp->if_watchdog = sk_watchdog; 958 ifp->if_baudrate = 1000000000; 959 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1; 960 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 961 962 /* 963 * Do miibus setup. 964 */ 965 sk_init_xmac(sc_if); 966 sc_if->sk_mii.mii_ifp = ifp; 967 sc_if->sk_mii.mii_readreg = sk_miibus_readreg; 968 sc_if->sk_mii.mii_writereg = sk_miibus_writereg; 969 sc_if->sk_mii.mii_statchg = sk_miibus_statchg; 970 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 971 sk_ifmedia_upd, sk_ifmedia_sts); 972 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 973 MII_OFFSET_ANY, 0); 974 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 975 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 976 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 977 0, NULL); 978 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 979 } 980 else 981 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 982 983 timeout_set(&sc_if->sk_tick_ch, sk_tick, sc_if); 984 timeout_add(&sc_if->sk_tick_ch, hz); 985 986 /* 987 * Call MI attach routines. 988 */ 989 if_attach(ifp); 990 ether_ifattach(ifp); 991 992 return; 993 994 fail: 995 sc->sk_if[sa->skc_port] = NULL; 996 } 997 998 int 999 skcprint(aux, pnp) 1000 void *aux; 1001 const char *pnp; 1002 { 1003 struct skc_attach_args *sa = aux; 1004 1005 if (pnp) 1006 printf("sk port %c at %s", 1007 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1008 else 1009 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1010 return (UNCONF); 1011 } 1012 1013 /* 1014 * Attach the interface. Allocate softc structures, do ifmedia 1015 * setup and ethernet/BPF attach. 1016 */ 1017 void 1018 skc_attach(parent, self, aux) 1019 struct device *parent, *self; 1020 void *aux; 1021 { 1022 struct sk_softc *sc = (struct sk_softc *)self; 1023 struct pci_attach_args *pa = aux; 1024 struct skc_attach_args skca; 1025 pci_chipset_tag_t pc = pa->pa_pc; 1026 pci_intr_handle_t ih; 1027 const char *intrstr = NULL; 1028 bus_addr_t iobase; 1029 bus_size_t iosize; 1030 int s; 1031 u_int32_t command; 1032 1033 s = splimp(); 1034 1035 /* 1036 * Handle power management nonsense. 1037 */ 1038 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1039 if (command == 0x01) { 1040 1041 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1042 if (command & SK_PSTATE_MASK) { 1043 u_int32_t iobase, membase, irq; 1044 1045 /* Save important PCI config data. */ 1046 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1047 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1048 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1049 1050 /* Reset the power state. */ 1051 printf("%s chip is in D%d power mode " 1052 "-- setting to D0\n", sc->sk_dev.dv_xname, 1053 command & SK_PSTATE_MASK); 1054 command &= 0xFFFFFFFC; 1055 pci_conf_write(pc, pa->pa_tag, 1056 SK_PCI_PWRMGMTCTRL, command); 1057 1058 /* Restore PCI config data. */ 1059 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1060 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1061 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1062 } 1063 } 1064 1065 /* 1066 * Map control/status registers. 1067 */ 1068 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1069 command |= PCI_COMMAND_IO_ENABLE | 1070 PCI_COMMAND_MEM_ENABLE | 1071 PCI_COMMAND_MASTER_ENABLE; 1072 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1073 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1074 1075 #ifdef SK_USEIOSPACE 1076 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1077 printf(": failed to enable I/O ports!\n"); 1078 goto fail; 1079 } 1080 /* 1081 * Map control/status registers. 1082 */ 1083 if (pci_io_find(pc, pa->pa_tag, SK_PCI_LOIO, &iobase, &iosize)) { 1084 printf(": can't find i/o space\n"); 1085 goto fail; 1086 } 1087 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->sk_bhandle)) { 1088 printf(": can't map i/o space\n"); 1089 goto fail; 1090 } 1091 sc->sk_btag = pa->pa_iot; 1092 #else 1093 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1094 printf(": failed to enable memory mapping!\n"); 1095 goto fail; 1096 } 1097 if (pci_mem_find(pc, pa->pa_tag, SK_PCI_LOMEM, &iobase, &iosize, NULL)){ 1098 printf(": can't find mem space\n"); 1099 goto fail; 1100 } 1101 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->sk_bhandle)) { 1102 printf(": can't map mem space\n"); 1103 goto fail; 1104 } 1105 sc->sk_btag = pa->pa_memt; 1106 #endif 1107 sc->sc_dmatag = pa->pa_dmat; 1108 1109 /* Allocate interrupt */ 1110 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 1111 pa->pa_intrline, &ih)) { 1112 printf(": couldn't map interrupt\n"); 1113 goto fail; 1114 } 1115 1116 intrstr = pci_intr_string(pc, ih); 1117 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc, 1118 self->dv_xname); 1119 if (sc->sk_intrhand == NULL) { 1120 printf(": couldn't establish interrupt"); 1121 if (intrstr != NULL) 1122 printf(" at %s", intrstr); 1123 goto fail; 1124 } 1125 printf(": %s\n", intrstr); 1126 1127 /* Reset the adapter. */ 1128 sk_reset(sc); 1129 1130 /* Read and save vital product data from EEPROM. */ 1131 sk_vpd_read(sc); 1132 1133 /* Read and save RAM size and RAMbuffer offset */ 1134 switch(sk_win_read_1(sc, SK_EPROM0)) { 1135 case SK_RAMSIZE_512K_64: 1136 sc->sk_ramsize = 0x80000; 1137 sc->sk_rboff = SK_RBOFF_0; 1138 break; 1139 case SK_RAMSIZE_1024K_64: 1140 sc->sk_ramsize = 0x100000; 1141 sc->sk_rboff = SK_RBOFF_80000; 1142 break; 1143 case SK_RAMSIZE_1024K_128: 1144 sc->sk_ramsize = 0x100000; 1145 sc->sk_rboff = SK_RBOFF_0; 1146 break; 1147 case SK_RAMSIZE_2048K_128: 1148 sc->sk_ramsize = 0x200000; 1149 sc->sk_rboff = SK_RBOFF_0; 1150 break; 1151 default: 1152 printf("%s: unknown ram size: %d\n", 1153 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_EPROM0)); 1154 goto fail; 1155 break; 1156 } 1157 1158 /* Read and save physical media type */ 1159 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1160 case SK_PMD_1000BASESX: 1161 sc->sk_pmd = IFM_1000_SX; 1162 break; 1163 case SK_PMD_1000BASELX: 1164 sc->sk_pmd = IFM_1000_LX; 1165 break; 1166 case SK_PMD_1000BASECX: 1167 sc->sk_pmd = IFM_1000_CX; 1168 break; 1169 case SK_PMD_1000BASETX: 1170 sc->sk_pmd = IFM_1000_TX; 1171 break; 1172 default: 1173 printf("%s: unknown media type: 0x%x\n", 1174 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1175 goto fail; 1176 } 1177 1178 /* Announce the product name. */ 1179 printf("%s: %s\n", sc->sk_dev.dv_xname, sc->sk_vpd_prodname); 1180 1181 skca.skc_port = SK_PORT_A; 1182 (void)config_found(&sc->sk_dev, &skca, skcprint); 1183 1184 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1185 skca.skc_port = SK_PORT_B; 1186 (void)config_found(&sc->sk_dev, &skca, skcprint); 1187 } 1188 1189 /* Turn on the 'driver is loaded' LED. */ 1190 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1191 1192 fail: 1193 splx(s); 1194 } 1195 1196 int sk_encap(sc_if, m_head, txidx) 1197 struct sk_if_softc *sc_if; 1198 struct mbuf *m_head; 1199 u_int32_t *txidx; 1200 { 1201 struct sk_tx_desc *f = NULL; 1202 struct mbuf *m; 1203 u_int32_t frag, cur, cnt = 0; 1204 1205 m = m_head; 1206 cur = frag = *txidx; 1207 1208 /* 1209 * Start packing the mbufs in this chain into 1210 * the fragment pointers. Stop when we run out 1211 * of fragments or hit the end of the mbuf chain. 1212 */ 1213 for (m = m_head; m != NULL; m = m->m_next) { 1214 if (m->m_len != 0) { 1215 if ((SK_TX_RING_CNT - 1216 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1217 return(ENOBUFS); 1218 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1219 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1220 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1221 if (cnt == 0) 1222 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1223 else 1224 f->sk_ctl |= SK_TXCTL_OWN; 1225 cur = frag; 1226 SK_INC(frag, SK_TX_RING_CNT); 1227 cnt++; 1228 } 1229 } 1230 1231 if (m != NULL) 1232 return(ENOBUFS); 1233 1234 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1235 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1236 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1237 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1238 sc_if->sk_cdata.sk_tx_cnt += cnt; 1239 1240 *txidx = frag; 1241 1242 return(0); 1243 } 1244 1245 void sk_start(ifp) 1246 struct ifnet *ifp; 1247 { 1248 struct sk_softc *sc; 1249 struct sk_if_softc *sc_if; 1250 struct mbuf *m_head = NULL; 1251 u_int32_t idx; 1252 1253 sc_if = ifp->if_softc; 1254 sc = sc_if->sk_softc; 1255 1256 idx = sc_if->sk_cdata.sk_tx_prod; 1257 1258 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1259 IF_DEQUEUE(&ifp->if_snd, m_head); 1260 if (m_head == NULL) 1261 break; 1262 1263 /* 1264 * Pack the data into the transmit ring. If we 1265 * don't have room, set the OACTIVE flag and wait 1266 * for the NIC to drain the ring. 1267 */ 1268 if (sk_encap(sc_if, m_head, &idx)) { 1269 IF_PREPEND(&ifp->if_snd, m_head); 1270 ifp->if_flags |= IFF_OACTIVE; 1271 break; 1272 } 1273 1274 /* 1275 * If there's a BPF listener, bounce a copy of this frame 1276 * to him. 1277 */ 1278 #if NBPFILTER > 0 1279 if (ifp->if_bpf) 1280 bpf_mtap(ifp->if_bpf, m_head); 1281 #endif 1282 } 1283 1284 /* Transmit */ 1285 sc_if->sk_cdata.sk_tx_prod = idx; 1286 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1287 1288 /* Set a timeout in case the chip goes out to lunch. */ 1289 ifp->if_timer = 5; 1290 1291 return; 1292 } 1293 1294 1295 void sk_watchdog(ifp) 1296 struct ifnet *ifp; 1297 { 1298 struct sk_if_softc *sc_if; 1299 1300 sc_if = ifp->if_softc; 1301 1302 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1303 sk_init(sc_if); 1304 1305 return; 1306 } 1307 1308 void sk_shutdown(v) 1309 void *v; 1310 { 1311 struct sk_softc *sc = v; 1312 1313 /* Turn off the 'driver is loaded' LED. */ 1314 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1315 1316 /* 1317 * Reset the GEnesis controller. Doing this should also 1318 * assert the resets on the attached XMAC(s). 1319 */ 1320 sk_reset(sc); 1321 1322 return; 1323 } 1324 1325 void sk_rxeof(sc_if) 1326 struct sk_if_softc *sc_if; 1327 { 1328 struct mbuf *m; 1329 struct ifnet *ifp; 1330 struct sk_chain *cur_rx; 1331 int total_len = 0; 1332 int i; 1333 u_int32_t rxstat; 1334 1335 ifp = &sc_if->arpcom.ac_if; 1336 i = sc_if->sk_cdata.sk_rx_prod; 1337 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1338 1339 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1340 1341 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1342 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1343 m = cur_rx->sk_mbuf; 1344 cur_rx->sk_mbuf = NULL; 1345 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1346 SK_INC(i, SK_RX_RING_CNT); 1347 1348 if (rxstat & XM_RXSTAT_ERRFRAME) { 1349 ifp->if_ierrors++; 1350 sk_newbuf(sc_if, cur_rx, m); 1351 continue; 1352 } 1353 1354 /* 1355 * Try to allocate a new jumbo buffer. If that 1356 * fails, copy the packet to mbufs and put the 1357 * jumbo buffer back in the ring so it can be 1358 * re-used. If allocating mbufs fails, then we 1359 * have to drop the packet. 1360 */ 1361 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1362 struct mbuf *m0; 1363 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1364 total_len + ETHER_ALIGN, 0, ifp, NULL); 1365 sk_newbuf(sc_if, cur_rx, m); 1366 if (m0 == NULL) { 1367 printf("%s: no receive buffers " 1368 "available -- packet dropped!\n", 1369 sc_if->sk_dev.dv_xname); 1370 ifp->if_ierrors++; 1371 continue; 1372 } 1373 m_adj(m0, ETHER_ALIGN); 1374 m = m0; 1375 } else { 1376 m->m_pkthdr.rcvif = ifp; 1377 m->m_pkthdr.len = m->m_len = total_len; 1378 } 1379 1380 ifp->if_ipackets++; 1381 1382 #if NBPFILTER > 0 1383 if (ifp->if_bpf) 1384 bpf_mtap(ifp->if_bpf, m); 1385 #endif 1386 /* pass it on. */ 1387 ether_input_mbuf(ifp, m); 1388 } 1389 1390 sc_if->sk_cdata.sk_rx_prod = i; 1391 1392 return; 1393 } 1394 1395 void sk_txeof(sc_if) 1396 struct sk_if_softc *sc_if; 1397 { 1398 struct sk_tx_desc *cur_tx = NULL; 1399 struct ifnet *ifp; 1400 u_int32_t idx; 1401 1402 ifp = &sc_if->arpcom.ac_if; 1403 1404 /* 1405 * Go through our tx ring and free mbufs for those 1406 * frames that have been sent. 1407 */ 1408 idx = sc_if->sk_cdata.sk_tx_cons; 1409 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1410 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1411 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1412 break; 1413 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1414 ifp->if_opackets++; 1415 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1416 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1417 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1418 } 1419 sc_if->sk_cdata.sk_tx_cnt--; 1420 SK_INC(idx, SK_TX_RING_CNT); 1421 ifp->if_timer = 0; 1422 } 1423 1424 sc_if->sk_cdata.sk_tx_cons = idx; 1425 1426 if (cur_tx != NULL) 1427 ifp->if_flags &= ~IFF_OACTIVE; 1428 1429 return; 1430 } 1431 1432 void 1433 sk_tick(xsc_if) 1434 void *xsc_if; 1435 { 1436 struct sk_if_softc *sc_if; 1437 struct mii_data *mii; 1438 struct ifnet *ifp; 1439 int i; 1440 1441 sc_if = xsc_if; 1442 ifp = &sc_if->arpcom.ac_if; 1443 mii = &sc_if->sk_mii; 1444 1445 if (!(ifp->if_flags & IFF_UP)) 1446 return; 1447 1448 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1449 sk_intr_bcom(sc_if); 1450 return; 1451 } 1452 1453 /* 1454 * According to SysKonnect, the correct way to verify that 1455 * the link has come back up is to poll bit 0 of the GPIO 1456 * register three times. This pin has the signal from the 1457 * link sync pin connected to it; if we read the same link 1458 * state 3 times in a row, we know the link is up. 1459 */ 1460 for (i = 0; i < 3; i++) { 1461 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1462 break; 1463 } 1464 1465 if (i != 3) { 1466 timeout_add(&sc_if->sk_tick_ch, hz); 1467 return; 1468 } 1469 1470 /* Turn the GP0 interrupt back on. */ 1471 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1472 SK_XM_READ_2(sc_if, XM_ISR); 1473 mii_tick(mii); 1474 mii_pollstat(mii); 1475 timeout_del(&sc_if->sk_tick_ch); 1476 } 1477 1478 void 1479 sk_intr_bcom(sc_if) 1480 struct sk_if_softc *sc_if; 1481 { 1482 struct sk_softc *sc; 1483 struct mii_data *mii; 1484 struct ifnet *ifp; 1485 int status; 1486 1487 sc = sc_if->sk_softc; 1488 mii = &sc_if->sk_mii; 1489 ifp = &sc_if->arpcom.ac_if; 1490 1491 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1492 1493 /* 1494 * Read the PHY interrupt register to make sure 1495 * we clear any pending interrupts. 1496 */ 1497 status = sk_miibus_readreg((struct device *)sc_if, 1498 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1499 1500 if (!(ifp->if_flags & IFF_RUNNING)) { 1501 sk_init_xmac(sc_if); 1502 return; 1503 } 1504 1505 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1506 int lstat; 1507 lstat = sk_miibus_readreg((struct device *)sc_if, 1508 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 1509 1510 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1511 mii_mediachg(mii); 1512 /* Turn off the link LED. */ 1513 SK_IF_WRITE_1(sc_if, 0, 1514 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1515 sc_if->sk_link = 0; 1516 } else if (status & BRGPHY_ISR_LNK_CHG) { 1517 sk_miibus_writereg((struct device *)sc_if, 1518 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 1519 mii_tick(mii); 1520 sc_if->sk_link = 1; 1521 /* Turn on the link LED. */ 1522 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1523 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1524 SK_LINKLED_BLINK_OFF); 1525 mii_pollstat(mii); 1526 } else { 1527 mii_tick(mii); 1528 timeout_add(&sc_if->sk_tick_ch, hz); 1529 } 1530 } 1531 1532 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1533 1534 return; 1535 } 1536 1537 void sk_intr_xmac(sc_if) 1538 struct sk_if_softc *sc_if; 1539 { 1540 struct sk_softc *sc; 1541 u_int16_t status; 1542 1543 sc = sc_if->sk_softc; 1544 status = SK_XM_READ_2(sc_if, XM_ISR); 1545 1546 if (status & XM_ISR_LINKEVENT) { 1547 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_LINKEVENT); 1548 if (sc_if->sk_link == 1) 1549 sc_if->sk_link = 0; 1550 } 1551 1552 if (status & XM_ISR_AUTONEG_DONE) 1553 timeout_add(&sc_if->sk_tick_ch, hz); 1554 1555 if (status & XM_IMR_TX_UNDERRUN) 1556 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1557 1558 if (status & XM_IMR_RX_OVERRUN) 1559 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1560 1561 return; 1562 } 1563 1564 int sk_intr(xsc) 1565 void *xsc; 1566 { 1567 struct sk_softc *sc = xsc; 1568 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 1569 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1570 u_int32_t status; 1571 int claimed = 0; 1572 1573 sc_if0 = sc->sk_if[SK_PORT_A]; 1574 sc_if1 = sc->sk_if[SK_PORT_B]; 1575 1576 if (sc_if0 != NULL) 1577 ifp0 = &sc_if0->arpcom.ac_if; 1578 if (sc_if1 != NULL) 1579 ifp1 = &sc_if1->arpcom.ac_if; 1580 1581 for (;;) { 1582 status = CSR_READ_4(sc, SK_ISSR); 1583 if (!(status & sc->sk_intrmask)) 1584 break; 1585 1586 claimed = 1; 1587 1588 /* Handle receive interrupts first. */ 1589 if (status & SK_ISR_RX1_EOF) { 1590 sk_rxeof(sc_if0); 1591 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1592 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1593 } 1594 if (status & SK_ISR_RX2_EOF) { 1595 sk_rxeof(sc_if1); 1596 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1597 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1598 } 1599 1600 /* Then transmit interrupts. */ 1601 if (status & SK_ISR_TX1_S_EOF) { 1602 sk_txeof(sc_if0); 1603 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1604 SK_TXBMU_CLR_IRQ_EOF); 1605 } 1606 if (status & SK_ISR_TX2_S_EOF) { 1607 sk_txeof(sc_if1); 1608 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1609 SK_TXBMU_CLR_IRQ_EOF); 1610 } 1611 1612 /* Then MAC interrupts. */ 1613 if (status & SK_ISR_MAC1 && 1614 ifp0->if_flags & IFF_RUNNING) 1615 sk_intr_xmac(sc_if0); 1616 1617 if (status & SK_ISR_MAC2 && 1618 ifp1->if_flags & IFF_RUNNING) 1619 sk_intr_xmac(sc_if1); 1620 1621 if (status & SK_ISR_EXTERNAL_REG) { 1622 if (ifp0 != NULL) 1623 sk_intr_bcom(sc_if0); 1624 if (ifp1 != NULL) 1625 sk_intr_bcom(sc_if1); 1626 } 1627 } 1628 1629 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1630 1631 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL) 1632 sk_start(ifp0); 1633 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL) 1634 sk_start(ifp1); 1635 1636 return (claimed); 1637 } 1638 1639 void sk_init_xmac(sc_if) 1640 struct sk_if_softc *sc_if; 1641 { 1642 struct sk_softc *sc; 1643 struct ifnet *ifp; 1644 struct sk_bcom_hack bhack[] = { 1645 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 1646 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 1647 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 1648 { 0, 0 } }; 1649 1650 sc = sc_if->sk_softc; 1651 ifp = &sc_if->arpcom.ac_if; 1652 1653 /* Unreset the XMAC. */ 1654 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 1655 DELAY(1000); 1656 1657 /* Reset the XMAC's internal state. */ 1658 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 1659 1660 /* Save the XMAC II revision */ 1661 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 1662 1663 /* 1664 * Perform additional initialization for external PHYs, 1665 * namely for the 1000baseTX cards that use the XMAC's 1666 * GMII mode. 1667 */ 1668 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1669 int i = 0; 1670 u_int32_t val; 1671 1672 /* Take PHY out of reset. */ 1673 val = sk_win_read_4(sc, SK_GPIO); 1674 if (sc_if->sk_port == SK_PORT_A) 1675 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 1676 else 1677 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 1678 sk_win_write_4(sc, SK_GPIO, val); 1679 1680 /* Enable GMII mode on the XMAC. */ 1681 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 1682 1683 sk_miibus_writereg((struct device *)sc_if, SK_PHYADDR_BCOM, 1684 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 1685 DELAY(10000); 1686 sk_miibus_writereg((struct device *)sc_if, SK_PHYADDR_BCOM, 1687 BRGPHY_MII_IMR, 0xFFF0); 1688 1689 /* 1690 * Early versions of the BCM5400 apparently have 1691 * a bug that requires them to have their reserved 1692 * registers initialized to some magic values. I don't 1693 * know what the numbers do, I'm just the messenger. 1694 */ 1695 if (sk_miibus_readreg((struct device *)sc_if, 1696 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 1697 while(bhack[i].reg) { 1698 sk_miibus_writereg((struct device *)sc_if, 1699 SK_PHYADDR_BCOM, bhack[i].reg, 1700 bhack[i].val); 1701 i++; 1702 } 1703 } 1704 } 1705 1706 /* Set station address */ 1707 SK_XM_WRITE_2(sc_if, XM_PAR0, 1708 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 1709 SK_XM_WRITE_2(sc_if, XM_PAR1, 1710 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 1711 SK_XM_WRITE_2(sc_if, XM_PAR2, 1712 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 1713 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 1714 1715 if (ifp->if_flags & IFF_PROMISC) { 1716 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1717 } else { 1718 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1719 } 1720 1721 if (ifp->if_flags & IFF_BROADCAST) { 1722 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 1723 } else { 1724 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 1725 } 1726 1727 /* We don't need the FCS appended to the packet. */ 1728 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 1729 1730 /* We want short frames padded to 60 bytes. */ 1731 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 1732 1733 /* 1734 * Enable the reception of all error frames. This is is 1735 * a necessary evil due to the design of the XMAC. The 1736 * XMAC's receive FIFO is only 8K in size, however jumbo 1737 * frames can be up to 9000 bytes in length. When bad 1738 * frame filtering is enabled, the XMAC's RX FIFO operates 1739 * in 'store and forward' mode. For this to work, the 1740 * entire frame has to fit into the FIFO, but that means 1741 * that jumbo frames larger than 8192 bytes will be 1742 * truncated. Disabling all bad frame filtering causes 1743 * the RX FIFO to operate in streaming mode, in which 1744 * case the XMAC will start transfering frames out of the 1745 * RX FIFO as soon as the FIFO threshold is reached. 1746 */ 1747 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 1748 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 1749 XM_MODE_RX_INRANGELEN); 1750 1751 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1752 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 1753 else 1754 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 1755 1756 /* 1757 * Bump up the transmit threshold. This helps hold off transmit 1758 * underruns when we're blasting traffic from both ports at once. 1759 */ 1760 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 1761 1762 /* Set multicast filter */ 1763 sk_setmulti(sc_if); 1764 1765 /* Clear and enable interrupts */ 1766 SK_XM_READ_2(sc_if, XM_ISR); 1767 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 1768 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 1769 else 1770 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 1771 1772 /* Configure MAC arbiter */ 1773 switch(sc_if->sk_xmac_rev) { 1774 case XM_XMAC_REV_B2: 1775 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 1776 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 1777 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 1778 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 1779 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 1780 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 1781 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 1782 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 1783 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 1784 break; 1785 case XM_XMAC_REV_C1: 1786 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 1787 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 1788 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 1789 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 1790 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 1791 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 1792 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 1793 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 1794 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 1795 break; 1796 default: 1797 break; 1798 } 1799 sk_win_write_2(sc, SK_MACARB_CTL, 1800 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 1801 1802 sc_if->sk_link = 1; 1803 1804 return; 1805 } 1806 1807 /* 1808 * Note that to properly initialize any part of the GEnesis chip, 1809 * you first have to take it out of reset mode. 1810 */ 1811 void sk_init(xsc) 1812 void *xsc; 1813 { 1814 struct sk_if_softc *sc_if = xsc; 1815 struct sk_softc *sc; 1816 struct ifnet *ifp; 1817 struct mii_data *mii; 1818 int s; 1819 1820 s = splimp(); 1821 1822 ifp = &sc_if->arpcom.ac_if; 1823 sc = sc_if->sk_softc; 1824 mii = &sc_if->sk_mii; 1825 1826 /* Cancel pending I/O and free all RX/TX buffers. */ 1827 sk_stop(sc_if); 1828 1829 /* Configure LINK_SYNC LED */ 1830 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 1831 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_ON); 1832 1833 /* Configure RX LED */ 1834 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_START); 1835 1836 /* Configure TX LED */ 1837 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_START); 1838 1839 /* Configure I2C registers */ 1840 1841 /* Configure XMAC(s) */ 1842 sk_init_xmac(sc_if); 1843 mii_mediachg(mii); 1844 1845 /* Configure MAC FIFOs */ 1846 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 1847 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 1848 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 1849 1850 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 1851 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 1852 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 1853 1854 /* Configure transmit arbiter(s) */ 1855 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 1856 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 1857 1858 /* Configure RAMbuffers */ 1859 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 1860 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 1861 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 1862 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 1863 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 1864 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 1865 1866 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 1867 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 1868 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 1869 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 1870 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 1871 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 1872 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 1873 1874 /* Configure BMUs */ 1875 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 1876 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 1877 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 1878 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 1879 1880 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 1881 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 1882 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 1883 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 1884 1885 /* Init descriptors */ 1886 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 1887 printf("%s: initialization failed: no " 1888 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 1889 sk_stop(sc_if); 1890 (void)splx(s); 1891 return; 1892 } 1893 sk_init_tx_ring(sc_if); 1894 1895 /* Configure interrupt handling */ 1896 CSR_READ_4(sc, SK_ISSR); 1897 if (sc_if->sk_port == SK_PORT_A) 1898 sc->sk_intrmask |= SK_INTRS1; 1899 else 1900 sc->sk_intrmask |= SK_INTRS2; 1901 1902 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 1903 1904 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1905 1906 /* Start BMUs. */ 1907 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 1908 1909 /* Enable XMACs TX and RX state machines */ 1910 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 1911 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1912 1913 ifp->if_flags |= IFF_RUNNING; 1914 ifp->if_flags &= ~IFF_OACTIVE; 1915 1916 splx(s); 1917 1918 return; 1919 } 1920 1921 void sk_stop(sc_if) 1922 struct sk_if_softc *sc_if; 1923 { 1924 int i; 1925 struct sk_softc *sc; 1926 struct ifnet *ifp; 1927 1928 sc = sc_if->sk_softc; 1929 ifp = &sc_if->arpcom.ac_if; 1930 1931 timeout_del(&sc_if->sk_tick_ch); 1932 1933 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1934 u_int32_t val; 1935 1936 /* Put PHY back into reset. */ 1937 val = sk_win_read_4(sc, SK_GPIO); 1938 if (sc_if->sk_port == SK_PORT_A) { 1939 val |= SK_GPIO_DIR0; 1940 val &= ~SK_GPIO_DAT0; 1941 } else { 1942 val |= SK_GPIO_DIR2; 1943 val &= ~SK_GPIO_DAT2; 1944 } 1945 sk_win_write_4(sc, SK_GPIO, val); 1946 } 1947 1948 /* Turn off various components of this interface. */ 1949 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 1950 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 1951 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 1952 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 1953 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 1954 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 1955 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 1956 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 1957 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 1958 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 1959 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 1960 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 1961 1962 /* Disable interrupts */ 1963 if (sc_if->sk_port == SK_PORT_A) 1964 sc->sk_intrmask &= ~SK_INTRS1; 1965 else 1966 sc->sk_intrmask &= ~SK_INTRS2; 1967 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1968 1969 SK_XM_READ_2(sc_if, XM_ISR); 1970 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 1971 1972 /* Free RX and TX mbufs still in the queues. */ 1973 for (i = 0; i < SK_RX_RING_CNT; i++) { 1974 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 1975 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 1976 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1977 } 1978 } 1979 1980 for (i = 0; i < SK_TX_RING_CNT; i++) { 1981 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 1982 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 1983 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1984 } 1985 } 1986 1987 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1988 1989 return; 1990 } 1991 1992 struct cfattach skc_ca = { 1993 sizeof(struct sk_softc), skc_probe, skc_attach, 1994 }; 1995 1996 struct cfdriver skc_cd = { 1997 0, "skc", DV_DULL 1998 }; 1999 2000 struct cfattach sk_ca = { 2001 sizeof(struct sk_if_softc), sk_probe, sk_attach, 2002 }; 2003 2004 struct cfdriver sk_cd = { 2005 0, "sk", DV_IFNET 2006 }; 2007