1 /* $OpenBSD: if_sk.c,v 1.34 2003/10/13 21:22:19 jason Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include "bpfilter.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/device.h> 99 #include <sys/queue.h> 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_types.h> 104 105 #ifdef INET 106 #include <netinet/in.h> 107 #include <netinet/in_systm.h> 108 #include <netinet/in_var.h> 109 #include <netinet/ip.h> 110 #include <netinet/udp.h> 111 #include <netinet/tcp.h> 112 #include <netinet/if_ether.h> 113 #endif 114 115 #include <net/if_media.h> 116 #include <net/if_vlan_var.h> 117 118 #if NBPFILTER > 0 119 #include <net/bpf.h> 120 #endif 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/brgphyreg.h> 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 #include <dev/pci/pcidevs.h> 129 130 #define SK_VERBOSE 131 /* #define SK_USEIOSPACE */ 132 133 #include <dev/pci/if_skreg.h> 134 #include <dev/pci/xmaciireg.h> 135 #include <dev/pci/yukonreg.h> 136 137 int skc_probe(struct device *, void *, void *); 138 void skc_attach(struct device *, struct device *self, void *aux); 139 int sk_probe(struct device *, void *, void *); 140 void sk_attach(struct device *, struct device *self, void *aux); 141 int skcprint(void *, const char *); 142 int sk_intr(void *); 143 void sk_intr_bcom(struct sk_if_softc *); 144 void sk_intr_xmac(struct sk_if_softc *); 145 void sk_intr_yukon(struct sk_if_softc *); 146 void sk_rxeof(struct sk_if_softc *); 147 void sk_txeof(struct sk_if_softc *); 148 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 149 void sk_start(struct ifnet *); 150 int sk_ioctl(struct ifnet *, u_long, caddr_t); 151 void sk_init(void *); 152 void sk_init_xmac(struct sk_if_softc *); 153 void sk_init_yukon(struct sk_if_softc *); 154 void sk_stop(struct sk_if_softc *); 155 void sk_watchdog(struct ifnet *); 156 void sk_shutdown(void *); 157 int sk_ifmedia_upd(struct ifnet *); 158 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 159 void sk_reset(struct sk_softc *); 160 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 161 int sk_init_rx_ring(struct sk_if_softc *); 162 int sk_init_tx_ring(struct sk_if_softc *); 163 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 164 void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int); 165 void sk_vpd_read(struct sk_softc *); 166 167 int sk_xmac_miibus_readreg(struct device *, int, int); 168 void sk_xmac_miibus_writereg(struct device *, int, int, int); 169 void sk_xmac_miibus_statchg(struct device *); 170 171 int sk_marv_miibus_readreg(struct device *, int, int); 172 void sk_marv_miibus_writereg(struct device *, int, int, int); 173 void sk_marv_miibus_statchg(struct device *); 174 175 u_int32_t sk_calchash(caddr_t); 176 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 177 void sk_setmulti(struct sk_if_softc *); 178 void sk_tick(void *); 179 void sk_rxcsum(struct ifnet *, struct mbuf *, const u_int16_t, const u_int16_t); 180 181 #ifdef SK_DEBUG 182 #define DPRINTF(x) if (skdebug) printf x 183 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 184 int skdebug = 0; 185 186 void sk_dump_txdesc(struct sk_tx_desc *, int); 187 void sk_dump_mbuf(struct mbuf *); 188 void sk_dump_bytes(const char *, int); 189 #else 190 #define DPRINTF(x) 191 #define DPRINTFN(n,x) 192 #endif 193 194 #define SK_SETBIT(sc, reg, x) \ 195 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 196 197 #define SK_CLRBIT(sc, reg, x) \ 198 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 199 200 #define SK_WIN_SETBIT_4(sc, reg, x) \ 201 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 202 203 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 204 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 205 206 #define SK_WIN_SETBIT_2(sc, reg, x) \ 207 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 208 209 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 210 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 211 212 /* supported device vendors */ 213 const struct pci_matchid skc_devices[] = { 214 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940}, 215 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_GE}, 216 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2}, 217 }; 218 219 static inline u_int32_t 220 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 221 { 222 #ifdef SK_USEIOSPACE 223 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 224 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 225 #else 226 return CSR_READ_4(sc, reg); 227 #endif 228 } 229 230 static inline u_int16_t 231 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 232 { 233 #ifdef SK_USEIOSPACE 234 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 235 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 236 #else 237 return CSR_READ_2(sc, reg); 238 #endif 239 } 240 241 static inline u_int8_t 242 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 243 { 244 #ifdef SK_USEIOSPACE 245 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 246 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 247 #else 248 return CSR_READ_1(sc, reg); 249 #endif 250 } 251 252 static inline void 253 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 254 { 255 #ifdef SK_USEIOSPACE 256 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 257 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 258 #else 259 CSR_WRITE_4(sc, reg, x); 260 #endif 261 } 262 263 static inline void 264 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 265 { 266 #ifdef SK_USEIOSPACE 267 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 268 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 269 #else 270 CSR_WRITE_2(sc, reg, x); 271 #endif 272 } 273 274 static inline void 275 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 276 { 277 #ifdef SK_USEIOSPACE 278 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 279 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 280 #else 281 CSR_WRITE_1(sc, reg, x); 282 #endif 283 } 284 285 /* 286 * The VPD EEPROM contains Vital Product Data, as suggested in 287 * the PCI 2.1 specification. The VPD data is separared into areas 288 * denoted by resource IDs. The SysKonnect VPD contains an ID string 289 * resource (the name of the adapter), a read-only area resource 290 * containing various key/data fields and a read/write area which 291 * can be used to store asset management information or log messages. 292 * We read the ID string and read-only into buffers attached to 293 * the controller softc structure for later use. At the moment, 294 * we only use the ID string during sk_attach(). 295 */ 296 u_int8_t 297 sk_vpd_readbyte(struct sk_softc *sc, int addr) 298 { 299 int i; 300 301 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 302 for (i = 0; i < SK_TIMEOUT; i++) { 303 DELAY(1); 304 if (sk_win_read_2(sc, 305 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 306 break; 307 } 308 309 if (i == SK_TIMEOUT) 310 return(0); 311 312 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 313 } 314 315 void 316 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 317 { 318 int i; 319 u_int8_t *ptr; 320 321 ptr = (u_int8_t *)res; 322 for (i = 0; i < sizeof(struct vpd_res); i++) 323 ptr[i] = sk_vpd_readbyte(sc, i + addr); 324 } 325 326 void 327 sk_vpd_read(struct sk_softc *sc) 328 { 329 int pos = 0, i; 330 struct vpd_res res; 331 332 if (sc->sk_vpd_prodname != NULL) 333 free(sc->sk_vpd_prodname, M_DEVBUF); 334 if (sc->sk_vpd_readonly != NULL) 335 free(sc->sk_vpd_readonly, M_DEVBUF); 336 sc->sk_vpd_prodname = NULL; 337 sc->sk_vpd_readonly = NULL; 338 339 sk_vpd_read_res(sc, &res, pos); 340 341 if (res.vr_id != VPD_RES_ID) { 342 printf("%s: bad VPD resource id: expected %x got %x\n", 343 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 344 return; 345 } 346 347 pos += sizeof(res); 348 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 349 if (sc->sk_vpd_prodname == NULL) 350 panic("sk_vpd_read"); 351 for (i = 0; i < res.vr_len; i++) 352 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 353 sc->sk_vpd_prodname[i] = '\0'; 354 pos += i; 355 356 sk_vpd_read_res(sc, &res, pos); 357 358 if (res.vr_id != VPD_RES_READ) { 359 printf("%s: bad VPD resource id: expected %x got %x\n", 360 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 361 return; 362 } 363 364 pos += sizeof(res); 365 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 366 if (sc->sk_vpd_readonly == NULL) 367 panic("sk_vpd_read"); 368 for (i = 0; i < res.vr_len + 1; i++) 369 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 370 } 371 372 int 373 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 374 { 375 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 376 int i; 377 378 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 379 380 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 381 return(0); 382 383 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 384 SK_XM_READ_2(sc_if, XM_PHY_DATA); 385 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 386 for (i = 0; i < SK_TIMEOUT; i++) { 387 DELAY(1); 388 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 389 XM_MMUCMD_PHYDATARDY) 390 break; 391 } 392 393 if (i == SK_TIMEOUT) { 394 printf("%s: phy failed to come ready\n", 395 sc_if->sk_dev.dv_xname); 396 return(0); 397 } 398 } 399 DELAY(1); 400 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 401 } 402 403 void 404 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 405 { 406 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 407 int i; 408 409 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 410 411 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 412 for (i = 0; i < SK_TIMEOUT; i++) { 413 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 414 break; 415 } 416 417 if (i == SK_TIMEOUT) { 418 printf("%s: phy failed to come ready\n", 419 sc_if->sk_dev.dv_xname); 420 return; 421 } 422 423 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 424 for (i = 0; i < SK_TIMEOUT; i++) { 425 DELAY(1); 426 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 427 break; 428 } 429 430 if (i == SK_TIMEOUT) 431 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 432 } 433 434 void 435 sk_xmac_miibus_statchg(struct device *dev) 436 { 437 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 438 struct mii_data *mii = &sc_if->sk_mii; 439 440 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 441 442 /* 443 * If this is a GMII PHY, manually set the XMAC's 444 * duplex mode accordingly. 445 */ 446 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 447 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 448 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 449 } else { 450 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 451 } 452 } 453 } 454 455 int 456 sk_marv_miibus_readreg(dev, phy, reg) 457 struct device *dev; 458 int phy, reg; 459 { 460 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 461 u_int16_t val; 462 int i; 463 464 if (phy != 0 || 465 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 466 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 467 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 468 phy, reg)); 469 return(0); 470 } 471 472 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 473 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 474 475 for (i = 0; i < SK_TIMEOUT; i++) { 476 DELAY(1); 477 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 478 if (val & YU_SMICR_READ_VALID) 479 break; 480 } 481 482 if (i == SK_TIMEOUT) { 483 printf("%s: phy failed to come ready\n", 484 sc_if->sk_dev.dv_xname); 485 return 0; 486 } 487 488 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 489 SK_TIMEOUT)); 490 491 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 492 493 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 494 phy, reg, val)); 495 496 return val; 497 } 498 499 void 500 sk_marv_miibus_writereg(dev, phy, reg, val) 501 struct device *dev; 502 int phy, reg, val; 503 { 504 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 505 int i; 506 507 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 508 phy, reg, val)); 509 510 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 511 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 512 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 513 514 for (i = 0; i < SK_TIMEOUT; i++) { 515 DELAY(1); 516 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 517 break; 518 } 519 } 520 521 void 522 sk_marv_miibus_statchg(dev) 523 struct device *dev; 524 { 525 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 526 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 527 } 528 529 #define SK_BITS 6 530 #define SK_POLY 0xEDB88320 531 532 u_int32_t 533 sk_calchash(caddr_t addr) 534 { 535 u_int32_t idx, bit, data, crc; 536 537 /* Compute CRC for the address value. */ 538 crc = 0xFFFFFFFF; /* initial value */ 539 540 for (idx = 0; idx < 6; idx++) { 541 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 542 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0); 543 } 544 545 return (~crc & ((1 << SK_BITS) - 1)); 546 } 547 548 void 549 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 550 { 551 int base = XM_RXFILT_ENTRY(slot); 552 553 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 554 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 555 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 556 } 557 558 void 559 sk_setmulti(struct sk_if_softc *sc_if) 560 { 561 struct sk_softc *sc = sc_if->sk_softc; 562 struct ifnet *ifp= &sc_if->arpcom.ac_if; 563 u_int32_t hashes[2] = { 0, 0 }; 564 int h, i; 565 struct arpcom *ac = &sc_if->arpcom; 566 struct ether_multi *enm; 567 struct ether_multistep step; 568 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 569 570 /* First, zot all the existing filters. */ 571 switch(sc->sk_type) { 572 case SK_GENESIS: 573 for (i = 1; i < XM_RXFILT_MAX; i++) 574 sk_setfilt(sc_if, (caddr_t)&dummy, i); 575 576 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 577 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 578 break; 579 case SK_YUKON: 580 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 581 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 582 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 583 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 584 break; 585 } 586 587 /* Now program new ones. */ 588 allmulti: 589 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 590 hashes[0] = 0xFFFFFFFF; 591 hashes[1] = 0xFFFFFFFF; 592 } else { 593 i = 1; 594 /* First find the tail of the list. */ 595 ETHER_FIRST_MULTI(step, ac, enm); 596 while (enm != NULL) { 597 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 598 ETHER_ADDR_LEN)) { 599 ifp->if_flags |= IFF_ALLMULTI; 600 goto allmulti; 601 } 602 /* 603 * Program the first XM_RXFILT_MAX multicast groups 604 * into the perfect filter. For all others, 605 * use the hash table. 606 */ 607 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 608 sk_setfilt(sc_if, enm->enm_addrlo, i); 609 i++; 610 } 611 else { 612 h = sk_calchash(enm->enm_addrlo); 613 if (h < 32) 614 hashes[0] |= (1 << h); 615 else 616 hashes[1] |= (1 << (h - 32)); 617 } 618 619 ETHER_NEXT_MULTI(step, enm); 620 } 621 } 622 623 switch(sc->sk_type) { 624 case SK_GENESIS: 625 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 626 XM_MODE_RX_USE_PERFECT); 627 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 628 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 629 break; 630 case SK_YUKON: 631 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 632 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 633 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 634 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 635 break; 636 } 637 } 638 639 int 640 sk_init_rx_ring(struct sk_if_softc *sc_if) 641 { 642 struct sk_chain_data *cd = &sc_if->sk_cdata; 643 struct sk_ring_data *rd = sc_if->sk_rdata; 644 int i; 645 646 bzero((char *)rd->sk_rx_ring, 647 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 648 649 for (i = 0; i < SK_RX_RING_CNT; i++) { 650 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 651 if (i == (SK_RX_RING_CNT - 1)) { 652 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 653 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 654 } else { 655 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 656 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 657 } 658 rd->sk_rx_ring[i].sk_csum1_start = ETHER_HDR_LEN; 659 rd->sk_rx_ring[i].sk_csum2_start = ETHER_HDR_LEN + 660 sizeof(struct ip); 661 } 662 663 for (i = 0; i < SK_RX_RING_CNT; i++) { 664 if (sk_newbuf(sc_if, i, NULL, NULL) == ENOBUFS) { 665 printf("%s: failed alloc of %dth mbuf\n", 666 sc_if->sk_dev.dv_xname, i); 667 return(ENOBUFS); 668 } 669 } 670 sc_if->sk_cdata.sk_rx_prod = 0; 671 sc_if->sk_cdata.sk_rx_cons = 0; 672 673 return(0); 674 } 675 676 int 677 sk_init_tx_ring(struct sk_if_softc *sc_if) 678 { 679 struct sk_softc *sc = sc_if->sk_softc; 680 struct sk_chain_data *cd = &sc_if->sk_cdata; 681 struct sk_ring_data *rd = sc_if->sk_rdata; 682 bus_dmamap_t dmamap; 683 struct sk_txmap_entry *entry; 684 int i; 685 686 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 687 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 688 689 SLIST_INIT(&sc_if->sk_txmap_listhead); 690 for (i = 0; i < SK_TX_RING_CNT; i++) { 691 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 692 if (i == (SK_TX_RING_CNT - 1)) { 693 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 694 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 695 } else { 696 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 697 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 698 } 699 700 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, SK_NTXSEG, 701 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap)) 702 return (ENOBUFS); 703 704 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 705 if (!entry) { 706 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 707 return (ENOBUFS); 708 } 709 entry->dmamap = dmamap; 710 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, link); 711 } 712 713 sc_if->sk_cdata.sk_tx_prod = 0; 714 sc_if->sk_cdata.sk_tx_cons = 0; 715 sc_if->sk_cdata.sk_tx_cnt = 0; 716 717 return (0); 718 } 719 720 int 721 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 722 bus_dmamap_t dmamap) 723 { 724 struct sk_softc *sc = sc_if->sk_softc; 725 struct mbuf *m_new = NULL; 726 struct sk_chain *c; 727 struct sk_rx_desc *r; 728 729 if (dmamap == NULL) { 730 /* if (m) panic() */ 731 732 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 733 0, BUS_DMA_NOWAIT, &dmamap)) { 734 printf("%s: can't create recv map\n", 735 sc_if->sk_dev.dv_xname); 736 return(ENOMEM); 737 } 738 } else if (m == NULL) 739 bus_dmamap_unload(sc->sc_dmatag, dmamap); 740 741 sc_if->sk_cdata.sk_rx_map[i] = dmamap; 742 743 if (m == NULL) { 744 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 745 if (m_new == NULL) { 746 printf("%s: no memory for rx list -- " 747 "packet dropped!\n", sc_if->sk_dev.dv_xname); 748 return(ENOBUFS); 749 } 750 751 /* Allocate the jumbo buffer */ 752 MCLGET(m_new, M_DONTWAIT); 753 if (!(m_new->m_flags & M_EXT)) { 754 m_freem(m_new); 755 return (ENOBUFS); 756 } 757 758 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 759 760 m_adj(m_new, ETHER_ALIGN); 761 762 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 763 BUS_DMA_NOWAIT)) 764 return(ENOBUFS); 765 } else { 766 /* 767 * We're re-using a previously allocated mbuf; 768 * be sure to re-init pointers and lengths to 769 * default values. 770 */ 771 m_new = m; 772 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 773 m_adj(m_new, ETHER_ALIGN); 774 m_new->m_data = m_new->m_ext.ext_buf; 775 } 776 777 c = &sc_if->sk_cdata.sk_rx_chain[i]; 778 r = c->sk_desc; 779 c->sk_mbuf = m_new; 780 r->sk_data_lo = dmamap->dm_segs[0].ds_addr; 781 r->sk_ctl = dmamap->dm_segs[0].ds_len | SK_RXSTAT; 782 783 return(0); 784 } 785 786 /* 787 * Set media options. 788 */ 789 int 790 sk_ifmedia_upd(struct ifnet *ifp) 791 { 792 struct sk_if_softc *sc_if = ifp->if_softc; 793 794 sk_init(sc_if); 795 mii_mediachg(&sc_if->sk_mii); 796 return(0); 797 } 798 799 /* 800 * Report current media status. 801 */ 802 void 803 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 804 { 805 struct sk_if_softc *sc_if = ifp->if_softc; 806 807 mii_pollstat(&sc_if->sk_mii); 808 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 809 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 810 } 811 812 int 813 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 814 { 815 struct sk_if_softc *sc_if = ifp->if_softc; 816 struct sk_softc *sc = sc_if->sk_softc; 817 struct ifreq *ifr = (struct ifreq *) data; 818 struct ifaddr *ifa = (struct ifaddr *) data; 819 struct mii_data *mii; 820 int s, error = 0; 821 822 s = splimp(); 823 824 if ((error = ether_ioctl(ifp, &sc_if->arpcom, command, data)) > 0) { 825 splx(s); 826 return error; 827 } 828 829 switch(command) { 830 case SIOCSIFADDR: 831 ifp->if_flags |= IFF_UP; 832 switch (ifa->ifa_addr->sa_family) { 833 #ifdef INET 834 case AF_INET: 835 sk_init(sc_if); 836 arp_ifinit(&sc_if->arpcom, ifa); 837 break; 838 #endif /* INET */ 839 default: 840 sk_init(sc_if); 841 break; 842 } 843 break; 844 case SIOCSIFMTU: 845 if (ifr->ifr_mtu > SK_JUMBO_MTU) 846 error = EINVAL; 847 else 848 ifp->if_mtu = ifr->ifr_mtu; 849 sk_init(sc_if); 850 break; 851 case SIOCSIFFLAGS: 852 if (ifp->if_flags & IFF_UP) { 853 if (ifp->if_flags & IFF_RUNNING && 854 ifp->if_flags & IFF_PROMISC && 855 !(sc_if->sk_if_flags & IFF_PROMISC)) { 856 switch(sc->sk_type) { 857 case SK_GENESIS: 858 SK_XM_SETBIT_4(sc_if, XM_MODE, 859 XM_MODE_RX_PROMISC); 860 break; 861 case SK_YUKON: 862 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 863 YU_RCR_UFLEN | YU_RCR_MUFLEN); 864 break; 865 } 866 sk_setmulti(sc_if); 867 } else if (ifp->if_flags & IFF_RUNNING && 868 !(ifp->if_flags & IFF_PROMISC) && 869 sc_if->sk_if_flags & IFF_PROMISC) { 870 switch(sc->sk_type) { 871 case SK_GENESIS: 872 SK_XM_CLRBIT_4(sc_if, XM_MODE, 873 XM_MODE_RX_PROMISC); 874 break; 875 case SK_YUKON: 876 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 877 YU_RCR_UFLEN | YU_RCR_MUFLEN); 878 break; 879 } 880 881 sk_setmulti(sc_if); 882 } else 883 sk_init(sc_if); 884 } else { 885 if (ifp->if_flags & IFF_RUNNING) 886 sk_stop(sc_if); 887 } 888 sc_if->sk_if_flags = ifp->if_flags; 889 error = 0; 890 break; 891 case SIOCADDMULTI: 892 case SIOCDELMULTI: 893 error = (command == SIOCADDMULTI) ? 894 ether_addmulti(ifr, &sc_if->arpcom) : 895 ether_delmulti(ifr, &sc_if->arpcom); 896 897 if (error == ENETRESET) { 898 /* 899 * Multicast list has changed; set the hardware 900 * filter accordingly. 901 */ 902 sk_setmulti(sc_if); 903 error = 0; 904 } 905 break; 906 case SIOCGIFMEDIA: 907 case SIOCSIFMEDIA: 908 mii = &sc_if->sk_mii; 909 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 910 break; 911 default: 912 error = EINVAL; 913 break; 914 } 915 916 splx(s); 917 918 return(error); 919 } 920 921 /* 922 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 923 * IDs against our list and return a device name if we find a match. 924 */ 925 int 926 skc_probe(struct device *parent, void *match, void *aux) 927 { 928 return (pci_matchbyid((struct pci_attach_args *)aux, skc_devices, 929 sizeof(skc_devices)/sizeof(skc_devices[0]))); 930 } 931 932 /* 933 * Force the GEnesis into reset, then bring it out of reset. 934 */ 935 void sk_reset(struct sk_softc *sc) 936 { 937 DPRINTFN(2, ("sk_reset\n")); 938 939 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 940 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 941 if (sc->sk_type == SK_YUKON) 942 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 943 944 DELAY(1000); 945 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 946 DELAY(2); 947 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 948 if (sc->sk_type == SK_YUKON) 949 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 950 951 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 952 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 953 CSR_READ_2(sc, SK_LINK_CTRL))); 954 955 if (sc->sk_type == SK_GENESIS) { 956 /* Configure packet arbiter */ 957 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 958 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 959 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 960 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 961 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 962 } 963 964 /* Enable RAM interface */ 965 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 966 967 /* 968 * Configure interrupt moderation. The moderation timer 969 * defers interrupts specified in the interrupt moderation 970 * timer mask based on the timeout specified in the interrupt 971 * moderation timer init register. Each bit in the timer 972 * register represents 18.825ns, so to specify a timeout in 973 * microseconds, we have to multiply by 54. 974 */ 975 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 976 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 977 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 978 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 979 } 980 981 int 982 sk_probe(struct device *parent, void *match, void *aux) 983 { 984 struct skc_attach_args *sa = aux; 985 986 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 987 return(0); 988 989 return (1); 990 } 991 992 /* 993 * Each XMAC chip is attached as a separate logical IP interface. 994 * Single port cards will have only one logical interface of course. 995 */ 996 void 997 sk_attach(struct device *parent, struct device *self, void *aux) 998 { 999 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1000 struct sk_softc *sc = (struct sk_softc *)parent; 1001 struct skc_attach_args *sa = aux; 1002 struct ifnet *ifp; 1003 caddr_t kva; 1004 bus_dma_segment_t seg; 1005 int i, rseg; 1006 1007 sc_if->sk_port = sa->skc_port; 1008 sc_if->sk_softc = sc; 1009 sc->sk_if[sa->skc_port] = sc_if; 1010 1011 if (sa->skc_port == SK_PORT_A) 1012 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1013 if (sa->skc_port == SK_PORT_B) 1014 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1015 1016 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1017 1018 /* 1019 * Get station address for this interface. Note that 1020 * dual port cards actually come with three station 1021 * addresses: one for each port, plus an extra. The 1022 * extra one is used by the SysKonnect driver software 1023 * as a 'virtual' station address for when both ports 1024 * are operating in failover mode. Currently we don't 1025 * use this extra address. 1026 */ 1027 for (i = 0; i < ETHER_ADDR_LEN; i++) 1028 sc_if->arpcom.ac_enaddr[i] = 1029 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1030 1031 1032 printf(": address %s\n", 1033 ether_sprintf(sc_if->arpcom.ac_enaddr)); 1034 1035 /* 1036 * Set up RAM buffer addresses. The NIC will have a certain 1037 * amount of SRAM on it, somewhere between 512K and 2MB. We 1038 * need to divide this up a) between the transmitter and 1039 * receiver and b) between the two XMACs, if this is a 1040 * dual port NIC. Our algotithm is to divide up the memory 1041 * evenly so that everyone gets a fair share. 1042 */ 1043 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1044 u_int32_t chunk, val; 1045 1046 chunk = sc->sk_ramsize / 2; 1047 val = sc->sk_rboff / sizeof(u_int64_t); 1048 sc_if->sk_rx_ramstart = val; 1049 val += (chunk / sizeof(u_int64_t)); 1050 sc_if->sk_rx_ramend = val - 1; 1051 sc_if->sk_tx_ramstart = val; 1052 val += (chunk / sizeof(u_int64_t)); 1053 sc_if->sk_tx_ramend = val - 1; 1054 } else { 1055 u_int32_t chunk, val; 1056 1057 chunk = sc->sk_ramsize / 4; 1058 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1059 sizeof(u_int64_t); 1060 sc_if->sk_rx_ramstart = val; 1061 val += (chunk / sizeof(u_int64_t)); 1062 sc_if->sk_rx_ramend = val - 1; 1063 sc_if->sk_tx_ramstart = val; 1064 val += (chunk / sizeof(u_int64_t)); 1065 sc_if->sk_tx_ramend = val - 1; 1066 } 1067 1068 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1069 " tx_ramstart=%#x tx_ramend=%#x\n", 1070 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1071 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1072 1073 /* Read and save PHY type and set PHY address */ 1074 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1075 switch (sc_if->sk_phytype) { 1076 case SK_PHYTYPE_XMAC: 1077 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1078 break; 1079 case SK_PHYTYPE_BCOM: 1080 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1081 break; 1082 case SK_PHYTYPE_MARV_COPPER: 1083 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1084 break; 1085 default: 1086 printf("%s: unsupported PHY type: %d\n", 1087 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1088 return; 1089 } 1090 1091 /* Allocate the descriptor queues. */ 1092 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1093 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1094 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 1095 goto fail; 1096 } 1097 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1098 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1099 printf("%s: can't map dma buffers (%d bytes)\n", 1100 sc_if->sk_dev.dv_xname, sizeof(struct sk_ring_data)); 1101 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1102 goto fail; 1103 } 1104 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1105 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1106 &sc_if->sk_ring_map)) { 1107 printf("%s: can't create dma map\n", sc_if->sk_dev.dv_xname); 1108 bus_dmamem_unmap(sc->sc_dmatag, kva, 1109 sizeof(struct sk_ring_data)); 1110 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1111 goto fail; 1112 } 1113 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1114 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1115 printf("%s: can't load dma map\n", sc_if->sk_dev.dv_xname); 1116 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1117 bus_dmamem_unmap(sc->sc_dmatag, kva, 1118 sizeof(struct sk_ring_data)); 1119 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1120 goto fail; 1121 } 1122 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1123 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1124 1125 ifp = &sc_if->arpcom.ac_if; 1126 ifp->if_softc = sc_if; 1127 ifp->if_mtu = ETHERMTU; 1128 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1129 ifp->if_ioctl = sk_ioctl; 1130 ifp->if_output = ether_output; 1131 ifp->if_start = sk_start; 1132 ifp->if_watchdog = sk_watchdog; 1133 ifp->if_baudrate = 1000000000; 1134 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1135 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1136 IFQ_SET_READY(&ifp->if_snd); 1137 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1138 1139 /* 1140 * Do miibus setup. 1141 */ 1142 switch (sc->sk_type) { 1143 case SK_GENESIS: 1144 sk_init_xmac(sc_if); 1145 break; 1146 case SK_YUKON: 1147 sk_init_yukon(sc_if); 1148 break; 1149 default: 1150 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1151 sc->sk_type); 1152 } 1153 1154 DPRINTFN(2, ("sk_attach: 1\n")); 1155 1156 sc_if->sk_mii.mii_ifp = ifp; 1157 switch (sc->sk_type) { 1158 case SK_GENESIS: 1159 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1160 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1161 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1162 break; 1163 case SK_YUKON: 1164 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1165 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1166 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1167 break; 1168 } 1169 1170 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1171 sk_ifmedia_upd, sk_ifmedia_sts); 1172 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1173 MII_OFFSET_ANY, 0); 1174 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1175 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1176 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1177 0, NULL); 1178 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1179 } 1180 else 1181 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1182 1183 timeout_set(&sc_if->sk_tick_ch, sk_tick, sc_if); 1184 timeout_add(&sc_if->sk_tick_ch, hz); 1185 1186 DPRINTFN(2, ("sk_attach: 1\n")); 1187 1188 /* 1189 * Call MI attach routines. 1190 */ 1191 if_attach(ifp); 1192 ether_ifattach(ifp); 1193 1194 DPRINTFN(2, ("sk_attach: end\n")); 1195 1196 return; 1197 1198 fail: 1199 sc->sk_if[sa->skc_port] = NULL; 1200 } 1201 1202 int 1203 skcprint(void *aux, const char *pnp) 1204 { 1205 struct skc_attach_args *sa = aux; 1206 1207 if (pnp) 1208 printf("sk port %c at %s", 1209 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1210 else 1211 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1212 return (UNCONF); 1213 } 1214 1215 /* 1216 * Attach the interface. Allocate softc structures, do ifmedia 1217 * setup and ethernet/BPF attach. 1218 */ 1219 void 1220 skc_attach(struct device *parent, struct device *self, void *aux) 1221 { 1222 struct sk_softc *sc = (struct sk_softc *)self; 1223 struct pci_attach_args *pa = aux; 1224 struct skc_attach_args skca; 1225 pci_chipset_tag_t pc = pa->pa_pc; 1226 pci_intr_handle_t ih; 1227 const char *intrstr = NULL; 1228 bus_addr_t iobase; 1229 bus_size_t iosize; 1230 int s; 1231 u_int32_t command; 1232 1233 DPRINTFN(2, ("begin skc_attach\n")); 1234 1235 s = splimp(); 1236 1237 /* 1238 * Handle power management nonsense. 1239 */ 1240 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1241 1242 if (command == 0x01) { 1243 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1244 if (command & SK_PSTATE_MASK) { 1245 u_int32_t iobase, membase, irq; 1246 1247 /* Save important PCI config data. */ 1248 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1249 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1250 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1251 1252 /* Reset the power state. */ 1253 printf("%s chip is in D%d power mode " 1254 "-- setting to D0\n", sc->sk_dev.dv_xname, 1255 command & SK_PSTATE_MASK); 1256 command &= 0xFFFFFFFC; 1257 pci_conf_write(pc, pa->pa_tag, 1258 SK_PCI_PWRMGMTCTRL, command); 1259 1260 /* Restore PCI config data. */ 1261 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1262 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1263 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1264 } 1265 } 1266 1267 /* 1268 * Map control/status registers. 1269 */ 1270 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1271 1272 switch (PCI_PRODUCT(pa->pa_id)) { 1273 case PCI_PRODUCT_SCHNEIDERKOCH_GE: 1274 sc->sk_type = SK_GENESIS; 1275 break; 1276 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1277 case PCI_PRODUCT_3COM_3C940: 1278 sc->sk_type = SK_YUKON; 1279 break; 1280 default: 1281 printf(": unknown device!\n"); 1282 goto fail; 1283 } 1284 1285 #ifdef SK_USEIOSPACE 1286 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1287 printf(": failed to enable I/O ports!\n"); 1288 goto fail; 1289 } 1290 /* 1291 * Map control/status registers. 1292 */ 1293 if (pci_io_find(pc, pa->pa_tag, SK_PCI_LOIO, &iobase, &iosize)) { 1294 printf(": can't find i/o space\n"); 1295 goto fail; 1296 } 1297 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->sk_bhandle)) { 1298 printf(": can't map i/o space\n"); 1299 goto fail; 1300 } 1301 sc->sk_btag = pa->pa_iot; 1302 #else 1303 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1304 printf(": failed to enable memory mapping!\n"); 1305 goto fail; 1306 } 1307 if (pci_mem_find(pc, pa->pa_tag, SK_PCI_LOMEM, &iobase, &iosize, NULL)){ 1308 printf(": can't find mem space\n"); 1309 goto fail; 1310 } 1311 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->sk_bhandle)) { 1312 printf(": can't map mem space\n"); 1313 goto fail; 1314 } 1315 sc->sk_btag = pa->pa_memt; 1316 1317 DPRINTFN(2, ("skc_attach: iobase=%#x, iosize=%#x\n", iobase, iosize)); 1318 #endif 1319 sc->sc_dmatag = pa->pa_dmat; 1320 1321 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1322 1323 /* Allocate interrupt */ 1324 if (pci_intr_map(pa, &ih)) { 1325 printf(": couldn't map interrupt\n"); 1326 goto fail; 1327 } 1328 1329 intrstr = pci_intr_string(pc, ih); 1330 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc, 1331 self->dv_xname); 1332 if (sc->sk_intrhand == NULL) { 1333 printf(": couldn't establish interrupt"); 1334 if (intrstr != NULL) 1335 printf(" at %s", intrstr); 1336 goto fail; 1337 } 1338 printf(": %s\n", intrstr); 1339 1340 /* Reset the adapter. */ 1341 sk_reset(sc); 1342 1343 /* Read and save vital product data from EEPROM. */ 1344 sk_vpd_read(sc); 1345 1346 if (sc->sk_type == SK_GENESIS) { 1347 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1348 /* Read and save RAM size and RAMbuffer offset */ 1349 switch(val) { 1350 case SK_RAMSIZE_512K_64: 1351 sc->sk_ramsize = 0x80000; 1352 sc->sk_rboff = SK_RBOFF_0; 1353 break; 1354 case SK_RAMSIZE_1024K_64: 1355 sc->sk_ramsize = 0x100000; 1356 sc->sk_rboff = SK_RBOFF_80000; 1357 break; 1358 case SK_RAMSIZE_1024K_128: 1359 sc->sk_ramsize = 0x100000; 1360 sc->sk_rboff = SK_RBOFF_0; 1361 break; 1362 case SK_RAMSIZE_2048K_128: 1363 sc->sk_ramsize = 0x200000; 1364 sc->sk_rboff = SK_RBOFF_0; 1365 break; 1366 default: 1367 printf("%s: unknown ram size: %d\n", 1368 sc->sk_dev.dv_xname, val); 1369 goto fail; 1370 break; 1371 } 1372 1373 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1374 sc->sk_ramsize, sc->sk_ramsize / 1024, 1375 sc->sk_rboff)); 1376 } else { 1377 sc->sk_ramsize = 0x20000; 1378 sc->sk_rboff = SK_RBOFF_0; 1379 1380 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1381 sc->sk_ramsize / 1024, sc->sk_ramsize, 1382 sc->sk_rboff)); 1383 } 1384 1385 /* Read and save physical media type */ 1386 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1387 case SK_PMD_1000BASESX: 1388 sc->sk_pmd = IFM_1000_SX; 1389 break; 1390 case SK_PMD_1000BASELX: 1391 sc->sk_pmd = IFM_1000_LX; 1392 break; 1393 case SK_PMD_1000BASECX: 1394 sc->sk_pmd = IFM_1000_CX; 1395 break; 1396 case SK_PMD_1000BASETX: 1397 sc->sk_pmd = IFM_1000_T; 1398 break; 1399 default: 1400 printf("%s: unknown media type: 0x%x\n", 1401 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1402 goto fail; 1403 } 1404 1405 /* Announce the product name. */ 1406 printf("%s: %s\n", sc->sk_dev.dv_xname, sc->sk_vpd_prodname); 1407 1408 skca.skc_port = SK_PORT_A; 1409 (void)config_found(&sc->sk_dev, &skca, skcprint); 1410 1411 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1412 skca.skc_port = SK_PORT_B; 1413 (void)config_found(&sc->sk_dev, &skca, skcprint); 1414 } 1415 1416 /* Turn on the 'driver is loaded' LED. */ 1417 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1418 1419 fail: 1420 splx(s); 1421 } 1422 1423 int 1424 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1425 { 1426 struct sk_softc *sc = sc_if->sk_softc; 1427 struct sk_tx_desc *f = NULL; 1428 u_int32_t frag, cur, cnt = 0; 1429 int i; 1430 struct sk_txmap_entry *entry; 1431 bus_dmamap_t txmap; 1432 1433 DPRINTFN(2, ("sk_encap\n")); 1434 1435 entry = SLIST_FIRST(&sc_if->sk_txmap_listhead); 1436 if (entry == NULL) { 1437 DPRINTFN(2, ("sk_encap: no txmap available\n")); 1438 return ENOBUFS; 1439 } 1440 txmap = entry->dmamap; 1441 1442 cur = frag = *txidx; 1443 1444 #ifdef SK_DEBUG 1445 if (skdebug >= 2) 1446 sk_dump_mbuf(m_head); 1447 #endif 1448 1449 /* 1450 * Start packing the mbufs in this chain into 1451 * the fragment pointers. Stop when we run out 1452 * of fragments or hit the end of the mbuf chain. 1453 */ 1454 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1455 BUS_DMA_NOWAIT)) { 1456 DPRINTFN(2, ("sk_encap: dmamap failed\n")); 1457 return(ENOBUFS); 1458 } 1459 1460 DPRINTFN(2, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1461 1462 for (i = 0; i < txmap->dm_nsegs; i++) { 1463 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1464 DPRINTFN(2, ("sk_encap: too few descriptors free\n")); 1465 return(ENOBUFS); 1466 } 1467 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1468 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1469 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1470 if (cnt == 0) 1471 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1472 else 1473 f->sk_ctl |= SK_TXCTL_OWN; 1474 1475 cur = frag; 1476 SK_INC(frag, SK_TX_RING_CNT); 1477 cnt++; 1478 } 1479 1480 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1481 SLIST_REMOVE_HEAD(&sc_if->sk_txmap_listhead, link); 1482 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1483 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1484 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1485 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1486 sc_if->sk_cdata.sk_tx_cnt += cnt; 1487 1488 #ifdef SK_DEBUG 1489 if (skdebug >= 2) { 1490 struct sk_tx_desc *desc; 1491 u_int32_t idx; 1492 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1493 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1494 sk_dump_txdesc(desc, idx); 1495 } 1496 } 1497 #endif 1498 1499 *txidx = frag; 1500 1501 DPRINTFN(2, ("sk_encap: completed successfully\n")); 1502 1503 return(0); 1504 } 1505 1506 void 1507 sk_start(struct ifnet *ifp) 1508 { 1509 struct sk_if_softc *sc_if = ifp->if_softc; 1510 struct sk_softc *sc = sc_if->sk_softc; 1511 struct mbuf *m_head = NULL; 1512 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1513 int pkts = 0; 1514 1515 DPRINTFN(2, ("sk_start\n")); 1516 1517 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1518 IFQ_POLL(&ifp->if_snd, m_head); 1519 if (m_head == NULL) 1520 break; 1521 1522 /* 1523 * Pack the data into the transmit ring. If we 1524 * don't have room, set the OACTIVE flag and wait 1525 * for the NIC to drain the ring. 1526 */ 1527 if (sk_encap(sc_if, m_head, &idx)) { 1528 ifp->if_flags |= IFF_OACTIVE; 1529 break; 1530 } 1531 1532 /* now we are committed to transmit the packet */ 1533 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1534 pkts++; 1535 1536 /* 1537 * If there's a BPF listener, bounce a copy of this frame 1538 * to him. 1539 */ 1540 #if NBPFILTER > 0 1541 if (ifp->if_bpf) 1542 bpf_mtap(ifp->if_bpf, m_head); 1543 #endif 1544 } 1545 if (pkts == 0) 1546 return; 1547 1548 /* Transmit */ 1549 sc_if->sk_cdata.sk_tx_prod = idx; 1550 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1551 1552 /* Set a timeout in case the chip goes out to lunch. */ 1553 ifp->if_timer = 5; 1554 } 1555 1556 1557 void 1558 sk_watchdog(struct ifnet *ifp) 1559 { 1560 struct sk_if_softc *sc_if = ifp->if_softc; 1561 1562 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1563 sk_init(sc_if); 1564 } 1565 1566 void 1567 sk_shutdown(void *v) 1568 { 1569 struct sk_softc *sc = v; 1570 1571 DPRINTFN(2, ("sk_shutdown\n")); 1572 1573 /* Turn off the 'driver is loaded' LED. */ 1574 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1575 1576 /* 1577 * Reset the GEnesis controller. Doing this should also 1578 * assert the resets on the attached XMAC(s). 1579 */ 1580 sk_reset(sc); 1581 } 1582 1583 void 1584 sk_rxeof(struct sk_if_softc *sc_if) 1585 { 1586 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1587 struct mbuf *m; 1588 struct sk_chain *cur_rx; 1589 struct sk_rx_desc *cur_desc; 1590 int i, cur, total_len = 0; 1591 u_int32_t rxstat; 1592 bus_dmamap_t dmamap; 1593 u_int16_t csum1, csum2; 1594 1595 DPRINTFN(2, ("sk_rxeof\n")); 1596 1597 i = sc_if->sk_cdata.sk_rx_prod; 1598 1599 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1600 cur = i; 1601 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1602 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1603 1604 rxstat = cur_desc->sk_xmac_rxstat; 1605 m = cur_rx->sk_mbuf; 1606 cur_rx->sk_mbuf = NULL; 1607 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1608 1609 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1610 sc_if->sk_cdata.sk_rx_map[cur] = 0; 1611 1612 csum1 = sc_if->sk_rdata->sk_rx_ring[i].sk_csum1; 1613 csum2 = sc_if->sk_rdata->sk_rx_ring[i].sk_csum2; 1614 1615 SK_INC(i, SK_RX_RING_CNT); 1616 1617 if (rxstat & XM_RXSTAT_ERRFRAME) { 1618 ifp->if_ierrors++; 1619 sk_newbuf(sc_if, cur, m, dmamap); 1620 continue; 1621 } 1622 1623 /* 1624 * Try to allocate a new jumbo buffer. If that 1625 * fails, copy the packet to mbufs and put the 1626 * jumbo buffer back in the ring so it can be 1627 * re-used. If allocating mbufs fails, then we 1628 * have to drop the packet. 1629 */ 1630 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1631 struct mbuf *m0; 1632 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1633 total_len + ETHER_ALIGN, 0, ifp, NULL); 1634 sk_newbuf(sc_if, cur, m, dmamap); 1635 if (m0 == NULL) { 1636 printf("%s: no receive buffers " 1637 "available -- packet dropped!\n", 1638 sc_if->sk_dev.dv_xname); 1639 ifp->if_ierrors++; 1640 continue; 1641 } 1642 m_adj(m0, ETHER_ALIGN); 1643 m = m0; 1644 } else { 1645 m->m_pkthdr.rcvif = ifp; 1646 m->m_pkthdr.len = m->m_len = total_len; 1647 } 1648 1649 ifp->if_ipackets++; 1650 1651 sk_rxcsum(ifp, m, csum1, csum2); 1652 1653 #if NBPFILTER > 0 1654 if (ifp->if_bpf) 1655 bpf_mtap(ifp->if_bpf, m); 1656 #endif 1657 1658 /* pass it on. */ 1659 ether_input_mbuf(ifp, m); 1660 } 1661 1662 sc_if->sk_cdata.sk_rx_prod = i; 1663 } 1664 1665 void 1666 sk_rxcsum(struct ifnet *ifp, struct mbuf *m, const u_int16_t csum1, const u_int16_t csum2) 1667 { 1668 struct ether_header *eh; 1669 struct ip *ip; 1670 u_int8_t *pp; 1671 int hlen, len, plen; 1672 u_int16_t iph_csum, ipo_csum, ipd_csum, csum; 1673 1674 pp = mtod(m, u_int8_t *); 1675 plen = m->m_pkthdr.len; 1676 if (plen < sizeof(*eh)) 1677 return; 1678 eh = (struct ether_header *)pp; 1679 iph_csum = in_cksum_addword(csum1, (~csum2 & 0xffff)); 1680 1681 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1682 u_int16_t *xp = (u_int16_t *)pp; 1683 1684 xp = (u_int16_t *)pp; 1685 if (xp[1] != htons(ETHERTYPE_IP)) 1686 return; 1687 iph_csum = in_cksum_addword(iph_csum, (~xp[0] & 0xffff)); 1688 iph_csum = in_cksum_addword(iph_csum, (~xp[1] & 0xffff)); 1689 xp = (u_int16_t *)(pp + sizeof(struct ip)); 1690 iph_csum = in_cksum_addword(iph_csum, xp[0]); 1691 iph_csum = in_cksum_addword(iph_csum, xp[1]); 1692 pp += EVL_ENCAPLEN; 1693 } else if (eh->ether_type != htons(ETHERTYPE_IP)) 1694 return; 1695 1696 pp += sizeof(*eh); 1697 plen -= sizeof(*eh); 1698 1699 ip = (struct ip *)pp; 1700 1701 if (ip->ip_v != IPVERSION) 1702 return; 1703 1704 hlen = ip->ip_hl << 2; 1705 if (hlen < sizeof(struct ip)) 1706 return; 1707 if (hlen > ntohs(ip->ip_len)) 1708 return; 1709 1710 /* Don't deal with truncated or padded packets. */ 1711 if (plen != ntohs(ip->ip_len)) 1712 return; 1713 1714 len = hlen - sizeof(struct ip); 1715 if (len > 0) { 1716 u_int16_t *p; 1717 1718 p = (u_int16_t *)(ip + 1); 1719 ipo_csum = 0; 1720 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++) 1721 ipo_csum = in_cksum_addword(ipo_csum, *p); 1722 iph_csum = in_cksum_addword(iph_csum, ipo_csum); 1723 ipd_csum = in_cksum_addword(csum2, (~ipo_csum & 0xffff)); 1724 } else 1725 ipd_csum = csum2; 1726 1727 if (iph_csum != 0xffff) { 1728 if (ifp->if_bpf) 1729 bpf_mtap(ifp->if_bpf, m); 1730 return; 1731 } 1732 m->m_pkthdr.csum |= M_IPV4_CSUM_IN_OK; 1733 1734 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1735 return; /* ip frag, we're done for now */ 1736 1737 pp += hlen; 1738 1739 /* Only know checksum protocol for udp/tcp */ 1740 if (ip->ip_p == IPPROTO_UDP) { 1741 struct udphdr *uh = (struct udphdr *)pp; 1742 1743 if (uh->uh_sum == 0) /* udp with no checksum */ 1744 return; 1745 } else if (ip->ip_p != IPPROTO_TCP) 1746 return; 1747 1748 csum = in_cksum_phdr(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1749 htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum); 1750 if (csum == 0xffff) { 1751 m->m_pkthdr.csum |= (ip->ip_p == IPPROTO_TCP) ? 1752 M_TCP_CSUM_IN_OK : M_UDP_CSUM_IN_OK; 1753 } 1754 } 1755 1756 void 1757 sk_txeof(struct sk_if_softc *sc_if) 1758 { 1759 struct sk_softc *sc = sc_if->sk_softc; 1760 struct sk_tx_desc *cur_tx = NULL; 1761 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1762 u_int32_t idx; 1763 struct sk_txmap_entry *entry; 1764 1765 DPRINTFN(2, ("sk_txeof\n")); 1766 1767 /* 1768 * Go through our tx ring and free mbufs for those 1769 * frames that have been sent. 1770 */ 1771 idx = sc_if->sk_cdata.sk_tx_cons; 1772 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1773 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1774 #ifdef SK_DEBUG 1775 if (skdebug >= 2) 1776 sk_dump_txdesc(cur_tx, idx); 1777 #endif 1778 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1779 break; 1780 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1781 ifp->if_opackets++; 1782 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1783 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1784 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1785 1786 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1787 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1788 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1789 1790 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1791 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, 1792 link); 1793 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1794 } 1795 sc_if->sk_cdata.sk_tx_cnt--; 1796 SK_INC(idx, SK_TX_RING_CNT); 1797 ifp->if_timer = 0; 1798 } 1799 1800 sc_if->sk_cdata.sk_tx_cons = idx; 1801 1802 if (cur_tx != NULL) 1803 ifp->if_flags &= ~IFF_OACTIVE; 1804 } 1805 1806 void 1807 sk_tick(void *xsc_if) 1808 { 1809 struct sk_if_softc *sc_if = xsc_if; 1810 struct mii_data *mii = &sc_if->sk_mii; 1811 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1812 int i; 1813 1814 DPRINTFN(2, ("sk_tick\n")); 1815 1816 if (!(ifp->if_flags & IFF_UP)) 1817 return; 1818 1819 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1820 sk_intr_bcom(sc_if); 1821 return; 1822 } 1823 1824 /* 1825 * According to SysKonnect, the correct way to verify that 1826 * the link has come back up is to poll bit 0 of the GPIO 1827 * register three times. This pin has the signal from the 1828 * link sync pin connected to it; if we read the same link 1829 * state 3 times in a row, we know the link is up. 1830 */ 1831 for (i = 0; i < 3; i++) { 1832 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1833 break; 1834 } 1835 1836 if (i != 3) { 1837 timeout_add(&sc_if->sk_tick_ch, hz); 1838 return; 1839 } 1840 1841 /* Turn the GP0 interrupt back on. */ 1842 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1843 SK_XM_READ_2(sc_if, XM_ISR); 1844 mii_tick(mii); 1845 mii_pollstat(mii); 1846 timeout_del(&sc_if->sk_tick_ch); 1847 } 1848 1849 void 1850 sk_intr_bcom(struct sk_if_softc *sc_if) 1851 { 1852 struct mii_data *mii = &sc_if->sk_mii; 1853 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1854 int status; 1855 1856 1857 DPRINTFN(2, ("sk_intr_bcom\n")); 1858 1859 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1860 1861 /* 1862 * Read the PHY interrupt register to make sure 1863 * we clear any pending interrupts. 1864 */ 1865 status = sk_xmac_miibus_readreg((struct device *)sc_if, 1866 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1867 1868 if (!(ifp->if_flags & IFF_RUNNING)) { 1869 sk_init_xmac(sc_if); 1870 return; 1871 } 1872 1873 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1874 int lstat; 1875 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 1876 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 1877 1878 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1879 mii_mediachg(mii); 1880 /* Turn off the link LED. */ 1881 SK_IF_WRITE_1(sc_if, 0, 1882 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1883 sc_if->sk_link = 0; 1884 } else if (status & BRGPHY_ISR_LNK_CHG) { 1885 sk_xmac_miibus_writereg((struct device *)sc_if, 1886 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 1887 mii_tick(mii); 1888 sc_if->sk_link = 1; 1889 /* Turn on the link LED. */ 1890 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1891 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1892 SK_LINKLED_BLINK_OFF); 1893 mii_pollstat(mii); 1894 } else { 1895 mii_tick(mii); 1896 timeout_add(&sc_if->sk_tick_ch, hz); 1897 } 1898 } 1899 1900 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1901 } 1902 1903 void 1904 sk_intr_xmac(struct sk_if_softc *sc_if) 1905 { 1906 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 1907 1908 DPRINTFN(2, ("sk_intr_xmac\n")); 1909 1910 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1911 if (status & XM_ISR_GP0_SET) { 1912 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1913 timeout_add(&sc_if->sk_tick_ch, hz); 1914 } 1915 1916 if (status & XM_ISR_AUTONEG_DONE) { 1917 timeout_add(&sc_if->sk_tick_ch, hz); 1918 } 1919 } 1920 1921 if (status & XM_IMR_TX_UNDERRUN) 1922 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1923 1924 if (status & XM_IMR_RX_OVERRUN) 1925 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1926 } 1927 1928 void 1929 sk_intr_yukon(sc_if) 1930 struct sk_if_softc *sc_if; 1931 { 1932 int status; 1933 1934 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1935 1936 DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status)); 1937 } 1938 1939 int 1940 sk_intr(void *xsc) 1941 { 1942 struct sk_softc *sc = xsc; 1943 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1944 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1945 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1946 u_int32_t status; 1947 int claimed = 0; 1948 1949 if (sc_if0 != NULL) 1950 ifp0 = &sc_if0->arpcom.ac_if; 1951 if (sc_if1 != NULL) 1952 ifp1 = &sc_if1->arpcom.ac_if; 1953 1954 for (;;) { 1955 status = CSR_READ_4(sc, SK_ISSR); 1956 DPRINTFN(2, ("sk_intr: status=%#x\n", status)); 1957 1958 if (!(status & sc->sk_intrmask)) 1959 break; 1960 1961 claimed = 1; 1962 1963 /* Handle receive interrupts first. */ 1964 if (status & SK_ISR_RX1_EOF) { 1965 sk_rxeof(sc_if0); 1966 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1967 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1968 } 1969 if (status & SK_ISR_RX2_EOF) { 1970 sk_rxeof(sc_if1); 1971 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1972 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1973 } 1974 1975 /* Then transmit interrupts. */ 1976 if (status & SK_ISR_TX1_S_EOF) { 1977 sk_txeof(sc_if0); 1978 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1979 SK_TXBMU_CLR_IRQ_EOF); 1980 } 1981 if (status & SK_ISR_TX2_S_EOF) { 1982 sk_txeof(sc_if1); 1983 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1984 SK_TXBMU_CLR_IRQ_EOF); 1985 } 1986 1987 /* Then MAC interrupts. */ 1988 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 1989 if (sc->sk_type == SK_GENESIS) 1990 sk_intr_xmac(sc_if0); 1991 else 1992 sk_intr_yukon(sc_if0); 1993 } 1994 1995 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 1996 if (sc->sk_type == SK_GENESIS) 1997 sk_intr_xmac(sc_if1); 1998 else 1999 sk_intr_yukon(sc_if1); 2000 2001 } 2002 2003 if (status & SK_ISR_EXTERNAL_REG) { 2004 if (ifp0 != NULL && 2005 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2006 sk_intr_bcom(sc_if0); 2007 2008 if (ifp1 != NULL && 2009 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2010 sk_intr_bcom(sc_if1); 2011 } 2012 } 2013 2014 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2015 2016 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2017 sk_start(ifp0); 2018 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2019 sk_start(ifp1); 2020 2021 return (claimed); 2022 } 2023 2024 void 2025 sk_init_xmac(struct sk_if_softc *sc_if) 2026 { 2027 struct sk_softc *sc = sc_if->sk_softc; 2028 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2029 struct sk_bcom_hack bhack[] = { 2030 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2031 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2032 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2033 { 0, 0 } }; 2034 2035 DPRINTFN(2, ("sk_init_xmac\n")); 2036 2037 /* Unreset the XMAC. */ 2038 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2039 DELAY(1000); 2040 2041 /* Reset the XMAC's internal state. */ 2042 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2043 2044 /* Save the XMAC II revision */ 2045 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2046 2047 /* 2048 * Perform additional initialization for external PHYs, 2049 * namely for the 1000baseTX cards that use the XMAC's 2050 * GMII mode. 2051 */ 2052 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2053 int i = 0; 2054 u_int32_t val; 2055 2056 /* Take PHY out of reset. */ 2057 val = sk_win_read_4(sc, SK_GPIO); 2058 if (sc_if->sk_port == SK_PORT_A) 2059 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2060 else 2061 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2062 sk_win_write_4(sc, SK_GPIO, val); 2063 2064 /* Enable GMII mode on the XMAC. */ 2065 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2066 2067 sk_xmac_miibus_writereg((struct device *)sc_if, 2068 SK_PHYADDR_BCOM, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2069 DELAY(10000); 2070 sk_xmac_miibus_writereg((struct device *)sc_if, 2071 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2072 2073 /* 2074 * Early versions of the BCM5400 apparently have 2075 * a bug that requires them to have their reserved 2076 * registers initialized to some magic values. I don't 2077 * know what the numbers do, I'm just the messenger. 2078 */ 2079 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2080 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2081 while(bhack[i].reg) { 2082 sk_xmac_miibus_writereg((struct device *)sc_if, 2083 SK_PHYADDR_BCOM, bhack[i].reg, 2084 bhack[i].val); 2085 i++; 2086 } 2087 } 2088 } 2089 2090 /* Set station address */ 2091 SK_XM_WRITE_2(sc_if, XM_PAR0, 2092 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2093 SK_XM_WRITE_2(sc_if, XM_PAR1, 2094 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2095 SK_XM_WRITE_2(sc_if, XM_PAR2, 2096 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2097 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2098 2099 if (ifp->if_flags & IFF_PROMISC) { 2100 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2101 } else { 2102 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2103 } 2104 2105 if (ifp->if_flags & IFF_BROADCAST) { 2106 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2107 } else { 2108 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2109 } 2110 2111 /* We don't need the FCS appended to the packet. */ 2112 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2113 2114 /* We want short frames padded to 60 bytes. */ 2115 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2116 2117 /* 2118 * Enable the reception of all error frames. This is is 2119 * a necessary evil due to the design of the XMAC. The 2120 * XMAC's receive FIFO is only 8K in size, however jumbo 2121 * frames can be up to 9000 bytes in length. When bad 2122 * frame filtering is enabled, the XMAC's RX FIFO operates 2123 * in 'store and forward' mode. For this to work, the 2124 * entire frame has to fit into the FIFO, but that means 2125 * that jumbo frames larger than 8192 bytes will be 2126 * truncated. Disabling all bad frame filtering causes 2127 * the RX FIFO to operate in streaming mode, in which 2128 * case the XMAC will start transfering frames out of the 2129 * RX FIFO as soon as the FIFO threshold is reached. 2130 */ 2131 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2132 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2133 XM_MODE_RX_INRANGELEN); 2134 2135 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2136 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2137 else 2138 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2139 2140 /* 2141 * Bump up the transmit threshold. This helps hold off transmit 2142 * underruns when we're blasting traffic from both ports at once. 2143 */ 2144 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2145 2146 /* Set multicast filter */ 2147 sk_setmulti(sc_if); 2148 2149 /* Clear and enable interrupts */ 2150 SK_XM_READ_2(sc_if, XM_ISR); 2151 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2152 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2153 else 2154 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2155 2156 /* Configure MAC arbiter */ 2157 switch(sc_if->sk_xmac_rev) { 2158 case XM_XMAC_REV_B2: 2159 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2160 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2161 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2162 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2163 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2164 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2165 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2166 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2167 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2168 break; 2169 case XM_XMAC_REV_C1: 2170 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2171 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2172 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2173 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2174 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2175 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2176 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2177 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2178 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2179 break; 2180 default: 2181 break; 2182 } 2183 sk_win_write_2(sc, SK_MACARB_CTL, 2184 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2185 2186 sc_if->sk_link = 1; 2187 } 2188 2189 void sk_init_yukon(sc_if) 2190 struct sk_if_softc *sc_if; 2191 { 2192 u_int32_t /*mac, */phy; 2193 u_int16_t reg; 2194 int i; 2195 2196 DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n", 2197 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2198 2199 /* GMAC and GPHY Reset */ 2200 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2201 2202 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2203 2204 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2205 DELAY(1000); 2206 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2207 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2208 DELAY(1000); 2209 2210 2211 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2212 2213 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2214 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2215 2216 switch(sc_if->sk_softc->sk_pmd) { 2217 case IFM_1000_SX: 2218 case IFM_1000_LX: 2219 phy |= SK_GPHY_FIBER; 2220 break; 2221 2222 case IFM_1000_CX: 2223 case IFM_1000_T: 2224 phy |= SK_GPHY_COPPER; 2225 break; 2226 } 2227 2228 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2229 2230 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2231 DELAY(1000); 2232 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2233 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2234 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2235 2236 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2237 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2238 2239 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2240 2241 /* unused read of the interrupt source register */ 2242 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2243 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2244 2245 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2246 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2247 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2248 2249 /* MIB Counter Clear Mode set */ 2250 reg |= YU_PAR_MIB_CLR; 2251 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2252 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2253 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2254 2255 /* MIB Counter Clear Mode clear */ 2256 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2257 reg &= ~YU_PAR_MIB_CLR; 2258 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2259 2260 /* receive control reg */ 2261 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2262 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2263 YU_RCR_CRCR); 2264 2265 /* transmit parameter register */ 2266 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2267 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2268 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2269 2270 /* serial mode register */ 2271 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2272 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2273 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2274 2275 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2276 /* Setup Yukon's address */ 2277 for (i = 0; i < 3; i++) { 2278 /* Write Source Address 1 (unicast filter) */ 2279 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2280 sc_if->arpcom.ac_enaddr[i * 2] | 2281 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2282 } 2283 2284 for (i = 0; i < 3; i++) { 2285 reg = sk_win_read_2(sc_if->sk_softc, 2286 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2287 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2288 } 2289 2290 /* clear all Multicast filter hash registers */ 2291 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2292 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 2293 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 2294 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 2295 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 2296 2297 /* enable interrupt mask for counter overflows */ 2298 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2299 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2300 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2301 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2302 2303 /* Configure RX MAC FIFO */ 2304 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2305 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2306 2307 /* Configure TX MAC FIFO */ 2308 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2309 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2310 2311 DPRINTFN(6, ("sk_init_yukon: end\n")); 2312 } 2313 2314 /* 2315 * Note that to properly initialize any part of the GEnesis chip, 2316 * you first have to take it out of reset mode. 2317 */ 2318 void 2319 sk_init(void *xsc_if) 2320 { 2321 struct sk_if_softc *sc_if = xsc_if; 2322 struct sk_softc *sc = sc_if->sk_softc; 2323 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2324 struct mii_data *mii = &sc_if->sk_mii; 2325 int s; 2326 2327 DPRINTFN(2, ("sk_init\n")); 2328 2329 s = splimp(); 2330 2331 /* Cancel pending I/O and free all RX/TX buffers. */ 2332 sk_stop(sc_if); 2333 2334 if (sc->sk_type == SK_GENESIS) { 2335 /* Configure LINK_SYNC LED */ 2336 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2337 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2338 SK_LINKLED_LINKSYNC_ON); 2339 2340 /* Configure RX LED */ 2341 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2342 SK_RXLEDCTL_COUNTER_START); 2343 2344 /* Configure TX LED */ 2345 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2346 SK_TXLEDCTL_COUNTER_START); 2347 } 2348 2349 /* Configure I2C registers */ 2350 2351 /* Configure XMAC(s) */ 2352 switch (sc->sk_type) { 2353 case SK_GENESIS: 2354 sk_init_xmac(sc_if); 2355 break; 2356 case SK_YUKON: 2357 sk_init_yukon(sc_if); 2358 break; 2359 } 2360 mii_mediachg(mii); 2361 2362 if (sc->sk_type == SK_GENESIS) { 2363 /* Configure MAC FIFOs */ 2364 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2365 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2366 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2367 2368 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2369 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2370 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2371 } 2372 2373 /* Configure transmit arbiter(s) */ 2374 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2375 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2376 2377 /* Configure RAMbuffers */ 2378 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2379 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2380 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2381 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2382 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2383 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2384 2385 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2386 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2387 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2388 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2389 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2390 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2391 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2392 2393 /* Configure BMUs */ 2394 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2395 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2396 SK_RX_RING_ADDR(sc_if, 0)); 2397 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2398 2399 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2400 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2401 SK_TX_RING_ADDR(sc_if, 0)); 2402 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2403 2404 /* Init descriptors */ 2405 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2406 printf("%s: initialization failed: no " 2407 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2408 sk_stop(sc_if); 2409 splx(s); 2410 return; 2411 } 2412 2413 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2414 printf("%s: initialization failed: no " 2415 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2416 sk_stop(sc_if); 2417 splx(s); 2418 return; 2419 } 2420 2421 /* Configure interrupt handling */ 2422 CSR_READ_4(sc, SK_ISSR); 2423 if (sc_if->sk_port == SK_PORT_A) 2424 sc->sk_intrmask |= SK_INTRS1; 2425 else 2426 sc->sk_intrmask |= SK_INTRS2; 2427 2428 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2429 2430 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2431 2432 /* Start BMUs. */ 2433 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2434 2435 if (sc->sk_type == SK_GENESIS) { 2436 /* Enable XMACs TX and RX state machines */ 2437 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2438 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2439 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2440 } 2441 2442 if (sc->sk_type == SK_YUKON) { 2443 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2444 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2445 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2446 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2447 } 2448 2449 2450 ifp->if_flags |= IFF_RUNNING; 2451 ifp->if_flags &= ~IFF_OACTIVE; 2452 2453 splx(s); 2454 } 2455 2456 void 2457 sk_stop(struct sk_if_softc *sc_if) 2458 { 2459 struct sk_softc *sc = sc_if->sk_softc; 2460 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2461 int i; 2462 2463 DPRINTFN(2, ("sk_stop\n")); 2464 2465 timeout_del(&sc_if->sk_tick_ch); 2466 2467 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2468 u_int32_t val; 2469 2470 /* Put PHY back into reset. */ 2471 val = sk_win_read_4(sc, SK_GPIO); 2472 if (sc_if->sk_port == SK_PORT_A) { 2473 val |= SK_GPIO_DIR0; 2474 val &= ~SK_GPIO_DAT0; 2475 } else { 2476 val |= SK_GPIO_DIR2; 2477 val &= ~SK_GPIO_DAT2; 2478 } 2479 sk_win_write_4(sc, SK_GPIO, val); 2480 } 2481 2482 /* Turn off various components of this interface. */ 2483 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2484 switch (sc->sk_type) { 2485 case SK_GENESIS: 2486 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2487 SK_TXMACCTL_XMAC_RESET); 2488 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2489 break; 2490 case SK_YUKON: 2491 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2492 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2493 break; 2494 } 2495 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2496 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2497 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2498 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2499 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2500 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2501 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2502 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2503 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2504 2505 /* Disable interrupts */ 2506 if (sc_if->sk_port == SK_PORT_A) 2507 sc->sk_intrmask &= ~SK_INTRS1; 2508 else 2509 sc->sk_intrmask &= ~SK_INTRS2; 2510 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2511 2512 SK_XM_READ_2(sc_if, XM_ISR); 2513 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2514 2515 /* Free RX and TX mbufs still in the queues. */ 2516 for (i = 0; i < SK_RX_RING_CNT; i++) { 2517 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2518 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2519 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2520 } 2521 } 2522 2523 for (i = 0; i < SK_TX_RING_CNT; i++) { 2524 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2525 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2526 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2527 } 2528 } 2529 2530 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2531 } 2532 2533 struct cfattach skc_ca = { 2534 sizeof(struct sk_softc), skc_probe, skc_attach, 2535 }; 2536 2537 struct cfdriver skc_cd = { 2538 0, "skc", DV_DULL 2539 }; 2540 2541 struct cfattach sk_ca = { 2542 sizeof(struct sk_if_softc), sk_probe, sk_attach, 2543 }; 2544 2545 struct cfdriver sk_cd = { 2546 0, "sk", DV_IFNET 2547 }; 2548 2549 #ifdef SK_DEBUG 2550 void 2551 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2552 { 2553 #define DESC_PRINT(X) \ 2554 if (desc->X) \ 2555 printf("txdesc[%d]." #X "=%#x\n", \ 2556 idx, desc->X); 2557 2558 DESC_PRINT(sk_ctl); 2559 DESC_PRINT(sk_next); 2560 DESC_PRINT(sk_data_lo); 2561 DESC_PRINT(sk_data_hi); 2562 DESC_PRINT(sk_xmac_txstat); 2563 DESC_PRINT(sk_rsvd0); 2564 DESC_PRINT(sk_csum_startval); 2565 DESC_PRINT(sk_csum_startpos); 2566 DESC_PRINT(sk_csum_writepos); 2567 DESC_PRINT(sk_rsvd1); 2568 #undef PRINT 2569 } 2570 2571 void 2572 sk_dump_bytes(const char *data, int len) 2573 { 2574 int c, i, j; 2575 2576 for (i = 0; i < len; i += 16) { 2577 printf("%08x ", i); 2578 c = len - i; 2579 if (c > 16) c = 16; 2580 2581 for (j = 0; j < c; j++) { 2582 printf("%02x ", data[i + j] & 0xff); 2583 if ((j & 0xf) == 7 && j > 0) 2584 printf(" "); 2585 } 2586 2587 for (; j < 16; j++) 2588 printf(" "); 2589 printf(" "); 2590 2591 for (j = 0; j < c; j++) { 2592 int ch = data[i + j] & 0xff; 2593 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2594 } 2595 2596 printf("\n"); 2597 2598 if (c < 16) 2599 break; 2600 } 2601 } 2602 2603 void 2604 sk_dump_mbuf(struct mbuf *m) 2605 { 2606 int count = m->m_pkthdr.len; 2607 2608 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2609 2610 while (count > 0 && m) { 2611 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2612 m, m->m_data, m->m_len); 2613 sk_dump_bytes(mtod(m, char *), m->m_len); 2614 2615 count -= m->m_len; 2616 m = m->m_next; 2617 } 2618 } 2619 #endif 2620