1 /* $OpenBSD: if_sk.c,v 1.17 2001/09/11 20:05:25 miod Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 39 * the SK-984x series adapters, both single port and dual port. 40 * References: 41 * The XaQti XMAC II datasheet, 42 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 43 * The SysKonnect GEnesis manual, http://www.syskonnect.com 44 * 45 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 46 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 47 * convience to others until Vitesse corrects this problem: 48 * 49 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 50 * 51 * Written by Bill Paul <wpaul@ee.columbia.edu> 52 * Department of Electrical Engineering 53 * Columbia University, New York City 54 */ 55 56 /* 57 * The SysKonnect gigabit ethernet adapters consist of two main 58 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 59 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 60 * components and a PHY while the GEnesis controller provides a PCI 61 * interface with DMA support. Each card may have between 512K and 62 * 2MB of SRAM on board depending on the configuration. 63 * 64 * The SysKonnect GEnesis controller can have either one or two XMAC 65 * chips connected to it, allowing single or dual port NIC configurations. 66 * SysKonnect has the distinction of being the only vendor on the market 67 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 68 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 69 * XMAC registers. This driver takes advantage of these features to allow 70 * both XMACs to operate as independent interfaces. 71 */ 72 73 #include "bpfilter.h" 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/sockio.h> 78 #include <sys/mbuf.h> 79 #include <sys/malloc.h> 80 #include <sys/kernel.h> 81 #include <sys/socket.h> 82 #include <sys/device.h> 83 #include <sys/queue.h> 84 85 #include <net/if.h> 86 #include <net/if_dl.h> 87 #include <net/if_types.h> 88 89 #ifdef INET 90 #include <netinet/in.h> 91 #include <netinet/in_systm.h> 92 #include <netinet/in_var.h> 93 #include <netinet/ip.h> 94 #include <netinet/if_ether.h> 95 #endif 96 97 #include <net/if_media.h> 98 99 #if NBPFILTER > 0 100 #include <net/bpf.h> 101 #endif 102 103 #include <vm/vm.h> /* for vtophys */ 104 #include <machine/bus.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 #include <dev/mii/brgphyreg.h> 109 110 #include <dev/pci/pcireg.h> 111 #include <dev/pci/pcivar.h> 112 #include <dev/pci/pcidevs.h> 113 114 #define SK_USEIOSPACE 115 #define SK_VERBOSE 116 117 #include <dev/pci/if_skreg.h> 118 #include <dev/pci/xmaciireg.h> 119 120 int skc_probe __P((struct device *, void *, void *)); 121 void skc_attach __P((struct device *, struct device *self, void *aux)); 122 int sk_probe __P((struct device *, void *, void *)); 123 void sk_attach __P((struct device *, struct device *self, void *aux)); 124 int skcprint __P((void *, const char *)); 125 int sk_attach_xmac __P((struct sk_softc *, int)); 126 int sk_intr __P((void *)); 127 void sk_intr_bcom __P((struct sk_if_softc *)); 128 void sk_intr_xmac __P((struct sk_if_softc *)); 129 void sk_rxeof __P((struct sk_if_softc *)); 130 void sk_txeof __P((struct sk_if_softc *)); 131 int sk_encap __P((struct sk_if_softc *, struct mbuf *, u_int32_t *)); 132 void sk_start __P((struct ifnet *)); 133 int sk_ioctl __P((struct ifnet *, u_long, caddr_t)); 134 void sk_init __P((void *)); 135 void sk_init_xmac __P((struct sk_if_softc *)); 136 void sk_stop __P((struct sk_if_softc *)); 137 void sk_watchdog __P((struct ifnet *)); 138 void sk_shutdown __P((void *)); 139 int sk_ifmedia_upd __P((struct ifnet *)); 140 void sk_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 141 void sk_reset __P((struct sk_softc *)); 142 int sk_newbuf __P((struct sk_if_softc *, struct sk_chain *, 143 struct mbuf *)); 144 int sk_init_rx_ring __P((struct sk_if_softc *)); 145 void sk_init_tx_ring __P((struct sk_if_softc *)); 146 u_int32_t sk_win_read_4 __P((struct sk_softc *, int)); 147 u_int16_t sk_win_read_2 __P((struct sk_softc *, int)); 148 u_int8_t sk_win_read_1 __P((struct sk_softc *, int)); 149 void sk_win_write_4 __P((struct sk_softc *, int, u_int32_t)); 150 void sk_win_write_2 __P((struct sk_softc *, int, u_int32_t)); 151 void sk_win_write_1 __P((struct sk_softc *, int, u_int32_t)); 152 u_int8_t sk_vpd_readbyte __P((struct sk_softc *, int)); 153 void sk_vpd_read_res __P((struct sk_softc *, 154 struct vpd_res *, int)); 155 void sk_vpd_read __P((struct sk_softc *)); 156 157 int sk_miibus_readreg __P((struct device *, int, int)); 158 void sk_miibus_writereg __P((struct device *, int, int, int)); 159 void sk_miibus_statchg __P((struct device *)); 160 161 u_int32_t sk_calchash __P((caddr_t)); 162 void sk_setfilt __P((struct sk_if_softc *, caddr_t, int)); 163 void sk_setmulti __P((struct sk_if_softc *)); 164 void sk_tick __P((void *)); 165 166 #define SK_SETBIT(sc, reg, x) \ 167 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 168 169 #define SK_CLRBIT(sc, reg, x) \ 170 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 171 172 #define SK_WIN_SETBIT_4(sc, reg, x) \ 173 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 174 175 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 176 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 177 178 #define SK_WIN_SETBIT_2(sc, reg, x) \ 179 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 180 181 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 182 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 183 184 u_int32_t sk_win_read_4(sc, reg) 185 struct sk_softc *sc; 186 int reg; 187 { 188 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 189 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 190 } 191 192 u_int16_t sk_win_read_2(sc, reg) 193 struct sk_softc *sc; 194 int reg; 195 { 196 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 197 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 198 } 199 200 u_int8_t sk_win_read_1(sc, reg) 201 struct sk_softc *sc; 202 int reg; 203 { 204 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 205 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 206 } 207 208 void sk_win_write_4(sc, reg, val) 209 struct sk_softc *sc; 210 int reg; 211 u_int32_t val; 212 { 213 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 214 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 215 return; 216 } 217 218 void sk_win_write_2(sc, reg, val) 219 struct sk_softc *sc; 220 int reg; 221 u_int32_t val; 222 { 223 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 224 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), (u_int32_t)val); 225 return; 226 } 227 228 void sk_win_write_1(sc, reg, val) 229 struct sk_softc *sc; 230 int reg; 231 u_int32_t val; 232 { 233 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 234 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 235 return; 236 } 237 238 /* 239 * The VPD EEPROM contains Vital Product Data, as suggested in 240 * the PCI 2.1 specification. The VPD data is separared into areas 241 * denoted by resource IDs. The SysKonnect VPD contains an ID string 242 * resource (the name of the adapter), a read-only area resource 243 * containing various key/data fields and a read/write area which 244 * can be used to store asset management information or log messages. 245 * We read the ID string and read-only into buffers attached to 246 * the controller softc structure for later use. At the moment, 247 * we only use the ID string during sk_attach(). 248 */ 249 u_int8_t sk_vpd_readbyte(sc, addr) 250 struct sk_softc *sc; 251 int addr; 252 { 253 int i; 254 255 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 256 for (i = 0; i < SK_TIMEOUT; i++) { 257 DELAY(1); 258 if (sk_win_read_2(sc, 259 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 260 break; 261 } 262 263 if (i == SK_TIMEOUT) 264 return(0); 265 266 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 267 } 268 269 void sk_vpd_read_res(sc, res, addr) 270 struct sk_softc *sc; 271 struct vpd_res *res; 272 int addr; 273 { 274 int i; 275 u_int8_t *ptr; 276 277 ptr = (u_int8_t *)res; 278 for (i = 0; i < sizeof(struct vpd_res); i++) 279 ptr[i] = sk_vpd_readbyte(sc, i + addr); 280 281 return; 282 } 283 284 void sk_vpd_read(sc) 285 struct sk_softc *sc; 286 { 287 int pos = 0, i; 288 struct vpd_res res; 289 290 if (sc->sk_vpd_prodname != NULL) 291 free(sc->sk_vpd_prodname, M_DEVBUF); 292 if (sc->sk_vpd_readonly != NULL) 293 free(sc->sk_vpd_readonly, M_DEVBUF); 294 sc->sk_vpd_prodname = NULL; 295 sc->sk_vpd_readonly = NULL; 296 297 sk_vpd_read_res(sc, &res, pos); 298 299 if (res.vr_id != VPD_RES_ID) { 300 printf("%s: bad VPD resource id: expected %x got %x\n", 301 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 302 return; 303 } 304 305 pos += sizeof(res); 306 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 307 for (i = 0; i < res.vr_len; i++) 308 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 309 sc->sk_vpd_prodname[i] = '\0'; 310 pos += i; 311 312 sk_vpd_read_res(sc, &res, pos); 313 314 if (res.vr_id != VPD_RES_READ) { 315 printf("%s: bad VPD resource id: expected %x got %x\n", 316 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 317 return; 318 } 319 320 pos += sizeof(res); 321 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 322 for (i = 0; i < res.vr_len + 1; i++) 323 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 324 325 return; 326 } 327 328 int 329 sk_miibus_readreg(dev, phy, reg) 330 struct device *dev; 331 int phy, reg; 332 { 333 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 334 int i; 335 336 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 337 return(0); 338 339 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 340 SK_XM_READ_2(sc_if, XM_PHY_DATA); 341 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 342 for (i = 0; i < SK_TIMEOUT; i++) { 343 DELAY(1); 344 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 345 XM_MMUCMD_PHYDATARDY) 346 break; 347 } 348 349 if (i == SK_TIMEOUT) { 350 printf("%s: phy failed to come ready\n", 351 sc_if->sk_dev.dv_xname); 352 return(0); 353 } 354 } 355 DELAY(1); 356 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 357 } 358 359 void 360 sk_miibus_writereg(dev, phy, reg, val) 361 struct device *dev; 362 int phy, reg, val; 363 { 364 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 365 int i; 366 367 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 368 for (i = 0; i < SK_TIMEOUT; i++) { 369 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 370 break; 371 } 372 373 if (i == SK_TIMEOUT) { 374 printf("%s: phy failed to come ready\n", 375 sc_if->sk_dev.dv_xname); 376 return; 377 } 378 379 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 380 for (i = 0; i < SK_TIMEOUT; i++) { 381 DELAY(1); 382 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 383 break; 384 } 385 386 if (i == SK_TIMEOUT) 387 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 388 389 return; 390 } 391 392 void 393 sk_miibus_statchg(dev) 394 struct device *dev; 395 { 396 struct sk_if_softc *sc_if; 397 struct mii_data *mii; 398 399 sc_if = (struct sk_if_softc *)dev; 400 mii = &sc_if->sk_mii; 401 402 /* 403 * If this is a GMII PHY, manually set the XMAC's 404 * duplex mode accordingly. 405 */ 406 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 407 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 408 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 409 } else { 410 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 411 } 412 } 413 414 return; 415 } 416 417 #define SK_POLY 0xEDB88320 418 #define SK_BITS 6 419 420 u_int32_t sk_calchash(addr) 421 caddr_t addr; 422 { 423 u_int32_t idx, bit, data, crc; 424 425 /* Compute CRC for the address value. */ 426 crc = 0xFFFFFFFF; /* initial value */ 427 428 for (idx = 0; idx < 6; idx++) { 429 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 430 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0); 431 } 432 433 return (~crc & ((1 << SK_BITS) - 1)); 434 } 435 436 void sk_setfilt(sc_if, addr, slot) 437 struct sk_if_softc *sc_if; 438 caddr_t addr; 439 int slot; 440 { 441 int base; 442 443 base = XM_RXFILT_ENTRY(slot); 444 445 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 446 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 447 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 448 449 return; 450 } 451 452 void 453 sk_setmulti(sc_if) 454 struct sk_if_softc *sc_if; 455 { 456 struct ifnet *ifp; 457 u_int32_t hashes[2] = { 0, 0 }; 458 int h, i; 459 struct arpcom *ac = &sc_if->arpcom; 460 struct ether_multi *enm; 461 struct ether_multistep step; 462 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 463 464 ifp = &sc_if->arpcom.ac_if; 465 466 /* First, zot all the existing filters. */ 467 for (i = 1; i < XM_RXFILT_MAX; i++) 468 sk_setfilt(sc_if, (caddr_t)&dummy, i); 469 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 470 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 471 472 /* Now program new ones. */ 473 allmulti: 474 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 475 hashes[0] = 0xFFFFFFFF; 476 hashes[1] = 0xFFFFFFFF; 477 } else { 478 i = 1; 479 /* First find the tail of the list. */ 480 ETHER_FIRST_MULTI(step, ac, enm); 481 while (enm != NULL) { 482 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 483 ifp->if_flags |= IFF_ALLMULTI; 484 goto allmulti; 485 } 486 /* 487 * Program the first XM_RXFILT_MAX multicast groups 488 * into the perfect filter. For all others, 489 * use the hash table. 490 */ 491 if (i < XM_RXFILT_MAX) { 492 sk_setfilt(sc_if, enm->enm_addrlo, i); 493 i++; 494 } 495 else { 496 h = sk_calchash(enm->enm_addrlo); 497 if (h < 32) 498 hashes[0] |= (1 << h); 499 else 500 hashes[1] |= (1 << (h - 32)); 501 } 502 503 ETHER_NEXT_MULTI(step, enm); 504 } 505 } 506 507 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 508 XM_MODE_RX_USE_PERFECT); 509 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 510 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 511 512 return; 513 } 514 515 int sk_init_rx_ring(sc_if) 516 struct sk_if_softc *sc_if; 517 { 518 struct sk_chain_data *cd; 519 struct sk_ring_data *rd; 520 int i; 521 522 cd = &sc_if->sk_cdata; 523 rd = sc_if->sk_rdata; 524 525 bzero((char *)rd->sk_rx_ring, 526 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 527 528 for (i = 0; i < SK_RX_RING_CNT; i++) { 529 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 530 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) { 531 printf("%s: failed alloc of %dth mbuf\n", 532 sc_if->sk_dev.dv_xname, i); 533 return(ENOBUFS); 534 } 535 if (i == (SK_RX_RING_CNT - 1)) { 536 cd->sk_rx_chain[i].sk_next = 537 &cd->sk_rx_chain[0]; 538 rd->sk_rx_ring[i].sk_next = 539 vtophys(&rd->sk_rx_ring[0]); 540 } else { 541 cd->sk_rx_chain[i].sk_next = 542 &cd->sk_rx_chain[i + 1]; 543 rd->sk_rx_ring[i].sk_next = 544 vtophys(&rd->sk_rx_ring[i + 1]); 545 } 546 } 547 548 sc_if->sk_cdata.sk_rx_prod = 0; 549 sc_if->sk_cdata.sk_rx_cons = 0; 550 551 return(0); 552 } 553 554 void sk_init_tx_ring(sc_if) 555 struct sk_if_softc *sc_if; 556 { 557 struct sk_chain_data *cd; 558 struct sk_ring_data *rd; 559 int i; 560 561 cd = &sc_if->sk_cdata; 562 rd = sc_if->sk_rdata; 563 564 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 565 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 566 567 for (i = 0; i < SK_TX_RING_CNT; i++) { 568 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 569 if (i == (SK_TX_RING_CNT - 1)) { 570 cd->sk_tx_chain[i].sk_next = 571 &cd->sk_tx_chain[0]; 572 rd->sk_tx_ring[i].sk_next = 573 vtophys(&rd->sk_tx_ring[0]); 574 } else { 575 cd->sk_tx_chain[i].sk_next = 576 &cd->sk_tx_chain[i + 1]; 577 rd->sk_tx_ring[i].sk_next = 578 vtophys(&rd->sk_tx_ring[i + 1]); 579 } 580 } 581 582 sc_if->sk_cdata.sk_tx_prod = 0; 583 sc_if->sk_cdata.sk_tx_cons = 0; 584 sc_if->sk_cdata.sk_tx_cnt = 0; 585 586 return; 587 } 588 589 int sk_newbuf(sc_if, c, m) 590 struct sk_if_softc *sc_if; 591 struct sk_chain *c; 592 struct mbuf *m; 593 { 594 struct mbuf *m_new = NULL; 595 struct sk_rx_desc *r; 596 597 if (m == NULL) { 598 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 599 if (m_new == NULL) { 600 printf("%s: no memory for rx list -- " 601 "packet dropped!\n", sc_if->sk_dev.dv_xname); 602 return(ENOBUFS); 603 } 604 605 /* Allocate the jumbo buffer */ 606 MCLGET(m_new, M_DONTWAIT); 607 if (!(m_new->m_flags & M_EXT)) { 608 m_freem(m_new); 609 return (ENOBUFS); 610 } 611 } else { 612 /* 613 * We're re-using a previously allocated mbuf; 614 * be sure to re-init pointers and lengths to 615 * default values. 616 */ 617 m_new = m; 618 m_new->m_data = m_new->m_ext.ext_buf; 619 } 620 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 621 622 /* 623 * Adjust alignment so packet payload begins on a 624 * longword boundary. Mandatory for Alpha, useful on 625 * x86 too. 626 */ 627 m_adj(m_new, ETHER_ALIGN); 628 629 r = c->sk_desc; 630 c->sk_mbuf = m_new; 631 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 632 r->sk_ctl = m_new->m_len | SK_RXSTAT; 633 634 return(0); 635 } 636 637 /* 638 * Set media options. 639 */ 640 int 641 sk_ifmedia_upd(ifp) 642 struct ifnet *ifp; 643 { 644 struct sk_if_softc *sc_if = ifp->if_softc; 645 646 sk_init(sc_if); 647 mii_mediachg(&sc_if->sk_mii); 648 return(0); 649 } 650 651 /* 652 * Report current media status. 653 */ 654 void 655 sk_ifmedia_sts(ifp, ifmr) 656 struct ifnet *ifp; 657 struct ifmediareq *ifmr; 658 { 659 struct sk_if_softc *sc_if = ifp->if_softc; 660 661 mii_pollstat(&sc_if->sk_mii); 662 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 663 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 664 } 665 666 int 667 sk_ioctl(ifp, command, data) 668 struct ifnet *ifp; 669 u_long command; 670 caddr_t data; 671 { 672 struct sk_if_softc *sc_if = ifp->if_softc; 673 struct ifreq *ifr = (struct ifreq *) data; 674 struct ifaddr *ifa = (struct ifaddr *) data; 675 struct mii_data *mii; 676 int s, error = 0; 677 678 s = splimp(); 679 680 if ((error = ether_ioctl(ifp, &sc_if->arpcom, command, data)) > 0) { 681 splx(s); 682 return error; 683 } 684 685 switch(command) { 686 case SIOCSIFADDR: 687 ifp->if_flags |= IFF_UP; 688 switch (ifa->ifa_addr->sa_family) { 689 #ifdef INET 690 case AF_INET: 691 sk_init(sc_if); 692 arp_ifinit(&sc_if->arpcom, ifa); 693 break; 694 #endif /* INET */ 695 default: 696 sk_init(sc_if); 697 break; 698 } 699 break; 700 case SIOCSIFFLAGS: 701 if (ifp->if_flags & IFF_UP) { 702 if (ifp->if_flags & IFF_RUNNING && 703 ifp->if_flags & IFF_PROMISC && 704 !(sc_if->sk_if_flags & IFF_PROMISC)) { 705 SK_XM_SETBIT_4(sc_if, XM_MODE, 706 XM_MODE_RX_PROMISC); 707 sk_setmulti(sc_if); 708 } else if (ifp->if_flags & IFF_RUNNING && 709 !(ifp->if_flags & IFF_PROMISC) && 710 sc_if->sk_if_flags & IFF_PROMISC) { 711 SK_XM_CLRBIT_4(sc_if, XM_MODE, 712 XM_MODE_RX_PROMISC); 713 sk_setmulti(sc_if); 714 } else 715 sk_init(sc_if); 716 } else { 717 if (ifp->if_flags & IFF_RUNNING) 718 sk_stop(sc_if); 719 } 720 sc_if->sk_if_flags = ifp->if_flags; 721 error = 0; 722 break; 723 case SIOCADDMULTI: 724 case SIOCDELMULTI: 725 error = (command == SIOCADDMULTI) ? 726 ether_addmulti(ifr, &sc_if->arpcom) : 727 ether_delmulti(ifr, &sc_if->arpcom); 728 729 if (error == ENETRESET) { 730 /* 731 * Multicast list has changed; set the hardware 732 * filter accordingly. 733 */ 734 sk_setmulti(sc_if); 735 error = 0; 736 } 737 break; 738 case SIOCGIFMEDIA: 739 case SIOCSIFMEDIA: 740 mii = &sc_if->sk_mii; 741 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 742 break; 743 default: 744 error = EINVAL; 745 break; 746 } 747 748 (void)splx(s); 749 750 return(error); 751 } 752 753 /* 754 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 755 * IDs against our list and return a device name if we find a match. 756 */ 757 int 758 skc_probe(parent, match, aux) 759 struct device *parent; 760 void *match, *aux; 761 { 762 struct pci_attach_args *pa = aux; 763 764 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SCHNEIDERKOCH) 765 return (0); 766 767 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_SCHNEIDERKOCH_GE) 768 return (0); 769 770 return (1); 771 } 772 773 /* 774 * Force the GEnesis into reset, then bring it out of reset. 775 */ 776 void sk_reset(sc) 777 struct sk_softc *sc; 778 { 779 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_RESET); 780 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_RESET); 781 DELAY(1000); 782 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_UNRESET); 783 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 784 785 /* Configure packet arbiter */ 786 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 787 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 788 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 789 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 790 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 791 792 /* Enable RAM interface */ 793 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 794 795 /* 796 * Configure interrupt moderation. The moderation timer 797 * defers interrupts specified in the interrupt moderation 798 * timer mask based on the timeout specified in the interrupt 799 * moderation timer init register. Each bit in the timer 800 * register represents 18.825ns, so to specify a timeout in 801 * microseconds, we have to multiply by 54. 802 */ 803 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 804 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 805 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 806 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 807 808 return; 809 } 810 811 int 812 sk_probe(parent, match, aux) 813 struct device *parent; 814 void *match, *aux; 815 { 816 struct skc_attach_args *sa = aux; 817 818 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 819 return(0); 820 821 return (1); 822 } 823 824 /* 825 * Each XMAC chip is attached as a separate logical IP interface. 826 * Single port cards will have only one logical interface of course. 827 */ 828 void 829 sk_attach(parent, self, aux) 830 struct device *parent, *self; 831 void *aux; 832 { 833 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 834 struct sk_softc *sc = (struct sk_softc *)parent; 835 struct skc_attach_args *sa = aux; 836 struct ifnet *ifp; 837 caddr_t kva; 838 bus_dma_segment_t seg; 839 bus_dmamap_t dmamap; 840 int i, rseg; 841 842 sc_if->sk_port = sa->skc_port; 843 sc_if->sk_softc = sc; 844 sc->sk_if[sa->skc_port] = sc_if; 845 846 if (sa->skc_port == SK_PORT_A) 847 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 848 if (sa->skc_port == SK_PORT_B) 849 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 850 851 /* 852 * Get station address for this interface. Note that 853 * dual port cards actually come with three station 854 * addresses: one for each port, plus an extra. The 855 * extra one is used by the SysKonnect driver software 856 * as a 'virtual' station address for when both ports 857 * are operating in failover mode. Currently we don't 858 * use this extra address. 859 */ 860 for (i = 0; i < ETHER_ADDR_LEN; i++) 861 sc_if->arpcom.ac_enaddr[i] = 862 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 863 864 865 printf(": address %s\n", 866 ether_sprintf(sc_if->arpcom.ac_enaddr)); 867 868 /* 869 * Set up RAM buffer addresses. The NIC will have a certain 870 * amount of SRAM on it, somewhere between 512K and 2MB. We 871 * need to divide this up a) between the transmitter and 872 * receiver and b) between the two XMACs, if this is a 873 * dual port NIC. Our algotithm is to divide up the memory 874 * evenly so that everyone gets a fair share. 875 */ 876 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 877 u_int32_t chunk, val; 878 879 chunk = sc->sk_ramsize / 2; 880 val = sc->sk_rboff / sizeof(u_int64_t); 881 sc_if->sk_rx_ramstart = val; 882 val += (chunk / sizeof(u_int64_t)); 883 sc_if->sk_rx_ramend = val - 1; 884 sc_if->sk_tx_ramstart = val; 885 val += (chunk / sizeof(u_int64_t)); 886 sc_if->sk_tx_ramend = val - 1; 887 } else { 888 u_int32_t chunk, val; 889 890 chunk = sc->sk_ramsize / 4; 891 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 892 sizeof(u_int64_t); 893 sc_if->sk_rx_ramstart = val; 894 val += (chunk / sizeof(u_int64_t)); 895 sc_if->sk_rx_ramend = val - 1; 896 sc_if->sk_tx_ramstart = val; 897 val += (chunk / sizeof(u_int64_t)); 898 sc_if->sk_tx_ramend = val - 1; 899 } 900 901 /* Read and save PHY type and set PHY address */ 902 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 903 switch (sc_if->sk_phytype) { 904 case SK_PHYTYPE_XMAC: 905 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 906 break; 907 case SK_PHYTYPE_BCOM: 908 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 909 break; 910 default: 911 printf("%s: unsupported PHY type: %d\n", 912 sc->sk_dev.dv_xname, sc_if->sk_phytype); 913 return; 914 } 915 916 /* Allocate the descriptor queues. */ 917 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 918 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 919 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 920 goto fail; 921 } 922 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 923 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 924 printf("%s: can't map dma buffers (%d bytes)\n", 925 sc_if->sk_dev.dv_xname, sizeof(struct sk_ring_data)); 926 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 927 goto fail; 928 } 929 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 930 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, &dmamap)) { 931 printf("%s: can't create dma map\n", sc_if->sk_dev.dv_xname); 932 bus_dmamem_unmap(sc->sc_dmatag, kva, 933 sizeof(struct sk_ring_data)); 934 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 935 goto fail; 936 } 937 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, 938 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 939 printf("%s: can't load dma map\n", sc_if->sk_dev.dv_xname); 940 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 941 bus_dmamem_unmap(sc->sc_dmatag, kva, 942 sizeof(struct sk_ring_data)); 943 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 944 goto fail; 945 } 946 sc_if->sk_rdata = (struct sk_ring_data *)kva; 947 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 948 949 ifp = &sc_if->arpcom.ac_if; 950 ifp->if_softc = sc_if; 951 ifp->if_mtu = ETHERMTU; 952 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 953 ifp->if_ioctl = sk_ioctl; 954 ifp->if_output = ether_output; 955 ifp->if_start = sk_start; 956 ifp->if_watchdog = sk_watchdog; 957 ifp->if_baudrate = 1000000000; 958 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1; 959 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 960 961 /* 962 * Do miibus setup. 963 */ 964 sk_init_xmac(sc_if); 965 sc_if->sk_mii.mii_ifp = ifp; 966 sc_if->sk_mii.mii_readreg = sk_miibus_readreg; 967 sc_if->sk_mii.mii_writereg = sk_miibus_writereg; 968 sc_if->sk_mii.mii_statchg = sk_miibus_statchg; 969 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 970 sk_ifmedia_upd, sk_ifmedia_sts); 971 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 972 MII_OFFSET_ANY, 0); 973 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 974 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 975 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 976 0, NULL); 977 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 978 } 979 else 980 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 981 982 timeout_set(&sc_if->sk_tick_ch, sk_tick, sc_if); 983 timeout_add(&sc_if->sk_tick_ch, hz); 984 985 /* 986 * Call MI attach routines. 987 */ 988 if_attach(ifp); 989 ether_ifattach(ifp); 990 991 return; 992 993 fail: 994 sc->sk_if[sa->skc_port] = NULL; 995 } 996 997 int 998 skcprint(aux, pnp) 999 void *aux; 1000 const char *pnp; 1001 { 1002 struct skc_attach_args *sa = aux; 1003 1004 if (pnp) 1005 printf("sk port %c at %s", 1006 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1007 else 1008 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1009 return (UNCONF); 1010 } 1011 1012 /* 1013 * Attach the interface. Allocate softc structures, do ifmedia 1014 * setup and ethernet/BPF attach. 1015 */ 1016 void 1017 skc_attach(parent, self, aux) 1018 struct device *parent, *self; 1019 void *aux; 1020 { 1021 struct sk_softc *sc = (struct sk_softc *)self; 1022 struct pci_attach_args *pa = aux; 1023 struct skc_attach_args skca; 1024 pci_chipset_tag_t pc = pa->pa_pc; 1025 pci_intr_handle_t ih; 1026 const char *intrstr = NULL; 1027 bus_addr_t iobase; 1028 bus_size_t iosize; 1029 int s; 1030 u_int32_t command; 1031 1032 s = splimp(); 1033 1034 /* 1035 * Handle power management nonsense. 1036 */ 1037 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1038 if (command == 0x01) { 1039 1040 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1041 if (command & SK_PSTATE_MASK) { 1042 u_int32_t iobase, membase, irq; 1043 1044 /* Save important PCI config data. */ 1045 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1046 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1047 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1048 1049 /* Reset the power state. */ 1050 printf("%s chip is in D%d power mode " 1051 "-- setting to D0\n", sc->sk_dev.dv_xname, 1052 command & SK_PSTATE_MASK); 1053 command &= 0xFFFFFFFC; 1054 pci_conf_write(pc, pa->pa_tag, 1055 SK_PCI_PWRMGMTCTRL, command); 1056 1057 /* Restore PCI config data. */ 1058 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1059 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1060 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1061 } 1062 } 1063 1064 /* 1065 * Map control/status registers. 1066 */ 1067 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1068 command |= PCI_COMMAND_IO_ENABLE | 1069 PCI_COMMAND_MEM_ENABLE | 1070 PCI_COMMAND_MASTER_ENABLE; 1071 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1072 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1073 1074 #ifdef SK_USEIOSPACE 1075 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1076 printf(": failed to enable I/O ports!\n"); 1077 goto fail; 1078 } 1079 /* 1080 * Map control/status registers. 1081 */ 1082 if (pci_io_find(pc, pa->pa_tag, SK_PCI_LOIO, &iobase, &iosize)) { 1083 printf(": can't find i/o space\n"); 1084 goto fail; 1085 } 1086 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->sk_bhandle)) { 1087 printf(": can't map i/o space\n"); 1088 goto fail; 1089 } 1090 sc->sk_btag = pa->pa_iot; 1091 #else 1092 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1093 printf(": failed to enable memory mapping!\n"); 1094 goto fail; 1095 } 1096 if (pci_mem_find(pc, pa->pa_tag, SK_PCI_LOMEM, &iobase, &iosize, NULL)){ 1097 printf(": can't find mem space\n"); 1098 goto fail; 1099 } 1100 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->sk_bhandle)) { 1101 printf(": can't map mem space\n"); 1102 goto fail; 1103 } 1104 sc->sk_btag = pa->pa_memt; 1105 #endif 1106 sc->sc_dmatag = pa->pa_dmat; 1107 1108 /* Allocate interrupt */ 1109 if (pci_intr_map(pa, &ih)) { 1110 printf(": couldn't map interrupt\n"); 1111 goto fail; 1112 } 1113 1114 intrstr = pci_intr_string(pc, ih); 1115 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc, 1116 self->dv_xname); 1117 if (sc->sk_intrhand == NULL) { 1118 printf(": couldn't establish interrupt"); 1119 if (intrstr != NULL) 1120 printf(" at %s", intrstr); 1121 goto fail; 1122 } 1123 printf(": %s\n", intrstr); 1124 1125 /* Reset the adapter. */ 1126 sk_reset(sc); 1127 1128 /* Read and save vital product data from EEPROM. */ 1129 sk_vpd_read(sc); 1130 1131 /* Read and save RAM size and RAMbuffer offset */ 1132 switch(sk_win_read_1(sc, SK_EPROM0)) { 1133 case SK_RAMSIZE_512K_64: 1134 sc->sk_ramsize = 0x80000; 1135 sc->sk_rboff = SK_RBOFF_0; 1136 break; 1137 case SK_RAMSIZE_1024K_64: 1138 sc->sk_ramsize = 0x100000; 1139 sc->sk_rboff = SK_RBOFF_80000; 1140 break; 1141 case SK_RAMSIZE_1024K_128: 1142 sc->sk_ramsize = 0x100000; 1143 sc->sk_rboff = SK_RBOFF_0; 1144 break; 1145 case SK_RAMSIZE_2048K_128: 1146 sc->sk_ramsize = 0x200000; 1147 sc->sk_rboff = SK_RBOFF_0; 1148 break; 1149 default: 1150 printf("%s: unknown ram size: %d\n", 1151 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_EPROM0)); 1152 goto fail; 1153 break; 1154 } 1155 1156 /* Read and save physical media type */ 1157 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1158 case SK_PMD_1000BASESX: 1159 sc->sk_pmd = IFM_1000_SX; 1160 break; 1161 case SK_PMD_1000BASELX: 1162 sc->sk_pmd = IFM_1000_LX; 1163 break; 1164 case SK_PMD_1000BASECX: 1165 sc->sk_pmd = IFM_1000_CX; 1166 break; 1167 case SK_PMD_1000BASETX: 1168 sc->sk_pmd = IFM_1000_TX; 1169 break; 1170 default: 1171 printf("%s: unknown media type: 0x%x\n", 1172 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1173 goto fail; 1174 } 1175 1176 /* Announce the product name. */ 1177 printf("%s: %s\n", sc->sk_dev.dv_xname, sc->sk_vpd_prodname); 1178 1179 skca.skc_port = SK_PORT_A; 1180 (void)config_found(&sc->sk_dev, &skca, skcprint); 1181 1182 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1183 skca.skc_port = SK_PORT_B; 1184 (void)config_found(&sc->sk_dev, &skca, skcprint); 1185 } 1186 1187 /* Turn on the 'driver is loaded' LED. */ 1188 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1189 1190 fail: 1191 splx(s); 1192 } 1193 1194 int sk_encap(sc_if, m_head, txidx) 1195 struct sk_if_softc *sc_if; 1196 struct mbuf *m_head; 1197 u_int32_t *txidx; 1198 { 1199 struct sk_tx_desc *f = NULL; 1200 struct mbuf *m; 1201 u_int32_t frag, cur, cnt = 0; 1202 1203 m = m_head; 1204 cur = frag = *txidx; 1205 1206 /* 1207 * Start packing the mbufs in this chain into 1208 * the fragment pointers. Stop when we run out 1209 * of fragments or hit the end of the mbuf chain. 1210 */ 1211 for (m = m_head; m != NULL; m = m->m_next) { 1212 if (m->m_len != 0) { 1213 if ((SK_TX_RING_CNT - 1214 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1215 return(ENOBUFS); 1216 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1217 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1218 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1219 if (cnt == 0) 1220 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1221 else 1222 f->sk_ctl |= SK_TXCTL_OWN; 1223 cur = frag; 1224 SK_INC(frag, SK_TX_RING_CNT); 1225 cnt++; 1226 } 1227 } 1228 1229 if (m != NULL) 1230 return(ENOBUFS); 1231 1232 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1233 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1234 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1235 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1236 sc_if->sk_cdata.sk_tx_cnt += cnt; 1237 1238 *txidx = frag; 1239 1240 return(0); 1241 } 1242 1243 void sk_start(ifp) 1244 struct ifnet *ifp; 1245 { 1246 struct sk_softc *sc; 1247 struct sk_if_softc *sc_if; 1248 struct mbuf *m_head = NULL; 1249 u_int32_t idx; 1250 1251 sc_if = ifp->if_softc; 1252 sc = sc_if->sk_softc; 1253 1254 idx = sc_if->sk_cdata.sk_tx_prod; 1255 1256 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1257 IF_DEQUEUE(&ifp->if_snd, m_head); 1258 if (m_head == NULL) 1259 break; 1260 1261 /* 1262 * Pack the data into the transmit ring. If we 1263 * don't have room, set the OACTIVE flag and wait 1264 * for the NIC to drain the ring. 1265 */ 1266 if (sk_encap(sc_if, m_head, &idx)) { 1267 IF_PREPEND(&ifp->if_snd, m_head); 1268 ifp->if_flags |= IFF_OACTIVE; 1269 break; 1270 } 1271 1272 /* 1273 * If there's a BPF listener, bounce a copy of this frame 1274 * to him. 1275 */ 1276 #if NBPFILTER > 0 1277 if (ifp->if_bpf) 1278 bpf_mtap(ifp->if_bpf, m_head); 1279 #endif 1280 } 1281 1282 /* Transmit */ 1283 sc_if->sk_cdata.sk_tx_prod = idx; 1284 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1285 1286 /* Set a timeout in case the chip goes out to lunch. */ 1287 ifp->if_timer = 5; 1288 1289 return; 1290 } 1291 1292 1293 void sk_watchdog(ifp) 1294 struct ifnet *ifp; 1295 { 1296 struct sk_if_softc *sc_if; 1297 1298 sc_if = ifp->if_softc; 1299 1300 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1301 sk_init(sc_if); 1302 1303 return; 1304 } 1305 1306 void sk_shutdown(v) 1307 void *v; 1308 { 1309 struct sk_softc *sc = v; 1310 1311 /* Turn off the 'driver is loaded' LED. */ 1312 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1313 1314 /* 1315 * Reset the GEnesis controller. Doing this should also 1316 * assert the resets on the attached XMAC(s). 1317 */ 1318 sk_reset(sc); 1319 1320 return; 1321 } 1322 1323 void sk_rxeof(sc_if) 1324 struct sk_if_softc *sc_if; 1325 { 1326 struct mbuf *m; 1327 struct ifnet *ifp; 1328 struct sk_chain *cur_rx; 1329 int total_len = 0; 1330 int i; 1331 u_int32_t rxstat; 1332 1333 ifp = &sc_if->arpcom.ac_if; 1334 i = sc_if->sk_cdata.sk_rx_prod; 1335 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1336 1337 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1338 1339 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1340 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1341 m = cur_rx->sk_mbuf; 1342 cur_rx->sk_mbuf = NULL; 1343 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1344 SK_INC(i, SK_RX_RING_CNT); 1345 1346 if (rxstat & XM_RXSTAT_ERRFRAME) { 1347 ifp->if_ierrors++; 1348 sk_newbuf(sc_if, cur_rx, m); 1349 continue; 1350 } 1351 1352 /* 1353 * Try to allocate a new jumbo buffer. If that 1354 * fails, copy the packet to mbufs and put the 1355 * jumbo buffer back in the ring so it can be 1356 * re-used. If allocating mbufs fails, then we 1357 * have to drop the packet. 1358 */ 1359 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1360 struct mbuf *m0; 1361 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1362 total_len + ETHER_ALIGN, 0, ifp, NULL); 1363 sk_newbuf(sc_if, cur_rx, m); 1364 if (m0 == NULL) { 1365 printf("%s: no receive buffers " 1366 "available -- packet dropped!\n", 1367 sc_if->sk_dev.dv_xname); 1368 ifp->if_ierrors++; 1369 continue; 1370 } 1371 m_adj(m0, ETHER_ALIGN); 1372 m = m0; 1373 } else { 1374 m->m_pkthdr.rcvif = ifp; 1375 m->m_pkthdr.len = m->m_len = total_len; 1376 } 1377 1378 ifp->if_ipackets++; 1379 1380 #if NBPFILTER > 0 1381 if (ifp->if_bpf) 1382 bpf_mtap(ifp->if_bpf, m); 1383 #endif 1384 /* pass it on. */ 1385 ether_input_mbuf(ifp, m); 1386 } 1387 1388 sc_if->sk_cdata.sk_rx_prod = i; 1389 1390 return; 1391 } 1392 1393 void sk_txeof(sc_if) 1394 struct sk_if_softc *sc_if; 1395 { 1396 struct sk_tx_desc *cur_tx = NULL; 1397 struct ifnet *ifp; 1398 u_int32_t idx; 1399 1400 ifp = &sc_if->arpcom.ac_if; 1401 1402 /* 1403 * Go through our tx ring and free mbufs for those 1404 * frames that have been sent. 1405 */ 1406 idx = sc_if->sk_cdata.sk_tx_cons; 1407 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1408 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1409 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1410 break; 1411 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1412 ifp->if_opackets++; 1413 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1414 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1415 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1416 } 1417 sc_if->sk_cdata.sk_tx_cnt--; 1418 SK_INC(idx, SK_TX_RING_CNT); 1419 ifp->if_timer = 0; 1420 } 1421 1422 sc_if->sk_cdata.sk_tx_cons = idx; 1423 1424 if (cur_tx != NULL) 1425 ifp->if_flags &= ~IFF_OACTIVE; 1426 1427 return; 1428 } 1429 1430 void 1431 sk_tick(xsc_if) 1432 void *xsc_if; 1433 { 1434 struct sk_if_softc *sc_if; 1435 struct mii_data *mii; 1436 struct ifnet *ifp; 1437 int i; 1438 1439 sc_if = xsc_if; 1440 ifp = &sc_if->arpcom.ac_if; 1441 mii = &sc_if->sk_mii; 1442 1443 if (!(ifp->if_flags & IFF_UP)) 1444 return; 1445 1446 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1447 sk_intr_bcom(sc_if); 1448 return; 1449 } 1450 1451 /* 1452 * According to SysKonnect, the correct way to verify that 1453 * the link has come back up is to poll bit 0 of the GPIO 1454 * register three times. This pin has the signal from the 1455 * link sync pin connected to it; if we read the same link 1456 * state 3 times in a row, we know the link is up. 1457 */ 1458 for (i = 0; i < 3; i++) { 1459 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1460 break; 1461 } 1462 1463 if (i != 3) { 1464 timeout_add(&sc_if->sk_tick_ch, hz); 1465 return; 1466 } 1467 1468 /* Turn the GP0 interrupt back on. */ 1469 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1470 SK_XM_READ_2(sc_if, XM_ISR); 1471 mii_tick(mii); 1472 mii_pollstat(mii); 1473 timeout_del(&sc_if->sk_tick_ch); 1474 } 1475 1476 void 1477 sk_intr_bcom(sc_if) 1478 struct sk_if_softc *sc_if; 1479 { 1480 struct sk_softc *sc; 1481 struct mii_data *mii; 1482 struct ifnet *ifp; 1483 int status; 1484 1485 sc = sc_if->sk_softc; 1486 mii = &sc_if->sk_mii; 1487 ifp = &sc_if->arpcom.ac_if; 1488 1489 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1490 1491 /* 1492 * Read the PHY interrupt register to make sure 1493 * we clear any pending interrupts. 1494 */ 1495 status = sk_miibus_readreg((struct device *)sc_if, 1496 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1497 1498 if (!(ifp->if_flags & IFF_RUNNING)) { 1499 sk_init_xmac(sc_if); 1500 return; 1501 } 1502 1503 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1504 int lstat; 1505 lstat = sk_miibus_readreg((struct device *)sc_if, 1506 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 1507 1508 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1509 mii_mediachg(mii); 1510 /* Turn off the link LED. */ 1511 SK_IF_WRITE_1(sc_if, 0, 1512 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1513 sc_if->sk_link = 0; 1514 } else if (status & BRGPHY_ISR_LNK_CHG) { 1515 sk_miibus_writereg((struct device *)sc_if, 1516 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 1517 mii_tick(mii); 1518 sc_if->sk_link = 1; 1519 /* Turn on the link LED. */ 1520 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1521 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1522 SK_LINKLED_BLINK_OFF); 1523 mii_pollstat(mii); 1524 } else { 1525 mii_tick(mii); 1526 timeout_add(&sc_if->sk_tick_ch, hz); 1527 } 1528 } 1529 1530 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1531 1532 return; 1533 } 1534 1535 void sk_intr_xmac(sc_if) 1536 struct sk_if_softc *sc_if; 1537 { 1538 struct sk_softc *sc; 1539 u_int16_t status; 1540 1541 sc = sc_if->sk_softc; 1542 status = SK_XM_READ_2(sc_if, XM_ISR); 1543 1544 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1545 if (status & XM_ISR_GP0_SET) { 1546 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1547 timeout_add(&sc_if->sk_tick_ch, hz); 1548 } 1549 1550 if (status & XM_ISR_AUTONEG_DONE) { 1551 timeout_add(&sc_if->sk_tick_ch, hz); 1552 } 1553 } 1554 1555 if (status & XM_IMR_TX_UNDERRUN) 1556 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1557 1558 if (status & XM_IMR_RX_OVERRUN) 1559 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1560 1561 return; 1562 } 1563 1564 int sk_intr(xsc) 1565 void *xsc; 1566 { 1567 struct sk_softc *sc = xsc; 1568 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 1569 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1570 u_int32_t status; 1571 int claimed = 0; 1572 1573 sc_if0 = sc->sk_if[SK_PORT_A]; 1574 sc_if1 = sc->sk_if[SK_PORT_B]; 1575 1576 if (sc_if0 != NULL) 1577 ifp0 = &sc_if0->arpcom.ac_if; 1578 if (sc_if1 != NULL) 1579 ifp1 = &sc_if1->arpcom.ac_if; 1580 1581 for (;;) { 1582 status = CSR_READ_4(sc, SK_ISSR); 1583 if (!(status & sc->sk_intrmask)) 1584 break; 1585 1586 claimed = 1; 1587 1588 /* Handle receive interrupts first. */ 1589 if (status & SK_ISR_RX1_EOF) { 1590 sk_rxeof(sc_if0); 1591 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1592 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1593 } 1594 if (status & SK_ISR_RX2_EOF) { 1595 sk_rxeof(sc_if1); 1596 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1597 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1598 } 1599 1600 /* Then transmit interrupts. */ 1601 if (status & SK_ISR_TX1_S_EOF) { 1602 sk_txeof(sc_if0); 1603 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1604 SK_TXBMU_CLR_IRQ_EOF); 1605 } 1606 if (status & SK_ISR_TX2_S_EOF) { 1607 sk_txeof(sc_if1); 1608 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1609 SK_TXBMU_CLR_IRQ_EOF); 1610 } 1611 1612 /* Then MAC interrupts. */ 1613 if (status & SK_ISR_MAC1 && 1614 ifp0->if_flags & IFF_RUNNING) 1615 sk_intr_xmac(sc_if0); 1616 1617 if (status & SK_ISR_MAC2 && 1618 ifp1->if_flags & IFF_RUNNING) 1619 sk_intr_xmac(sc_if1); 1620 1621 if (status & SK_ISR_EXTERNAL_REG) { 1622 if (ifp0 != NULL) 1623 sk_intr_bcom(sc_if0); 1624 if (ifp1 != NULL) 1625 sk_intr_bcom(sc_if1); 1626 } 1627 } 1628 1629 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1630 1631 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL) 1632 sk_start(ifp0); 1633 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL) 1634 sk_start(ifp1); 1635 1636 return (claimed); 1637 } 1638 1639 void sk_init_xmac(sc_if) 1640 struct sk_if_softc *sc_if; 1641 { 1642 struct sk_softc *sc; 1643 struct ifnet *ifp; 1644 struct sk_bcom_hack bhack[] = { 1645 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 1646 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 1647 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 1648 { 0, 0 } }; 1649 1650 sc = sc_if->sk_softc; 1651 ifp = &sc_if->arpcom.ac_if; 1652 1653 /* Unreset the XMAC. */ 1654 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 1655 DELAY(1000); 1656 1657 /* Reset the XMAC's internal state. */ 1658 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 1659 1660 /* Save the XMAC II revision */ 1661 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 1662 1663 /* 1664 * Perform additional initialization for external PHYs, 1665 * namely for the 1000baseTX cards that use the XMAC's 1666 * GMII mode. 1667 */ 1668 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1669 int i = 0; 1670 u_int32_t val; 1671 1672 /* Take PHY out of reset. */ 1673 val = sk_win_read_4(sc, SK_GPIO); 1674 if (sc_if->sk_port == SK_PORT_A) 1675 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 1676 else 1677 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 1678 sk_win_write_4(sc, SK_GPIO, val); 1679 1680 /* Enable GMII mode on the XMAC. */ 1681 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 1682 1683 sk_miibus_writereg((struct device *)sc_if, SK_PHYADDR_BCOM, 1684 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 1685 DELAY(10000); 1686 sk_miibus_writereg((struct device *)sc_if, SK_PHYADDR_BCOM, 1687 BRGPHY_MII_IMR, 0xFFF0); 1688 1689 /* 1690 * Early versions of the BCM5400 apparently have 1691 * a bug that requires them to have their reserved 1692 * registers initialized to some magic values. I don't 1693 * know what the numbers do, I'm just the messenger. 1694 */ 1695 if (sk_miibus_readreg((struct device *)sc_if, 1696 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 1697 while(bhack[i].reg) { 1698 sk_miibus_writereg((struct device *)sc_if, 1699 SK_PHYADDR_BCOM, bhack[i].reg, 1700 bhack[i].val); 1701 i++; 1702 } 1703 } 1704 } 1705 1706 /* Set station address */ 1707 SK_XM_WRITE_2(sc_if, XM_PAR0, 1708 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 1709 SK_XM_WRITE_2(sc_if, XM_PAR1, 1710 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 1711 SK_XM_WRITE_2(sc_if, XM_PAR2, 1712 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 1713 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 1714 1715 if (ifp->if_flags & IFF_PROMISC) { 1716 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1717 } else { 1718 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1719 } 1720 1721 if (ifp->if_flags & IFF_BROADCAST) { 1722 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 1723 } else { 1724 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 1725 } 1726 1727 /* We don't need the FCS appended to the packet. */ 1728 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 1729 1730 /* We want short frames padded to 60 bytes. */ 1731 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 1732 1733 /* 1734 * Enable the reception of all error frames. This is is 1735 * a necessary evil due to the design of the XMAC. The 1736 * XMAC's receive FIFO is only 8K in size, however jumbo 1737 * frames can be up to 9000 bytes in length. When bad 1738 * frame filtering is enabled, the XMAC's RX FIFO operates 1739 * in 'store and forward' mode. For this to work, the 1740 * entire frame has to fit into the FIFO, but that means 1741 * that jumbo frames larger than 8192 bytes will be 1742 * truncated. Disabling all bad frame filtering causes 1743 * the RX FIFO to operate in streaming mode, in which 1744 * case the XMAC will start transfering frames out of the 1745 * RX FIFO as soon as the FIFO threshold is reached. 1746 */ 1747 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 1748 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 1749 XM_MODE_RX_INRANGELEN); 1750 1751 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1752 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 1753 else 1754 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 1755 1756 /* 1757 * Bump up the transmit threshold. This helps hold off transmit 1758 * underruns when we're blasting traffic from both ports at once. 1759 */ 1760 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 1761 1762 /* Set multicast filter */ 1763 sk_setmulti(sc_if); 1764 1765 /* Clear and enable interrupts */ 1766 SK_XM_READ_2(sc_if, XM_ISR); 1767 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 1768 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 1769 else 1770 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 1771 1772 /* Configure MAC arbiter */ 1773 switch(sc_if->sk_xmac_rev) { 1774 case XM_XMAC_REV_B2: 1775 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 1776 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 1777 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 1778 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 1779 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 1780 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 1781 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 1782 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 1783 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 1784 break; 1785 case XM_XMAC_REV_C1: 1786 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 1787 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 1788 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 1789 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 1790 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 1791 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 1792 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 1793 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 1794 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 1795 break; 1796 default: 1797 break; 1798 } 1799 sk_win_write_2(sc, SK_MACARB_CTL, 1800 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 1801 1802 sc_if->sk_link = 1; 1803 1804 return; 1805 } 1806 1807 /* 1808 * Note that to properly initialize any part of the GEnesis chip, 1809 * you first have to take it out of reset mode. 1810 */ 1811 void sk_init(xsc) 1812 void *xsc; 1813 { 1814 struct sk_if_softc *sc_if = xsc; 1815 struct sk_softc *sc; 1816 struct ifnet *ifp; 1817 struct mii_data *mii; 1818 int s; 1819 1820 s = splimp(); 1821 1822 ifp = &sc_if->arpcom.ac_if; 1823 sc = sc_if->sk_softc; 1824 mii = &sc_if->sk_mii; 1825 1826 /* Cancel pending I/O and free all RX/TX buffers. */ 1827 sk_stop(sc_if); 1828 1829 /* Configure LINK_SYNC LED */ 1830 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 1831 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_ON); 1832 1833 /* Configure RX LED */ 1834 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_START); 1835 1836 /* Configure TX LED */ 1837 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_START); 1838 1839 /* Configure I2C registers */ 1840 1841 /* Configure XMAC(s) */ 1842 sk_init_xmac(sc_if); 1843 mii_mediachg(mii); 1844 1845 /* Configure MAC FIFOs */ 1846 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 1847 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 1848 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 1849 1850 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 1851 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 1852 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 1853 1854 /* Configure transmit arbiter(s) */ 1855 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 1856 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 1857 1858 /* Configure RAMbuffers */ 1859 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 1860 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 1861 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 1862 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 1863 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 1864 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 1865 1866 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 1867 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 1868 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 1869 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 1870 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 1871 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 1872 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 1873 1874 /* Configure BMUs */ 1875 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 1876 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 1877 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 1878 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 1879 1880 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 1881 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 1882 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 1883 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 1884 1885 /* Init descriptors */ 1886 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 1887 printf("%s: initialization failed: no " 1888 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 1889 sk_stop(sc_if); 1890 (void)splx(s); 1891 return; 1892 } 1893 sk_init_tx_ring(sc_if); 1894 1895 /* Configure interrupt handling */ 1896 CSR_READ_4(sc, SK_ISSR); 1897 if (sc_if->sk_port == SK_PORT_A) 1898 sc->sk_intrmask |= SK_INTRS1; 1899 else 1900 sc->sk_intrmask |= SK_INTRS2; 1901 1902 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 1903 1904 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1905 1906 /* Start BMUs. */ 1907 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 1908 1909 /* Enable XMACs TX and RX state machines */ 1910 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 1911 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1912 1913 ifp->if_flags |= IFF_RUNNING; 1914 ifp->if_flags &= ~IFF_OACTIVE; 1915 1916 splx(s); 1917 1918 return; 1919 } 1920 1921 void sk_stop(sc_if) 1922 struct sk_if_softc *sc_if; 1923 { 1924 int i; 1925 struct sk_softc *sc; 1926 struct ifnet *ifp; 1927 1928 sc = sc_if->sk_softc; 1929 ifp = &sc_if->arpcom.ac_if; 1930 1931 timeout_del(&sc_if->sk_tick_ch); 1932 1933 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1934 u_int32_t val; 1935 1936 /* Put PHY back into reset. */ 1937 val = sk_win_read_4(sc, SK_GPIO); 1938 if (sc_if->sk_port == SK_PORT_A) { 1939 val |= SK_GPIO_DIR0; 1940 val &= ~SK_GPIO_DAT0; 1941 } else { 1942 val |= SK_GPIO_DIR2; 1943 val &= ~SK_GPIO_DAT2; 1944 } 1945 sk_win_write_4(sc, SK_GPIO, val); 1946 } 1947 1948 /* Turn off various components of this interface. */ 1949 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 1950 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 1951 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 1952 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 1953 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 1954 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 1955 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 1956 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 1957 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 1958 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 1959 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 1960 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 1961 1962 /* Disable interrupts */ 1963 if (sc_if->sk_port == SK_PORT_A) 1964 sc->sk_intrmask &= ~SK_INTRS1; 1965 else 1966 sc->sk_intrmask &= ~SK_INTRS2; 1967 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1968 1969 SK_XM_READ_2(sc_if, XM_ISR); 1970 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 1971 1972 /* Free RX and TX mbufs still in the queues. */ 1973 for (i = 0; i < SK_RX_RING_CNT; i++) { 1974 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 1975 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 1976 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1977 } 1978 } 1979 1980 for (i = 0; i < SK_TX_RING_CNT; i++) { 1981 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 1982 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 1983 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1984 } 1985 } 1986 1987 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1988 1989 return; 1990 } 1991 1992 struct cfattach skc_ca = { 1993 sizeof(struct sk_softc), skc_probe, skc_attach, 1994 }; 1995 1996 struct cfdriver skc_cd = { 1997 0, "skc", DV_DULL 1998 }; 1999 2000 struct cfattach sk_ca = { 2001 sizeof(struct sk_if_softc), sk_probe, sk_attach, 2002 }; 2003 2004 struct cfdriver sk_cd = { 2005 0, "sk", DV_IFNET 2006 }; 2007