1 /* $OpenBSD: if_sk.c,v 1.169 2014/07/12 18:48:52 tedu Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include "bpfilter.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/timeout.h> 99 #include <sys/device.h> 100 #include <sys/queue.h> 101 102 #include <net/if.h> 103 #include <net/if_dl.h> 104 #include <net/if_types.h> 105 106 #ifdef INET 107 #include <netinet/in.h> 108 #include <netinet/in_systm.h> 109 #include <netinet/ip.h> 110 #include <netinet/udp.h> 111 #include <netinet/tcp.h> 112 #include <netinet/if_ether.h> 113 #endif 114 115 #include <net/if_media.h> 116 #include <net/if_vlan_var.h> 117 118 #if NBPFILTER > 0 119 #include <net/bpf.h> 120 #endif 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/brgphyreg.h> 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 #include <dev/pci/pcidevs.h> 129 130 #include <dev/pci/if_skreg.h> 131 #include <dev/pci/if_skvar.h> 132 133 int skc_probe(struct device *, void *, void *); 134 void skc_attach(struct device *, struct device *self, void *aux); 135 int skc_detach(struct device *, int); 136 int skc_activate(struct device *, int); 137 int sk_probe(struct device *, void *, void *); 138 void sk_attach(struct device *, struct device *self, void *aux); 139 int sk_detach(struct device *, int); 140 int sk_activate(struct device *, int); 141 int skcprint(void *, const char *); 142 int sk_intr(void *); 143 void sk_intr_bcom(struct sk_if_softc *); 144 void sk_intr_xmac(struct sk_if_softc *); 145 void sk_intr_yukon(struct sk_if_softc *); 146 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 147 void sk_rxeof(struct sk_if_softc *); 148 void sk_txeof(struct sk_if_softc *); 149 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 150 void sk_start(struct ifnet *); 151 int sk_ioctl(struct ifnet *, u_long, caddr_t); 152 void sk_init(void *); 153 void sk_init_xmac(struct sk_if_softc *); 154 void sk_init_yukon(struct sk_if_softc *); 155 void sk_stop(struct sk_if_softc *, int softonly); 156 void sk_watchdog(struct ifnet *); 157 int sk_ifmedia_upd(struct ifnet *); 158 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 159 void skc_reset(struct sk_softc *); 160 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 161 int sk_alloc_jumbo_mem(struct sk_if_softc *); 162 void *sk_jalloc(struct sk_if_softc *); 163 void sk_jfree(caddr_t, u_int, void *); 164 int sk_reset(struct sk_if_softc *); 165 int sk_init_rx_ring(struct sk_if_softc *); 166 int sk_init_tx_ring(struct sk_if_softc *); 167 168 int sk_xmac_miibus_readreg(struct device *, int, int); 169 void sk_xmac_miibus_writereg(struct device *, int, int, int); 170 void sk_xmac_miibus_statchg(struct device *); 171 172 int sk_marv_miibus_readreg(struct device *, int, int); 173 void sk_marv_miibus_writereg(struct device *, int, int, int); 174 void sk_marv_miibus_statchg(struct device *); 175 176 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 177 void sk_iff(struct sk_if_softc *); 178 void sk_iff_xmac(struct sk_if_softc *); 179 void sk_iff_yukon(struct sk_if_softc *); 180 181 void sk_tick(void *); 182 void sk_yukon_tick(void *); 183 184 #ifdef SK_DEBUG 185 #define DPRINTF(x) if (skdebug) printf x 186 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 187 int skdebug = 0; 188 189 void sk_dump_txdesc(struct sk_tx_desc *, int); 190 void sk_dump_mbuf(struct mbuf *); 191 void sk_dump_bytes(const char *, int); 192 #else 193 #define DPRINTF(x) 194 #define DPRINTFN(n,x) 195 #endif 196 197 /* supported device vendors */ 198 const struct pci_matchid skc_devices[] = { 199 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940 }, 200 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940B }, 201 { PCI_VENDOR_CNET, PCI_PRODUCT_CNET_GIGACARD }, 202 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_A1 }, 203 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_B1 }, 204 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064 }, 205 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON }, 206 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_BELKIN }, 207 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK98XX }, 208 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK98XX2 }, 209 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821 }, 210 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9843 } 211 }; 212 213 #define SK_LINKSYS_EG1032_SUBID 0x00151737 214 215 static inline u_int32_t 216 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 217 { 218 return CSR_READ_4(sc, reg); 219 } 220 221 static inline u_int16_t 222 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 223 { 224 return CSR_READ_2(sc, reg); 225 } 226 227 static inline u_int8_t 228 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 229 { 230 return CSR_READ_1(sc, reg); 231 } 232 233 static inline void 234 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 235 { 236 CSR_WRITE_4(sc, reg, x); 237 } 238 239 static inline void 240 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 241 { 242 CSR_WRITE_2(sc, reg, x); 243 } 244 245 static inline void 246 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 247 { 248 CSR_WRITE_1(sc, reg, x); 249 } 250 251 int 252 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 253 { 254 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 255 int i; 256 257 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 258 259 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 260 return (0); 261 262 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 263 SK_XM_READ_2(sc_if, XM_PHY_DATA); 264 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 265 for (i = 0; i < SK_TIMEOUT; i++) { 266 DELAY(1); 267 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 268 XM_MMUCMD_PHYDATARDY) 269 break; 270 } 271 272 if (i == SK_TIMEOUT) { 273 printf("%s: phy failed to come ready\n", 274 sc_if->sk_dev.dv_xname); 275 return (0); 276 } 277 } 278 DELAY(1); 279 return (SK_XM_READ_2(sc_if, XM_PHY_DATA)); 280 } 281 282 void 283 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 284 { 285 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 286 int i; 287 288 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 289 290 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 291 for (i = 0; i < SK_TIMEOUT; i++) { 292 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 293 break; 294 } 295 296 if (i == SK_TIMEOUT) { 297 printf("%s: phy failed to come ready\n", 298 sc_if->sk_dev.dv_xname); 299 return; 300 } 301 302 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 303 for (i = 0; i < SK_TIMEOUT; i++) { 304 DELAY(1); 305 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 306 break; 307 } 308 309 if (i == SK_TIMEOUT) 310 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 311 } 312 313 void 314 sk_xmac_miibus_statchg(struct device *dev) 315 { 316 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 317 struct mii_data *mii = &sc_if->sk_mii; 318 319 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 320 321 /* 322 * If this is a GMII PHY, manually set the XMAC's 323 * duplex mode accordingly. 324 */ 325 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 326 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 327 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 328 else 329 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 330 } 331 } 332 333 int 334 sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 335 { 336 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 337 u_int16_t val; 338 int i; 339 340 if (phy != 0 || 341 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 342 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 343 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 344 phy, reg)); 345 return (0); 346 } 347 348 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 349 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 350 351 for (i = 0; i < SK_TIMEOUT; i++) { 352 DELAY(1); 353 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 354 if (val & YU_SMICR_READ_VALID) 355 break; 356 } 357 358 if (i == SK_TIMEOUT) { 359 printf("%s: phy failed to come ready\n", 360 sc_if->sk_dev.dv_xname); 361 return (0); 362 } 363 364 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 365 SK_TIMEOUT)); 366 367 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 368 369 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 370 phy, reg, val)); 371 372 return (val); 373 } 374 375 void 376 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 377 { 378 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 379 int i; 380 381 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 382 phy, reg, val)); 383 384 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 385 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 386 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 387 388 for (i = 0; i < SK_TIMEOUT; i++) { 389 DELAY(1); 390 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 391 break; 392 } 393 394 if (i == SK_TIMEOUT) 395 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 396 } 397 398 void 399 sk_marv_miibus_statchg(struct device *dev) 400 { 401 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 402 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 403 } 404 405 void 406 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 407 { 408 int base = XM_RXFILT_ENTRY(slot); 409 410 SK_XM_WRITE_2(sc_if, base, letoh16(*(u_int16_t *)(&addr[0]))); 411 SK_XM_WRITE_2(sc_if, base + 2, letoh16(*(u_int16_t *)(&addr[2]))); 412 SK_XM_WRITE_2(sc_if, base + 4, letoh16(*(u_int16_t *)(&addr[4]))); 413 } 414 415 void 416 sk_iff(struct sk_if_softc *sc_if) 417 { 418 struct sk_softc *sc = sc_if->sk_softc; 419 420 if (SK_IS_GENESIS(sc)) 421 sk_iff_xmac(sc_if); 422 else 423 sk_iff_yukon(sc_if); 424 } 425 426 void 427 sk_iff_xmac(struct sk_if_softc *sc_if) 428 { 429 struct ifnet *ifp = &sc_if->arpcom.ac_if; 430 struct arpcom *ac = &sc_if->arpcom; 431 struct ether_multi *enm; 432 struct ether_multistep step; 433 u_int32_t reg, hashes[2]; 434 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 435 int h, i; 436 437 reg = SK_XM_READ_4(sc_if, XM_MODE); 438 reg &= ~(XM_MODE_RX_NOBROAD | XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH | 439 XM_MODE_RX_USE_PERFECT | XM_MODE_RX_USE_STATION); 440 ifp->if_flags &= ~IFF_ALLMULTI; 441 442 /* 443 * Always accept frames destined to our station address. 444 */ 445 reg |= XM_MODE_RX_USE_STATION; 446 447 /* don't use perfect filter. */ 448 for (i = 1; i < XM_RXFILT_MAX; i++) 449 sk_setfilt(sc_if, (caddr_t)&dummy, i); 450 451 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 452 ifp->if_flags |= IFF_ALLMULTI; 453 if (ifp->if_flags & IFF_PROMISC) 454 reg |= XM_MODE_RX_PROMISC; 455 else 456 reg |= XM_MODE_RX_USE_HASH; 457 hashes[0] = hashes[1] = 0xFFFFFFFF; 458 } else { 459 reg |= XM_MODE_RX_USE_HASH; 460 /* Program new filter. */ 461 bzero(hashes, sizeof(hashes)); 462 463 ETHER_FIRST_MULTI(step, ac, enm); 464 while (enm != NULL) { 465 h = ether_crc32_le(enm->enm_addrlo, 466 ETHER_ADDR_LEN) & ((1 << SK_HASH_BITS) - 1); 467 468 if (h < 32) 469 hashes[0] |= (1 << h); 470 else 471 hashes[1] |= (1 << (h - 32)); 472 473 ETHER_NEXT_MULTI(step, enm); 474 } 475 } 476 477 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 478 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 479 SK_XM_WRITE_4(sc_if, XM_MODE, reg); 480 } 481 482 void 483 sk_iff_yukon(struct sk_if_softc *sc_if) 484 { 485 struct ifnet *ifp = &sc_if->arpcom.ac_if; 486 struct arpcom *ac = &sc_if->arpcom; 487 struct ether_multi *enm; 488 struct ether_multistep step; 489 u_int32_t hashes[2]; 490 u_int16_t rcr; 491 int h; 492 493 rcr = SK_YU_READ_2(sc_if, YUKON_RCR); 494 rcr &= ~(YU_RCR_MUFLEN | YU_RCR_UFLEN); 495 ifp->if_flags &= ~IFF_ALLMULTI; 496 497 /* 498 * Always accept frames destined to our station address. 499 */ 500 rcr |= YU_RCR_UFLEN; 501 502 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 503 ifp->if_flags |= IFF_ALLMULTI; 504 if (ifp->if_flags & IFF_PROMISC) 505 rcr &= ~YU_RCR_UFLEN; 506 else 507 rcr |= YU_RCR_MUFLEN; 508 hashes[0] = hashes[1] = 0xFFFFFFFF; 509 } else { 510 rcr |= YU_RCR_MUFLEN; 511 /* Program new filter. */ 512 bzero(hashes, sizeof(hashes)); 513 514 ETHER_FIRST_MULTI(step, ac, enm); 515 while (enm != NULL) { 516 h = ether_crc32_be(enm->enm_addrlo, 517 ETHER_ADDR_LEN) & ((1 << SK_HASH_BITS) - 1); 518 519 if (h < 32) 520 hashes[0] |= (1 << h); 521 else 522 hashes[1] |= (1 << (h - 32)); 523 524 ETHER_NEXT_MULTI(step, enm); 525 } 526 } 527 528 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 529 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 530 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 531 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 532 SK_YU_WRITE_2(sc_if, YUKON_RCR, rcr); 533 } 534 535 int 536 sk_init_rx_ring(struct sk_if_softc *sc_if) 537 { 538 struct sk_chain_data *cd = &sc_if->sk_cdata; 539 struct sk_ring_data *rd = sc_if->sk_rdata; 540 int i, nexti; 541 542 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 543 544 for (i = 0; i < SK_RX_RING_CNT; i++) { 545 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 546 if (i == (SK_RX_RING_CNT - 1)) 547 nexti = 0; 548 else 549 nexti = i + 1; 550 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 551 rd->sk_rx_ring[i].sk_next = htole32(SK_RX_RING_ADDR(sc_if, nexti)); 552 } 553 554 for (i = 0; i < SK_RX_RING_CNT; i++) { 555 if (sk_newbuf(sc_if, i, NULL, 556 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 557 printf("%s: failed alloc of %dth mbuf\n", 558 sc_if->sk_dev.dv_xname, i); 559 return (ENOBUFS); 560 } 561 } 562 563 sc_if->sk_cdata.sk_rx_prod = 0; 564 sc_if->sk_cdata.sk_rx_cons = 0; 565 566 return (0); 567 } 568 569 int 570 sk_init_tx_ring(struct sk_if_softc *sc_if) 571 { 572 struct sk_softc *sc = sc_if->sk_softc; 573 struct sk_chain_data *cd = &sc_if->sk_cdata; 574 struct sk_ring_data *rd = sc_if->sk_rdata; 575 bus_dmamap_t dmamap; 576 struct sk_txmap_entry *entry; 577 int i, nexti; 578 579 bzero(sc_if->sk_rdata->sk_tx_ring, 580 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 581 582 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 583 for (i = 0; i < SK_TX_RING_CNT; i++) { 584 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 585 if (i == (SK_TX_RING_CNT - 1)) 586 nexti = 0; 587 else 588 nexti = i + 1; 589 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 590 rd->sk_tx_ring[i].sk_next = htole32(SK_TX_RING_ADDR(sc_if, nexti)); 591 592 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 593 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 594 return (ENOBUFS); 595 596 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 597 if (!entry) { 598 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 599 return (ENOBUFS); 600 } 601 entry->dmamap = dmamap; 602 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 603 } 604 605 sc_if->sk_cdata.sk_tx_prod = 0; 606 sc_if->sk_cdata.sk_tx_cons = 0; 607 sc_if->sk_cdata.sk_tx_cnt = 0; 608 609 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 610 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 611 612 return (0); 613 } 614 615 int 616 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 617 bus_dmamap_t dmamap) 618 { 619 struct mbuf *m_new = NULL; 620 struct sk_chain *c; 621 struct sk_rx_desc *r; 622 623 if (m == NULL) { 624 caddr_t buf = NULL; 625 626 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 627 if (m_new == NULL) 628 return (ENOBUFS); 629 630 /* Allocate the jumbo buffer */ 631 buf = sk_jalloc(sc_if); 632 if (buf == NULL) { 633 m_freem(m_new); 634 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 635 "dropped!\n", sc_if->arpcom.ac_if.if_xname)); 636 return (ENOBUFS); 637 } 638 639 /* Attach the buffer to the mbuf */ 640 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 641 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 642 } else { 643 /* 644 * We're re-using a previously allocated mbuf; 645 * be sure to re-init pointers and lengths to 646 * default values. 647 */ 648 m_new = m; 649 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 650 m_new->m_data = m_new->m_ext.ext_buf; 651 } 652 m_adj(m_new, ETHER_ALIGN); 653 654 c = &sc_if->sk_cdata.sk_rx_chain[i]; 655 r = c->sk_desc; 656 c->sk_mbuf = m_new; 657 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 658 (((vaddr_t)m_new->m_data 659 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 660 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 661 662 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 663 664 return (0); 665 } 666 667 /* 668 * Memory management for jumbo frames. 669 */ 670 671 int 672 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 673 { 674 struct sk_softc *sc = sc_if->sk_softc; 675 caddr_t ptr, kva; 676 bus_dma_segment_t seg; 677 int i, rseg, state, error; 678 struct sk_jpool_entry *entry; 679 680 state = error = 0; 681 682 /* Grab a big chunk o' storage. */ 683 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 684 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 685 printf(": can't alloc rx buffers"); 686 return (ENOBUFS); 687 } 688 689 state = 1; 690 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, &kva, 691 BUS_DMA_NOWAIT)) { 692 printf(": can't map dma buffers (%d bytes)", SK_JMEM); 693 error = ENOBUFS; 694 goto out; 695 } 696 697 state = 2; 698 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 699 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 700 printf(": can't create dma map"); 701 error = ENOBUFS; 702 goto out; 703 } 704 705 state = 3; 706 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 707 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 708 printf(": can't load dma map"); 709 error = ENOBUFS; 710 goto out; 711 } 712 713 state = 4; 714 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 715 DPRINTFN(1,("sk_jumbo_buf = 0x%08X\n", sc_if->sk_cdata.sk_jumbo_buf)); 716 717 LIST_INIT(&sc_if->sk_jfree_listhead); 718 LIST_INIT(&sc_if->sk_jinuse_listhead); 719 720 /* 721 * Now divide it up into 9K pieces and save the addresses 722 * in an array. 723 */ 724 ptr = sc_if->sk_cdata.sk_jumbo_buf; 725 for (i = 0; i < SK_JSLOTS; i++) { 726 sc_if->sk_cdata.sk_jslots[i] = ptr; 727 ptr += SK_JLEN; 728 entry = malloc(sizeof(struct sk_jpool_entry), 729 M_DEVBUF, M_NOWAIT); 730 if (entry == NULL) { 731 sc_if->sk_cdata.sk_jumbo_buf = NULL; 732 printf(": no memory for jumbo buffer queue!"); 733 error = ENOBUFS; 734 goto out; 735 } 736 entry->slot = i; 737 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 738 entry, jpool_entries); 739 } 740 out: 741 if (error != 0) { 742 switch (state) { 743 case 4: 744 bus_dmamap_unload(sc->sc_dmatag, 745 sc_if->sk_cdata.sk_rx_jumbo_map); 746 case 3: 747 bus_dmamap_destroy(sc->sc_dmatag, 748 sc_if->sk_cdata.sk_rx_jumbo_map); 749 case 2: 750 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 751 case 1: 752 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 753 break; 754 default: 755 break; 756 } 757 } 758 759 return (error); 760 } 761 762 /* 763 * Allocate a jumbo buffer. 764 */ 765 void * 766 sk_jalloc(struct sk_if_softc *sc_if) 767 { 768 struct sk_jpool_entry *entry; 769 770 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 771 772 if (entry == NULL) 773 return (NULL); 774 775 LIST_REMOVE(entry, jpool_entries); 776 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 777 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 778 } 779 780 /* 781 * Release a jumbo buffer. 782 */ 783 void 784 sk_jfree(caddr_t buf, u_int size, void *arg) 785 { 786 struct sk_jpool_entry *entry; 787 struct sk_if_softc *sc; 788 int i; 789 790 /* Extract the softc struct pointer. */ 791 sc = (struct sk_if_softc *)arg; 792 793 if (sc == NULL) 794 panic("sk_jfree: can't find softc pointer!"); 795 796 /* calculate the slot this buffer belongs to */ 797 i = ((vaddr_t)buf 798 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 799 800 if ((i < 0) || (i >= SK_JSLOTS)) 801 panic("sk_jfree: asked to free buffer that we don't manage!"); 802 803 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 804 if (entry == NULL) 805 panic("sk_jfree: buffer not in use!"); 806 entry->slot = i; 807 LIST_REMOVE(entry, jpool_entries); 808 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 809 } 810 811 /* 812 * Set media options. 813 */ 814 int 815 sk_ifmedia_upd(struct ifnet *ifp) 816 { 817 struct sk_if_softc *sc_if = ifp->if_softc; 818 819 mii_mediachg(&sc_if->sk_mii); 820 return (0); 821 } 822 823 /* 824 * Report current media status. 825 */ 826 void 827 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 828 { 829 struct sk_if_softc *sc_if = ifp->if_softc; 830 831 mii_pollstat(&sc_if->sk_mii); 832 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 833 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 834 } 835 836 int 837 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 838 { 839 struct sk_if_softc *sc_if = ifp->if_softc; 840 struct ifaddr *ifa = (struct ifaddr *) data; 841 struct ifreq *ifr = (struct ifreq *) data; 842 struct mii_data *mii; 843 int s, error = 0; 844 845 s = splnet(); 846 847 switch(command) { 848 case SIOCSIFADDR: 849 ifp->if_flags |= IFF_UP; 850 if (!(ifp->if_flags & IFF_RUNNING)) 851 sk_init(sc_if); 852 #ifdef INET 853 if (ifa->ifa_addr->sa_family == AF_INET) 854 arp_ifinit(&sc_if->arpcom, ifa); 855 #endif 856 break; 857 858 case SIOCSIFFLAGS: 859 if (ifp->if_flags & IFF_UP) { 860 if (ifp->if_flags & IFF_RUNNING) 861 error = ENETRESET; 862 else 863 sk_init(sc_if); 864 } else { 865 if (ifp->if_flags & IFF_RUNNING) 866 sk_stop(sc_if, 0); 867 } 868 break; 869 870 case SIOCGIFMEDIA: 871 case SIOCSIFMEDIA: 872 mii = &sc_if->sk_mii; 873 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 874 break; 875 876 default: 877 error = ether_ioctl(ifp, &sc_if->arpcom, command, data); 878 } 879 880 if (error == ENETRESET) { 881 if (ifp->if_flags & IFF_RUNNING) 882 sk_iff(sc_if); 883 error = 0; 884 } 885 886 splx(s); 887 return (error); 888 } 889 890 /* 891 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 892 * IDs against our list and return a device name if we find a match. 893 */ 894 int 895 skc_probe(struct device *parent, void *match, void *aux) 896 { 897 struct pci_attach_args *pa = aux; 898 pci_chipset_tag_t pc = pa->pa_pc; 899 pcireg_t subid; 900 901 subid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 902 903 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 904 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 905 subid == SK_LINKSYS_EG1032_SUBID) 906 return (1); 907 908 return (pci_matchbyid((struct pci_attach_args *)aux, skc_devices, 909 nitems(skc_devices))); 910 } 911 912 /* 913 * Force the GEnesis into reset, then bring it out of reset. 914 */ 915 void 916 skc_reset(struct sk_softc *sc) 917 { 918 u_int32_t imtimer_ticks; 919 920 DPRINTFN(2, ("skc_reset\n")); 921 922 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 923 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 924 if (SK_IS_YUKON(sc)) 925 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 926 927 DELAY(1000); 928 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 929 DELAY(2); 930 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 931 if (SK_IS_YUKON(sc)) 932 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 933 934 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 935 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 936 CSR_READ_2(sc, SK_LINK_CTRL))); 937 938 if (SK_IS_GENESIS(sc)) { 939 /* Configure packet arbiter */ 940 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 941 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 942 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 943 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 944 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 945 } 946 947 /* Enable RAM interface */ 948 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 949 950 /* 951 * Configure interrupt moderation. The moderation timer 952 * defers interrupts specified in the interrupt moderation 953 * timer mask based on the timeout specified in the interrupt 954 * moderation timer init register. Each bit in the timer 955 * register represents one tick, so to specify a timeout in 956 * microseconds, we have to multiply by the correct number of 957 * ticks-per-microsecond. 958 */ 959 switch (sc->sk_type) { 960 case SK_GENESIS: 961 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 962 break; 963 default: 964 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 965 break; 966 } 967 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(100)); 968 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 969 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 970 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 971 } 972 973 int 974 sk_probe(struct device *parent, void *match, void *aux) 975 { 976 struct skc_attach_args *sa = aux; 977 978 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 979 return (0); 980 981 switch (sa->skc_type) { 982 case SK_GENESIS: 983 case SK_YUKON: 984 case SK_YUKON_LITE: 985 case SK_YUKON_LP: 986 return (1); 987 } 988 989 return (0); 990 } 991 992 /* 993 * Each XMAC chip is attached as a separate logical IP interface. 994 * Single port cards will have only one logical interface of course. 995 */ 996 void 997 sk_attach(struct device *parent, struct device *self, void *aux) 998 { 999 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1000 struct sk_softc *sc = (struct sk_softc *)parent; 1001 struct skc_attach_args *sa = aux; 1002 struct ifnet *ifp; 1003 caddr_t kva; 1004 int i; 1005 1006 sc_if->sk_port = sa->skc_port; 1007 sc_if->sk_softc = sc; 1008 sc->sk_if[sa->skc_port] = sc_if; 1009 1010 if (sa->skc_port == SK_PORT_A) 1011 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1012 if (sa->skc_port == SK_PORT_B) 1013 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1014 1015 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1016 1017 /* 1018 * Get station address for this interface. Note that 1019 * dual port cards actually come with three station 1020 * addresses: one for each port, plus an extra. The 1021 * extra one is used by the SysKonnect driver software 1022 * as a 'virtual' station address for when both ports 1023 * are operating in failover mode. Currently we don't 1024 * use this extra address. 1025 */ 1026 for (i = 0; i < ETHER_ADDR_LEN; i++) 1027 sc_if->arpcom.ac_enaddr[i] = 1028 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1029 1030 printf(": address %s\n", 1031 ether_sprintf(sc_if->arpcom.ac_enaddr)); 1032 1033 /* 1034 * Set up RAM buffer addresses. The NIC will have a certain 1035 * amount of SRAM on it, somewhere between 512K and 2MB. We 1036 * need to divide this up a) between the transmitter and 1037 * receiver and b) between the two XMACs, if this is a 1038 * dual port NIC. Our algorithm is to divide up the memory 1039 * evenly so that everyone gets a fair share. 1040 */ 1041 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1042 u_int32_t chunk, val; 1043 1044 chunk = sc->sk_ramsize / 2; 1045 val = sc->sk_rboff / sizeof(u_int64_t); 1046 sc_if->sk_rx_ramstart = val; 1047 val += (chunk / sizeof(u_int64_t)); 1048 sc_if->sk_rx_ramend = val - 1; 1049 sc_if->sk_tx_ramstart = val; 1050 val += (chunk / sizeof(u_int64_t)); 1051 sc_if->sk_tx_ramend = val - 1; 1052 } else { 1053 u_int32_t chunk, val; 1054 1055 chunk = sc->sk_ramsize / 4; 1056 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1057 sizeof(u_int64_t); 1058 sc_if->sk_rx_ramstart = val; 1059 val += (chunk / sizeof(u_int64_t)); 1060 sc_if->sk_rx_ramend = val - 1; 1061 sc_if->sk_tx_ramstart = val; 1062 val += (chunk / sizeof(u_int64_t)); 1063 sc_if->sk_tx_ramend = val - 1; 1064 } 1065 1066 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1067 " tx_ramstart=%#x tx_ramend=%#x\n", 1068 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1069 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1070 1071 /* Read and save PHY type */ 1072 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1073 1074 /* Set PHY address */ 1075 if (SK_IS_GENESIS(sc)) { 1076 switch (sc_if->sk_phytype) { 1077 case SK_PHYTYPE_XMAC: 1078 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1079 break; 1080 case SK_PHYTYPE_BCOM: 1081 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1082 break; 1083 default: 1084 printf("%s: unsupported PHY type: %d\n", 1085 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1086 return; 1087 } 1088 } 1089 1090 if (SK_IS_YUKON(sc)) { 1091 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1092 sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) { 1093 /* not initialized, punt */ 1094 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1095 1096 sc->sk_coppertype = 1; 1097 } 1098 1099 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1100 1101 if (!(sc->sk_coppertype)) 1102 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 1103 } 1104 1105 /* Allocate the descriptor queues. */ 1106 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1107 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1108 BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 1109 printf(": can't alloc rx buffers\n"); 1110 goto fail; 1111 } 1112 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg, 1113 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1114 printf(": can't map dma buffers (%lu bytes)\n", 1115 (ulong)sizeof(struct sk_ring_data)); 1116 goto fail_1; 1117 } 1118 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1119 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1120 &sc_if->sk_ring_map)) { 1121 printf(": can't create dma map\n"); 1122 goto fail_2; 1123 } 1124 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1125 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1126 printf(": can't load dma map\n"); 1127 goto fail_3; 1128 } 1129 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1130 1131 /* Try to allocate memory for jumbo buffers. */ 1132 if (sk_alloc_jumbo_mem(sc_if)) { 1133 printf(": jumbo buffer allocation failed\n"); 1134 goto fail_3; 1135 } 1136 1137 ifp = &sc_if->arpcom.ac_if; 1138 ifp->if_softc = sc_if; 1139 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1140 ifp->if_ioctl = sk_ioctl; 1141 ifp->if_start = sk_start; 1142 ifp->if_watchdog = sk_watchdog; 1143 ifp->if_hardmtu = SK_JUMBO_MTU; 1144 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1145 IFQ_SET_READY(&ifp->if_snd); 1146 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1147 1148 ifp->if_capabilities = IFCAP_VLAN_MTU; 1149 1150 if (sk_reset(sc_if) == -1) { 1151 printf(": unknown device type %d\n", sc_if->sk_softc->sk_type); 1152 /* dealloc jumbo on error */ 1153 goto fail_3; 1154 } 1155 1156 DPRINTFN(2, ("sk_attach: 1\n")); 1157 1158 sc_if->sk_mii.mii_ifp = ifp; 1159 if (SK_IS_GENESIS(sc)) { 1160 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1161 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1162 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1163 } else { 1164 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1165 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1166 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1167 } 1168 1169 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1170 sk_ifmedia_upd, sk_ifmedia_sts); 1171 if (SK_IS_GENESIS(sc)) { 1172 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1173 MII_OFFSET_ANY, 0); 1174 } else { 1175 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1176 MII_OFFSET_ANY, MIIF_DOPAUSE); 1177 } 1178 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1179 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1180 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1181 0, NULL); 1182 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1183 } else 1184 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1185 1186 if (SK_IS_GENESIS(sc)) { 1187 timeout_set(&sc_if->sk_tick_ch, sk_tick, sc_if); 1188 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1189 } else 1190 timeout_set(&sc_if->sk_tick_ch, sk_yukon_tick, sc_if); 1191 1192 /* 1193 * Call MI attach routines. 1194 */ 1195 if_attach(ifp); 1196 ether_ifattach(ifp); 1197 1198 DPRINTFN(2, ("sk_attach: end\n")); 1199 return; 1200 1201 fail_2: 1202 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct sk_ring_data)); 1203 fail_1: 1204 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1205 fail_3: 1206 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1207 fail: 1208 sc->sk_if[sa->skc_port] = NULL; 1209 } 1210 1211 int 1212 sk_reset(struct sk_if_softc *sc_if) 1213 { 1214 /* 1215 * Do miibus setup. 1216 */ 1217 switch (sc_if->sk_softc->sk_type) { 1218 case SK_GENESIS: 1219 sk_init_xmac(sc_if); 1220 break; 1221 case SK_YUKON: 1222 case SK_YUKON_LITE: 1223 case SK_YUKON_LP: 1224 sk_init_yukon(sc_if); 1225 break; 1226 default: 1227 return (-1); 1228 } 1229 return (0); 1230 } 1231 1232 int 1233 sk_detach(struct device *self, int flags) 1234 { 1235 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 1236 struct sk_softc *sc = sc_if->sk_softc; 1237 struct ifnet *ifp= &sc_if->arpcom.ac_if; 1238 1239 if (sc->sk_if[sc_if->sk_port] == NULL) 1240 return (0); 1241 1242 sk_stop(sc_if, 1); 1243 1244 /* Detach any PHYs we might have. */ 1245 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1246 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1247 1248 /* Delete any remaining media. */ 1249 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1250 1251 ether_ifdetach(ifp); 1252 if_detach(ifp); 1253 1254 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc_if->sk_rdata, 1255 sizeof(struct sk_ring_data)); 1256 bus_dmamem_free(sc->sc_dmatag, 1257 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1258 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1259 sc->sk_if[sc_if->sk_port] = NULL; 1260 1261 return (0); 1262 } 1263 1264 int 1265 sk_activate(struct device *self, int act) 1266 { 1267 struct sk_if_softc *sc_if = (void *)self; 1268 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1269 int rv = 0; 1270 1271 switch (act) { 1272 case DVACT_RESUME: 1273 sk_reset(sc_if); 1274 if (ifp->if_flags & IFF_RUNNING) 1275 sk_init(sc_if); 1276 break; 1277 default: 1278 rv = config_activate_children(self, act); 1279 break; 1280 } 1281 return (rv); 1282 } 1283 1284 int 1285 skcprint(void *aux, const char *pnp) 1286 { 1287 struct skc_attach_args *sa = aux; 1288 1289 if (pnp) 1290 printf("sk port %c at %s", 1291 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1292 else 1293 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1294 return (UNCONF); 1295 } 1296 1297 /* 1298 * Attach the interface. Allocate softc structures, do ifmedia 1299 * setup and ethernet/BPF attach. 1300 */ 1301 void 1302 skc_attach(struct device *parent, struct device *self, void *aux) 1303 { 1304 struct sk_softc *sc = (struct sk_softc *)self; 1305 struct pci_attach_args *pa = aux; 1306 struct skc_attach_args skca; 1307 pci_chipset_tag_t pc = pa->pa_pc; 1308 pcireg_t memtype; 1309 pci_intr_handle_t ih; 1310 const char *intrstr = NULL; 1311 u_int8_t skrs; 1312 char *revstr = NULL; 1313 1314 DPRINTFN(2, ("begin skc_attach\n")); 1315 1316 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 1317 1318 /* 1319 * Map control/status registers. 1320 */ 1321 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1322 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1323 &sc->sk_bhandle, NULL, &sc->sk_bsize, 0)) { 1324 printf(": can't map mem space\n"); 1325 return; 1326 } 1327 1328 sc->sc_dmatag = pa->pa_dmat; 1329 1330 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1331 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1332 sc->sk_pc = pc; 1333 1334 /* bail out here if chip is not recognized */ 1335 if (! SK_IS_GENESIS(sc) && ! SK_IS_YUKON(sc)) { 1336 printf(": unknown chip type: %d\n", sc->sk_type); 1337 goto fail_1; 1338 } 1339 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1340 1341 /* Allocate interrupt */ 1342 if (pci_intr_map(pa, &ih)) { 1343 printf(": couldn't map interrupt\n"); 1344 goto fail_1; 1345 } 1346 1347 intrstr = pci_intr_string(pc, ih); 1348 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc, 1349 self->dv_xname); 1350 if (sc->sk_intrhand == NULL) { 1351 printf(": couldn't establish interrupt"); 1352 if (intrstr != NULL) 1353 printf(" at %s", intrstr); 1354 printf("\n"); 1355 goto fail_1; 1356 } 1357 1358 /* Reset the adapter. */ 1359 skc_reset(sc); 1360 1361 skrs = sk_win_read_1(sc, SK_EPROM0); 1362 if (SK_IS_GENESIS(sc)) { 1363 /* Read and save RAM size and RAMbuffer offset */ 1364 switch(skrs) { 1365 case SK_RAMSIZE_512K_64: 1366 sc->sk_ramsize = 0x80000; 1367 sc->sk_rboff = SK_RBOFF_0; 1368 break; 1369 case SK_RAMSIZE_1024K_64: 1370 sc->sk_ramsize = 0x100000; 1371 sc->sk_rboff = SK_RBOFF_80000; 1372 break; 1373 case SK_RAMSIZE_1024K_128: 1374 sc->sk_ramsize = 0x100000; 1375 sc->sk_rboff = SK_RBOFF_0; 1376 break; 1377 case SK_RAMSIZE_2048K_128: 1378 sc->sk_ramsize = 0x200000; 1379 sc->sk_rboff = SK_RBOFF_0; 1380 break; 1381 default: 1382 printf(": unknown ram size: %d\n", skrs); 1383 goto fail_2; 1384 break; 1385 } 1386 } else { 1387 if (skrs == 0x00) 1388 sc->sk_ramsize = 0x20000; 1389 else 1390 sc->sk_ramsize = skrs * (1<<12); 1391 sc->sk_rboff = SK_RBOFF_0; 1392 } 1393 1394 DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n", 1395 sc->sk_ramsize, sc->sk_ramsize / 1024, 1396 sc->sk_rboff)); 1397 1398 /* Read and save physical media type */ 1399 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1400 1401 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1') 1402 sc->sk_coppertype = 1; 1403 else 1404 sc->sk_coppertype = 0; 1405 1406 switch (sc->sk_type) { 1407 case SK_GENESIS: 1408 sc->sk_name = "GEnesis"; 1409 break; 1410 case SK_YUKON: 1411 sc->sk_name = "Yukon"; 1412 break; 1413 case SK_YUKON_LITE: 1414 sc->sk_name = "Yukon Lite"; 1415 break; 1416 case SK_YUKON_LP: 1417 sc->sk_name = "Yukon LP"; 1418 break; 1419 default: 1420 sc->sk_name = "Yukon (Unknown)"; 1421 } 1422 1423 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1424 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1425 u_int32_t flashaddr; 1426 u_int8_t testbyte; 1427 1428 flashaddr = sk_win_read_4(sc, SK_EP_ADDR); 1429 1430 /* test Flash-Address Register */ 1431 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff); 1432 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1433 1434 if (testbyte != 0) { 1435 /* This is a Yukon Lite Rev A0 */ 1436 sc->sk_type = SK_YUKON_LITE; 1437 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1438 /* restore Flash-Address Register */ 1439 sk_win_write_4(sc, SK_EP_ADDR, flashaddr); 1440 } 1441 } 1442 1443 if (sc->sk_type == SK_YUKON_LITE) { 1444 switch (sc->sk_rev) { 1445 case SK_YUKON_LITE_REV_A0: 1446 revstr = "A0"; 1447 break; 1448 case SK_YUKON_LITE_REV_A1: 1449 revstr = "A1"; 1450 break; 1451 case SK_YUKON_LITE_REV_A3: 1452 revstr = "A3"; 1453 break; 1454 default: 1455 ; 1456 } 1457 } 1458 1459 /* Announce the product name. */ 1460 printf(", %s", sc->sk_name); 1461 if (revstr != NULL) 1462 printf(" rev. %s", revstr); 1463 printf(" (0x%x): %s\n", sc->sk_rev, intrstr); 1464 1465 sc->sk_macs = 1; 1466 1467 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) 1468 sc->sk_macs++; 1469 1470 skca.skc_port = SK_PORT_A; 1471 skca.skc_type = sc->sk_type; 1472 skca.skc_rev = sc->sk_rev; 1473 (void)config_found(&sc->sk_dev, &skca, skcprint); 1474 1475 if (sc->sk_macs > 1) { 1476 skca.skc_port = SK_PORT_B; 1477 skca.skc_type = sc->sk_type; 1478 skca.skc_rev = sc->sk_rev; 1479 (void)config_found(&sc->sk_dev, &skca, skcprint); 1480 } 1481 1482 /* Turn on the 'driver is loaded' LED. */ 1483 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1484 1485 return; 1486 1487 fail_2: 1488 pci_intr_disestablish(pc, sc->sk_intrhand); 1489 fail_1: 1490 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1491 } 1492 1493 int 1494 skc_detach(struct device *self, int flags) 1495 { 1496 struct sk_softc *sc = (struct sk_softc *)self; 1497 int rv; 1498 1499 if (sc->sk_intrhand) 1500 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1501 1502 rv = config_detach_children(self, flags); 1503 if (rv != 0) 1504 return (rv); 1505 1506 if (sc->sk_bsize > 0) 1507 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1508 1509 return(0); 1510 } 1511 1512 int 1513 skc_activate(struct device *self, int act) 1514 { 1515 struct sk_softc *sc = (void *)self; 1516 int rv = 0; 1517 1518 switch (act) { 1519 case DVACT_RESUME: 1520 skc_reset(sc); 1521 rv = config_activate_children(self, act); 1522 break; 1523 default: 1524 rv = config_activate_children(self, act); 1525 break; 1526 } 1527 return (rv); 1528 } 1529 1530 int 1531 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1532 { 1533 struct sk_softc *sc = sc_if->sk_softc; 1534 struct sk_tx_desc *f = NULL; 1535 u_int32_t frag, cur, sk_ctl; 1536 int i; 1537 struct sk_txmap_entry *entry; 1538 bus_dmamap_t txmap; 1539 1540 DPRINTFN(2, ("sk_encap\n")); 1541 1542 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1543 if (entry == NULL) { 1544 DPRINTFN(2, ("sk_encap: no txmap available\n")); 1545 return (ENOBUFS); 1546 } 1547 txmap = entry->dmamap; 1548 1549 cur = frag = *txidx; 1550 1551 #ifdef SK_DEBUG 1552 if (skdebug >= 2) 1553 sk_dump_mbuf(m_head); 1554 #endif 1555 1556 /* 1557 * Start packing the mbufs in this chain into 1558 * the fragment pointers. Stop when we run out 1559 * of fragments or hit the end of the mbuf chain. 1560 */ 1561 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1562 BUS_DMA_NOWAIT)) { 1563 DPRINTFN(2, ("sk_encap: dmamap failed\n")); 1564 return (ENOBUFS); 1565 } 1566 1567 if (txmap->dm_nsegs > (SK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1568 DPRINTFN(2, ("sk_encap: too few descriptors free\n")); 1569 bus_dmamap_unload(sc->sc_dmatag, txmap); 1570 return (ENOBUFS); 1571 } 1572 1573 DPRINTFN(2, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1574 1575 /* Sync the DMA map. */ 1576 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1577 BUS_DMASYNC_PREWRITE); 1578 1579 for (i = 0; i < txmap->dm_nsegs; i++) { 1580 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1581 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1582 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1583 if (i == 0) 1584 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1585 else 1586 sk_ctl |= SK_TXCTL_OWN; 1587 f->sk_ctl = htole32(sk_ctl); 1588 cur = frag; 1589 SK_INC(frag, SK_TX_RING_CNT); 1590 } 1591 1592 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1593 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1594 1595 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1596 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1597 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1598 1599 /* Sync descriptors before handing to chip */ 1600 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1601 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1602 1603 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1604 htole32(SK_TXCTL_OWN); 1605 1606 /* Sync first descriptor to hand it off */ 1607 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1608 1609 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1610 1611 #ifdef SK_DEBUG 1612 if (skdebug >= 2) { 1613 struct sk_tx_desc *desc; 1614 u_int32_t idx; 1615 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1616 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1617 sk_dump_txdesc(desc, idx); 1618 } 1619 } 1620 #endif 1621 1622 *txidx = frag; 1623 1624 DPRINTFN(2, ("sk_encap: completed successfully\n")); 1625 1626 return (0); 1627 } 1628 1629 void 1630 sk_start(struct ifnet *ifp) 1631 { 1632 struct sk_if_softc *sc_if = ifp->if_softc; 1633 struct sk_softc *sc = sc_if->sk_softc; 1634 struct mbuf *m_head = NULL; 1635 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1636 int pkts = 0; 1637 1638 DPRINTFN(2, ("sk_start\n")); 1639 1640 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1641 IFQ_POLL(&ifp->if_snd, m_head); 1642 if (m_head == NULL) 1643 break; 1644 1645 /* 1646 * Pack the data into the transmit ring. If we 1647 * don't have room, set the OACTIVE flag and wait 1648 * for the NIC to drain the ring. 1649 */ 1650 if (sk_encap(sc_if, m_head, &idx)) { 1651 ifp->if_flags |= IFF_OACTIVE; 1652 break; 1653 } 1654 1655 /* now we are committed to transmit the packet */ 1656 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1657 pkts++; 1658 1659 /* 1660 * If there's a BPF listener, bounce a copy of this frame 1661 * to him. 1662 */ 1663 #if NBPFILTER > 0 1664 if (ifp->if_bpf) 1665 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1666 #endif 1667 } 1668 if (pkts == 0) 1669 return; 1670 1671 /* Transmit */ 1672 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1673 sc_if->sk_cdata.sk_tx_prod = idx; 1674 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1675 1676 /* Set a timeout in case the chip goes out to lunch. */ 1677 ifp->if_timer = 5; 1678 } 1679 } 1680 1681 1682 void 1683 sk_watchdog(struct ifnet *ifp) 1684 { 1685 struct sk_if_softc *sc_if = ifp->if_softc; 1686 1687 /* 1688 * Reclaim first as there is a possibility of losing Tx completion 1689 * interrupts. 1690 */ 1691 sk_txeof(sc_if); 1692 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1693 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1694 1695 ifp->if_oerrors++; 1696 1697 sk_init(sc_if); 1698 } 1699 } 1700 1701 static __inline int 1702 sk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1703 { 1704 if (sc->sk_type == SK_GENESIS) { 1705 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 1706 XM_RXSTAT_BYTES(stat) != len) 1707 return (0); 1708 } else { 1709 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1710 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1711 YU_RXSTAT_JABBER)) != 0 || 1712 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1713 YU_RXSTAT_BYTES(stat) != len) 1714 return (0); 1715 } 1716 1717 return (1); 1718 } 1719 1720 void 1721 sk_rxeof(struct sk_if_softc *sc_if) 1722 { 1723 struct sk_softc *sc = sc_if->sk_softc; 1724 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1725 struct mbuf *m; 1726 struct sk_chain *cur_rx; 1727 struct sk_rx_desc *cur_desc; 1728 int i, cur, total_len = 0; 1729 u_int32_t rxstat, sk_ctl; 1730 bus_dmamap_t dmamap; 1731 1732 DPRINTFN(2, ("sk_rxeof\n")); 1733 1734 i = sc_if->sk_cdata.sk_rx_prod; 1735 1736 for (;;) { 1737 cur = i; 1738 1739 /* Sync the descriptor */ 1740 SK_CDRXSYNC(sc_if, cur, 1741 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1742 1743 sk_ctl = letoh32(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1744 if ((sk_ctl & SK_RXCTL_OWN) != 0) { 1745 /* Invalidate the descriptor -- it's not ready yet */ 1746 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 1747 sc_if->sk_cdata.sk_rx_prod = i; 1748 break; 1749 } 1750 1751 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1752 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1753 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1754 1755 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1756 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1757 1758 rxstat = letoh32(cur_desc->sk_xmac_rxstat); 1759 m = cur_rx->sk_mbuf; 1760 cur_rx->sk_mbuf = NULL; 1761 total_len = SK_RXBYTES(letoh32(cur_desc->sk_ctl)); 1762 1763 SK_INC(i, SK_RX_RING_CNT); 1764 1765 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 1766 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 1767 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 1768 total_len < SK_MIN_FRAMELEN || 1769 total_len > SK_JUMBO_FRAMELEN || 1770 sk_rxvalid(sc, rxstat, total_len) == 0) { 1771 ifp->if_ierrors++; 1772 sk_newbuf(sc_if, cur, m, dmamap); 1773 continue; 1774 } 1775 1776 /* 1777 * Try to allocate a new jumbo buffer. If that 1778 * fails, copy the packet to mbufs and put the 1779 * jumbo buffer back in the ring so it can be 1780 * re-used. If allocating mbufs fails, then we 1781 * have to drop the packet. 1782 */ 1783 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1784 struct mbuf *m0; 1785 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 1786 ifp); 1787 sk_newbuf(sc_if, cur, m, dmamap); 1788 if (m0 == NULL) { 1789 ifp->if_ierrors++; 1790 continue; 1791 } 1792 m = m0; 1793 } else { 1794 m->m_pkthdr.rcvif = ifp; 1795 m->m_pkthdr.len = m->m_len = total_len; 1796 } 1797 1798 ifp->if_ipackets++; 1799 1800 #if NBPFILTER > 0 1801 if (ifp->if_bpf) 1802 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1803 #endif 1804 1805 /* pass it on. */ 1806 ether_input_mbuf(ifp, m); 1807 } 1808 } 1809 1810 void 1811 sk_txeof(struct sk_if_softc *sc_if) 1812 { 1813 struct sk_softc *sc = sc_if->sk_softc; 1814 struct sk_tx_desc *cur_tx; 1815 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1816 u_int32_t idx, sk_ctl; 1817 struct sk_txmap_entry *entry; 1818 1819 DPRINTFN(2, ("sk_txeof\n")); 1820 1821 /* 1822 * Go through our tx ring and free mbufs for those 1823 * frames that have been sent. 1824 */ 1825 idx = sc_if->sk_cdata.sk_tx_cons; 1826 while (idx != sc_if->sk_cdata.sk_tx_prod) { 1827 SK_CDTXSYNC(sc_if, idx, 1, 1828 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1829 1830 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1831 sk_ctl = letoh32(cur_tx->sk_ctl); 1832 #ifdef SK_DEBUG 1833 if (skdebug >= 2) 1834 sk_dump_txdesc(cur_tx, idx); 1835 #endif 1836 if (sk_ctl & SK_TXCTL_OWN) { 1837 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 1838 break; 1839 } 1840 if (sk_ctl & SK_TXCTL_LASTFRAG) 1841 ifp->if_opackets++; 1842 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1843 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1844 1845 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1846 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1847 1848 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1849 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1850 1851 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1852 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1853 link); 1854 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1855 } 1856 sc_if->sk_cdata.sk_tx_cnt--; 1857 SK_INC(idx, SK_TX_RING_CNT); 1858 } 1859 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1860 1861 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 1862 ifp->if_flags &= ~IFF_OACTIVE; 1863 1864 sc_if->sk_cdata.sk_tx_cons = idx; 1865 } 1866 1867 void 1868 sk_tick(void *xsc_if) 1869 { 1870 struct sk_if_softc *sc_if = xsc_if; 1871 struct mii_data *mii = &sc_if->sk_mii; 1872 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1873 int i; 1874 1875 DPRINTFN(2, ("sk_tick\n")); 1876 1877 if (!(ifp->if_flags & IFF_UP)) 1878 return; 1879 1880 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1881 sk_intr_bcom(sc_if); 1882 return; 1883 } 1884 1885 /* 1886 * According to SysKonnect, the correct way to verify that 1887 * the link has come back up is to poll bit 0 of the GPIO 1888 * register three times. This pin has the signal from the 1889 * link sync pin connected to it; if we read the same link 1890 * state 3 times in a row, we know the link is up. 1891 */ 1892 for (i = 0; i < 3; i++) { 1893 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1894 break; 1895 } 1896 1897 if (i != 3) { 1898 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1899 return; 1900 } 1901 1902 /* Turn the GP0 interrupt back on. */ 1903 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1904 SK_XM_READ_2(sc_if, XM_ISR); 1905 mii_tick(mii); 1906 timeout_del(&sc_if->sk_tick_ch); 1907 } 1908 1909 void 1910 sk_yukon_tick(void *xsc_if) 1911 { 1912 struct sk_if_softc *sc_if = xsc_if; 1913 struct mii_data *mii = &sc_if->sk_mii; 1914 int s; 1915 1916 s = splnet(); 1917 mii_tick(mii); 1918 splx(s); 1919 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1920 } 1921 1922 void 1923 sk_intr_bcom(struct sk_if_softc *sc_if) 1924 { 1925 struct mii_data *mii = &sc_if->sk_mii; 1926 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1927 int status; 1928 1929 DPRINTFN(2, ("sk_intr_bcom\n")); 1930 1931 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1932 1933 /* 1934 * Read the PHY interrupt register to make sure 1935 * we clear any pending interrupts. 1936 */ 1937 status = sk_xmac_miibus_readreg((struct device *)sc_if, 1938 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1939 1940 if (!(ifp->if_flags & IFF_RUNNING)) { 1941 sk_init_xmac(sc_if); 1942 return; 1943 } 1944 1945 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1946 int lstat; 1947 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 1948 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 1949 1950 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1951 mii_mediachg(mii); 1952 /* Turn off the link LED. */ 1953 SK_IF_WRITE_1(sc_if, 0, 1954 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1955 sc_if->sk_link = 0; 1956 } else if (status & BRGPHY_ISR_LNK_CHG) { 1957 sk_xmac_miibus_writereg((struct device *)sc_if, 1958 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 1959 mii_tick(mii); 1960 sc_if->sk_link = 1; 1961 /* Turn on the link LED. */ 1962 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1963 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1964 SK_LINKLED_BLINK_OFF); 1965 } else { 1966 mii_tick(mii); 1967 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1968 } 1969 } 1970 1971 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1972 } 1973 1974 void 1975 sk_intr_xmac(struct sk_if_softc *sc_if) 1976 { 1977 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 1978 1979 DPRINTFN(2, ("sk_intr_xmac\n")); 1980 1981 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1982 if (status & XM_ISR_GP0_SET) { 1983 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1984 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1985 } 1986 1987 if (status & XM_ISR_AUTONEG_DONE) { 1988 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1989 } 1990 } 1991 1992 if (status & XM_IMR_TX_UNDERRUN) 1993 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1994 1995 if (status & XM_IMR_RX_OVERRUN) 1996 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1997 } 1998 1999 void 2000 sk_intr_yukon(struct sk_if_softc *sc_if) 2001 { 2002 u_int8_t status; 2003 2004 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2005 /* RX overrun */ 2006 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2007 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2008 SK_RFCTL_RX_FIFO_OVER); 2009 } 2010 /* TX underrun */ 2011 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2012 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2013 SK_TFCTL_TX_FIFO_UNDER); 2014 } 2015 2016 DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status)); 2017 } 2018 2019 int 2020 sk_intr(void *xsc) 2021 { 2022 struct sk_softc *sc = xsc; 2023 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2024 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2025 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2026 u_int32_t status; 2027 int claimed = 0; 2028 2029 status = CSR_READ_4(sc, SK_ISSR); 2030 if (status == 0 || status == 0xffffffff) 2031 return (0); 2032 2033 if (sc_if0 != NULL) 2034 ifp0 = &sc_if0->arpcom.ac_if; 2035 if (sc_if1 != NULL) 2036 ifp1 = &sc_if1->arpcom.ac_if; 2037 2038 for (; (status &= sc->sk_intrmask) != 0;) { 2039 claimed = 1; 2040 2041 /* Handle receive interrupts first. */ 2042 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2043 sk_rxeof(sc_if0); 2044 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2045 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2046 } 2047 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2048 sk_rxeof(sc_if1); 2049 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2050 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2051 } 2052 2053 /* Then transmit interrupts. */ 2054 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2055 sk_txeof(sc_if0); 2056 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2057 SK_TXBMU_CLR_IRQ_EOF); 2058 } 2059 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2060 sk_txeof(sc_if1); 2061 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2062 SK_TXBMU_CLR_IRQ_EOF); 2063 } 2064 2065 /* Then MAC interrupts. */ 2066 if (sc_if0 && (status & SK_ISR_MAC1) && 2067 (ifp0->if_flags & IFF_RUNNING)) { 2068 if (SK_IS_GENESIS(sc)) 2069 sk_intr_xmac(sc_if0); 2070 else 2071 sk_intr_yukon(sc_if0); 2072 } 2073 2074 if (sc_if1 && (status & SK_ISR_MAC2) && 2075 (ifp1->if_flags & IFF_RUNNING)) { 2076 if (SK_IS_GENESIS(sc)) 2077 sk_intr_xmac(sc_if1); 2078 else 2079 sk_intr_yukon(sc_if1); 2080 2081 } 2082 2083 if (status & SK_ISR_EXTERNAL_REG) { 2084 if (sc_if0 != NULL && 2085 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2086 sk_intr_bcom(sc_if0); 2087 2088 if (sc_if1 != NULL && 2089 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2090 sk_intr_bcom(sc_if1); 2091 } 2092 status = CSR_READ_4(sc, SK_ISSR); 2093 } 2094 2095 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2096 2097 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2098 sk_start(ifp0); 2099 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2100 sk_start(ifp1); 2101 2102 return (claimed); 2103 } 2104 2105 void 2106 sk_init_xmac(struct sk_if_softc *sc_if) 2107 { 2108 struct sk_softc *sc = sc_if->sk_softc; 2109 struct sk_bcom_hack bhack[] = { 2110 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2111 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2112 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2113 { 0, 0 } }; 2114 2115 DPRINTFN(2, ("sk_init_xmac\n")); 2116 2117 /* Unreset the XMAC. */ 2118 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2119 DELAY(1000); 2120 2121 /* Reset the XMAC's internal state. */ 2122 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2123 2124 /* Save the XMAC II revision */ 2125 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2126 2127 /* 2128 * Perform additional initialization for external PHYs, 2129 * namely for the 1000baseTX cards that use the XMAC's 2130 * GMII mode. 2131 */ 2132 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2133 int i = 0; 2134 u_int32_t val; 2135 2136 /* Take PHY out of reset. */ 2137 val = sk_win_read_4(sc, SK_GPIO); 2138 if (sc_if->sk_port == SK_PORT_A) 2139 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2140 else 2141 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2142 sk_win_write_4(sc, SK_GPIO, val); 2143 2144 /* Enable GMII mode on the XMAC. */ 2145 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2146 2147 sk_xmac_miibus_writereg((struct device *)sc_if, 2148 SK_PHYADDR_BCOM, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2149 DELAY(10000); 2150 sk_xmac_miibus_writereg((struct device *)sc_if, 2151 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2152 2153 /* 2154 * Early versions of the BCM5400 apparently have 2155 * a bug that requires them to have their reserved 2156 * registers initialized to some magic values. I don't 2157 * know what the numbers do, I'm just the messenger. 2158 */ 2159 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2160 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2161 while(bhack[i].reg) { 2162 sk_xmac_miibus_writereg((struct device *)sc_if, 2163 SK_PHYADDR_BCOM, bhack[i].reg, 2164 bhack[i].val); 2165 i++; 2166 } 2167 } 2168 } 2169 2170 /* Set station address */ 2171 SK_XM_WRITE_2(sc_if, XM_PAR0, 2172 letoh16(*(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0]))); 2173 SK_XM_WRITE_2(sc_if, XM_PAR1, 2174 letoh16(*(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2]))); 2175 SK_XM_WRITE_2(sc_if, XM_PAR2, 2176 letoh16(*(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4]))); 2177 2178 /* We don't need the FCS appended to the packet. */ 2179 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2180 2181 /* We want short frames padded to 60 bytes. */ 2182 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2183 2184 /* 2185 * Enable the reception of all error frames. This is 2186 * a necessary evil due to the design of the XMAC. The 2187 * XMAC's receive FIFO is only 8K in size, however jumbo 2188 * frames can be up to 9000 bytes in length. When bad 2189 * frame filtering is enabled, the XMAC's RX FIFO operates 2190 * in 'store and forward' mode. For this to work, the 2191 * entire frame has to fit into the FIFO, but that means 2192 * that jumbo frames larger than 8192 bytes will be 2193 * truncated. Disabling all bad frame filtering causes 2194 * the RX FIFO to operate in streaming mode, in which 2195 * case the XMAC will start transferring frames out of the 2196 * RX FIFO as soon as the FIFO threshold is reached. 2197 */ 2198 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2199 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2200 XM_MODE_RX_INRANGELEN); 2201 2202 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2203 2204 /* 2205 * Bump up the transmit threshold. This helps hold off transmit 2206 * underruns when we're blasting traffic from both ports at once. 2207 */ 2208 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2209 2210 /* Program promiscuous mode and multicast filters. */ 2211 sk_iff(sc_if); 2212 2213 /* Clear and enable interrupts */ 2214 SK_XM_READ_2(sc_if, XM_ISR); 2215 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2216 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2217 else 2218 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2219 2220 /* Configure MAC arbiter */ 2221 switch(sc_if->sk_xmac_rev) { 2222 case XM_XMAC_REV_B2: 2223 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2224 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2225 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2226 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2227 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2228 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2229 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2230 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2231 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2232 break; 2233 case XM_XMAC_REV_C1: 2234 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2235 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2236 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2237 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2238 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2239 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2240 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2241 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2242 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2243 break; 2244 default: 2245 break; 2246 } 2247 sk_win_write_2(sc, SK_MACARB_CTL, 2248 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2249 2250 sc_if->sk_link = 1; 2251 } 2252 2253 void sk_init_yukon(struct sk_if_softc *sc_if) 2254 { 2255 u_int32_t phy, v; 2256 u_int16_t reg; 2257 struct sk_softc *sc; 2258 int i; 2259 2260 sc = sc_if->sk_softc; 2261 2262 DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n", 2263 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2264 2265 if (sc->sk_type == SK_YUKON_LITE && 2266 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2267 /* 2268 * Workaround code for COMA mode, set PHY reset. 2269 * Otherwise it will not correctly take chip out of 2270 * powerdown (coma) 2271 */ 2272 v = sk_win_read_4(sc, SK_GPIO); 2273 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 2274 sk_win_write_4(sc, SK_GPIO, v); 2275 } 2276 2277 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2278 2279 /* GMAC and GPHY Reset */ 2280 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2281 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2282 DELAY(1000); 2283 2284 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2285 2286 if (sc->sk_type == SK_YUKON_LITE && 2287 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2288 /* 2289 * Workaround code for COMA mode, clear PHY reset 2290 */ 2291 v = sk_win_read_4(sc, SK_GPIO); 2292 v |= SK_GPIO_DIR9; 2293 v &= ~SK_GPIO_DAT9; 2294 sk_win_write_4(sc, SK_GPIO, v); 2295 } 2296 2297 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2298 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2299 2300 if (sc->sk_coppertype) 2301 phy |= SK_GPHY_COPPER; 2302 else 2303 phy |= SK_GPHY_FIBER; 2304 2305 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2306 2307 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2308 DELAY(1000); 2309 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2310 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2311 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2312 2313 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2314 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2315 2316 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2317 2318 /* unused read of the interrupt source register */ 2319 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2320 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2321 2322 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2323 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2324 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2325 2326 /* MIB Counter Clear Mode set */ 2327 reg |= YU_PAR_MIB_CLR; 2328 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2329 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2330 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2331 2332 /* MIB Counter Clear Mode clear */ 2333 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2334 reg &= ~YU_PAR_MIB_CLR; 2335 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2336 2337 /* receive control reg */ 2338 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2339 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2340 2341 /* transmit parameter register */ 2342 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2343 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2344 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2345 2346 /* serial mode register */ 2347 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2348 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2349 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2350 YU_SMR_IPG_DATA(0x1e)); 2351 2352 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2353 /* Setup Yukon's address */ 2354 for (i = 0; i < 3; i++) { 2355 /* Write Source Address 1 (unicast filter) */ 2356 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2357 sc_if->arpcom.ac_enaddr[i * 2] | 2358 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2359 } 2360 2361 for (i = 0; i < 3; i++) { 2362 reg = sk_win_read_2(sc_if->sk_softc, 2363 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2364 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2365 } 2366 2367 /* Program promiscuous mode and multicast filters. */ 2368 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2369 sk_iff(sc_if); 2370 2371 /* enable interrupt mask for counter overflows */ 2372 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2373 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2374 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2375 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2376 2377 /* Configure RX MAC FIFO Flush Mask */ 2378 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2379 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2380 YU_RXSTAT_JABBER; 2381 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2382 2383 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 2384 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 2385 v = SK_TFCTL_OPERATION_ON; 2386 else 2387 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 2388 /* Configure RX MAC FIFO */ 2389 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2390 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 2391 2392 /* Increase flush threshould to 64 bytes */ 2393 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2394 SK_RFCTL_FIFO_THRESHOLD + 1); 2395 2396 /* Configure TX MAC FIFO */ 2397 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2398 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2399 2400 DPRINTFN(6, ("sk_init_yukon: end\n")); 2401 } 2402 2403 /* 2404 * Note that to properly initialize any part of the GEnesis chip, 2405 * you first have to take it out of reset mode. 2406 */ 2407 void 2408 sk_init(void *xsc_if) 2409 { 2410 struct sk_if_softc *sc_if = xsc_if; 2411 struct sk_softc *sc = sc_if->sk_softc; 2412 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2413 struct mii_data *mii = &sc_if->sk_mii; 2414 int s; 2415 2416 DPRINTFN(2, ("sk_init\n")); 2417 2418 s = splnet(); 2419 2420 /* Cancel pending I/O and free all RX/TX buffers. */ 2421 sk_stop(sc_if, 0); 2422 2423 if (SK_IS_GENESIS(sc)) { 2424 /* Configure LINK_SYNC LED */ 2425 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2426 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2427 SK_LINKLED_LINKSYNC_ON); 2428 2429 /* Configure RX LED */ 2430 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2431 SK_RXLEDCTL_COUNTER_START); 2432 2433 /* Configure TX LED */ 2434 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2435 SK_TXLEDCTL_COUNTER_START); 2436 } 2437 2438 /* 2439 * Configure descriptor poll timer 2440 * 2441 * SK-NET GENESIS data sheet says that possibility of losing Start 2442 * transmit command due to CPU/cache related interim storage problems 2443 * under certain conditions. The document recommends a polling 2444 * mechanism to send a Start transmit command to initiate transfer 2445 * of ready descriptors regulary. To cope with this issue sk(4) now 2446 * enables descriptor poll timer to initiate descriptor processing 2447 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 2448 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 2449 * command instead of waiting for next descriptor polling time. 2450 * The same rule may apply to Rx side too but it seems that is not 2451 * needed at the moment. 2452 * Since sk(4) uses descriptor polling as a last resort there is no 2453 * need to set smaller polling time than maximum allowable one. 2454 */ 2455 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 2456 2457 /* Configure I2C registers */ 2458 2459 /* Configure XMAC(s) */ 2460 switch (sc->sk_type) { 2461 case SK_GENESIS: 2462 sk_init_xmac(sc_if); 2463 break; 2464 case SK_YUKON: 2465 case SK_YUKON_LITE: 2466 case SK_YUKON_LP: 2467 sk_init_yukon(sc_if); 2468 break; 2469 } 2470 mii_mediachg(mii); 2471 2472 if (SK_IS_GENESIS(sc)) { 2473 /* Configure MAC FIFOs */ 2474 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2475 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2476 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2477 2478 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2479 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2480 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2481 } 2482 2483 /* Configure transmit arbiter(s) */ 2484 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2485 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2486 2487 /* Configure RAMbuffers */ 2488 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2489 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2490 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2491 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2492 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2493 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2494 2495 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2496 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2497 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2498 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2499 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2500 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2501 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2502 2503 /* Configure BMUs */ 2504 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2505 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2506 SK_RX_RING_ADDR(sc_if, 0)); 2507 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2508 2509 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2510 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2511 SK_TX_RING_ADDR(sc_if, 0)); 2512 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2513 2514 /* Init descriptors */ 2515 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2516 printf("%s: initialization failed: no " 2517 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2518 sk_stop(sc_if, 0); 2519 splx(s); 2520 return; 2521 } 2522 2523 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2524 printf("%s: initialization failed: no " 2525 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2526 sk_stop(sc_if, 0); 2527 splx(s); 2528 return; 2529 } 2530 2531 /* Configure interrupt handling */ 2532 CSR_READ_4(sc, SK_ISSR); 2533 if (sc_if->sk_port == SK_PORT_A) 2534 sc->sk_intrmask |= SK_INTRS1; 2535 else 2536 sc->sk_intrmask |= SK_INTRS2; 2537 2538 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2539 2540 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2541 2542 /* Start BMUs. */ 2543 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2544 2545 if (SK_IS_GENESIS(sc)) { 2546 /* Enable XMACs TX and RX state machines */ 2547 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2548 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2549 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2550 } 2551 2552 if (SK_IS_YUKON(sc)) { 2553 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2554 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2555 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2556 } 2557 2558 /* Activate descriptor polling timer */ 2559 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 2560 /* start transfer of Tx descriptors */ 2561 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2562 2563 ifp->if_flags |= IFF_RUNNING; 2564 ifp->if_flags &= ~IFF_OACTIVE; 2565 2566 if (SK_IS_YUKON(sc)) 2567 timeout_add_sec(&sc_if->sk_tick_ch, 1); 2568 2569 splx(s); 2570 } 2571 2572 void 2573 sk_stop(struct sk_if_softc *sc_if, int softonly) 2574 { 2575 struct sk_softc *sc = sc_if->sk_softc; 2576 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2577 struct sk_txmap_entry *dma; 2578 int i; 2579 u_int32_t val; 2580 2581 DPRINTFN(2, ("sk_stop\n")); 2582 2583 timeout_del(&sc_if->sk_tick_ch); 2584 2585 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2586 2587 if (!softonly) { 2588 /* stop Tx descriptor polling timer */ 2589 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 2590 /* stop transfer of Tx descriptors */ 2591 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 2592 for (i = 0; i < SK_TIMEOUT; i++) { 2593 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 2594 if (!(val & SK_TXBMU_TX_STOP)) 2595 break; 2596 DELAY(1); 2597 } 2598 if (i == SK_TIMEOUT) 2599 printf("%s: cannot stop transfer of Tx descriptors\n", 2600 sc_if->sk_dev.dv_xname); 2601 /* stop transfer of Rx descriptors */ 2602 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 2603 for (i = 0; i < SK_TIMEOUT; i++) { 2604 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 2605 if (!(val & SK_RXBMU_RX_STOP)) 2606 break; 2607 DELAY(1); 2608 } 2609 if (i == SK_TIMEOUT) 2610 printf("%s: cannot stop transfer of Rx descriptors\n", 2611 sc_if->sk_dev.dv_xname); 2612 2613 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2614 u_int32_t val; 2615 2616 /* Put PHY back into reset. */ 2617 val = sk_win_read_4(sc, SK_GPIO); 2618 if (sc_if->sk_port == SK_PORT_A) { 2619 val |= SK_GPIO_DIR0; 2620 val &= ~SK_GPIO_DAT0; 2621 } else { 2622 val |= SK_GPIO_DIR2; 2623 val &= ~SK_GPIO_DAT2; 2624 } 2625 sk_win_write_4(sc, SK_GPIO, val); 2626 } 2627 2628 /* Turn off various components of this interface. */ 2629 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2630 switch (sc->sk_type) { 2631 case SK_GENESIS: 2632 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2633 SK_TXMACCTL_XMAC_RESET); 2634 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2635 break; 2636 case SK_YUKON: 2637 case SK_YUKON_LITE: 2638 case SK_YUKON_LP: 2639 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2640 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2641 break; 2642 } 2643 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2644 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2645 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2646 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2647 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2648 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2649 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2650 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2651 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2652 2653 /* Disable interrupts */ 2654 if (sc_if->sk_port == SK_PORT_A) 2655 sc->sk_intrmask &= ~SK_INTRS1; 2656 else 2657 sc->sk_intrmask &= ~SK_INTRS2; 2658 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2659 2660 SK_XM_READ_2(sc_if, XM_ISR); 2661 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2662 } 2663 2664 /* Free RX and TX mbufs still in the queues. */ 2665 for (i = 0; i < SK_RX_RING_CNT; i++) { 2666 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2667 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2668 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2669 } 2670 } 2671 2672 for (i = 0; i < SK_TX_RING_CNT; i++) { 2673 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2674 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2675 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2676 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2677 sc_if->sk_cdata.sk_tx_map[i], link); 2678 sc_if->sk_cdata.sk_tx_map[i] = 0; 2679 } 2680 } 2681 2682 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2683 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2684 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2685 free(dma, M_DEVBUF, 0); 2686 } 2687 } 2688 2689 struct cfattach skc_ca = { 2690 sizeof(struct sk_softc), skc_probe, skc_attach, skc_detach, 2691 skc_activate 2692 }; 2693 2694 struct cfdriver skc_cd = { 2695 0, "skc", DV_DULL 2696 }; 2697 2698 struct cfattach sk_ca = { 2699 sizeof(struct sk_if_softc), sk_probe, sk_attach, sk_detach, 2700 sk_activate 2701 }; 2702 2703 struct cfdriver sk_cd = { 2704 NULL, "sk", DV_IFNET 2705 }; 2706 2707 #ifdef SK_DEBUG 2708 void 2709 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2710 { 2711 #define DESC_PRINT(X) \ 2712 if (X) \ 2713 printf("txdesc[%d]." #X "=%#x\n", \ 2714 idx, X); 2715 2716 DESC_PRINT(letoh32(desc->sk_ctl)); 2717 DESC_PRINT(letoh32(desc->sk_next)); 2718 DESC_PRINT(letoh32(desc->sk_data_lo)); 2719 DESC_PRINT(letoh32(desc->sk_data_hi)); 2720 DESC_PRINT(letoh32(desc->sk_xmac_txstat)); 2721 DESC_PRINT(letoh16(desc->sk_rsvd0)); 2722 DESC_PRINT(letoh16(desc->sk_rsvd1)); 2723 #undef PRINT 2724 } 2725 2726 void 2727 sk_dump_bytes(const char *data, int len) 2728 { 2729 int c, i, j; 2730 2731 for (i = 0; i < len; i += 16) { 2732 printf("%08x ", i); 2733 c = len - i; 2734 if (c > 16) c = 16; 2735 2736 for (j = 0; j < c; j++) { 2737 printf("%02x ", data[i + j] & 0xff); 2738 if ((j & 0xf) == 7 && j > 0) 2739 printf(" "); 2740 } 2741 2742 for (; j < 16; j++) 2743 printf(" "); 2744 printf(" "); 2745 2746 for (j = 0; j < c; j++) { 2747 int ch = data[i + j] & 0xff; 2748 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2749 } 2750 2751 printf("\n"); 2752 2753 if (c < 16) 2754 break; 2755 } 2756 } 2757 2758 void 2759 sk_dump_mbuf(struct mbuf *m) 2760 { 2761 int count = m->m_pkthdr.len; 2762 2763 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2764 2765 while (count > 0 && m) { 2766 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2767 m, m->m_data, m->m_len); 2768 sk_dump_bytes(mtod(m, char *), m->m_len); 2769 2770 count -= m->m_len; 2771 m = m->m_next; 2772 } 2773 } 2774 #endif 2775