1 /* $OpenBSD: if_sis.c,v 1.16 2001/08/12 20:03:49 mickey Exp $ */ 2 /* 3 * Copyright (c) 1997, 1998, 1999 4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/pci/if_sis.c,v 1.30 2001/02/06 10:11:47 phk Exp $ 34 */ 35 36 /* 37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 38 * available from http://www.sis.com.tw. 39 * 40 * This driver also supports the NatSemi DP83815. Datasheets are 41 * available from http://www.national.com. 42 * 43 * Written by Bill Paul <wpaul@ee.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61 #include "bpfilter.h" 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/mbuf.h> 66 #include <sys/protosw.h> 67 #include <sys/socket.h> 68 #include <sys/ioctl.h> 69 #include <sys/errno.h> 70 #include <sys/malloc.h> 71 #include <sys/kernel.h> 72 #include <sys/timeout.h> 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_types.h> 77 78 #ifdef INET 79 #include <netinet/in.h> 80 #include <netinet/in_systm.h> 81 #include <netinet/in_var.h> 82 #include <netinet/ip.h> 83 #include <netinet/if_ether.h> 84 #endif 85 86 #include <net/if_media.h> 87 88 #if NBPFILTER > 0 89 #include <net/bpf.h> 90 #endif 91 92 #include <vm/vm.h> /* for vtophys */ 93 94 #include <sys/device.h> 95 96 #include <dev/mii/mii.h> 97 #include <dev/mii/miivar.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #define SIS_USEIOSPACE 104 105 #include <dev/pci/if_sisreg.h> 106 107 int sis_probe __P((struct device *, void *, void *)); 108 void sis_attach __P((struct device *, struct device *, void *)); 109 int sis_intr __P((void *)); 110 void sis_shutdown __P((void *)); 111 int sis_newbuf __P((struct sis_softc *, struct sis_desc *, 112 struct mbuf *)); 113 int sis_encap __P((struct sis_softc *, struct mbuf *, u_int32_t *)); 114 void sis_rxeof __P((struct sis_softc *)); 115 void sis_rxeoc __P((struct sis_softc *)); 116 void sis_txeof __P((struct sis_softc *)); 117 void sis_tick __P((void *)); 118 void sis_start __P((struct ifnet *)); 119 int sis_ioctl __P((struct ifnet *, u_long, caddr_t)); 120 void sis_init __P((void *)); 121 void sis_stop __P((struct sis_softc *)); 122 void sis_watchdog __P((struct ifnet *)); 123 int sis_ifmedia_upd __P((struct ifnet *)); 124 void sis_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 125 126 u_int16_t sis_reverse __P((u_int16_t)); 127 void sis_delay __P((struct sis_softc *)); 128 void sis_eeprom_idle __P((struct sis_softc *)); 129 void sis_eeprom_putbyte __P((struct sis_softc *, int)); 130 void sis_eeprom_getword __P((struct sis_softc *, int, u_int16_t *)); 131 #ifdef __i386__ 132 void sis_read_cmos __P((struct sis_softc *, struct pci_attach_args *, caddr_t, int, int)); 133 #endif 134 void sis_read_eeprom __P((struct sis_softc *, caddr_t, int, int, int)); 135 136 int sis_miibus_readreg __P((struct device *, int, int)); 137 void sis_miibus_writereg __P((struct device *, int, int, int)); 138 void sis_miibus_statchg __P((struct device *)); 139 140 void sis_setmulti_sis __P((struct sis_softc *)); 141 void sis_setmulti_ns __P((struct sis_softc *)); 142 u_int32_t sis_crc __P((struct sis_softc *, caddr_t)); 143 void sis_reset __P((struct sis_softc *)); 144 int sis_list_rx_init __P((struct sis_softc *)); 145 int sis_list_tx_init __P((struct sis_softc *)); 146 147 #define SIS_SETBIT(sc, reg, x) \ 148 CSR_WRITE_4(sc, reg, \ 149 CSR_READ_4(sc, reg) | (x)) 150 151 #define SIS_CLRBIT(sc, reg, x) \ 152 CSR_WRITE_4(sc, reg, \ 153 CSR_READ_4(sc, reg) & ~(x)) 154 155 #define SIO_SET(x) \ 156 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 157 158 #define SIO_CLR(x) \ 159 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 160 161 /* 162 * Routine to reverse the bits in a word. Stolen almost 163 * verbatim from /usr/games/fortune. 164 */ 165 u_int16_t sis_reverse(n) 166 u_int16_t n; 167 { 168 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 169 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 170 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 171 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 172 173 return(n); 174 } 175 176 void sis_delay(sc) 177 struct sis_softc *sc; 178 { 179 int idx; 180 181 for (idx = (300 / 33) + 1; idx > 0; idx--) 182 CSR_READ_4(sc, SIS_CSR); 183 184 return; 185 } 186 187 void sis_eeprom_idle(sc) 188 struct sis_softc *sc; 189 { 190 register int i; 191 192 SIO_SET(SIS_EECTL_CSEL); 193 sis_delay(sc); 194 SIO_SET(SIS_EECTL_CLK); 195 sis_delay(sc); 196 197 for (i = 0; i < 25; i++) { 198 SIO_CLR(SIS_EECTL_CLK); 199 sis_delay(sc); 200 SIO_SET(SIS_EECTL_CLK); 201 sis_delay(sc); 202 } 203 204 SIO_CLR(SIS_EECTL_CLK); 205 sis_delay(sc); 206 SIO_CLR(SIS_EECTL_CSEL); 207 sis_delay(sc); 208 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 209 210 return; 211 } 212 213 /* 214 * Send a read command and address to the EEPROM, check for ACK. 215 */ 216 void sis_eeprom_putbyte(sc, addr) 217 struct sis_softc *sc; 218 int addr; 219 { 220 register int d, i; 221 222 d = addr | SIS_EECMD_READ; 223 224 /* 225 * Feed in each bit and stobe the clock. 226 */ 227 for (i = 0x400; i; i >>= 1) { 228 if (d & i) { 229 SIO_SET(SIS_EECTL_DIN); 230 } else { 231 SIO_CLR(SIS_EECTL_DIN); 232 } 233 sis_delay(sc); 234 SIO_SET(SIS_EECTL_CLK); 235 sis_delay(sc); 236 SIO_CLR(SIS_EECTL_CLK); 237 sis_delay(sc); 238 } 239 240 return; 241 } 242 243 /* 244 * Read a word of data stored in the EEPROM at address 'addr.' 245 */ 246 void sis_eeprom_getword(sc, addr, dest) 247 struct sis_softc *sc; 248 int addr; 249 u_int16_t *dest; 250 { 251 register int i; 252 u_int16_t word = 0; 253 254 /* Force EEPROM to idle state. */ 255 sis_eeprom_idle(sc); 256 257 /* Enter EEPROM access mode. */ 258 sis_delay(sc); 259 SIO_CLR(SIS_EECTL_CLK); 260 sis_delay(sc); 261 SIO_SET(SIS_EECTL_CSEL); 262 sis_delay(sc); 263 264 /* 265 * Send address of word we want to read. 266 */ 267 sis_eeprom_putbyte(sc, addr); 268 269 /* 270 * Start reading bits from EEPROM. 271 */ 272 for (i = 0x8000; i; i >>= 1) { 273 SIO_SET(SIS_EECTL_CLK); 274 sis_delay(sc); 275 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 276 word |= i; 277 sis_delay(sc); 278 SIO_CLR(SIS_EECTL_CLK); 279 sis_delay(sc); 280 } 281 282 /* Turn off EEPROM access mode. */ 283 sis_eeprom_idle(sc); 284 285 *dest = word; 286 287 return; 288 } 289 290 /* 291 * Read a sequence of words from the EEPROM. 292 */ 293 void sis_read_eeprom(sc, dest, off, cnt, swap) 294 struct sis_softc *sc; 295 caddr_t dest; 296 int off; 297 int cnt; 298 int swap; 299 { 300 int i; 301 u_int16_t word = 0, *ptr; 302 303 for (i = 0; i < cnt; i++) { 304 sis_eeprom_getword(sc, off + i, &word); 305 ptr = (u_int16_t *)(dest + (i * 2)); 306 if (swap) 307 *ptr = ntohs(word); 308 else 309 *ptr = word; 310 } 311 312 return; 313 } 314 315 #ifdef __i386__ 316 void sis_read_cmos(sc, pa, dest, off, cnt) 317 struct sis_softc *sc; 318 struct pci_attach_args *pa; 319 caddr_t dest; 320 int off, cnt; 321 { 322 bus_space_tag_t btag; 323 u_int32_t reg; 324 int i; 325 326 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x48); 327 pci_conf_write(pa->pa_pc, pa->pa_tag, 0x48, reg | 0x40); 328 329 btag = I386_BUS_SPACE_IO; 330 331 for (i = 0; i < cnt; i++) { 332 bus_space_write_1(btag, 0x0, 0x70, i + off); 333 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 334 } 335 336 pci_conf_write(pa->pa_pc, pa->pa_tag, 0x48, reg & ~0x40); 337 } 338 #endif 339 340 int sis_miibus_readreg(self, phy, reg) 341 struct device *self; 342 int phy, reg; 343 { 344 struct sis_softc *sc = (struct sis_softc *)self; 345 int i, val = 0; 346 347 if (sc->sis_type == SIS_TYPE_83815) { 348 if (phy != 0) 349 return(0); 350 /* 351 * The NatSemi chip can take a while after 352 * a reset to come ready, during which the BMSR 353 * returns a value of 0. This is *never* supposed 354 * to happen: some of the BMSR bits are meant to 355 * be hardwired in the on position, and this can 356 * confuse the miibus code a bit during the probe 357 * and attach phase. So we make an effort to check 358 * for this condition and wait for it to clear. 359 */ 360 if (!CSR_READ_4(sc, NS_BMSR)) 361 DELAY(1000); 362 val = CSR_READ_4(sc, NS_BMCR + (reg * 4)); 363 return(val); 364 } 365 366 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 367 return(0); 368 369 CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 370 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 371 372 for (i = 0; i < SIS_TIMEOUT; i++) { 373 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 374 break; 375 } 376 377 if (i == SIS_TIMEOUT) { 378 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 379 return(0); 380 } 381 382 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 383 384 if (val == 0xFFFF) 385 return(0); 386 387 return(val); 388 } 389 390 void sis_miibus_writereg(self, phy, reg, data) 391 struct device *self; 392 int phy, reg, data; 393 { 394 struct sis_softc *sc = (struct sis_softc *)self; 395 int i; 396 397 if (sc->sis_type == SIS_TYPE_83815) { 398 if (phy != 0) 399 return; 400 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 401 return; 402 } 403 404 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 405 return; 406 407 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 408 (reg << 6) | SIS_PHYOP_WRITE); 409 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 410 411 for (i = 0; i < SIS_TIMEOUT; i++) { 412 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 413 break; 414 } 415 416 if (i == SIS_TIMEOUT) 417 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 418 419 return; 420 } 421 422 void sis_miibus_statchg(self) 423 struct device *self; 424 { 425 struct sis_softc *sc = (struct sis_softc *)self; 426 427 sis_init(sc); 428 429 return; 430 } 431 432 u_int32_t sis_crc(sc, addr) 433 struct sis_softc *sc; 434 caddr_t addr; 435 { 436 u_int32_t crc, carry; 437 int i, j; 438 u_int8_t c; 439 440 /* Compute CRC for the address value. */ 441 crc = 0xFFFFFFFF; /* initial value */ 442 443 for (i = 0; i < 6; i++) { 444 c = *(addr + i); 445 for (j = 0; j < 8; j++) { 446 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 447 crc <<= 1; 448 c >>= 1; 449 if (carry) 450 crc = (crc ^ 0x04c11db6) | carry; 451 } 452 } 453 454 /* 455 * return the filter bit position 456 * 457 * The NatSemi chip has a 512-bit filter, which is 458 * different than the SiS, so we special-case it. 459 */ 460 if (sc->sis_type == SIS_TYPE_83815) 461 return((crc >> 23) & 0x1FF); 462 463 return((crc >> 25) & 0x0000007F); 464 } 465 466 void sis_setmulti_ns(sc) 467 struct sis_softc *sc; 468 { 469 struct ifnet *ifp; 470 struct arpcom *ac = &sc->arpcom; 471 struct ether_multi *enm; 472 struct ether_multistep step; 473 u_int32_t h = 0, i, filtsave; 474 int bit, index; 475 476 ifp = &sc->arpcom.ac_if; 477 478 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 479 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 480 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 481 return; 482 } 483 484 /* 485 * We have to explicitly enable the multicast hash table 486 * on the NatSemi chip if we want to use it, which we do. 487 */ 488 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 489 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 490 491 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 492 493 /* first, zot all the existing hash bits */ 494 for (i = 0; i < 32; i++) { 495 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 496 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 497 } 498 499 ETHER_FIRST_MULTI(step, ac, enm); 500 while (enm != NULL) { 501 h = sis_crc(sc, enm->enm_addrlo); 502 index = h >> 3; 503 bit = h & 0x1F; 504 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 505 if (bit > 0xF) 506 bit -= 0x10; 507 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 508 ETHER_NEXT_MULTI(step, enm); 509 } 510 511 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 512 513 return; 514 } 515 516 void sis_setmulti_sis(sc) 517 struct sis_softc *sc; 518 { 519 struct ifnet *ifp; 520 struct arpcom *ac = &sc->arpcom; 521 struct ether_multi *enm; 522 struct ether_multistep step; 523 u_int32_t h = 0, i, filtsave; 524 525 ifp = &sc->arpcom.ac_if; 526 527 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 528 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 529 return; 530 } 531 532 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 533 534 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 535 536 /* first, zot all the existing hash bits */ 537 for (i = 0; i < 8; i++) { 538 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + ((i * 16) >> 4)) << 16); 539 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 540 } 541 542 /* now program new ones */ 543 ETHER_FIRST_MULTI(step, ac, enm); 544 while (enm != NULL) { 545 h = sis_crc(sc, enm->enm_addrlo); 546 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + (h >> 4)) << 16); 547 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << (h & 0xF))); 548 ETHER_NEXT_MULTI(step, enm); 549 } 550 551 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 552 553 return; 554 } 555 556 void sis_reset(sc) 557 struct sis_softc *sc; 558 { 559 register int i; 560 561 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 562 563 for (i = 0; i < SIS_TIMEOUT; i++) { 564 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 565 break; 566 } 567 568 if (i == SIS_TIMEOUT) 569 printf("sis%d: reset never completed\n", sc->sis_unit); 570 571 /* Wait a little while for the chip to get its brains in order. */ 572 DELAY(1000); 573 574 /* 575 * If this is a NetSemi chip, make sure to clear 576 * PME mode. 577 */ 578 if (sc->sis_type == SIS_TYPE_83815) { 579 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 580 CSR_WRITE_4(sc, NS_CLKRUN, 0); 581 } 582 583 return; 584 } 585 586 /* 587 * Probe for an SiS chip. Check the PCI vendor and device 588 * IDs against our list and return a device name if we find a match. 589 */ 590 int sis_probe(parent, match, aux) 591 struct device *parent; 592 void *match; 593 void *aux; 594 { 595 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 596 597 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS && 598 PCI_VENDOR(pa->pa_id) != PCI_VENDOR_NS) 599 return(0); 600 601 switch (PCI_PRODUCT(pa->pa_id)) { 602 case PCI_PRODUCT_SIS_900: 603 case PCI_PRODUCT_SIS_7016: 604 case PCI_PRODUCT_NS_DP83815: 605 return(1); 606 } 607 608 return(0); 609 610 } 611 612 /* 613 * Attach the interface. Allocate softc structures, do ifmedia 614 * setup and ethernet/BPF attach. 615 */ 616 void sis_attach(parent, self, aux) 617 struct device *parent, *self; 618 void *aux; 619 { 620 int s; 621 const char *intrstr = NULL; 622 u_int32_t command; 623 struct sis_softc *sc = (struct sis_softc *)self; 624 struct pci_attach_args *pa = aux; 625 pci_chipset_tag_t pc = pa->pa_pc; 626 pci_intr_handle_t ih; 627 struct ifnet *ifp; 628 bus_addr_t iobase; 629 bus_size_t iosize; 630 631 s = splnet(); 632 sc->sis_unit = sc->sc_dev.dv_unit; 633 634 switch (PCI_PRODUCT(pa->pa_id)) { 635 case PCI_PRODUCT_SIS_900: 636 sc->sis_type = SIS_TYPE_900; 637 break; 638 case PCI_PRODUCT_SIS_7016: 639 sc->sis_type = SIS_TYPE_7016; 640 break; 641 case PCI_PRODUCT_NS_DP83815: 642 sc->sis_type = SIS_TYPE_83815; 643 break; 644 default: 645 break; 646 } 647 648 /* 649 * Handle power management nonsense. 650 */ 651 command = pci_conf_read(pc, pa->pa_tag, SIS_PCI_CAPID) & 0x000000FF; 652 if (command == 0x01) { 653 654 command = pci_conf_read(pc, pa->pa_tag, SIS_PCI_PWRMGMTCTRL); 655 if (command & SIS_PSTATE_MASK) { 656 u_int32_t iobase, membase, irq; 657 658 /* Save important PCI config data. */ 659 iobase = pci_conf_read(pc, pa->pa_tag, SIS_PCI_LOIO); 660 membase = pci_conf_read(pc, pa->pa_tag, SIS_PCI_LOMEM); 661 irq = pci_conf_read(pc, pa->pa_tag, SIS_PCI_INTLINE); 662 663 /* Reset the power state. */ 664 printf("sis%d: chip is in D%d power mode " 665 "-- setting to D0\n", sc->sis_unit, command & SIS_PSTATE_MASK); 666 command &= 0xFFFFFFFC; 667 pci_conf_write(pc, pa->pa_tag, SIS_PCI_PWRMGMTCTRL, command); 668 669 /* Restore PCI config data. */ 670 pci_conf_write(pc, pa->pa_tag, SIS_PCI_LOIO, iobase); 671 pci_conf_write(pc, pa->pa_tag, SIS_PCI_LOMEM, membase); 672 pci_conf_write(pc, pa->pa_tag, SIS_PCI_INTLINE, irq); 673 } 674 } 675 676 /* 677 * Map control/status registers. 678 */ 679 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 680 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 681 PCI_COMMAND_MASTER_ENABLE; 682 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 683 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 684 685 #ifdef SIS_USEIOSPACE 686 if (!(command & PCI_COMMAND_IO_ENABLE)) { 687 printf(": failed to enable I/O ports\n"); 688 goto fail; 689 } 690 if (pci_io_find(pc, pa->pa_tag, SIS_PCI_LOIO, &iobase, &iosize)) { 691 printf(": can't find I/O space\n"); 692 goto fail; 693 } 694 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->sis_bhandle)) { 695 printf(": can't map I/O space\n"); 696 goto fail; 697 } 698 sc->sis_btag = pa->pa_iot; 699 #else 700 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 701 printf(": failed to enable memory mapping\n"); 702 goto fail; 703 } 704 if (pci_mem_find(pc, pa->pa_tag, SIS_PCI_LOMEM, &iobase, &iosize,NULL)){ 705 printf(": can't find mem space\n"); 706 goto fail; 707 } 708 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->sis_bhandle)) { 709 printf(": can't map mem space\n"); 710 goto fail; 711 } 712 sc->sis_btag = pa->pa_memt; 713 #endif 714 715 /* Allocate interrupt */ 716 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, pa->pa_intrline, 717 &ih)) { 718 printf(": couldn't map interrupt\n"); 719 goto fail; 720 } 721 intrstr = pci_intr_string(pc, ih); 722 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sis_intr, sc, 723 self->dv_xname); 724 if (sc->sc_ih == NULL) { 725 printf(": couldn't establish interrupt"); 726 if (intrstr != NULL) 727 printf(" at %s", intrstr); 728 printf("\n"); 729 goto fail; 730 } 731 printf(": %s", intrstr); 732 733 /* Reset the adapter. */ 734 sis_reset(sc); 735 736 /* 737 * Get station address from the EEPROM. 738 */ 739 switch (PCI_VENDOR(pa->pa_id)) { 740 case PCI_VENDOR_NS: 741 /* 742 * Reading the MAC address out of the EEPROM on 743 * the NatSemi chip takes a bit more work than 744 * you'd expect. The address spans 4 16-bit words, 745 * with the first word containing only a single bit. 746 * You have to shift everything over one bit to 747 * get it aligned properly. Also, the bits are 748 * stored backwards (the LSB is really the MSB, 749 * and so on) so you have to reverse them in order 750 * to get the MAC address into the form we want. 751 * Why? Who the hell knows. 752 */ 753 { 754 u_int16_t tmp[4]; 755 756 sis_read_eeprom(sc, (caddr_t)&tmp, NS_EE_NODEADDR,4,0); 757 758 /* Shift everything over one bit. */ 759 tmp[3] = tmp[3] >> 1; 760 tmp[3] |= tmp[2] << 15; 761 tmp[2] = tmp[2] >> 1; 762 tmp[2] |= tmp[1] << 15; 763 tmp[1] = tmp[1] >> 1; 764 tmp[1] |= tmp[0] << 15; 765 766 /* Now reverse all the bits. */ 767 tmp[3] = sis_reverse(tmp[3]); 768 tmp[2] = sis_reverse(tmp[2]); 769 tmp[1] = sis_reverse(tmp[1]); 770 771 bcopy((char *)&tmp[1], sc->arpcom.ac_enaddr, 772 ETHER_ADDR_LEN); 773 } 774 break; 775 case PCI_VENDOR_SIS: 776 default: 777 #ifdef __i386__ 778 /* 779 * If this is a SiS 630E chipset with an embedded 780 * SiS 900 controller, we have to read the MAC address 781 * from the APC CMOS RAM. Our method for doing this 782 * is very ugly since we have to reach out and grab 783 * ahold of hardware for which we cannot properly 784 * allocate resources. This code is only compiled on 785 * the i386 architecture since the SiS 630E chipset 786 * is for x86 motherboards only. Note that there are 787 * a lot of magic numbers in this hack. These are 788 * taken from SiS's Linux driver. I'd like to replace 789 * them with proper symbolic definitions, but that 790 * requires some datasheets that I don't have access 791 * to at the moment. 792 */ 793 command = pci_conf_read(pc, pa->pa_tag, 794 PCI_CLASS_REG) & 0x000000ff; 795 if (command == SIS_REV_630S || 796 command == SIS_REV_630E || 797 command == SIS_REV_630EA1) 798 sis_read_cmos(sc, pa, (caddr_t)&sc->arpcom.ac_enaddr, 799 0x9, 6); 800 else 801 #endif 802 sis_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 803 SIS_EE_NODEADDR, 3, 0); 804 break; 805 } 806 807 printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); 808 809 sc->sis_ldata_ptr = malloc(sizeof(struct sis_list_data) + 8, 810 M_DEVBUF, M_NOWAIT); 811 if (sc->sis_ldata_ptr == NULL) { 812 printf("%s: no memory for list buffers!\n", sc->sis_unit); 813 goto fail; 814 } 815 816 sc->sis_ldata = (struct sis_list_data *)sc->sis_ldata_ptr; 817 bzero(sc->sis_ldata, sizeof(struct sis_list_data)); 818 819 ifp = &sc->arpcom.ac_if; 820 ifp->if_softc = sc; 821 ifp->if_mtu = ETHERMTU; 822 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 823 ifp->if_ioctl = sis_ioctl; 824 ifp->if_output = ether_output; 825 ifp->if_start = sis_start; 826 ifp->if_watchdog = sis_watchdog; 827 ifp->if_baudrate = 10000000; 828 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 829 IFQ_SET_READY(&ifp->if_snd); 830 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 831 832 sc->sc_mii.mii_ifp = ifp; 833 sc->sc_mii.mii_readreg = sis_miibus_readreg; 834 sc->sc_mii.mii_writereg = sis_miibus_writereg; 835 sc->sc_mii.mii_statchg = sis_miibus_statchg; 836 ifmedia_init(&sc->sc_mii.mii_media, 0, sis_ifmedia_upd,sis_ifmedia_sts); 837 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 838 0); 839 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 840 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 841 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 842 } else 843 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 844 845 /* 846 * Call MI attach routines. 847 */ 848 if_attach(ifp); 849 ether_ifattach(ifp); 850 851 shutdownhook_establish(sis_shutdown, sc); 852 853 fail: 854 splx(s); 855 return; 856 } 857 858 /* 859 * Initialize the transmit descriptors. 860 */ 861 int sis_list_tx_init(sc) 862 struct sis_softc *sc; 863 { 864 struct sis_list_data *ld; 865 struct sis_ring_data *cd; 866 int i; 867 868 cd = &sc->sis_cdata; 869 ld = sc->sis_ldata; 870 871 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 872 if (i == (SIS_TX_LIST_CNT - 1)) { 873 ld->sis_tx_list[i].sis_nextdesc = 874 &ld->sis_tx_list[0]; 875 ld->sis_tx_list[i].sis_next = 876 vtophys(&ld->sis_tx_list[0]); 877 } else { 878 ld->sis_tx_list[i].sis_nextdesc = 879 &ld->sis_tx_list[i + 1]; 880 ld->sis_tx_list[i].sis_next = 881 vtophys(&ld->sis_tx_list[i + 1]); 882 } 883 ld->sis_tx_list[i].sis_mbuf = NULL; 884 ld->sis_tx_list[i].sis_ptr = 0; 885 ld->sis_tx_list[i].sis_ctl = 0; 886 } 887 888 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 889 890 return(0); 891 } 892 893 894 /* 895 * Initialize the RX descriptors and allocate mbufs for them. Note that 896 * we arrange the descriptors in a closed ring, so that the last descriptor 897 * points back to the first. 898 */ 899 int sis_list_rx_init(sc) 900 struct sis_softc *sc; 901 { 902 struct sis_list_data *ld; 903 struct sis_ring_data *cd; 904 int i; 905 906 ld = sc->sis_ldata; 907 cd = &sc->sis_cdata; 908 909 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 910 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 911 return(ENOBUFS); 912 if (i == (SIS_RX_LIST_CNT - 1)) { 913 ld->sis_rx_list[i].sis_nextdesc = 914 &ld->sis_rx_list[0]; 915 ld->sis_rx_list[i].sis_next = 916 vtophys(&ld->sis_rx_list[0]); 917 } else { 918 ld->sis_rx_list[i].sis_nextdesc = 919 &ld->sis_rx_list[i + 1]; 920 ld->sis_rx_list[i].sis_next = 921 vtophys(&ld->sis_rx_list[i + 1]); 922 } 923 } 924 925 cd->sis_rx_prod = 0; 926 927 return(0); 928 } 929 930 /* 931 * Initialize an RX descriptor and attach an MBUF cluster. 932 */ 933 int sis_newbuf(sc, c, m) 934 struct sis_softc *sc; 935 struct sis_desc *c; 936 struct mbuf *m; 937 { 938 struct mbuf *m_new = NULL; 939 940 if (m == NULL) { 941 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 942 if (m_new == NULL) { 943 printf("sis%d: no memory for rx list " 944 "-- packet dropped!\n", sc->sis_unit); 945 return(ENOBUFS); 946 } 947 948 MCLGET(m_new, M_DONTWAIT); 949 if (!(m_new->m_flags & M_EXT)) { 950 printf("sis%d: no memory for rx list " 951 "-- packet dropped!\n", sc->sis_unit); 952 m_freem(m_new); 953 return(ENOBUFS); 954 } 955 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 956 } else { 957 m_new = m; 958 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 959 m_new->m_data = m_new->m_ext.ext_buf; 960 } 961 962 m_adj(m_new, sizeof(u_int64_t)); 963 964 c->sis_mbuf = m_new; 965 c->sis_ptr = vtophys(mtod(m_new, caddr_t)); 966 c->sis_ctl = SIS_RXLEN; 967 968 return(0); 969 } 970 971 /* 972 * A frame has been uploaded: pass the resulting mbuf chain up to 973 * the higher level protocols. 974 */ 975 void sis_rxeof(sc) 976 struct sis_softc *sc; 977 { 978 struct mbuf *m; 979 struct ifnet *ifp; 980 struct sis_desc *cur_rx; 981 int i, total_len = 0; 982 u_int32_t rxstat; 983 984 ifp = &sc->arpcom.ac_if; 985 i = sc->sis_cdata.sis_rx_prod; 986 987 while(SIS_OWNDESC(&sc->sis_ldata->sis_rx_list[i])) { 988 struct mbuf *m0 = NULL; 989 990 cur_rx = &sc->sis_ldata->sis_rx_list[i]; 991 rxstat = cur_rx->sis_rxstat; 992 m = cur_rx->sis_mbuf; 993 cur_rx->sis_mbuf = NULL; 994 total_len = SIS_RXBYTES(cur_rx); 995 SIS_INC(i, SIS_RX_LIST_CNT); 996 997 /* 998 * If an error occurs, update stats, clear the 999 * status word and leave the mbuf cluster in place: 1000 * it should simply get re-used next time this descriptor 1001 * comes up in the ring. 1002 */ 1003 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1004 ifp->if_ierrors++; 1005 if (rxstat & SIS_RXSTAT_COLL) 1006 ifp->if_collisions++; 1007 sis_newbuf(sc, cur_rx, m); 1008 continue; 1009 } 1010 1011 /* No errors; receive the packet. */ 1012 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1013 total_len + ETHER_ALIGN, 0, ifp, NULL); 1014 sis_newbuf(sc, cur_rx, m); 1015 if (m0 == NULL) { 1016 ifp->if_ierrors++; 1017 continue; 1018 } 1019 m_adj(m0, ETHER_ALIGN); 1020 m = m0; 1021 1022 ifp->if_ipackets++; 1023 1024 #if NBPFILTER > 0 1025 if (ifp->if_bpf) 1026 bpf_mtap(ifp->if_bpf, m); 1027 #endif 1028 1029 /* pass it on. */ 1030 ether_input_mbuf(ifp, m); 1031 } 1032 1033 sc->sis_cdata.sis_rx_prod = i; 1034 1035 return; 1036 } 1037 1038 void sis_rxeoc(sc) 1039 struct sis_softc *sc; 1040 { 1041 sis_rxeof(sc); 1042 sis_init(sc); 1043 return; 1044 } 1045 1046 /* 1047 * A frame was downloaded to the chip. It's safe for us to clean up 1048 * the list buffers. 1049 */ 1050 1051 void sis_txeof(sc) 1052 struct sis_softc *sc; 1053 { 1054 struct sis_desc *cur_tx = NULL; 1055 struct ifnet *ifp; 1056 u_int32_t idx; 1057 1058 ifp = &sc->arpcom.ac_if; 1059 1060 /* Clear the timeout timer. */ 1061 ifp->if_timer = 0; 1062 1063 /* 1064 * Go through our tx list and free mbufs for those 1065 * frames that have been transmitted. 1066 */ 1067 idx = sc->sis_cdata.sis_tx_cons; 1068 while (idx != sc->sis_cdata.sis_tx_prod) { 1069 cur_tx = &sc->sis_ldata->sis_tx_list[idx]; 1070 1071 if (SIS_OWNDESC(cur_tx)) 1072 break; 1073 1074 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) { 1075 sc->sis_cdata.sis_tx_cnt--; 1076 SIS_INC(idx, SIS_TX_LIST_CNT); 1077 continue; 1078 } 1079 1080 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1081 ifp->if_oerrors++; 1082 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1083 ifp->if_collisions++; 1084 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1085 ifp->if_collisions++; 1086 } 1087 1088 ifp->if_collisions += 1089 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1090 1091 ifp->if_opackets++; 1092 if (cur_tx->sis_mbuf != NULL) { 1093 m_freem(cur_tx->sis_mbuf); 1094 cur_tx->sis_mbuf = NULL; 1095 } 1096 1097 sc->sis_cdata.sis_tx_cnt--; 1098 SIS_INC(idx, SIS_TX_LIST_CNT); 1099 ifp->if_timer = 0; 1100 } 1101 1102 sc->sis_cdata.sis_tx_cons = idx; 1103 1104 if (cur_tx != NULL) 1105 ifp->if_flags &= ~IFF_OACTIVE; 1106 1107 return; 1108 } 1109 1110 void sis_tick(xsc) 1111 void *xsc; 1112 { 1113 struct sis_softc *sc = (struct sis_softc *)xsc; 1114 struct mii_data *mii; 1115 struct ifnet *ifp; 1116 int s; 1117 1118 s = splnet(); 1119 1120 ifp = &sc->arpcom.ac_if; 1121 1122 mii = &sc->sc_mii; 1123 mii_tick(mii); 1124 1125 if (!sc->sis_link) { 1126 mii_pollstat(mii); 1127 if (mii->mii_media_status & IFM_ACTIVE && 1128 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1129 sc->sis_link++; 1130 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1131 sis_start(ifp); 1132 } 1133 timeout_add(&sc->sis_timeout, hz); 1134 1135 splx(s); 1136 1137 return; 1138 } 1139 1140 int sis_intr(arg) 1141 void *arg; 1142 { 1143 struct sis_softc *sc; 1144 struct ifnet *ifp; 1145 u_int32_t status; 1146 int claimed = 0; 1147 1148 sc = arg; 1149 ifp = &sc->arpcom.ac_if; 1150 1151 /* Supress unwanted interrupts */ 1152 if (!(ifp->if_flags & IFF_UP)) { 1153 sis_stop(sc); 1154 return claimed; 1155 } 1156 1157 /* Disable interrupts. */ 1158 CSR_WRITE_4(sc, SIS_IER, 0); 1159 1160 for (;;) { 1161 /* Reading the ISR register clears all interrupts. */ 1162 status = CSR_READ_4(sc, SIS_ISR); 1163 1164 if ((status & SIS_INTRS) == 0) 1165 break; 1166 1167 claimed = 1; 1168 1169 if ((status & SIS_ISR_TX_DESC_OK) || 1170 (status & SIS_ISR_TX_ERR) || 1171 (status & SIS_ISR_TX_OK) || 1172 (status & SIS_ISR_TX_IDLE)) 1173 sis_txeof(sc); 1174 1175 if ((status & SIS_ISR_RX_DESC_OK) || 1176 (status & SIS_ISR_RX_OK)) 1177 sis_rxeof(sc); 1178 1179 if ((status & SIS_ISR_RX_ERR) || 1180 (status & SIS_ISR_RX_OFLOW)) { 1181 sis_rxeoc(sc); 1182 } 1183 1184 if (status & SIS_ISR_SYSERR) { 1185 sis_reset(sc); 1186 sis_init(sc); 1187 } 1188 } 1189 1190 /* Re-enable interrupts. */ 1191 CSR_WRITE_4(sc, SIS_IER, 1); 1192 1193 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1194 sis_start(ifp); 1195 1196 return claimed; 1197 } 1198 1199 /* 1200 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1201 * pointers to the fragment pointers. 1202 */ 1203 int sis_encap(sc, m_head, txidx) 1204 struct sis_softc *sc; 1205 struct mbuf *m_head; 1206 u_int32_t *txidx; 1207 { 1208 struct sis_desc *f = NULL; 1209 struct mbuf *m; 1210 int frag, cur, cnt = 0; 1211 1212 /* 1213 * Start packing the mbufs in this chain into 1214 * the fragment pointers. Stop when we run out 1215 * of fragments or hit the end of the mbuf chain. 1216 */ 1217 m = m_head; 1218 cur = frag = *txidx; 1219 1220 for (m = m_head; m != NULL; m = m->m_next) { 1221 if (m->m_len != 0) { 1222 if ((SIS_TX_LIST_CNT - 1223 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1224 return(ENOBUFS); 1225 f = &sc->sis_ldata->sis_tx_list[frag]; 1226 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1227 f->sis_ptr = vtophys(mtod(m, vm_offset_t)); 1228 if (cnt != 0) 1229 f->sis_ctl |= SIS_CMDSTS_OWN; 1230 cur = frag; 1231 SIS_INC(frag, SIS_TX_LIST_CNT); 1232 cnt++; 1233 } 1234 } 1235 1236 if (m != NULL) 1237 return(ENOBUFS); 1238 1239 sc->sis_ldata->sis_tx_list[cur].sis_mbuf = m_head; 1240 sc->sis_ldata->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1241 sc->sis_ldata->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1242 sc->sis_cdata.sis_tx_cnt += cnt; 1243 *txidx = frag; 1244 1245 return(0); 1246 } 1247 1248 /* 1249 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1250 * to the mbuf data regions directly in the transmit lists. We also save a 1251 * copy of the pointers since the transmit list fragment pointers are 1252 * physical addresses. 1253 */ 1254 1255 void sis_start(ifp) 1256 struct ifnet *ifp; 1257 { 1258 struct sis_softc *sc; 1259 struct mbuf *m_head = NULL; 1260 u_int32_t idx; 1261 1262 sc = ifp->if_softc; 1263 1264 if (!sc->sis_link) 1265 return; 1266 1267 idx = sc->sis_cdata.sis_tx_prod; 1268 1269 if (ifp->if_flags & IFF_OACTIVE) 1270 return; 1271 1272 while(sc->sis_ldata->sis_tx_list[idx].sis_mbuf == NULL) { 1273 IFQ_POLL(&ifp->if_snd, m_head); 1274 if (m_head == NULL) 1275 break; 1276 1277 if (sis_encap(sc, m_head, &idx)) { 1278 ifp->if_flags |= IFF_OACTIVE; 1279 break; 1280 } 1281 1282 /* now we are committed to transmit the packet */ 1283 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1284 1285 /* 1286 * If there's a BPF listener, bounce a copy of this frame 1287 * to him. 1288 */ 1289 #if NBPFILTER > 0 1290 if (ifp->if_bpf) 1291 bpf_mtap(ifp->if_bpf, m_head); 1292 #endif 1293 } 1294 if (idx == sc->sis_cdata.sis_tx_prod) 1295 return; 1296 1297 /* Transmit */ 1298 sc->sis_cdata.sis_tx_prod = idx; 1299 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1300 1301 /* 1302 * Set a timeout in case the chip goes out to lunch. 1303 */ 1304 ifp->if_timer = 5; 1305 1306 return; 1307 } 1308 1309 void sis_init(xsc) 1310 void *xsc; 1311 { 1312 struct sis_softc *sc = (struct sis_softc *)xsc; 1313 struct ifnet *ifp = &sc->arpcom.ac_if; 1314 struct mii_data *mii; 1315 int s; 1316 1317 s = splnet(); 1318 1319 /* 1320 * Cancel pending I/O and free all RX/TX buffers. 1321 */ 1322 sis_stop(sc); 1323 1324 mii = &sc->sc_mii; 1325 1326 /* Set MAC address */ 1327 if (sc->sis_type == SIS_TYPE_83815) { 1328 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1329 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1330 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1331 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1332 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1333 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1334 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1335 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1336 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1337 } else { 1338 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1339 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1340 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1341 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1342 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1343 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1344 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1345 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1346 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1347 } 1348 1349 /* Init circular RX list. */ 1350 if (sis_list_rx_init(sc) == ENOBUFS) { 1351 printf("sis%d: initialization failed: no " 1352 "memory for rx buffers\n", sc->sis_unit); 1353 sis_stop(sc); 1354 (void)splx(s); 1355 return; 1356 } 1357 1358 /* 1359 * Init tx descriptors. 1360 */ 1361 sis_list_tx_init(sc); 1362 1363 /* 1364 * For the NatSemi chip, we have to explicitly enable the 1365 * reception of ARP frames, as well as turn on the 'perfect 1366 * match' filter where we store the station address, otherwise 1367 * we won't receive unicasts meant for this host. 1368 */ 1369 if (sc->sis_type == SIS_TYPE_83815) { 1370 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1371 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1372 } 1373 1374 /* If we want promiscuous mode, set the allframes bit. */ 1375 if (ifp->if_flags & IFF_PROMISC) { 1376 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1377 } else { 1378 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1379 } 1380 1381 /* 1382 * Set the capture broadcast bit to capture broadcast frames. 1383 */ 1384 if (ifp->if_flags & IFF_BROADCAST) { 1385 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1386 } else { 1387 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1388 } 1389 1390 /* 1391 * Load the multicast filter. 1392 */ 1393 if (sc->sis_type == SIS_TYPE_83815) 1394 sis_setmulti_ns(sc); 1395 else 1396 sis_setmulti_sis(sc); 1397 1398 /* Turn the receive filter on */ 1399 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1400 1401 /* 1402 * Load the address of the RX and TX lists. 1403 */ 1404 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 1405 vtophys(&sc->sis_ldata->sis_rx_list[0])); 1406 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 1407 vtophys(&sc->sis_ldata->sis_tx_list[0])); 1408 1409 /* Set RX configuration */ 1410 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG); 1411 1412 /* Set TX configuration */ 1413 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 1414 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1415 else 1416 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1417 1418 /* Set full/half duplex mode. */ 1419 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1420 SIS_SETBIT(sc, SIS_TX_CFG, 1421 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1422 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1423 } else { 1424 SIS_CLRBIT(sc, SIS_TX_CFG, 1425 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1426 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1427 } 1428 1429 /* 1430 * Enable interrupts. 1431 */ 1432 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1433 CSR_WRITE_4(sc, SIS_IER, 1); 1434 1435 /* Enable receiver and transmitter. */ 1436 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1437 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1438 1439 #ifdef notdef 1440 mii_mediachg(mii); 1441 #endif 1442 1443 /* 1444 * Page 75 of the DP83815 manual recommends the 1445 * following register settings "for optimum 1446 * performance." Note however that at least three 1447 * of the registers are listed as "reserved" in 1448 * the register map, so who knows what they do. 1449 */ 1450 if (sc->sis_type == SIS_TYPE_83815) { 1451 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1452 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1453 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1454 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1455 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1456 } 1457 1458 ifp->if_flags |= IFF_RUNNING; 1459 ifp->if_flags &= ~IFF_OACTIVE; 1460 1461 (void)splx(s); 1462 1463 timeout_set(&sc->sis_timeout, sis_tick, sc); 1464 timeout_add(&sc->sis_timeout, hz); 1465 1466 return; 1467 } 1468 1469 /* 1470 * Set media options. 1471 */ 1472 int sis_ifmedia_upd(ifp) 1473 struct ifnet *ifp; 1474 { 1475 struct sis_softc *sc; 1476 struct mii_data *mii; 1477 1478 sc = ifp->if_softc; 1479 1480 mii = &sc->sc_mii; 1481 sc->sis_link = 0; 1482 if (mii->mii_instance) { 1483 struct mii_softc *miisc; 1484 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1485 mii_phy_reset(miisc); 1486 } 1487 mii_mediachg(mii); 1488 1489 return(0); 1490 } 1491 1492 /* 1493 * Report current media status. 1494 */ 1495 void sis_ifmedia_sts(ifp, ifmr) 1496 struct ifnet *ifp; 1497 struct ifmediareq *ifmr; 1498 { 1499 struct sis_softc *sc; 1500 struct mii_data *mii; 1501 1502 sc = ifp->if_softc; 1503 1504 mii = &sc->sc_mii; 1505 mii_pollstat(mii); 1506 ifmr->ifm_active = mii->mii_media_active; 1507 ifmr->ifm_status = mii->mii_media_status; 1508 1509 return; 1510 } 1511 1512 int sis_ioctl(ifp, command, data) 1513 struct ifnet *ifp; 1514 u_long command; 1515 caddr_t data; 1516 { 1517 struct sis_softc *sc = ifp->if_softc; 1518 struct ifreq *ifr = (struct ifreq *) data; 1519 struct ifaddr *ifa = (struct ifaddr *)data; 1520 struct mii_data *mii; 1521 int s, error = 0; 1522 1523 s = splnet(); 1524 1525 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 1526 splx(s); 1527 return error; 1528 } 1529 1530 switch(command) { 1531 case SIOCSIFADDR: 1532 ifp->if_flags |= IFF_UP; 1533 switch (ifa->ifa_addr->sa_family) { 1534 case AF_INET: 1535 sis_init(sc); 1536 arp_ifinit(&sc->arpcom, ifa); 1537 break; 1538 default: 1539 sis_init(sc); 1540 break; 1541 } 1542 break; 1543 case SIOCSIFFLAGS: 1544 if (ifp->if_flags & IFF_UP) { 1545 sis_init(sc); 1546 } else { 1547 if (ifp->if_flags & IFF_RUNNING) 1548 sis_stop(sc); 1549 } 1550 error = 0; 1551 break; 1552 case SIOCADDMULTI: 1553 case SIOCDELMULTI: 1554 error = (command == SIOCADDMULTI) ? 1555 ether_addmulti(ifr, &sc->arpcom) : 1556 ether_delmulti(ifr, &sc->arpcom); 1557 1558 if (error == ENETRESET) { 1559 /* 1560 * Multicast list has changed; set the hardware 1561 * filter accordingly. 1562 */ 1563 if (sc->sis_type == SIS_TYPE_83815) 1564 sis_setmulti_ns(sc); 1565 else 1566 sis_setmulti_sis(sc); 1567 error = 0; 1568 } 1569 break; 1570 case SIOCGIFMEDIA: 1571 case SIOCSIFMEDIA: 1572 mii = &sc->sc_mii; 1573 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1574 break; 1575 default: 1576 error = EINVAL; 1577 break; 1578 } 1579 1580 (void)splx(s); 1581 1582 return(error); 1583 } 1584 1585 void sis_watchdog(ifp) 1586 struct ifnet *ifp; 1587 { 1588 struct sis_softc *sc; 1589 int s; 1590 1591 sc = ifp->if_softc; 1592 1593 ifp->if_oerrors++; 1594 printf("sis%d: watchdog timeout\n", sc->sis_unit); 1595 1596 s = splnet(); 1597 sis_stop(sc); 1598 sis_reset(sc); 1599 sis_init(sc); 1600 1601 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1602 sis_start(ifp); 1603 1604 splx(s); 1605 return; 1606 } 1607 1608 /* 1609 * Stop the adapter and free any mbufs allocated to the 1610 * RX and TX lists. 1611 */ 1612 void sis_stop(sc) 1613 struct sis_softc *sc; 1614 { 1615 register int i; 1616 struct ifnet *ifp; 1617 1618 ifp = &sc->arpcom.ac_if; 1619 ifp->if_timer = 0; 1620 1621 timeout_del(&sc->sis_timeout); 1622 CSR_WRITE_4(sc, SIS_IER, 0); 1623 CSR_WRITE_4(sc, SIS_IMR, 0); 1624 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1625 DELAY(1000); 1626 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 1627 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 1628 1629 sc->sis_link = 0; 1630 1631 /* 1632 * Free data in the RX lists. 1633 */ 1634 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1635 if (sc->sis_ldata->sis_rx_list[i].sis_mbuf != NULL) { 1636 m_freem(sc->sis_ldata->sis_rx_list[i].sis_mbuf); 1637 sc->sis_ldata->sis_rx_list[i].sis_mbuf = NULL; 1638 } 1639 } 1640 bzero((char *)&sc->sis_ldata->sis_rx_list, 1641 sizeof(sc->sis_ldata->sis_rx_list)); 1642 1643 /* 1644 * Free the TX list buffers. 1645 */ 1646 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1647 if (sc->sis_ldata->sis_tx_list[i].sis_mbuf != NULL) { 1648 m_freem(sc->sis_ldata->sis_tx_list[i].sis_mbuf); 1649 sc->sis_ldata->sis_tx_list[i].sis_mbuf = NULL; 1650 } 1651 } 1652 1653 bzero((char *)&sc->sis_ldata->sis_tx_list, 1654 sizeof(sc->sis_ldata->sis_tx_list)); 1655 1656 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1657 1658 return; 1659 } 1660 1661 /* 1662 * Stop all chip I/O so that the kernel's probe routines don't 1663 * get confused by errant DMAs when rebooting. 1664 */ 1665 void sis_shutdown(v) 1666 void *v; 1667 { 1668 struct sis_softc *sc = (struct sis_softc *)v; 1669 1670 sis_stop(sc); 1671 } 1672 1673 struct cfattach sis_ca = { 1674 sizeof(struct sis_softc), sis_probe, sis_attach 1675 }; 1676 1677 struct cfdriver sis_cd = { 1678 0, "sis", DV_IFNET 1679 }; 1680 1681