1 /* $OpenBSD: if_sis.c,v 1.34 2003/10/30 22:10:25 deraadt Exp $ */ 2 /* 3 * Copyright (c) 1997, 1998, 1999 4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/pci/if_sis.c,v 1.30 2001/02/06 10:11:47 phk Exp $ 34 */ 35 36 /* 37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 38 * available from http://www.sis.com.tw. 39 * 40 * This driver also supports the NatSemi DP83815. Datasheets are 41 * available from http://www.national.com. 42 * 43 * Written by Bill Paul <wpaul@ee.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61 #include "bpfilter.h" 62 #include "vlan.h" 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/mbuf.h> 67 #include <sys/protosw.h> 68 #include <sys/socket.h> 69 #include <sys/ioctl.h> 70 #include <sys/errno.h> 71 #include <sys/malloc.h> 72 #include <sys/kernel.h> 73 #include <sys/timeout.h> 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #ifdef INET 80 #include <netinet/in.h> 81 #include <netinet/in_systm.h> 82 #include <netinet/in_var.h> 83 #include <netinet/ip.h> 84 #include <netinet/if_ether.h> 85 #endif 86 87 #include <net/if_media.h> 88 89 #if NBPFILTER > 0 90 #include <net/bpf.h> 91 #endif 92 93 #include <sys/device.h> 94 95 #include <dev/mii/mii.h> 96 #include <dev/mii/miivar.h> 97 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pcivar.h> 100 #include <dev/pci/pcidevs.h> 101 102 #define SIS_USEIOSPACE 103 104 #include <dev/pci/if_sisreg.h> 105 106 int sis_probe(struct device *, void *, void *); 107 void sis_attach(struct device *, struct device *, void *); 108 int sis_intr(void *); 109 void sis_shutdown(void *); 110 int sis_newbuf(struct sis_softc *, struct sis_desc *, 111 struct mbuf *); 112 int sis_encap(struct sis_softc *, struct mbuf *, u_int32_t *); 113 void sis_rxeof(struct sis_softc *); 114 void sis_rxeoc(struct sis_softc *); 115 void sis_txeof(struct sis_softc *); 116 void sis_tick(void *); 117 void sis_start(struct ifnet *); 118 int sis_ioctl(struct ifnet *, u_long, caddr_t); 119 void sis_init(void *); 120 void sis_stop(struct sis_softc *); 121 void sis_watchdog(struct ifnet *); 122 int sis_ifmedia_upd(struct ifnet *); 123 void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 124 125 u_int16_t sis_reverse(u_int16_t); 126 void sis_delay(struct sis_softc *); 127 void sis_eeprom_idle(struct sis_softc *); 128 void sis_eeprom_putbyte(struct sis_softc *, int); 129 void sis_eeprom_getword(struct sis_softc *, int, u_int16_t *); 130 #ifdef __i386__ 131 void sis_read_cmos(struct sis_softc *, struct pci_attach_args *, caddr_t, int, int); 132 #endif 133 void sis_read_mac(struct sis_softc *, struct pci_attach_args *); 134 void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int); 135 136 void sis_mii_sync(struct sis_softc *); 137 void sis_mii_send(struct sis_softc *, u_int32_t, int); 138 int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *); 139 int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *); 140 int sis_miibus_readreg(struct device *, int, int); 141 void sis_miibus_writereg(struct device *, int, int, int); 142 void sis_miibus_statchg(struct device *); 143 144 void sis_setmulti_sis(struct sis_softc *); 145 void sis_setmulti_ns(struct sis_softc *); 146 u_int32_t sis_crc(struct sis_softc *, caddr_t); 147 void sis_reset(struct sis_softc *); 148 int sis_list_rx_init(struct sis_softc *); 149 int sis_list_tx_init(struct sis_softc *); 150 151 #define SIS_SETBIT(sc, reg, x) \ 152 CSR_WRITE_4(sc, reg, \ 153 CSR_READ_4(sc, reg) | (x)) 154 155 #define SIS_CLRBIT(sc, reg, x) \ 156 CSR_WRITE_4(sc, reg, \ 157 CSR_READ_4(sc, reg) & ~(x)) 158 159 #define SIO_SET(x) \ 160 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 161 162 #define SIO_CLR(x) \ 163 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 164 165 /* 166 * Routine to reverse the bits in a word. Stolen almost 167 * verbatim from /usr/games/fortune. 168 */ 169 u_int16_t sis_reverse(n) 170 u_int16_t n; 171 { 172 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 173 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 174 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 175 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 176 177 return(n); 178 } 179 180 void sis_delay(sc) 181 struct sis_softc *sc; 182 { 183 int idx; 184 185 for (idx = (300 / 33) + 1; idx > 0; idx--) 186 CSR_READ_4(sc, SIS_CSR); 187 188 return; 189 } 190 191 void sis_eeprom_idle(sc) 192 struct sis_softc *sc; 193 { 194 register int i; 195 196 SIO_SET(SIS_EECTL_CSEL); 197 sis_delay(sc); 198 SIO_SET(SIS_EECTL_CLK); 199 sis_delay(sc); 200 201 for (i = 0; i < 25; i++) { 202 SIO_CLR(SIS_EECTL_CLK); 203 sis_delay(sc); 204 SIO_SET(SIS_EECTL_CLK); 205 sis_delay(sc); 206 } 207 208 SIO_CLR(SIS_EECTL_CLK); 209 sis_delay(sc); 210 SIO_CLR(SIS_EECTL_CSEL); 211 sis_delay(sc); 212 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 213 214 return; 215 } 216 217 /* 218 * Send a read command and address to the EEPROM, check for ACK. 219 */ 220 void sis_eeprom_putbyte(sc, addr) 221 struct sis_softc *sc; 222 int addr; 223 { 224 register int d, i; 225 226 d = addr | SIS_EECMD_READ; 227 228 /* 229 * Feed in each bit and strobe the clock. 230 */ 231 for (i = 0x400; i; i >>= 1) { 232 if (d & i) { 233 SIO_SET(SIS_EECTL_DIN); 234 } else { 235 SIO_CLR(SIS_EECTL_DIN); 236 } 237 sis_delay(sc); 238 SIO_SET(SIS_EECTL_CLK); 239 sis_delay(sc); 240 SIO_CLR(SIS_EECTL_CLK); 241 sis_delay(sc); 242 } 243 244 return; 245 } 246 247 /* 248 * Read a word of data stored in the EEPROM at address 'addr.' 249 */ 250 void sis_eeprom_getword(sc, addr, dest) 251 struct sis_softc *sc; 252 int addr; 253 u_int16_t *dest; 254 { 255 register int i; 256 u_int16_t word = 0; 257 258 /* Force EEPROM to idle state. */ 259 sis_eeprom_idle(sc); 260 261 /* Enter EEPROM access mode. */ 262 sis_delay(sc); 263 SIO_CLR(SIS_EECTL_CLK); 264 sis_delay(sc); 265 SIO_SET(SIS_EECTL_CSEL); 266 sis_delay(sc); 267 268 /* 269 * Send address of word we want to read. 270 */ 271 sis_eeprom_putbyte(sc, addr); 272 273 /* 274 * Start reading bits from EEPROM. 275 */ 276 for (i = 0x8000; i; i >>= 1) { 277 SIO_SET(SIS_EECTL_CLK); 278 sis_delay(sc); 279 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 280 word |= i; 281 sis_delay(sc); 282 SIO_CLR(SIS_EECTL_CLK); 283 sis_delay(sc); 284 } 285 286 /* Turn off EEPROM access mode. */ 287 sis_eeprom_idle(sc); 288 289 *dest = word; 290 291 return; 292 } 293 294 /* 295 * Read a sequence of words from the EEPROM. 296 */ 297 void sis_read_eeprom(sc, dest, off, cnt, swap) 298 struct sis_softc *sc; 299 caddr_t dest; 300 int off; 301 int cnt; 302 int swap; 303 { 304 int i; 305 u_int16_t word = 0, *ptr; 306 307 for (i = 0; i < cnt; i++) { 308 sis_eeprom_getword(sc, off + i, &word); 309 ptr = (u_int16_t *)(dest + (i * 2)); 310 if (swap) 311 *ptr = ntohs(word); 312 else 313 *ptr = word; 314 } 315 316 return; 317 } 318 319 #ifdef __i386__ 320 void sis_read_cmos(sc, pa, dest, off, cnt) 321 struct sis_softc *sc; 322 struct pci_attach_args *pa; 323 caddr_t dest; 324 int off, cnt; 325 { 326 bus_space_tag_t btag; 327 u_int32_t reg; 328 int i; 329 330 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x48); 331 pci_conf_write(pa->pa_pc, pa->pa_tag, 0x48, reg | 0x40); 332 333 btag = I386_BUS_SPACE_IO; 334 335 for (i = 0; i < cnt; i++) { 336 bus_space_write_1(btag, 0x0, 0x70, i + off); 337 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 338 } 339 340 pci_conf_write(pa->pa_pc, pa->pa_tag, 0x48, reg & ~0x40); 341 } 342 #endif 343 344 void sis_read_mac(sc, pa) 345 struct sis_softc *sc; 346 struct pci_attach_args *pa; 347 { 348 u_int16_t *enaddr = (u_int16_t *) &sc->arpcom.ac_enaddr; 349 350 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RELOAD); 351 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_RELOAD); 352 353 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 354 355 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 356 enaddr[0] = CSR_READ_4(sc, SIS_RXFILT_DATA) & 0xffff; 357 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 358 enaddr[1] = CSR_READ_4(sc, SIS_RXFILT_DATA) & 0xffff; 359 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 360 enaddr[2] = CSR_READ_4(sc, SIS_RXFILT_DATA) & 0xffff; 361 362 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 363 } 364 365 /* 366 * Sync the PHYs by setting data bit and strobing the clock 32 times. 367 */ 368 void sis_mii_sync(sc) 369 struct sis_softc *sc; 370 { 371 register int i; 372 373 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 374 375 for (i = 0; i < 32; i++) { 376 SIO_SET(SIS_MII_CLK); 377 DELAY(1); 378 SIO_CLR(SIS_MII_CLK); 379 DELAY(1); 380 } 381 382 return; 383 } 384 385 /* 386 * Clock a series of bits through the MII. 387 */ 388 void sis_mii_send(sc, bits, cnt) 389 struct sis_softc *sc; 390 u_int32_t bits; 391 int cnt; 392 { 393 int i; 394 395 SIO_CLR(SIS_MII_CLK); 396 397 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 398 if (bits & i) { 399 SIO_SET(SIS_MII_DATA); 400 } else { 401 SIO_CLR(SIS_MII_DATA); 402 } 403 DELAY(1); 404 SIO_CLR(SIS_MII_CLK); 405 DELAY(1); 406 SIO_SET(SIS_MII_CLK); 407 } 408 } 409 410 /* 411 * Read an PHY register through the MII. 412 */ 413 int sis_mii_readreg(sc, frame) 414 struct sis_softc *sc; 415 struct sis_mii_frame *frame; 416 417 { 418 int i, ack, s; 419 420 s = splimp(); 421 422 /* 423 * Set up frame for RX. 424 */ 425 frame->mii_stdelim = SIS_MII_STARTDELIM; 426 frame->mii_opcode = SIS_MII_READOP; 427 frame->mii_turnaround = 0; 428 frame->mii_data = 0; 429 430 /* 431 * Turn on data xmit. 432 */ 433 SIO_SET(SIS_MII_DIR); 434 435 sis_mii_sync(sc); 436 437 /* 438 * Send command/address info. 439 */ 440 sis_mii_send(sc, frame->mii_stdelim, 2); 441 sis_mii_send(sc, frame->mii_opcode, 2); 442 sis_mii_send(sc, frame->mii_phyaddr, 5); 443 sis_mii_send(sc, frame->mii_regaddr, 5); 444 445 /* Idle bit */ 446 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 447 DELAY(1); 448 SIO_SET(SIS_MII_CLK); 449 DELAY(1); 450 451 /* Turn off xmit. */ 452 SIO_CLR(SIS_MII_DIR); 453 454 /* Check for ack */ 455 SIO_CLR(SIS_MII_CLK); 456 DELAY(1); 457 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 458 SIO_SET(SIS_MII_CLK); 459 DELAY(1); 460 461 /* 462 * Now try reading data bits. If the ack failed, we still 463 * need to clock through 16 cycles to keep the PHY(s) in sync. 464 */ 465 if (ack) { 466 for(i = 0; i < 16; i++) { 467 SIO_CLR(SIS_MII_CLK); 468 DELAY(1); 469 SIO_SET(SIS_MII_CLK); 470 DELAY(1); 471 } 472 goto fail; 473 } 474 475 for (i = 0x8000; i; i >>= 1) { 476 SIO_CLR(SIS_MII_CLK); 477 DELAY(1); 478 if (!ack) { 479 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 480 frame->mii_data |= i; 481 DELAY(1); 482 } 483 SIO_SET(SIS_MII_CLK); 484 DELAY(1); 485 } 486 487 fail: 488 489 SIO_CLR(SIS_MII_CLK); 490 DELAY(1); 491 SIO_SET(SIS_MII_CLK); 492 DELAY(1); 493 494 splx(s); 495 496 if (ack) 497 return(1); 498 return(0); 499 } 500 501 /* 502 * Write to a PHY register through the MII. 503 */ 504 int sis_mii_writereg(sc, frame) 505 struct sis_softc *sc; 506 struct sis_mii_frame *frame; 507 508 { 509 int s; 510 511 s = splimp(); 512 /* 513 * Set up frame for TX. 514 */ 515 516 frame->mii_stdelim = SIS_MII_STARTDELIM; 517 frame->mii_opcode = SIS_MII_WRITEOP; 518 frame->mii_turnaround = SIS_MII_TURNAROUND; 519 520 /* 521 * Turn on data output. 522 */ 523 SIO_SET(SIS_MII_DIR); 524 525 sis_mii_sync(sc); 526 527 sis_mii_send(sc, frame->mii_stdelim, 2); 528 sis_mii_send(sc, frame->mii_opcode, 2); 529 sis_mii_send(sc, frame->mii_phyaddr, 5); 530 sis_mii_send(sc, frame->mii_regaddr, 5); 531 sis_mii_send(sc, frame->mii_turnaround, 2); 532 sis_mii_send(sc, frame->mii_data, 16); 533 534 /* Idle bit. */ 535 SIO_SET(SIS_MII_CLK); 536 DELAY(1); 537 SIO_CLR(SIS_MII_CLK); 538 DELAY(1); 539 540 /* 541 * Turn off xmit. 542 */ 543 SIO_CLR(SIS_MII_DIR); 544 545 splx(s); 546 547 return(0); 548 } 549 550 int sis_miibus_readreg(self, phy, reg) 551 struct device *self; 552 int phy, reg; 553 { 554 struct sis_softc *sc = (struct sis_softc *)self; 555 struct sis_mii_frame frame; 556 557 if (sc->sis_type == SIS_TYPE_83815) { 558 if (phy != 0) 559 return(0); 560 /* 561 * The NatSemi chip can take a while after 562 * a reset to come ready, during which the BMSR 563 * returns a value of 0. This is *never* supposed 564 * to happen: some of the BMSR bits are meant to 565 * be hardwired in the on position, and this can 566 * confuse the miibus code a bit during the probe 567 * and attach phase. So we make an effort to check 568 * for this condition and wait for it to clear. 569 */ 570 if (!CSR_READ_4(sc, NS_BMSR)) 571 DELAY(1000); 572 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 573 } 574 575 /* 576 * Chipsets < SIS_635 seem not to be able to read/write 577 * through mdio. Use the enhanced PHY access register 578 * again for them. 579 */ 580 if (sc->sis_type == SIS_TYPE_900 && 581 sc->sis_rev < SIS_REV_635) { 582 int i, val = 0; 583 584 if (phy != 0) 585 return(0); 586 587 CSR_WRITE_4(sc, SIS_PHYCTL, 588 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 589 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 590 591 for (i = 0; i < SIS_TIMEOUT; i++) { 592 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 593 break; 594 } 595 596 if (i == SIS_TIMEOUT) { 597 printf("%s: PHY failed to come ready\n", 598 sc->sc_dev.dv_xname); 599 return(0); 600 } 601 602 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 603 604 if (val == 0xFFFF) 605 return(0); 606 607 return(val); 608 } else { 609 bzero((char *)&frame, sizeof(frame)); 610 611 frame.mii_phyaddr = phy; 612 frame.mii_regaddr = reg; 613 sis_mii_readreg(sc, &frame); 614 615 return(frame.mii_data); 616 } 617 } 618 619 620 void sis_miibus_writereg(self, phy, reg, data) 621 struct device *self; 622 int phy, reg, data; 623 { 624 struct sis_softc *sc = (struct sis_softc *)self; 625 struct sis_mii_frame frame; 626 627 if (sc->sis_type == SIS_TYPE_83815) { 628 if (phy != 0) 629 return; 630 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 631 return; 632 } 633 634 /* 635 * Chipsets < SIS_635 seem not to be able to read/write 636 * through mdio. Use the enhanced PHY access register 637 * again for them. 638 */ 639 if (sc->sis_type == SIS_TYPE_900 && 640 sc->sis_rev < SIS_REV_635) { 641 int i; 642 643 if (phy != 0) 644 return; 645 646 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 647 (reg << 6) | SIS_PHYOP_WRITE); 648 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 649 650 for (i = 0; i < SIS_TIMEOUT; i++) { 651 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 652 break; 653 } 654 655 if (i == SIS_TIMEOUT) 656 printf("%s: PHY failed to come ready\n", 657 sc->sc_dev.dv_xname); 658 } else { 659 bzero((char *)&frame, sizeof(frame)); 660 661 frame.mii_phyaddr = phy; 662 frame.mii_regaddr = reg; 663 frame.mii_data = data; 664 sis_mii_writereg(sc, &frame); 665 } 666 return; 667 } 668 669 void 670 sis_miibus_statchg(self) 671 struct device *self; 672 { 673 struct sis_softc *sc = (struct sis_softc *)self; 674 675 sis_init(sc); 676 677 return; 678 } 679 680 u_int32_t sis_crc(sc, addr) 681 struct sis_softc *sc; 682 caddr_t addr; 683 { 684 u_int32_t crc, carry; 685 int i, j; 686 u_int8_t c; 687 688 /* Compute CRC for the address value. */ 689 crc = 0xFFFFFFFF; /* initial value */ 690 691 for (i = 0; i < 6; i++) { 692 c = *(addr + i); 693 for (j = 0; j < 8; j++) { 694 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 695 crc <<= 1; 696 c >>= 1; 697 if (carry) 698 crc = (crc ^ 0x04c11db6) | carry; 699 } 700 } 701 702 /* 703 * return the filter bit position 704 * 705 * The NatSemi chip has a 512-bit filter, which is 706 * different than the SiS, so we special-case it. 707 */ 708 if (sc->sis_type == SIS_TYPE_83815) 709 return((crc >> 23) & 0x1FF); 710 711 return((crc >> 25) & 0x0000007F); 712 } 713 714 void sis_setmulti_ns(sc) 715 struct sis_softc *sc; 716 { 717 struct ifnet *ifp; 718 struct arpcom *ac = &sc->arpcom; 719 struct ether_multi *enm; 720 struct ether_multistep step; 721 u_int32_t h = 0, i, filtsave; 722 int bit, index; 723 724 ifp = &sc->arpcom.ac_if; 725 726 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 727 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 728 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 729 return; 730 } 731 732 /* 733 * We have to explicitly enable the multicast hash table 734 * on the NatSemi chip if we want to use it, which we do. 735 */ 736 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 737 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 738 739 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 740 741 /* first, zot all the existing hash bits */ 742 for (i = 0; i < 32; i++) { 743 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 744 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 745 } 746 747 ETHER_FIRST_MULTI(step, ac, enm); 748 while (enm != NULL) { 749 h = sis_crc(sc, enm->enm_addrlo); 750 index = h >> 3; 751 bit = h & 0x1F; 752 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 753 if (bit > 0xF) 754 bit -= 0x10; 755 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 756 ETHER_NEXT_MULTI(step, enm); 757 } 758 759 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 760 761 return; 762 } 763 764 void sis_setmulti_sis(sc) 765 struct sis_softc *sc; 766 { 767 struct ifnet *ifp; 768 struct arpcom *ac = &sc->arpcom; 769 struct ether_multi *enm; 770 struct ether_multistep step; 771 u_int32_t h = 0, i, filtsave; 772 773 ifp = &sc->arpcom.ac_if; 774 775 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 776 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 777 return; 778 } 779 780 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 781 782 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 783 784 /* first, zot all the existing hash bits */ 785 for (i = 0; i < 8; i++) { 786 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + ((i * 16) >> 4)) << 16); 787 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 788 } 789 790 /* now program new ones */ 791 ETHER_FIRST_MULTI(step, ac, enm); 792 while (enm != NULL) { 793 h = sis_crc(sc, enm->enm_addrlo); 794 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + (h >> 4)) << 16); 795 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << (h & 0xF))); 796 ETHER_NEXT_MULTI(step, enm); 797 } 798 799 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 800 801 return; 802 } 803 804 void sis_reset(sc) 805 struct sis_softc *sc; 806 { 807 register int i; 808 809 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 810 811 for (i = 0; i < SIS_TIMEOUT; i++) { 812 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 813 break; 814 } 815 816 if (i == SIS_TIMEOUT) 817 printf("%s: reset never completed\n", sc->sc_dev.dv_xname); 818 819 /* Wait a little while for the chip to get its brains in order. */ 820 DELAY(1000); 821 822 /* 823 * If this is a NetSemi chip, make sure to clear 824 * PME mode. 825 */ 826 if (sc->sis_type == SIS_TYPE_83815) { 827 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 828 CSR_WRITE_4(sc, NS_CLKRUN, 0); 829 } 830 831 return; 832 } 833 834 const struct pci_matchid sis_devices[] = { 835 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900 }, 836 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016 }, 837 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815 }, 838 }; 839 840 /* 841 * Probe for an SiS chip. Check the PCI vendor and device 842 * IDs against our list and return a device name if we find a match. 843 */ 844 int sis_probe(parent, match, aux) 845 struct device *parent; 846 void *match; 847 void *aux; 848 { 849 return (pci_matchbyid((struct pci_attach_args *)aux, sis_devices, 850 sizeof(sis_devices)/sizeof(sis_devices[0]))); 851 } 852 853 /* 854 * Attach the interface. Allocate softc structures, do ifmedia 855 * setup and ethernet/BPF attach. 856 */ 857 void sis_attach(parent, self, aux) 858 struct device *parent, *self; 859 void *aux; 860 { 861 int i, s; 862 const char *intrstr = NULL; 863 u_int32_t command; 864 struct sis_softc *sc = (struct sis_softc *)self; 865 struct pci_attach_args *pa = aux; 866 pci_chipset_tag_t pc = pa->pa_pc; 867 pci_intr_handle_t ih; 868 struct ifnet *ifp; 869 bus_addr_t iobase; 870 bus_size_t iosize; 871 872 s = splnet(); 873 874 switch (PCI_PRODUCT(pa->pa_id)) { 875 case PCI_PRODUCT_SIS_900: 876 sc->sis_type = SIS_TYPE_900; 877 break; 878 case PCI_PRODUCT_SIS_7016: 879 sc->sis_type = SIS_TYPE_7016; 880 break; 881 case PCI_PRODUCT_NS_DP83815: 882 sc->sis_type = SIS_TYPE_83815; 883 break; 884 default: 885 break; 886 } 887 888 /* 889 * Handle power management nonsense. 890 */ 891 command = pci_conf_read(pc, pa->pa_tag, SIS_PCI_CAPID) & 0x000000FF; 892 if (command == 0x01) { 893 894 command = pci_conf_read(pc, pa->pa_tag, SIS_PCI_PWRMGMTCTRL); 895 if (command & SIS_PSTATE_MASK) { 896 u_int32_t iobase, membase, irq; 897 898 /* Save important PCI config data. */ 899 iobase = pci_conf_read(pc, pa->pa_tag, SIS_PCI_LOIO); 900 membase = pci_conf_read(pc, pa->pa_tag, SIS_PCI_LOMEM); 901 irq = pci_conf_read(pc, pa->pa_tag, SIS_PCI_INTLINE); 902 903 /* Reset the power state. */ 904 printf("%s: chip is in D%d power mode -- setting to D0\n", 905 sc->sc_dev.dv_xname, command & SIS_PSTATE_MASK); 906 command &= 0xFFFFFFFC; 907 pci_conf_write(pc, pa->pa_tag, SIS_PCI_PWRMGMTCTRL, command); 908 909 /* Restore PCI config data. */ 910 pci_conf_write(pc, pa->pa_tag, SIS_PCI_LOIO, iobase); 911 pci_conf_write(pc, pa->pa_tag, SIS_PCI_LOMEM, membase); 912 pci_conf_write(pc, pa->pa_tag, SIS_PCI_INTLINE, irq); 913 } 914 } 915 916 /* 917 * Map control/status registers. 918 */ 919 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 920 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 921 PCI_COMMAND_MASTER_ENABLE; 922 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 923 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 924 925 #ifdef SIS_USEIOSPACE 926 if (!(command & PCI_COMMAND_IO_ENABLE)) { 927 printf(": failed to enable I/O ports\n"); 928 goto fail; 929 } 930 if (pci_io_find(pc, pa->pa_tag, SIS_PCI_LOIO, &iobase, &iosize)) { 931 printf(": can't find I/O space\n"); 932 goto fail; 933 } 934 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->sis_bhandle)) { 935 printf(": can't map I/O space\n"); 936 goto fail; 937 } 938 sc->sis_btag = pa->pa_iot; 939 #else 940 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 941 printf(": failed to enable memory mapping\n"); 942 goto fail; 943 } 944 if (pci_mem_find(pc, pa->pa_tag, SIS_PCI_LOMEM, &iobase, &iosize,NULL)){ 945 printf(": can't find mem space\n"); 946 goto fail; 947 } 948 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->sis_bhandle)) { 949 printf(": can't map mem space\n"); 950 goto fail; 951 } 952 sc->sis_btag = pa->pa_memt; 953 #endif 954 955 /* Allocate interrupt */ 956 if (pci_intr_map(pa, &ih)) { 957 printf(": couldn't map interrupt\n"); 958 goto fail; 959 } 960 intrstr = pci_intr_string(pc, ih); 961 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sis_intr, sc, 962 self->dv_xname); 963 if (sc->sc_ih == NULL) { 964 printf(": couldn't establish interrupt"); 965 if (intrstr != NULL) 966 printf(" at %s", intrstr); 967 printf("\n"); 968 goto fail; 969 } 970 printf(": %s", intrstr); 971 972 sc->sis_rev = PCI_REVISION(pa->pa_class); 973 974 /* Reset the adapter. */ 975 sis_reset(sc); 976 977 /* 978 * Get station address from the EEPROM. 979 */ 980 switch (PCI_VENDOR(pa->pa_id)) { 981 case PCI_VENDOR_NS: 982 /* 983 * Reading the MAC address out of the EEPROM on 984 * the NatSemi chip takes a bit more work than 985 * you'd expect. The address spans 4 16-bit words, 986 * with the first word containing only a single bit. 987 * You have to shift everything over one bit to 988 * get it aligned properly. Also, the bits are 989 * stored backwards (the LSB is really the MSB, 990 * and so on) so you have to reverse them in order 991 * to get the MAC address into the form we want. 992 * Why? Who the hell knows. 993 */ 994 { 995 u_int16_t tmp[4]; 996 997 sis_read_eeprom(sc, (caddr_t)&tmp, NS_EE_NODEADDR,4,0); 998 999 /* Shift everything over one bit. */ 1000 tmp[3] = tmp[3] >> 1; 1001 tmp[3] |= tmp[2] << 15; 1002 tmp[2] = tmp[2] >> 1; 1003 tmp[2] |= tmp[1] << 15; 1004 tmp[1] = tmp[1] >> 1; 1005 tmp[1] |= tmp[0] << 15; 1006 1007 /* Now reverse all the bits. */ 1008 tmp[3] = sis_reverse(tmp[3]); 1009 tmp[2] = sis_reverse(tmp[2]); 1010 tmp[1] = sis_reverse(tmp[1]); 1011 1012 bcopy((char *)&tmp[1], sc->arpcom.ac_enaddr, 1013 ETHER_ADDR_LEN); 1014 } 1015 break; 1016 case PCI_VENDOR_SIS: 1017 default: 1018 #ifdef __i386__ 1019 /* 1020 * If this is a SiS 630E chipset with an embedded 1021 * SiS 900 controller, we have to read the MAC address 1022 * from the APC CMOS RAM. Our method for doing this 1023 * is very ugly since we have to reach out and grab 1024 * ahold of hardware for which we cannot properly 1025 * allocate resources. This code is only compiled on 1026 * the i386 architecture since the SiS 630E chipset 1027 * is for x86 motherboards only. Note that there are 1028 * a lot of magic numbers in this hack. These are 1029 * taken from SiS's Linux driver. I'd like to replace 1030 * them with proper symbolic definitions, but that 1031 * requires some datasheets that I don't have access 1032 * to at the moment. 1033 */ 1034 if (sc->sis_rev == SIS_REV_630S || 1035 sc->sis_rev == SIS_REV_630E) 1036 sis_read_cmos(sc, pa, (caddr_t)&sc->arpcom.ac_enaddr, 1037 0x9, 6); 1038 else 1039 #endif 1040 if (sc->sis_rev == SIS_REV_635 || 1041 sc->sis_rev == SIS_REV_630ET || 1042 sc->sis_rev == SIS_REV_630EA1) 1043 sis_read_mac(sc, pa); 1044 else 1045 sis_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1046 SIS_EE_NODEADDR, 3, 0); 1047 break; 1048 } 1049 1050 printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); 1051 1052 sc->sc_dmat = pa->pa_dmat; 1053 1054 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct sis_list_data), 1055 PAGE_SIZE, 0, sc->sc_listseg, 1, &sc->sc_listnseg, 1056 BUS_DMA_NOWAIT) != 0) { 1057 printf(": can't alloc list mem\n"); 1058 return; 1059 } 1060 if (bus_dmamem_map(sc->sc_dmat, sc->sc_listseg, sc->sc_listnseg, 1061 sizeof(struct sis_list_data), &sc->sc_listkva, 1062 BUS_DMA_NOWAIT) != 0) { 1063 printf(": can't map list mem\n"); 1064 return; 1065 } 1066 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct sis_list_data), 1, 1067 sizeof(struct sis_list_data), 0, BUS_DMA_NOWAIT, 1068 &sc->sc_listmap) != 0) { 1069 printf(": can't alloc list map\n"); 1070 return; 1071 } 1072 if (bus_dmamap_load(sc->sc_dmat, sc->sc_listmap, sc->sc_listkva, 1073 sizeof(struct sis_list_data), NULL, BUS_DMA_NOWAIT) != 0) { 1074 printf(": can't load list map\n"); 1075 return; 1076 } 1077 sc->sis_ldata = (struct sis_list_data *)sc->sc_listkva; 1078 bzero(sc->sis_ldata, sizeof(struct sis_list_data)); 1079 1080 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1081 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1082 BUS_DMA_NOWAIT, &sc->sis_ldata->sis_rx_list[i].map) != 0) { 1083 printf(": can't create rx map\n"); 1084 return; 1085 } 1086 } 1087 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1088 BUS_DMA_NOWAIT, &sc->sc_rx_sparemap) != 0) { 1089 printf(": can't create rx spare map\n"); 1090 return; 1091 } 1092 1093 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1094 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1095 SIS_TX_LIST_CNT - 3, MCLBYTES, 0, BUS_DMA_NOWAIT, 1096 &sc->sis_ldata->sis_tx_list[i].map) != 0) { 1097 printf(": can't create tx map\n"); 1098 return; 1099 } 1100 } 1101 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, SIS_TX_LIST_CNT - 3, 1102 MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->sc_tx_sparemap) != 0) { 1103 printf(": can't create tx spare map\n"); 1104 return; 1105 } 1106 1107 ifp = &sc->arpcom.ac_if; 1108 ifp->if_softc = sc; 1109 ifp->if_mtu = ETHERMTU; 1110 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1111 ifp->if_ioctl = sis_ioctl; 1112 ifp->if_output = ether_output; 1113 ifp->if_start = sis_start; 1114 ifp->if_watchdog = sis_watchdog; 1115 ifp->if_baudrate = 10000000; 1116 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1117 IFQ_SET_READY(&ifp->if_snd); 1118 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1119 1120 #if NVLAN > 0 1121 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1122 #endif 1123 1124 sc->sc_mii.mii_ifp = ifp; 1125 sc->sc_mii.mii_readreg = sis_miibus_readreg; 1126 sc->sc_mii.mii_writereg = sis_miibus_writereg; 1127 sc->sc_mii.mii_statchg = sis_miibus_statchg; 1128 ifmedia_init(&sc->sc_mii.mii_media, 0, sis_ifmedia_upd,sis_ifmedia_sts); 1129 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 1130 0); 1131 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1132 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1133 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1134 } else 1135 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1136 1137 /* 1138 * Call MI attach routines. 1139 */ 1140 if_attach(ifp); 1141 ether_ifattach(ifp); 1142 1143 shutdownhook_establish(sis_shutdown, sc); 1144 1145 fail: 1146 splx(s); 1147 return; 1148 } 1149 1150 /* 1151 * Initialize the transmit descriptors. 1152 */ 1153 int sis_list_tx_init(sc) 1154 struct sis_softc *sc; 1155 { 1156 struct sis_list_data *ld; 1157 struct sis_ring_data *cd; 1158 int i; 1159 bus_addr_t next; 1160 1161 cd = &sc->sis_cdata; 1162 ld = sc->sis_ldata; 1163 1164 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1165 next = sc->sc_listmap->dm_segs[0].ds_addr; 1166 if (i == (SIS_TX_LIST_CNT - 1)) { 1167 ld->sis_tx_list[i].sis_nextdesc = 1168 &ld->sis_tx_list[0]; 1169 next += 1170 offsetof(struct sis_list_data, sis_tx_list[0]); 1171 } else { 1172 ld->sis_tx_list[i].sis_nextdesc = 1173 &ld->sis_tx_list[i+1]; 1174 next += 1175 offsetof(struct sis_list_data, sis_tx_list[i+1]); 1176 } 1177 ld->sis_tx_list[i].sis_next = next; 1178 ld->sis_tx_list[i].sis_mbuf = NULL; 1179 ld->sis_tx_list[i].sis_ptr = 0; 1180 ld->sis_tx_list[i].sis_ctl = 0; 1181 } 1182 1183 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1184 1185 return(0); 1186 } 1187 1188 1189 /* 1190 * Initialize the RX descriptors and allocate mbufs for them. Note that 1191 * we arrange the descriptors in a closed ring, so that the last descriptor 1192 * points back to the first. 1193 */ 1194 int sis_list_rx_init(sc) 1195 struct sis_softc *sc; 1196 { 1197 struct sis_list_data *ld; 1198 struct sis_ring_data *cd; 1199 int i; 1200 bus_addr_t next; 1201 1202 ld = sc->sis_ldata; 1203 cd = &sc->sis_cdata; 1204 1205 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1206 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1207 return(ENOBUFS); 1208 next = sc->sc_listmap->dm_segs[0].ds_addr; 1209 if (i == (SIS_RX_LIST_CNT - 1)) { 1210 ld->sis_rx_list[i].sis_nextdesc = &ld->sis_rx_list[0]; 1211 next += 1212 offsetof(struct sis_list_data, sis_rx_list[0]); 1213 } else { 1214 ld->sis_rx_list[i].sis_nextdesc = &ld->sis_rx_list[i+1]; 1215 next += 1216 offsetof(struct sis_list_data, sis_rx_list[i+1]); 1217 } 1218 ld->sis_rx_list[i].sis_next = next; 1219 } 1220 1221 cd->sis_rx_prod = 0; 1222 1223 return(0); 1224 } 1225 1226 /* 1227 * Initialize an RX descriptor and attach an MBUF cluster. 1228 */ 1229 int sis_newbuf(sc, c, m) 1230 struct sis_softc *sc; 1231 struct sis_desc *c; 1232 struct mbuf *m; 1233 { 1234 struct mbuf *m_new = NULL; 1235 bus_dmamap_t map; 1236 1237 if (m == NULL) { 1238 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1239 if (m_new == NULL) { 1240 printf("%s: no memory for rx list -- packet dropped!\n", 1241 sc->sc_dev.dv_xname); 1242 return(ENOBUFS); 1243 } 1244 1245 MCLGET(m_new, M_DONTWAIT); 1246 if (!(m_new->m_flags & M_EXT)) { 1247 printf("%s: no memory for rx list -- packet dropped!\n", 1248 sc->sc_dev.dv_xname); 1249 m_freem(m_new); 1250 return(ENOBUFS); 1251 } 1252 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1253 } else { 1254 m_new = m; 1255 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1256 m_new->m_data = m_new->m_ext.ext_buf; 1257 } 1258 1259 if (bus_dmamap_load(sc->sc_dmat, sc->sc_rx_sparemap, 1260 mtod(m_new, caddr_t), MCLBYTES, NULL, BUS_DMA_NOWAIT) != 0) { 1261 printf("%s: rx load failed\n", sc->sc_dev.dv_xname); 1262 m_freem(m_new); 1263 return (ENOBUFS); 1264 } 1265 map = c->map; 1266 c->map = sc->sc_rx_sparemap; 1267 sc->sc_rx_sparemap = map; 1268 1269 bus_dmamap_sync(sc->sc_dmat, c->map, 0, c->map->dm_mapsize, 1270 BUS_DMASYNC_PREREAD); 1271 1272 m_adj(m_new, sizeof(u_int64_t)); 1273 1274 c->sis_mbuf = m_new; 1275 c->sis_ptr = c->map->dm_segs[0].ds_addr + sizeof(u_int64_t); 1276 c->sis_ctl = SIS_RXLEN; 1277 1278 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 1279 ((caddr_t)c - sc->sc_listkva), sizeof(struct sis_desc), 1280 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1281 1282 return(0); 1283 } 1284 1285 /* 1286 * A frame has been uploaded: pass the resulting mbuf chain up to 1287 * the higher level protocols. 1288 */ 1289 void sis_rxeof(sc) 1290 struct sis_softc *sc; 1291 { 1292 struct mbuf *m; 1293 struct ifnet *ifp; 1294 struct sis_desc *cur_rx; 1295 int i, total_len = 0; 1296 u_int32_t rxstat; 1297 1298 ifp = &sc->arpcom.ac_if; 1299 i = sc->sis_cdata.sis_rx_prod; 1300 1301 while(SIS_OWNDESC(&sc->sis_ldata->sis_rx_list[i])) { 1302 1303 cur_rx = &sc->sis_ldata->sis_rx_list[i]; 1304 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 1305 ((caddr_t)cur_rx - sc->sc_listkva), 1306 sizeof(struct sis_desc), 1307 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1308 1309 rxstat = cur_rx->sis_rxstat; 1310 m = cur_rx->sis_mbuf; 1311 cur_rx->sis_mbuf = NULL; 1312 total_len = SIS_RXBYTES(cur_rx); 1313 SIS_INC(i, SIS_RX_LIST_CNT); 1314 1315 1316 /* 1317 * If an error occurs, update stats, clear the 1318 * status word and leave the mbuf cluster in place: 1319 * it should simply get re-used next time this descriptor 1320 * comes up in the ring. 1321 */ 1322 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1323 ifp->if_ierrors++; 1324 if (rxstat & SIS_RXSTAT_COLL) 1325 ifp->if_collisions++; 1326 sis_newbuf(sc, cur_rx, m); 1327 continue; 1328 } 1329 1330 /* No errors; receive the packet. */ 1331 bus_dmamap_sync(sc->sc_dmat, cur_rx->map, 0, 1332 cur_rx->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1333 #ifndef __STRICT_ALIGNMENT 1334 /* 1335 * On some architectures, we do not have alignment problems, 1336 * so try to allocate a new buffer for the receive ring, and 1337 * pass up the one where the packet is already, saving the 1338 * expensive copy done in m_devget(). 1339 * If we are on an architecture with alignment problems, or 1340 * if the allocation fails, then use m_devget and leave the 1341 * existing buffer in the receive ring. 1342 */ 1343 if (sis_newbuf(sc, cur_rx, NULL) == 0) { 1344 m->m_pkthdr.rcvif = ifp; 1345 m->m_pkthdr.len = m->m_len = total_len; 1346 } else 1347 #endif 1348 { 1349 struct mbuf *m0; 1350 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1351 total_len + ETHER_ALIGN, 0, ifp, NULL); 1352 sis_newbuf(sc, cur_rx, m); 1353 if (m0 == NULL) { 1354 ifp->if_ierrors++; 1355 continue; 1356 } 1357 m_adj(m0, ETHER_ALIGN); 1358 m = m0; 1359 } 1360 1361 ifp->if_ipackets++; 1362 1363 #if NBPFILTER > 0 1364 if (ifp->if_bpf) 1365 bpf_mtap(ifp->if_bpf, m); 1366 #endif 1367 1368 /* pass it on. */ 1369 ether_input_mbuf(ifp, m); 1370 } 1371 1372 sc->sis_cdata.sis_rx_prod = i; 1373 1374 return; 1375 } 1376 1377 void sis_rxeoc(sc) 1378 struct sis_softc *sc; 1379 { 1380 sis_rxeof(sc); 1381 sis_init(sc); 1382 return; 1383 } 1384 1385 /* 1386 * A frame was downloaded to the chip. It's safe for us to clean up 1387 * the list buffers. 1388 */ 1389 1390 void sis_txeof(sc) 1391 struct sis_softc *sc; 1392 { 1393 struct sis_desc *cur_tx = NULL; 1394 struct ifnet *ifp; 1395 u_int32_t idx; 1396 1397 ifp = &sc->arpcom.ac_if; 1398 1399 /* Clear the timeout timer. */ 1400 ifp->if_timer = 0; 1401 1402 /* 1403 * Go through our tx list and free mbufs for those 1404 * frames that have been transmitted. 1405 */ 1406 idx = sc->sis_cdata.sis_tx_cons; 1407 while (idx != sc->sis_cdata.sis_tx_prod) { 1408 cur_tx = &sc->sis_ldata->sis_tx_list[idx]; 1409 1410 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 1411 ((caddr_t)cur_tx - sc->sc_listkva), 1412 sizeof(struct sis_desc), 1413 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1414 1415 if (SIS_OWNDESC(cur_tx)) 1416 break; 1417 1418 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) { 1419 sc->sis_cdata.sis_tx_cnt--; 1420 SIS_INC(idx, SIS_TX_LIST_CNT); 1421 continue; 1422 } 1423 1424 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1425 ifp->if_oerrors++; 1426 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1427 ifp->if_collisions++; 1428 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1429 ifp->if_collisions++; 1430 } 1431 1432 ifp->if_collisions += 1433 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1434 1435 ifp->if_opackets++; 1436 if (cur_tx->map->dm_nsegs != 0) { 1437 bus_dmamap_t map = cur_tx->map; 1438 1439 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1440 BUS_DMASYNC_POSTWRITE); 1441 bus_dmamap_unload(sc->sc_dmat, map); 1442 } 1443 if (cur_tx->sis_mbuf != NULL) { 1444 m_freem(cur_tx->sis_mbuf); 1445 cur_tx->sis_mbuf = NULL; 1446 } 1447 1448 sc->sis_cdata.sis_tx_cnt--; 1449 SIS_INC(idx, SIS_TX_LIST_CNT); 1450 ifp->if_timer = 0; 1451 } 1452 1453 sc->sis_cdata.sis_tx_cons = idx; 1454 1455 if (cur_tx != NULL) 1456 ifp->if_flags &= ~IFF_OACTIVE; 1457 1458 return; 1459 } 1460 1461 void sis_tick(xsc) 1462 void *xsc; 1463 { 1464 struct sis_softc *sc = (struct sis_softc *)xsc; 1465 struct mii_data *mii; 1466 struct ifnet *ifp; 1467 int s; 1468 1469 s = splnet(); 1470 1471 ifp = &sc->arpcom.ac_if; 1472 1473 mii = &sc->sc_mii; 1474 mii_tick(mii); 1475 1476 if (!sc->sis_link) { 1477 mii_pollstat(mii); 1478 if (mii->mii_media_status & IFM_ACTIVE && 1479 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1480 sc->sis_link++; 1481 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1482 sis_start(ifp); 1483 } 1484 timeout_add(&sc->sis_timeout, hz); 1485 1486 splx(s); 1487 1488 return; 1489 } 1490 1491 int sis_intr(arg) 1492 void *arg; 1493 { 1494 struct sis_softc *sc; 1495 struct ifnet *ifp; 1496 u_int32_t status; 1497 int claimed = 0; 1498 1499 sc = arg; 1500 ifp = &sc->arpcom.ac_if; 1501 1502 /* Supress unwanted interrupts */ 1503 if (!(ifp->if_flags & IFF_UP)) { 1504 sis_stop(sc); 1505 return claimed; 1506 } 1507 1508 /* Disable interrupts. */ 1509 CSR_WRITE_4(sc, SIS_IER, 0); 1510 1511 for (;;) { 1512 /* Reading the ISR register clears all interrupts. */ 1513 status = CSR_READ_4(sc, SIS_ISR); 1514 1515 if ((status & SIS_INTRS) == 0) 1516 break; 1517 1518 claimed = 1; 1519 1520 if (status & 1521 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1522 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE)) 1523 sis_txeof(sc); 1524 1525 if (status & 1526 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | 1527 SIS_ISR_RX_IDLE)) 1528 sis_rxeof(sc); 1529 1530 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1531 sis_rxeoc(sc); 1532 1533 if (status & (SIS_ISR_RX_IDLE)) 1534 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1535 1536 if (status & SIS_ISR_SYSERR) { 1537 sis_reset(sc); 1538 sis_init(sc); 1539 } 1540 } 1541 1542 /* Re-enable interrupts. */ 1543 CSR_WRITE_4(sc, SIS_IER, 1); 1544 1545 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1546 sis_start(ifp); 1547 1548 return claimed; 1549 } 1550 1551 /* 1552 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1553 * pointers to the fragment pointers. 1554 */ 1555 int sis_encap(sc, m_head, txidx) 1556 struct sis_softc *sc; 1557 struct mbuf *m_head; 1558 u_int32_t *txidx; 1559 { 1560 struct sis_desc *f = NULL; 1561 int frag, cur, i; 1562 bus_dmamap_t map; 1563 1564 map = sc->sc_tx_sparemap; 1565 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, 1566 m_head, BUS_DMA_NOWAIT) != 0) 1567 return (ENOBUFS); 1568 1569 /* 1570 * Start packing the mbufs in this chain into 1571 * the fragment pointers. Stop when we run out 1572 * of fragments or hit the end of the mbuf chain. 1573 */ 1574 cur = frag = *txidx; 1575 1576 for (i = 0; i < map->dm_nsegs; i++) { 1577 if ((SIS_TX_LIST_CNT - (sc->sis_cdata.sis_tx_cnt + i)) < 2) 1578 return(ENOBUFS); 1579 f = &sc->sis_ldata->sis_tx_list[frag]; 1580 f->sis_ctl = SIS_CMDSTS_MORE | map->dm_segs[i].ds_len; 1581 f->sis_ptr = map->dm_segs[i].ds_addr; 1582 if (i != 0) 1583 f->sis_ctl |= SIS_CMDSTS_OWN; 1584 cur = frag; 1585 SIS_INC(frag, SIS_TX_LIST_CNT); 1586 } 1587 1588 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1589 BUS_DMASYNC_PREWRITE); 1590 1591 sc->sis_ldata->sis_tx_list[cur].sis_mbuf = m_head; 1592 sc->sis_ldata->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1593 sc->sis_ldata->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1594 sc->sis_cdata.sis_tx_cnt += i; 1595 *txidx = frag; 1596 1597 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 1598 offsetof(struct sis_list_data, sis_tx_list[0]), 1599 sizeof(struct sis_desc) * SIS_TX_LIST_CNT, 1600 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1601 1602 return(0); 1603 } 1604 1605 /* 1606 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1607 * to the mbuf data regions directly in the transmit lists. We also save a 1608 * copy of the pointers since the transmit list fragment pointers are 1609 * physical addresses. 1610 */ 1611 1612 void sis_start(ifp) 1613 struct ifnet *ifp; 1614 { 1615 struct sis_softc *sc; 1616 struct mbuf *m_head = NULL; 1617 u_int32_t idx; 1618 1619 sc = ifp->if_softc; 1620 1621 if (!sc->sis_link) 1622 return; 1623 1624 idx = sc->sis_cdata.sis_tx_prod; 1625 1626 if (ifp->if_flags & IFF_OACTIVE) 1627 return; 1628 1629 while(sc->sis_ldata->sis_tx_list[idx].sis_mbuf == NULL) { 1630 IFQ_POLL(&ifp->if_snd, m_head); 1631 if (m_head == NULL) 1632 break; 1633 1634 if (sis_encap(sc, m_head, &idx)) { 1635 ifp->if_flags |= IFF_OACTIVE; 1636 break; 1637 } 1638 1639 /* now we are committed to transmit the packet */ 1640 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1641 1642 /* 1643 * If there's a BPF listener, bounce a copy of this frame 1644 * to him. 1645 */ 1646 #if NBPFILTER > 0 1647 if (ifp->if_bpf) 1648 bpf_mtap(ifp->if_bpf, m_head); 1649 #endif 1650 } 1651 if (idx == sc->sis_cdata.sis_tx_prod) 1652 return; 1653 1654 /* Transmit */ 1655 sc->sis_cdata.sis_tx_prod = idx; 1656 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1657 1658 /* 1659 * Set a timeout in case the chip goes out to lunch. 1660 */ 1661 ifp->if_timer = 5; 1662 1663 return; 1664 } 1665 1666 void sis_init(xsc) 1667 void *xsc; 1668 { 1669 struct sis_softc *sc = (struct sis_softc *)xsc; 1670 struct ifnet *ifp = &sc->arpcom.ac_if; 1671 struct mii_data *mii; 1672 int s; 1673 int tmp; 1674 1675 s = splnet(); 1676 1677 /* 1678 * Cancel pending I/O and free all RX/TX buffers. 1679 */ 1680 sis_stop(sc); 1681 1682 mii = &sc->sc_mii; 1683 1684 /* Set MAC address */ 1685 if (sc->sis_type == SIS_TYPE_83815) { 1686 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1687 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1688 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1689 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1690 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1691 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1692 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1693 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1694 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1695 } else { 1696 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1697 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1698 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1699 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1700 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1701 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1702 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1703 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1704 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1705 } 1706 1707 /* Init circular RX list. */ 1708 if (sis_list_rx_init(sc) == ENOBUFS) { 1709 printf("%s: initialization failed: no memory for rx buffers\n", 1710 sc->sc_dev.dv_xname); 1711 sis_stop(sc); 1712 splx(s); 1713 return; 1714 } 1715 1716 /* 1717 * Init tx descriptors. 1718 */ 1719 sis_list_tx_init(sc); 1720 1721 /* 1722 * For the NatSemi chip, we have to explicitly enable the 1723 * reception of ARP frames, as well as turn on the 'perfect 1724 * match' filter where we store the station address, otherwise 1725 * we won't receive unicasts meant for this host. 1726 */ 1727 if (sc->sis_type == SIS_TYPE_83815) { 1728 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1729 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1730 } 1731 1732 /* If we want promiscuous mode, set the allframes bit. */ 1733 if (ifp->if_flags & IFF_PROMISC) { 1734 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1735 } else { 1736 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1737 } 1738 1739 /* 1740 * Set the capture broadcast bit to capture broadcast frames. 1741 */ 1742 if (ifp->if_flags & IFF_BROADCAST) { 1743 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1744 } else { 1745 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1746 } 1747 1748 /* 1749 * Load the multicast filter. 1750 */ 1751 if (sc->sis_type == SIS_TYPE_83815) 1752 sis_setmulti_ns(sc); 1753 else 1754 sis_setmulti_sis(sc); 1755 1756 /* Turn the receive filter on */ 1757 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1758 1759 /* 1760 * Load the address of the RX and TX lists. 1761 */ 1762 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sc_listmap->dm_segs[0].ds_addr + 1763 offsetof(struct sis_list_data, sis_rx_list[0])); 1764 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sc_listmap->dm_segs[0].ds_addr + 1765 offsetof(struct sis_list_data, sis_tx_list[0])); 1766 1767 /* Set RX configuration */ 1768 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG); 1769 1770 /* Accept Long Packets for VLAN support */ 1771 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1772 1773 /* Set TX configuration */ 1774 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 1775 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1776 else 1777 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1778 1779 /* Set full/half duplex mode. */ 1780 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1781 SIS_SETBIT(sc, SIS_TX_CFG, 1782 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1783 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1784 } else { 1785 SIS_CLRBIT(sc, SIS_TX_CFG, 1786 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1787 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1788 } 1789 1790 /* 1791 * Enable interrupts. 1792 */ 1793 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1794 CSR_WRITE_4(sc, SIS_IER, 1); 1795 1796 /* Enable receiver and transmitter. */ 1797 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1798 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1799 1800 #ifdef notdef 1801 mii_mediachg(mii); 1802 #endif 1803 1804 /* 1805 * Page 75 of the DP83815 manual recommends the 1806 * following register settings "for optimum 1807 * performance." Note however that at least three 1808 * of the registers are listed as "reserved" in 1809 * the register map, so who knows what they do. 1810 */ 1811 if (sc->sis_type == SIS_TYPE_83815) { 1812 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1813 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1814 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1815 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1816 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1817 1818 /* 1819 * A small number of DP83815's will have excessive receive 1820 * errors when using short cables (<30m/100feet) in 100Base-TX 1821 * mode. This patch was taken from the National Semiconductor 1822 * linux driver and (supposedly - no mention of this in any NS 1823 * docs) modifies the dsp's signal attenuation. 1824 */ 1825 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_10_T) { 1826 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1827 tmp = CSR_READ_4(sc, NS_PHY_DSPCFG); 1828 tmp &= 0xFFF; 1829 CSR_WRITE_4(sc, NS_PHY_DSPCFG, (tmp | 0x1000)); 1830 DELAY(100); 1831 tmp = CSR_READ_4(sc, NS_PHY_TDATA); 1832 tmp &= 0xFF; 1833 if (!(tmp & 0x80) || (tmp >= 0xD8)) { 1834 CSR_WRITE_4(sc, NS_PHY_TDATA, 0xE8); 1835 tmp = CSR_READ_4(sc, NS_PHY_DSPCFG); 1836 CSR_WRITE_4(sc, NS_PHY_DSPCFG, (tmp | 0x20)); 1837 } else { 1838 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 1839 } 1840 } 1841 } 1842 1843 ifp->if_flags |= IFF_RUNNING; 1844 ifp->if_flags &= ~IFF_OACTIVE; 1845 1846 splx(s); 1847 1848 timeout_set(&sc->sis_timeout, sis_tick, sc); 1849 timeout_add(&sc->sis_timeout, hz); 1850 1851 return; 1852 } 1853 1854 /* 1855 * Set media options. 1856 */ 1857 int sis_ifmedia_upd(ifp) 1858 struct ifnet *ifp; 1859 { 1860 struct sis_softc *sc; 1861 struct mii_data *mii; 1862 1863 sc = ifp->if_softc; 1864 1865 mii = &sc->sc_mii; 1866 sc->sis_link = 0; 1867 if (mii->mii_instance) { 1868 struct mii_softc *miisc; 1869 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1870 mii_phy_reset(miisc); 1871 } 1872 mii_mediachg(mii); 1873 1874 return(0); 1875 } 1876 1877 /* 1878 * Report current media status. 1879 */ 1880 void sis_ifmedia_sts(ifp, ifmr) 1881 struct ifnet *ifp; 1882 struct ifmediareq *ifmr; 1883 { 1884 struct sis_softc *sc; 1885 struct mii_data *mii; 1886 1887 sc = ifp->if_softc; 1888 1889 mii = &sc->sc_mii; 1890 mii_pollstat(mii); 1891 ifmr->ifm_active = mii->mii_media_active; 1892 ifmr->ifm_status = mii->mii_media_status; 1893 1894 return; 1895 } 1896 1897 int sis_ioctl(ifp, command, data) 1898 struct ifnet *ifp; 1899 u_long command; 1900 caddr_t data; 1901 { 1902 struct sis_softc *sc = ifp->if_softc; 1903 struct ifreq *ifr = (struct ifreq *) data; 1904 struct ifaddr *ifa = (struct ifaddr *)data; 1905 struct mii_data *mii; 1906 int s, error = 0; 1907 1908 s = splnet(); 1909 1910 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 1911 splx(s); 1912 return error; 1913 } 1914 1915 switch(command) { 1916 case SIOCSIFADDR: 1917 ifp->if_flags |= IFF_UP; 1918 switch (ifa->ifa_addr->sa_family) { 1919 case AF_INET: 1920 sis_init(sc); 1921 arp_ifinit(&sc->arpcom, ifa); 1922 break; 1923 default: 1924 sis_init(sc); 1925 break; 1926 } 1927 break; 1928 case SIOCSIFFLAGS: 1929 if (ifp->if_flags & IFF_UP) { 1930 sis_init(sc); 1931 } else { 1932 if (ifp->if_flags & IFF_RUNNING) 1933 sis_stop(sc); 1934 } 1935 error = 0; 1936 break; 1937 case SIOCADDMULTI: 1938 case SIOCDELMULTI: 1939 error = (command == SIOCADDMULTI) ? 1940 ether_addmulti(ifr, &sc->arpcom) : 1941 ether_delmulti(ifr, &sc->arpcom); 1942 1943 if (error == ENETRESET) { 1944 /* 1945 * Multicast list has changed; set the hardware 1946 * filter accordingly. 1947 */ 1948 if (sc->sis_type == SIS_TYPE_83815) 1949 sis_setmulti_ns(sc); 1950 else 1951 sis_setmulti_sis(sc); 1952 error = 0; 1953 } 1954 break; 1955 case SIOCGIFMEDIA: 1956 case SIOCSIFMEDIA: 1957 mii = &sc->sc_mii; 1958 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1959 break; 1960 default: 1961 error = EINVAL; 1962 break; 1963 } 1964 1965 splx(s); 1966 1967 return(error); 1968 } 1969 1970 void sis_watchdog(ifp) 1971 struct ifnet *ifp; 1972 { 1973 struct sis_softc *sc; 1974 int s; 1975 1976 sc = ifp->if_softc; 1977 1978 ifp->if_oerrors++; 1979 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1980 1981 s = splnet(); 1982 sis_stop(sc); 1983 sis_reset(sc); 1984 sis_init(sc); 1985 1986 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1987 sis_start(ifp); 1988 1989 splx(s); 1990 return; 1991 } 1992 1993 /* 1994 * Stop the adapter and free any mbufs allocated to the 1995 * RX and TX lists. 1996 */ 1997 void sis_stop(sc) 1998 struct sis_softc *sc; 1999 { 2000 register int i; 2001 struct ifnet *ifp; 2002 2003 ifp = &sc->arpcom.ac_if; 2004 ifp->if_timer = 0; 2005 2006 timeout_del(&sc->sis_timeout); 2007 CSR_WRITE_4(sc, SIS_IER, 0); 2008 CSR_WRITE_4(sc, SIS_IMR, 0); 2009 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2010 DELAY(1000); 2011 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2012 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2013 2014 sc->sis_link = 0; 2015 2016 /* 2017 * Free data in the RX lists. 2018 */ 2019 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2020 if (sc->sis_ldata->sis_rx_list[i].map->dm_nsegs != 0) { 2021 bus_dmamap_t map = sc->sis_ldata->sis_rx_list[i].map; 2022 2023 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2024 BUS_DMASYNC_POSTREAD); 2025 bus_dmamap_unload(sc->sc_dmat, map); 2026 } 2027 if (sc->sis_ldata->sis_rx_list[i].sis_mbuf != NULL) { 2028 m_freem(sc->sis_ldata->sis_rx_list[i].sis_mbuf); 2029 sc->sis_ldata->sis_rx_list[i].sis_mbuf = NULL; 2030 } 2031 bzero((char *)&sc->sis_ldata->sis_rx_list[i], 2032 sizeof(struct sis_desc) - sizeof(bus_dmamap_t)); 2033 } 2034 2035 /* 2036 * Free the TX list buffers. 2037 */ 2038 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2039 if (sc->sis_ldata->sis_tx_list[i].map->dm_nsegs != 0) { 2040 bus_dmamap_t map = sc->sis_ldata->sis_tx_list[i].map; 2041 2042 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2043 BUS_DMASYNC_POSTWRITE); 2044 bus_dmamap_unload(sc->sc_dmat, map); 2045 } 2046 if (sc->sis_ldata->sis_tx_list[i].sis_mbuf != NULL) { 2047 m_freem(sc->sis_ldata->sis_tx_list[i].sis_mbuf); 2048 sc->sis_ldata->sis_tx_list[i].sis_mbuf = NULL; 2049 } 2050 bzero((char *)&sc->sis_ldata->sis_tx_list[i], 2051 sizeof(struct sis_desc) - sizeof(bus_dmamap_t)); 2052 } 2053 2054 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2055 2056 return; 2057 } 2058 2059 /* 2060 * Stop all chip I/O so that the kernel's probe routines don't 2061 * get confused by errant DMAs when rebooting. 2062 */ 2063 void sis_shutdown(v) 2064 void *v; 2065 { 2066 struct sis_softc *sc = (struct sis_softc *)v; 2067 2068 sis_stop(sc); 2069 } 2070 2071 struct cfattach sis_ca = { 2072 sizeof(struct sis_softc), sis_probe, sis_attach 2073 }; 2074 2075 struct cfdriver sis_cd = { 2076 0, "sis", DV_IFNET 2077 }; 2078 2079