1 /* $OpenBSD: if_rtw_pci.c,v 1.20 2015/11/24 17:11:39 mpi Exp $ */ 2 /* $NetBSD: if_rtw_pci.c,v 1.1 2004/09/26 02:33:36 dyoung Exp $ */ 3 4 /*- 5 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center; Charles M. Hannum; and David Young. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus front-end for the Realtek RTL8180L 802.11 MAC/BBP chip. 36 * 37 * Derived from the ADMtek ADM8211 PCI bus front-end. 38 * 39 * Derived from the ``Tulip'' PCI bus front-end. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/endian.h> 52 53 #include <net/if.h> 54 #include <net/if_media.h> 55 #include <netinet/in.h> 56 #include <netinet/if_ether.h> 57 58 #include <net80211/ieee80211_radiotap.h> 59 #include <net80211/ieee80211_var.h> 60 61 #include <machine/bus.h> 62 #include <machine/intr.h> 63 64 #include <dev/ic/rtwreg.h> 65 #include <dev/ic/sa2400reg.h> 66 #include <dev/ic/rtwvar.h> 67 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcidevs.h> 71 72 int rtw_pci_enable(struct rtw_softc *); 73 void rtw_pci_disable(struct rtw_softc *); 74 int rtw_pci_detach(struct device *, int); 75 76 /* 77 * PCI configuration space registers used by the RTL8180L. 78 */ 79 #define RTW_PCI_IOBA 0x10 /* i/o mapped base */ 80 #define RTW_PCI_MMBA 0x14 /* memory mapped base */ 81 82 struct rtw_pci_softc { 83 struct rtw_softc psc_rtw; /* real RTL8180L softc */ 84 85 pci_intr_handle_t psc_ih; /* interrupt handle */ 86 void *psc_intrcookie; 87 88 pci_chipset_tag_t psc_pc; /* our PCI chipset */ 89 pcitag_t psc_pcitag; /* our PCI tag */ 90 bus_size_t psc_mapsize; 91 }; 92 93 int rtw_pci_match(struct device *, void *, void *); 94 void rtw_pci_attach(struct device *, struct device *, void *); 95 96 struct cfattach rtw_pci_ca = { 97 sizeof (struct rtw_pci_softc), rtw_pci_match, rtw_pci_attach, 98 rtw_pci_detach, rtw_activate 99 }; 100 101 const struct pci_matchid rtw_pci_products[] = { 102 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8180 }, 103 #ifdef RTW_DEBUG 104 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8185 }, 105 { PCI_VENDOR_BELKIN2, PCI_PRODUCT_BELKIN2_F5D7010 }, 106 #endif 107 { PCI_VENDOR_BELKIN2, PCI_PRODUCT_BELKIN2_F5D6001 }, 108 { PCI_VENDOR_BELKIN2, PCI_PRODUCT_BELKIN2_F5D6020V3 }, 109 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DWL610 }, 110 }; 111 112 int 113 rtw_pci_match(struct device *parent, void *match, void *aux) 114 { 115 return (pci_matchbyid((struct pci_attach_args *)aux, rtw_pci_products, 116 nitems(rtw_pci_products))); 117 } 118 119 int 120 rtw_pci_enable(struct rtw_softc *sc) 121 { 122 struct rtw_pci_softc *psc = (void *)sc; 123 124 /* Establish the interrupt. */ 125 psc->psc_intrcookie = pci_intr_establish(psc->psc_pc, psc->psc_ih, 126 IPL_NET, rtw_intr, sc, sc->sc_dev.dv_xname); 127 if (psc->psc_intrcookie == NULL) { 128 printf("%s: unable to establish interrupt\n", 129 sc->sc_dev.dv_xname); 130 return (1); 131 } 132 133 return (0); 134 } 135 136 void 137 rtw_pci_disable(struct rtw_softc *sc) 138 { 139 struct rtw_pci_softc *psc = (void *)sc; 140 141 /* Unhook the interrupt handler. */ 142 pci_intr_disestablish(psc->psc_pc, psc->psc_intrcookie); 143 psc->psc_intrcookie = NULL; 144 } 145 146 void 147 rtw_pci_attach(struct device *parent, struct device *self, void *aux) 148 { 149 struct rtw_pci_softc *psc = (void *) self; 150 struct rtw_softc *sc = &psc->psc_rtw; 151 struct rtw_regs *regs = &sc->sc_regs; 152 struct pci_attach_args *pa = aux; 153 pci_chipset_tag_t pc = pa->pa_pc; 154 const char *intrstr = NULL; 155 bus_space_tag_t iot, memt; 156 bus_space_handle_t ioh, memh; 157 bus_size_t iosize, memsize; 158 int ioh_valid, memh_valid; 159 160 psc->psc_pc = pa->pa_pc; 161 psc->psc_pcitag = pa->pa_tag; 162 163 /* 164 * No power management hooks. 165 * XXX Maybe we should add some! 166 */ 167 sc->sc_flags |= RTW_F_ENABLED; 168 169 /* 170 * Get revision info, and set some chip-specific variables. 171 */ 172 sc->sc_rev = PCI_REVISION(pa->pa_class); 173 174 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 175 176 /* 177 * Map the device. 178 */ 179 ioh_valid = (pci_mapreg_map(pa, RTW_PCI_IOBA, 180 PCI_MAPREG_TYPE_IO, 0, 181 &iot, &ioh, NULL, &iosize, 0) == 0); 182 memh_valid = (pci_mapreg_map(pa, RTW_PCI_MMBA, 183 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 184 &memt, &memh, NULL, &memsize, 0) == 0); 185 186 if (memh_valid) { 187 regs->r_bt = memt; 188 regs->r_bh = memh; 189 psc->psc_mapsize = memsize; 190 } else if (ioh_valid) { 191 regs->r_bt = iot; 192 regs->r_bh = ioh; 193 psc->psc_mapsize = iosize; 194 } else { 195 printf(": unable to map device registers\n"); 196 return; 197 } 198 199 sc->sc_dmat = pa->pa_dmat; 200 201 /* 202 * Map and establish our interrupt. 203 */ 204 if (pci_intr_map(pa, &psc->psc_ih)) { 205 printf(": unable to map interrupt\n"); 206 return; 207 } 208 intrstr = pci_intr_string(pc, psc->psc_ih); 209 psc->psc_intrcookie = pci_intr_establish(pc, psc->psc_ih, IPL_NET, 210 rtw_intr, sc, sc->sc_dev.dv_xname); 211 if (psc->psc_intrcookie == NULL) { 212 printf(": unable to establish interrupt"); 213 if (intrstr != NULL) 214 printf(" at %s", intrstr); 215 printf("\n"); 216 return; 217 } 218 219 printf(": %s\n", intrstr); 220 221 sc->sc_enable = rtw_pci_enable; 222 sc->sc_disable = rtw_pci_disable; 223 224 /* 225 * Finish off the attach. 226 */ 227 rtw_attach(sc); 228 } 229 230 int 231 rtw_pci_detach(struct device *self, int flags) 232 { 233 struct rtw_pci_softc *psc = (void *)self; 234 struct rtw_softc *sc = &psc->psc_rtw; 235 struct rtw_regs *regs = &sc->sc_regs; 236 int rv; 237 238 rv = rtw_detach(sc); 239 if (rv) 240 return (rv); 241 if (psc->psc_intrcookie != NULL) 242 pci_intr_disestablish(psc->psc_pc, psc->psc_intrcookie); 243 bus_space_unmap(regs->r_bt, regs->r_bh, psc->psc_mapsize); 244 245 return (0); 246 } 247