1 /* $OpenBSD: if_pcn.c,v 1.29 2013/12/07 20:12:15 brad Exp $ */ 2 /* $NetBSD: if_pcn.c,v 1.26 2005/05/07 09:15:44 is Exp $ */ 3 4 /* 5 * Copyright (c) 2001 Wasabi Systems, Inc. 6 * All rights reserved. 7 * 8 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed for the NetBSD Project by 21 * Wasabi Systems, Inc. 22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the AMD PCnet-PCI series of Ethernet 41 * chips: 42 * 43 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 44 * Local Bus 45 * 46 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 47 * for PCI Local Bus 48 * 49 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 50 * Ethernet Controller for PCI Local Bus 51 * 52 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 53 * with OnNow Support 54 * 55 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 56 * Ethernet Controller with Integrated PHY 57 * 58 * This also supports the virtual PCnet-PCI Ethernet interface found 59 * in VMware. 60 * 61 * TODO: 62 * 63 * * Split this into bus-specific and bus-independent portions. 64 * The core could also be used for the ILACC (Am79900) 32-bit 65 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 66 */ 67 68 #include "bpfilter.h" 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/timeout.h> 73 #include <sys/mbuf.h> 74 #include <sys/malloc.h> 75 #include <sys/kernel.h> 76 #include <sys/socket.h> 77 #include <sys/ioctl.h> 78 #include <sys/errno.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 82 #include <net/if.h> 83 #include <net/if_dl.h> 84 85 #ifdef INET 86 #include <netinet/in.h> 87 #include <netinet/in_systm.h> 88 #include <netinet/ip.h> 89 #include <netinet/if_ether.h> 90 #endif 91 92 #include <net/if_media.h> 93 94 #if NBPFILTER > 0 95 #include <net/bpf.h> 96 #endif 97 98 #include <machine/bus.h> 99 #include <machine/intr.h> 100 #include <machine/endian.h> 101 102 #include <dev/mii/mii.h> 103 #include <dev/mii/miivar.h> 104 105 #include <dev/ic/am79900reg.h> 106 #include <dev/ic/lancereg.h> 107 108 #include <dev/pci/pcireg.h> 109 #include <dev/pci/pcivar.h> 110 #include <dev/pci/pcidevs.h> 111 112 /* 113 * Register definitions for the AMD PCnet-PCI series of Ethernet 114 * chips. 115 * 116 * These are only the registers that we access directly from PCI 117 * space. Everything else (accessed via the RAP + RDP/BDP) is 118 * defined in <dev/ic/lancereg.h>. 119 */ 120 121 /* 122 * PCI configuration space. 123 */ 124 125 #define PCN_PCI_CBIO (PCI_MAPREG_START + 0x00) 126 #define PCN_PCI_CBMEM (PCI_MAPREG_START + 0x04) 127 128 /* 129 * I/O map in Word I/O mode. 130 */ 131 132 #define PCN16_APROM 0x00 133 #define PCN16_RDP 0x10 134 #define PCN16_RAP 0x12 135 #define PCN16_RESET 0x14 136 #define PCN16_BDP 0x16 137 138 /* 139 * I/O map in DWord I/O mode. 140 */ 141 142 #define PCN32_APROM 0x00 143 #define PCN32_RDP 0x10 144 #define PCN32_RAP 0x14 145 #define PCN32_RESET 0x18 146 #define PCN32_BDP 0x1c 147 148 /* 149 * Transmit descriptor list size. This is arbitrary, but allocate 150 * enough descriptors for 128 pending transmissions, and 4 segments 151 * per packet. This MUST work out to a power of 2. 152 * 153 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 154 * 155 * So we play a little trick here. We give each packet up to 16 156 * DMA segments, but only allocate the max of 512 descriptors. The 157 * transmit logic can deal with this, we just are hoping to sneak by. 158 */ 159 #define PCN_NTXSEGS 16 160 161 #define PCN_TXQUEUELEN 128 162 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 163 #define PCN_NTXDESC 512 164 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 165 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 166 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 167 168 /* Tx interrupt every N + 1 packets. */ 169 #define PCN_TXINTR_MASK 7 170 171 /* 172 * Receive descriptor list size. We have one Rx buffer per incoming 173 * packet, so this logic is a little simpler. 174 */ 175 #define PCN_NRXDESC 128 176 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 177 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 178 179 /* 180 * Control structures are DMA'd to the PCnet chip. We allocate them in 181 * a single clump that maps to a single DMA segment to make several things 182 * easier. 183 */ 184 struct pcn_control_data { 185 /* The transmit descriptors. */ 186 struct letmd pcd_txdescs[PCN_NTXDESC]; 187 188 /* The receive descriptors. */ 189 struct lermd pcd_rxdescs[PCN_NRXDESC]; 190 191 /* The init block. */ 192 struct leinit pcd_initblock; 193 }; 194 195 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 196 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 197 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 198 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 199 200 /* 201 * Software state for transmit jobs. 202 */ 203 struct pcn_txsoft { 204 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 205 bus_dmamap_t txs_dmamap; /* our DMA map */ 206 int txs_firstdesc; /* first descriptor in packet */ 207 int txs_lastdesc; /* last descriptor in packet */ 208 }; 209 210 /* 211 * Software state for receive jobs. 212 */ 213 struct pcn_rxsoft { 214 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 215 bus_dmamap_t rxs_dmamap; /* our DMA map */ 216 }; 217 218 /* 219 * Description of Rx FIFO watermarks for various revisions. 220 */ 221 static const char * const pcn_79c970_rcvfw[] = { 222 "16 bytes", 223 "64 bytes", 224 "128 bytes", 225 NULL, 226 }; 227 228 static const char * const pcn_79c971_rcvfw[] = { 229 "16 bytes", 230 "64 bytes", 231 "112 bytes", 232 NULL, 233 }; 234 235 /* 236 * Description of Tx start points for various revisions. 237 */ 238 static const char * const pcn_79c970_xmtsp[] = { 239 "8 bytes", 240 "64 bytes", 241 "128 bytes", 242 "248 bytes", 243 }; 244 245 static const char * const pcn_79c971_xmtsp[] = { 246 "20 bytes", 247 "64 bytes", 248 "128 bytes", 249 "248 bytes", 250 }; 251 252 static const char * const pcn_79c971_xmtsp_sram[] = { 253 "44 bytes", 254 "64 bytes", 255 "128 bytes", 256 "store-and-forward", 257 }; 258 259 /* 260 * Description of Tx FIFO watermarks for various revisions. 261 */ 262 static const char * const pcn_79c970_xmtfw[] = { 263 "16 bytes", 264 "64 bytes", 265 "128 bytes", 266 NULL, 267 }; 268 269 static const char * const pcn_79c971_xmtfw[] = { 270 "16 bytes", 271 "64 bytes", 272 "108 bytes", 273 NULL, 274 }; 275 276 /* 277 * Software state per device. 278 */ 279 struct pcn_softc { 280 struct device sc_dev; /* generic device information */ 281 bus_space_tag_t sc_st; /* bus space tag */ 282 bus_space_handle_t sc_sh; /* bus space handle */ 283 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 284 struct arpcom sc_arpcom; /* Ethernet common data */ 285 286 /* Points to our media routines, etc. */ 287 const struct pcn_variant *sc_variant; 288 289 void *sc_ih; /* interrupt cookie */ 290 291 struct mii_data sc_mii; /* MII/media information */ 292 293 struct timeout sc_tick_timeout; /* tick timeout */ 294 295 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 296 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 297 298 /* Software state for transmit and receive descriptors. */ 299 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 300 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 301 302 /* Control data structures */ 303 struct pcn_control_data *sc_control_data; 304 #define sc_txdescs sc_control_data->pcd_txdescs 305 #define sc_rxdescs sc_control_data->pcd_rxdescs 306 #define sc_initblock sc_control_data->pcd_initblock 307 308 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 309 int sc_rcvfw; 310 311 const char * const *sc_xmtsp_desc; /* Tx start point info */ 312 int sc_xmtsp; 313 314 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 315 int sc_xmtfw; 316 317 int sc_flags; /* misc. flags; see below */ 318 int sc_swstyle; /* the software style in use */ 319 320 int sc_txfree; /* number of free Tx descriptors */ 321 int sc_txnext; /* next ready Tx descriptor */ 322 323 int sc_txsfree; /* number of free Tx jobs */ 324 int sc_txsnext; /* next free Tx job */ 325 int sc_txsdirty; /* dirty Tx jobs */ 326 327 int sc_rxptr; /* next ready Rx descriptor/job */ 328 329 uint32_t sc_csr5; /* prototype CSR5 register */ 330 uint32_t sc_mode; /* prototype MODE register */ 331 }; 332 333 /* sc_flags */ 334 #define PCN_F_HAS_MII 0x0001 /* has MII */ 335 336 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 337 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 338 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 339 340 #define PCN_CDTXSYNC(sc, x, n, ops) \ 341 do { \ 342 int __x, __n; \ 343 \ 344 __x = (x); \ 345 __n = (n); \ 346 \ 347 /* If it will wrap around, sync to the end of the ring. */ \ 348 if ((__x + __n) > PCN_NTXDESC) { \ 349 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 350 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 351 (PCN_NTXDESC - __x), (ops)); \ 352 __n -= (PCN_NTXDESC - __x); \ 353 __x = 0; \ 354 } \ 355 \ 356 /* Now sync whatever is left. */ \ 357 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 358 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 359 } while (/*CONSTCOND*/0) 360 361 #define PCN_CDRXSYNC(sc, x, ops) \ 362 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 363 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 364 365 #define PCN_CDINITSYNC(sc, ops) \ 366 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 367 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 368 369 #define PCN_INIT_RXDESC(sc, x) \ 370 do { \ 371 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 372 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 373 struct mbuf *__m = __rxs->rxs_mbuf; \ 374 \ 375 /* \ 376 * Note: We scoot the packet forward 2 bytes in the buffer \ 377 * so that the payload after the Ethernet header is aligned \ 378 * to a 4-byte boundary. \ 379 */ \ 380 __m->m_data = __m->m_ext.ext_buf + 2; \ 381 \ 382 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 383 __rmd->rmd2 = \ 384 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 385 __rmd->rmd0 = 0; \ 386 } else { \ 387 __rmd->rmd2 = 0; \ 388 __rmd->rmd0 = \ 389 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 390 } \ 391 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 392 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 393 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 394 } while(/*CONSTCOND*/0) 395 396 void pcn_start(struct ifnet *); 397 void pcn_watchdog(struct ifnet *); 398 int pcn_ioctl(struct ifnet *, u_long, caddr_t); 399 int pcn_init(struct ifnet *); 400 void pcn_stop(struct ifnet *, int); 401 402 void pcn_reset(struct pcn_softc *); 403 void pcn_rxdrain(struct pcn_softc *); 404 int pcn_add_rxbuf(struct pcn_softc *, int); 405 void pcn_tick(void *); 406 407 void pcn_spnd(struct pcn_softc *); 408 409 void pcn_set_filter(struct pcn_softc *); 410 411 int pcn_intr(void *); 412 void pcn_txintr(struct pcn_softc *); 413 int pcn_rxintr(struct pcn_softc *); 414 415 int pcn_mii_readreg(struct device *, int, int); 416 void pcn_mii_writereg(struct device *, int, int, int); 417 void pcn_mii_statchg(struct device *); 418 419 void pcn_79c970_mediainit(struct pcn_softc *); 420 int pcn_79c970_mediachange(struct ifnet *); 421 void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 422 423 void pcn_79c971_mediainit(struct pcn_softc *); 424 int pcn_79c971_mediachange(struct ifnet *); 425 void pcn_79c971_mediastatus(struct ifnet *, struct ifmediareq *); 426 427 /* 428 * Description of a PCnet-PCI variant. Used to select media access 429 * method, mostly, and to print a nice description of the chip. 430 */ 431 static const struct pcn_variant { 432 const char *pcv_desc; 433 void (*pcv_mediainit)(struct pcn_softc *); 434 uint16_t pcv_chipid; 435 } pcn_variants[] = { 436 { "Am79c970", 437 pcn_79c970_mediainit, 438 PARTID_Am79c970 }, 439 440 { "Am79c970A", 441 pcn_79c970_mediainit, 442 PARTID_Am79c970A }, 443 444 { "Am79c971", 445 pcn_79c971_mediainit, 446 PARTID_Am79c971 }, 447 448 { "Am79c972", 449 pcn_79c971_mediainit, 450 PARTID_Am79c972 }, 451 452 { "Am79c973", 453 pcn_79c971_mediainit, 454 PARTID_Am79c973 }, 455 456 { "Am79c975", 457 pcn_79c971_mediainit, 458 PARTID_Am79c975 }, 459 460 { "Am79c976", 461 pcn_79c971_mediainit, 462 PARTID_Am79c976 }, 463 464 { "Am79c978", 465 pcn_79c971_mediainit, 466 PARTID_Am79c978 }, 467 468 { "Unknown", 469 pcn_79c971_mediainit, 470 0 }, 471 }; 472 473 int pcn_copy_small = 0; 474 475 int pcn_match(struct device *, void *, void *); 476 void pcn_attach(struct device *, struct device *, void *); 477 478 struct cfattach pcn_ca = { 479 sizeof(struct pcn_softc), pcn_match, pcn_attach, 480 }; 481 482 const struct pci_matchid pcn_devices[] = { 483 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCNET_PCI }, 484 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCHOME_PCI } 485 }; 486 487 struct cfdriver pcn_cd = { 488 NULL, "pcn", DV_IFNET 489 }; 490 491 /* 492 * Routines to read and write the PCnet-PCI CSR/BCR space. 493 */ 494 495 static __inline uint32_t 496 pcn_csr_read(struct pcn_softc *sc, int reg) 497 { 498 499 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 500 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 501 } 502 503 static __inline void 504 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 505 { 506 507 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 508 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 509 } 510 511 static __inline uint32_t 512 pcn_bcr_read(struct pcn_softc *sc, int reg) 513 { 514 515 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 516 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 517 } 518 519 static __inline void 520 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 521 { 522 523 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 524 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 525 } 526 527 static const struct pcn_variant * 528 pcn_lookup_variant(uint16_t chipid) 529 { 530 const struct pcn_variant *pcv; 531 532 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 533 if (chipid == pcv->pcv_chipid) 534 return (pcv); 535 } 536 537 /* 538 * This covers unknown chips, which we simply treat like 539 * a generic PCnet-FAST. 540 */ 541 return (pcv); 542 } 543 544 int 545 pcn_match(struct device *parent, void *match, void *aux) 546 { 547 struct pci_attach_args *pa = aux; 548 549 /* 550 * IBM makes a PCI variant of this card which shows up as a 551 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 552 * this card is truly a pcn card, so we have a special case match for 553 * it. 554 */ 555 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 556 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 557 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 558 return(1); 559 560 return (pci_matchbyid((struct pci_attach_args *)aux, pcn_devices, 561 nitems(pcn_devices))); 562 } 563 564 void 565 pcn_attach(struct device *parent, struct device *self, void *aux) 566 { 567 struct pcn_softc *sc = (struct pcn_softc *) self; 568 struct pci_attach_args *pa = aux; 569 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 570 pci_chipset_tag_t pc = pa->pa_pc; 571 pci_intr_handle_t ih; 572 const char *intrstr = NULL; 573 bus_space_tag_t iot, memt; 574 bus_space_handle_t ioh, memh; 575 bus_dma_segment_t seg; 576 int ioh_valid, memh_valid; 577 int i, rseg, error; 578 uint32_t chipid, reg; 579 uint8_t enaddr[ETHER_ADDR_LEN]; 580 581 timeout_set(&sc->sc_tick_timeout, pcn_tick, sc); 582 583 /* 584 * Map the device. 585 */ 586 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 587 &iot, &ioh, NULL, NULL, 0) == 0); 588 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 589 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 590 &memt, &memh, NULL, NULL, 0) == 0); 591 592 if (memh_valid) { 593 sc->sc_st = memt; 594 sc->sc_sh = memh; 595 } else if (ioh_valid) { 596 sc->sc_st = iot; 597 sc->sc_sh = ioh; 598 } else { 599 printf(": unable to map device registers\n"); 600 return; 601 } 602 603 sc->sc_dmat = pa->pa_dmat; 604 605 /* Get it out of power save mode, if needed. */ 606 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 607 608 /* 609 * Reset the chip to a known state. This also puts the 610 * chip into 32-bit mode. 611 */ 612 pcn_reset(sc); 613 614 #if !defined(PCN_NO_PROM) 615 616 /* 617 * Read the Ethernet address from the EEPROM. 618 */ 619 for (i = 0; i < ETHER_ADDR_LEN; i++) 620 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 621 PCN32_APROM + i); 622 #else 623 /* 624 * The PROM is not used; instead we assume that the MAC address 625 * has been programmed into the device's physical address 626 * registers by the boot firmware 627 */ 628 629 for (i=0; i < 3; i++) { 630 uint32_t val; 631 val = pcn_csr_read(sc, LE_CSR12 + i); 632 enaddr[2*i] = val & 0x0ff; 633 enaddr[2*i+1] = (val >> 8) & 0x0ff; 634 } 635 #endif 636 637 /* 638 * Now that the device is mapped, attempt to figure out what 639 * kind of chip we have. Note that IDL has all 32 bits of 640 * the chip ID when we're in 32-bit mode. 641 */ 642 chipid = pcn_csr_read(sc, LE_CSR88); 643 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 644 645 /* 646 * Map and establish our interrupt. 647 */ 648 if (pci_intr_map(pa, &ih)) { 649 printf(": unable to map interrupt\n"); 650 return; 651 } 652 intrstr = pci_intr_string(pc, ih); 653 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc, 654 self->dv_xname); 655 if (sc->sc_ih == NULL) { 656 printf(": unable to establish interrupt"); 657 if (intrstr != NULL) 658 printf(" at %s", intrstr); 659 printf("\n"); 660 return; 661 } 662 663 /* 664 * Allocate the control data structures, and create and load the 665 * DMA map for it. 666 */ 667 if ((error = bus_dmamem_alloc(sc->sc_dmat, 668 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 669 0)) != 0) { 670 printf(": unable to allocate control data, error = %d\n", 671 error); 672 return; 673 } 674 675 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 676 sizeof(struct pcn_control_data), (caddr_t *)&sc->sc_control_data, 677 BUS_DMA_COHERENT)) != 0) { 678 printf(": unable to map control data, error = %d\n", 679 error); 680 goto fail_1; 681 } 682 683 if ((error = bus_dmamap_create(sc->sc_dmat, 684 sizeof(struct pcn_control_data), 1, 685 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 686 printf(": unable to create control data DMA map, " 687 "error = %d\n", error); 688 goto fail_2; 689 } 690 691 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 692 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 693 0)) != 0) { 694 printf(": unable to load control data DMA map, error = %d\n", 695 error); 696 goto fail_3; 697 } 698 699 /* Create the transmit buffer DMA maps. */ 700 for (i = 0; i < PCN_TXQUEUELEN; i++) { 701 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 702 PCN_NTXSEGS, MCLBYTES, 0, 0, 703 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 704 printf(": unable to create tx DMA map %d, " 705 "error = %d\n", i, error); 706 goto fail_4; 707 } 708 } 709 710 /* Create the receive buffer DMA maps. */ 711 for (i = 0; i < PCN_NRXDESC; i++) { 712 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 713 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 714 printf(": unable to create rx DMA map %d, " 715 "error = %d\n", i, error); 716 goto fail_5; 717 } 718 sc->sc_rxsoft[i].rxs_mbuf = NULL; 719 } 720 721 printf(", %s, rev %d: %s, address %s\n", sc->sc_variant->pcv_desc, 722 CHIPID_VER(chipid), intrstr, ether_sprintf(enaddr)); 723 724 /* Initialize our media structures. */ 725 (*sc->sc_variant->pcv_mediainit)(sc); 726 727 /* 728 * Initialize FIFO watermark info. 729 */ 730 switch (sc->sc_variant->pcv_chipid) { 731 case PARTID_Am79c970: 732 case PARTID_Am79c970A: 733 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 734 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 735 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 736 break; 737 738 default: 739 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 740 /* 741 * Read BCR25 to determine how much SRAM is 742 * on the board. If > 0, then we the chip 743 * uses different Start Point thresholds. 744 * 745 * Note BCR25 and BCR26 are loaded from the 746 * EEPROM on RST, and unaffected by S_RESET, 747 * so we don't really have to worry about 748 * them except for this. 749 */ 750 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 751 if (reg != 0) 752 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 753 else 754 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 755 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 756 break; 757 } 758 759 /* 760 * Set up defaults -- see the tables above for what these 761 * values mean. 762 * 763 * XXX How should we tune RCVFW and XMTFW? 764 */ 765 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 766 sc->sc_xmtsp = 1; 767 sc->sc_xmtfw = 0; 768 769 ifp = &sc->sc_arpcom.ac_if; 770 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 771 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 772 ifp->if_softc = sc; 773 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 774 ifp->if_ioctl = pcn_ioctl; 775 ifp->if_start = pcn_start; 776 ifp->if_watchdog = pcn_watchdog; 777 IFQ_SET_MAXLEN(&ifp->if_snd, PCN_NTXDESC -1); 778 IFQ_SET_READY(&ifp->if_snd); 779 780 /* Attach the interface. */ 781 if_attach(ifp); 782 ether_ifattach(ifp); 783 return; 784 785 /* 786 * Free any resources we've allocated during the failed attach 787 * attempt. Do this in reverse order and fall through. 788 */ 789 fail_5: 790 for (i = 0; i < PCN_NRXDESC; i++) { 791 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 792 bus_dmamap_destroy(sc->sc_dmat, 793 sc->sc_rxsoft[i].rxs_dmamap); 794 } 795 fail_4: 796 for (i = 0; i < PCN_TXQUEUELEN; i++) { 797 if (sc->sc_txsoft[i].txs_dmamap != NULL) 798 bus_dmamap_destroy(sc->sc_dmat, 799 sc->sc_txsoft[i].txs_dmamap); 800 } 801 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 802 fail_3: 803 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 804 fail_2: 805 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 806 sizeof(struct pcn_control_data)); 807 fail_1: 808 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 809 } 810 811 /* 812 * pcn_start: [ifnet interface function] 813 * 814 * Start packet transmission on the interface. 815 */ 816 void 817 pcn_start(struct ifnet *ifp) 818 { 819 struct pcn_softc *sc = ifp->if_softc; 820 struct mbuf *m0, *m; 821 struct pcn_txsoft *txs; 822 bus_dmamap_t dmamap; 823 int error, nexttx, lasttx = -1, ofree, seg; 824 825 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 826 return; 827 828 /* 829 * Remember the previous number of free descriptors and 830 * the first descriptor we'll use. 831 */ 832 ofree = sc->sc_txfree; 833 834 /* 835 * Loop through the send queue, setting up transmit descriptors 836 * until we drain the queue, or use up all available transmit 837 * descriptors. 838 */ 839 for (;;) { 840 /* Grab a packet off the queue. */ 841 IFQ_POLL(&ifp->if_snd, m0); 842 if (m0 == NULL) 843 break; 844 m = NULL; 845 846 /* Get a work queue entry. */ 847 if (sc->sc_txsfree == 0) 848 break; 849 850 txs = &sc->sc_txsoft[sc->sc_txsnext]; 851 dmamap = txs->txs_dmamap; 852 853 /* 854 * Load the DMA map. If this fails, the packet either 855 * didn't fit in the alloted number of segments, or we 856 * were short on resources. In this case, we'll copy 857 * and try again. 858 */ 859 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 860 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 861 MGETHDR(m, M_DONTWAIT, MT_DATA); 862 if (m == NULL) 863 break; 864 if (m0->m_pkthdr.len > MHLEN) { 865 MCLGET(m, M_DONTWAIT); 866 if ((m->m_flags & M_EXT) == 0) { 867 m_freem(m); 868 break; 869 } 870 } 871 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 872 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 873 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 874 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 875 if (error) 876 break; 877 } 878 879 /* 880 * Ensure we have enough descriptors free to describe 881 * the packet. Note, we always reserve one descriptor 882 * at the end of the ring as a termination point, to 883 * prevent wrap-around. 884 */ 885 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 886 /* 887 * Not enough free descriptors to transmit this 888 * packet. We haven't committed anything yet, 889 * so just unload the DMA map, put the packet 890 * back on the queue, and punt. Notify the upper 891 * layer that there are not more slots left. 892 * 893 * XXX We could allocate an mbuf and copy, but 894 * XXX is it worth it? 895 */ 896 ifp->if_flags |= IFF_OACTIVE; 897 bus_dmamap_unload(sc->sc_dmat, dmamap); 898 if (m != NULL) 899 m_freem(m); 900 break; 901 } 902 903 IFQ_DEQUEUE(&ifp->if_snd, m0); 904 if (m != NULL) { 905 m_freem(m0); 906 m0 = m; 907 } 908 909 /* 910 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 911 */ 912 913 /* Sync the DMA map. */ 914 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 915 BUS_DMASYNC_PREWRITE); 916 917 /* 918 * Initialize the transmit descriptors. 919 */ 920 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 921 for (nexttx = sc->sc_txnext, seg = 0; 922 seg < dmamap->dm_nsegs; 923 seg++, nexttx = PCN_NEXTTX(nexttx)) { 924 /* 925 * If this is the first descriptor we're 926 * enqueueing, don't set the OWN bit just 927 * yet. That could cause a race condition. 928 * We'll do it below. 929 */ 930 sc->sc_txdescs[nexttx].tmd0 = 0; 931 sc->sc_txdescs[nexttx].tmd2 = 932 htole32(dmamap->dm_segs[seg].ds_addr); 933 sc->sc_txdescs[nexttx].tmd1 = 934 htole32(LE_T1_ONES | 935 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 936 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 937 LE_T1_BCNT_MASK)); 938 lasttx = nexttx; 939 } 940 } else { 941 for (nexttx = sc->sc_txnext, seg = 0; 942 seg < dmamap->dm_nsegs; 943 seg++, nexttx = PCN_NEXTTX(nexttx)) { 944 /* 945 * If this is the first descriptor we're 946 * enqueueing, don't set the OWN bit just 947 * yet. That could cause a race condition. 948 * We'll do it below. 949 */ 950 sc->sc_txdescs[nexttx].tmd0 = 951 htole32(dmamap->dm_segs[seg].ds_addr); 952 sc->sc_txdescs[nexttx].tmd2 = 0; 953 sc->sc_txdescs[nexttx].tmd1 = 954 htole32(LE_T1_ONES | 955 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 956 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 957 LE_T1_BCNT_MASK)); 958 lasttx = nexttx; 959 } 960 } 961 962 KASSERT(lasttx != -1); 963 /* Interrupt on the packet, if appropriate. */ 964 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 965 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 966 967 /* Set `start of packet' and `end of packet' appropriately. */ 968 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 969 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 970 htole32(LE_T1_OWN|LE_T1_STP); 971 972 /* Sync the descriptors we're using. */ 973 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 974 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 975 976 /* Kick the transmitter. */ 977 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 978 979 /* 980 * Store a pointer to the packet so we can free it later, 981 * and remember what txdirty will be once the packet is 982 * done. 983 */ 984 txs->txs_mbuf = m0; 985 txs->txs_firstdesc = sc->sc_txnext; 986 txs->txs_lastdesc = lasttx; 987 988 /* Advance the tx pointer. */ 989 sc->sc_txfree -= dmamap->dm_nsegs; 990 sc->sc_txnext = nexttx; 991 992 sc->sc_txsfree--; 993 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 994 995 #if NBPFILTER > 0 996 /* Pass the packet to any BPF listeners. */ 997 if (ifp->if_bpf) 998 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 999 #endif /* NBPFILTER > 0 */ 1000 } 1001 1002 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1003 /* No more slots left; notify upper layer. */ 1004 ifp->if_flags |= IFF_OACTIVE; 1005 } 1006 1007 if (sc->sc_txfree != ofree) { 1008 /* Set a watchdog timer in case the chip flakes out. */ 1009 ifp->if_timer = 5; 1010 } 1011 } 1012 1013 /* 1014 * pcn_watchdog: [ifnet interface function] 1015 * 1016 * Watchdog timer handler. 1017 */ 1018 void 1019 pcn_watchdog(struct ifnet *ifp) 1020 { 1021 struct pcn_softc *sc = ifp->if_softc; 1022 1023 /* 1024 * Since we're not interrupting every packet, sweep 1025 * up before we report an error. 1026 */ 1027 pcn_txintr(sc); 1028 1029 if (sc->sc_txfree != PCN_NTXDESC) { 1030 printf("%s: device timeout (txfree %d txsfree %d)\n", 1031 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree); 1032 ifp->if_oerrors++; 1033 1034 /* Reset the interface. */ 1035 (void) pcn_init(ifp); 1036 } 1037 1038 /* Try to get more packets going. */ 1039 pcn_start(ifp); 1040 } 1041 1042 /* 1043 * pcn_ioctl: [ifnet interface function] 1044 * 1045 * Handle control requests from the operator. 1046 */ 1047 int 1048 pcn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1049 { 1050 struct pcn_softc *sc = ifp->if_softc; 1051 struct ifaddr *ifa = (struct ifaddr *) data; 1052 struct ifreq *ifr = (struct ifreq *) data; 1053 int s, error = 0; 1054 1055 s = splnet(); 1056 1057 switch (cmd) { 1058 case SIOCSIFADDR: 1059 ifp->if_flags |= IFF_UP; 1060 if (!(ifp->if_flags & IFF_RUNNING)) 1061 pcn_init(ifp); 1062 #ifdef INET 1063 if (ifa->ifa_addr->sa_family == AF_INET) 1064 arp_ifinit(&sc->sc_arpcom, ifa); 1065 #endif 1066 break; 1067 1068 case SIOCSIFFLAGS: 1069 if (ifp->if_flags & IFF_UP) { 1070 if (ifp->if_flags & IFF_RUNNING) 1071 error = ENETRESET; 1072 else 1073 pcn_init(ifp); 1074 } else { 1075 if (ifp->if_flags & IFF_RUNNING) 1076 pcn_stop(ifp, 1); 1077 } 1078 break; 1079 1080 case SIOCSIFMEDIA: 1081 case SIOCGIFMEDIA: 1082 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1083 break; 1084 1085 default: 1086 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1087 } 1088 1089 if (error == ENETRESET) { 1090 if (ifp->if_flags & IFF_RUNNING) 1091 error = pcn_init(ifp); 1092 else 1093 error = 0; 1094 } 1095 1096 /* Try to get more packets going. */ 1097 pcn_start(ifp); 1098 1099 splx(s); 1100 return (error); 1101 } 1102 1103 /* 1104 * pcn_intr: 1105 * 1106 * Interrupt service routine. 1107 */ 1108 int 1109 pcn_intr(void *arg) 1110 { 1111 struct pcn_softc *sc = arg; 1112 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1113 uint32_t csr0; 1114 int wantinit, handled = 0; 1115 1116 for (wantinit = 0; wantinit == 0;) { 1117 csr0 = pcn_csr_read(sc, LE_CSR0); 1118 if ((csr0 & LE_C0_INTR) == 0) 1119 break; 1120 1121 /* ACK the bits and re-enable interrupts. */ 1122 pcn_csr_write(sc, LE_CSR0, csr0 & 1123 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1124 LE_C0_TINT|LE_C0_IDON)); 1125 1126 handled = 1; 1127 1128 if (csr0 & LE_C0_RINT) 1129 wantinit = pcn_rxintr(sc); 1130 1131 if (csr0 & LE_C0_TINT) 1132 pcn_txintr(sc); 1133 1134 if (csr0 & LE_C0_ERR) { 1135 if (csr0 & LE_C0_BABL) 1136 ifp->if_oerrors++; 1137 if (csr0 & LE_C0_MISS) 1138 ifp->if_ierrors++; 1139 if (csr0 & LE_C0_MERR) { 1140 printf("%s: memory error\n", 1141 sc->sc_dev.dv_xname); 1142 wantinit = 1; 1143 break; 1144 } 1145 } 1146 1147 if ((csr0 & LE_C0_RXON) == 0) { 1148 printf("%s: receiver disabled\n", 1149 sc->sc_dev.dv_xname); 1150 ifp->if_ierrors++; 1151 wantinit = 1; 1152 } 1153 1154 if ((csr0 & LE_C0_TXON) == 0) { 1155 printf("%s: transmitter disabled\n", 1156 sc->sc_dev.dv_xname); 1157 ifp->if_oerrors++; 1158 wantinit = 1; 1159 } 1160 } 1161 1162 if (handled) { 1163 if (wantinit) 1164 pcn_init(ifp); 1165 1166 /* Try to get more packets going. */ 1167 pcn_start(ifp); 1168 } 1169 1170 return (handled); 1171 } 1172 1173 /* 1174 * pcn_spnd: 1175 * 1176 * Suspend the chip. 1177 */ 1178 void 1179 pcn_spnd(struct pcn_softc *sc) 1180 { 1181 int i; 1182 1183 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1184 1185 for (i = 0; i < 10000; i++) { 1186 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1187 return; 1188 delay(5); 1189 } 1190 1191 printf("%s: WARNING: chip failed to enter suspended state\n", 1192 sc->sc_dev.dv_xname); 1193 } 1194 1195 /* 1196 * pcn_txintr: 1197 * 1198 * Helper; handle transmit interrupts. 1199 */ 1200 void 1201 pcn_txintr(struct pcn_softc *sc) 1202 { 1203 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1204 struct pcn_txsoft *txs; 1205 uint32_t tmd1, tmd2, tmd; 1206 int i, j; 1207 1208 ifp->if_flags &= ~IFF_OACTIVE; 1209 1210 /* 1211 * Go through our Tx list and free mbufs for those 1212 * frames which have been transmitted. 1213 */ 1214 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1215 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1216 txs = &sc->sc_txsoft[i]; 1217 1218 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1219 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1220 1221 tmd1 = letoh32(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1222 if (tmd1 & LE_T1_OWN) 1223 break; 1224 1225 /* 1226 * Slightly annoying -- we have to loop through the 1227 * descriptors we've used looking for ERR, since it 1228 * can appear on any descriptor in the chain. 1229 */ 1230 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1231 tmd = letoh32(sc->sc_txdescs[j].tmd1); 1232 if (tmd & LE_T1_ERR) { 1233 ifp->if_oerrors++; 1234 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1235 tmd2 = letoh32(sc->sc_txdescs[j].tmd0); 1236 else 1237 tmd2 = letoh32(sc->sc_txdescs[j].tmd2); 1238 if (tmd2 & LE_T2_UFLO) { 1239 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1240 sc->sc_xmtsp++; 1241 printf("%s: transmit " 1242 "underrun; new threshold: " 1243 "%s\n", 1244 sc->sc_dev.dv_xname, 1245 sc->sc_xmtsp_desc[ 1246 sc->sc_xmtsp]); 1247 pcn_spnd(sc); 1248 pcn_csr_write(sc, LE_CSR80, 1249 LE_C80_RCVFW(sc->sc_rcvfw) | 1250 LE_C80_XMTSP(sc->sc_xmtsp) | 1251 LE_C80_XMTFW(sc->sc_xmtfw)); 1252 pcn_csr_write(sc, LE_CSR5, 1253 sc->sc_csr5); 1254 } else { 1255 printf("%s: transmit " 1256 "underrun\n", 1257 sc->sc_dev.dv_xname); 1258 } 1259 } else if (tmd2 & LE_T2_BUFF) { 1260 printf("%s: transmit buffer error\n", 1261 sc->sc_dev.dv_xname); 1262 } 1263 if (tmd2 & LE_T2_LCOL) 1264 ifp->if_collisions++; 1265 if (tmd2 & LE_T2_RTRY) 1266 ifp->if_collisions += 16; 1267 goto next_packet; 1268 } 1269 if (j == txs->txs_lastdesc) 1270 break; 1271 } 1272 if (tmd1 & LE_T1_ONE) 1273 ifp->if_collisions++; 1274 else if (tmd & LE_T1_MORE) { 1275 /* Real number is unknown. */ 1276 ifp->if_collisions += 2; 1277 } 1278 ifp->if_opackets++; 1279 next_packet: 1280 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1281 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1282 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1283 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1284 m_freem(txs->txs_mbuf); 1285 txs->txs_mbuf = NULL; 1286 } 1287 1288 /* Update the dirty transmit buffer pointer. */ 1289 sc->sc_txsdirty = i; 1290 1291 /* 1292 * If there are no more pending transmissions, cancel the watchdog 1293 * timer. 1294 */ 1295 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1296 ifp->if_timer = 0; 1297 } 1298 1299 /* 1300 * pcn_rxintr: 1301 * 1302 * Helper; handle receive interrupts. 1303 */ 1304 int 1305 pcn_rxintr(struct pcn_softc *sc) 1306 { 1307 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1308 struct pcn_rxsoft *rxs; 1309 struct mbuf *m; 1310 uint32_t rmd1; 1311 int i, len; 1312 1313 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1314 rxs = &sc->sc_rxsoft[i]; 1315 1316 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1317 1318 rmd1 = letoh32(sc->sc_rxdescs[i].rmd1); 1319 1320 if (rmd1 & LE_R1_OWN) 1321 break; 1322 1323 /* 1324 * Check for errors and make sure the packet fit into 1325 * a single buffer. We have structured this block of 1326 * code the way it is in order to compress it into 1327 * one test in the common case (no error). 1328 */ 1329 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1330 (LE_R1_STP|LE_R1_ENP))) { 1331 /* Make sure the packet is in a single buffer. */ 1332 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1333 (LE_R1_STP|LE_R1_ENP)) { 1334 printf("%s: packet spilled into next buffer\n", 1335 sc->sc_dev.dv_xname); 1336 return (1); /* pcn_intr() will re-init */ 1337 } 1338 1339 /* 1340 * If the packet had an error, simple recycle the 1341 * buffer. 1342 */ 1343 if (rmd1 & LE_R1_ERR) { 1344 ifp->if_ierrors++; 1345 /* 1346 * If we got an overflow error, chances 1347 * are there will be a CRC error. In 1348 * this case, just print the overflow 1349 * error, and skip the others. 1350 */ 1351 if (rmd1 & LE_R1_OFLO) 1352 printf("%s: overflow error\n", 1353 sc->sc_dev.dv_xname); 1354 else { 1355 #define PRINTIT(x, str) \ 1356 if (rmd1 & (x)) \ 1357 printf("%s: %s\n", \ 1358 sc->sc_dev.dv_xname, str); 1359 PRINTIT(LE_R1_FRAM, "framing error"); 1360 PRINTIT(LE_R1_CRC, "CRC error"); 1361 PRINTIT(LE_R1_BUFF, "buffer error"); 1362 } 1363 #undef PRINTIT 1364 PCN_INIT_RXDESC(sc, i); 1365 continue; 1366 } 1367 } 1368 1369 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1370 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1371 1372 /* 1373 * No errors; receive the packet. 1374 */ 1375 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1376 len = letoh32(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1377 else 1378 len = letoh32(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1379 1380 /* 1381 * The LANCE family includes the CRC with every packet; 1382 * trim it off here. 1383 */ 1384 len -= ETHER_CRC_LEN; 1385 1386 /* 1387 * If the packet is small enough to fit in a 1388 * single header mbuf, allocate one and copy 1389 * the data into it. This greatly reduces 1390 * memory consumption when we receive lots 1391 * of small packets. 1392 * 1393 * Otherwise, we add a new buffer to the receive 1394 * chain. If this fails, we drop the packet and 1395 * recycle the old buffer. 1396 */ 1397 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1398 MGETHDR(m, M_DONTWAIT, MT_DATA); 1399 if (m == NULL) 1400 goto dropit; 1401 m->m_data += 2; 1402 memcpy(mtod(m, caddr_t), 1403 mtod(rxs->rxs_mbuf, caddr_t), len); 1404 PCN_INIT_RXDESC(sc, i); 1405 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1406 rxs->rxs_dmamap->dm_mapsize, 1407 BUS_DMASYNC_PREREAD); 1408 } else { 1409 m = rxs->rxs_mbuf; 1410 if (pcn_add_rxbuf(sc, i) != 0) { 1411 dropit: 1412 ifp->if_ierrors++; 1413 PCN_INIT_RXDESC(sc, i); 1414 bus_dmamap_sync(sc->sc_dmat, 1415 rxs->rxs_dmamap, 0, 1416 rxs->rxs_dmamap->dm_mapsize, 1417 BUS_DMASYNC_PREREAD); 1418 continue; 1419 } 1420 } 1421 1422 m->m_pkthdr.rcvif = ifp; 1423 m->m_pkthdr.len = m->m_len = len; 1424 1425 #if NBPFILTER > 0 1426 /* Pass this up to any BPF listeners. */ 1427 if (ifp->if_bpf) 1428 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1429 #endif /* NBPFILTER > 0 */ 1430 1431 /* Pass it on. */ 1432 ether_input_mbuf(ifp, m); 1433 ifp->if_ipackets++; 1434 } 1435 1436 /* Update the receive pointer. */ 1437 sc->sc_rxptr = i; 1438 return (0); 1439 } 1440 1441 /* 1442 * pcn_tick: 1443 * 1444 * One second timer, used to tick the MII. 1445 */ 1446 void 1447 pcn_tick(void *arg) 1448 { 1449 struct pcn_softc *sc = arg; 1450 int s; 1451 1452 s = splnet(); 1453 mii_tick(&sc->sc_mii); 1454 splx(s); 1455 1456 timeout_add_sec(&sc->sc_tick_timeout, 1); 1457 } 1458 1459 /* 1460 * pcn_reset: 1461 * 1462 * Perform a soft reset on the PCnet-PCI. 1463 */ 1464 void 1465 pcn_reset(struct pcn_softc *sc) 1466 { 1467 1468 /* 1469 * The PCnet-PCI chip is reset by reading from the 1470 * RESET register. Note that while the NE2100 LANCE 1471 * boards require a write after the read, the PCnet-PCI 1472 * chips do not require this. 1473 * 1474 * Since we don't know if we're in 16-bit or 32-bit 1475 * mode right now, issue both (it's safe) in the 1476 * hopes that one will succeed. 1477 */ 1478 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1479 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1480 1481 /* Wait 1ms for it to finish. */ 1482 delay(1000); 1483 1484 /* 1485 * Select 32-bit I/O mode by issuing a 32-bit write to the 1486 * RDP. Since the RAP is 0 after a reset, writing a 0 1487 * to RDP is safe (since it simply clears CSR0). 1488 */ 1489 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1490 } 1491 1492 /* 1493 * pcn_init: [ifnet interface function] 1494 * 1495 * Initialize the interface. Must be called at splnet(). 1496 */ 1497 int 1498 pcn_init(struct ifnet *ifp) 1499 { 1500 struct pcn_softc *sc = ifp->if_softc; 1501 struct pcn_rxsoft *rxs; 1502 uint8_t *enaddr = LLADDR(ifp->if_sadl); 1503 int i, error = 0; 1504 uint32_t reg; 1505 1506 /* Cancel any pending I/O. */ 1507 pcn_stop(ifp, 0); 1508 1509 /* Reset the chip to a known state. */ 1510 pcn_reset(sc); 1511 1512 /* 1513 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1514 * else. 1515 * 1516 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1517 * because the structure layout is compatible with ILACC, 1518 * but the burst mode is only available in SSTYLE 3, and 1519 * burst mode should provide some performance enhancement. 1520 */ 1521 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1522 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1523 else 1524 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1525 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1526 1527 /* Initialize the transmit descriptor ring. */ 1528 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1529 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1530 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1531 sc->sc_txfree = PCN_NTXDESC; 1532 sc->sc_txnext = 0; 1533 1534 /* Initialize the transmit job descriptors. */ 1535 for (i = 0; i < PCN_TXQUEUELEN; i++) 1536 sc->sc_txsoft[i].txs_mbuf = NULL; 1537 sc->sc_txsfree = PCN_TXQUEUELEN; 1538 sc->sc_txsnext = 0; 1539 sc->sc_txsdirty = 0; 1540 1541 /* 1542 * Initialize the receive descriptor and receive job 1543 * descriptor rings. 1544 */ 1545 for (i = 0; i < PCN_NRXDESC; i++) { 1546 rxs = &sc->sc_rxsoft[i]; 1547 if (rxs->rxs_mbuf == NULL) { 1548 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1549 printf("%s: unable to allocate or map rx " 1550 "buffer %d, error = %d\n", 1551 sc->sc_dev.dv_xname, i, error); 1552 /* 1553 * XXX Should attempt to run with fewer receive 1554 * XXX buffers instead of just failing. 1555 */ 1556 pcn_rxdrain(sc); 1557 goto out; 1558 } 1559 } else 1560 PCN_INIT_RXDESC(sc, i); 1561 } 1562 sc->sc_rxptr = 0; 1563 1564 /* Initialize MODE for the initialization block. */ 1565 sc->sc_mode = 0; 1566 1567 /* 1568 * If we have MII, simply select MII in the MODE register, 1569 * and clear ASEL. Otherwise, let ASEL stand (for now), 1570 * and leave PORTSEL alone (it is ignored with ASEL is set). 1571 */ 1572 if (sc->sc_flags & PCN_F_HAS_MII) { 1573 pcn_bcr_write(sc, LE_BCR2, 1574 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1575 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1576 1577 /* 1578 * Disable MII auto-negotiation. We handle that in 1579 * our own MII layer. 1580 */ 1581 pcn_bcr_write(sc, LE_BCR32, 1582 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1583 } 1584 1585 /* Set the multicast filter in the init block. */ 1586 pcn_set_filter(sc); 1587 1588 /* 1589 * Set the Tx and Rx descriptor ring addresses in the init 1590 * block, the TLEN and RLEN other fields of the init block 1591 * MODE register. 1592 */ 1593 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1594 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1595 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1596 ((ffs(PCN_NTXDESC) - 1) << 28) | 1597 ((ffs(PCN_NRXDESC) - 1) << 20)); 1598 1599 /* Set the station address in the init block. */ 1600 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1601 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1602 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1603 (enaddr[5] << 8)); 1604 1605 /* Initialize CSR3. */ 1606 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1607 1608 /* Initialize CSR4. */ 1609 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1610 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1611 1612 /* Initialize CSR5. */ 1613 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1614 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1615 1616 /* 1617 * If we have an Am79c971 or greater, initialize CSR7. 1618 * 1619 * XXX Might be nice to use the MII auto-poll interrupt someday. 1620 */ 1621 switch (sc->sc_variant->pcv_chipid) { 1622 case PARTID_Am79c970: 1623 case PARTID_Am79c970A: 1624 /* Not available on these chips. */ 1625 break; 1626 1627 default: 1628 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1629 break; 1630 } 1631 1632 /* 1633 * On the Am79c970A and greater, initialize BCR18 to 1634 * enable burst mode. 1635 * 1636 * Also enable the "no underflow" option on the Am79c971 and 1637 * higher, which prevents the chip from generating transmit 1638 * underflows, yet sill provides decent performance. Note if 1639 * chip is not connected to external SRAM, then we still have 1640 * to handle underflow errors (the NOUFLO bit is ignored in 1641 * that case). 1642 */ 1643 reg = pcn_bcr_read(sc, LE_BCR18); 1644 switch (sc->sc_variant->pcv_chipid) { 1645 case PARTID_Am79c970: 1646 break; 1647 1648 case PARTID_Am79c970A: 1649 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1650 break; 1651 1652 default: 1653 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1654 break; 1655 } 1656 pcn_bcr_write(sc, LE_BCR18, reg); 1657 1658 /* 1659 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1660 */ 1661 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1662 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1663 1664 /* 1665 * Send the init block to the chip, and wait for it 1666 * to be processed. 1667 */ 1668 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1669 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1670 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1671 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1672 delay(100); 1673 for (i = 0; i < 10000; i++) { 1674 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1675 break; 1676 delay(10); 1677 } 1678 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1679 if (i == 10000) { 1680 printf("%s: timeout processing init block\n", 1681 sc->sc_dev.dv_xname); 1682 error = EIO; 1683 goto out; 1684 } 1685 1686 /* Set the media. */ 1687 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 1688 1689 /* Enable interrupts and external activity (and ACK IDON). */ 1690 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1691 1692 if (sc->sc_flags & PCN_F_HAS_MII) { 1693 /* Start the one second MII clock. */ 1694 timeout_add_sec(&sc->sc_tick_timeout, 1); 1695 } 1696 1697 /* ...all done! */ 1698 ifp->if_flags |= IFF_RUNNING; 1699 ifp->if_flags &= ~IFF_OACTIVE; 1700 1701 out: 1702 if (error) 1703 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1704 return (error); 1705 } 1706 1707 /* 1708 * pcn_rxdrain: 1709 * 1710 * Drain the receive queue. 1711 */ 1712 void 1713 pcn_rxdrain(struct pcn_softc *sc) 1714 { 1715 struct pcn_rxsoft *rxs; 1716 int i; 1717 1718 for (i = 0; i < PCN_NRXDESC; i++) { 1719 rxs = &sc->sc_rxsoft[i]; 1720 if (rxs->rxs_mbuf != NULL) { 1721 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1722 m_freem(rxs->rxs_mbuf); 1723 rxs->rxs_mbuf = NULL; 1724 } 1725 } 1726 } 1727 1728 /* 1729 * pcn_stop: [ifnet interface function] 1730 * 1731 * Stop transmission on the interface. 1732 */ 1733 void 1734 pcn_stop(struct ifnet *ifp, int disable) 1735 { 1736 struct pcn_softc *sc = ifp->if_softc; 1737 struct pcn_txsoft *txs; 1738 int i; 1739 1740 if (sc->sc_flags & PCN_F_HAS_MII) { 1741 /* Stop the one second clock. */ 1742 timeout_del(&sc->sc_tick_timeout); 1743 1744 /* Down the MII. */ 1745 mii_down(&sc->sc_mii); 1746 } 1747 1748 /* Mark the interface as down and cancel the watchdog timer. */ 1749 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1750 ifp->if_timer = 0; 1751 1752 /* Stop the chip. */ 1753 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1754 1755 /* Release any queued transmit buffers. */ 1756 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1757 txs = &sc->sc_txsoft[i]; 1758 if (txs->txs_mbuf != NULL) { 1759 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1760 m_freem(txs->txs_mbuf); 1761 txs->txs_mbuf = NULL; 1762 } 1763 } 1764 1765 if (disable) 1766 pcn_rxdrain(sc); 1767 } 1768 1769 /* 1770 * pcn_add_rxbuf: 1771 * 1772 * Add a receive buffer to the indicated descriptor. 1773 */ 1774 int 1775 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1776 { 1777 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1778 struct mbuf *m; 1779 int error; 1780 1781 MGETHDR(m, M_DONTWAIT, MT_DATA); 1782 if (m == NULL) 1783 return (ENOBUFS); 1784 1785 MCLGET(m, M_DONTWAIT); 1786 if ((m->m_flags & M_EXT) == 0) { 1787 m_freem(m); 1788 return (ENOBUFS); 1789 } 1790 1791 if (rxs->rxs_mbuf != NULL) 1792 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1793 1794 rxs->rxs_mbuf = m; 1795 1796 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1797 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1798 BUS_DMA_READ|BUS_DMA_NOWAIT); 1799 if (error) { 1800 printf("%s: can't load rx DMA map %d, error = %d\n", 1801 sc->sc_dev.dv_xname, idx, error); 1802 panic("pcn_add_rxbuf"); 1803 } 1804 1805 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1806 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1807 1808 PCN_INIT_RXDESC(sc, idx); 1809 1810 return (0); 1811 } 1812 1813 /* 1814 * pcn_set_filter: 1815 * 1816 * Set up the receive filter. 1817 */ 1818 void 1819 pcn_set_filter(struct pcn_softc *sc) 1820 { 1821 struct arpcom *ac = &sc->sc_arpcom; 1822 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1823 struct ether_multi *enm; 1824 struct ether_multistep step; 1825 uint32_t crc; 1826 1827 ifp->if_flags &= ~IFF_ALLMULTI; 1828 1829 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 1830 ifp->if_flags |= IFF_ALLMULTI; 1831 if (ifp->if_flags & IFF_PROMISC) 1832 sc->sc_mode |= LE_C15_PROM; 1833 sc->sc_initblock.init_ladrf[0] = 1834 sc->sc_initblock.init_ladrf[1] = 1835 sc->sc_initblock.init_ladrf[2] = 1836 sc->sc_initblock.init_ladrf[3] = 0xffff; 1837 } else { 1838 sc->sc_initblock.init_ladrf[0] = 1839 sc->sc_initblock.init_ladrf[1] = 1840 sc->sc_initblock.init_ladrf[2] = 1841 sc->sc_initblock.init_ladrf[3] = 0; 1842 1843 /* 1844 * Set up the multicast address filter by passing all multicast 1845 * addresses through a CRC generator, and then using the high 1846 * order 6 bits as an index into the 64-bit logical address 1847 * filter. The high order bits select the word, while the rest 1848 * of the bits select the bit within the word. 1849 */ 1850 ETHER_FIRST_MULTI(step, ac, enm); 1851 while (enm != NULL) { 1852 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1853 1854 /* Just want the 6 most significant bits. */ 1855 crc >>= 26; 1856 1857 /* Set the corresponding bit in the filter. */ 1858 sc->sc_initblock.init_ladrf[crc >> 4] |= 1859 htole16(1 << (crc & 0xf)); 1860 1861 ETHER_NEXT_MULTI(step, enm); 1862 } 1863 } 1864 } 1865 1866 /* 1867 * pcn_79c970_mediainit: 1868 * 1869 * Initialize media for the Am79c970. 1870 */ 1871 void 1872 pcn_79c970_mediainit(struct pcn_softc *sc) 1873 { 1874 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange, 1875 pcn_79c970_mediastatus); 1876 1877 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_10_5, 1878 PORTSEL_AUI, NULL); 1879 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1880 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_10_5|IFM_FDX, 1881 PORTSEL_AUI, NULL); 1882 1883 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_10_T, 1884 PORTSEL_10T, NULL); 1885 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1886 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_10_T|IFM_FDX, 1887 PORTSEL_10T, NULL); 1888 1889 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 1890 0, NULL); 1891 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1892 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO|IFM_FDX, 1893 0, NULL); 1894 1895 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1896 } 1897 1898 /* 1899 * pcn_79c970_mediastatus: [ifmedia interface function] 1900 * 1901 * Get the current interface media status (Am79c970 version). 1902 */ 1903 void 1904 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1905 { 1906 struct pcn_softc *sc = ifp->if_softc; 1907 1908 /* 1909 * The currently selected media is always the active media. 1910 * Note: We have no way to determine what media the AUTO 1911 * process picked. 1912 */ 1913 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 1914 } 1915 1916 /* 1917 * pcn_79c970_mediachange: [ifmedia interface function] 1918 * 1919 * Set hardware to newly-selected media (Am79c970 version). 1920 */ 1921 int 1922 pcn_79c970_mediachange(struct ifnet *ifp) 1923 { 1924 struct pcn_softc *sc = ifp->if_softc; 1925 uint32_t reg; 1926 1927 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 1928 /* 1929 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 1930 */ 1931 reg = pcn_bcr_read(sc, LE_BCR2); 1932 reg |= LE_B2_ASEL; 1933 pcn_bcr_write(sc, LE_BCR2, reg); 1934 } else { 1935 /* 1936 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 1937 */ 1938 reg = pcn_bcr_read(sc, LE_BCR2); 1939 reg &= ~LE_B2_ASEL; 1940 pcn_bcr_write(sc, LE_BCR2, reg); 1941 1942 reg = pcn_csr_read(sc, LE_CSR15); 1943 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 1944 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 1945 pcn_csr_write(sc, LE_CSR15, reg); 1946 } 1947 1948 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 1949 reg = LE_B9_FDEN; 1950 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 1951 reg |= LE_B9_AUIFD; 1952 pcn_bcr_write(sc, LE_BCR9, reg); 1953 } else 1954 pcn_bcr_write(sc, LE_BCR9, 0); 1955 1956 return (0); 1957 } 1958 1959 /* 1960 * pcn_79c971_mediainit: 1961 * 1962 * Initialize media for the Am79c971. 1963 */ 1964 void 1965 pcn_79c971_mediainit(struct pcn_softc *sc) 1966 { 1967 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1968 1969 /* We have MII. */ 1970 sc->sc_flags |= PCN_F_HAS_MII; 1971 1972 /* 1973 * The built-in 10BASE-T interface is mapped to the MII 1974 * on the PCNet-FAST. Unfortunately, there's no EEPROM 1975 * word that tells us which PHY to use. 1976 * This driver used to ignore all but the first PHY to 1977 * answer, but this code was removed to support multiple 1978 * external PHYs. As the default instance will be the first 1979 * one to answer, no harm is done by letting the possibly 1980 * non-connected internal PHY show up. 1981 */ 1982 1983 /* Initialize our media structures and probe the MII. */ 1984 sc->sc_mii.mii_ifp = ifp; 1985 sc->sc_mii.mii_readreg = pcn_mii_readreg; 1986 sc->sc_mii.mii_writereg = pcn_mii_writereg; 1987 sc->sc_mii.mii_statchg = pcn_mii_statchg; 1988 ifmedia_init(&sc->sc_mii.mii_media, 0, pcn_79c971_mediachange, 1989 pcn_79c971_mediastatus); 1990 1991 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1992 MII_OFFSET_ANY, 0); 1993 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1994 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1995 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1996 } else 1997 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1998 } 1999 2000 /* 2001 * pcn_79c971_mediastatus: [ifmedia interface function] 2002 * 2003 * Get the current interface media status (Am79c971 version). 2004 */ 2005 void 2006 pcn_79c971_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2007 { 2008 struct pcn_softc *sc = ifp->if_softc; 2009 2010 mii_pollstat(&sc->sc_mii); 2011 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2012 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2013 } 2014 2015 /* 2016 * pcn_79c971_mediachange: [ifmedia interface function] 2017 * 2018 * Set hardware to newly-selected media (Am79c971 version). 2019 */ 2020 int 2021 pcn_79c971_mediachange(struct ifnet *ifp) 2022 { 2023 struct pcn_softc *sc = ifp->if_softc; 2024 2025 if (ifp->if_flags & IFF_UP) 2026 mii_mediachg(&sc->sc_mii); 2027 return (0); 2028 } 2029 2030 /* 2031 * pcn_mii_readreg: [mii interface function] 2032 * 2033 * Read a PHY register on the MII. 2034 */ 2035 int 2036 pcn_mii_readreg(struct device *self, int phy, int reg) 2037 { 2038 struct pcn_softc *sc = (void *) self; 2039 uint32_t rv; 2040 2041 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2042 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2043 if (rv == 0xffff) 2044 return (0); 2045 2046 return (rv); 2047 } 2048 2049 /* 2050 * pcn_mii_writereg: [mii interface function] 2051 * 2052 * Write a PHY register on the MII. 2053 */ 2054 void 2055 pcn_mii_writereg(struct device *self, int phy, int reg, int val) 2056 { 2057 struct pcn_softc *sc = (void *) self; 2058 2059 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2060 pcn_bcr_write(sc, LE_BCR34, val); 2061 } 2062 2063 /* 2064 * pcn_mii_statchg: [mii interface function] 2065 * 2066 * Callback from MII layer when media changes. 2067 */ 2068 void 2069 pcn_mii_statchg(struct device *self) 2070 { 2071 struct pcn_softc *sc = (void *) self; 2072 2073 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2074 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2075 else 2076 pcn_bcr_write(sc, LE_BCR9, 0); 2077 } 2078