1 /* $OpenBSD: if_nge.c,v 1.78 2013/11/26 09:50:33 mpi Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 5 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_nge.c,v 1.35 2002/08/08 18:33:28 ambrisko Exp $ 35 */ 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #include "bpfilter.h" 92 #include "vlan.h" 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/sockio.h> 97 #include <sys/mbuf.h> 98 #include <sys/malloc.h> 99 #include <sys/kernel.h> 100 #include <sys/device.h> 101 #include <sys/socket.h> 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/ip.h> 111 #include <netinet/if_ether.h> 112 #endif 113 114 #if NVLAN > 0 115 #include <net/if_types.h> 116 #include <net/if_vlan_var.h> 117 #endif 118 119 #if NBPFILTER > 0 120 #include <net/bpf.h> 121 #endif 122 123 #include <uvm/uvm_extern.h> /* for vtophys */ 124 #define VTOPHYS(v) vtophys((vaddr_t)(v)) 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 #include <dev/pci/pcidevs.h> 129 130 #include <dev/mii/mii.h> 131 #include <dev/mii/miivar.h> 132 133 #define NGE_USEIOSPACE 134 135 #include <dev/pci/if_ngereg.h> 136 137 int nge_probe(struct device *, void *, void *); 138 void nge_attach(struct device *, struct device *, void *); 139 140 int nge_alloc_jumbo_mem(struct nge_softc *); 141 void *nge_jalloc(struct nge_softc *); 142 void nge_jfree(caddr_t, u_int, void *); 143 144 int nge_newbuf(struct nge_softc *, struct nge_desc *, 145 struct mbuf *); 146 int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *); 147 void nge_rxeof(struct nge_softc *); 148 void nge_txeof(struct nge_softc *); 149 int nge_intr(void *); 150 void nge_tick(void *); 151 void nge_start(struct ifnet *); 152 int nge_ioctl(struct ifnet *, u_long, caddr_t); 153 void nge_init(void *); 154 void nge_stop(struct nge_softc *); 155 void nge_watchdog(struct ifnet *); 156 int nge_ifmedia_mii_upd(struct ifnet *); 157 void nge_ifmedia_mii_sts(struct ifnet *, struct ifmediareq *); 158 int nge_ifmedia_tbi_upd(struct ifnet *); 159 void nge_ifmedia_tbi_sts(struct ifnet *, struct ifmediareq *); 160 161 void nge_delay(struct nge_softc *); 162 void nge_eeprom_idle(struct nge_softc *); 163 void nge_eeprom_putbyte(struct nge_softc *, int); 164 void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *); 165 void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int); 166 167 void nge_mii_sync(struct nge_softc *); 168 void nge_mii_send(struct nge_softc *, u_int32_t, int); 169 int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *); 170 int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *); 171 172 int nge_miibus_readreg(struct device *, int, int); 173 void nge_miibus_writereg(struct device *, int, int, int); 174 void nge_miibus_statchg(struct device *); 175 176 void nge_setmulti(struct nge_softc *); 177 void nge_reset(struct nge_softc *); 178 int nge_list_rx_init(struct nge_softc *); 179 int nge_list_tx_init(struct nge_softc *); 180 181 #ifdef NGE_USEIOSPACE 182 #define NGE_RES SYS_RES_IOPORT 183 #define NGE_RID NGE_PCI_LOIO 184 #else 185 #define NGE_RES SYS_RES_MEMORY 186 #define NGE_RID NGE_PCI_LOMEM 187 #endif 188 189 #ifdef NGE_DEBUG 190 #define DPRINTF(x) if (ngedebug) printf x 191 #define DPRINTFN(n,x) if (ngedebug >= (n)) printf x 192 int ngedebug = 0; 193 #else 194 #define DPRINTF(x) 195 #define DPRINTFN(n,x) 196 #endif 197 198 #define NGE_SETBIT(sc, reg, x) \ 199 CSR_WRITE_4(sc, reg, \ 200 CSR_READ_4(sc, reg) | (x)) 201 202 #define NGE_CLRBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, \ 204 CSR_READ_4(sc, reg) & ~(x)) 205 206 #define SIO_SET(x) \ 207 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 208 209 #define SIO_CLR(x) \ 210 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 211 212 void 213 nge_delay(struct nge_softc *sc) 214 { 215 int idx; 216 217 for (idx = (300 / 33) + 1; idx > 0; idx--) 218 CSR_READ_4(sc, NGE_CSR); 219 } 220 221 void 222 nge_eeprom_idle(struct nge_softc *sc) 223 { 224 int i; 225 226 SIO_SET(NGE_MEAR_EE_CSEL); 227 nge_delay(sc); 228 SIO_SET(NGE_MEAR_EE_CLK); 229 nge_delay(sc); 230 231 for (i = 0; i < 25; i++) { 232 SIO_CLR(NGE_MEAR_EE_CLK); 233 nge_delay(sc); 234 SIO_SET(NGE_MEAR_EE_CLK); 235 nge_delay(sc); 236 } 237 238 SIO_CLR(NGE_MEAR_EE_CLK); 239 nge_delay(sc); 240 SIO_CLR(NGE_MEAR_EE_CSEL); 241 nge_delay(sc); 242 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 243 } 244 245 /* 246 * Send a read command and address to the EEPROM, check for ACK. 247 */ 248 void 249 nge_eeprom_putbyte(struct nge_softc *sc, int addr) 250 { 251 int d, i; 252 253 d = addr | NGE_EECMD_READ; 254 255 /* 256 * Feed in each bit and strobe the clock. 257 */ 258 for (i = 0x400; i; i >>= 1) { 259 if (d & i) { 260 SIO_SET(NGE_MEAR_EE_DIN); 261 } else { 262 SIO_CLR(NGE_MEAR_EE_DIN); 263 } 264 nge_delay(sc); 265 SIO_SET(NGE_MEAR_EE_CLK); 266 nge_delay(sc); 267 SIO_CLR(NGE_MEAR_EE_CLK); 268 nge_delay(sc); 269 } 270 } 271 272 /* 273 * Read a word of data stored in the EEPROM at address 'addr.' 274 */ 275 void 276 nge_eeprom_getword(struct nge_softc *sc, int addr, u_int16_t *dest) 277 { 278 int i; 279 u_int16_t word = 0; 280 281 /* Force EEPROM to idle state. */ 282 nge_eeprom_idle(sc); 283 284 /* Enter EEPROM access mode. */ 285 nge_delay(sc); 286 SIO_CLR(NGE_MEAR_EE_CLK); 287 nge_delay(sc); 288 SIO_SET(NGE_MEAR_EE_CSEL); 289 nge_delay(sc); 290 291 /* 292 * Send address of word we want to read. 293 */ 294 nge_eeprom_putbyte(sc, addr); 295 296 /* 297 * Start reading bits from EEPROM. 298 */ 299 for (i = 0x8000; i; i >>= 1) { 300 SIO_SET(NGE_MEAR_EE_CLK); 301 nge_delay(sc); 302 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 303 word |= i; 304 nge_delay(sc); 305 SIO_CLR(NGE_MEAR_EE_CLK); 306 nge_delay(sc); 307 } 308 309 /* Turn off EEPROM access mode. */ 310 nge_eeprom_idle(sc); 311 312 *dest = word; 313 } 314 315 /* 316 * Read a sequence of words from the EEPROM. 317 */ 318 void 319 nge_read_eeprom(struct nge_softc *sc, caddr_t dest, int off, int cnt, int swap) 320 { 321 int i; 322 u_int16_t word = 0, *ptr; 323 324 for (i = 0; i < cnt; i++) { 325 nge_eeprom_getword(sc, off + i, &word); 326 ptr = (u_int16_t *)(dest + (i * 2)); 327 if (swap) 328 *ptr = ntohs(word); 329 else 330 *ptr = word; 331 } 332 } 333 334 /* 335 * Sync the PHYs by setting data bit and strobing the clock 32 times. 336 */ 337 void 338 nge_mii_sync(struct nge_softc *sc) 339 { 340 int i; 341 342 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 343 344 for (i = 0; i < 32; i++) { 345 SIO_SET(NGE_MEAR_MII_CLK); 346 DELAY(1); 347 SIO_CLR(NGE_MEAR_MII_CLK); 348 DELAY(1); 349 } 350 } 351 352 /* 353 * Clock a series of bits through the MII. 354 */ 355 void 356 nge_mii_send(struct nge_softc *sc, u_int32_t bits, int cnt) 357 { 358 int i; 359 360 SIO_CLR(NGE_MEAR_MII_CLK); 361 362 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 363 if (bits & i) { 364 SIO_SET(NGE_MEAR_MII_DATA); 365 } else { 366 SIO_CLR(NGE_MEAR_MII_DATA); 367 } 368 DELAY(1); 369 SIO_CLR(NGE_MEAR_MII_CLK); 370 DELAY(1); 371 SIO_SET(NGE_MEAR_MII_CLK); 372 } 373 } 374 375 /* 376 * Read an PHY register through the MII. 377 */ 378 int 379 nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame) 380 { 381 int i, ack, s; 382 383 s = splnet(); 384 385 /* 386 * Set up frame for RX. 387 */ 388 frame->mii_stdelim = NGE_MII_STARTDELIM; 389 frame->mii_opcode = NGE_MII_READOP; 390 frame->mii_turnaround = 0; 391 frame->mii_data = 0; 392 393 CSR_WRITE_4(sc, NGE_MEAR, 0); 394 395 /* 396 * Turn on data xmit. 397 */ 398 SIO_SET(NGE_MEAR_MII_DIR); 399 400 nge_mii_sync(sc); 401 402 /* 403 * Send command/address info. 404 */ 405 nge_mii_send(sc, frame->mii_stdelim, 2); 406 nge_mii_send(sc, frame->mii_opcode, 2); 407 nge_mii_send(sc, frame->mii_phyaddr, 5); 408 nge_mii_send(sc, frame->mii_regaddr, 5); 409 410 /* Idle bit */ 411 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 412 DELAY(1); 413 SIO_SET(NGE_MEAR_MII_CLK); 414 DELAY(1); 415 416 /* Turn off xmit. */ 417 SIO_CLR(NGE_MEAR_MII_DIR); 418 /* Check for ack */ 419 SIO_CLR(NGE_MEAR_MII_CLK); 420 DELAY(1); 421 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 422 SIO_SET(NGE_MEAR_MII_CLK); 423 DELAY(1); 424 425 /* 426 * Now try reading data bits. If the ack failed, we still 427 * need to clock through 16 cycles to keep the PHY(s) in sync. 428 */ 429 if (ack) { 430 for(i = 0; i < 16; i++) { 431 SIO_CLR(NGE_MEAR_MII_CLK); 432 DELAY(1); 433 SIO_SET(NGE_MEAR_MII_CLK); 434 DELAY(1); 435 } 436 goto fail; 437 } 438 439 for (i = 0x8000; i; i >>= 1) { 440 SIO_CLR(NGE_MEAR_MII_CLK); 441 DELAY(1); 442 if (!ack) { 443 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 444 frame->mii_data |= i; 445 DELAY(1); 446 } 447 SIO_SET(NGE_MEAR_MII_CLK); 448 DELAY(1); 449 } 450 451 fail: 452 453 SIO_CLR(NGE_MEAR_MII_CLK); 454 DELAY(1); 455 SIO_SET(NGE_MEAR_MII_CLK); 456 DELAY(1); 457 458 splx(s); 459 460 if (ack) 461 return(1); 462 return(0); 463 } 464 465 /* 466 * Write to a PHY register through the MII. 467 */ 468 int 469 nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame) 470 { 471 int s; 472 473 s = splnet(); 474 /* 475 * Set up frame for TX. 476 */ 477 478 frame->mii_stdelim = NGE_MII_STARTDELIM; 479 frame->mii_opcode = NGE_MII_WRITEOP; 480 frame->mii_turnaround = NGE_MII_TURNAROUND; 481 482 /* 483 * Turn on data output. 484 */ 485 SIO_SET(NGE_MEAR_MII_DIR); 486 487 nge_mii_sync(sc); 488 489 nge_mii_send(sc, frame->mii_stdelim, 2); 490 nge_mii_send(sc, frame->mii_opcode, 2); 491 nge_mii_send(sc, frame->mii_phyaddr, 5); 492 nge_mii_send(sc, frame->mii_regaddr, 5); 493 nge_mii_send(sc, frame->mii_turnaround, 2); 494 nge_mii_send(sc, frame->mii_data, 16); 495 496 /* Idle bit. */ 497 SIO_SET(NGE_MEAR_MII_CLK); 498 DELAY(1); 499 SIO_CLR(NGE_MEAR_MII_CLK); 500 DELAY(1); 501 502 /* 503 * Turn off xmit. 504 */ 505 SIO_CLR(NGE_MEAR_MII_DIR); 506 507 splx(s); 508 509 return(0); 510 } 511 512 int 513 nge_miibus_readreg(struct device *dev, int phy, int reg) 514 { 515 struct nge_softc *sc = (struct nge_softc *)dev; 516 struct nge_mii_frame frame; 517 518 DPRINTFN(9, ("%s: nge_miibus_readreg\n", sc->sc_dv.dv_xname)); 519 520 bzero(&frame, sizeof(frame)); 521 522 frame.mii_phyaddr = phy; 523 frame.mii_regaddr = reg; 524 nge_mii_readreg(sc, &frame); 525 526 return(frame.mii_data); 527 } 528 529 void 530 nge_miibus_writereg(struct device *dev, int phy, int reg, int data) 531 { 532 struct nge_softc *sc = (struct nge_softc *)dev; 533 struct nge_mii_frame frame; 534 535 536 DPRINTFN(9, ("%s: nge_miibus_writereg\n", sc->sc_dv.dv_xname)); 537 538 bzero(&frame, sizeof(frame)); 539 540 frame.mii_phyaddr = phy; 541 frame.mii_regaddr = reg; 542 frame.mii_data = data; 543 nge_mii_writereg(sc, &frame); 544 } 545 546 void 547 nge_miibus_statchg(struct device *dev) 548 { 549 struct nge_softc *sc = (struct nge_softc *)dev; 550 struct mii_data *mii = &sc->nge_mii; 551 u_int32_t txcfg, rxcfg; 552 553 txcfg = CSR_READ_4(sc, NGE_TX_CFG); 554 rxcfg = CSR_READ_4(sc, NGE_RX_CFG); 555 556 DPRINTFN(4, ("%s: nge_miibus_statchg txcfg=%#x, rxcfg=%#x\n", 557 sc->sc_dv.dv_xname, txcfg, rxcfg)); 558 559 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 560 txcfg |= (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR); 561 rxcfg |= (NGE_RXCFG_RX_FDX); 562 } else { 563 txcfg &= ~(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR); 564 rxcfg &= ~(NGE_RXCFG_RX_FDX); 565 } 566 567 txcfg |= NGE_TXCFG_AUTOPAD; 568 569 CSR_WRITE_4(sc, NGE_TX_CFG, txcfg); 570 CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg); 571 572 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 573 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 574 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 575 else 576 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 577 } 578 579 void 580 nge_setmulti(struct nge_softc *sc) 581 { 582 struct arpcom *ac = &sc->arpcom; 583 struct ifnet *ifp = &ac->ac_if; 584 struct ether_multi *enm; 585 struct ether_multistep step; 586 u_int32_t h = 0, i, filtsave; 587 int bit, index; 588 589 if (ac->ac_multirangecnt > 0) 590 ifp->if_flags |= IFF_ALLMULTI; 591 592 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 593 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 594 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 595 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 596 return; 597 } 598 599 /* 600 * We have to explicitly enable the multicast hash table 601 * on the NatSemi chip if we want to use it, which we do. 602 * We also have to tell it that we don't want to use the 603 * hash table for matching unicast addresses. 604 */ 605 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 606 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 607 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 608 609 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 610 611 /* first, zot all the existing hash bits */ 612 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 613 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 614 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 615 } 616 617 /* 618 * From the 11 bits returned by the crc routine, the top 7 619 * bits represent the 16-bit word in the mcast hash table 620 * that needs to be updated, and the lower 4 bits represent 621 * which bit within that byte needs to be set. 622 */ 623 ETHER_FIRST_MULTI(step, ac, enm); 624 while (enm != NULL) { 625 h = (ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 21) & 626 0x00000FFF; 627 index = (h >> 4) & 0x7F; 628 bit = h & 0xF; 629 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 630 NGE_FILTADDR_MCAST_LO + (index * 2)); 631 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 632 ETHER_NEXT_MULTI(step, enm); 633 } 634 635 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 636 } 637 638 void 639 nge_reset(struct nge_softc *sc) 640 { 641 int i; 642 643 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 644 645 for (i = 0; i < NGE_TIMEOUT; i++) { 646 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 647 break; 648 } 649 650 if (i == NGE_TIMEOUT) 651 printf("%s: reset never completed\n", sc->sc_dv.dv_xname); 652 653 /* Wait a little while for the chip to get its brains in order. */ 654 DELAY(1000); 655 656 /* 657 * If this is a NetSemi chip, make sure to clear 658 * PME mode. 659 */ 660 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 661 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 662 } 663 664 /* 665 * Probe for an NatSemi chip. Check the PCI vendor and device 666 * IDs against our list and return a device name if we find a match. 667 */ 668 int 669 nge_probe(struct device *parent, void *match, void *aux) 670 { 671 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 672 673 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 674 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_DP83820) 675 return (1); 676 677 return (0); 678 } 679 680 /* 681 * Attach the interface. Allocate softc structures, do ifmedia 682 * setup and ethernet/BPF attach. 683 */ 684 void 685 nge_attach(struct device *parent, struct device *self, void *aux) 686 { 687 struct nge_softc *sc = (struct nge_softc *)self; 688 struct pci_attach_args *pa = aux; 689 pci_chipset_tag_t pc = pa->pa_pc; 690 pci_intr_handle_t ih; 691 const char *intrstr = NULL; 692 bus_size_t size; 693 bus_dma_segment_t seg; 694 bus_dmamap_t dmamap; 695 int rseg; 696 u_char eaddr[ETHER_ADDR_LEN]; 697 #ifndef NGE_USEIOSPACE 698 pcireg_t memtype; 699 #endif 700 struct ifnet *ifp; 701 caddr_t kva; 702 703 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 704 705 /* 706 * Map control/status registers. 707 */ 708 DPRINTFN(5, ("%s: map control/status regs\n", sc->sc_dv.dv_xname)); 709 710 #ifdef NGE_USEIOSPACE 711 DPRINTFN(5, ("%s: pci_mapreg_map\n", sc->sc_dv.dv_xname)); 712 if (pci_mapreg_map(pa, NGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 713 &sc->nge_btag, &sc->nge_bhandle, NULL, &size, 0)) { 714 printf(": can't map i/o space\n"); 715 return; 716 } 717 #else 718 DPRINTFN(5, ("%s: pci_mapreg_map\n", sc->sc_dv.dv_xname)); 719 memtype = pci_mapreg_type(pc, pa->pa_tag, NGE_PCI_LOMEM); 720 if (pci_mapreg_map(pa, NGE_PCI_LOMEM, memtype, 0, &sc->nge_btag, 721 &sc->nge_bhandle, NULL, &size, 0)) { 722 printf(": can't map mem space\n"); 723 return; 724 } 725 #endif 726 727 /* Disable all interrupts */ 728 CSR_WRITE_4(sc, NGE_IER, 0); 729 730 DPRINTFN(5, ("%s: pci_intr_map\n", sc->sc_dv.dv_xname)); 731 if (pci_intr_map(pa, &ih)) { 732 printf(": couldn't map interrupt\n"); 733 goto fail_1; 734 } 735 736 DPRINTFN(5, ("%s: pci_intr_string\n", sc->sc_dv.dv_xname)); 737 intrstr = pci_intr_string(pc, ih); 738 DPRINTFN(5, ("%s: pci_intr_establish\n", sc->sc_dv.dv_xname)); 739 sc->nge_intrhand = pci_intr_establish(pc, ih, IPL_NET, nge_intr, sc, 740 sc->sc_dv.dv_xname); 741 if (sc->nge_intrhand == NULL) { 742 printf(": couldn't establish interrupt"); 743 if (intrstr != NULL) 744 printf(" at %s", intrstr); 745 printf("\n"); 746 goto fail_1; 747 } 748 printf(": %s", intrstr); 749 750 /* Reset the adapter. */ 751 DPRINTFN(5, ("%s: nge_reset\n", sc->sc_dv.dv_xname)); 752 nge_reset(sc); 753 754 /* 755 * Get station address from the EEPROM. 756 */ 757 DPRINTFN(5, ("%s: nge_read_eeprom\n", sc->sc_dv.dv_xname)); 758 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 759 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 760 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 761 762 /* 763 * A NatSemi chip was detected. Inform the world. 764 */ 765 printf(", address %s\n", ether_sprintf(eaddr)); 766 767 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 768 769 sc->sc_dmatag = pa->pa_dmat; 770 DPRINTFN(5, ("%s: bus_dmamem_alloc\n", sc->sc_dv.dv_xname)); 771 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct nge_list_data), 772 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT | 773 BUS_DMA_ZERO)) { 774 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 775 goto fail_2; 776 } 777 DPRINTFN(5, ("%s: bus_dmamem_map\n", sc->sc_dv.dv_xname)); 778 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 779 sizeof(struct nge_list_data), &kva, 780 BUS_DMA_NOWAIT)) { 781 printf("%s: can't map dma buffers (%zd bytes)\n", 782 sc->sc_dv.dv_xname, sizeof(struct nge_list_data)); 783 goto fail_3; 784 } 785 DPRINTFN(5, ("%s: bus_dmamem_create\n", sc->sc_dv.dv_xname)); 786 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct nge_list_data), 1, 787 sizeof(struct nge_list_data), 0, 788 BUS_DMA_NOWAIT, &dmamap)) { 789 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 790 goto fail_4; 791 } 792 DPRINTFN(5, ("%s: bus_dmamem_load\n", sc->sc_dv.dv_xname)); 793 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, 794 sizeof(struct nge_list_data), NULL, 795 BUS_DMA_NOWAIT)) { 796 goto fail_5; 797 } 798 799 DPRINTFN(5, ("%s: bzero\n", sc->sc_dv.dv_xname)); 800 sc->nge_ldata = (struct nge_list_data *)kva; 801 802 /* Try to allocate memory for jumbo buffers. */ 803 DPRINTFN(5, ("%s: nge_alloc_jumbo_mem\n", sc->sc_dv.dv_xname)); 804 if (nge_alloc_jumbo_mem(sc)) { 805 printf("%s: jumbo buffer allocation failed\n", 806 sc->sc_dv.dv_xname); 807 goto fail_5; 808 } 809 810 ifp = &sc->arpcom.ac_if; 811 ifp->if_softc = sc; 812 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 813 ifp->if_ioctl = nge_ioctl; 814 ifp->if_start = nge_start; 815 ifp->if_watchdog = nge_watchdog; 816 ifp->if_hardmtu = NGE_JUMBO_MTU; 817 IFQ_SET_MAXLEN(&ifp->if_snd, NGE_TX_LIST_CNT - 1); 818 IFQ_SET_READY(&ifp->if_snd); 819 DPRINTFN(5, ("%s: bcopy\n", sc->sc_dv.dv_xname)); 820 bcopy(sc->sc_dv.dv_xname, ifp->if_xname, IFNAMSIZ); 821 822 ifp->if_capabilities = IFCAP_VLAN_MTU; 823 824 #if NVLAN > 0 825 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 826 #endif 827 828 /* 829 * Do MII setup. 830 */ 831 DPRINTFN(5, ("%s: mii setup\n", sc->sc_dv.dv_xname)); 832 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 833 DPRINTFN(5, ("%s: TBI mode\n", sc->sc_dv.dv_xname)); 834 sc->nge_tbi = 1; 835 836 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_tbi_upd, 837 nge_ifmedia_tbi_sts); 838 839 ifmedia_add(&sc->nge_ifmedia, IFM_ETHER|IFM_NONE, 0, NULL), 840 ifmedia_add(&sc->nge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 841 ifmedia_add(&sc->nge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 842 0, NULL); 843 ifmedia_add(&sc->nge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 844 845 ifmedia_set(&sc->nge_ifmedia, IFM_ETHER|IFM_AUTO); 846 847 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 848 | NGE_GPIO_GP4_OUT 849 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 850 | NGE_GPIO_GP3_OUTENB | NGE_GPIO_GP4_OUTENB 851 | NGE_GPIO_GP5_OUTENB); 852 853 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 854 } else { 855 sc->nge_mii.mii_ifp = ifp; 856 sc->nge_mii.mii_readreg = nge_miibus_readreg; 857 sc->nge_mii.mii_writereg = nge_miibus_writereg; 858 sc->nge_mii.mii_statchg = nge_miibus_statchg; 859 860 ifmedia_init(&sc->nge_mii.mii_media, 0, nge_ifmedia_mii_upd, 861 nge_ifmedia_mii_sts); 862 mii_attach(&sc->sc_dv, &sc->nge_mii, 0xffffffff, MII_PHY_ANY, 863 MII_OFFSET_ANY, 0); 864 865 if (LIST_FIRST(&sc->nge_mii.mii_phys) == NULL) { 866 867 printf("%s: no PHY found!\n", sc->sc_dv.dv_xname); 868 ifmedia_add(&sc->nge_mii.mii_media, 869 IFM_ETHER|IFM_MANUAL, 0, NULL); 870 ifmedia_set(&sc->nge_mii.mii_media, 871 IFM_ETHER|IFM_MANUAL); 872 } 873 else 874 ifmedia_set(&sc->nge_mii.mii_media, 875 IFM_ETHER|IFM_AUTO); 876 } 877 878 /* 879 * Call MI attach routine. 880 */ 881 DPRINTFN(5, ("%s: if_attach\n", sc->sc_dv.dv_xname)); 882 if_attach(ifp); 883 DPRINTFN(5, ("%s: ether_ifattach\n", sc->sc_dv.dv_xname)); 884 ether_ifattach(ifp); 885 DPRINTFN(5, ("%s: timeout_set\n", sc->sc_dv.dv_xname)); 886 timeout_set(&sc->nge_timeout, nge_tick, sc); 887 timeout_add_sec(&sc->nge_timeout, 1); 888 return; 889 890 fail_5: 891 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 892 893 fail_4: 894 bus_dmamem_unmap(sc->sc_dmatag, kva, 895 sizeof(struct nge_list_data)); 896 897 fail_3: 898 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 899 900 fail_2: 901 pci_intr_disestablish(pc, sc->nge_intrhand); 902 903 fail_1: 904 bus_space_unmap(sc->nge_btag, sc->nge_bhandle, size); 905 } 906 907 /* 908 * Initialize the transmit descriptors. 909 */ 910 int 911 nge_list_tx_init(struct nge_softc *sc) 912 { 913 struct nge_list_data *ld; 914 struct nge_ring_data *cd; 915 int i; 916 917 cd = &sc->nge_cdata; 918 ld = sc->nge_ldata; 919 920 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 921 if (i == (NGE_TX_LIST_CNT - 1)) { 922 ld->nge_tx_list[i].nge_nextdesc = 923 &ld->nge_tx_list[0]; 924 ld->nge_tx_list[i].nge_next = 925 VTOPHYS(&ld->nge_tx_list[0]); 926 } else { 927 ld->nge_tx_list[i].nge_nextdesc = 928 &ld->nge_tx_list[i + 1]; 929 ld->nge_tx_list[i].nge_next = 930 VTOPHYS(&ld->nge_tx_list[i + 1]); 931 } 932 ld->nge_tx_list[i].nge_mbuf = NULL; 933 ld->nge_tx_list[i].nge_ptr = 0; 934 ld->nge_tx_list[i].nge_ctl = 0; 935 } 936 937 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 938 939 return(0); 940 } 941 942 943 /* 944 * Initialize the RX descriptors and allocate mbufs for them. Note that 945 * we arrange the descriptors in a closed ring, so that the last descriptor 946 * points back to the first. 947 */ 948 int 949 nge_list_rx_init(struct nge_softc *sc) 950 { 951 struct nge_list_data *ld; 952 struct nge_ring_data *cd; 953 int i; 954 955 ld = sc->nge_ldata; 956 cd = &sc->nge_cdata; 957 958 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 959 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 960 return(ENOBUFS); 961 if (i == (NGE_RX_LIST_CNT - 1)) { 962 ld->nge_rx_list[i].nge_nextdesc = 963 &ld->nge_rx_list[0]; 964 ld->nge_rx_list[i].nge_next = 965 VTOPHYS(&ld->nge_rx_list[0]); 966 } else { 967 ld->nge_rx_list[i].nge_nextdesc = 968 &ld->nge_rx_list[i + 1]; 969 ld->nge_rx_list[i].nge_next = 970 VTOPHYS(&ld->nge_rx_list[i + 1]); 971 } 972 } 973 974 cd->nge_rx_prod = 0; 975 976 return(0); 977 } 978 979 /* 980 * Initialize an RX descriptor and attach an MBUF cluster. 981 */ 982 int 983 nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m) 984 { 985 struct mbuf *m_new = NULL; 986 987 if (m == NULL) { 988 caddr_t buf = NULL; 989 990 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 991 if (m_new == NULL) 992 return (ENOBUFS); 993 994 /* Allocate the jumbo buffer */ 995 buf = nge_jalloc(sc); 996 if (buf == NULL) { 997 m_freem(m_new); 998 return (ENOBUFS); 999 } 1000 1001 /* Attach the buffer to the mbuf */ 1002 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES; 1003 MEXTADD(m_new, buf, NGE_MCLBYTES, 0, nge_jfree, sc); 1004 } else { 1005 /* 1006 * We're re-using a previously allocated mbuf; 1007 * be sure to re-init pointers and lengths to 1008 * default values. 1009 */ 1010 m_new = m; 1011 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES; 1012 m_new->m_data = m_new->m_ext.ext_buf; 1013 } 1014 1015 m_adj(m_new, sizeof(u_int64_t)); 1016 1017 c->nge_mbuf = m_new; 1018 c->nge_ptr = VTOPHYS(mtod(m_new, caddr_t)); 1019 DPRINTFN(7,("%s: c->nge_ptr=%#x\n", sc->sc_dv.dv_xname, 1020 c->nge_ptr)); 1021 c->nge_ctl = m_new->m_len; 1022 c->nge_extsts = 0; 1023 1024 return(0); 1025 } 1026 1027 int 1028 nge_alloc_jumbo_mem(struct nge_softc *sc) 1029 { 1030 caddr_t ptr, kva; 1031 bus_dma_segment_t seg; 1032 bus_dmamap_t dmamap; 1033 int i, rseg, state, error; 1034 struct nge_jpool_entry *entry; 1035 1036 state = error = 0; 1037 1038 if (bus_dmamem_alloc(sc->sc_dmatag, NGE_JMEM, PAGE_SIZE, 0, 1039 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1040 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 1041 return (ENOBUFS); 1042 } 1043 1044 state = 1; 1045 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, NGE_JMEM, &kva, 1046 BUS_DMA_NOWAIT)) { 1047 printf("%s: can't map dma buffers (%zd bytes)\n", 1048 sc->sc_dv.dv_xname, NGE_JMEM); 1049 error = ENOBUFS; 1050 goto out; 1051 } 1052 1053 state = 2; 1054 if (bus_dmamap_create(sc->sc_dmatag, NGE_JMEM, 1, 1055 NGE_JMEM, 0, BUS_DMA_NOWAIT, &dmamap)) { 1056 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 1057 error = ENOBUFS; 1058 goto out; 1059 } 1060 1061 state = 3; 1062 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, NGE_JMEM, 1063 NULL, BUS_DMA_NOWAIT)) { 1064 printf("%s: can't load dma map\n", sc->sc_dv.dv_xname); 1065 error = ENOBUFS; 1066 goto out; 1067 } 1068 1069 state = 4; 1070 sc->nge_cdata.nge_jumbo_buf = (caddr_t)kva; 1071 DPRINTFN(1,("%s: nge_jumbo_buf=%#x, NGE_MCLBYTES=%#x\n", 1072 sc->sc_dv.dv_xname , sc->nge_cdata.nge_jumbo_buf, 1073 NGE_MCLBYTES)); 1074 1075 LIST_INIT(&sc->nge_jfree_listhead); 1076 LIST_INIT(&sc->nge_jinuse_listhead); 1077 1078 /* 1079 * Now divide it up into 9K pieces and save the addresses 1080 * in an array. Note that we play an evil trick here by using 1081 * the first few bytes in the buffer to hold the address 1082 * of the softc structure for this interface. This is because 1083 * nge_jfree() needs it, but it is called by the mbuf management 1084 * code which will not pass it to us explicitly. 1085 */ 1086 ptr = sc->nge_cdata.nge_jumbo_buf; 1087 for (i = 0; i < NGE_JSLOTS; i++) { 1088 sc->nge_cdata.nge_jslots[i].nge_buf = ptr; 1089 sc->nge_cdata.nge_jslots[i].nge_inuse = 0; 1090 ptr += NGE_MCLBYTES; 1091 entry = malloc(sizeof(struct nge_jpool_entry), 1092 M_DEVBUF, M_NOWAIT); 1093 if (entry == NULL) { 1094 sc->nge_cdata.nge_jumbo_buf = NULL; 1095 printf("%s: no memory for jumbo buffer queue!\n", 1096 sc->sc_dv.dv_xname); 1097 error = ENOBUFS; 1098 goto out; 1099 } 1100 entry->slot = i; 1101 LIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, 1102 jpool_entries); 1103 } 1104 out: 1105 if (error != 0) { 1106 switch (state) { 1107 case 4: 1108 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1109 case 3: 1110 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1111 case 2: 1112 bus_dmamem_unmap(sc->sc_dmatag, kva, NGE_JMEM); 1113 case 1: 1114 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1115 break; 1116 default: 1117 break; 1118 } 1119 } 1120 1121 return (error); 1122 } 1123 1124 /* 1125 * Allocate a jumbo buffer. 1126 */ 1127 void * 1128 nge_jalloc(struct nge_softc *sc) 1129 { 1130 struct nge_jpool_entry *entry; 1131 1132 entry = LIST_FIRST(&sc->nge_jfree_listhead); 1133 1134 if (entry == NULL) 1135 return (NULL); 1136 1137 LIST_REMOVE(entry, jpool_entries); 1138 LIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1139 sc->nge_cdata.nge_jslots[entry->slot].nge_inuse = 1; 1140 return(sc->nge_cdata.nge_jslots[entry->slot].nge_buf); 1141 } 1142 1143 /* 1144 * Release a jumbo buffer. 1145 */ 1146 void 1147 nge_jfree(caddr_t buf, u_int size, void *arg) 1148 { 1149 struct nge_softc *sc; 1150 int i; 1151 struct nge_jpool_entry *entry; 1152 1153 /* Extract the softc struct pointer. */ 1154 sc = (struct nge_softc *)arg; 1155 1156 if (sc == NULL) 1157 panic("nge_jfree: can't find softc pointer!"); 1158 1159 /* calculate the slot this buffer belongs to */ 1160 1161 i = ((vaddr_t)buf - (vaddr_t)sc->nge_cdata.nge_jumbo_buf) 1162 / NGE_MCLBYTES; 1163 1164 if ((i < 0) || (i >= NGE_JSLOTS)) 1165 panic("nge_jfree: asked to free buffer that we don't manage!"); 1166 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0) 1167 panic("nge_jfree: buffer already free!"); 1168 else { 1169 sc->nge_cdata.nge_jslots[i].nge_inuse--; 1170 if(sc->nge_cdata.nge_jslots[i].nge_inuse == 0) { 1171 entry = LIST_FIRST(&sc->nge_jinuse_listhead); 1172 if (entry == NULL) 1173 panic("nge_jfree: buffer not in use!"); 1174 entry->slot = i; 1175 LIST_REMOVE(entry, jpool_entries); 1176 LIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1177 entry, jpool_entries); 1178 } 1179 } 1180 } 1181 1182 /* 1183 * A frame has been uploaded: pass the resulting mbuf chain up to 1184 * the higher level protocols. 1185 */ 1186 void 1187 nge_rxeof(struct nge_softc *sc) 1188 { 1189 struct mbuf *m; 1190 struct ifnet *ifp; 1191 struct nge_desc *cur_rx; 1192 int i, total_len = 0; 1193 u_int32_t rxstat; 1194 1195 ifp = &sc->arpcom.ac_if; 1196 i = sc->nge_cdata.nge_rx_prod; 1197 1198 while (NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1199 struct mbuf *m0 = NULL; 1200 u_int32_t extsts; 1201 1202 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1203 rxstat = cur_rx->nge_rxstat; 1204 extsts = cur_rx->nge_extsts; 1205 m = cur_rx->nge_mbuf; 1206 cur_rx->nge_mbuf = NULL; 1207 total_len = NGE_RXBYTES(cur_rx); 1208 NGE_INC(i, NGE_RX_LIST_CNT); 1209 1210 /* 1211 * If an error occurs, update stats, clear the 1212 * status word and leave the mbuf cluster in place: 1213 * it should simply get re-used next time this descriptor 1214 * comes up in the ring. 1215 */ 1216 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1217 #if NVLAN > 0 1218 if ((rxstat & NGE_RXSTAT_RUNT) && 1219 total_len >= (ETHER_MIN_LEN - ETHER_CRC_LEN - 1220 ETHER_VLAN_ENCAP_LEN)) { 1221 /* 1222 * Workaround a hardware bug. Accept runt 1223 * frames if its length is larger than or 1224 * equal to 56. 1225 */ 1226 } else { 1227 #endif 1228 ifp->if_ierrors++; 1229 nge_newbuf(sc, cur_rx, m); 1230 continue; 1231 #if NVLAN > 0 1232 } 1233 #endif 1234 } 1235 1236 /* 1237 * Ok. NatSemi really screwed up here. This is the 1238 * only gigE chip I know of with alignment constraints 1239 * on receive buffers. RX buffers must be 64-bit aligned. 1240 */ 1241 #ifndef __STRICT_ALIGNMENT 1242 /* 1243 * By popular demand, ignore the alignment problems 1244 * on the Intel x86 platform. The performance hit 1245 * incurred due to unaligned accesses is much smaller 1246 * than the hit produced by forcing buffer copies all 1247 * the time, especially with jumbo frames. We still 1248 * need to fix up the alignment everywhere else though. 1249 */ 1250 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1251 #endif 1252 m0 = m_devget(mtod(m, char *), total_len, 1253 ETHER_ALIGN, ifp); 1254 nge_newbuf(sc, cur_rx, m); 1255 if (m0 == NULL) { 1256 ifp->if_ierrors++; 1257 continue; 1258 } 1259 m_adj(m0, ETHER_ALIGN); 1260 m = m0; 1261 #ifndef __STRICT_ALIGNMENT 1262 } else { 1263 m->m_pkthdr.rcvif = ifp; 1264 m->m_pkthdr.len = m->m_len = total_len; 1265 } 1266 #endif 1267 1268 ifp->if_ipackets++; 1269 1270 #if NVLAN > 0 1271 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1272 m->m_pkthdr.ether_vtag = 1273 ntohs(extsts & NGE_RXEXTSTS_VTCI); 1274 m->m_flags |= M_VLANTAG; 1275 } 1276 #endif 1277 1278 #if NBPFILTER > 0 1279 /* 1280 * Handle BPF listeners. Let the BPF user see the packet. 1281 */ 1282 if (ifp->if_bpf) 1283 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 1284 #endif 1285 1286 /* Do IP checksum checking. */ 1287 if (extsts & NGE_RXEXTSTS_IPPKT) { 1288 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1289 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1290 if ((extsts & NGE_RXEXTSTS_TCPPKT) && 1291 (!(extsts & NGE_RXEXTSTS_TCPCSUMERR))) 1292 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 1293 else if ((extsts & NGE_RXEXTSTS_UDPPKT) && 1294 (!(extsts & NGE_RXEXTSTS_UDPCSUMERR))) 1295 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 1296 } 1297 1298 ether_input_mbuf(ifp, m); 1299 } 1300 1301 sc->nge_cdata.nge_rx_prod = i; 1302 } 1303 1304 /* 1305 * A frame was downloaded to the chip. It's safe for us to clean up 1306 * the list buffers. 1307 */ 1308 1309 void 1310 nge_txeof(struct nge_softc *sc) 1311 { 1312 struct nge_desc *cur_tx; 1313 struct ifnet *ifp; 1314 u_int32_t idx; 1315 1316 ifp = &sc->arpcom.ac_if; 1317 1318 /* 1319 * Go through our tx list and free mbufs for those 1320 * frames that have been transmitted. 1321 */ 1322 idx = sc->nge_cdata.nge_tx_cons; 1323 while (idx != sc->nge_cdata.nge_tx_prod) { 1324 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1325 1326 if (NGE_OWNDESC(cur_tx)) 1327 break; 1328 1329 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1330 sc->nge_cdata.nge_tx_cnt--; 1331 NGE_INC(idx, NGE_TX_LIST_CNT); 1332 continue; 1333 } 1334 1335 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1336 ifp->if_oerrors++; 1337 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1338 ifp->if_collisions++; 1339 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1340 ifp->if_collisions++; 1341 } 1342 1343 ifp->if_collisions += 1344 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1345 1346 ifp->if_opackets++; 1347 if (cur_tx->nge_mbuf != NULL) { 1348 m_freem(cur_tx->nge_mbuf); 1349 cur_tx->nge_mbuf = NULL; 1350 ifp->if_flags &= ~IFF_OACTIVE; 1351 } 1352 1353 sc->nge_cdata.nge_tx_cnt--; 1354 NGE_INC(idx, NGE_TX_LIST_CNT); 1355 } 1356 1357 sc->nge_cdata.nge_tx_cons = idx; 1358 1359 if (idx == sc->nge_cdata.nge_tx_prod) 1360 ifp->if_timer = 0; 1361 } 1362 1363 void 1364 nge_tick(void *xsc) 1365 { 1366 struct nge_softc *sc = xsc; 1367 struct mii_data *mii = &sc->nge_mii; 1368 struct ifnet *ifp = &sc->arpcom.ac_if; 1369 int s; 1370 1371 s = splnet(); 1372 1373 DPRINTFN(10, ("%s: nge_tick: link=%d\n", sc->sc_dv.dv_xname, 1374 sc->nge_link)); 1375 1376 timeout_add_sec(&sc->nge_timeout, 1); 1377 if (sc->nge_link) { 1378 splx(s); 1379 return; 1380 } 1381 1382 if (sc->nge_tbi) { 1383 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1384 == IFM_AUTO) { 1385 u_int32_t bmsr, anlpar, txcfg, rxcfg; 1386 1387 bmsr = CSR_READ_4(sc, NGE_TBI_BMSR); 1388 DPRINTFN(2, ("%s: nge_tick: bmsr=%#x\n", 1389 sc->sc_dv.dv_xname, bmsr)); 1390 1391 if (!(bmsr & NGE_TBIBMSR_ANEG_DONE)) { 1392 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1393 1394 splx(s); 1395 return; 1396 } 1397 1398 anlpar = CSR_READ_4(sc, NGE_TBI_ANLPAR); 1399 txcfg = CSR_READ_4(sc, NGE_TX_CFG); 1400 rxcfg = CSR_READ_4(sc, NGE_RX_CFG); 1401 1402 DPRINTFN(2, ("%s: nge_tick: anlpar=%#x, txcfg=%#x, " 1403 "rxcfg=%#x\n", sc->sc_dv.dv_xname, anlpar, 1404 txcfg, rxcfg)); 1405 1406 if (anlpar == 0 || anlpar & NGE_TBIANAR_FDX) { 1407 txcfg |= (NGE_TXCFG_IGN_HBEAT| 1408 NGE_TXCFG_IGN_CARR); 1409 rxcfg |= NGE_RXCFG_RX_FDX; 1410 } else { 1411 txcfg &= ~(NGE_TXCFG_IGN_HBEAT| 1412 NGE_TXCFG_IGN_CARR); 1413 rxcfg &= ~(NGE_RXCFG_RX_FDX); 1414 } 1415 txcfg |= NGE_TXCFG_AUTOPAD; 1416 CSR_WRITE_4(sc, NGE_TX_CFG, txcfg); 1417 CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg); 1418 } 1419 1420 DPRINTF(("%s: gigabit link up\n", sc->sc_dv.dv_xname)); 1421 sc->nge_link++; 1422 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1423 nge_start(ifp); 1424 } else { 1425 mii_tick(mii); 1426 if (mii->mii_media_status & IFM_ACTIVE && 1427 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1428 sc->nge_link++; 1429 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1430 DPRINTF(("%s: gigabit link up\n", 1431 sc->sc_dv.dv_xname)); 1432 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1433 nge_start(ifp); 1434 } 1435 1436 } 1437 1438 splx(s); 1439 } 1440 1441 int 1442 nge_intr(void *arg) 1443 { 1444 struct nge_softc *sc; 1445 struct ifnet *ifp; 1446 u_int32_t status; 1447 int claimed = 0; 1448 1449 sc = arg; 1450 ifp = &sc->arpcom.ac_if; 1451 1452 /* Suppress unwanted interrupts */ 1453 if (!(ifp->if_flags & IFF_UP)) { 1454 nge_stop(sc); 1455 return (0); 1456 } 1457 1458 /* Disable interrupts. */ 1459 CSR_WRITE_4(sc, NGE_IER, 0); 1460 1461 /* Data LED on for TBI mode */ 1462 if(sc->nge_tbi) 1463 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1464 | NGE_GPIO_GP3_OUT); 1465 1466 for (;;) { 1467 /* Reading the ISR register clears all interrupts. */ 1468 status = CSR_READ_4(sc, NGE_ISR); 1469 1470 if ((status & NGE_INTRS) == 0) 1471 break; 1472 1473 claimed = 1; 1474 1475 if ((status & NGE_ISR_TX_DESC_OK) || 1476 (status & NGE_ISR_TX_ERR) || 1477 (status & NGE_ISR_TX_OK) || 1478 (status & NGE_ISR_TX_IDLE)) 1479 nge_txeof(sc); 1480 1481 if ((status & NGE_ISR_RX_DESC_OK) || 1482 (status & NGE_ISR_RX_ERR) || 1483 (status & NGE_ISR_RX_OFLOW) || 1484 (status & NGE_ISR_RX_FIFO_OFLOW) || 1485 (status & NGE_ISR_RX_IDLE) || 1486 (status & NGE_ISR_RX_OK)) 1487 nge_rxeof(sc); 1488 1489 if ((status & NGE_ISR_RX_IDLE)) 1490 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1491 1492 if (status & NGE_ISR_SYSERR) { 1493 nge_reset(sc); 1494 ifp->if_flags &= ~IFF_RUNNING; 1495 nge_init(sc); 1496 } 1497 1498 #if 0 1499 /* 1500 * XXX: nge_tick() is not ready to be called this way 1501 * it screws up the aneg timeout because mii_tick() is 1502 * only to be called once per second. 1503 */ 1504 if (status & NGE_IMR_PHY_INTR) { 1505 sc->nge_link = 0; 1506 nge_tick(sc); 1507 } 1508 #endif 1509 } 1510 1511 /* Re-enable interrupts. */ 1512 CSR_WRITE_4(sc, NGE_IER, 1); 1513 1514 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1515 nge_start(ifp); 1516 1517 /* Data LED off for TBI mode */ 1518 if(sc->nge_tbi) 1519 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1520 & ~NGE_GPIO_GP3_OUT); 1521 1522 return claimed; 1523 } 1524 1525 /* 1526 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1527 * pointers to the fragment pointers. 1528 */ 1529 int 1530 nge_encap(struct nge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1531 { 1532 struct nge_desc *f = NULL; 1533 struct mbuf *m; 1534 int frag, cur, cnt = 0; 1535 1536 /* 1537 * Start packing the mbufs in this chain into 1538 * the fragment pointers. Stop when we run out 1539 * of fragments or hit the end of the mbuf chain. 1540 */ 1541 m = m_head; 1542 cur = frag = *txidx; 1543 1544 for (m = m_head; m != NULL; m = m->m_next) { 1545 if (m->m_len != 0) { 1546 if ((NGE_TX_LIST_CNT - 1547 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1548 return(ENOBUFS); 1549 f = &sc->nge_ldata->nge_tx_list[frag]; 1550 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1551 f->nge_ptr = VTOPHYS(mtod(m, vaddr_t)); 1552 DPRINTFN(7,("%s: f->nge_ptr=%#x\n", 1553 sc->sc_dv.dv_xname, f->nge_ptr)); 1554 if (cnt != 0) 1555 f->nge_ctl |= NGE_CMDSTS_OWN; 1556 cur = frag; 1557 NGE_INC(frag, NGE_TX_LIST_CNT); 1558 cnt++; 1559 } 1560 } 1561 1562 if (m != NULL) 1563 return(ENOBUFS); 1564 1565 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1566 1567 #if NVLAN > 0 1568 if (m_head->m_flags & M_VLANTAG) { 1569 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1570 (NGE_TXEXTSTS_VLANPKT|htons(m_head->m_pkthdr.ether_vtag)); 1571 } 1572 #endif 1573 1574 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1575 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1576 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1577 sc->nge_cdata.nge_tx_cnt += cnt; 1578 *txidx = frag; 1579 1580 return(0); 1581 } 1582 1583 /* 1584 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1585 * to the mbuf data regions directly in the transmit lists. We also save a 1586 * copy of the pointers since the transmit list fragment pointers are 1587 * physical addresses. 1588 */ 1589 1590 void 1591 nge_start(struct ifnet *ifp) 1592 { 1593 struct nge_softc *sc; 1594 struct mbuf *m_head = NULL; 1595 u_int32_t idx; 1596 int pkts = 0; 1597 1598 sc = ifp->if_softc; 1599 1600 if (!sc->nge_link) 1601 return; 1602 1603 idx = sc->nge_cdata.nge_tx_prod; 1604 1605 if (ifp->if_flags & IFF_OACTIVE) 1606 return; 1607 1608 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1609 IFQ_POLL(&ifp->if_snd, m_head); 1610 if (m_head == NULL) 1611 break; 1612 1613 if (nge_encap(sc, m_head, &idx)) { 1614 ifp->if_flags |= IFF_OACTIVE; 1615 break; 1616 } 1617 1618 /* now we are committed to transmit the packet */ 1619 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1620 pkts++; 1621 1622 #if NBPFILTER > 0 1623 /* 1624 * If there's a BPF listener, bounce a copy of this frame 1625 * to him. 1626 */ 1627 if (ifp->if_bpf) 1628 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1629 #endif 1630 } 1631 if (pkts == 0) 1632 return; 1633 1634 /* Transmit */ 1635 sc->nge_cdata.nge_tx_prod = idx; 1636 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1637 1638 /* 1639 * Set a timeout in case the chip goes out to lunch. 1640 */ 1641 ifp->if_timer = 5; 1642 } 1643 1644 void 1645 nge_init(void *xsc) 1646 { 1647 struct nge_softc *sc = xsc; 1648 struct ifnet *ifp = &sc->arpcom.ac_if; 1649 struct mii_data *mii; 1650 u_int32_t txcfg, rxcfg; 1651 int s, media; 1652 1653 if (ifp->if_flags & IFF_RUNNING) 1654 return; 1655 1656 s = splnet(); 1657 1658 /* 1659 * Cancel pending I/O and free all RX/TX buffers. 1660 */ 1661 nge_stop(sc); 1662 1663 mii = sc->nge_tbi ? NULL: &sc->nge_mii; 1664 1665 /* Set MAC address */ 1666 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1667 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1668 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1669 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1670 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1671 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1672 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1673 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1674 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1675 1676 /* Init circular RX list. */ 1677 if (nge_list_rx_init(sc) == ENOBUFS) { 1678 printf("%s: initialization failed: no " 1679 "memory for rx buffers\n", sc->sc_dv.dv_xname); 1680 nge_stop(sc); 1681 splx(s); 1682 return; 1683 } 1684 1685 /* 1686 * Init tx descriptors. 1687 */ 1688 nge_list_tx_init(sc); 1689 1690 /* 1691 * For the NatSemi chip, we have to explicitly enable the 1692 * reception of ARP frames, as well as turn on the 'perfect 1693 * match' filter where we store the station address, otherwise 1694 * we won't receive unicasts meant for this host. 1695 */ 1696 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1697 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1698 1699 /* If we want promiscuous mode, set the allframes bit. */ 1700 if (ifp->if_flags & IFF_PROMISC) 1701 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1702 else 1703 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1704 1705 /* 1706 * Set the capture broadcast bit to capture broadcast frames. 1707 */ 1708 if (ifp->if_flags & IFF_BROADCAST) 1709 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1710 else 1711 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1712 1713 /* 1714 * Load the multicast filter. 1715 */ 1716 nge_setmulti(sc); 1717 1718 /* Turn the receive filter on */ 1719 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1720 1721 /* 1722 * Load the address of the RX and TX lists. 1723 */ 1724 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1725 VTOPHYS(&sc->nge_ldata->nge_rx_list[0])); 1726 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1727 VTOPHYS(&sc->nge_ldata->nge_tx_list[0])); 1728 1729 /* Set RX configuration */ 1730 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1731 1732 /* 1733 * Enable hardware checksum validation for all IPv4 1734 * packets, do not reject packets with bad checksums. 1735 */ 1736 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1737 1738 /* 1739 * If VLAN support is enabled, tell the chip to detect 1740 * and strip VLAN tag info from received frames. The tag 1741 * will be provided in the extsts field in the RX descriptors. 1742 */ 1743 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1744 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1745 NGE_VIPRXCTL_TAG_DETECT_ENB | NGE_VIPRXCTL_TAG_STRIP_ENB); 1746 1747 /* Set TX configuration */ 1748 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1749 1750 /* 1751 * If VLAN support is enabled, tell the chip to insert 1752 * VLAN tags on a per-packet basis as dictated by the 1753 * code in the frame encapsulation routine. 1754 */ 1755 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1756 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1757 1758 /* Set full/half duplex mode. */ 1759 if (sc->nge_tbi) 1760 media = sc->nge_ifmedia.ifm_cur->ifm_media; 1761 else 1762 media = mii->mii_media_active; 1763 1764 txcfg = CSR_READ_4(sc, NGE_TX_CFG); 1765 rxcfg = CSR_READ_4(sc, NGE_RX_CFG); 1766 1767 DPRINTFN(4, ("%s: nge_init txcfg=%#x, rxcfg=%#x\n", 1768 sc->sc_dv.dv_xname, txcfg, rxcfg)); 1769 1770 if ((media & IFM_GMASK) == IFM_FDX) { 1771 txcfg |= (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR); 1772 rxcfg |= (NGE_RXCFG_RX_FDX); 1773 } else { 1774 txcfg &= ~(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR); 1775 rxcfg &= ~(NGE_RXCFG_RX_FDX); 1776 } 1777 1778 txcfg |= NGE_TXCFG_AUTOPAD; 1779 1780 CSR_WRITE_4(sc, NGE_TX_CFG, txcfg); 1781 CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg); 1782 1783 nge_tick(sc); 1784 1785 /* 1786 * Enable the delivery of PHY interrupts based on 1787 * link/speed/duplex status changes and enable return 1788 * of extended status information in the DMA descriptors, 1789 * required for checksum offloading. 1790 */ 1791 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD|NGE_CFG_PHYINTR_LNK| 1792 NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1793 1794 DPRINTFN(1, ("%s: nge_init: config=%#x\n", sc->sc_dv.dv_xname, 1795 CSR_READ_4(sc, NGE_CFG))); 1796 1797 /* 1798 * Configure interrupt holdoff (moderation). We can 1799 * have the chip delay interrupt delivery for a certain 1800 * period. Units are in 100us, and the max setting 1801 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1802 */ 1803 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1804 1805 /* 1806 * Enable interrupts. 1807 */ 1808 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1809 CSR_WRITE_4(sc, NGE_IER, 1); 1810 1811 /* Enable receiver and transmitter. */ 1812 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1813 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1814 1815 if (sc->nge_tbi) 1816 nge_ifmedia_tbi_upd(ifp); 1817 else 1818 nge_ifmedia_mii_upd(ifp); 1819 1820 ifp->if_flags |= IFF_RUNNING; 1821 ifp->if_flags &= ~IFF_OACTIVE; 1822 1823 splx(s); 1824 } 1825 1826 /* 1827 * Set mii media options. 1828 */ 1829 int 1830 nge_ifmedia_mii_upd(struct ifnet *ifp) 1831 { 1832 struct nge_softc *sc = ifp->if_softc; 1833 struct mii_data *mii = &sc->nge_mii; 1834 1835 DPRINTFN(2, ("%s: nge_ifmedia_mii_upd\n", sc->sc_dv.dv_xname)); 1836 1837 sc->nge_link = 0; 1838 1839 if (mii->mii_instance) { 1840 struct mii_softc *miisc; 1841 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1842 mii_phy_reset(miisc); 1843 } 1844 mii_mediachg(mii); 1845 1846 return(0); 1847 } 1848 1849 /* 1850 * Report current mii media status. 1851 */ 1852 void 1853 nge_ifmedia_mii_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1854 { 1855 struct nge_softc *sc = ifp->if_softc; 1856 struct mii_data *mii = &sc->nge_mii; 1857 1858 DPRINTFN(2, ("%s: nge_ifmedia_mii_sts\n", sc->sc_dv.dv_xname)); 1859 1860 mii_pollstat(mii); 1861 ifmr->ifm_active = mii->mii_media_active; 1862 ifmr->ifm_status = mii->mii_media_status; 1863 } 1864 1865 /* 1866 * Set mii media options. 1867 */ 1868 int 1869 nge_ifmedia_tbi_upd(struct ifnet *ifp) 1870 { 1871 struct nge_softc *sc = ifp->if_softc; 1872 1873 DPRINTFN(2, ("%s: nge_ifmedia_tbi_upd\n", sc->sc_dv.dv_xname)); 1874 1875 sc->nge_link = 0; 1876 1877 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1878 == IFM_AUTO) { 1879 u_int32_t anar, bmcr; 1880 anar = CSR_READ_4(sc, NGE_TBI_ANAR); 1881 anar |= (NGE_TBIANAR_HDX | NGE_TBIANAR_FDX); 1882 CSR_WRITE_4(sc, NGE_TBI_ANAR, anar); 1883 1884 bmcr = CSR_READ_4(sc, NGE_TBI_BMCR); 1885 bmcr |= (NGE_TBIBMCR_ENABLE_ANEG|NGE_TBIBMCR_RESTART_ANEG); 1886 CSR_WRITE_4(sc, NGE_TBI_BMCR, bmcr); 1887 1888 bmcr &= ~(NGE_TBIBMCR_RESTART_ANEG); 1889 CSR_WRITE_4(sc, NGE_TBI_BMCR, bmcr); 1890 } else { 1891 u_int32_t txcfg, rxcfg; 1892 txcfg = CSR_READ_4(sc, NGE_TX_CFG); 1893 rxcfg = CSR_READ_4(sc, NGE_RX_CFG); 1894 1895 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1896 == IFM_FDX) { 1897 txcfg |= NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR; 1898 rxcfg |= NGE_RXCFG_RX_FDX; 1899 } else { 1900 txcfg &= ~(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR); 1901 rxcfg &= ~(NGE_RXCFG_RX_FDX); 1902 } 1903 1904 txcfg |= NGE_TXCFG_AUTOPAD; 1905 CSR_WRITE_4(sc, NGE_TX_CFG, txcfg); 1906 CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg); 1907 } 1908 1909 NGE_CLRBIT(sc, NGE_GPIO, NGE_GPIO_GP3_OUT); 1910 1911 return(0); 1912 } 1913 1914 /* 1915 * Report current tbi media status. 1916 */ 1917 void 1918 nge_ifmedia_tbi_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1919 { 1920 struct nge_softc *sc = ifp->if_softc; 1921 u_int32_t bmcr; 1922 1923 bmcr = CSR_READ_4(sc, NGE_TBI_BMCR); 1924 1925 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) == IFM_AUTO) { 1926 u_int32_t bmsr = CSR_READ_4(sc, NGE_TBI_BMSR); 1927 DPRINTFN(2, ("%s: nge_ifmedia_tbi_sts bmsr=%#x, bmcr=%#x\n", 1928 sc->sc_dv.dv_xname, bmsr, bmcr)); 1929 1930 if (!(bmsr & NGE_TBIBMSR_ANEG_DONE)) { 1931 ifmr->ifm_active = IFM_ETHER|IFM_NONE; 1932 ifmr->ifm_status = IFM_AVALID; 1933 return; 1934 } 1935 } else { 1936 DPRINTFN(2, ("%s: nge_ifmedia_tbi_sts bmcr=%#x\n", 1937 sc->sc_dv.dv_xname, bmcr)); 1938 } 1939 1940 ifmr->ifm_status = IFM_AVALID|IFM_ACTIVE; 1941 ifmr->ifm_active = IFM_ETHER|IFM_1000_SX; 1942 1943 if (bmcr & NGE_TBIBMCR_LOOPBACK) 1944 ifmr->ifm_active |= IFM_LOOP; 1945 1946 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) == IFM_AUTO) { 1947 u_int32_t anlpar = CSR_READ_4(sc, NGE_TBI_ANLPAR); 1948 DPRINTFN(2, ("%s: nge_ifmedia_tbi_sts anlpar=%#x\n", 1949 sc->sc_dv.dv_xname, anlpar)); 1950 1951 ifmr->ifm_active |= IFM_AUTO; 1952 if (anlpar & NGE_TBIANLPAR_FDX) { 1953 ifmr->ifm_active |= IFM_FDX; 1954 } else if (anlpar & NGE_TBIANLPAR_HDX) { 1955 ifmr->ifm_active |= IFM_HDX; 1956 } else 1957 ifmr->ifm_active |= IFM_FDX; 1958 1959 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) == IFM_FDX) 1960 ifmr->ifm_active |= IFM_FDX; 1961 else 1962 ifmr->ifm_active |= IFM_HDX; 1963 1964 } 1965 1966 int 1967 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1968 { 1969 struct nge_softc *sc = ifp->if_softc; 1970 struct ifaddr *ifa = (struct ifaddr *) data; 1971 struct ifreq *ifr = (struct ifreq *) data; 1972 struct mii_data *mii; 1973 int s, error = 0; 1974 1975 s = splnet(); 1976 1977 switch(command) { 1978 case SIOCSIFADDR: 1979 ifp->if_flags |= IFF_UP; 1980 switch (ifa->ifa_addr->sa_family) { 1981 #ifdef INET 1982 case AF_INET: 1983 nge_init(sc); 1984 arp_ifinit(&sc->arpcom, ifa); 1985 break; 1986 #endif /* INET */ 1987 default: 1988 nge_init(sc); 1989 break; 1990 } 1991 break; 1992 1993 case SIOCSIFFLAGS: 1994 if (ifp->if_flags & IFF_UP) { 1995 if (ifp->if_flags & IFF_RUNNING && 1996 ifp->if_flags & IFF_PROMISC && 1997 !(sc->nge_if_flags & IFF_PROMISC)) { 1998 NGE_SETBIT(sc, NGE_RXFILT_CTL, 1999 NGE_RXFILTCTL_ALLPHYS| 2000 NGE_RXFILTCTL_ALLMULTI); 2001 } else if (ifp->if_flags & IFF_RUNNING && 2002 !(ifp->if_flags & IFF_PROMISC) && 2003 sc->nge_if_flags & IFF_PROMISC) { 2004 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2005 NGE_RXFILTCTL_ALLPHYS); 2006 if (!(ifp->if_flags & IFF_ALLMULTI)) 2007 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2008 NGE_RXFILTCTL_ALLMULTI); 2009 } else { 2010 ifp->if_flags &= ~IFF_RUNNING; 2011 nge_init(sc); 2012 } 2013 } else { 2014 if (ifp->if_flags & IFF_RUNNING) 2015 nge_stop(sc); 2016 } 2017 sc->nge_if_flags = ifp->if_flags; 2018 error = 0; 2019 break; 2020 2021 case SIOCGIFMEDIA: 2022 case SIOCSIFMEDIA: 2023 if (sc->nge_tbi) { 2024 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 2025 command); 2026 } else { 2027 mii = &sc->nge_mii; 2028 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2029 command); 2030 } 2031 break; 2032 2033 default: 2034 error = ether_ioctl(ifp, &sc->arpcom, command, data); 2035 } 2036 2037 if (error == ENETRESET) { 2038 if (ifp->if_flags & IFF_RUNNING) 2039 nge_setmulti(sc); 2040 error = 0; 2041 } 2042 2043 splx(s); 2044 return(error); 2045 } 2046 2047 void 2048 nge_watchdog(struct ifnet *ifp) 2049 { 2050 struct nge_softc *sc; 2051 2052 sc = ifp->if_softc; 2053 2054 ifp->if_oerrors++; 2055 printf("%s: watchdog timeout\n", sc->sc_dv.dv_xname); 2056 2057 nge_stop(sc); 2058 nge_reset(sc); 2059 ifp->if_flags &= ~IFF_RUNNING; 2060 nge_init(sc); 2061 2062 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2063 nge_start(ifp); 2064 } 2065 2066 /* 2067 * Stop the adapter and free any mbufs allocated to the 2068 * RX and TX lists. 2069 */ 2070 void 2071 nge_stop(struct nge_softc *sc) 2072 { 2073 int i; 2074 struct ifnet *ifp; 2075 struct mii_data *mii; 2076 2077 ifp = &sc->arpcom.ac_if; 2078 ifp->if_timer = 0; 2079 if (sc->nge_tbi) { 2080 mii = NULL; 2081 } else { 2082 mii = &sc->nge_mii; 2083 } 2084 2085 timeout_del(&sc->nge_timeout); 2086 2087 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2088 2089 CSR_WRITE_4(sc, NGE_IER, 0); 2090 CSR_WRITE_4(sc, NGE_IMR, 0); 2091 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2092 DELAY(1000); 2093 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2094 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2095 2096 if (!sc->nge_tbi) 2097 mii_down(mii); 2098 2099 sc->nge_link = 0; 2100 2101 /* 2102 * Free data in the RX lists. 2103 */ 2104 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2105 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2106 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2107 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2108 } 2109 } 2110 bzero(&sc->nge_ldata->nge_rx_list, 2111 sizeof(sc->nge_ldata->nge_rx_list)); 2112 2113 /* 2114 * Free the TX list buffers. 2115 */ 2116 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2117 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2118 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2119 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2120 } 2121 } 2122 2123 bzero(&sc->nge_ldata->nge_tx_list, 2124 sizeof(sc->nge_ldata->nge_tx_list)); 2125 } 2126 2127 struct cfattach nge_ca = { 2128 sizeof(struct nge_softc), nge_probe, nge_attach 2129 }; 2130 2131 struct cfdriver nge_cd = { 2132 NULL, "nge", DV_IFNET 2133 }; 2134