1 /* $OpenBSD: if_nge.c,v 1.15 2001/11/13 21:00:16 mickey Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 5 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.19 2001/07/25 00:19:55 brooks Exp $ 35 */ 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #include "bpfilter.h" 92 #include "vlan.h" 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/sockio.h> 97 #include <sys/mbuf.h> 98 #include <sys/malloc.h> 99 #include <sys/kernel.h> 100 #include <sys/device.h> 101 #include <sys/socket.h> 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/in_var.h> 111 #include <netinet/ip.h> 112 #include <netinet/if_ether.h> 113 #endif 114 115 #if NVLAN > 0 116 #include <net/if_types.h> 117 #include <net/if_vlan_var.h> 118 #endif 119 120 #if NBPFILTER > 0 121 #include <net/bpf.h> 122 #endif 123 124 #include <uvm/uvm_extern.h> /* for vtophys */ 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 #include <dev/pci/pcidevs.h> 129 130 #include <dev/mii/mii.h> 131 #include <dev/mii/miivar.h> 132 133 #define NGE_USEIOSPACE 134 135 #include <dev/pci/if_ngereg.h> 136 137 int nge_probe __P((struct device *, void *, void *)); 138 void nge_attach __P((struct device *, struct device *, void *)); 139 140 int nge_alloc_jumbo_mem __P((struct nge_softc *)); 141 void *nge_jalloc __P((struct nge_softc *)); 142 void nge_jfree __P((caddr_t, u_int, void *)); 143 144 int nge_newbuf __P((struct nge_softc *, struct nge_desc *, 145 struct mbuf *)); 146 int nge_encap __P((struct nge_softc *, struct mbuf *, u_int32_t *)); 147 void nge_rxeof __P((struct nge_softc *)); 148 void nge_rxeoc __P((struct nge_softc *)); 149 void nge_txeof __P((struct nge_softc *)); 150 int nge_intr __P((void *)); 151 void nge_tick __P((void *)); 152 void nge_start __P((struct ifnet *)); 153 int nge_ioctl __P((struct ifnet *, u_long, caddr_t)); 154 void nge_init __P((void *)); 155 void nge_stop __P((struct nge_softc *)); 156 void nge_watchdog __P((struct ifnet *)); 157 void nge_shutdown __P((void *)); 158 int nge_ifmedia_upd __P((struct ifnet *)); 159 void nge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 160 161 void nge_delay __P((struct nge_softc *)); 162 void nge_eeprom_idle __P((struct nge_softc *)); 163 void nge_eeprom_putbyte __P((struct nge_softc *, int)); 164 void nge_eeprom_getword __P((struct nge_softc *, int, u_int16_t *)); 165 void nge_read_eeprom __P((struct nge_softc *, caddr_t, int, int, int)); 166 167 void nge_mii_sync __P((struct nge_softc *)); 168 void nge_mii_send __P((struct nge_softc *, u_int32_t, int)); 169 int nge_mii_readreg __P((struct nge_softc *, struct nge_mii_frame *)); 170 int nge_mii_writereg __P((struct nge_softc *, struct nge_mii_frame *)); 171 172 int nge_miibus_readreg __P((struct device *, int, int)); 173 void nge_miibus_writereg __P((struct device *, int, int, int)); 174 void nge_miibus_statchg __P((struct device *)); 175 176 void nge_setmulti __P((struct nge_softc *)); 177 u_int32_t nge_crc __P((struct nge_softc *, caddr_t)); 178 void nge_reset __P((struct nge_softc *)); 179 int nge_list_rx_init __P((struct nge_softc *)); 180 int nge_list_tx_init __P((struct nge_softc *)); 181 182 #ifdef NGE_USEIOSPACE 183 #define NGE_RES SYS_RES_IOPORT 184 #define NGE_RID NGE_PCI_LOIO 185 #else 186 #define NGE_RES SYS_RES_MEMORY 187 #define NGE_RID NGE_PCI_LOMEM 188 #endif 189 190 #ifdef NGE_DEBUG 191 #define DPRINTF(x) if (ngedebug) printf x 192 #define DPRINTFN(n,x) if (ngedebug >= (n)) printf x 193 int ngedebug = 0; 194 #else 195 #define DPRINTF(x) 196 #define DPRINTFN(n,x) 197 #endif 198 199 #define NGE_SETBIT(sc, reg, x) \ 200 CSR_WRITE_4(sc, reg, \ 201 CSR_READ_4(sc, reg) | (x)) 202 203 #define NGE_CLRBIT(sc, reg, x) \ 204 CSR_WRITE_4(sc, reg, \ 205 CSR_READ_4(sc, reg) & ~(x)) 206 207 #define SIO_SET(x) \ 208 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x) 209 210 #define SIO_CLR(x) \ 211 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x) 212 213 void nge_delay(sc) 214 struct nge_softc *sc; 215 { 216 int idx; 217 218 for (idx = (300 / 33) + 1; idx > 0; idx--) 219 CSR_READ_4(sc, NGE_CSR); 220 } 221 222 void nge_eeprom_idle(sc) 223 struct nge_softc *sc; 224 { 225 int i; 226 227 SIO_SET(NGE_MEAR_EE_CSEL); 228 nge_delay(sc); 229 SIO_SET(NGE_MEAR_EE_CLK); 230 nge_delay(sc); 231 232 for (i = 0; i < 25; i++) { 233 SIO_CLR(NGE_MEAR_EE_CLK); 234 nge_delay(sc); 235 SIO_SET(NGE_MEAR_EE_CLK); 236 nge_delay(sc); 237 } 238 239 SIO_CLR(NGE_MEAR_EE_CLK); 240 nge_delay(sc); 241 SIO_CLR(NGE_MEAR_EE_CSEL); 242 nge_delay(sc); 243 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 244 } 245 246 /* 247 * Send a read command and address to the EEPROM, check for ACK. 248 */ 249 void nge_eeprom_putbyte(sc, addr) 250 struct nge_softc *sc; 251 int addr; 252 { 253 register int d, i; 254 255 d = addr | NGE_EECMD_READ; 256 257 /* 258 * Feed in each bit and stobe the clock. 259 */ 260 for (i = 0x400; i; i >>= 1) { 261 if (d & i) { 262 SIO_SET(NGE_MEAR_EE_DIN); 263 } else { 264 SIO_CLR(NGE_MEAR_EE_DIN); 265 } 266 nge_delay(sc); 267 SIO_SET(NGE_MEAR_EE_CLK); 268 nge_delay(sc); 269 SIO_CLR(NGE_MEAR_EE_CLK); 270 nge_delay(sc); 271 } 272 } 273 274 /* 275 * Read a word of data stored in the EEPROM at address 'addr.' 276 */ 277 void nge_eeprom_getword(sc, addr, dest) 278 struct nge_softc *sc; 279 int addr; 280 u_int16_t *dest; 281 { 282 register int i; 283 u_int16_t word = 0; 284 285 /* Force EEPROM to idle state. */ 286 nge_eeprom_idle(sc); 287 288 /* Enter EEPROM access mode. */ 289 nge_delay(sc); 290 SIO_CLR(NGE_MEAR_EE_CLK); 291 nge_delay(sc); 292 SIO_SET(NGE_MEAR_EE_CSEL); 293 nge_delay(sc); 294 295 /* 296 * Send address of word we want to read. 297 */ 298 nge_eeprom_putbyte(sc, addr); 299 300 /* 301 * Start reading bits from EEPROM. 302 */ 303 for (i = 0x8000; i; i >>= 1) { 304 SIO_SET(NGE_MEAR_EE_CLK); 305 nge_delay(sc); 306 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 307 word |= i; 308 nge_delay(sc); 309 SIO_CLR(NGE_MEAR_EE_CLK); 310 nge_delay(sc); 311 } 312 313 /* Turn off EEPROM access mode. */ 314 nge_eeprom_idle(sc); 315 316 *dest = word; 317 } 318 319 /* 320 * Read a sequence of words from the EEPROM. 321 */ 322 void nge_read_eeprom(sc, dest, off, cnt, swap) 323 struct nge_softc *sc; 324 caddr_t dest; 325 int off; 326 int cnt; 327 int swap; 328 { 329 int i; 330 u_int16_t word = 0, *ptr; 331 332 for (i = 0; i < cnt; i++) { 333 nge_eeprom_getword(sc, off + i, &word); 334 ptr = (u_int16_t *)(dest + (i * 2)); 335 if (swap) 336 *ptr = ntohs(word); 337 else 338 *ptr = word; 339 } 340 } 341 342 /* 343 * Sync the PHYs by setting data bit and strobing the clock 32 times. 344 */ 345 void nge_mii_sync(sc) 346 struct nge_softc *sc; 347 { 348 register int i; 349 350 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 351 352 for (i = 0; i < 32; i++) { 353 SIO_SET(NGE_MEAR_MII_CLK); 354 DELAY(1); 355 SIO_CLR(NGE_MEAR_MII_CLK); 356 DELAY(1); 357 } 358 } 359 360 /* 361 * Clock a series of bits through the MII. 362 */ 363 void nge_mii_send(sc, bits, cnt) 364 struct nge_softc *sc; 365 u_int32_t bits; 366 int cnt; 367 { 368 int i; 369 370 SIO_CLR(NGE_MEAR_MII_CLK); 371 372 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 373 if (bits & i) { 374 SIO_SET(NGE_MEAR_MII_DATA); 375 } else { 376 SIO_CLR(NGE_MEAR_MII_DATA); 377 } 378 DELAY(1); 379 SIO_CLR(NGE_MEAR_MII_CLK); 380 DELAY(1); 381 SIO_SET(NGE_MEAR_MII_CLK); 382 } 383 } 384 385 /* 386 * Read an PHY register through the MII. 387 */ 388 int nge_mii_readreg(sc, frame) 389 struct nge_softc *sc; 390 struct nge_mii_frame *frame; 391 { 392 int i, ack, s; 393 394 s = splimp(); 395 396 /* 397 * Set up frame for RX. 398 */ 399 frame->mii_stdelim = NGE_MII_STARTDELIM; 400 frame->mii_opcode = NGE_MII_READOP; 401 frame->mii_turnaround = 0; 402 frame->mii_data = 0; 403 404 CSR_WRITE_4(sc, NGE_MEAR, 0); 405 406 /* 407 * Turn on data xmit. 408 */ 409 SIO_SET(NGE_MEAR_MII_DIR); 410 411 nge_mii_sync(sc); 412 413 /* 414 * Send command/address info. 415 */ 416 nge_mii_send(sc, frame->mii_stdelim, 2); 417 nge_mii_send(sc, frame->mii_opcode, 2); 418 nge_mii_send(sc, frame->mii_phyaddr, 5); 419 nge_mii_send(sc, frame->mii_regaddr, 5); 420 421 /* Idle bit */ 422 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 423 DELAY(1); 424 SIO_SET(NGE_MEAR_MII_CLK); 425 DELAY(1); 426 427 /* Turn off xmit. */ 428 SIO_CLR(NGE_MEAR_MII_DIR); 429 /* Check for ack */ 430 SIO_CLR(NGE_MEAR_MII_CLK); 431 DELAY(1); 432 SIO_SET(NGE_MEAR_MII_CLK); 433 DELAY(1); 434 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 435 436 /* 437 * Now try reading data bits. If the ack failed, we still 438 * need to clock through 16 cycles to keep the PHY(s) in sync. 439 */ 440 if (ack) { 441 for(i = 0; i < 16; i++) { 442 SIO_CLR(NGE_MEAR_MII_CLK); 443 DELAY(1); 444 SIO_SET(NGE_MEAR_MII_CLK); 445 DELAY(1); 446 } 447 goto fail; 448 } 449 450 for (i = 0x8000; i; i >>= 1) { 451 SIO_CLR(NGE_MEAR_MII_CLK); 452 DELAY(1); 453 if (!ack) { 454 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 455 frame->mii_data |= i; 456 DELAY(1); 457 } 458 SIO_SET(NGE_MEAR_MII_CLK); 459 DELAY(1); 460 } 461 462 fail: 463 464 SIO_CLR(NGE_MEAR_MII_CLK); 465 DELAY(1); 466 SIO_SET(NGE_MEAR_MII_CLK); 467 DELAY(1); 468 469 splx(s); 470 471 if (ack) 472 return(1); 473 return(0); 474 } 475 476 /* 477 * Write to a PHY register through the MII. 478 */ 479 int nge_mii_writereg(sc, frame) 480 struct nge_softc *sc; 481 struct nge_mii_frame *frame; 482 { 483 int s; 484 485 s = splimp(); 486 /* 487 * Set up frame for TX. 488 */ 489 490 frame->mii_stdelim = NGE_MII_STARTDELIM; 491 frame->mii_opcode = NGE_MII_WRITEOP; 492 frame->mii_turnaround = NGE_MII_TURNAROUND; 493 494 /* 495 * Turn on data output. 496 */ 497 SIO_SET(NGE_MEAR_MII_DIR); 498 499 nge_mii_sync(sc); 500 501 nge_mii_send(sc, frame->mii_stdelim, 2); 502 nge_mii_send(sc, frame->mii_opcode, 2); 503 nge_mii_send(sc, frame->mii_phyaddr, 5); 504 nge_mii_send(sc, frame->mii_regaddr, 5); 505 nge_mii_send(sc, frame->mii_turnaround, 2); 506 nge_mii_send(sc, frame->mii_data, 16); 507 508 /* Idle bit. */ 509 SIO_SET(NGE_MEAR_MII_CLK); 510 DELAY(1); 511 SIO_CLR(NGE_MEAR_MII_CLK); 512 DELAY(1); 513 514 /* 515 * Turn off xmit. 516 */ 517 SIO_CLR(NGE_MEAR_MII_DIR); 518 519 splx(s); 520 521 return(0); 522 } 523 524 int nge_miibus_readreg(dev, phy, reg) 525 struct device *dev; 526 int phy, reg; 527 { 528 struct nge_softc *sc = (struct nge_softc *)dev; 529 struct nge_mii_frame frame; 530 531 bzero((char *)&frame, sizeof(frame)); 532 533 frame.mii_phyaddr = phy; 534 frame.mii_regaddr = reg; 535 nge_mii_readreg(sc, &frame); 536 537 return(frame.mii_data); 538 } 539 540 void nge_miibus_writereg(dev, phy, reg, data) 541 struct device *dev; 542 int phy, reg, data; 543 { 544 struct nge_softc *sc = (struct nge_softc *)dev; 545 struct nge_mii_frame frame; 546 547 548 bzero((char *)&frame, sizeof(frame)); 549 550 frame.mii_phyaddr = phy; 551 frame.mii_regaddr = reg; 552 frame.mii_data = data; 553 nge_mii_writereg(sc, &frame); 554 } 555 556 void nge_miibus_statchg(dev) 557 struct device *dev; 558 { 559 struct nge_softc *sc = (struct nge_softc *)dev; 560 struct mii_data *mii = &sc->nge_mii; 561 562 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 563 NGE_SETBIT(sc, NGE_TX_CFG, 564 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 565 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 566 } else { 567 NGE_CLRBIT(sc, NGE_TX_CFG, 568 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 569 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 570 } 571 572 switch (IFM_SUBTYPE(sc->nge_mii.mii_media_active)) { 573 case IFM_1000_TX: /* Gigabit using GMII interface */ 574 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 575 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_TBI_EN); 576 break; 577 578 case IFM_1000_SX: /* Gigabit using TBI interface */ 579 case IFM_1000_CX: 580 case IFM_1000_LX: 581 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 582 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_TBI_EN); 583 break; 584 585 default: /* Default to MII interface */ 586 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000| 587 NGE_CFG_TBI_EN); 588 break; 589 } 590 591 } 592 593 u_int32_t nge_crc(sc, addr) 594 struct nge_softc *sc; 595 caddr_t addr; 596 { 597 u_int32_t crc, carry; 598 int i, j; 599 u_int8_t c; 600 601 /* Compute CRC for the address value. */ 602 crc = 0xFFFFFFFF; /* initial value */ 603 604 for (i = 0; i < 6; i++) { 605 c = *(addr + i); 606 for (j = 0; j < 8; j++) { 607 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 608 crc <<= 1; 609 c >>= 1; 610 if (carry) 611 crc = (crc ^ 0x04c11db6) | carry; 612 } 613 } 614 615 /* 616 * return the filter bit position 617 */ 618 619 return((crc >> 21) & 0x00000FFF); 620 } 621 622 void nge_setmulti(sc) 623 struct nge_softc *sc; 624 { 625 struct arpcom *ac = &sc->arpcom; 626 struct ifnet *ifp = &ac->ac_if; 627 struct ether_multi *enm; 628 struct ether_multistep step; 629 u_int32_t h = 0, i, filtsave; 630 int bit, index; 631 632 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 633 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 634 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 635 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 636 return; 637 } 638 639 /* 640 * We have to explicitly enable the multicast hash table 641 * on the NatSemi chip if we want to use it, which we do. 642 * We also have to tell it that we don't want to use the 643 * hash table for matching unicast addresses. 644 */ 645 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 646 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 647 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 648 649 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 650 651 /* first, zot all the existing hash bits */ 652 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 653 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 654 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 655 } 656 657 /* 658 * From the 11 bits returned by the crc routine, the top 7 659 * bits represent the 16-bit word in the mcast hash table 660 * that needs to be updated, and the lower 4 bits represent 661 * which bit within that byte needs to be set. 662 */ 663 ETHER_FIRST_MULTI(step, ac, enm); 664 while (enm != NULL) { 665 h = nge_crc(sc, LLADDR((struct sockaddr_dl *)enm->enm_addrlo)); 666 index = (h >> 4) & 0x7F; 667 bit = h & 0xF; 668 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 669 NGE_FILTADDR_MCAST_LO + (index * 2)); 670 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 671 ETHER_NEXT_MULTI(step, enm); 672 } 673 674 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 675 } 676 677 void nge_reset(sc) 678 struct nge_softc *sc; 679 { 680 register int i; 681 682 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 683 684 for (i = 0; i < NGE_TIMEOUT; i++) { 685 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 686 break; 687 } 688 689 if (i == NGE_TIMEOUT) 690 printf("%s: reset never completed\n", sc->sc_dv.dv_xname); 691 692 /* Wait a little while for the chip to get its brains in order. */ 693 DELAY(1000); 694 695 /* 696 * If this is a NetSemi chip, make sure to clear 697 * PME mode. 698 */ 699 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 700 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 701 } 702 703 /* 704 * Probe for an NatSemi chip. Check the PCI vendor and device 705 * IDs against our list and return a device name if we find a match. 706 */ 707 int nge_probe(parent, match, aux) 708 struct device *parent; 709 void *match; 710 void *aux; 711 { 712 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 713 714 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 715 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_DP83820) 716 return (1); 717 718 return (0); 719 } 720 721 struct nge_softc *my_nge_softc; 722 723 /* 724 * Attach the interface. Allocate softc structures, do ifmedia 725 * setup and ethernet/BPF attach. 726 */ 727 void nge_attach(parent, self, aux) 728 struct device *parent, *self; 729 void *aux; 730 { 731 struct nge_softc *sc = (struct nge_softc *)self; 732 struct pci_attach_args *pa = aux; 733 pci_chipset_tag_t pc = pa->pa_pc; 734 pci_intr_handle_t ih; 735 const char *intrstr = NULL; 736 bus_addr_t iobase; 737 bus_size_t iosize; 738 bus_dma_segment_t seg; 739 bus_dmamap_t dmamap; 740 int s, rseg; 741 u_char eaddr[ETHER_ADDR_LEN]; 742 u_int32_t command; 743 struct ifnet *ifp; 744 int error = 0; 745 caddr_t kva; 746 747 s = splimp(); 748 my_nge_softc = sc; 749 750 /* 751 * Handle power management nonsense. 752 */ 753 DPRINTFN(5, ("Preparing for conf read\n")); 754 command = pci_conf_read(pc, pa->pa_tag, NGE_PCI_CAPID) & 0x000000FF; 755 if (command == 0x01) { 756 command = pci_conf_read(pc, pa->pa_tag, NGE_PCI_PWRMGMTCTRL); 757 if (command & NGE_PSTATE_MASK) { 758 u_int32_t iobase, membase, irq; 759 760 /* Save important PCI config data. */ 761 iobase = pci_conf_read(pc, pa->pa_tag, NGE_PCI_LOIO); 762 membase = pci_conf_read(pc, pa->pa_tag, NGE_PCI_LOMEM); 763 irq = pci_conf_read(pc, pa->pa_tag, NGE_PCI_INTLINE); 764 765 /* Reset the power state. */ 766 printf("%s: chip is in D%d power mode " 767 "-- setting to D0\n", sc->sc_dv.dv_xname, 768 command & NGE_PSTATE_MASK); 769 command &= 0xFFFFFFFC; 770 pci_conf_write(pc, pa->pa_tag, 771 NGE_PCI_PWRMGMTCTRL, command); 772 773 /* Restore PCI config data. */ 774 pci_conf_write(pc, pa->pa_tag, NGE_PCI_LOIO, iobase); 775 pci_conf_write(pc, pa->pa_tag, NGE_PCI_LOMEM, membase); 776 pci_conf_write(pc, pa->pa_tag, NGE_PCI_INTLINE, irq); 777 } 778 } 779 780 /* 781 * Map control/status registers. 782 */ 783 DPRINTFN(5, ("Map control/status regs\n")); 784 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 785 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 786 PCI_COMMAND_MASTER_ENABLE; 787 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 788 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 789 790 #ifdef NGE_USEIOSPACE 791 if (!(command & PCI_COMMAND_IO_ENABLE)) { 792 printf("%s: failed to enable I/O ports!\n", 793 sc->sc_dv.dv_xname); 794 error = ENXIO;; 795 goto fail; 796 } 797 /* 798 * Map control/status registers. 799 */ 800 DPRINTFN(5, ("pci_io_find\n")); 801 if (pci_io_find(pc, pa->pa_tag, NGE_PCI_LOIO, &iobase, &iosize)) { 802 printf(": can't find i/o space\n"); 803 goto fail; 804 } 805 DPRINTFN(5, ("bus_space_map\n")); 806 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->nge_bhandle)) { 807 printf(": can't map i/o space\n"); 808 goto fail; 809 } 810 sc->nge_btag = pa->pa_iot; 811 #else 812 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 813 printf("%s: failed to enable memory mapping!\n", 814 sc->sc_dv.dv_xname); 815 error = ENXIO; 816 goto fail; 817 } 818 DPRINTFN(5, ("pci_mem_find\n")); 819 if (pci_mem_find(pc, pa->pa_tag, NGE_PCI_LOMEM, &iobase, 820 &iosize, NULL)) { 821 printf(": can't find mem space\n"); 822 goto fail; 823 } 824 DPRINTFN(5, ("bus_space_map\n")); 825 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->nge_bhandle)) { 826 printf(": can't map mem space\n"); 827 goto fail; 828 } 829 830 sc->nge_btag = pa->pa_memt; 831 #endif 832 833 DPRINTFN(5, ("pci_intr_map\n")); 834 if (pci_intr_map(pa, &ih)) { 835 printf(": couldn't map interrupt\n"); 836 goto fail; 837 } 838 839 DPRINTFN(5, ("pci_intr_string\n")); 840 intrstr = pci_intr_string(pc, ih); 841 DPRINTFN(5, ("pci_intr_establish\n")); 842 sc->nge_intrhand = pci_intr_establish(pc, ih, IPL_NET, nge_intr, sc, 843 sc->sc_dv.dv_xname); 844 if (sc->nge_intrhand == NULL) { 845 printf(": couldn't establish interrupt"); 846 if (intrstr != NULL) 847 printf(" at %s", intrstr); 848 printf("\n"); 849 goto fail; 850 } 851 printf(": %s", intrstr); 852 853 /* Reset the adapter. */ 854 DPRINTFN(5, ("nge_reset\n")); 855 nge_reset(sc); 856 857 /* 858 * Get station address from the EEPROM. 859 */ 860 DPRINTFN(5, ("nge_read_eeprom\n")); 861 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 862 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 863 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 864 865 /* 866 * A NatSemi chip was detected. Inform the world. 867 */ 868 printf(": Ethernet address: %s\n", ether_sprintf(eaddr)); 869 870 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 871 872 sc->sc_dmatag = pa->pa_dmat; 873 DPRINTFN(5, ("bus_dmamem_alloc\n")); 874 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct nge_list_data), 875 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 876 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 877 goto fail; 878 } 879 DPRINTFN(5, ("bus_dmamem_map\n")); 880 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 881 sizeof(struct nge_list_data), &kva, 882 BUS_DMA_NOWAIT)) { 883 printf("%s: can't map dma buffers (%d bytes)\n", 884 sc->sc_dv.dv_xname, sizeof(struct nge_list_data)); 885 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 886 goto fail; 887 } 888 DPRINTFN(5, ("bus_dmamem_create\n")); 889 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct nge_list_data), 1, 890 sizeof(struct nge_list_data), 0, 891 BUS_DMA_NOWAIT, &dmamap)) { 892 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 893 bus_dmamem_unmap(sc->sc_dmatag, kva, 894 sizeof(struct nge_list_data)); 895 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 896 goto fail; 897 } 898 DPRINTFN(5, ("bus_dmamem_load\n")); 899 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, 900 sizeof(struct nge_list_data), NULL, 901 BUS_DMA_NOWAIT)) { 902 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 903 bus_dmamem_unmap(sc->sc_dmatag, kva, 904 sizeof(struct nge_list_data)); 905 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 906 goto fail; 907 } 908 909 DPRINTFN(5, ("bzero\n")); 910 sc->nge_ldata = (struct nge_list_data *)kva; 911 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 912 913 /* Try to allocate memory for jumbo buffers. */ 914 DPRINTFN(5, ("nge_alloc_jumbo_mem\n")); 915 if (nge_alloc_jumbo_mem(sc)) { 916 printf("%s: jumbo buffer allocation failed\n", 917 sc->sc_dv.dv_xname); 918 goto fail; 919 } 920 921 ifp = &sc->arpcom.ac_if; 922 ifp->if_softc = sc; 923 ifp->if_mtu = ETHERMTU; 924 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 925 ifp->if_ioctl = nge_ioctl; 926 ifp->if_output = ether_output; 927 ifp->if_start = nge_start; 928 ifp->if_watchdog = nge_watchdog; 929 ifp->if_baudrate = 1000000000; 930 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 931 ifp->if_capabilities = 932 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 933 #if NVLAN > 0 934 ifp->if_capabilities |= IFCAP_VLAN_MTU; 935 #endif 936 DPRINTFN(5, ("bcopy\n")); 937 bcopy(sc->sc_dv.dv_xname, ifp->if_xname, IFNAMSIZ); 938 939 /* 940 * Do MII setup. 941 */ 942 DPRINTFN(5, ("mii setup\n")); 943 sc->nge_mii.mii_ifp = ifp; 944 sc->nge_mii.mii_readreg = nge_miibus_readreg; 945 sc->nge_mii.mii_writereg = nge_miibus_writereg; 946 sc->nge_mii.mii_statchg = nge_miibus_statchg; 947 ifmedia_init(&sc->nge_mii.mii_media, 0, nge_ifmedia_upd, 948 nge_ifmedia_sts); 949 mii_attach(&sc->sc_dv, &sc->nge_mii, 0xffffffff, MII_PHY_ANY, 950 MII_OFFSET_ANY, 0); 951 952 if (LIST_FIRST(&sc->nge_mii.mii_phys) == NULL) { 953 printf("%s: no PHY found!\n", sc->sc_dv.dv_xname); 954 ifmedia_add(&sc->nge_mii.mii_media, IFM_ETHER|IFM_MANUAL, 955 0, NULL); 956 ifmedia_set(&sc->nge_mii.mii_media, IFM_ETHER|IFM_MANUAL); 957 } 958 else 959 ifmedia_set(&sc->nge_mii.mii_media, IFM_ETHER|IFM_AUTO); 960 961 /* 962 * Call MI attach routine. 963 */ 964 DPRINTFN(5, ("if_attach\n")); 965 if_attach(ifp); 966 DPRINTFN(5, ("ether_ifattach\n")); 967 ether_ifattach(ifp); 968 DPRINTFN(5, ("timeout_set\n")); 969 timeout_set(&sc->nge_timeout, nge_tick, sc); 970 timeout_add(&sc->nge_timeout, hz); 971 972 fail: 973 splx(s); 974 } 975 976 /* 977 * Initialize the transmit descriptors. 978 */ 979 int nge_list_tx_init(sc) 980 struct nge_softc *sc; 981 { 982 struct nge_list_data *ld; 983 struct nge_ring_data *cd; 984 int i; 985 986 cd = &sc->nge_cdata; 987 ld = sc->nge_ldata; 988 989 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 990 if (i == (NGE_TX_LIST_CNT - 1)) { 991 ld->nge_tx_list[i].nge_nextdesc = 992 &ld->nge_tx_list[0]; 993 ld->nge_tx_list[i].nge_next = 994 vtophys(&ld->nge_tx_list[0]); 995 } else { 996 ld->nge_tx_list[i].nge_nextdesc = 997 &ld->nge_tx_list[i + 1]; 998 ld->nge_tx_list[i].nge_next = 999 vtophys(&ld->nge_tx_list[i + 1]); 1000 } 1001 ld->nge_tx_list[i].nge_mbuf = NULL; 1002 ld->nge_tx_list[i].nge_ptr = 0; 1003 ld->nge_tx_list[i].nge_ctl = 0; 1004 } 1005 1006 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1007 1008 return(0); 1009 } 1010 1011 1012 /* 1013 * Initialize the RX descriptors and allocate mbufs for them. Note that 1014 * we arrange the descriptors in a closed ring, so that the last descriptor 1015 * points back to the first. 1016 */ 1017 int nge_list_rx_init(sc) 1018 struct nge_softc *sc; 1019 { 1020 struct nge_list_data *ld; 1021 struct nge_ring_data *cd; 1022 int i; 1023 1024 ld = sc->nge_ldata; 1025 cd = &sc->nge_cdata; 1026 1027 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1028 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1029 return(ENOBUFS); 1030 if (i == (NGE_RX_LIST_CNT - 1)) { 1031 ld->nge_rx_list[i].nge_nextdesc = 1032 &ld->nge_rx_list[0]; 1033 ld->nge_rx_list[i].nge_next = 1034 vtophys(&ld->nge_rx_list[0]); 1035 } else { 1036 ld->nge_rx_list[i].nge_nextdesc = 1037 &ld->nge_rx_list[i + 1]; 1038 ld->nge_rx_list[i].nge_next = 1039 vtophys(&ld->nge_rx_list[i + 1]); 1040 } 1041 } 1042 1043 cd->nge_rx_prod = 0; 1044 1045 return(0); 1046 } 1047 1048 /* 1049 * Initialize an RX descriptor and attach an MBUF cluster. 1050 */ 1051 int nge_newbuf(sc, c, m) 1052 struct nge_softc *sc; 1053 struct nge_desc *c; 1054 struct mbuf *m; 1055 { 1056 struct mbuf *m_new = NULL; 1057 caddr_t *buf = NULL; 1058 1059 if (m == NULL) { 1060 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1061 if (m_new == NULL) { 1062 printf("%s: no memory for rx list " 1063 "-- packet dropped!\n", sc->sc_dv.dv_xname); 1064 return(ENOBUFS); 1065 } 1066 1067 /* Allocate the jumbo buffer */ 1068 buf = nge_jalloc(sc); 1069 if (buf == NULL) { 1070 #ifdef NGE_VERBOSE 1071 printf("%s: jumbo allocation failed " 1072 "-- packet dropped!\n", sc->sc_dv.dv_xname); 1073 #endif 1074 m_freem(m_new); 1075 return(ENOBUFS); 1076 } 1077 /* Attach the buffer to the mbuf */ 1078 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 1079 m_new->m_flags |= M_EXT; 1080 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 1081 m_new->m_len = NGE_MCLBYTES; 1082 m_new->m_ext.ext_free = nge_jfree; 1083 m_new->m_ext.ext_arg = sc; 1084 MCLINITREFERENCE(m_new); 1085 } else { 1086 m_new = m; 1087 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES; 1088 m_new->m_data = m_new->m_ext.ext_buf; 1089 } 1090 1091 m_adj(m_new, sizeof(u_int64_t)); 1092 1093 c->nge_mbuf = m_new; 1094 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1095 DPRINTFN(7,("c->nge_ptr = 0x%08X\n", c->nge_ptr)); 1096 c->nge_ctl = m_new->m_len; 1097 c->nge_extsts = 0; 1098 1099 return(0); 1100 } 1101 1102 int nge_alloc_jumbo_mem(sc) 1103 struct nge_softc *sc; 1104 { 1105 caddr_t ptr, kva; 1106 bus_dma_segment_t seg; 1107 bus_dmamap_t dmamap; 1108 int i, rseg; 1109 struct nge_jpool_entry *entry; 1110 1111 if (bus_dmamem_alloc(sc->sc_dmatag, NGE_JMEM, PAGE_SIZE, 0, 1112 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1113 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 1114 return (ENOBUFS); 1115 } 1116 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, NGE_JMEM, &kva, 1117 BUS_DMA_NOWAIT)) { 1118 printf("%s: can't map dma buffers (%d bytes)\n", 1119 sc->sc_dv.dv_xname, NGE_JMEM); 1120 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1121 return (ENOBUFS); 1122 } 1123 if (bus_dmamap_create(sc->sc_dmatag, NGE_JMEM, 1, 1124 NGE_JMEM, 0, BUS_DMA_NOWAIT, &dmamap)) { 1125 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 1126 bus_dmamem_unmap(sc->sc_dmatag, kva, NGE_JMEM); 1127 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1128 return (ENOBUFS); 1129 } 1130 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, NGE_JMEM, 1131 NULL, BUS_DMA_NOWAIT)) { 1132 printf("%s: can't load dma map\n", sc->sc_dv.dv_xname); 1133 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1134 bus_dmamem_unmap(sc->sc_dmatag, kva, NGE_JMEM); 1135 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1136 return (ENOBUFS); 1137 } 1138 sc->nge_cdata.nge_jumbo_buf = (caddr_t)kva; 1139 DPRINTFN(1,("nge_jumbo_buf = 0x%08X\n", sc->nge_cdata.nge_jumbo_buf)); 1140 DPRINTFN(1,("NGE_MCLBYTES = 0x%08X\n", NGE_MCLBYTES)); 1141 1142 LIST_INIT(&sc->nge_jfree_listhead); 1143 LIST_INIT(&sc->nge_jinuse_listhead); 1144 1145 /* 1146 * Now divide it up into 9K pieces and save the addresses 1147 * in an array. Note that we play an evil trick here by using 1148 * the first few bytes in the buffer to hold the the address 1149 * of the softc structure for this interface. This is because 1150 * nge_jfree() needs it, but it is called by the mbuf management 1151 * code which will not pass it to us explicitly. 1152 */ 1153 ptr = sc->nge_cdata.nge_jumbo_buf; 1154 for (i = 0; i < NGE_JSLOTS; i++) { 1155 sc->nge_cdata.nge_jslots[i].nge_buf = ptr; 1156 sc->nge_cdata.nge_jslots[i].nge_inuse = 0; 1157 ptr += NGE_MCLBYTES; 1158 entry = malloc(sizeof(struct nge_jpool_entry), 1159 M_DEVBUF, M_NOWAIT); 1160 if (entry == NULL) { 1161 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1162 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1163 bus_dmamem_unmap(sc->sc_dmatag, kva, NGE_JMEM); 1164 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1165 sc->nge_cdata.nge_jumbo_buf = NULL; 1166 printf("%s: no memory for jumbo buffer queue!\n", 1167 sc->sc_dv.dv_xname); 1168 return(ENOBUFS); 1169 } 1170 entry->slot = i; 1171 LIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, 1172 jpool_entries); 1173 } 1174 1175 return(0); 1176 } 1177 1178 /* 1179 * Allocate a jumbo buffer. 1180 */ 1181 void *nge_jalloc(sc) 1182 struct nge_softc *sc; 1183 { 1184 struct nge_jpool_entry *entry; 1185 1186 entry = LIST_FIRST(&sc->nge_jfree_listhead); 1187 1188 if (entry == NULL) { 1189 #ifdef NGE_VERBOSE 1190 printf("%s: no free jumbo buffers\n", sc->sc_dv.dv_xname); 1191 #endif 1192 return(NULL); 1193 } 1194 1195 LIST_REMOVE(entry, jpool_entries); 1196 LIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1197 sc->nge_cdata.nge_jslots[entry->slot].nge_inuse = 1; 1198 return(sc->nge_cdata.nge_jslots[entry->slot].nge_buf); 1199 } 1200 1201 /* 1202 * Release a jumbo buffer. 1203 */ 1204 void nge_jfree(buf, size, arg) 1205 caddr_t buf; 1206 u_int size; 1207 void *arg; 1208 { 1209 struct nge_softc *sc; 1210 int i; 1211 struct nge_jpool_entry *entry; 1212 1213 /* Extract the softc struct pointer. */ 1214 sc = (struct nge_softc *)arg; 1215 1216 if (sc == NULL) 1217 panic("nge_jfree: can't find softc pointer!"); 1218 1219 /* calculate the slot this buffer belongs to */ 1220 1221 i = ((vaddr_t)buf - (vaddr_t)sc->nge_cdata.nge_jumbo_buf) 1222 / NGE_MCLBYTES; 1223 1224 if ((i < 0) || (i >= NGE_JSLOTS)) 1225 panic("nge_jfree: asked to free buffer that we don't manage!"); 1226 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0) 1227 panic("nge_jfree: buffer already free!"); 1228 else { 1229 sc->nge_cdata.nge_jslots[i].nge_inuse--; 1230 if(sc->nge_cdata.nge_jslots[i].nge_inuse == 0) { 1231 entry = LIST_FIRST(&sc->nge_jinuse_listhead); 1232 if (entry == NULL) 1233 panic("nge_jfree: buffer not in use!"); 1234 entry->slot = i; 1235 LIST_REMOVE(entry, jpool_entries); 1236 LIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1237 entry, jpool_entries); 1238 } 1239 } 1240 } 1241 1242 /* 1243 * A frame has been uploaded: pass the resulting mbuf chain up to 1244 * the higher level protocols. 1245 */ 1246 void nge_rxeof(sc) 1247 struct nge_softc *sc; 1248 { 1249 struct mbuf *m; 1250 struct ifnet *ifp; 1251 struct nge_desc *cur_rx; 1252 int i, total_len = 0; 1253 u_int32_t rxstat; 1254 1255 ifp = &sc->arpcom.ac_if; 1256 i = sc->nge_cdata.nge_rx_prod; 1257 1258 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1259 struct mbuf *m0 = NULL; 1260 u_int32_t extsts; 1261 1262 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1263 rxstat = cur_rx->nge_rxstat; 1264 extsts = cur_rx->nge_extsts; 1265 m = cur_rx->nge_mbuf; 1266 cur_rx->nge_mbuf = NULL; 1267 total_len = NGE_RXBYTES(cur_rx); 1268 NGE_INC(i, NGE_RX_LIST_CNT); 1269 1270 /* 1271 * If an error occurs, update stats, clear the 1272 * status word and leave the mbuf cluster in place: 1273 * it should simply get re-used next time this descriptor 1274 * comes up in the ring. 1275 */ 1276 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1277 ifp->if_ierrors++; 1278 nge_newbuf(sc, cur_rx, m); 1279 continue; 1280 } 1281 1282 1283 /* 1284 * Ok. NatSemi really screwed up here. This is the 1285 * only gigE chip I know of with alignment constraints 1286 * on receive buffers. RX buffers must be 64-bit aligned. 1287 */ 1288 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1289 total_len + ETHER_ALIGN, 0, ifp, NULL); 1290 nge_newbuf(sc, cur_rx, m); 1291 if (m0 == NULL) { 1292 printf("%s: no receive buffers " 1293 "available -- packet dropped!\n", 1294 sc->sc_dv.dv_xname); 1295 ifp->if_ierrors++; 1296 continue; 1297 } 1298 m_adj(m0, ETHER_ALIGN); 1299 m = m0; 1300 1301 ifp->if_ipackets++; 1302 1303 #if NBPFILTER > 0 1304 /* 1305 * Handle BPF listeners. Let the BPF user see the packet. 1306 */ 1307 if (ifp->if_bpf) 1308 bpf_mtap(ifp->if_bpf, m); 1309 #endif 1310 1311 /* Do IP checksum checking. */ 1312 if (extsts & NGE_RXEXTSTS_IPPKT) { 1313 if (extsts & NGE_RXEXTSTS_IPCSUMERR) 1314 m->m_pkthdr.csum |= M_IPV4_CSUM_IN_BAD; 1315 else 1316 m->m_pkthdr.csum |= M_IPV4_CSUM_IN_OK; 1317 } 1318 if (extsts & NGE_RXEXTSTS_TCPPKT) { 1319 if (extsts & NGE_RXEXTSTS_TCPCSUMERR) 1320 m->m_pkthdr.csum |= M_TCP_CSUM_IN_BAD; 1321 else 1322 m->m_pkthdr.csum |= M_TCP_CSUM_IN_OK; 1323 } 1324 if (extsts & NGE_RXEXTSTS_UDPPKT) { 1325 if (extsts & NGE_RXEXTSTS_UDPCSUMERR) 1326 m->m_pkthdr.csum |= M_UDP_CSUM_IN_BAD; 1327 else 1328 m->m_pkthdr.csum |= M_UDP_CSUM_IN_OK; 1329 } 1330 1331 #if NVLAN > 0 1332 /* 1333 * If we received a packet with a vlan tag, pass it 1334 * to vlan_input() instead of ether_input(). 1335 */ 1336 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1337 if (vlan_input_tag(m, extsts & NGE_RXEXTSTS_VTCI) < 0) 1338 ifp->if_data.ifi_noproto++; 1339 continue; 1340 } 1341 #endif 1342 1343 ether_input_mbuf(ifp, m); 1344 } 1345 1346 sc->nge_cdata.nge_rx_prod = i; 1347 } 1348 1349 void nge_rxeoc(sc) 1350 struct nge_softc *sc; 1351 { 1352 struct ifnet *ifp; 1353 1354 ifp = &sc->arpcom.ac_if; 1355 nge_rxeof(sc); 1356 ifp->if_flags &= ~IFF_RUNNING; 1357 nge_init(sc); 1358 } 1359 1360 /* 1361 * A frame was downloaded to the chip. It's safe for us to clean up 1362 * the list buffers. 1363 */ 1364 1365 void nge_txeof(sc) 1366 struct nge_softc *sc; 1367 { 1368 struct nge_desc *cur_tx = NULL; 1369 struct ifnet *ifp; 1370 u_int32_t idx; 1371 1372 ifp = &sc->arpcom.ac_if; 1373 1374 /* Clear the timeout timer. */ 1375 ifp->if_timer = 0; 1376 1377 /* 1378 * Go through our tx list and free mbufs for those 1379 * frames that have been transmitted. 1380 */ 1381 idx = sc->nge_cdata.nge_tx_cons; 1382 while (idx != sc->nge_cdata.nge_tx_prod) { 1383 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1384 1385 if (NGE_OWNDESC(cur_tx)) 1386 break; 1387 1388 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1389 sc->nge_cdata.nge_tx_cnt--; 1390 NGE_INC(idx, NGE_TX_LIST_CNT); 1391 continue; 1392 } 1393 1394 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1395 ifp->if_oerrors++; 1396 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1397 ifp->if_collisions++; 1398 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1399 ifp->if_collisions++; 1400 } 1401 1402 ifp->if_collisions += 1403 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1404 1405 ifp->if_opackets++; 1406 if (cur_tx->nge_mbuf != NULL) { 1407 m_freem(cur_tx->nge_mbuf); 1408 cur_tx->nge_mbuf = NULL; 1409 } 1410 1411 sc->nge_cdata.nge_tx_cnt--; 1412 NGE_INC(idx, NGE_TX_LIST_CNT); 1413 ifp->if_timer = 0; 1414 } 1415 1416 sc->nge_cdata.nge_tx_cons = idx; 1417 1418 if (cur_tx != NULL) 1419 ifp->if_flags &= ~IFF_OACTIVE; 1420 } 1421 1422 void nge_tick(xsc) 1423 void *xsc; 1424 { 1425 struct nge_softc *sc = xsc; 1426 struct mii_data *mii = &sc->nge_mii; 1427 struct ifnet *ifp = &sc->arpcom.ac_if; 1428 int s; 1429 1430 s = splimp(); 1431 1432 mii_tick(mii); 1433 1434 if (!sc->nge_link) { 1435 mii_pollstat(mii); 1436 if (mii->mii_media_status & IFM_ACTIVE && 1437 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1438 sc->nge_link++; 1439 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) 1440 DPRINTFN("%s: gigabit link up\n", 1441 sc->sc_dv.dv_xname); 1442 if (ifp->if_snd.ifq_head != NULL) 1443 nge_start(ifp); 1444 } else 1445 timeout_add(&sc->nge_timeout, hz); 1446 } 1447 1448 splx(s); 1449 } 1450 1451 int nge_intr(arg) 1452 void *arg; 1453 { 1454 struct nge_softc *sc; 1455 struct ifnet *ifp; 1456 u_int32_t status; 1457 int claimed = 0; 1458 1459 sc = arg; 1460 ifp = &sc->arpcom.ac_if; 1461 1462 /* Supress unwanted interrupts */ 1463 if (!(ifp->if_flags & IFF_UP)) { 1464 nge_stop(sc); 1465 return (0); 1466 } 1467 1468 /* Disable interrupts. */ 1469 CSR_WRITE_4(sc, NGE_IER, 0); 1470 1471 for (;;) { 1472 /* Reading the ISR register clears all interrupts. */ 1473 status = CSR_READ_4(sc, NGE_ISR); 1474 1475 if ((status & NGE_INTRS) == 0) 1476 break; 1477 1478 claimed = 1; 1479 1480 if ((status & NGE_ISR_TX_DESC_OK) || 1481 (status & NGE_ISR_TX_ERR) || 1482 (status & NGE_ISR_TX_OK) || 1483 (status & NGE_ISR_TX_IDLE)) 1484 nge_txeof(sc); 1485 1486 if ((status & NGE_ISR_RX_DESC_OK) || 1487 (status & NGE_ISR_RX_OK)) 1488 nge_rxeof(sc); 1489 1490 if ((status & NGE_ISR_RX_ERR) || 1491 (status & NGE_ISR_RX_OFLOW)) { 1492 nge_rxeoc(sc); 1493 } 1494 1495 if (status & NGE_ISR_SYSERR) { 1496 nge_reset(sc); 1497 ifp->if_flags &= ~IFF_RUNNING; 1498 nge_init(sc); 1499 } 1500 1501 if (status & NGE_ISR_PHY_INTR) { 1502 sc->nge_link = 0; 1503 nge_tick(sc); 1504 } 1505 } 1506 1507 /* Re-enable interrupts. */ 1508 CSR_WRITE_4(sc, NGE_IER, 1); 1509 1510 if (ifp->if_snd.ifq_head != NULL) 1511 nge_start(ifp); 1512 1513 return claimed; 1514 } 1515 1516 /* 1517 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1518 * pointers to the fragment pointers. 1519 */ 1520 int nge_encap(sc, m_head, txidx) 1521 struct nge_softc *sc; 1522 struct mbuf *m_head; 1523 u_int32_t *txidx; 1524 { 1525 struct nge_desc *f = NULL; 1526 struct mbuf *m; 1527 int frag, cur, cnt = 0; 1528 #if NVLAN > 0 1529 struct ifvlan *ifv = NULL; 1530 1531 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1532 m_head->m_pkthdr.rcvif != NULL) 1533 ifv = m_head->m_pkthdr.rcvif->if_softc; 1534 #endif 1535 1536 /* 1537 * Start packing the mbufs in this chain into 1538 * the fragment pointers. Stop when we run out 1539 * of fragments or hit the end of the mbuf chain. 1540 */ 1541 m = m_head; 1542 cur = frag = *txidx; 1543 1544 for (m = m_head; m != NULL; m = m->m_next) { 1545 if (m->m_len != 0) { 1546 if ((NGE_TX_LIST_CNT - 1547 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1548 return(ENOBUFS); 1549 f = &sc->nge_ldata->nge_tx_list[frag]; 1550 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1551 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1552 DPRINTFN(7,("f->nge_ptr = 0x%08X\n", f->nge_ptr)); 1553 if (cnt != 0) 1554 f->nge_ctl |= NGE_CMDSTS_OWN; 1555 cur = frag; 1556 NGE_INC(frag, NGE_TX_LIST_CNT); 1557 cnt++; 1558 } 1559 } 1560 1561 if (m != NULL) 1562 return(ENOBUFS); 1563 1564 /* 1565 * Card handles checksumming on a packet by packet 1566 * basis. 1567 */ 1568 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1569 if (m_head->m_pkthdr.csum) { 1570 if (m_head->m_pkthdr.csum & M_IPV4_CSUM_OUT) 1571 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1572 NGE_TXEXTSTS_IPCSUM; 1573 if (m_head->m_pkthdr.csum & M_TCPV4_CSUM_OUT) 1574 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1575 NGE_TXEXTSTS_TCPCSUM; 1576 if (m_head->m_pkthdr.csum & M_UDPV4_CSUM_OUT) 1577 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1578 NGE_TXEXTSTS_UDPCSUM; 1579 } 1580 1581 #if NVLAN > 0 1582 if (ifv != NULL) { 1583 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1584 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag); 1585 } 1586 #endif 1587 1588 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1589 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1590 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1591 sc->nge_cdata.nge_tx_cnt += cnt; 1592 *txidx = frag; 1593 1594 return(0); 1595 } 1596 1597 /* 1598 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1599 * to the mbuf data regions directly in the transmit lists. We also save a 1600 * copy of the pointers since the transmit list fragment pointers are 1601 * physical addresses. 1602 */ 1603 1604 void nge_start(ifp) 1605 struct ifnet *ifp; 1606 { 1607 struct nge_softc *sc; 1608 struct mbuf *m_head = NULL; 1609 u_int32_t idx; 1610 1611 sc = ifp->if_softc; 1612 1613 if (!sc->nge_link) 1614 return; 1615 1616 idx = sc->nge_cdata.nge_tx_prod; 1617 1618 if (ifp->if_flags & IFF_OACTIVE) 1619 return; 1620 1621 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1622 IF_DEQUEUE(&ifp->if_snd, m_head); 1623 if (m_head == NULL) 1624 break; 1625 1626 if (nge_encap(sc, m_head, &idx)) { 1627 IF_PREPEND(&ifp->if_snd, m_head); 1628 ifp->if_flags |= IFF_OACTIVE; 1629 break; 1630 } 1631 1632 #if NBPFILTER > 0 1633 /* 1634 * If there's a BPF listener, bounce a copy of this frame 1635 * to him. 1636 */ 1637 if (ifp->if_bpf) 1638 bpf_mtap(ifp->if_bpf, m_head); 1639 #endif 1640 } 1641 1642 /* Transmit */ 1643 sc->nge_cdata.nge_tx_prod = idx; 1644 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1645 1646 /* 1647 * Set a timeout in case the chip goes out to lunch. 1648 */ 1649 ifp->if_timer = 5; 1650 } 1651 1652 int nge_loop = 0; 1653 1654 void nge_init(xsc) 1655 void *xsc; 1656 { 1657 struct nge_softc *sc = xsc; 1658 struct ifnet *ifp = &sc->arpcom.ac_if; 1659 struct mii_data *mii = &sc->nge_mii; 1660 int s; 1661 1662 if (ifp->if_flags & IFF_RUNNING) 1663 return; 1664 1665 s = splimp(); 1666 1667 /* 1668 * Cancel pending I/O and free all RX/TX buffers. 1669 */ 1670 nge_stop(sc); 1671 nge_reset(sc); 1672 1673 /* Turn the receive filter off */ 1674 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1675 1676 /* Set MAC address */ 1677 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1678 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1679 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1680 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1681 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1682 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1683 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1684 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1685 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1686 1687 /* Init circular RX list. */ 1688 if (nge_list_rx_init(sc) == ENOBUFS) { 1689 printf("%s: initialization failed: no " 1690 "memory for rx buffers\n", sc->sc_dv.dv_xname); 1691 nge_stop(sc); 1692 (void)splx(s); 1693 return; 1694 } 1695 1696 /* 1697 * Init tx descriptors. 1698 */ 1699 nge_list_tx_init(sc); 1700 1701 /* 1702 * For the NatSemi chip, we have to explicitly enable the 1703 * reception of ARP frames, as well as turn on the 'perfect 1704 * match' filter where we store the station address, otherwise 1705 * we won't receive unicasts meant for this host. 1706 */ 1707 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1708 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1709 1710 /* If we want promiscuous mode, set the allframes bit. */ 1711 if (ifp->if_flags & IFF_PROMISC) { 1712 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1713 } else { 1714 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1715 } 1716 1717 /* 1718 * Set the capture broadcast bit to capture broadcast frames. 1719 */ 1720 if (ifp->if_flags & IFF_BROADCAST) { 1721 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1722 } else { 1723 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1724 } 1725 1726 /* 1727 * Load the multicast filter. 1728 */ 1729 nge_setmulti(sc); 1730 1731 /* Turn the receive filter on */ 1732 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1733 1734 /* 1735 * Load the address of the RX and TX lists. 1736 */ 1737 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1738 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1739 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1740 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1741 1742 /* Set RX configuration */ 1743 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1744 1745 /* 1746 * Enable hardware checksum validation for all IPv4 1747 * packets, do not reject packets with bad checksums. 1748 */ 1749 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1750 1751 #if NVLAN > 0 1752 /* 1753 * If VLAN support is enabled, tell the chip to detect 1754 * and strip VLAN tag info from received frames. The tag 1755 * will be provided in the extsts field in the RX descriptors. 1756 */ 1757 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1758 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1759 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1760 #endif 1761 1762 /* Set TX configuration */ 1763 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG | 1764 (nge_loop ? NGE_TXCFG_LOOPBK : 0)); 1765 1766 /* 1767 * Enable TX IPv4 checksumming on a per-packet basis. 1768 */ 1769 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1770 1771 #if NVLAN > 0 1772 /* 1773 * If VLAN support is enabled, tell the chip to insert 1774 * VLAN tags on a per-packet basis as dictated by the 1775 * code in the frame encapsulation routine. 1776 */ 1777 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1778 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1779 #endif 1780 1781 /* Set full/half duplex mode. */ 1782 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1783 NGE_SETBIT(sc, NGE_TX_CFG, 1784 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1785 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1786 } else { 1787 NGE_CLRBIT(sc, NGE_TX_CFG, 1788 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1789 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1790 } 1791 1792 /* 1793 * Enable the delivery of PHY interrupts based on 1794 * link/speed/duplex status changes and enable return 1795 * of extended status information in the DMA descriptors, 1796 * required for checksum offloading. 1797 */ 1798 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD|NGE_CFG_PHYINTR_LNK| 1799 NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1800 1801 DPRINTFN("NGE_CFG: 0x%08X\n", CSR_READ_4(sc, NGE_CFG)); 1802 1803 /* 1804 * Enable interrupts. 1805 */ 1806 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1807 CSR_WRITE_4(sc, NGE_IER, 1); 1808 1809 /* Enable receiver and transmitter. */ 1810 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1811 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1812 1813 nge_ifmedia_upd(ifp); 1814 1815 ifp->if_flags |= IFF_RUNNING; 1816 ifp->if_flags &= ~IFF_OACTIVE; 1817 1818 (void)splx(s); 1819 } 1820 1821 /* 1822 * Set media options. 1823 */ 1824 int nge_ifmedia_upd(ifp) 1825 struct ifnet *ifp; 1826 { 1827 struct nge_softc *sc = ifp->if_softc; 1828 struct mii_data *mii = &sc->nge_mii; 1829 1830 sc->nge_link = 0; 1831 if (mii->mii_instance) { 1832 struct mii_softc *miisc; 1833 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1834 miisc = LIST_NEXT(miisc, mii_list)) 1835 mii_phy_reset(miisc); 1836 } 1837 mii_mediachg(mii); 1838 1839 return(0); 1840 } 1841 1842 /* 1843 * Report current media status. 1844 */ 1845 void nge_ifmedia_sts(ifp, ifmr) 1846 struct ifnet *ifp; 1847 struct ifmediareq *ifmr; 1848 { 1849 struct nge_softc *sc = ifp->if_softc; 1850 struct mii_data *mii = &sc->nge_mii; 1851 1852 mii_pollstat(mii); 1853 ifmr->ifm_active = mii->mii_media_active; 1854 ifmr->ifm_status = mii->mii_media_status; 1855 } 1856 1857 int nge_ioctl(ifp, command, data) 1858 struct ifnet *ifp; 1859 u_long command; 1860 caddr_t data; 1861 { 1862 struct nge_softc *sc = ifp->if_softc; 1863 struct ifreq *ifr = (struct ifreq *) data; 1864 struct ifaddr *ifa = (struct ifaddr *)data; 1865 struct mii_data *mii; 1866 int s, error = 0; 1867 1868 s = splimp(); 1869 1870 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 1871 splx(s); 1872 return (error); 1873 } 1874 1875 switch(command) { 1876 case SIOCSIFMTU: 1877 if (ifr->ifr_mtu > NGE_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 1878 error = EINVAL; 1879 else { 1880 ifp->if_mtu = ifr->ifr_mtu; 1881 /* 1882 * If requested MTU is larger than the 1883 * size of the TX buffer, turn off TX 1884 * checksumming. 1885 */ 1886 if (ifr->ifr_mtu >= 8152) 1887 ifp->if_capabilities &= ~(IFCAP_CSUM_IPv4 | 1888 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4); 1889 else 1890 ifp->if_capabilities = IFCAP_CSUM_IPv4 | 1891 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1892 } 1893 break; 1894 case SIOCSIFADDR: 1895 ifp->if_flags |= IFF_UP; 1896 switch (ifa->ifa_addr->sa_family) { 1897 #ifdef INET 1898 case AF_INET: 1899 nge_init(sc); 1900 arp_ifinit(&sc->arpcom, ifa); 1901 break; 1902 #endif /* INET */ 1903 default: 1904 nge_init(sc); 1905 break; 1906 } 1907 break; 1908 case SIOCSIFFLAGS: 1909 if (ifp->if_flags & IFF_UP) { 1910 if (ifp->if_flags & IFF_RUNNING && 1911 ifp->if_flags & IFF_PROMISC && 1912 !(sc->nge_if_flags & IFF_PROMISC)) { 1913 NGE_SETBIT(sc, NGE_RXFILT_CTL, 1914 NGE_RXFILTCTL_ALLPHYS| 1915 NGE_RXFILTCTL_ALLMULTI); 1916 } else if (ifp->if_flags & IFF_RUNNING && 1917 !(ifp->if_flags & IFF_PROMISC) && 1918 sc->nge_if_flags & IFF_PROMISC) { 1919 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1920 NGE_RXFILTCTL_ALLPHYS); 1921 if (!(ifp->if_flags & IFF_ALLMULTI)) 1922 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1923 NGE_RXFILTCTL_ALLMULTI); 1924 } else { 1925 ifp->if_flags &= ~IFF_RUNNING; 1926 nge_init(sc); 1927 } 1928 } else { 1929 if (ifp->if_flags & IFF_RUNNING) 1930 nge_stop(sc); 1931 } 1932 sc->nge_if_flags = ifp->if_flags; 1933 error = 0; 1934 break; 1935 case SIOCADDMULTI: 1936 case SIOCDELMULTI: 1937 error = (command == SIOCADDMULTI) 1938 ? ether_addmulti(ifr, &sc->arpcom) 1939 : ether_delmulti(ifr, &sc->arpcom); 1940 1941 if (error == ENETRESET) { 1942 if (ifp->if_flags & IFF_RUNNING) 1943 nge_setmulti(sc); 1944 error = 0; 1945 } 1946 break; 1947 case SIOCGIFMEDIA: 1948 case SIOCSIFMEDIA: 1949 mii = &sc->nge_mii; 1950 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1951 break; 1952 default: 1953 error = EINVAL; 1954 break; 1955 } 1956 1957 (void)splx(s); 1958 1959 return(error); 1960 } 1961 1962 void nge_watchdog(ifp) 1963 struct ifnet *ifp; 1964 { 1965 struct nge_softc *sc; 1966 1967 sc = ifp->if_softc; 1968 1969 ifp->if_oerrors++; 1970 printf("%s: watchdog timeout\n", sc->sc_dv.dv_xname); 1971 1972 nge_stop(sc); 1973 nge_reset(sc); 1974 ifp->if_flags &= ~IFF_RUNNING; 1975 nge_init(sc); 1976 1977 if (ifp->if_snd.ifq_head != NULL) 1978 nge_start(ifp); 1979 } 1980 1981 /* 1982 * Stop the adapter and free any mbufs allocated to the 1983 * RX and TX lists. 1984 */ 1985 void nge_stop(sc) 1986 struct nge_softc *sc; 1987 { 1988 register int i; 1989 struct ifnet *ifp; 1990 struct ifmedia_entry *ifm; 1991 struct mii_data *mii = &sc->nge_mii; 1992 int mtmp, itmp; 1993 1994 ifp = &sc->arpcom.ac_if; 1995 ifp->if_timer = 0; 1996 1997 timeout_del(&sc->nge_timeout); 1998 CSR_WRITE_4(sc, NGE_IER, 0); 1999 CSR_WRITE_4(sc, NGE_IMR, 0); 2000 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2001 DELAY(1000); 2002 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2003 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2004 2005 /* 2006 * Isolate/power down the PHY, but leave the media selection 2007 * unchanged so that things will be put back to normal when 2008 * we bring the interface back up. 2009 */ 2010 itmp = ifp->if_flags; 2011 ifp->if_flags |= IFF_UP; 2012 ifm = mii->mii_media.ifm_cur; 2013 mtmp = ifm->ifm_media; 2014 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2015 mii_mediachg(mii); 2016 ifm->ifm_media = mtmp; 2017 ifp->if_flags = itmp; 2018 2019 sc->nge_link = 0; 2020 2021 /* 2022 * Free data in the RX lists. 2023 */ 2024 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2025 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2026 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2027 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2028 } 2029 } 2030 bzero((char *)&sc->nge_ldata->nge_rx_list, 2031 sizeof(sc->nge_ldata->nge_rx_list)); 2032 2033 /* 2034 * Free the TX list buffers. 2035 */ 2036 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2037 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2038 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2039 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2040 } 2041 } 2042 2043 bzero((char *)&sc->nge_ldata->nge_tx_list, 2044 sizeof(sc->nge_ldata->nge_tx_list)); 2045 2046 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2047 } 2048 2049 /* 2050 * Stop all chip I/O so that the kernel's probe routines don't 2051 * get confused by errant DMAs when rebooting. 2052 */ 2053 void nge_shutdown(xsc) 2054 void *xsc; 2055 { 2056 struct nge_softc *sc = (struct nge_softc *)xsc; 2057 2058 nge_reset(sc); 2059 nge_stop(sc); 2060 } 2061 2062 struct cfattach nge_ca = { 2063 sizeof(struct nge_softc), nge_probe, nge_attach 2064 }; 2065 2066 struct cfdriver nge_cd = { 2067 0, "nge", DV_IFNET 2068 }; 2069