1 /* $OpenBSD: if_myxreg.h,v 1.8 2015/02/18 23:58:34 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Reyk Floeter <reyk@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Register definitions for the Myricom Myri-10G Lanai-Z8E Ethernet chipsets. 21 */ 22 23 #ifndef _MYX_REG_H 24 #define _MYX_REG_H 25 26 /* 27 * Common definitions 28 */ 29 30 #define MYXBAR0 PCI_MAPREG_START 31 32 #define MYX_NRXDESC 256 33 #define MYX_NTXDESC_MIN 2 34 #define MYX_IRQCOALDELAY 60 35 #define MYX_IRQDEASSERTWAIT 1 36 37 #define MYXALIGN_CMD 64 38 #define MYXALIGN_DATA PAGE_SIZE 39 #define MYX_BOUNDARY 4096 40 41 #define MYX_ADDRHIGH(_v) (((u_int64_t)_v >> 32) & 0xffffffff) 42 #define MYX_ADDRLOW(_v) ((u_int64_t)_v & 0xffffffff) 43 44 /* 45 * PCI memory/register layout 46 */ 47 48 #define MYX_SRAM 0x00000000 /* SRAM offset */ 49 #define MYX_SRAM_SIZE 0x001dff00 /* SRAM size */ 50 #define MYX_HEADER_POS 0x0000003c /* Header position offset */ 51 #define MYX_HEADER_POS_SIZE 0x00000004 /* Header position size */ 52 #define MYX_FW 0x00100000 /* Firmware offset */ 53 #define MYX_FW_BOOT 0x00100008 /* Firmware boot offset */ 54 #define MYX_STRING_SPECS 0x001dfe00 /* STRING_SPECS offset */ 55 #define MYX_STRING_SPECS_SIZE 0x00000100 /* STRING_SPECS size */ 56 #define MYX_BOOT 0x00fc0000 /* Boot handoff */ 57 #define MYX_RDMA 0x00fc01c0 /* Dummy RDMA */ 58 #define MYX_CMD 0x00f80000 /* Command offset */ 59 60 /* 61 * Firmware definitions 62 */ 63 64 #define MYXFW_ALIGNED "myx-eth_z8e" 65 #define MYXFW_UNALIGNED "myx-ethp_z8e" 66 #define MYXFW_TYPE_ETH 0x45544820 67 #define MYXFW_VER "1.4." /* stored as a string... */ 68 69 #define MYXFW_MIN_LEN (MYX_HEADER_POS + MYX_HEADER_POS_SIZE) 70 71 struct myx_gen_hdr { 72 u_int32_t fw_hdrlength; 73 u_int32_t fw_type; 74 u_int8_t fw_version[128]; 75 u_int32_t fw_mcp_globals; 76 u_int32_t fw_sram_size; 77 u_int32_t fw_specs; 78 u_int32_t fw_specs_len; 79 } __packed; 80 81 /* 82 * Commands, descriptors, and DMA structures 83 */ 84 85 struct myx_cmd { 86 u_int32_t mc_cmd; 87 u_int32_t mc_data0; 88 u_int32_t mc_data1; 89 u_int32_t mc_data2; 90 u_int32_t mc_addr_high; 91 u_int32_t mc_addr_low; 92 u_int8_t mc_pad[40]; /* pad up to 64 bytes */ 93 } __packed; 94 95 struct myx_response { 96 u_int32_t mr_data; 97 u_int32_t mr_result; 98 } __packed; 99 100 struct myx_bootcmd { 101 u_int32_t bc_addr_high; 102 u_int32_t bc_addr_low; 103 u_int32_t bc_result; 104 u_int32_t bc_offset; 105 u_int32_t bc_length; 106 u_int32_t bc_copyto; 107 u_int32_t bc_jumpto; 108 u_int8_t bc_pad[36]; /* pad up to 64 bytes */ 109 } __packed; 110 111 struct myx_rdmacmd { 112 u_int32_t rc_addr_high; 113 u_int32_t rc_addr_low; 114 u_int32_t rc_result; 115 u_int32_t rc_rdma_high; 116 u_int32_t rc_rdma_low; 117 u_int32_t rc_enable; 118 #define MYXRDMA_ON 1 119 #define MYXRDMA_OFF 0 120 u_int8_t rc_pad[40]; /* pad up to 64 bytes */ 121 } __packed; 122 123 struct myx_status { 124 u_int32_t ms_reserved; 125 u_int32_t ms_dropped_pause; 126 u_int32_t ms_dropped_unicast; 127 u_int32_t ms_dropped_crc32err; 128 u_int32_t ms_dropped_phyerr; 129 u_int32_t ms_dropped_mcast; 130 u_int32_t ms_txdonecnt; 131 u_int32_t ms_linkstate; 132 #define MYXSTS_LINKDOWN 0 133 #define MYXSTS_LINKUP 1 134 #define MYXSTS_LINKUNKNOWN 2 135 u_int32_t ms_dropped_linkoverflow; 136 u_int32_t ms_dropped_linkerror; 137 u_int32_t ms_dropped_runt; 138 u_int32_t ms_dropped_overrun; 139 u_int32_t ms_dropped_smallbufunderrun; 140 u_int32_t ms_dropped_bigbufunderrun; 141 u_int32_t ms_rdmatags_available; 142 #define MYXSTS_RDMAON 1 143 #define MYXSTS_RDMAOFF 0 144 u_int8_t ms_txstopped; 145 u_int8_t ms_linkdown; 146 u_int8_t ms_statusupdated; 147 u_int8_t ms_isvalid; 148 } __packed __aligned(4); 149 150 struct myx_intrq_desc { 151 u_int16_t iq_csum; 152 u_int16_t iq_length; 153 } __packed __aligned(4); 154 155 struct myx_rx_desc { 156 u_int64_t rx_addr; 157 } __packed __aligned(8); 158 159 struct myx_tx_desc { 160 u_int64_t tx_addr; 161 u_int16_t tx_hdr_offset; 162 u_int16_t tx_length; 163 u_int8_t tx_pad; 164 u_int8_t tx_nsegs; 165 u_int8_t tx_cksum_offset; 166 u_int8_t tx_flags; 167 #define MYXTXD_FLAGS_SMALL (1<<0) 168 #define MYXTXD_FLAGS_FIRST (1<<1) 169 #define MYXTXD_FLAGS_ALIGN_ODD (1<<2) 170 #define MYXTXD_FLAGS_CKSUM (1<<3) 171 #define MYXTXD_FLAGS_NO_TSO (1<<4) 172 173 #define MYXTXD_FLAGS_TSO_HDR (1<<0) 174 #define MYXTXD_FLAGS_TSO_LAST (1<<3) 175 #define MYXTXD_FLAGS_TSO_CHOP (1<<4) 176 #define MYXTXD_FLAGS_TSO_PLD (1<<5) 177 } __packed __aligned(8); 178 179 enum { 180 MYXCMD_NONE = 0, 181 MYXCMD_RESET = 1, 182 MYXCMD_GET_VERSION = 2, 183 MYXCMD_SET_INTRQDMA = 3, 184 MYXCMD_SET_BIGBUFSZ = 4, 185 MYXCMD_SET_SMALLBUFSZ = 5, 186 MYXCMD_GET_TXRINGOFF = 6, 187 MYXCMD_GET_RXSMALLRINGOFF = 7, 188 MYXCMD_GET_RXBIGRINGOFF = 8, 189 MYXCMD_GET_INTRACKOFF = 9, 190 MYXCMD_GET_INTRDEASSERTOFF = 10, 191 MYXCMD_GET_TXRINGSZ = 11, 192 MYXCMD_GET_RXRINGSZ = 12, 193 MYXCMD_SET_INTRQSZ = 13, 194 MYXCMD_SET_IFUP = 14, 195 MYXCMD_SET_IFDOWN = 15, 196 MYXCMD_SET_MTU = 16, 197 MYXCMD_GET_INTRCOALDELAYOFF = 17, 198 MYXCMD_SET_STATSINTVL = 18, 199 MYXCMD_SET_STATSDMA_OLD = 19, 200 MYXCMD_SET_PROMISC = 20, 201 MYXCMD_UNSET_PROMISC = 21, 202 MYXCMD_SET_LLADDR = 22, 203 MYXCMD_SET_FC = 23, 204 MYXCMD_UNSET_FC = 24, 205 #define MYXCMD_FC_DEFAULT MYXCMD_SET_FC /* set flow control */ 206 MYXCMD_DMA_TEST = 25, 207 MYXCMD_SET_ALLMULTI = 26, 208 MYXCMD_UNSET_ALLMULTI = 27, 209 MYXCMD_SET_MCASTGROUP = 28, 210 MYXCMD_UNSET_MCASTGROUP = 29, 211 MYXCMD_UNSET_MCAST = 30, 212 MYXCMD_SET_STATSDMA = 31, 213 MYXCMD_UNALIGNED_DMA_TEST = 32, 214 MYXCMD_GET_UNALIGNED_STATUS = 33, 215 MYXCMD_MAX = 34 216 }; 217 218 enum { 219 MYXCMD_OK = 0, 220 MYXCMD_UNKNOWN = 1, 221 MYXCMD_ERR_RANGE = 2, 222 MYXCMD_ERR_BUSY = 3, 223 MYXCMD_ERR_EMPTY = 4, 224 MYXCMD_ERR_CLOSED = 5, 225 MYXCMD_ERR_HASH = 6, 226 MYXCMD_ERR_BADPORT = 7, 227 MYXCMD_ERR_RES = 8, 228 MYXCMD_ERR_MULTICAST = 9, 229 MYXCMD_ERR_UNALIGNED = 10 230 }; 231 232 #endif /* _MYX_REG_H */ 233