1 /* $OpenBSD: if_msk.c,v 1.123 2016/04/13 10:34:32 mpi Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include "bpfilter.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/timeout.h> 99 #include <sys/device.h> 100 #include <sys/queue.h> 101 102 #include <net/if.h> 103 104 #include <netinet/in.h> 105 #include <netinet/if_ether.h> 106 107 #include <net/if_media.h> 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #include <dev/mii/mii.h> 114 #include <dev/mii/miivar.h> 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 #include <dev/pci/pcidevs.h> 119 120 #include <dev/pci/if_skreg.h> 121 #include <dev/pci/if_mskvar.h> 122 123 int mskc_probe(struct device *, void *, void *); 124 void mskc_attach(struct device *, struct device *self, void *aux); 125 int mskc_detach(struct device *, int); 126 int mskc_activate(struct device *, int); 127 void mskc_reset(struct sk_softc *); 128 int msk_probe(struct device *, void *, void *); 129 void msk_attach(struct device *, struct device *self, void *aux); 130 int msk_detach(struct device *, int); 131 int msk_activate(struct device *, int); 132 void msk_reset(struct sk_if_softc *); 133 int mskcprint(void *, const char *); 134 int msk_intr(void *); 135 void msk_intr_yukon(struct sk_if_softc *); 136 static __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 137 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 138 void msk_txeof(struct sk_if_softc *); 139 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 140 void msk_start(struct ifnet *); 141 int msk_ioctl(struct ifnet *, u_long, caddr_t); 142 void msk_init(void *); 143 void msk_init_yukon(struct sk_if_softc *); 144 void msk_stop(struct sk_if_softc *, int); 145 void msk_watchdog(struct ifnet *); 146 int msk_ifmedia_upd(struct ifnet *); 147 void msk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 148 int msk_newbuf(struct sk_if_softc *); 149 int msk_init_rx_ring(struct sk_if_softc *); 150 int msk_init_tx_ring(struct sk_if_softc *); 151 void msk_fill_rx_ring(struct sk_if_softc *); 152 153 int msk_miibus_readreg(struct device *, int, int); 154 void msk_miibus_writereg(struct device *, int, int, int); 155 void msk_miibus_statchg(struct device *); 156 157 void msk_iff(struct sk_if_softc *); 158 void msk_tick(void *); 159 160 #ifdef MSK_DEBUG 161 #define DPRINTF(x) if (mskdebug) printf x 162 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 163 int mskdebug = 0; 164 165 void msk_dump_txdesc(struct msk_tx_desc *, int); 166 void msk_dump_mbuf(struct mbuf *); 167 void msk_dump_bytes(const char *, int); 168 #else 169 #define DPRINTF(x) 170 #define DPRINTFN(n,x) 171 #endif 172 173 /* supported device vendors */ 174 const struct pci_matchid mskc_devices[] = { 175 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 176 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 177 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 178 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8021CU }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8021X }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8022CU }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8022X }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 200 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8061CU }, 201 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8061X }, 202 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8062CU }, 203 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8062X }, 204 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 205 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 206 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 207 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 208 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 209 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 210 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 211 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 212 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 213 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 214 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Exx }, 215 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Sxx } 216 }; 217 218 static inline u_int32_t 219 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 220 { 221 return CSR_READ_4(sc, reg); 222 } 223 224 static inline u_int16_t 225 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 226 { 227 return CSR_READ_2(sc, reg); 228 } 229 230 static inline u_int8_t 231 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 232 { 233 return CSR_READ_1(sc, reg); 234 } 235 236 static inline void 237 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 238 { 239 CSR_WRITE_4(sc, reg, x); 240 } 241 242 static inline void 243 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 244 { 245 CSR_WRITE_2(sc, reg, x); 246 } 247 248 static inline void 249 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 250 { 251 CSR_WRITE_1(sc, reg, x); 252 } 253 254 int 255 msk_miibus_readreg(struct device *dev, int phy, int reg) 256 { 257 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 258 u_int16_t val; 259 int i; 260 261 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 262 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 263 264 for (i = 0; i < SK_TIMEOUT; i++) { 265 DELAY(1); 266 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 267 if (val & YU_SMICR_READ_VALID) 268 break; 269 } 270 271 if (i == SK_TIMEOUT) { 272 printf("%s: phy failed to come ready\n", 273 sc_if->sk_dev.dv_xname); 274 return (0); 275 } 276 277 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 278 SK_TIMEOUT)); 279 280 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 281 282 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 283 phy, reg, val)); 284 285 return (val); 286 } 287 288 void 289 msk_miibus_writereg(struct device *dev, int phy, int reg, int val) 290 { 291 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 292 int i; 293 294 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 295 phy, reg, val)); 296 297 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 298 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 299 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 300 301 for (i = 0; i < SK_TIMEOUT; i++) { 302 DELAY(1); 303 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 304 break; 305 } 306 307 if (i == SK_TIMEOUT) 308 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 309 } 310 311 void 312 msk_miibus_statchg(struct device *dev) 313 { 314 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 315 struct mii_data *mii = &sc_if->sk_mii; 316 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 317 int gpcr; 318 319 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 320 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 321 322 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 323 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 324 /* Set speed. */ 325 gpcr |= YU_GPCR_SPEED_DIS; 326 switch (IFM_SUBTYPE(mii->mii_media_active)) { 327 case IFM_1000_SX: 328 case IFM_1000_LX: 329 case IFM_1000_CX: 330 case IFM_1000_T: 331 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 332 break; 333 case IFM_100_TX: 334 gpcr |= YU_GPCR_SPEED; 335 break; 336 } 337 338 /* Set duplex. */ 339 gpcr |= YU_GPCR_DPLX_DIS; 340 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 341 gpcr |= YU_GPCR_DUPLEX; 342 343 /* Disable flow control. */ 344 gpcr |= YU_GPCR_FCTL_DIS; 345 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 346 } 347 348 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 349 350 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 351 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 352 } 353 354 void 355 msk_iff(struct sk_if_softc *sc_if) 356 { 357 struct ifnet *ifp = &sc_if->arpcom.ac_if; 358 struct arpcom *ac = &sc_if->arpcom; 359 struct ether_multi *enm; 360 struct ether_multistep step; 361 u_int32_t hashes[2]; 362 u_int16_t rcr; 363 int h; 364 365 rcr = SK_YU_READ_2(sc_if, YUKON_RCR); 366 rcr &= ~(YU_RCR_MUFLEN | YU_RCR_UFLEN); 367 ifp->if_flags &= ~IFF_ALLMULTI; 368 369 /* 370 * Always accept frames destined to our station address. 371 */ 372 rcr |= YU_RCR_UFLEN; 373 374 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 375 ifp->if_flags |= IFF_ALLMULTI; 376 if (ifp->if_flags & IFF_PROMISC) 377 rcr &= ~YU_RCR_UFLEN; 378 else 379 rcr |= YU_RCR_MUFLEN; 380 hashes[0] = hashes[1] = 0xFFFFFFFF; 381 } else { 382 rcr |= YU_RCR_MUFLEN; 383 /* Program new filter. */ 384 bzero(hashes, sizeof(hashes)); 385 386 ETHER_FIRST_MULTI(step, ac, enm); 387 while (enm != NULL) { 388 h = ether_crc32_be(enm->enm_addrlo, 389 ETHER_ADDR_LEN) & ((1 << SK_HASH_BITS) - 1); 390 391 if (h < 32) 392 hashes[0] |= (1 << h); 393 else 394 hashes[1] |= (1 << (h - 32)); 395 396 ETHER_NEXT_MULTI(step, enm); 397 } 398 } 399 400 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 401 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 402 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 403 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 404 SK_YU_WRITE_2(sc_if, YUKON_RCR, rcr); 405 } 406 407 int 408 msk_init_rx_ring(struct sk_if_softc *sc_if) 409 { 410 struct msk_chain_data *cd = &sc_if->sk_cdata; 411 struct msk_ring_data *rd = sc_if->sk_rdata; 412 int i, nexti; 413 414 bzero(rd->sk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 415 416 for (i = 0; i < MSK_RX_RING_CNT; i++) { 417 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 418 if (i == (MSK_RX_RING_CNT - 1)) 419 nexti = 0; 420 else 421 nexti = i + 1; 422 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 423 } 424 425 sc_if->sk_cdata.sk_rx_prod = 0; 426 sc_if->sk_cdata.sk_rx_cons = 0; 427 428 if_rxr_init(&sc_if->sk_cdata.sk_rx_ring, 2, MSK_RX_RING_CNT); 429 430 msk_fill_rx_ring(sc_if); 431 return (0); 432 } 433 434 int 435 msk_init_tx_ring(struct sk_if_softc *sc_if) 436 { 437 struct sk_softc *sc = sc_if->sk_softc; 438 struct msk_chain_data *cd = &sc_if->sk_cdata; 439 struct msk_ring_data *rd = sc_if->sk_rdata; 440 bus_dmamap_t dmamap; 441 struct sk_txmap_entry *entry; 442 int i, nexti; 443 444 bzero(sc_if->sk_rdata->sk_tx_ring, 445 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 446 447 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 448 for (i = 0; i < MSK_TX_RING_CNT; i++) { 449 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 450 if (i == (MSK_TX_RING_CNT - 1)) 451 nexti = 0; 452 else 453 nexti = i + 1; 454 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 455 456 if (bus_dmamap_create(sc->sc_dmatag, sc_if->sk_pktlen, 457 SK_NTXSEG, sc_if->sk_pktlen, 0, BUS_DMA_NOWAIT, &dmamap)) 458 return (ENOBUFS); 459 460 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 461 if (!entry) { 462 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 463 return (ENOBUFS); 464 } 465 entry->dmamap = dmamap; 466 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 467 } 468 469 sc_if->sk_cdata.sk_tx_prod = 0; 470 sc_if->sk_cdata.sk_tx_cons = 0; 471 sc_if->sk_cdata.sk_tx_cnt = 0; 472 473 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 474 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 475 476 return (0); 477 } 478 479 int 480 msk_newbuf(struct sk_if_softc *sc_if) 481 { 482 struct sk_chain *c; 483 struct msk_rx_desc *r; 484 struct mbuf *m; 485 bus_dmamap_t dmamap; 486 int error; 487 int i, head; 488 489 m = MCLGETI(NULL, M_DONTWAIT, NULL, sc_if->sk_pktlen); 490 if (m == NULL) 491 return (0); 492 m->m_len = m->m_pkthdr.len = sc_if->sk_pktlen; 493 m_adj(m, ETHER_ALIGN); 494 495 dmamap = sc_if->sk_cdata.sk_rx_map[sc_if->sk_cdata.sk_rx_prod]; 496 497 error = bus_dmamap_load_mbuf(sc_if->sk_softc->sc_dmatag, dmamap, m, 498 BUS_DMA_READ|BUS_DMA_NOWAIT); 499 if (error) { 500 m_freem(m); 501 return (0); 502 } 503 504 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 505 dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 506 507 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 508 head = sc_if->sk_cdata.sk_rx_prod; 509 r = c->sk_le; 510 c->sk_mbuf = m; 511 512 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr); 513 r->sk_len = htole16(dmamap->dm_segs[0].ds_len); 514 r->sk_ctl = 0; 515 516 MSK_CDRXSYNC(sc_if, head, BUS_DMASYNC_PREWRITE); 517 518 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 519 520 for (i = 1; i < dmamap->dm_nsegs; i++) { 521 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 522 r = c->sk_le; 523 c->sk_mbuf = NULL; 524 525 r->sk_addr = htole32(dmamap->dm_segs[i].ds_addr); 526 r->sk_len = htole16(dmamap->dm_segs[i].ds_len); 527 r->sk_ctl = 0; 528 529 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 530 BUS_DMASYNC_PREWRITE); 531 532 r->sk_opcode = SK_Y2_RXOPC_BUFFER | SK_Y2_RXOPC_OWN; 533 534 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 535 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 536 537 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 538 } 539 540 c = &sc_if->sk_cdata.sk_rx_chain[head]; 541 r = c->sk_le; 542 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 543 544 MSK_CDRXSYNC(sc_if, head, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 545 546 return (dmamap->dm_nsegs); 547 } 548 549 /* 550 * Set media options. 551 */ 552 int 553 msk_ifmedia_upd(struct ifnet *ifp) 554 { 555 struct sk_if_softc *sc_if = ifp->if_softc; 556 557 mii_mediachg(&sc_if->sk_mii); 558 return (0); 559 } 560 561 /* 562 * Report current media status. 563 */ 564 void 565 msk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 566 { 567 struct sk_if_softc *sc_if = ifp->if_softc; 568 569 mii_pollstat(&sc_if->sk_mii); 570 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 571 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 572 } 573 574 int 575 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 576 { 577 struct sk_if_softc *sc_if = ifp->if_softc; 578 struct ifreq *ifr = (struct ifreq *) data; 579 struct mii_data *mii; 580 int s, error = 0; 581 582 s = splnet(); 583 584 switch(command) { 585 case SIOCSIFADDR: 586 ifp->if_flags |= IFF_UP; 587 if (!(ifp->if_flags & IFF_RUNNING)) 588 msk_init(sc_if); 589 break; 590 591 case SIOCSIFFLAGS: 592 if (ifp->if_flags & IFF_UP) { 593 if (ifp->if_flags & IFF_RUNNING) 594 error = ENETRESET; 595 else 596 msk_init(sc_if); 597 } else { 598 if (ifp->if_flags & IFF_RUNNING) 599 msk_stop(sc_if, 0); 600 } 601 break; 602 603 case SIOCGIFMEDIA: 604 case SIOCSIFMEDIA: 605 mii = &sc_if->sk_mii; 606 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 607 break; 608 609 case SIOCGIFRXR: 610 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 611 NULL, sc_if->sk_pktlen, &sc_if->sk_cdata.sk_rx_ring); 612 break; 613 614 default: 615 error = ether_ioctl(ifp, &sc_if->arpcom, command, data); 616 } 617 618 if (error == ENETRESET) { 619 if (ifp->if_flags & IFF_RUNNING) 620 msk_iff(sc_if); 621 error = 0; 622 } 623 624 splx(s); 625 return (error); 626 } 627 628 /* 629 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 630 * IDs against our list and return a device name if we find a match. 631 */ 632 int 633 mskc_probe(struct device *parent, void *match, void *aux) 634 { 635 return (pci_matchbyid((struct pci_attach_args *)aux, mskc_devices, 636 nitems(mskc_devices))); 637 } 638 639 /* 640 * Force the GEnesis into reset, then bring it out of reset. 641 */ 642 void 643 mskc_reset(struct sk_softc *sc) 644 { 645 u_int32_t imtimer_ticks, reg1; 646 int reg; 647 648 DPRINTFN(2, ("mskc_reset\n")); 649 650 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 651 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 652 653 DELAY(1000); 654 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 655 DELAY(2); 656 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 657 658 sk_win_write_1(sc, SK_TESTCTL1, 2); 659 660 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 661 sc->sk_type >= SK_YUKON_FE_P) { 662 /* enable all clocks. */ 663 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 664 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 665 reg1 &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 666 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 667 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 668 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 669 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), reg1); 670 671 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5)); 672 reg1 &= SK_Y2_REG5_TIM_VMAIN_AV_MASK; 673 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), reg1); 674 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_CFGREG1), 0); 675 676 /* 677 * Disable status race, workaround for Yukon EC Ultra & 678 * Yukon EX. 679 */ 680 reg1 = sk_win_read_4(sc, SK_GPIO); 681 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 682 sk_win_write_4(sc, SK_GPIO, reg1); 683 sk_win_read_4(sc, SK_GPIO); 684 } 685 686 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 687 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 688 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 689 else 690 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 691 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 692 693 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 694 sk_win_write_1(sc, SK_Y2_CLKGATE, 695 SK_Y2_CLKGATE_LINK1_GATE_DIS | 696 SK_Y2_CLKGATE_LINK2_GATE_DIS | 697 SK_Y2_CLKGATE_LINK1_CORE_DIS | 698 SK_Y2_CLKGATE_LINK2_CORE_DIS | 699 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 700 else 701 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 702 703 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 704 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 705 DELAY(1000); 706 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 707 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 708 709 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 710 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 711 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 712 } 713 714 sk_win_write_1(sc, SK_TESTCTL1, 1); 715 716 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 717 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 718 CSR_READ_2(sc, SK_LINK_CTRL))); 719 720 /* Disable ASF */ 721 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 722 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 723 724 /* Clear I2C IRQ noise */ 725 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 726 727 /* Disable hardware timer */ 728 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 729 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 730 731 /* Disable descriptor polling */ 732 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 733 734 /* Disable time stamps */ 735 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 736 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 737 738 /* Enable RAM interface */ 739 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 740 for (reg = SK_TO0;reg <= SK_TO11; reg++) 741 sk_win_write_1(sc, reg, 36); 742 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 743 for (reg = SK_TO0;reg <= SK_TO11; reg++) 744 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 745 746 /* 747 * Configure interrupt moderation. The moderation timer 748 * defers interrupts specified in the interrupt moderation 749 * timer mask based on the timeout specified in the interrupt 750 * moderation timer init register. Each bit in the timer 751 * register represents one tick, so to specify a timeout in 752 * microseconds, we have to multiply by the correct number of 753 * ticks-per-microsecond. 754 */ 755 switch (sc->sk_type) { 756 case SK_YUKON_EC: 757 case SK_YUKON_EC_U: 758 case SK_YUKON_EX: 759 case SK_YUKON_SUPR: 760 case SK_YUKON_ULTRA2: 761 case SK_YUKON_OPTIMA: 762 case SK_YUKON_PRM: 763 case SK_YUKON_OPTIMA2: 764 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 765 break; 766 case SK_YUKON_FE: 767 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 768 break; 769 case SK_YUKON_FE_P: 770 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 771 break; 772 case SK_YUKON_XL: 773 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 774 break; 775 default: 776 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 777 break; 778 } 779 780 /* Reset status ring. */ 781 bzero(sc->sk_status_ring, 782 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 783 sc->sk_status_idx = 0; 784 785 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 786 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 787 788 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 789 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 790 sc->sk_status_map->dm_segs[0].ds_addr); 791 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 792 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 793 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 10); 794 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 16); 795 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 16); 796 797 #if 0 798 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 799 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 800 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(20)); 801 #else 802 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(4)); 803 #endif 804 805 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 806 807 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 808 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 809 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 810 } 811 812 int 813 msk_probe(struct device *parent, void *match, void *aux) 814 { 815 struct skc_attach_args *sa = aux; 816 817 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 818 return (0); 819 820 switch (sa->skc_type) { 821 case SK_YUKON_XL: 822 case SK_YUKON_EC_U: 823 case SK_YUKON_EX: 824 case SK_YUKON_EC: 825 case SK_YUKON_FE: 826 case SK_YUKON_FE_P: 827 case SK_YUKON_SUPR: 828 case SK_YUKON_ULTRA2: 829 case SK_YUKON_OPTIMA: 830 case SK_YUKON_PRM: 831 case SK_YUKON_OPTIMA2: 832 return (1); 833 } 834 835 return (0); 836 } 837 838 void 839 msk_reset(struct sk_if_softc *sc_if) 840 { 841 /* GMAC and GPHY Reset */ 842 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 843 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 844 DELAY(1000); 845 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 846 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 847 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 848 } 849 850 /* 851 * Each XMAC chip is attached as a separate logical IP interface. 852 * Single port cards will have only one logical interface of course. 853 */ 854 void 855 msk_attach(struct device *parent, struct device *self, void *aux) 856 { 857 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 858 struct sk_softc *sc = (struct sk_softc *)parent; 859 struct skc_attach_args *sa = aux; 860 struct ifnet *ifp; 861 caddr_t kva; 862 int i; 863 u_int32_t chunk; 864 int mii_flags; 865 int error; 866 867 sc_if->sk_port = sa->skc_port; 868 sc_if->sk_softc = sc; 869 sc->sk_if[sa->skc_port] = sc_if; 870 871 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 872 873 /* 874 * Get station address for this interface. Note that 875 * dual port cards actually come with three station 876 * addresses: one for each port, plus an extra. The 877 * extra one is used by the SysKonnect driver software 878 * as a 'virtual' station address for when both ports 879 * are operating in failover mode. Currently we don't 880 * use this extra address. 881 */ 882 for (i = 0; i < ETHER_ADDR_LEN; i++) 883 sc_if->arpcom.ac_enaddr[i] = 884 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 885 886 printf(": address %s\n", 887 ether_sprintf(sc_if->arpcom.ac_enaddr)); 888 889 /* 890 * Set up RAM buffer addresses. The Yukon2 has a small amount 891 * of SRAM on it, somewhere between 4K and 48K. We need to 892 * divide this up between the transmitter and receiver. We 893 * give the receiver 2/3 of the memory (rounded down), and the 894 * transmitter whatever remains. 895 */ 896 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 897 sc_if->sk_rx_ramstart = 0; 898 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 899 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 900 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 901 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 902 903 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 904 " tx_ramstart=%#x tx_ramend=%#x\n", 905 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 906 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 907 908 /* Allocate the descriptor queues. */ 909 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 910 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 911 BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 912 printf(": can't alloc rx buffers\n"); 913 goto fail; 914 } 915 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 916 sc_if->sk_ring_nseg, 917 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 918 printf(": can't map dma buffers (%lu bytes)\n", 919 (ulong)sizeof(struct msk_ring_data)); 920 goto fail_1; 921 } 922 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 923 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 924 &sc_if->sk_ring_map)) { 925 printf(": can't create dma map\n"); 926 goto fail_2; 927 } 928 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 929 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 930 printf(": can't load dma map\n"); 931 goto fail_3; 932 } 933 sc_if->sk_rdata = (struct msk_ring_data *)kva; 934 935 if (sc->sk_type != SK_YUKON_FE && 936 sc->sk_type != SK_YUKON_FE_P) 937 sc_if->sk_pktlen = SK_JLEN; 938 else 939 sc_if->sk_pktlen = MCLBYTES; 940 941 for (i = 0; i < MSK_RX_RING_CNT; i++) { 942 if ((error = bus_dmamap_create(sc->sc_dmatag, 943 sc_if->sk_pktlen, SK_NRXSEG, sc_if->sk_pktlen, 944 0, 0, &sc_if->sk_cdata.sk_rx_map[i])) != 0) { 945 printf("\n%s: unable to create rx DMA map %d, " 946 "error = %d\n", sc->sk_dev.dv_xname, i, error); 947 goto fail_4; 948 } 949 } 950 951 ifp = &sc_if->arpcom.ac_if; 952 ifp->if_softc = sc_if; 953 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 954 ifp->if_ioctl = msk_ioctl; 955 ifp->if_start = msk_start; 956 ifp->if_watchdog = msk_watchdog; 957 if (sc->sk_type != SK_YUKON_FE && 958 sc->sk_type != SK_YUKON_FE_P) 959 ifp->if_hardmtu = SK_JUMBO_MTU; 960 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 961 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 962 963 ifp->if_capabilities = IFCAP_VLAN_MTU; 964 965 msk_reset(sc_if); 966 967 /* 968 * Do miibus setup. 969 */ 970 msk_init_yukon(sc_if); 971 972 DPRINTFN(2, ("msk_attach: 1\n")); 973 974 sc_if->sk_mii.mii_ifp = ifp; 975 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 976 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 977 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 978 979 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 980 msk_ifmedia_upd, msk_ifmedia_sts); 981 mii_flags = MIIF_DOPAUSE; 982 if (sc->sk_fibertype) 983 mii_flags |= MIIF_HAVEFIBER; 984 mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0, 985 MII_OFFSET_ANY, mii_flags); 986 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 987 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 988 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 989 0, NULL); 990 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 991 } else 992 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 993 994 timeout_set(&sc_if->sk_tick_ch, msk_tick, sc_if); 995 996 /* 997 * Call MI attach routines. 998 */ 999 if_attach(ifp); 1000 ether_ifattach(ifp); 1001 1002 DPRINTFN(2, ("msk_attach: end\n")); 1003 return; 1004 1005 fail_4: 1006 for (i = 0; i < MSK_RX_RING_CNT; i++) { 1007 if (sc_if->sk_cdata.sk_rx_map[i] != NULL) 1008 bus_dmamap_destroy(sc->sc_dmatag, 1009 sc_if->sk_cdata.sk_rx_map[i]); 1010 } 1011 1012 fail_3: 1013 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1014 fail_2: 1015 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1016 fail_1: 1017 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1018 fail: 1019 sc->sk_if[sa->skc_port] = NULL; 1020 } 1021 1022 int 1023 msk_detach(struct device *self, int flags) 1024 { 1025 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 1026 struct sk_softc *sc = sc_if->sk_softc; 1027 struct ifnet *ifp= &sc_if->arpcom.ac_if; 1028 1029 if (sc->sk_if[sc_if->sk_port] == NULL) 1030 return (0); 1031 1032 msk_stop(sc_if, 1); 1033 1034 /* Detach any PHYs we might have. */ 1035 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1036 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1037 1038 /* Delete any remaining media. */ 1039 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1040 1041 ether_ifdetach(ifp); 1042 if_detach(ifp); 1043 1044 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc_if->sk_rdata, 1045 sizeof(struct msk_ring_data)); 1046 bus_dmamem_free(sc->sc_dmatag, 1047 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1048 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1049 sc->sk_if[sc_if->sk_port] = NULL; 1050 1051 return (0); 1052 } 1053 1054 int 1055 msk_activate(struct device *self, int act) 1056 { 1057 struct sk_if_softc *sc_if = (void *)self; 1058 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1059 int rv = 0; 1060 1061 switch (act) { 1062 case DVACT_RESUME: 1063 msk_reset(sc_if); 1064 if (ifp->if_flags & IFF_RUNNING) 1065 msk_init(sc_if); 1066 break; 1067 default: 1068 rv = config_activate_children(self, act); 1069 break; 1070 } 1071 return (rv); 1072 } 1073 1074 int 1075 mskcprint(void *aux, const char *pnp) 1076 { 1077 struct skc_attach_args *sa = aux; 1078 1079 if (pnp) 1080 printf("msk port %c at %s", 1081 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1082 else 1083 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1084 return (UNCONF); 1085 } 1086 1087 /* 1088 * Attach the interface. Allocate softc structures, do ifmedia 1089 * setup and ethernet/BPF attach. 1090 */ 1091 void 1092 mskc_attach(struct device *parent, struct device *self, void *aux) 1093 { 1094 struct sk_softc *sc = (struct sk_softc *)self; 1095 struct pci_attach_args *pa = aux; 1096 struct skc_attach_args skca; 1097 pci_chipset_tag_t pc = pa->pa_pc; 1098 pcireg_t memtype; 1099 pci_intr_handle_t ih; 1100 const char *intrstr = NULL; 1101 u_int8_t hw, pmd; 1102 char *revstr = NULL; 1103 caddr_t kva; 1104 1105 DPRINTFN(2, ("begin mskc_attach\n")); 1106 1107 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 1108 1109 /* 1110 * Map control/status registers. 1111 */ 1112 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1113 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1114 &sc->sk_bhandle, NULL, &sc->sk_bsize, 0)) { 1115 printf(": can't map mem space\n"); 1116 return; 1117 } 1118 1119 sc->sc_dmatag = pa->pa_dmat; 1120 1121 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1122 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1123 1124 /* bail out here if chip is not recognized */ 1125 if (!(SK_IS_YUKON2(sc))) { 1126 printf(": unknown chip type: %d\n", sc->sk_type); 1127 goto fail_1; 1128 } 1129 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1130 1131 /* Allocate interrupt */ 1132 if (pci_intr_map(pa, &ih)) { 1133 printf(": couldn't map interrupt\n"); 1134 goto fail_1; 1135 } 1136 1137 intrstr = pci_intr_string(pc, ih); 1138 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc, 1139 self->dv_xname); 1140 if (sc->sk_intrhand == NULL) { 1141 printf(": couldn't establish interrupt"); 1142 if (intrstr != NULL) 1143 printf(" at %s", intrstr); 1144 printf("\n"); 1145 goto fail_1; 1146 } 1147 sc->sk_pc = pc; 1148 1149 if (bus_dmamem_alloc(sc->sc_dmatag, 1150 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1151 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1152 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, 1153 BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 1154 printf(": can't alloc status buffers\n"); 1155 goto fail_2; 1156 } 1157 1158 if (bus_dmamem_map(sc->sc_dmatag, 1159 &sc->sk_status_seg, sc->sk_status_nseg, 1160 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1161 &kva, BUS_DMA_NOWAIT)) { 1162 printf(": can't map dma buffers (%lu bytes)\n", 1163 (ulong)(MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc))); 1164 goto fail_3; 1165 } 1166 if (bus_dmamap_create(sc->sc_dmatag, 1167 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1168 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1169 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1170 printf(": can't create dma map\n"); 1171 goto fail_4; 1172 } 1173 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1174 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1175 NULL, BUS_DMA_NOWAIT)) { 1176 printf(": can't load dma map\n"); 1177 goto fail_5; 1178 } 1179 sc->sk_status_ring = (struct msk_status_desc *)kva; 1180 1181 /* Reset the adapter. */ 1182 mskc_reset(sc); 1183 1184 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1185 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1186 1187 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1188 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1189 sc->sk_fibertype = 1; 1190 1191 switch (sc->sk_type) { 1192 case SK_YUKON_XL: 1193 sc->sk_name = "Yukon-2 XL"; 1194 break; 1195 case SK_YUKON_EC_U: 1196 sc->sk_name = "Yukon-2 EC Ultra"; 1197 break; 1198 case SK_YUKON_EX: 1199 sc->sk_name = "Yukon-2 Extreme"; 1200 break; 1201 case SK_YUKON_EC: 1202 sc->sk_name = "Yukon-2 EC"; 1203 break; 1204 case SK_YUKON_FE: 1205 sc->sk_name = "Yukon-2 FE"; 1206 break; 1207 case SK_YUKON_FE_P: 1208 sc->sk_name = "Yukon-2 FE+"; 1209 break; 1210 case SK_YUKON_SUPR: 1211 sc->sk_name = "Yukon-2 Supreme"; 1212 break; 1213 case SK_YUKON_ULTRA2: 1214 sc->sk_name = "Yukon-2 Ultra 2"; 1215 break; 1216 case SK_YUKON_OPTIMA: 1217 sc->sk_name = "Yukon-2 Optima"; 1218 break; 1219 case SK_YUKON_PRM: 1220 sc->sk_name = "Yukon-2 Optima Prime"; 1221 break; 1222 case SK_YUKON_OPTIMA2: 1223 sc->sk_name = "Yukon-2 Optima 2"; 1224 break; 1225 default: 1226 sc->sk_name = "Yukon (Unknown)"; 1227 } 1228 1229 if (sc->sk_type == SK_YUKON_XL) { 1230 switch (sc->sk_rev) { 1231 case SK_YUKON_XL_REV_A0: 1232 revstr = "A0"; 1233 break; 1234 case SK_YUKON_XL_REV_A1: 1235 revstr = "A1"; 1236 break; 1237 case SK_YUKON_XL_REV_A2: 1238 revstr = "A2"; 1239 break; 1240 case SK_YUKON_XL_REV_A3: 1241 revstr = "A3"; 1242 break; 1243 default: 1244 ; 1245 } 1246 } 1247 1248 if (sc->sk_type == SK_YUKON_EC) { 1249 switch (sc->sk_rev) { 1250 case SK_YUKON_EC_REV_A1: 1251 revstr = "A1"; 1252 break; 1253 case SK_YUKON_EC_REV_A2: 1254 revstr = "A2"; 1255 break; 1256 case SK_YUKON_EC_REV_A3: 1257 revstr = "A3"; 1258 break; 1259 default: 1260 ; 1261 } 1262 } 1263 1264 if (sc->sk_type == SK_YUKON_EC_U) { 1265 switch (sc->sk_rev) { 1266 case SK_YUKON_EC_U_REV_A0: 1267 revstr = "A0"; 1268 break; 1269 case SK_YUKON_EC_U_REV_A1: 1270 revstr = "A1"; 1271 break; 1272 case SK_YUKON_EC_U_REV_B0: 1273 revstr = "B0"; 1274 break; 1275 case SK_YUKON_EC_U_REV_B1: 1276 revstr = "B1"; 1277 break; 1278 default: 1279 ; 1280 } 1281 } 1282 1283 if (sc->sk_type == SK_YUKON_FE) { 1284 switch (sc->sk_rev) { 1285 case SK_YUKON_FE_REV_A1: 1286 revstr = "A1"; 1287 break; 1288 case SK_YUKON_FE_REV_A2: 1289 revstr = "A2"; 1290 break; 1291 default: 1292 ; 1293 } 1294 } 1295 1296 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1297 revstr = "A0"; 1298 1299 if (sc->sk_type == SK_YUKON_EX) { 1300 switch (sc->sk_rev) { 1301 case SK_YUKON_EX_REV_A0: 1302 revstr = "A0"; 1303 break; 1304 case SK_YUKON_EX_REV_B0: 1305 revstr = "B0"; 1306 break; 1307 default: 1308 ; 1309 } 1310 } 1311 1312 if (sc->sk_type == SK_YUKON_SUPR) { 1313 switch (sc->sk_rev) { 1314 case SK_YUKON_SUPR_REV_A0: 1315 revstr = "A0"; 1316 break; 1317 case SK_YUKON_SUPR_REV_B0: 1318 revstr = "B0"; 1319 break; 1320 case SK_YUKON_SUPR_REV_B1: 1321 revstr = "B1"; 1322 break; 1323 default: 1324 ; 1325 } 1326 } 1327 1328 if (sc->sk_type == SK_YUKON_PRM) { 1329 switch (sc->sk_rev) { 1330 case SK_YUKON_PRM_REV_Z1: 1331 revstr = "Z1"; 1332 break; 1333 case SK_YUKON_PRM_REV_A0: 1334 revstr = "A0"; 1335 break; 1336 default: 1337 ; 1338 } 1339 } 1340 1341 /* Announce the product name. */ 1342 printf(", %s", sc->sk_name); 1343 if (revstr != NULL) 1344 printf(" rev. %s", revstr); 1345 printf(" (0x%x): %s\n", sc->sk_rev, intrstr); 1346 1347 sc->sk_macs = 1; 1348 1349 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1350 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1351 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1352 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1353 sc->sk_macs++; 1354 } 1355 1356 skca.skc_port = SK_PORT_A; 1357 skca.skc_type = sc->sk_type; 1358 skca.skc_rev = sc->sk_rev; 1359 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1360 1361 if (sc->sk_macs > 1) { 1362 skca.skc_port = SK_PORT_B; 1363 skca.skc_type = sc->sk_type; 1364 skca.skc_rev = sc->sk_rev; 1365 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1366 } 1367 1368 /* Turn on the 'driver is loaded' LED. */ 1369 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1370 1371 return; 1372 1373 fail_4: 1374 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sk_status_ring, 1375 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1376 fail_3: 1377 bus_dmamem_free(sc->sc_dmatag, 1378 &sc->sk_status_seg, sc->sk_status_nseg); 1379 sc->sk_status_nseg = 0; 1380 fail_5: 1381 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1382 fail_2: 1383 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1384 sc->sk_intrhand = NULL; 1385 fail_1: 1386 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1387 sc->sk_bsize = 0; 1388 } 1389 1390 int 1391 mskc_detach(struct device *self, int flags) 1392 { 1393 struct sk_softc *sc = (struct sk_softc *)self; 1394 int rv; 1395 1396 if (sc->sk_intrhand) 1397 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1398 1399 rv = config_detach_children(self, flags); 1400 if (rv != 0) 1401 return (rv); 1402 1403 if (sc->sk_status_nseg > 0) { 1404 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1405 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sk_status_ring, 1406 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1407 bus_dmamem_free(sc->sc_dmatag, 1408 &sc->sk_status_seg, sc->sk_status_nseg); 1409 } 1410 1411 if (sc->sk_bsize > 0) 1412 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1413 1414 return(0); 1415 } 1416 1417 int 1418 mskc_activate(struct device *self, int act) 1419 { 1420 struct sk_softc *sc = (void *)self; 1421 int rv = 0; 1422 1423 switch (act) { 1424 case DVACT_RESUME: 1425 mskc_reset(sc); 1426 rv = config_activate_children(self, act); 1427 break; 1428 default: 1429 rv = config_activate_children(self, act); 1430 break; 1431 } 1432 return (rv); 1433 } 1434 1435 int 1436 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1437 { 1438 struct sk_softc *sc = sc_if->sk_softc; 1439 struct msk_tx_desc *f = NULL; 1440 u_int32_t frag, cur; 1441 int i; 1442 struct sk_txmap_entry *entry; 1443 bus_dmamap_t txmap; 1444 1445 DPRINTFN(2, ("msk_encap\n")); 1446 1447 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1448 if (entry == NULL) { 1449 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1450 return (ENOBUFS); 1451 } 1452 txmap = entry->dmamap; 1453 1454 cur = frag = *txidx; 1455 1456 #ifdef MSK_DEBUG 1457 if (mskdebug >= 2) 1458 msk_dump_mbuf(m_head); 1459 #endif 1460 1461 /* 1462 * Start packing the mbufs in this chain into 1463 * the fragment pointers. Stop when we run out 1464 * of fragments or hit the end of the mbuf chain. 1465 */ 1466 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1467 BUS_DMA_NOWAIT)) { 1468 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1469 return (ENOBUFS); 1470 } 1471 1472 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1473 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1474 bus_dmamap_unload(sc->sc_dmatag, txmap); 1475 return (ENOBUFS); 1476 } 1477 1478 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1479 1480 /* Sync the DMA map. */ 1481 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1482 BUS_DMASYNC_PREWRITE); 1483 1484 for (i = 0; i < txmap->dm_nsegs; i++) { 1485 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1486 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1487 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1488 f->sk_ctl = 0; 1489 if (i == 0) 1490 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1491 else 1492 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1493 cur = frag; 1494 SK_INC(frag, MSK_TX_RING_CNT); 1495 } 1496 1497 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1498 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1499 1500 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1501 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1502 1503 /* Sync descriptors before handing to chip */ 1504 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1505 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1506 1507 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1508 1509 /* Sync first descriptor to hand it off */ 1510 MSK_CDTXSYNC(sc_if, *txidx, 1, 1511 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1512 1513 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1514 1515 #ifdef MSK_DEBUG 1516 if (mskdebug >= 2) { 1517 struct msk_tx_desc *le; 1518 u_int32_t idx; 1519 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1520 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1521 msk_dump_txdesc(le, idx); 1522 } 1523 } 1524 #endif 1525 1526 *txidx = frag; 1527 1528 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1529 1530 return (0); 1531 } 1532 1533 void 1534 msk_start(struct ifnet *ifp) 1535 { 1536 struct sk_if_softc *sc_if = ifp->if_softc; 1537 struct mbuf *m_head = NULL; 1538 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1539 int pkts = 0; 1540 1541 DPRINTFN(2, ("msk_start\n")); 1542 1543 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1544 m_head = ifq_deq_begin(&ifp->if_snd); 1545 if (m_head == NULL) 1546 break; 1547 1548 /* 1549 * Pack the data into the transmit ring. If we 1550 * don't have room, set the OACTIVE flag and wait 1551 * for the NIC to drain the ring. 1552 */ 1553 if (msk_encap(sc_if, m_head, &idx)) { 1554 ifq_deq_rollback(&ifp->if_snd, m_head); 1555 ifq_set_oactive(&ifp->if_snd); 1556 break; 1557 } 1558 1559 /* now we are committed to transmit the packet */ 1560 ifq_deq_commit(&ifp->if_snd, m_head); 1561 pkts++; 1562 1563 /* 1564 * If there's a BPF listener, bounce a copy of this frame 1565 * to him. 1566 */ 1567 #if NBPFILTER > 0 1568 if (ifp->if_bpf) 1569 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1570 #endif 1571 } 1572 if (pkts == 0) 1573 return; 1574 1575 /* Transmit */ 1576 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1577 sc_if->sk_cdata.sk_tx_prod = idx; 1578 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1579 1580 /* Set a timeout in case the chip goes out to lunch. */ 1581 ifp->if_timer = 5; 1582 } 1583 } 1584 1585 void 1586 msk_watchdog(struct ifnet *ifp) 1587 { 1588 struct sk_if_softc *sc_if = ifp->if_softc; 1589 1590 /* 1591 * Reclaim first as there is a possibility of losing Tx completion 1592 * interrupts. 1593 */ 1594 msk_txeof(sc_if); 1595 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1596 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1597 1598 ifp->if_oerrors++; 1599 1600 /* XXX Resets both ports; we shouldn't do that. */ 1601 mskc_reset(sc_if->sk_softc); 1602 msk_reset(sc_if); 1603 msk_init(sc_if); 1604 } 1605 } 1606 1607 static __inline int 1608 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1609 { 1610 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1611 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1612 YU_RXSTAT_JABBER)) != 0 || 1613 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1614 YU_RXSTAT_BYTES(stat) != len) 1615 return (0); 1616 1617 return (1); 1618 } 1619 1620 void 1621 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1622 { 1623 struct sk_softc *sc = sc_if->sk_softc; 1624 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1625 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1626 struct mbuf *m; 1627 struct sk_chain *cur_rx; 1628 int i, cur, total_len = len; 1629 bus_dmamap_t dmamap; 1630 1631 DPRINTFN(2, ("msk_rxeof\n")); 1632 1633 cur = sc_if->sk_cdata.sk_rx_cons; 1634 1635 /* Sync the descriptor */ 1636 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1637 1638 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1639 if (cur_rx->sk_mbuf == NULL) 1640 return; 1641 1642 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1643 for (i = 0; i < dmamap->dm_nsegs; i++) { 1644 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1645 } 1646 if_rxr_put(&sc_if->sk_cdata.sk_rx_ring, dmamap->dm_nsegs); 1647 1648 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1649 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1650 bus_dmamap_unload(sc_if->sk_softc->sc_dmatag, dmamap); 1651 1652 m = cur_rx->sk_mbuf; 1653 cur_rx->sk_mbuf = NULL; 1654 1655 if (total_len < SK_MIN_FRAMELEN || 1656 total_len > SK_JUMBO_FRAMELEN || 1657 msk_rxvalid(sc, rxstat, total_len) == 0) { 1658 ifp->if_ierrors++; 1659 m_freem(m); 1660 return; 1661 } 1662 1663 m->m_pkthdr.len = m->m_len = total_len; 1664 1665 ml_enqueue(&ml, m); 1666 if_input(ifp, &ml); 1667 } 1668 1669 void 1670 msk_txeof(struct sk_if_softc *sc_if) 1671 { 1672 struct sk_softc *sc = sc_if->sk_softc; 1673 struct msk_tx_desc *cur_tx; 1674 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1675 u_int32_t idx, reg, sk_ctl; 1676 struct sk_txmap_entry *entry; 1677 1678 DPRINTFN(2, ("msk_txeof\n")); 1679 1680 if (sc_if->sk_port == SK_PORT_A) 1681 reg = SK_STAT_BMU_TXA1_RIDX; 1682 else 1683 reg = SK_STAT_BMU_TXA2_RIDX; 1684 1685 /* 1686 * Go through our tx ring and free mbufs for those 1687 * frames that have been sent. 1688 */ 1689 idx = sc_if->sk_cdata.sk_tx_cons; 1690 while (idx != sk_win_read_2(sc, reg)) { 1691 MSK_CDTXSYNC(sc_if, idx, 1, 1692 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1693 1694 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1695 sk_ctl = cur_tx->sk_ctl; 1696 #ifdef MSK_DEBUG 1697 if (mskdebug >= 2) 1698 msk_dump_txdesc(cur_tx, idx); 1699 #endif 1700 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1701 ifp->if_opackets++; 1702 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1703 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1704 1705 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1706 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1707 1708 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1709 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1710 1711 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1712 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1713 link); 1714 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1715 } 1716 sc_if->sk_cdata.sk_tx_cnt--; 1717 SK_INC(idx, MSK_TX_RING_CNT); 1718 } 1719 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1720 1721 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1722 ifq_clr_oactive(&ifp->if_snd); 1723 1724 sc_if->sk_cdata.sk_tx_cons = idx; 1725 } 1726 1727 void 1728 msk_fill_rx_ring(struct sk_if_softc *sc_if) 1729 { 1730 u_int slots, used; 1731 1732 slots = if_rxr_get(&sc_if->sk_cdata.sk_rx_ring, MSK_RX_RING_CNT); 1733 while (slots > 0) { 1734 used = msk_newbuf(sc_if); 1735 if (used == 0) 1736 break; 1737 1738 slots -= used; 1739 } 1740 if_rxr_put(&sc_if->sk_cdata.sk_rx_ring, slots); 1741 } 1742 1743 void 1744 msk_tick(void *xsc_if) 1745 { 1746 struct sk_if_softc *sc_if = xsc_if; 1747 struct mii_data *mii = &sc_if->sk_mii; 1748 int s; 1749 1750 s = splnet(); 1751 mii_tick(mii); 1752 splx(s); 1753 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1754 } 1755 1756 void 1757 msk_intr_yukon(struct sk_if_softc *sc_if) 1758 { 1759 u_int8_t status; 1760 1761 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1762 /* RX overrun */ 1763 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1764 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1765 SK_RFCTL_RX_FIFO_OVER); 1766 } 1767 /* TX underrun */ 1768 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1769 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1770 SK_TFCTL_TX_FIFO_UNDER); 1771 } 1772 1773 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1774 } 1775 1776 int 1777 msk_intr(void *xsc) 1778 { 1779 struct sk_softc *sc = xsc; 1780 struct sk_if_softc *sc_if; 1781 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1782 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1783 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1784 int claimed = 0, rx[2] = {0, 0}; 1785 u_int32_t status; 1786 struct msk_status_desc *cur_st; 1787 1788 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1789 if (status == 0xffffffff) 1790 return (0); 1791 if (status == 0) { 1792 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1793 return (0); 1794 } 1795 1796 status = CSR_READ_4(sc, SK_ISR); 1797 1798 if (sc_if0 != NULL) 1799 ifp0 = &sc_if0->arpcom.ac_if; 1800 if (sc_if1 != NULL) 1801 ifp1 = &sc_if1->arpcom.ac_if; 1802 1803 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1804 (ifp0->if_flags & IFF_RUNNING)) { 1805 msk_intr_yukon(sc_if0); 1806 } 1807 1808 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1809 (ifp1->if_flags & IFF_RUNNING)) { 1810 msk_intr_yukon(sc_if1); 1811 } 1812 1813 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1814 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1815 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1816 1817 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 1818 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1819 switch (cur_st->sk_opcode) { 1820 case SK_Y2_STOPC_RXSTAT: 1821 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 1822 rx[cur_st->sk_link & 0x01] = 1; 1823 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 1824 letoh32(cur_st->sk_status)); 1825 break; 1826 case SK_Y2_STOPC_TXSTAT: 1827 if (sc_if0) 1828 msk_txeof(sc_if0); 1829 if (sc_if1) 1830 msk_txeof(sc_if1); 1831 break; 1832 default: 1833 printf("opcode=0x%x\n", cur_st->sk_opcode); 1834 break; 1835 } 1836 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1837 1838 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1839 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1840 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1841 } 1842 1843 if (status & SK_Y2_IMR_BMU) { 1844 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1845 claimed = 1; 1846 } 1847 1848 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1849 1850 if (rx[0]) { 1851 msk_fill_rx_ring(sc_if0); 1852 SK_IF_WRITE_2(sc_if0, 0, SK_RXQ1_Y2_PREF_PUTIDX, 1853 sc_if0->sk_cdata.sk_rx_prod); 1854 } 1855 if (rx[1]) { 1856 msk_fill_rx_ring(sc_if1); 1857 SK_IF_WRITE_2(sc_if1, 0, SK_RXQ1_Y2_PREF_PUTIDX, 1858 sc_if1->sk_cdata.sk_rx_prod); 1859 } 1860 1861 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1862 msk_start(ifp0); 1863 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1864 msk_start(ifp1); 1865 1866 return (claimed); 1867 } 1868 1869 void 1870 msk_init_yukon(struct sk_if_softc *sc_if) 1871 { 1872 u_int32_t v; 1873 u_int16_t reg; 1874 struct sk_softc *sc; 1875 int i; 1876 1877 sc = sc_if->sk_softc; 1878 1879 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1880 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1881 1882 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1883 1884 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1885 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1886 1887 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1888 1889 /* unused read of the interrupt source register */ 1890 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1891 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1892 1893 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1894 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1895 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1896 1897 /* MIB Counter Clear Mode set */ 1898 reg |= YU_PAR_MIB_CLR; 1899 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1900 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1901 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1902 1903 /* MIB Counter Clear Mode clear */ 1904 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1905 reg &= ~YU_PAR_MIB_CLR; 1906 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1907 1908 /* receive control reg */ 1909 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1910 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1911 1912 /* transmit parameter register */ 1913 DPRINTFN(6, ("msk_init_yukon: 8\n")); 1914 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 1915 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 1916 1917 /* serial mode register */ 1918 DPRINTFN(6, ("msk_init_yukon: 9\n")); 1919 reg = YU_SMR_DATA_BLIND(0x1c) | 1920 YU_SMR_MFL_VLAN | 1921 YU_SMR_IPG_DATA(0x1e); 1922 1923 if (sc->sk_type != SK_YUKON_FE && 1924 sc->sk_type != SK_YUKON_FE_P) 1925 reg |= YU_SMR_MFL_JUMBO; 1926 1927 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 1928 1929 DPRINTFN(6, ("msk_init_yukon: 10\n")); 1930 /* Setup Yukon's address */ 1931 for (i = 0; i < 3; i++) { 1932 /* Write Source Address 1 (unicast filter) */ 1933 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 1934 sc_if->arpcom.ac_enaddr[i * 2] | 1935 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 1936 } 1937 1938 for (i = 0; i < 3; i++) { 1939 reg = sk_win_read_2(sc_if->sk_softc, 1940 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 1941 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 1942 } 1943 1944 /* Program promiscuous mode and multicast filters */ 1945 DPRINTFN(6, ("msk_init_yukon: 11\n")); 1946 msk_iff(sc_if); 1947 1948 /* enable interrupt mask for counter overflows */ 1949 DPRINTFN(6, ("msk_init_yukon: 12\n")); 1950 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 1951 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 1952 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 1953 1954 /* Configure RX MAC FIFO Flush Mask */ 1955 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 1956 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 1957 YU_RXSTAT_JABBER; 1958 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 1959 1960 /* Configure RX MAC FIFO */ 1961 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 1962 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 1963 SK_RFCTL_FIFO_FLUSH_ON); 1964 1965 /* Increase flush threshould to 64 bytes */ 1966 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 1967 SK_RFCTL_FIFO_THRESHOLD + 1); 1968 1969 /* Configure TX MAC FIFO */ 1970 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 1971 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 1972 1973 #if 1 1974 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 1975 #endif 1976 DPRINTFN(6, ("msk_init_yukon: end\n")); 1977 } 1978 1979 /* 1980 * Note that to properly initialize any part of the GEnesis chip, 1981 * you first have to take it out of reset mode. 1982 */ 1983 void 1984 msk_init(void *xsc_if) 1985 { 1986 struct sk_if_softc *sc_if = xsc_if; 1987 struct sk_softc *sc = sc_if->sk_softc; 1988 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1989 struct mii_data *mii = &sc_if->sk_mii; 1990 int s; 1991 1992 DPRINTFN(2, ("msk_init\n")); 1993 1994 s = splnet(); 1995 1996 /* Cancel pending I/O and free all RX/TX buffers. */ 1997 msk_stop(sc_if, 0); 1998 1999 /* Configure I2C registers */ 2000 2001 /* Configure XMAC(s) */ 2002 msk_init_yukon(sc_if); 2003 mii_mediachg(mii); 2004 2005 /* Configure transmit arbiter(s) */ 2006 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2007 #if 0 2008 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2009 #endif 2010 2011 /* Configure RAMbuffers */ 2012 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2013 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2014 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2015 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2016 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2017 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2018 2019 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2020 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2021 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2022 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2023 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2024 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2025 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2026 2027 /* Configure BMUs */ 2028 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2029 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2030 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2031 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_WATERMARK, 0x00000600); 2032 2033 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2034 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2035 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2036 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_WATERMARK, 0x00000600); 2037 2038 /* Make sure the sync transmit queue is disabled. */ 2039 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2040 2041 /* Init descriptors */ 2042 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2043 printf("%s: initialization failed: no " 2044 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2045 msk_stop(sc_if, 0); 2046 splx(s); 2047 return; 2048 } 2049 2050 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2051 printf("%s: initialization failed: no " 2052 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2053 msk_stop(sc_if, 0); 2054 splx(s); 2055 return; 2056 } 2057 2058 /* Initialize prefetch engine. */ 2059 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2060 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2061 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2062 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2063 MSK_RX_RING_ADDR(sc_if, 0)); 2064 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2065 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2066 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2067 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2068 2069 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2070 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2071 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2072 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2073 MSK_TX_RING_ADDR(sc_if, 0)); 2074 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2075 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2076 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2077 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2078 2079 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2080 sc_if->sk_cdata.sk_rx_prod); 2081 2082 /* Configure interrupt handling */ 2083 if (sc_if->sk_port == SK_PORT_A) 2084 sc->sk_intrmask |= SK_Y2_INTRS1; 2085 else 2086 sc->sk_intrmask |= SK_Y2_INTRS2; 2087 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2088 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2089 2090 ifp->if_flags |= IFF_RUNNING; 2091 ifq_clr_oactive(&ifp->if_snd); 2092 2093 timeout_add_sec(&sc_if->sk_tick_ch, 1); 2094 2095 splx(s); 2096 } 2097 2098 void 2099 msk_stop(struct sk_if_softc *sc_if, int softonly) 2100 { 2101 struct sk_softc *sc = sc_if->sk_softc; 2102 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2103 struct sk_txmap_entry *dma; 2104 int i; 2105 2106 DPRINTFN(2, ("msk_stop\n")); 2107 2108 timeout_del(&sc_if->sk_tick_ch); 2109 2110 ifp->if_flags &= ~IFF_RUNNING; 2111 ifq_clr_oactive(&ifp->if_snd); 2112 2113 /* Stop transfer of Tx descriptors */ 2114 2115 /* Stop transfer of Rx descriptors */ 2116 2117 if (!softonly) { 2118 /* Turn off various components of this interface. */ 2119 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2120 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2121 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2122 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2123 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2124 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2125 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2126 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2127 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2128 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2129 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2130 2131 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2132 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2133 2134 /* Disable interrupts */ 2135 if (sc_if->sk_port == SK_PORT_A) 2136 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2137 else 2138 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2139 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2140 } 2141 2142 /* Free RX and TX mbufs still in the queues. */ 2143 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2144 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2145 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2146 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2147 } 2148 } 2149 2150 sc_if->sk_cdata.sk_rx_prod = 0; 2151 sc_if->sk_cdata.sk_rx_cons = 0; 2152 2153 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2154 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2155 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2156 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2157 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2158 sc_if->sk_cdata.sk_tx_map[i], link); 2159 sc_if->sk_cdata.sk_tx_map[i] = 0; 2160 } 2161 } 2162 2163 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2164 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2165 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2166 free(dma, M_DEVBUF, sizeof *dma); 2167 } 2168 } 2169 2170 struct cfattach mskc_ca = { 2171 sizeof(struct sk_softc), mskc_probe, mskc_attach, mskc_detach, 2172 mskc_activate 2173 }; 2174 2175 struct cfdriver mskc_cd = { 2176 NULL, "mskc", DV_DULL 2177 }; 2178 2179 struct cfattach msk_ca = { 2180 sizeof(struct sk_if_softc), msk_probe, msk_attach, msk_detach, 2181 msk_activate 2182 }; 2183 2184 struct cfdriver msk_cd = { 2185 NULL, "msk", DV_IFNET 2186 }; 2187 2188 #ifdef MSK_DEBUG 2189 void 2190 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2191 { 2192 #define DESC_PRINT(X) \ 2193 if (X) \ 2194 printf("txdesc[%d]." #X "=%#x\n", \ 2195 idx, X); 2196 2197 DESC_PRINT(letoh32(le->sk_addr)); 2198 DESC_PRINT(letoh16(le->sk_len)); 2199 DESC_PRINT(le->sk_ctl); 2200 DESC_PRINT(le->sk_opcode); 2201 #undef DESC_PRINT 2202 } 2203 2204 void 2205 msk_dump_bytes(const char *data, int len) 2206 { 2207 int c, i, j; 2208 2209 for (i = 0; i < len; i += 16) { 2210 printf("%08x ", i); 2211 c = len - i; 2212 if (c > 16) c = 16; 2213 2214 for (j = 0; j < c; j++) { 2215 printf("%02x ", data[i + j] & 0xff); 2216 if ((j & 0xf) == 7 && j > 0) 2217 printf(" "); 2218 } 2219 2220 for (; j < 16; j++) 2221 printf(" "); 2222 printf(" "); 2223 2224 for (j = 0; j < c; j++) { 2225 int ch = data[i + j] & 0xff; 2226 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2227 } 2228 2229 printf("\n"); 2230 2231 if (c < 16) 2232 break; 2233 } 2234 } 2235 2236 void 2237 msk_dump_mbuf(struct mbuf *m) 2238 { 2239 int count = m->m_pkthdr.len; 2240 2241 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2242 2243 while (count > 0 && m) { 2244 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2245 m, m->m_data, m->m_len); 2246 msk_dump_bytes(mtod(m, char *), m->m_len); 2247 2248 count -= m->m_len; 2249 m = m->m_next; 2250 } 2251 } 2252 #endif 2253