1 /* $OpenBSD: if_msk.c,v 1.93 2011/06/22 16:44:27 tedu Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include "bpfilter.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/timeout.h> 99 #include <sys/device.h> 100 #include <sys/queue.h> 101 102 #include <net/if.h> 103 #include <net/if_dl.h> 104 #include <net/if_types.h> 105 106 #ifdef INET 107 #include <netinet/in.h> 108 #include <netinet/in_systm.h> 109 #include <netinet/in_var.h> 110 #include <netinet/ip.h> 111 #include <netinet/udp.h> 112 #include <netinet/tcp.h> 113 #include <netinet/if_ether.h> 114 #endif 115 116 #include <net/if_media.h> 117 #include <net/if_vlan_var.h> 118 119 #if NBPFILTER > 0 120 #include <net/bpf.h> 121 #endif 122 123 #include <dev/mii/mii.h> 124 #include <dev/mii/miivar.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/pcidevs.h> 130 131 #include <dev/pci/if_skreg.h> 132 #include <dev/pci/if_mskvar.h> 133 134 int mskc_probe(struct device *, void *, void *); 135 void mskc_attach(struct device *, struct device *self, void *aux); 136 int mskc_detach(struct device *, int); 137 int mskc_activate(struct device *, int); 138 void mskc_reset(struct sk_softc *); 139 int msk_probe(struct device *, void *, void *); 140 void msk_attach(struct device *, struct device *self, void *aux); 141 int msk_detach(struct device *, int); 142 int msk_activate(struct device *, int); 143 void msk_reset(struct sk_if_softc *); 144 int mskcprint(void *, const char *); 145 int msk_intr(void *); 146 void msk_intr_yukon(struct sk_if_softc *); 147 static __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 148 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 149 void msk_txeof(struct sk_if_softc *); 150 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 151 void msk_start(struct ifnet *); 152 int msk_ioctl(struct ifnet *, u_long, caddr_t); 153 void msk_init(void *); 154 void msk_init_yukon(struct sk_if_softc *); 155 void msk_stop(struct sk_if_softc *, int); 156 void msk_watchdog(struct ifnet *); 157 int msk_ifmedia_upd(struct ifnet *); 158 void msk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 159 int msk_newbuf(struct sk_if_softc *); 160 int msk_init_rx_ring(struct sk_if_softc *); 161 int msk_init_tx_ring(struct sk_if_softc *); 162 void msk_fill_rx_ring(struct sk_if_softc *); 163 164 int msk_miibus_readreg(struct device *, int, int); 165 void msk_miibus_writereg(struct device *, int, int, int); 166 void msk_miibus_statchg(struct device *); 167 168 void msk_setmulti(struct sk_if_softc *); 169 void msk_setpromisc(struct sk_if_softc *); 170 void msk_tick(void *); 171 172 #ifdef MSK_DEBUG 173 #define DPRINTF(x) if (mskdebug) printf x 174 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 175 int mskdebug = 0; 176 177 void msk_dump_txdesc(struct msk_tx_desc *, int); 178 void msk_dump_mbuf(struct mbuf *); 179 void msk_dump_bytes(const char *, int); 180 #else 181 #define DPRINTF(x) 182 #define DPRINTFN(n,x) 183 #endif 184 185 /* supported device vendors */ 186 const struct pci_matchid mskc_devices[] = { 187 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 188 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 189 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 190 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8021CU }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8021X }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8022CU }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8022X }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 200 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 201 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 202 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 203 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 204 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 205 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 206 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 207 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 208 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 209 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 210 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 211 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 212 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8061CU }, 213 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8061X }, 214 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8062CU }, 215 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8062X }, 216 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 217 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 218 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 219 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 220 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 221 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 222 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 223 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 224 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 225 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Exx }, 226 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Sxx } 227 }; 228 229 static inline u_int32_t 230 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 231 { 232 return CSR_READ_4(sc, reg); 233 } 234 235 static inline u_int16_t 236 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 237 { 238 return CSR_READ_2(sc, reg); 239 } 240 241 static inline u_int8_t 242 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 243 { 244 return CSR_READ_1(sc, reg); 245 } 246 247 static inline void 248 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 249 { 250 CSR_WRITE_4(sc, reg, x); 251 } 252 253 static inline void 254 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 255 { 256 CSR_WRITE_2(sc, reg, x); 257 } 258 259 static inline void 260 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 261 { 262 CSR_WRITE_1(sc, reg, x); 263 } 264 265 int 266 msk_miibus_readreg(struct device *dev, int phy, int reg) 267 { 268 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 269 u_int16_t val; 270 int i; 271 272 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 273 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 274 275 for (i = 0; i < SK_TIMEOUT; i++) { 276 DELAY(1); 277 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 278 if (val & YU_SMICR_READ_VALID) 279 break; 280 } 281 282 if (i == SK_TIMEOUT) { 283 printf("%s: phy failed to come ready\n", 284 sc_if->sk_dev.dv_xname); 285 return (0); 286 } 287 288 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 289 SK_TIMEOUT)); 290 291 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 292 293 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 294 phy, reg, val)); 295 296 return (val); 297 } 298 299 void 300 msk_miibus_writereg(struct device *dev, int phy, int reg, int val) 301 { 302 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 303 int i; 304 305 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 306 phy, reg, val)); 307 308 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 309 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 310 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 311 312 for (i = 0; i < SK_TIMEOUT; i++) { 313 DELAY(1); 314 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 315 break; 316 } 317 318 if (i == SK_TIMEOUT) 319 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 320 } 321 322 void 323 msk_miibus_statchg(struct device *dev) 324 { 325 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 326 struct mii_data *mii = &sc_if->sk_mii; 327 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 328 int gpcr; 329 330 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 331 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 332 333 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 334 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 335 /* Set speed. */ 336 gpcr |= YU_GPCR_SPEED_DIS; 337 switch (IFM_SUBTYPE(mii->mii_media_active)) { 338 case IFM_1000_SX: 339 case IFM_1000_LX: 340 case IFM_1000_CX: 341 case IFM_1000_T: 342 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 343 break; 344 case IFM_100_TX: 345 gpcr |= YU_GPCR_SPEED; 346 break; 347 } 348 349 /* Set duplex. */ 350 gpcr |= YU_GPCR_DPLX_DIS; 351 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 352 gpcr |= YU_GPCR_DUPLEX; 353 354 /* Disable flow control. */ 355 gpcr |= YU_GPCR_FCTL_DIS; 356 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 357 } 358 359 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 360 361 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 362 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 363 } 364 365 void 366 msk_setmulti(struct sk_if_softc *sc_if) 367 { 368 struct ifnet *ifp= &sc_if->arpcom.ac_if; 369 u_int32_t hashes[2] = { 0, 0 }; 370 int h; 371 struct arpcom *ac = &sc_if->arpcom; 372 struct ether_multi *enm; 373 struct ether_multistep step; 374 375 /* First, zot all the existing filters. */ 376 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 377 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 378 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 379 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 380 381 382 /* Now program new ones. */ 383 allmulti: 384 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 385 hashes[0] = 0xFFFFFFFF; 386 hashes[1] = 0xFFFFFFFF; 387 } else { 388 /* First find the tail of the list. */ 389 ETHER_FIRST_MULTI(step, ac, enm); 390 while (enm != NULL) { 391 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 392 ETHER_ADDR_LEN)) { 393 ifp->if_flags |= IFF_ALLMULTI; 394 goto allmulti; 395 } 396 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 397 ((1 << SK_HASH_BITS) - 1); 398 if (h < 32) 399 hashes[0] |= (1 << h); 400 else 401 hashes[1] |= (1 << (h - 32)); 402 403 ETHER_NEXT_MULTI(step, enm); 404 } 405 } 406 407 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 408 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 409 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 410 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 411 } 412 413 void 414 msk_setpromisc(struct sk_if_softc *sc_if) 415 { 416 struct ifnet *ifp = &sc_if->arpcom.ac_if; 417 418 if (ifp->if_flags & IFF_PROMISC) 419 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 420 YU_RCR_UFLEN | YU_RCR_MUFLEN); 421 else 422 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 423 YU_RCR_UFLEN | YU_RCR_MUFLEN); 424 } 425 426 int 427 msk_init_rx_ring(struct sk_if_softc *sc_if) 428 { 429 struct msk_chain_data *cd = &sc_if->sk_cdata; 430 struct msk_ring_data *rd = sc_if->sk_rdata; 431 int i, nexti; 432 433 bzero(rd->sk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 434 435 for (i = 0; i < MSK_RX_RING_CNT; i++) { 436 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 437 if (i == (MSK_RX_RING_CNT - 1)) 438 nexti = 0; 439 else 440 nexti = i + 1; 441 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 442 } 443 444 sc_if->sk_cdata.sk_rx_prod = 0; 445 sc_if->sk_cdata.sk_rx_cons = 0; 446 sc_if->sk_cdata.sk_rx_cnt = 0; 447 448 msk_fill_rx_ring(sc_if); 449 return (0); 450 } 451 452 int 453 msk_init_tx_ring(struct sk_if_softc *sc_if) 454 { 455 struct sk_softc *sc = sc_if->sk_softc; 456 struct msk_chain_data *cd = &sc_if->sk_cdata; 457 struct msk_ring_data *rd = sc_if->sk_rdata; 458 bus_dmamap_t dmamap; 459 struct sk_txmap_entry *entry; 460 int i, nexti; 461 462 bzero(sc_if->sk_rdata->sk_tx_ring, 463 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 464 465 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 466 for (i = 0; i < MSK_TX_RING_CNT; i++) { 467 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 468 if (i == (MSK_TX_RING_CNT - 1)) 469 nexti = 0; 470 else 471 nexti = i + 1; 472 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 473 474 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 475 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 476 return (ENOBUFS); 477 478 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 479 if (!entry) { 480 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 481 return (ENOBUFS); 482 } 483 entry->dmamap = dmamap; 484 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 485 } 486 487 sc_if->sk_cdata.sk_tx_prod = 0; 488 sc_if->sk_cdata.sk_tx_cons = 0; 489 sc_if->sk_cdata.sk_tx_cnt = 0; 490 491 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 492 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 493 494 return (0); 495 } 496 497 int 498 msk_newbuf(struct sk_if_softc *sc_if) 499 { 500 struct sk_chain *c; 501 struct msk_rx_desc *r; 502 struct mbuf *m; 503 bus_dmamap_t dmamap; 504 int error; 505 int i, head; 506 507 m = MCLGETI(NULL, M_DONTWAIT, &sc_if->arpcom.ac_if, sc_if->sk_pktlen); 508 if (!m) 509 return (ENOBUFS); 510 m->m_len = m->m_pkthdr.len = sc_if->sk_pktlen; 511 m_adj(m, ETHER_ALIGN); 512 513 dmamap = sc_if->sk_cdata.sk_rx_map[sc_if->sk_cdata.sk_rx_prod]; 514 515 error = bus_dmamap_load_mbuf(sc_if->sk_softc->sc_dmatag, dmamap, m, 516 BUS_DMA_READ|BUS_DMA_NOWAIT); 517 if (error) { 518 m_freem(m); 519 return (ENOBUFS); 520 } 521 522 if (dmamap->dm_nsegs > (MSK_RX_RING_CNT - sc_if->sk_cdata.sk_rx_cnt)) { 523 bus_dmamap_unload(sc_if->sk_softc->sc_dmatag, dmamap); 524 m_freem(m); 525 return (ENOBUFS); 526 } 527 528 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 529 dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 530 531 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 532 head = sc_if->sk_cdata.sk_rx_prod; 533 r = c->sk_le; 534 c->sk_mbuf = m; 535 536 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr); 537 r->sk_len = htole16(dmamap->dm_segs[0].ds_len); 538 r->sk_ctl = 0; 539 540 MSK_CDRXSYNC(sc_if, head, BUS_DMASYNC_PREWRITE); 541 542 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 543 sc_if->sk_cdata.sk_rx_cnt++; 544 545 for (i = 1; i < dmamap->dm_nsegs; i++) { 546 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 547 r = c->sk_le; 548 c->sk_mbuf = NULL; 549 550 r->sk_addr = htole32(dmamap->dm_segs[i].ds_addr); 551 r->sk_len = htole16(dmamap->dm_segs[i].ds_len); 552 r->sk_ctl = 0; 553 554 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 555 BUS_DMASYNC_PREWRITE); 556 557 r->sk_opcode = SK_Y2_RXOPC_BUFFER | SK_Y2_RXOPC_OWN; 558 559 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 560 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 561 562 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 563 sc_if->sk_cdata.sk_rx_cnt++; 564 } 565 566 c = &sc_if->sk_cdata.sk_rx_chain[head]; 567 r = c->sk_le; 568 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 569 570 MSK_CDRXSYNC(sc_if, head, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 571 572 return (0); 573 } 574 575 /* 576 * Set media options. 577 */ 578 int 579 msk_ifmedia_upd(struct ifnet *ifp) 580 { 581 struct sk_if_softc *sc_if = ifp->if_softc; 582 583 mii_mediachg(&sc_if->sk_mii); 584 return (0); 585 } 586 587 /* 588 * Report current media status. 589 */ 590 void 591 msk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 592 { 593 struct sk_if_softc *sc_if = ifp->if_softc; 594 595 mii_pollstat(&sc_if->sk_mii); 596 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 597 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 598 } 599 600 int 601 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 602 { 603 struct sk_if_softc *sc_if = ifp->if_softc; 604 struct ifaddr *ifa = (struct ifaddr *) data; 605 struct ifreq *ifr = (struct ifreq *) data; 606 struct mii_data *mii; 607 int s, error = 0; 608 609 s = splnet(); 610 611 switch(command) { 612 case SIOCSIFADDR: 613 ifp->if_flags |= IFF_UP; 614 if (!(ifp->if_flags & IFF_RUNNING)) 615 msk_init(sc_if); 616 #ifdef INET 617 if (ifa->ifa_addr->sa_family == AF_INET) 618 arp_ifinit(&sc_if->arpcom, ifa); 619 #endif /* INET */ 620 break; 621 622 case SIOCSIFFLAGS: 623 if (ifp->if_flags & IFF_UP) { 624 if (ifp->if_flags & IFF_RUNNING && 625 (sc_if->sk_if_flags ^ ifp->if_flags) & 626 IFF_PROMISC) { 627 msk_setpromisc(sc_if); 628 msk_setmulti(sc_if); 629 } else { 630 if (!(ifp->if_flags & IFF_RUNNING)) 631 msk_init(sc_if); 632 } 633 } else { 634 if (ifp->if_flags & IFF_RUNNING) 635 msk_stop(sc_if, 0); 636 } 637 sc_if->sk_if_flags = ifp->if_flags; 638 break; 639 640 case SIOCGIFMEDIA: 641 case SIOCSIFMEDIA: 642 mii = &sc_if->sk_mii; 643 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 644 break; 645 646 default: 647 error = ether_ioctl(ifp, &sc_if->arpcom, command, data); 648 } 649 650 if (error == ENETRESET) { 651 if (ifp->if_flags & IFF_RUNNING) 652 msk_setmulti(sc_if); 653 error = 0; 654 } 655 656 splx(s); 657 return (error); 658 } 659 660 /* 661 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 662 * IDs against our list and return a device name if we find a match. 663 */ 664 int 665 mskc_probe(struct device *parent, void *match, void *aux) 666 { 667 return (pci_matchbyid((struct pci_attach_args *)aux, mskc_devices, 668 nitems(mskc_devices))); 669 } 670 671 /* 672 * Force the GEnesis into reset, then bring it out of reset. 673 */ 674 void 675 mskc_reset(struct sk_softc *sc) 676 { 677 u_int32_t imtimer_ticks, reg1; 678 int reg; 679 680 DPRINTFN(2, ("mskc_reset\n")); 681 682 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 683 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 684 685 DELAY(1000); 686 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 687 DELAY(2); 688 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 689 690 sk_win_write_1(sc, SK_TESTCTL1, 2); 691 692 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 693 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 694 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 695 else 696 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 697 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 698 699 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 700 sk_win_write_1(sc, SK_Y2_CLKGATE, 701 SK_Y2_CLKGATE_LINK1_GATE_DIS | 702 SK_Y2_CLKGATE_LINK2_GATE_DIS | 703 SK_Y2_CLKGATE_LINK1_CORE_DIS | 704 SK_Y2_CLKGATE_LINK2_CORE_DIS | 705 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 706 else 707 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 708 709 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 710 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 711 DELAY(1000); 712 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 713 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 714 715 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 716 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 717 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 718 } 719 720 sk_win_write_1(sc, SK_TESTCTL1, 1); 721 722 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 723 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 724 CSR_READ_2(sc, SK_LINK_CTRL))); 725 726 /* Disable ASF */ 727 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 728 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 729 730 /* Clear I2C IRQ noise */ 731 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 732 733 /* Disable hardware timer */ 734 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 735 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 736 737 /* Disable descriptor polling */ 738 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 739 740 /* Disable time stamps */ 741 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 742 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 743 744 /* Enable RAM interface */ 745 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 746 for (reg = SK_TO0;reg <= SK_TO11; reg++) 747 sk_win_write_1(sc, reg, 36); 748 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 749 for (reg = SK_TO0;reg <= SK_TO11; reg++) 750 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 751 752 /* 753 * Configure interrupt moderation. The moderation timer 754 * defers interrupts specified in the interrupt moderation 755 * timer mask based on the timeout specified in the interrupt 756 * moderation timer init register. Each bit in the timer 757 * register represents one tick, so to specify a timeout in 758 * microseconds, we have to multiply by the correct number of 759 * ticks-per-microsecond. 760 */ 761 switch (sc->sk_type) { 762 case SK_YUKON_EC: 763 case SK_YUKON_XL: 764 case SK_YUKON_FE: 765 case SK_YUKON_OPTIMA: 766 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 767 break; 768 default: 769 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 770 } 771 772 /* Reset status ring. */ 773 bzero(sc->sk_status_ring, 774 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 775 sc->sk_status_idx = 0; 776 777 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 778 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 779 780 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 781 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 782 sc->sk_status_map->dm_segs[0].ds_addr); 783 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 784 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 785 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 10); 786 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 16); 787 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 16); 788 789 #if 0 790 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 791 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 792 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(20)); 793 #else 794 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(4)); 795 #endif 796 797 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 798 799 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 800 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 801 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 802 } 803 804 int 805 msk_probe(struct device *parent, void *match, void *aux) 806 { 807 struct skc_attach_args *sa = aux; 808 809 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 810 return (0); 811 812 switch (sa->skc_type) { 813 case SK_YUKON_XL: 814 case SK_YUKON_EC_U: 815 case SK_YUKON_EX: 816 case SK_YUKON_EC: 817 case SK_YUKON_FE: 818 case SK_YUKON_FE_P: 819 case SK_YUKON_SUPR: 820 case SK_YUKON_ULTRA2: 821 case SK_YUKON_OPTIMA: 822 return (1); 823 } 824 825 return (0); 826 } 827 828 void 829 msk_reset(struct sk_if_softc *sc_if) 830 { 831 /* GMAC and GPHY Reset */ 832 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 833 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 834 DELAY(1000); 835 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 836 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 837 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 838 } 839 840 /* 841 * Each XMAC chip is attached as a separate logical IP interface. 842 * Single port cards will have only one logical interface of course. 843 */ 844 void 845 msk_attach(struct device *parent, struct device *self, void *aux) 846 { 847 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 848 struct sk_softc *sc = (struct sk_softc *)parent; 849 struct skc_attach_args *sa = aux; 850 struct ifnet *ifp; 851 caddr_t kva; 852 int i; 853 u_int32_t chunk; 854 int mii_flags; 855 int error; 856 857 sc_if->sk_port = sa->skc_port; 858 sc_if->sk_softc = sc; 859 sc->sk_if[sa->skc_port] = sc_if; 860 861 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 862 863 /* 864 * Get station address for this interface. Note that 865 * dual port cards actually come with three station 866 * addresses: one for each port, plus an extra. The 867 * extra one is used by the SysKonnect driver software 868 * as a 'virtual' station address for when both ports 869 * are operating in failover mode. Currently we don't 870 * use this extra address. 871 */ 872 for (i = 0; i < ETHER_ADDR_LEN; i++) 873 sc_if->arpcom.ac_enaddr[i] = 874 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 875 876 printf(": address %s\n", 877 ether_sprintf(sc_if->arpcom.ac_enaddr)); 878 879 /* 880 * Set up RAM buffer addresses. The Yukon2 has a small amount 881 * of SRAM on it, somewhere between 4K and 48K. We need to 882 * divide this up between the transmitter and receiver. We 883 * give the receiver 2/3 of the memory (rounded down), and the 884 * transmitter whatever remains. 885 */ 886 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 887 sc_if->sk_rx_ramstart = 0; 888 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 889 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 890 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 891 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 892 893 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 894 " tx_ramstart=%#x tx_ramend=%#x\n", 895 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 896 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 897 898 /* Allocate the descriptor queues. */ 899 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 900 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 901 BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 902 printf(": can't alloc rx buffers\n"); 903 goto fail; 904 } 905 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 906 sc_if->sk_ring_nseg, 907 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 908 printf(": can't map dma buffers (%lu bytes)\n", 909 (ulong)sizeof(struct msk_ring_data)); 910 goto fail_1; 911 } 912 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 913 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 914 &sc_if->sk_ring_map)) { 915 printf(": can't create dma map\n"); 916 goto fail_2; 917 } 918 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 919 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 920 printf(": can't load dma map\n"); 921 goto fail_3; 922 } 923 sc_if->sk_rdata = (struct msk_ring_data *)kva; 924 925 if (sc->sk_type != SK_YUKON_FE && 926 sc->sk_type != SK_YUKON_FE_P) 927 sc_if->sk_pktlen = SK_JLEN; 928 else 929 sc_if->sk_pktlen = MCLBYTES; 930 931 for (i = 0; i < MSK_RX_RING_CNT; i++) { 932 if ((error = bus_dmamap_create(sc->sc_dmatag, 933 sc_if->sk_pktlen, 4, sc_if->sk_pktlen, 934 0, 0, &sc_if->sk_cdata.sk_rx_map[i])) != 0) { 935 printf("\n%s: unable to create rx DMA map %d, " 936 "error = %d\n", sc->sk_dev.dv_xname, i, error); 937 goto fail_4; 938 } 939 } 940 941 ifp = &sc_if->arpcom.ac_if; 942 ifp->if_softc = sc_if; 943 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 944 ifp->if_ioctl = msk_ioctl; 945 ifp->if_start = msk_start; 946 ifp->if_watchdog = msk_watchdog; 947 ifp->if_baudrate = 1000000000; 948 if (sc->sk_type != SK_YUKON_FE && 949 sc->sk_type != SK_YUKON_FE_P) 950 ifp->if_hardmtu = SK_JUMBO_MTU; 951 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 952 IFQ_SET_READY(&ifp->if_snd); 953 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 954 955 ifp->if_capabilities = IFCAP_VLAN_MTU; 956 957 msk_reset(sc_if); 958 959 /* 960 * Do miibus setup. 961 */ 962 msk_init_yukon(sc_if); 963 964 DPRINTFN(2, ("msk_attach: 1\n")); 965 966 sc_if->sk_mii.mii_ifp = ifp; 967 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 968 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 969 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 970 971 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 972 msk_ifmedia_upd, msk_ifmedia_sts); 973 mii_flags = MIIF_DOPAUSE; 974 if (sc->sk_fibertype) 975 mii_flags |= MIIF_HAVEFIBER; 976 mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0, 977 MII_OFFSET_ANY, mii_flags); 978 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 979 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 980 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 981 0, NULL); 982 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 983 } else 984 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 985 986 timeout_set(&sc_if->sk_tick_ch, msk_tick, sc_if); 987 988 /* 989 * Call MI attach routines. 990 */ 991 if_attach(ifp); 992 ether_ifattach(ifp); 993 m_clsetwms(ifp, sc_if->sk_pktlen, 2, MSK_RX_RING_CNT); 994 995 DPRINTFN(2, ("msk_attach: end\n")); 996 return; 997 998 fail_4: 999 for (i = 0; i < MSK_RX_RING_CNT; i++) { 1000 if (sc_if->sk_cdata.sk_rx_map[i] != NULL) 1001 bus_dmamap_destroy(sc->sc_dmatag, 1002 sc_if->sk_cdata.sk_rx_map[i]); 1003 } 1004 1005 fail_3: 1006 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1007 fail_2: 1008 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1009 fail_1: 1010 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1011 fail: 1012 sc->sk_if[sa->skc_port] = NULL; 1013 } 1014 1015 int 1016 msk_detach(struct device *self, int flags) 1017 { 1018 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 1019 struct sk_softc *sc = sc_if->sk_softc; 1020 struct ifnet *ifp= &sc_if->arpcom.ac_if; 1021 1022 if (sc->sk_if[sc_if->sk_port] == NULL) 1023 return (0); 1024 1025 msk_stop(sc_if, 1); 1026 1027 /* Detach any PHYs we might have. */ 1028 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1029 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1030 1031 /* Delete any remaining media. */ 1032 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1033 1034 ether_ifdetach(ifp); 1035 if_detach(ifp); 1036 1037 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc_if->sk_rdata, 1038 sizeof(struct msk_ring_data)); 1039 bus_dmamem_free(sc->sc_dmatag, 1040 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1041 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1042 sc->sk_if[sc_if->sk_port] = NULL; 1043 1044 return (0); 1045 } 1046 1047 int 1048 msk_activate(struct device *self, int act) 1049 { 1050 struct sk_if_softc *sc_if = (void *)self; 1051 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1052 int rv = 0; 1053 1054 switch (act) { 1055 case DVACT_QUIESCE: 1056 rv = config_activate_children(self, act); 1057 break; 1058 case DVACT_SUSPEND: 1059 rv = config_activate_children(self, act); 1060 break; 1061 case DVACT_RESUME: 1062 msk_reset(sc_if); 1063 rv = config_activate_children(self, act); 1064 if (ifp->if_flags & IFF_RUNNING) 1065 msk_init(sc_if); 1066 break; 1067 } 1068 return (rv); 1069 } 1070 1071 int 1072 mskcprint(void *aux, const char *pnp) 1073 { 1074 struct skc_attach_args *sa = aux; 1075 1076 if (pnp) 1077 printf("msk port %c at %s", 1078 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1079 else 1080 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1081 return (UNCONF); 1082 } 1083 1084 /* 1085 * Attach the interface. Allocate softc structures, do ifmedia 1086 * setup and ethernet/BPF attach. 1087 */ 1088 void 1089 mskc_attach(struct device *parent, struct device *self, void *aux) 1090 { 1091 struct sk_softc *sc = (struct sk_softc *)self; 1092 struct pci_attach_args *pa = aux; 1093 struct skc_attach_args skca; 1094 pci_chipset_tag_t pc = pa->pa_pc; 1095 pcireg_t command, memtype; 1096 pci_intr_handle_t ih; 1097 const char *intrstr = NULL; 1098 u_int8_t hw, pmd; 1099 char *revstr = NULL; 1100 caddr_t kva; 1101 1102 DPRINTFN(2, ("begin mskc_attach\n")); 1103 1104 /* 1105 * Handle power management nonsense. 1106 */ 1107 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1108 1109 if (command == 0x01) { 1110 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1111 if (command & SK_PSTATE_MASK) { 1112 u_int32_t iobase, membase, irq; 1113 1114 /* Save important PCI config data. */ 1115 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1116 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1117 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1118 1119 /* Reset the power state. */ 1120 printf("%s chip is in D%d power mode " 1121 "-- setting to D0\n", sc->sk_dev.dv_xname, 1122 command & SK_PSTATE_MASK); 1123 command &= 0xFFFFFFFC; 1124 pci_conf_write(pc, pa->pa_tag, 1125 SK_PCI_PWRMGMTCTRL, command); 1126 1127 /* Restore PCI config data. */ 1128 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1129 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1130 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1131 } 1132 } 1133 1134 /* 1135 * Map control/status registers. 1136 */ 1137 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1138 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1139 &sc->sk_bhandle, NULL, &sc->sk_bsize, 0)) { 1140 printf(": can't map mem space\n"); 1141 return; 1142 } 1143 1144 sc->sc_dmatag = pa->pa_dmat; 1145 1146 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1147 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1148 1149 /* bail out here if chip is not recognized */ 1150 if (!(SK_IS_YUKON2(sc))) { 1151 printf(": unknown chip type: %d\n", sc->sk_type); 1152 goto fail_1; 1153 } 1154 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1155 1156 /* Allocate interrupt */ 1157 if (pci_intr_map(pa, &ih)) { 1158 printf(": couldn't map interrupt\n"); 1159 goto fail_1; 1160 } 1161 1162 intrstr = pci_intr_string(pc, ih); 1163 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc, 1164 self->dv_xname); 1165 if (sc->sk_intrhand == NULL) { 1166 printf(": couldn't establish interrupt"); 1167 if (intrstr != NULL) 1168 printf(" at %s", intrstr); 1169 printf("\n"); 1170 goto fail_1; 1171 } 1172 sc->sk_pc = pc; 1173 1174 if (bus_dmamem_alloc(sc->sc_dmatag, 1175 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1176 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1177 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, 1178 BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 1179 printf(": can't alloc status buffers\n"); 1180 goto fail_2; 1181 } 1182 1183 if (bus_dmamem_map(sc->sc_dmatag, 1184 &sc->sk_status_seg, sc->sk_status_nseg, 1185 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1186 &kva, BUS_DMA_NOWAIT)) { 1187 printf(": can't map dma buffers (%lu bytes)\n", 1188 (ulong)(MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc))); 1189 goto fail_3; 1190 } 1191 if (bus_dmamap_create(sc->sc_dmatag, 1192 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1193 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1194 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1195 printf(": can't create dma map\n"); 1196 goto fail_4; 1197 } 1198 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1199 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1200 NULL, BUS_DMA_NOWAIT)) { 1201 printf(": can't load dma map\n"); 1202 goto fail_5; 1203 } 1204 sc->sk_status_ring = (struct msk_status_desc *)kva; 1205 1206 /* Reset the adapter. */ 1207 mskc_reset(sc); 1208 1209 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1210 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1211 1212 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1213 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1214 sc->sk_fibertype = 1; 1215 1216 switch (sc->sk_type) { 1217 case SK_YUKON_XL: 1218 sc->sk_name = "Yukon-2 XL"; 1219 break; 1220 case SK_YUKON_EC_U: 1221 sc->sk_name = "Yukon-2 EC Ultra"; 1222 break; 1223 case SK_YUKON_EX: 1224 sc->sk_name = "Yukon-2 Extreme"; 1225 break; 1226 case SK_YUKON_EC: 1227 sc->sk_name = "Yukon-2 EC"; 1228 break; 1229 case SK_YUKON_FE: 1230 sc->sk_name = "Yukon-2 FE"; 1231 break; 1232 case SK_YUKON_FE_P: 1233 sc->sk_name = "Yukon-2 FE+"; 1234 break; 1235 case SK_YUKON_SUPR: 1236 sc->sk_name = "Yukon-2 Supreme"; 1237 break; 1238 case SK_YUKON_ULTRA2: 1239 sc->sk_name = "Yukon-2 Ultra2"; 1240 break; 1241 case SK_YUKON_OPTIMA: 1242 sc->sk_name = "Yukon-2 Optima"; 1243 break; 1244 default: 1245 sc->sk_name = "Yukon (Unknown)"; 1246 } 1247 1248 if (sc->sk_type == SK_YUKON_XL) { 1249 switch (sc->sk_rev) { 1250 case SK_YUKON_XL_REV_A0: 1251 revstr = "A0"; 1252 break; 1253 case SK_YUKON_XL_REV_A1: 1254 revstr = "A1"; 1255 break; 1256 case SK_YUKON_XL_REV_A2: 1257 revstr = "A2"; 1258 break; 1259 case SK_YUKON_XL_REV_A3: 1260 revstr = "A3"; 1261 break; 1262 default: 1263 ; 1264 } 1265 } 1266 1267 if (sc->sk_type == SK_YUKON_EC) { 1268 switch (sc->sk_rev) { 1269 case SK_YUKON_EC_REV_A1: 1270 revstr = "A1"; 1271 break; 1272 case SK_YUKON_EC_REV_A2: 1273 revstr = "A2"; 1274 break; 1275 case SK_YUKON_EC_REV_A3: 1276 revstr = "A3"; 1277 break; 1278 default: 1279 ; 1280 } 1281 } 1282 1283 if (sc->sk_type == SK_YUKON_EC_U) { 1284 switch (sc->sk_rev) { 1285 case SK_YUKON_EC_U_REV_A0: 1286 revstr = "A0"; 1287 break; 1288 case SK_YUKON_EC_U_REV_A1: 1289 revstr = "A1"; 1290 break; 1291 case SK_YUKON_EC_U_REV_B0: 1292 revstr = "B0"; 1293 break; 1294 default: 1295 ; 1296 } 1297 } 1298 1299 if (sc->sk_type == SK_YUKON_FE) { 1300 switch (sc->sk_rev) { 1301 case SK_YUKON_FE_REV_A1: 1302 revstr = "A1"; 1303 break; 1304 case SK_YUKON_FE_REV_A2: 1305 revstr = "A2"; 1306 break; 1307 default: 1308 ; 1309 } 1310 } 1311 1312 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1313 revstr = "A0"; 1314 1315 if (sc->sk_type == SK_YUKON_EX) { 1316 switch (sc->sk_rev) { 1317 case SK_YUKON_EX_REV_A0: 1318 revstr = "A0"; 1319 break; 1320 case SK_YUKON_EX_REV_B0: 1321 revstr = "B0"; 1322 break; 1323 default: 1324 ; 1325 } 1326 } 1327 1328 if (sc->sk_type == SK_YUKON_SUPR && sc->sk_rev == SK_YUKON_SUPR_REV_A0) 1329 revstr = "A0"; 1330 1331 1332 /* Announce the product name. */ 1333 printf(", %s", sc->sk_name); 1334 if (revstr != NULL) 1335 printf(" rev. %s", revstr); 1336 printf(" (0x%x): %s\n", sc->sk_rev, intrstr); 1337 1338 sc->sk_macs = 1; 1339 1340 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1341 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1342 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1343 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1344 sc->sk_macs++; 1345 } 1346 1347 skca.skc_port = SK_PORT_A; 1348 skca.skc_type = sc->sk_type; 1349 skca.skc_rev = sc->sk_rev; 1350 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1351 1352 if (sc->sk_macs > 1) { 1353 skca.skc_port = SK_PORT_B; 1354 skca.skc_type = sc->sk_type; 1355 skca.skc_rev = sc->sk_rev; 1356 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1357 } 1358 1359 /* Turn on the 'driver is loaded' LED. */ 1360 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1361 1362 return; 1363 1364 fail_4: 1365 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sk_status_ring, 1366 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1367 fail_3: 1368 bus_dmamem_free(sc->sc_dmatag, 1369 &sc->sk_status_seg, sc->sk_status_nseg); 1370 sc->sk_status_nseg = 0; 1371 fail_5: 1372 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1373 fail_2: 1374 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1375 sc->sk_intrhand = NULL; 1376 fail_1: 1377 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1378 sc->sk_bsize = 0; 1379 } 1380 1381 int 1382 mskc_detach(struct device *self, int flags) 1383 { 1384 struct sk_softc *sc = (struct sk_softc *)self; 1385 int rv; 1386 1387 if (sc->sk_intrhand) 1388 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1389 1390 rv = config_detach_children(self, flags); 1391 if (rv != 0) 1392 return (rv); 1393 1394 if (sc->sk_status_nseg > 0) { 1395 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1396 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sk_status_ring, 1397 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1398 bus_dmamem_free(sc->sc_dmatag, 1399 &sc->sk_status_seg, sc->sk_status_nseg); 1400 } 1401 1402 if (sc->sk_bsize > 0) 1403 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1404 1405 return(0); 1406 } 1407 1408 int 1409 mskc_activate(struct device *self, int act) 1410 { 1411 struct sk_softc *sc = (void *)self; 1412 int rv = 0; 1413 1414 switch (act) { 1415 case DVACT_QUIESCE: 1416 rv = config_activate_children(self, act); 1417 break; 1418 case DVACT_SUSPEND: 1419 rv = config_activate_children(self, act); 1420 break; 1421 case DVACT_RESUME: 1422 mskc_reset(sc); 1423 rv = config_activate_children(self, act); 1424 break; 1425 } 1426 return (rv); 1427 } 1428 1429 int 1430 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1431 { 1432 struct sk_softc *sc = sc_if->sk_softc; 1433 struct msk_tx_desc *f = NULL; 1434 u_int32_t frag, cur; 1435 int i; 1436 struct sk_txmap_entry *entry; 1437 bus_dmamap_t txmap; 1438 1439 DPRINTFN(2, ("msk_encap\n")); 1440 1441 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1442 if (entry == NULL) { 1443 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1444 return (ENOBUFS); 1445 } 1446 txmap = entry->dmamap; 1447 1448 cur = frag = *txidx; 1449 1450 #ifdef MSK_DEBUG 1451 if (mskdebug >= 2) 1452 msk_dump_mbuf(m_head); 1453 #endif 1454 1455 /* 1456 * Start packing the mbufs in this chain into 1457 * the fragment pointers. Stop when we run out 1458 * of fragments or hit the end of the mbuf chain. 1459 */ 1460 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1461 BUS_DMA_NOWAIT)) { 1462 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1463 return (ENOBUFS); 1464 } 1465 1466 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1467 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1468 bus_dmamap_unload(sc->sc_dmatag, txmap); 1469 return (ENOBUFS); 1470 } 1471 1472 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1473 1474 /* Sync the DMA map. */ 1475 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1476 BUS_DMASYNC_PREWRITE); 1477 1478 for (i = 0; i < txmap->dm_nsegs; i++) { 1479 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1480 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1481 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1482 f->sk_ctl = 0; 1483 if (i == 0) 1484 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1485 else 1486 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1487 cur = frag; 1488 SK_INC(frag, MSK_TX_RING_CNT); 1489 } 1490 1491 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1492 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1493 1494 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1495 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1496 1497 /* Sync descriptors before handing to chip */ 1498 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1499 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1500 1501 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1502 1503 /* Sync first descriptor to hand it off */ 1504 MSK_CDTXSYNC(sc_if, *txidx, 1, 1505 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1506 1507 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1508 1509 #ifdef MSK_DEBUG 1510 if (mskdebug >= 2) { 1511 struct msk_tx_desc *le; 1512 u_int32_t idx; 1513 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1514 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1515 msk_dump_txdesc(le, idx); 1516 } 1517 } 1518 #endif 1519 1520 *txidx = frag; 1521 1522 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1523 1524 return (0); 1525 } 1526 1527 void 1528 msk_start(struct ifnet *ifp) 1529 { 1530 struct sk_if_softc *sc_if = ifp->if_softc; 1531 struct mbuf *m_head = NULL; 1532 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1533 int pkts = 0; 1534 1535 DPRINTFN(2, ("msk_start\n")); 1536 1537 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1538 IFQ_POLL(&ifp->if_snd, m_head); 1539 if (m_head == NULL) 1540 break; 1541 1542 /* 1543 * Pack the data into the transmit ring. If we 1544 * don't have room, set the OACTIVE flag and wait 1545 * for the NIC to drain the ring. 1546 */ 1547 if (msk_encap(sc_if, m_head, &idx)) { 1548 ifp->if_flags |= IFF_OACTIVE; 1549 break; 1550 } 1551 1552 /* now we are committed to transmit the packet */ 1553 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1554 pkts++; 1555 1556 /* 1557 * If there's a BPF listener, bounce a copy of this frame 1558 * to him. 1559 */ 1560 #if NBPFILTER > 0 1561 if (ifp->if_bpf) 1562 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1563 #endif 1564 } 1565 if (pkts == 0) 1566 return; 1567 1568 /* Transmit */ 1569 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1570 sc_if->sk_cdata.sk_tx_prod = idx; 1571 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1572 1573 /* Set a timeout in case the chip goes out to lunch. */ 1574 ifp->if_timer = 5; 1575 } 1576 } 1577 1578 void 1579 msk_watchdog(struct ifnet *ifp) 1580 { 1581 struct sk_if_softc *sc_if = ifp->if_softc; 1582 1583 /* 1584 * Reclaim first as there is a possibility of losing Tx completion 1585 * interrupts. 1586 */ 1587 msk_txeof(sc_if); 1588 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1589 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1590 1591 ifp->if_oerrors++; 1592 1593 /* XXX Resets both ports; we shouldn't do that. */ 1594 mskc_reset(sc_if->sk_softc); 1595 msk_reset(sc_if); 1596 msk_init(sc_if); 1597 } 1598 } 1599 1600 static __inline int 1601 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1602 { 1603 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1604 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1605 YU_RXSTAT_JABBER)) != 0 || 1606 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1607 YU_RXSTAT_BYTES(stat) != len) 1608 return (0); 1609 1610 return (1); 1611 } 1612 1613 void 1614 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1615 { 1616 struct sk_softc *sc = sc_if->sk_softc; 1617 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1618 struct mbuf *m; 1619 struct sk_chain *cur_rx; 1620 int i, cur, total_len = len; 1621 bus_dmamap_t dmamap; 1622 1623 DPRINTFN(2, ("msk_rxeof\n")); 1624 1625 cur = sc_if->sk_cdata.sk_rx_cons; 1626 1627 /* Sync the descriptor */ 1628 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1629 1630 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1631 if (cur_rx->sk_mbuf == NULL) 1632 return; 1633 1634 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1635 for (i = 0; i < dmamap->dm_nsegs; i++) { 1636 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1637 sc_if->sk_cdata.sk_rx_cnt--; 1638 } 1639 1640 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1641 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1642 bus_dmamap_unload(sc_if->sk_softc->sc_dmatag, dmamap); 1643 1644 m = cur_rx->sk_mbuf; 1645 cur_rx->sk_mbuf = NULL; 1646 1647 if (total_len < SK_MIN_FRAMELEN || 1648 total_len > SK_JUMBO_FRAMELEN || 1649 msk_rxvalid(sc, rxstat, total_len) == 0) { 1650 ifp->if_ierrors++; 1651 m_freem(m); 1652 return; 1653 } 1654 1655 m->m_pkthdr.rcvif = ifp; 1656 m->m_pkthdr.len = m->m_len = total_len; 1657 1658 ifp->if_ipackets++; 1659 1660 #if NBPFILTER > 0 1661 if (ifp->if_bpf) 1662 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1663 #endif 1664 1665 /* pass it on. */ 1666 ether_input_mbuf(ifp, m); 1667 } 1668 1669 void 1670 msk_txeof(struct sk_if_softc *sc_if) 1671 { 1672 struct sk_softc *sc = sc_if->sk_softc; 1673 struct msk_tx_desc *cur_tx; 1674 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1675 u_int32_t idx, reg, sk_ctl; 1676 struct sk_txmap_entry *entry; 1677 1678 DPRINTFN(2, ("msk_txeof\n")); 1679 1680 if (sc_if->sk_port == SK_PORT_A) 1681 reg = SK_STAT_BMU_TXA1_RIDX; 1682 else 1683 reg = SK_STAT_BMU_TXA2_RIDX; 1684 1685 /* 1686 * Go through our tx ring and free mbufs for those 1687 * frames that have been sent. 1688 */ 1689 idx = sc_if->sk_cdata.sk_tx_cons; 1690 while (idx != sk_win_read_2(sc, reg)) { 1691 MSK_CDTXSYNC(sc_if, idx, 1, 1692 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1693 1694 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1695 sk_ctl = cur_tx->sk_ctl; 1696 #ifdef MSK_DEBUG 1697 if (mskdebug >= 2) 1698 msk_dump_txdesc(cur_tx, idx); 1699 #endif 1700 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1701 ifp->if_opackets++; 1702 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1703 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1704 1705 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1706 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1707 1708 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1709 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1710 1711 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1712 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1713 link); 1714 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1715 } 1716 sc_if->sk_cdata.sk_tx_cnt--; 1717 SK_INC(idx, MSK_TX_RING_CNT); 1718 } 1719 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1720 1721 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1722 ifp->if_flags &= ~IFF_OACTIVE; 1723 1724 sc_if->sk_cdata.sk_tx_cons = idx; 1725 } 1726 1727 void 1728 msk_fill_rx_ring(struct sk_if_softc *sc_if) 1729 { 1730 while (sc_if->sk_cdata.sk_rx_cnt < MSK_RX_RING_CNT) { 1731 if (msk_newbuf(sc_if) == ENOBUFS) 1732 break; 1733 } 1734 } 1735 1736 void 1737 msk_tick(void *xsc_if) 1738 { 1739 struct sk_if_softc *sc_if = xsc_if; 1740 struct mii_data *mii = &sc_if->sk_mii; 1741 int s; 1742 1743 s = splnet(); 1744 mii_tick(mii); 1745 splx(s); 1746 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1747 } 1748 1749 void 1750 msk_intr_yukon(struct sk_if_softc *sc_if) 1751 { 1752 u_int8_t status; 1753 1754 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1755 /* RX overrun */ 1756 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1757 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1758 SK_RFCTL_RX_FIFO_OVER); 1759 } 1760 /* TX underrun */ 1761 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1762 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1763 SK_TFCTL_TX_FIFO_UNDER); 1764 } 1765 1766 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1767 } 1768 1769 int 1770 msk_intr(void *xsc) 1771 { 1772 struct sk_softc *sc = xsc; 1773 struct sk_if_softc *sc_if; 1774 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1775 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1776 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1777 int claimed = 0, rx[2] = {0, 0}; 1778 u_int32_t status; 1779 struct msk_status_desc *cur_st; 1780 1781 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1782 if (status == 0xffffffff) 1783 return (0); 1784 if (status == 0) { 1785 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1786 return (0); 1787 } 1788 1789 status = CSR_READ_4(sc, SK_ISR); 1790 1791 if (sc_if0 != NULL) 1792 ifp0 = &sc_if0->arpcom.ac_if; 1793 if (sc_if1 != NULL) 1794 ifp1 = &sc_if1->arpcom.ac_if; 1795 1796 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1797 (ifp0->if_flags & IFF_RUNNING)) { 1798 msk_intr_yukon(sc_if0); 1799 } 1800 1801 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1802 (ifp1->if_flags & IFF_RUNNING)) { 1803 msk_intr_yukon(sc_if1); 1804 } 1805 1806 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1807 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1808 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1809 1810 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 1811 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1812 switch (cur_st->sk_opcode) { 1813 case SK_Y2_STOPC_RXSTAT: 1814 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 1815 rx[cur_st->sk_link & 0x01] = 1; 1816 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 1817 letoh32(cur_st->sk_status)); 1818 break; 1819 case SK_Y2_STOPC_TXSTAT: 1820 if (sc_if0) 1821 msk_txeof(sc_if0); 1822 if (sc_if1) 1823 msk_txeof(sc_if1); 1824 break; 1825 default: 1826 printf("opcode=0x%x\n", cur_st->sk_opcode); 1827 break; 1828 } 1829 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1830 1831 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1832 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1833 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1834 } 1835 1836 if (status & SK_Y2_IMR_BMU) { 1837 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1838 claimed = 1; 1839 } 1840 1841 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1842 1843 if (rx[0]) { 1844 msk_fill_rx_ring(sc_if0); 1845 SK_IF_WRITE_2(sc_if0, 0, SK_RXQ1_Y2_PREF_PUTIDX, 1846 sc_if0->sk_cdata.sk_rx_prod); 1847 } 1848 if (rx[1]) { 1849 msk_fill_rx_ring(sc_if1); 1850 SK_IF_WRITE_2(sc_if1, 0, SK_RXQ1_Y2_PREF_PUTIDX, 1851 sc_if1->sk_cdata.sk_rx_prod); 1852 } 1853 1854 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1855 msk_start(ifp0); 1856 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1857 msk_start(ifp1); 1858 1859 return (claimed); 1860 } 1861 1862 void 1863 msk_init_yukon(struct sk_if_softc *sc_if) 1864 { 1865 u_int32_t v; 1866 u_int16_t reg; 1867 struct sk_softc *sc; 1868 int i; 1869 1870 sc = sc_if->sk_softc; 1871 1872 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1873 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1874 1875 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1876 1877 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1878 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1879 1880 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1881 1882 /* unused read of the interrupt source register */ 1883 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1884 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1885 1886 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1887 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1888 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1889 1890 /* MIB Counter Clear Mode set */ 1891 reg |= YU_PAR_MIB_CLR; 1892 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1893 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1894 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1895 1896 /* MIB Counter Clear Mode clear */ 1897 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1898 reg &= ~YU_PAR_MIB_CLR; 1899 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1900 1901 /* receive control reg */ 1902 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1903 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1904 1905 /* transmit parameter register */ 1906 DPRINTFN(6, ("msk_init_yukon: 8\n")); 1907 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 1908 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 1909 1910 /* serial mode register */ 1911 DPRINTFN(6, ("msk_init_yukon: 9\n")); 1912 reg = YU_SMR_DATA_BLIND(0x1c) | 1913 YU_SMR_MFL_VLAN | 1914 YU_SMR_IPG_DATA(0x1e); 1915 1916 if (sc->sk_type != SK_YUKON_FE && 1917 sc->sk_type != SK_YUKON_FE_P) 1918 reg |= YU_SMR_MFL_JUMBO; 1919 1920 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 1921 1922 DPRINTFN(6, ("msk_init_yukon: 10\n")); 1923 /* Setup Yukon's address */ 1924 for (i = 0; i < 3; i++) { 1925 /* Write Source Address 1 (unicast filter) */ 1926 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 1927 sc_if->arpcom.ac_enaddr[i * 2] | 1928 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 1929 } 1930 1931 for (i = 0; i < 3; i++) { 1932 reg = sk_win_read_2(sc_if->sk_softc, 1933 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 1934 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 1935 } 1936 1937 /* Set promiscuous mode */ 1938 msk_setpromisc(sc_if); 1939 1940 /* Set multicast filter */ 1941 DPRINTFN(6, ("msk_init_yukon: 11\n")); 1942 msk_setmulti(sc_if); 1943 1944 /* enable interrupt mask for counter overflows */ 1945 DPRINTFN(6, ("msk_init_yukon: 12\n")); 1946 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 1947 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 1948 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 1949 1950 /* Configure RX MAC FIFO Flush Mask */ 1951 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 1952 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 1953 YU_RXSTAT_JABBER; 1954 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 1955 1956 /* Configure RX MAC FIFO */ 1957 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 1958 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 1959 SK_RFCTL_FIFO_FLUSH_ON); 1960 1961 /* Increase flush threshould to 64 bytes */ 1962 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 1963 SK_RFCTL_FIFO_THRESHOLD + 1); 1964 1965 /* Configure TX MAC FIFO */ 1966 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 1967 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 1968 1969 #if 1 1970 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 1971 #endif 1972 DPRINTFN(6, ("msk_init_yukon: end\n")); 1973 } 1974 1975 /* 1976 * Note that to properly initialize any part of the GEnesis chip, 1977 * you first have to take it out of reset mode. 1978 */ 1979 void 1980 msk_init(void *xsc_if) 1981 { 1982 struct sk_if_softc *sc_if = xsc_if; 1983 struct sk_softc *sc = sc_if->sk_softc; 1984 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1985 struct mii_data *mii = &sc_if->sk_mii; 1986 int s; 1987 1988 DPRINTFN(2, ("msk_init\n")); 1989 1990 s = splnet(); 1991 1992 /* Cancel pending I/O and free all RX/TX buffers. */ 1993 msk_stop(sc_if, 0); 1994 1995 /* Configure I2C registers */ 1996 1997 /* Configure XMAC(s) */ 1998 msk_init_yukon(sc_if); 1999 mii_mediachg(mii); 2000 2001 /* Configure transmit arbiter(s) */ 2002 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2003 #if 0 2004 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2005 #endif 2006 2007 /* Configure RAMbuffers */ 2008 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2009 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2010 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2011 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2012 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2013 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2014 2015 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2016 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2017 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2018 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2019 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2020 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2021 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2022 2023 /* Configure BMUs */ 2024 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2025 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2026 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2027 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_WATERMARK, 0x00000600); 2028 2029 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2030 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2031 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2032 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_WATERMARK, 0x00000600); 2033 2034 /* Make sure the sync transmit queue is disabled. */ 2035 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2036 2037 /* Init descriptors */ 2038 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2039 printf("%s: initialization failed: no " 2040 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2041 msk_stop(sc_if, 0); 2042 splx(s); 2043 return; 2044 } 2045 2046 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2047 printf("%s: initialization failed: no " 2048 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2049 msk_stop(sc_if, 0); 2050 splx(s); 2051 return; 2052 } 2053 2054 /* Initialize prefetch engine. */ 2055 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2056 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2057 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2058 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2059 MSK_RX_RING_ADDR(sc_if, 0)); 2060 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2061 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2062 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2063 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2064 2065 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2066 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2067 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2068 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2069 MSK_TX_RING_ADDR(sc_if, 0)); 2070 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2071 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2072 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2073 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2074 2075 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2076 sc_if->sk_cdata.sk_rx_prod); 2077 2078 /* Configure interrupt handling */ 2079 if (sc_if->sk_port == SK_PORT_A) 2080 sc->sk_intrmask |= SK_Y2_INTRS1; 2081 else 2082 sc->sk_intrmask |= SK_Y2_INTRS2; 2083 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2084 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2085 2086 ifp->if_flags |= IFF_RUNNING; 2087 ifp->if_flags &= ~IFF_OACTIVE; 2088 2089 timeout_add_sec(&sc_if->sk_tick_ch, 1); 2090 2091 splx(s); 2092 } 2093 2094 void 2095 msk_stop(struct sk_if_softc *sc_if, int softonly) 2096 { 2097 struct sk_softc *sc = sc_if->sk_softc; 2098 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2099 struct sk_txmap_entry *dma; 2100 int i; 2101 2102 DPRINTFN(2, ("msk_stop\n")); 2103 2104 timeout_del(&sc_if->sk_tick_ch); 2105 2106 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2107 2108 /* Stop transfer of Tx descriptors */ 2109 2110 /* Stop transfer of Rx descriptors */ 2111 2112 if (!softonly) { 2113 /* Turn off various components of this interface. */ 2114 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2115 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2116 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2117 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2118 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2119 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2120 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2121 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2122 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2123 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2124 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2125 2126 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2127 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2128 2129 /* Disable interrupts */ 2130 if (sc_if->sk_port == SK_PORT_A) 2131 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2132 else 2133 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2134 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2135 } 2136 2137 /* Free RX and TX mbufs still in the queues. */ 2138 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2139 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2140 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2141 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2142 } 2143 } 2144 2145 sc_if->sk_cdata.sk_rx_prod = 0; 2146 sc_if->sk_cdata.sk_rx_cons = 0; 2147 sc_if->sk_cdata.sk_rx_cnt = 0; 2148 2149 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2150 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2151 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2152 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2153 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2154 sc_if->sk_cdata.sk_tx_map[i], link); 2155 sc_if->sk_cdata.sk_tx_map[i] = 0; 2156 } 2157 } 2158 2159 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2160 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2161 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2162 free(dma, M_DEVBUF); 2163 } 2164 } 2165 2166 struct cfattach mskc_ca = { 2167 sizeof(struct sk_softc), mskc_probe, mskc_attach, mskc_detach, 2168 mskc_activate 2169 }; 2170 2171 struct cfdriver mskc_cd = { 2172 NULL, "mskc", DV_DULL 2173 }; 2174 2175 struct cfattach msk_ca = { 2176 sizeof(struct sk_if_softc), msk_probe, msk_attach, msk_detach, 2177 msk_activate 2178 }; 2179 2180 struct cfdriver msk_cd = { 2181 NULL, "msk", DV_IFNET 2182 }; 2183 2184 #ifdef MSK_DEBUG 2185 void 2186 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2187 { 2188 #define DESC_PRINT(X) \ 2189 if (X) \ 2190 printf("txdesc[%d]." #X "=%#x\n", \ 2191 idx, X); 2192 2193 DESC_PRINT(letoh32(le->sk_addr)); 2194 DESC_PRINT(letoh16(le->sk_len)); 2195 DESC_PRINT(le->sk_ctl); 2196 DESC_PRINT(le->sk_opcode); 2197 #undef DESC_PRINT 2198 } 2199 2200 void 2201 msk_dump_bytes(const char *data, int len) 2202 { 2203 int c, i, j; 2204 2205 for (i = 0; i < len; i += 16) { 2206 printf("%08x ", i); 2207 c = len - i; 2208 if (c > 16) c = 16; 2209 2210 for (j = 0; j < c; j++) { 2211 printf("%02x ", data[i + j] & 0xff); 2212 if ((j & 0xf) == 7 && j > 0) 2213 printf(" "); 2214 } 2215 2216 for (; j < 16; j++) 2217 printf(" "); 2218 printf(" "); 2219 2220 for (j = 0; j < c; j++) { 2221 int ch = data[i + j] & 0xff; 2222 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2223 } 2224 2225 printf("\n"); 2226 2227 if (c < 16) 2228 break; 2229 } 2230 } 2231 2232 void 2233 msk_dump_mbuf(struct mbuf *m) 2234 { 2235 int count = m->m_pkthdr.len; 2236 2237 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2238 2239 while (count > 0 && m) { 2240 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2241 m, m->m_data, m->m_len); 2242 msk_dump_bytes(mtod(m, char *), m->m_len); 2243 2244 count -= m->m_len; 2245 m = m->m_next; 2246 } 2247 } 2248 #endif 2249