1 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include "bpfilter.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/timeout.h> 99 #include <sys/device.h> 100 #include <sys/queue.h> 101 102 #include <net/if.h> 103 #include <net/if_dl.h> 104 #include <net/if_types.h> 105 106 #ifdef INET 107 #include <netinet/in.h> 108 #include <netinet/in_systm.h> 109 #include <netinet/in_var.h> 110 #include <netinet/ip.h> 111 #include <netinet/udp.h> 112 #include <netinet/tcp.h> 113 #include <netinet/if_ether.h> 114 #endif 115 116 #include <net/if_media.h> 117 #include <net/if_vlan_var.h> 118 119 #if NBPFILTER > 0 120 #include <net/bpf.h> 121 #endif 122 123 #include <dev/mii/mii.h> 124 #include <dev/mii/miivar.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/pcidevs.h> 130 131 #include <dev/pci/if_skreg.h> 132 #include <dev/pci/if_mskvar.h> 133 134 int mskc_probe(struct device *, void *, void *); 135 void mskc_attach(struct device *, struct device *self, void *aux); 136 void mskc_shutdown(void *); 137 int msk_probe(struct device *, void *, void *); 138 void msk_attach(struct device *, struct device *self, void *aux); 139 int mskcprint(void *, const char *); 140 int msk_intr(void *); 141 void msk_intr_yukon(struct sk_if_softc *); 142 __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 143 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 144 void msk_txeof(struct sk_if_softc *); 145 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 146 void msk_start(struct ifnet *); 147 int msk_ioctl(struct ifnet *, u_long, caddr_t); 148 void msk_init(void *); 149 void msk_init_yukon(struct sk_if_softc *); 150 void msk_stop(struct sk_if_softc *); 151 void msk_watchdog(struct ifnet *); 152 int msk_ifmedia_upd(struct ifnet *); 153 void msk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 154 void msk_reset(struct sk_softc *); 155 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 156 int msk_alloc_jumbo_mem(struct sk_if_softc *); 157 void *msk_jalloc(struct sk_if_softc *); 158 void msk_jfree(caddr_t, u_int, void *); 159 int msk_init_rx_ring(struct sk_if_softc *); 160 int msk_init_tx_ring(struct sk_if_softc *); 161 162 int msk_miibus_readreg(struct device *, int, int); 163 void msk_miibus_writereg(struct device *, int, int, int); 164 void msk_miibus_statchg(struct device *); 165 166 void msk_setfilt(struct sk_if_softc *, caddr_t, int); 167 void msk_setmulti(struct sk_if_softc *); 168 void msk_setpromisc(struct sk_if_softc *); 169 void msk_tick(void *); 170 171 #ifdef MSK_DEBUG 172 #define DPRINTF(x) if (mskdebug) printf x 173 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 174 int mskdebug = 0; 175 176 void msk_dump_txdesc(struct msk_tx_desc *, int); 177 void msk_dump_mbuf(struct mbuf *); 178 void msk_dump_bytes(const char *, int); 179 #else 180 #define DPRINTF(x) 181 #define DPRINTFN(n,x) 182 #endif 183 184 /* supported device vendors */ 185 const struct pci_matchid mskc_devices[] = { 186 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 187 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 188 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 200 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 201 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 202 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 203 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 204 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 205 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 206 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 207 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 208 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 209 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 210 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 211 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 212 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Sxx }, 213 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Exx } 214 }; 215 216 static inline u_int32_t 217 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 218 { 219 return CSR_READ_4(sc, reg); 220 } 221 222 static inline u_int16_t 223 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 224 { 225 return CSR_READ_2(sc, reg); 226 } 227 228 static inline u_int8_t 229 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 230 { 231 return CSR_READ_1(sc, reg); 232 } 233 234 static inline void 235 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 236 { 237 CSR_WRITE_4(sc, reg, x); 238 } 239 240 static inline void 241 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 242 { 243 CSR_WRITE_2(sc, reg, x); 244 } 245 246 static inline void 247 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 248 { 249 CSR_WRITE_1(sc, reg, x); 250 } 251 252 int 253 msk_miibus_readreg(struct device *dev, int phy, int reg) 254 { 255 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 256 u_int16_t val; 257 int i; 258 259 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 260 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 261 262 for (i = 0; i < SK_TIMEOUT; i++) { 263 DELAY(1); 264 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 265 if (val & YU_SMICR_READ_VALID) 266 break; 267 } 268 269 if (i == SK_TIMEOUT) { 270 printf("%s: phy failed to come ready\n", 271 sc_if->sk_dev.dv_xname); 272 return (0); 273 } 274 275 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 276 SK_TIMEOUT)); 277 278 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 279 280 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 281 phy, reg, val)); 282 283 return (val); 284 } 285 286 void 287 msk_miibus_writereg(struct device *dev, int phy, int reg, int val) 288 { 289 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 290 int i; 291 292 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 293 phy, reg, val)); 294 295 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 296 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 297 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 298 299 for (i = 0; i < SK_TIMEOUT; i++) { 300 DELAY(1); 301 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 302 break; 303 } 304 305 if (i == SK_TIMEOUT) 306 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 307 } 308 309 void 310 msk_miibus_statchg(struct device *dev) 311 { 312 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 313 struct mii_data *mii = &sc_if->sk_mii; 314 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 315 int gpcr; 316 317 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 318 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 319 320 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 321 /* Set speed. */ 322 gpcr |= YU_GPCR_SPEED_DIS; 323 switch (IFM_SUBTYPE(mii->mii_media_active)) { 324 case IFM_1000_SX: 325 case IFM_1000_LX: 326 case IFM_1000_CX: 327 case IFM_1000_T: 328 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 329 break; 330 case IFM_100_TX: 331 gpcr |= YU_GPCR_SPEED; 332 break; 333 } 334 335 /* Set duplex. */ 336 gpcr |= YU_GPCR_DPLX_DIS; 337 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 338 gpcr |= YU_GPCR_DUPLEX; 339 340 /* Disable flow control. */ 341 gpcr |= YU_GPCR_FCTL_DIS; 342 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 343 } 344 345 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 346 347 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 348 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 349 } 350 351 #define HASH_BITS 6 352 353 void 354 msk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 355 { 356 int base = XM_RXFILT_ENTRY(slot); 357 358 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 359 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 360 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 361 } 362 363 void 364 msk_setmulti(struct sk_if_softc *sc_if) 365 { 366 struct ifnet *ifp= &sc_if->arpcom.ac_if; 367 u_int32_t hashes[2] = { 0, 0 }; 368 int h; 369 struct arpcom *ac = &sc_if->arpcom; 370 struct ether_multi *enm; 371 struct ether_multistep step; 372 373 /* First, zot all the existing filters. */ 374 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 375 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 376 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 377 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 378 379 380 /* Now program new ones. */ 381 allmulti: 382 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 383 hashes[0] = 0xFFFFFFFF; 384 hashes[1] = 0xFFFFFFFF; 385 } else { 386 /* First find the tail of the list. */ 387 ETHER_FIRST_MULTI(step, ac, enm); 388 while (enm != NULL) { 389 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 390 ETHER_ADDR_LEN)) { 391 ifp->if_flags |= IFF_ALLMULTI; 392 goto allmulti; 393 } 394 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 395 ((1 << HASH_BITS) - 1); 396 if (h < 32) 397 hashes[0] |= (1 << h); 398 else 399 hashes[1] |= (1 << (h - 32)); 400 401 ETHER_NEXT_MULTI(step, enm); 402 } 403 } 404 405 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 406 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 407 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 408 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 409 } 410 411 void 412 msk_setpromisc(struct sk_if_softc *sc_if) 413 { 414 struct ifnet *ifp = &sc_if->arpcom.ac_if; 415 416 if (ifp->if_flags & IFF_PROMISC) 417 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 418 YU_RCR_UFLEN | YU_RCR_MUFLEN); 419 else 420 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 421 YU_RCR_UFLEN | YU_RCR_MUFLEN); 422 } 423 424 int 425 msk_init_rx_ring(struct sk_if_softc *sc_if) 426 { 427 struct msk_chain_data *cd = &sc_if->sk_cdata; 428 struct msk_ring_data *rd = sc_if->sk_rdata; 429 int i, nexti; 430 431 bzero((char *)rd->sk_rx_ring, 432 sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 433 434 for (i = 0; i < MSK_RX_RING_CNT; i++) { 435 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 436 if (i == (MSK_RX_RING_CNT - 1)) 437 nexti = 0; 438 else 439 nexti = i + 1; 440 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 441 } 442 443 for (i = 0; i < MSK_RX_RING_CNT; i++) { 444 if (msk_newbuf(sc_if, i, NULL, 445 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 446 printf("%s: failed alloc of %dth mbuf\n", 447 sc_if->sk_dev.dv_xname, i); 448 return (ENOBUFS); 449 } 450 } 451 452 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 453 sc_if->sk_cdata.sk_rx_cons = 0; 454 455 return (0); 456 } 457 458 int 459 msk_init_tx_ring(struct sk_if_softc *sc_if) 460 { 461 struct sk_softc *sc = sc_if->sk_softc; 462 struct msk_chain_data *cd = &sc_if->sk_cdata; 463 struct msk_ring_data *rd = sc_if->sk_rdata; 464 bus_dmamap_t dmamap; 465 struct sk_txmap_entry *entry; 466 int i, nexti; 467 468 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 469 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 470 471 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 472 for (i = 0; i < MSK_TX_RING_CNT; i++) { 473 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 474 if (i == (MSK_TX_RING_CNT - 1)) 475 nexti = 0; 476 else 477 nexti = i + 1; 478 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 479 480 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 481 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 482 return (ENOBUFS); 483 484 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 485 if (!entry) { 486 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 487 return (ENOBUFS); 488 } 489 entry->dmamap = dmamap; 490 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 491 } 492 493 sc_if->sk_cdata.sk_tx_prod = 0; 494 sc_if->sk_cdata.sk_tx_cons = 0; 495 sc_if->sk_cdata.sk_tx_cnt = 0; 496 497 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 498 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 499 500 return (0); 501 } 502 503 int 504 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 505 bus_dmamap_t dmamap) 506 { 507 struct mbuf *m_new = NULL; 508 struct sk_chain *c; 509 struct msk_rx_desc *r; 510 511 if (m == NULL) { 512 caddr_t buf = NULL; 513 514 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 515 if (m_new == NULL) 516 return (ENOBUFS); 517 518 /* Allocate the jumbo buffer */ 519 buf = msk_jalloc(sc_if); 520 if (buf == NULL) { 521 m_freem(m_new); 522 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 523 "dropped!\n", sc_if->arpcom.ac_if.if_xname)); 524 return (ENOBUFS); 525 } 526 527 /* Attach the buffer to the mbuf */ 528 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 529 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 530 } else { 531 /* 532 * We're re-using a previously allocated mbuf; 533 * be sure to re-init pointers and lengths to 534 * default values. 535 */ 536 m_new = m; 537 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 538 m_new->m_data = m_new->m_ext.ext_buf; 539 } 540 m_adj(m_new, ETHER_ALIGN); 541 542 c = &sc_if->sk_cdata.sk_rx_chain[i]; 543 r = c->sk_le; 544 c->sk_mbuf = m_new; 545 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 546 (((vaddr_t)m_new->m_data 547 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 548 r->sk_len = htole16(SK_JLEN); 549 r->sk_ctl = 0; 550 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 551 552 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 553 554 return (0); 555 } 556 557 /* 558 * Memory management for jumbo frames. 559 */ 560 561 int 562 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 563 { 564 struct sk_softc *sc = sc_if->sk_softc; 565 caddr_t ptr, kva; 566 bus_dma_segment_t seg; 567 int i, rseg, state, error; 568 struct sk_jpool_entry *entry; 569 570 state = error = 0; 571 572 /* Grab a big chunk o' storage. */ 573 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 574 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 575 printf(": can't alloc rx buffers"); 576 return (ENOBUFS); 577 } 578 579 state = 1; 580 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, &kva, 581 BUS_DMA_NOWAIT)) { 582 printf(": can't map dma buffers (%d bytes)", MSK_JMEM); 583 error = ENOBUFS; 584 goto out; 585 } 586 587 state = 2; 588 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 589 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 590 printf(": can't create dma map"); 591 error = ENOBUFS; 592 goto out; 593 } 594 595 state = 3; 596 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 597 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 598 printf(": can't load dma map"); 599 error = ENOBUFS; 600 goto out; 601 } 602 603 state = 4; 604 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 605 DPRINTFN(1,("msk_jumbo_buf = 0x%08X\n", sc_if->sk_cdata.sk_jumbo_buf)); 606 607 LIST_INIT(&sc_if->sk_jfree_listhead); 608 LIST_INIT(&sc_if->sk_jinuse_listhead); 609 610 /* 611 * Now divide it up into 9K pieces and save the addresses 612 * in an array. 613 */ 614 ptr = sc_if->sk_cdata.sk_jumbo_buf; 615 for (i = 0; i < MSK_JSLOTS; i++) { 616 sc_if->sk_cdata.sk_jslots[i] = ptr; 617 ptr += SK_JLEN; 618 entry = malloc(sizeof(struct sk_jpool_entry), 619 M_DEVBUF, M_NOWAIT); 620 if (entry == NULL) { 621 sc_if->sk_cdata.sk_jumbo_buf = NULL; 622 printf(": no memory for jumbo buffer queue!"); 623 error = ENOBUFS; 624 goto out; 625 } 626 entry->slot = i; 627 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 628 entry, jpool_entries); 629 } 630 out: 631 if (error != 0) { 632 switch (state) { 633 case 4: 634 bus_dmamap_unload(sc->sc_dmatag, 635 sc_if->sk_cdata.sk_rx_jumbo_map); 636 case 3: 637 bus_dmamap_destroy(sc->sc_dmatag, 638 sc_if->sk_cdata.sk_rx_jumbo_map); 639 case 2: 640 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 641 case 1: 642 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 643 break; 644 default: 645 break; 646 } 647 } 648 649 return (error); 650 } 651 652 /* 653 * Allocate a jumbo buffer. 654 */ 655 void * 656 msk_jalloc(struct sk_if_softc *sc_if) 657 { 658 struct sk_jpool_entry *entry; 659 660 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 661 662 if (entry == NULL) 663 return (NULL); 664 665 LIST_REMOVE(entry, jpool_entries); 666 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 667 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 668 } 669 670 /* 671 * Release a jumbo buffer. 672 */ 673 void 674 msk_jfree(caddr_t buf, u_int size, void *arg) 675 { 676 struct sk_jpool_entry *entry; 677 struct sk_if_softc *sc; 678 int i; 679 680 /* Extract the softc struct pointer. */ 681 sc = (struct sk_if_softc *)arg; 682 683 if (sc == NULL) 684 panic("sk_jfree: can't find softc pointer!"); 685 686 /* calculate the slot this buffer belongs to */ 687 i = ((vaddr_t)buf 688 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 689 690 if ((i < 0) || (i >= MSK_JSLOTS)) 691 panic("sk_jfree: asked to free buffer that we don't manage!"); 692 693 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 694 if (entry == NULL) 695 panic("msk_jfree: buffer not in use!"); 696 entry->slot = i; 697 LIST_REMOVE(entry, jpool_entries); 698 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 699 } 700 701 /* 702 * Set media options. 703 */ 704 int 705 msk_ifmedia_upd(struct ifnet *ifp) 706 { 707 struct sk_if_softc *sc_if = ifp->if_softc; 708 709 mii_mediachg(&sc_if->sk_mii); 710 return (0); 711 } 712 713 /* 714 * Report current media status. 715 */ 716 void 717 msk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 718 { 719 struct sk_if_softc *sc_if = ifp->if_softc; 720 721 mii_pollstat(&sc_if->sk_mii); 722 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 723 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 724 } 725 726 int 727 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 728 { 729 struct sk_if_softc *sc_if = ifp->if_softc; 730 struct ifreq *ifr = (struct ifreq *) data; 731 struct ifaddr *ifa = (struct ifaddr *) data; 732 struct mii_data *mii; 733 int s, error = 0; 734 735 s = splnet(); 736 737 if ((error = ether_ioctl(ifp, &sc_if->arpcom, command, data)) > 0) { 738 splx(s); 739 return (error); 740 } 741 742 switch(command) { 743 case SIOCSIFADDR: 744 ifp->if_flags |= IFF_UP; 745 if (!(ifp->if_flags & IFF_RUNNING)) 746 msk_init(sc_if); 747 #ifdef INET 748 if (ifa->ifa_addr->sa_family == AF_INET) 749 arp_ifinit(&sc_if->arpcom, ifa); 750 #endif /* INET */ 751 break; 752 case SIOCSIFMTU: 753 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu) 754 error = EINVAL; 755 else if (ifp->if_mtu != ifr->ifr_mtu) 756 ifp->if_mtu = ifr->ifr_mtu; 757 break; 758 case SIOCSIFFLAGS: 759 if (ifp->if_flags & IFF_UP) { 760 if (ifp->if_flags & IFF_RUNNING && 761 (sc_if->sk_if_flags ^ ifp->if_flags) & 762 IFF_PROMISC) { 763 msk_setpromisc(sc_if); 764 msk_setmulti(sc_if); 765 } else { 766 if (!(ifp->if_flags & IFF_RUNNING)) 767 msk_init(sc_if); 768 } 769 } else { 770 if (ifp->if_flags & IFF_RUNNING) 771 msk_stop(sc_if); 772 } 773 sc_if->sk_if_flags = ifp->if_flags; 774 break; 775 case SIOCADDMULTI: 776 case SIOCDELMULTI: 777 error = (command == SIOCADDMULTI) ? 778 ether_addmulti(ifr, &sc_if->arpcom) : 779 ether_delmulti(ifr, &sc_if->arpcom); 780 781 if (error == ENETRESET) { 782 /* 783 * Multicast list has changed; set the hardware 784 * filter accordingly. 785 */ 786 if (ifp->if_flags & IFF_RUNNING) 787 msk_setmulti(sc_if); 788 error = 0; 789 } 790 break; 791 case SIOCGIFMEDIA: 792 case SIOCSIFMEDIA: 793 mii = &sc_if->sk_mii; 794 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 795 break; 796 default: 797 error = ENOTTY; 798 break; 799 } 800 801 splx(s); 802 803 return (error); 804 } 805 806 /* 807 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 808 * IDs against our list and return a device name if we find a match. 809 */ 810 int 811 mskc_probe(struct device *parent, void *match, void *aux) 812 { 813 return (pci_matchbyid((struct pci_attach_args *)aux, mskc_devices, 814 sizeof(mskc_devices)/sizeof(mskc_devices[0]))); 815 } 816 817 /* 818 * Force the GEnesis into reset, then bring it out of reset. 819 */ 820 void msk_reset(struct sk_softc *sc) 821 { 822 u_int32_t imtimer_ticks, reg1; 823 int reg; 824 825 DPRINTFN(2, ("msk_reset\n")); 826 827 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 828 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 829 830 DELAY(1000); 831 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 832 DELAY(2); 833 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 834 835 sk_win_write_1(sc, SK_TESTCTL1, 2); 836 837 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 838 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 839 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 840 else 841 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 842 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 843 844 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 845 sk_win_write_1(sc, SK_Y2_CLKGATE, 846 SK_Y2_CLKGATE_LINK1_GATE_DIS | 847 SK_Y2_CLKGATE_LINK2_GATE_DIS | 848 SK_Y2_CLKGATE_LINK1_CORE_DIS | 849 SK_Y2_CLKGATE_LINK2_CORE_DIS | 850 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 851 else 852 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 853 854 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 855 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 856 DELAY(1000); 857 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 858 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 859 860 sk_win_write_1(sc, SK_TESTCTL1, 1); 861 862 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 863 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 864 CSR_READ_2(sc, SK_LINK_CTRL))); 865 866 /* Disable ASF */ 867 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 868 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 869 870 /* Clear I2C IRQ noise */ 871 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 872 873 /* Disable hardware timer */ 874 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 875 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 876 877 /* Disable descriptor polling */ 878 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 879 880 /* Disable time stamps */ 881 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 882 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 883 884 /* Enable RAM interface */ 885 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 886 for (reg = SK_TO0;reg <= SK_TO11; reg++) 887 sk_win_write_1(sc, reg, 36); 888 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 889 for (reg = SK_TO0;reg <= SK_TO11; reg++) 890 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 891 892 /* 893 * Configure interrupt moderation. The moderation timer 894 * defers interrupts specified in the interrupt moderation 895 * timer mask based on the timeout specified in the interrupt 896 * moderation timer init register. Each bit in the timer 897 * register represents one tick, so to specify a timeout in 898 * microseconds, we have to multiply by the correct number of 899 * ticks-per-microsecond. 900 */ 901 switch (sc->sk_type) { 902 case SK_YUKON_EC: 903 case SK_YUKON_XL: 904 case SK_YUKON_FE: 905 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 906 break; 907 default: 908 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 909 } 910 911 /* Reset status ring. */ 912 bzero((char *)sc->sk_status_ring, 913 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 914 sc->sk_status_idx = 0; 915 916 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 917 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 918 919 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 920 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 921 sc->sk_status_map->dm_segs[0].ds_addr); 922 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 923 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 924 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 10); 925 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 16); 926 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 16); 927 928 #if 0 929 sk_win_write_4(sc, SK_Y2_LEV_TIMERINIT, SK_IM_USECS(100)); 930 sk_win_write_4(sc, 0x0ec0, SK_IM_USECS(1000)); 931 932 sk_win_write_4(sc, 0x0ed0, SK_IM_USECS(20)); 933 #else 934 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(4)); 935 #endif 936 937 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 938 939 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 940 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 941 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 942 } 943 944 int 945 msk_probe(struct device *parent, void *match, void *aux) 946 { 947 struct skc_attach_args *sa = aux; 948 949 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 950 return (0); 951 952 switch (sa->skc_type) { 953 case SK_YUKON_XL: 954 case SK_YUKON_EC_U: 955 case SK_YUKON_EC: 956 case SK_YUKON_FE: 957 return (1); 958 } 959 960 return (0); 961 } 962 963 /* 964 * Each XMAC chip is attached as a separate logical IP interface. 965 * Single port cards will have only one logical interface of course. 966 */ 967 void 968 msk_attach(struct device *parent, struct device *self, void *aux) 969 { 970 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 971 struct sk_softc *sc = (struct sk_softc *)parent; 972 struct skc_attach_args *sa = aux; 973 struct ifnet *ifp; 974 caddr_t kva; 975 bus_dma_segment_t seg; 976 int i, rseg; 977 u_int32_t chunk, val; 978 979 sc_if->sk_port = sa->skc_port; 980 sc_if->sk_softc = sc; 981 sc->sk_if[sa->skc_port] = sc_if; 982 983 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 984 985 /* 986 * Get station address for this interface. Note that 987 * dual port cards actually come with three station 988 * addresses: one for each port, plus an extra. The 989 * extra one is used by the SysKonnect driver software 990 * as a 'virtual' station address for when both ports 991 * are operating in failover mode. Currently we don't 992 * use this extra address. 993 */ 994 for (i = 0; i < ETHER_ADDR_LEN; i++) 995 sc_if->arpcom.ac_enaddr[i] = 996 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 997 998 printf(", address %s\n", 999 ether_sprintf(sc_if->arpcom.ac_enaddr)); 1000 1001 /* 1002 * Set up RAM buffer addresses. The NIC will have a certain 1003 * amount of SRAM on it, somewhere between 512K and 2MB. We 1004 * need to divide this up a) between the transmitter and 1005 * receiver and b) between the two XMACs, if this is a 1006 * dual port NIC. Our algorithm is to divide up the memory 1007 * evenly so that everyone gets a fair share. 1008 * 1009 * Just to be contrary, Yukon2 appears to have separate memory 1010 * for each MAC. 1011 */ 1012 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 1013 val = sc->sk_rboff / sizeof(u_int64_t); 1014 sc_if->sk_rx_ramstart = val; 1015 val += (chunk / sizeof(u_int64_t)); 1016 sc_if->sk_rx_ramend = val - 1; 1017 chunk = sc->sk_ramsize - chunk; 1018 sc_if->sk_tx_ramstart = val; 1019 val += (chunk / sizeof(u_int64_t)); 1020 sc_if->sk_tx_ramend = val - 1; 1021 1022 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1023 " tx_ramstart=%#x tx_ramend=%#x\n", 1024 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1025 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1026 1027 /* Allocate the descriptor queues. */ 1028 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1029 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1030 printf(": can't alloc rx buffers\n"); 1031 goto fail; 1032 } 1033 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1034 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1035 printf(": can't map dma buffers (%z bytes)\n", 1036 sizeof(struct msk_ring_data)); 1037 goto fail_1; 1038 } 1039 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1040 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1041 &sc_if->sk_ring_map)) { 1042 printf(": can't create dma map\n"); 1043 goto fail_2; 1044 } 1045 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1046 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1047 printf(": can't load dma map\n"); 1048 goto fail_3; 1049 } 1050 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1051 bzero(sc_if->sk_rdata, sizeof(struct msk_ring_data)); 1052 1053 /* Try to allocate memory for jumbo buffers. */ 1054 if (msk_alloc_jumbo_mem(sc_if)) { 1055 printf(": jumbo buffer allocation failed\n"); 1056 goto fail_3; 1057 } 1058 1059 ifp = &sc_if->arpcom.ac_if; 1060 ifp->if_softc = sc_if; 1061 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1062 ifp->if_ioctl = msk_ioctl; 1063 ifp->if_start = msk_start; 1064 ifp->if_watchdog = msk_watchdog; 1065 ifp->if_baudrate = 1000000000; 1066 if (sc->sk_type != SK_YUKON_FE) 1067 ifp->if_hardmtu = SK_JUMBO_MTU; 1068 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1069 IFQ_SET_READY(&ifp->if_snd); 1070 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1071 1072 ifp->if_capabilities = IFCAP_VLAN_MTU; 1073 1074 /* 1075 * Do miibus setup. 1076 */ 1077 msk_init_yukon(sc_if); 1078 1079 DPRINTFN(2, ("msk_attach: 1\n")); 1080 1081 sc_if->sk_mii.mii_ifp = ifp; 1082 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1083 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1084 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1085 1086 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1087 msk_ifmedia_upd, msk_ifmedia_sts); 1088 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1089 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); 1090 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1091 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1092 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1093 0, NULL); 1094 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1095 } else 1096 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1097 1098 timeout_set(&sc_if->sk_tick_ch, msk_tick, sc_if); 1099 1100 /* 1101 * Call MI attach routines. 1102 */ 1103 if_attach(ifp); 1104 ether_ifattach(ifp); 1105 1106 shutdownhook_establish(mskc_shutdown, sc); 1107 1108 DPRINTFN(2, ("msk_attach: end\n")); 1109 return; 1110 1111 fail_3: 1112 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1113 fail_2: 1114 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1115 fail_1: 1116 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1117 fail: 1118 sc->sk_if[sa->skc_port] = NULL; 1119 } 1120 1121 int 1122 mskcprint(void *aux, const char *pnp) 1123 { 1124 struct skc_attach_args *sa = aux; 1125 1126 if (pnp) 1127 printf("sk port %c at %s", 1128 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1129 else 1130 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1131 return (UNCONF); 1132 } 1133 1134 /* 1135 * Attach the interface. Allocate softc structures, do ifmedia 1136 * setup and ethernet/BPF attach. 1137 */ 1138 void 1139 mskc_attach(struct device *parent, struct device *self, void *aux) 1140 { 1141 struct sk_softc *sc = (struct sk_softc *)self; 1142 struct pci_attach_args *pa = aux; 1143 struct skc_attach_args skca; 1144 pci_chipset_tag_t pc = pa->pa_pc; 1145 pcireg_t command, memtype; 1146 pci_intr_handle_t ih; 1147 const char *intrstr = NULL; 1148 bus_size_t size; 1149 u_int8_t hw, skrs; 1150 char *revstr = NULL; 1151 caddr_t kva; 1152 bus_dma_segment_t seg; 1153 int rseg; 1154 1155 DPRINTFN(2, ("begin mskc_attach\n")); 1156 1157 /* 1158 * Handle power management nonsense. 1159 */ 1160 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1161 1162 if (command == 0x01) { 1163 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1164 if (command & SK_PSTATE_MASK) { 1165 u_int32_t iobase, membase, irq; 1166 1167 /* Save important PCI config data. */ 1168 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1169 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1170 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1171 1172 /* Reset the power state. */ 1173 printf("%s chip is in D%d power mode " 1174 "-- setting to D0\n", sc->sk_dev.dv_xname, 1175 command & SK_PSTATE_MASK); 1176 command &= 0xFFFFFFFC; 1177 pci_conf_write(pc, pa->pa_tag, 1178 SK_PCI_PWRMGMTCTRL, command); 1179 1180 /* Restore PCI config data. */ 1181 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1182 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1183 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1184 } 1185 } 1186 1187 /* 1188 * Map control/status registers. 1189 */ 1190 1191 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1192 switch (memtype) { 1193 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1194 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1195 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1196 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1197 NULL, &size, 0) == 0) 1198 break; 1199 default: 1200 printf(": can't map mem space\n"); 1201 return; 1202 } 1203 1204 sc->sc_dmatag = pa->pa_dmat; 1205 1206 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1207 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1208 1209 /* bail out here if chip is not recognized */ 1210 if (!(SK_IS_YUKON2(sc))) { 1211 printf(": unknown chip type: %d\n", sc->sk_type); 1212 goto fail_1; 1213 } 1214 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1215 1216 /* Allocate interrupt */ 1217 if (pci_intr_map(pa, &ih)) { 1218 printf(": couldn't map interrupt\n"); 1219 goto fail_1; 1220 } 1221 1222 intrstr = pci_intr_string(pc, ih); 1223 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc, 1224 self->dv_xname); 1225 if (sc->sk_intrhand == NULL) { 1226 printf(": couldn't establish interrupt"); 1227 if (intrstr != NULL) 1228 printf(" at %s", intrstr); 1229 printf("\n"); 1230 goto fail_1; 1231 } 1232 1233 if (bus_dmamem_alloc(sc->sc_dmatag, 1234 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1235 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1236 printf(": can't alloc status buffers\n"); 1237 goto fail_2; 1238 } 1239 1240 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1241 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1242 &kva, BUS_DMA_NOWAIT)) { 1243 printf(": can't map dma buffers (%z bytes)\n", 1244 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1245 goto fail_3; 1246 } 1247 if (bus_dmamap_create(sc->sc_dmatag, 1248 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1249 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1250 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1251 printf(": can't create dma map\n"); 1252 goto fail_4; 1253 } 1254 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1255 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1256 NULL, BUS_DMA_NOWAIT)) { 1257 printf(": can't load dma map\n"); 1258 goto fail_5; 1259 } 1260 sc->sk_status_ring = (struct msk_status_desc *)kva; 1261 bzero(sc->sk_status_ring, 1262 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1263 1264 /* Reset the adapter. */ 1265 msk_reset(sc); 1266 1267 skrs = sk_win_read_1(sc, SK_EPROM0); 1268 if (skrs == 0x00) 1269 sc->sk_ramsize = 0x20000; 1270 else 1271 sc->sk_ramsize = skrs * (1<<12); 1272 sc->sk_rboff = SK_RBOFF_0; 1273 1274 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1275 sc->sk_ramsize, sc->sk_ramsize / 1024, 1276 sc->sk_rboff)); 1277 1278 switch (sc->sk_type) { 1279 case SK_YUKON_XL: 1280 sc->sk_name = "Yukon-2 XL"; 1281 break; 1282 case SK_YUKON_EC_U: 1283 sc->sk_name = "Yukon-2 EC Ultra"; 1284 break; 1285 case SK_YUKON_EC: 1286 sc->sk_name = "Yukon-2 EC"; 1287 break; 1288 case SK_YUKON_FE: 1289 sc->sk_name = "Yukon-2 FE"; 1290 break; 1291 default: 1292 sc->sk_name = "Yukon (Unknown)"; 1293 } 1294 1295 if (sc->sk_type == SK_YUKON_XL) { 1296 switch (sc->sk_rev) { 1297 case SK_YUKON_XL_REV_A0: 1298 revstr = "A0"; 1299 break; 1300 case SK_YUKON_XL_REV_A1: 1301 revstr = "A1"; 1302 break; 1303 case SK_YUKON_XL_REV_A2: 1304 revstr = "A2"; 1305 break; 1306 case SK_YUKON_XL_REV_A3: 1307 revstr = "A3"; 1308 break; 1309 default: 1310 ; 1311 } 1312 } 1313 1314 if (sc->sk_type == SK_YUKON_EC) { 1315 switch (sc->sk_rev) { 1316 case SK_YUKON_EC_REV_A1: 1317 revstr = "A1"; 1318 break; 1319 case SK_YUKON_EC_REV_A2: 1320 revstr = "A2"; 1321 break; 1322 case SK_YUKON_EC_REV_A3: 1323 revstr = "A3"; 1324 break; 1325 default: 1326 ; 1327 } 1328 } 1329 1330 if (sc->sk_type == SK_YUKON_EC_U) { 1331 switch (sc->sk_rev) { 1332 case SK_YUKON_EC_U_REV_A0: 1333 revstr = "A0"; 1334 break; 1335 case SK_YUKON_EC_U_REV_A1: 1336 revstr = "A1"; 1337 break; 1338 default: 1339 ; 1340 } 1341 } 1342 1343 /* Announce the product name. */ 1344 printf(", %s", sc->sk_name); 1345 if (revstr != NULL) 1346 printf(" rev. %s", revstr); 1347 printf(" (0x%x): %s\n", sc->sk_rev, intrstr); 1348 1349 sc->sk_macs = 1; 1350 1351 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1352 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1353 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1354 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1355 sc->sk_macs++; 1356 } 1357 1358 skca.skc_port = SK_PORT_A; 1359 skca.skc_type = sc->sk_type; 1360 skca.skc_rev = sc->sk_rev; 1361 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1362 1363 if (sc->sk_macs > 1) { 1364 skca.skc_port = SK_PORT_B; 1365 skca.skc_type = sc->sk_type; 1366 skca.skc_rev = sc->sk_rev; 1367 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1368 } 1369 1370 /* Turn on the 'driver is loaded' LED. */ 1371 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1372 1373 return; 1374 1375 fail_5: 1376 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1377 fail_4: 1378 bus_dmamem_unmap(sc->sc_dmatag, kva, 1379 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1380 fail_3: 1381 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1382 fail_2: 1383 pci_intr_disestablish(pc, sc->sk_intrhand); 1384 fail_1: 1385 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1386 } 1387 1388 int 1389 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1390 { 1391 struct sk_softc *sc = sc_if->sk_softc; 1392 struct msk_tx_desc *f = NULL; 1393 u_int32_t frag, cur; 1394 int i; 1395 struct sk_txmap_entry *entry; 1396 bus_dmamap_t txmap; 1397 1398 DPRINTFN(2, ("msk_encap\n")); 1399 1400 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1401 if (entry == NULL) { 1402 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1403 return (ENOBUFS); 1404 } 1405 txmap = entry->dmamap; 1406 1407 cur = frag = *txidx; 1408 1409 #ifdef MSK_DEBUG 1410 if (mskdebug >= 2) 1411 msk_dump_mbuf(m_head); 1412 #endif 1413 1414 /* 1415 * Start packing the mbufs in this chain into 1416 * the fragment pointers. Stop when we run out 1417 * of fragments or hit the end of the mbuf chain. 1418 */ 1419 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1420 BUS_DMA_NOWAIT)) { 1421 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1422 return (ENOBUFS); 1423 } 1424 1425 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1426 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1427 bus_dmamap_unload(sc->sc_dmatag, txmap); 1428 return (ENOBUFS); 1429 } 1430 1431 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1432 1433 /* Sync the DMA map. */ 1434 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1435 BUS_DMASYNC_PREWRITE); 1436 1437 for (i = 0; i < txmap->dm_nsegs; i++) { 1438 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1439 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1440 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1441 f->sk_ctl = 0; 1442 if (i == 0) 1443 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1444 else 1445 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1446 cur = frag; 1447 SK_INC(frag, MSK_TX_RING_CNT); 1448 } 1449 1450 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1451 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1452 1453 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1454 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1455 1456 /* Sync descriptors before handing to chip */ 1457 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1458 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1459 1460 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1461 1462 /* Sync first descriptor to hand it off */ 1463 MSK_CDTXSYNC(sc_if, *txidx, 1, 1464 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1465 1466 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1467 1468 #ifdef MSK_DEBUG 1469 if (mskdebug >= 2) { 1470 struct msk_tx_desc *le; 1471 u_int32_t idx; 1472 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1473 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1474 msk_dump_txdesc(le, idx); 1475 } 1476 } 1477 #endif 1478 1479 *txidx = frag; 1480 1481 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1482 1483 return (0); 1484 } 1485 1486 void 1487 msk_start(struct ifnet *ifp) 1488 { 1489 struct sk_if_softc *sc_if = ifp->if_softc; 1490 struct mbuf *m_head = NULL; 1491 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1492 int pkts = 0; 1493 1494 DPRINTFN(2, ("msk_start\n")); 1495 1496 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1497 IFQ_POLL(&ifp->if_snd, m_head); 1498 if (m_head == NULL) 1499 break; 1500 1501 /* 1502 * Pack the data into the transmit ring. If we 1503 * don't have room, set the OACTIVE flag and wait 1504 * for the NIC to drain the ring. 1505 */ 1506 if (msk_encap(sc_if, m_head, &idx)) { 1507 ifp->if_flags |= IFF_OACTIVE; 1508 break; 1509 } 1510 1511 /* now we are committed to transmit the packet */ 1512 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1513 pkts++; 1514 1515 /* 1516 * If there's a BPF listener, bounce a copy of this frame 1517 * to him. 1518 */ 1519 #if NBPFILTER > 0 1520 if (ifp->if_bpf) 1521 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1522 #endif 1523 } 1524 if (pkts == 0) 1525 return; 1526 1527 /* Transmit */ 1528 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1529 sc_if->sk_cdata.sk_tx_prod = idx; 1530 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1531 1532 /* Set a timeout in case the chip goes out to lunch. */ 1533 ifp->if_timer = 5; 1534 } 1535 } 1536 1537 void 1538 msk_watchdog(struct ifnet *ifp) 1539 { 1540 struct sk_if_softc *sc_if = ifp->if_softc; 1541 1542 /* 1543 * Reclaim first as there is a possibility of losing Tx completion 1544 * interrupts. 1545 */ 1546 msk_txeof(sc_if); 1547 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1548 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1549 1550 ifp->if_oerrors++; 1551 1552 /* XXX Resets both ports; we shouldn't do that. */ 1553 msk_reset(sc_if->sk_softc); 1554 msk_init(sc_if); 1555 } 1556 } 1557 1558 void 1559 mskc_shutdown(void *v) 1560 { 1561 struct sk_softc *sc = v; 1562 1563 DPRINTFN(2, ("msk_shutdown\n")); 1564 1565 /* Turn off the 'driver is loaded' LED. */ 1566 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1567 1568 /* 1569 * Reset the GEnesis controller. Doing this should also 1570 * assert the resets on the attached XMAC(s). 1571 */ 1572 msk_reset(sc); 1573 } 1574 1575 __inline int 1576 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1577 { 1578 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1579 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1580 YU_RXSTAT_JABBER)) != 0 || 1581 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1582 YU_RXSTAT_BYTES(stat) != len) 1583 return (0); 1584 1585 return (1); 1586 } 1587 1588 void 1589 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1590 { 1591 struct sk_softc *sc = sc_if->sk_softc; 1592 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1593 struct mbuf *m; 1594 struct sk_chain *cur_rx; 1595 int cur, total_len = len; 1596 bus_dmamap_t dmamap; 1597 1598 DPRINTFN(2, ("msk_rxeof\n")); 1599 1600 cur = sc_if->sk_cdata.sk_rx_cons; 1601 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1602 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1603 1604 /* Sync the descriptor */ 1605 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1606 1607 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1608 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1609 1610 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1611 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1612 1613 m = cur_rx->sk_mbuf; 1614 cur_rx->sk_mbuf = NULL; 1615 1616 if (total_len < SK_MIN_FRAMELEN || 1617 total_len > SK_JUMBO_FRAMELEN || 1618 msk_rxvalid(sc, rxstat, total_len) == 0) { 1619 ifp->if_ierrors++; 1620 msk_newbuf(sc_if, cur, m, dmamap); 1621 return; 1622 } 1623 1624 /* 1625 * Try to allocate a new jumbo buffer. If that fails, copy the 1626 * packet to mbufs and put the jumbo buffer back in the ring 1627 * so it can be re-used. If allocating mbufs fails, then we 1628 * have to drop the packet. 1629 */ 1630 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1631 struct mbuf *m0; 1632 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1633 total_len + ETHER_ALIGN, 0, ifp, NULL); 1634 msk_newbuf(sc_if, cur, m, dmamap); 1635 if (m0 == NULL) { 1636 ifp->if_ierrors++; 1637 return; 1638 } 1639 m_adj(m0, ETHER_ALIGN); 1640 m = m0; 1641 } else { 1642 m->m_pkthdr.rcvif = ifp; 1643 m->m_pkthdr.len = m->m_len = total_len; 1644 } 1645 1646 ifp->if_ipackets++; 1647 1648 #if NBPFILTER > 0 1649 if (ifp->if_bpf) 1650 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1651 #endif 1652 1653 /* pass it on. */ 1654 ether_input_mbuf(ifp, m); 1655 } 1656 1657 void 1658 msk_txeof(struct sk_if_softc *sc_if) 1659 { 1660 struct sk_softc *sc = sc_if->sk_softc; 1661 struct msk_tx_desc *cur_tx; 1662 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1663 u_int32_t idx, reg, sk_ctl; 1664 struct sk_txmap_entry *entry; 1665 1666 DPRINTFN(2, ("msk_txeof\n")); 1667 1668 if (sc_if->sk_port == SK_PORT_A) 1669 reg = SK_STAT_BMU_TXA1_RIDX; 1670 else 1671 reg = SK_STAT_BMU_TXA2_RIDX; 1672 1673 /* 1674 * Go through our tx ring and free mbufs for those 1675 * frames that have been sent. 1676 */ 1677 idx = sc_if->sk_cdata.sk_tx_cons; 1678 while (idx != sk_win_read_2(sc, reg)) { 1679 MSK_CDTXSYNC(sc_if, idx, 1, 1680 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1681 1682 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1683 sk_ctl = cur_tx->sk_ctl; 1684 #ifdef MSK_DEBUG 1685 if (mskdebug >= 2) 1686 msk_dump_txdesc(cur_tx, idx); 1687 #endif 1688 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1689 ifp->if_opackets++; 1690 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1691 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1692 1693 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1694 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1695 1696 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1697 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1698 1699 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1700 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1701 link); 1702 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1703 } 1704 sc_if->sk_cdata.sk_tx_cnt--; 1705 SK_INC(idx, MSK_TX_RING_CNT); 1706 } 1707 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1708 1709 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1710 ifp->if_flags &= ~IFF_OACTIVE; 1711 1712 sc_if->sk_cdata.sk_tx_cons = idx; 1713 } 1714 1715 void 1716 msk_tick(void *xsc_if) 1717 { 1718 struct sk_if_softc *sc_if = xsc_if; 1719 struct mii_data *mii = &sc_if->sk_mii; 1720 1721 mii_tick(mii); 1722 timeout_add(&sc_if->sk_tick_ch, hz); 1723 } 1724 1725 void 1726 msk_intr_yukon(struct sk_if_softc *sc_if) 1727 { 1728 u_int8_t status; 1729 1730 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1731 /* RX overrun */ 1732 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1733 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1734 SK_RFCTL_RX_FIFO_OVER); 1735 } 1736 /* TX underrun */ 1737 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1738 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1739 SK_TFCTL_TX_FIFO_UNDER); 1740 } 1741 1742 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1743 } 1744 1745 int 1746 msk_intr(void *xsc) 1747 { 1748 struct sk_softc *sc = xsc; 1749 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1750 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1751 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1752 int claimed = 0; 1753 u_int32_t status; 1754 struct msk_status_desc *cur_st; 1755 1756 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1757 if (status == 0) { 1758 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1759 return (0); 1760 } 1761 1762 status = CSR_READ_4(sc, SK_ISR); 1763 1764 if (sc_if0 != NULL) 1765 ifp0 = &sc_if0->arpcom.ac_if; 1766 if (sc_if1 != NULL) 1767 ifp1 = &sc_if1->arpcom.ac_if; 1768 1769 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1770 (ifp0->if_flags & IFF_RUNNING)) { 1771 msk_intr_yukon(sc_if0); 1772 } 1773 1774 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1775 (ifp1->if_flags & IFF_RUNNING)) { 1776 msk_intr_yukon(sc_if1); 1777 } 1778 1779 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1780 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1781 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1782 1783 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 1784 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1785 switch (cur_st->sk_opcode) { 1786 case SK_Y2_STOPC_RXSTAT: 1787 msk_rxeof(sc->sk_if[cur_st->sk_link], 1788 letoh16(cur_st->sk_len), 1789 letoh32(cur_st->sk_status)); 1790 SK_IF_WRITE_2(sc->sk_if[cur_st->sk_link], 0, 1791 SK_RXQ1_Y2_PREF_PUTIDX, 1792 sc->sk_if[cur_st->sk_link]->sk_cdata.sk_rx_prod); 1793 break; 1794 case SK_Y2_STOPC_TXSTAT: 1795 if (sc_if0) 1796 msk_txeof(sc_if0); 1797 if (sc_if1) 1798 msk_txeof(sc_if1); 1799 break; 1800 default: 1801 printf("opcode=0x%x\n", cur_st->sk_opcode); 1802 break; 1803 } 1804 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1805 1806 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1807 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1808 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1809 } 1810 1811 if (status & SK_Y2_IMR_BMU) { 1812 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1813 claimed = 1; 1814 } 1815 1816 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1817 1818 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1819 msk_start(ifp0); 1820 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1821 msk_start(ifp1); 1822 1823 return (claimed); 1824 } 1825 1826 void 1827 msk_init_yukon(struct sk_if_softc *sc_if) 1828 { 1829 u_int32_t v; 1830 u_int16_t reg; 1831 struct sk_softc *sc; 1832 int i; 1833 1834 sc = sc_if->sk_softc; 1835 1836 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1837 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1838 1839 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1840 1841 /* GMAC and GPHY Reset */ 1842 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1843 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1844 DELAY(1000); 1845 1846 DPRINTFN(6, ("msk_init_yukon: 2\n")); 1847 1848 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1849 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1850 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1851 1852 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1853 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1854 1855 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1856 1857 /* unused read of the interrupt source register */ 1858 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1859 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1860 1861 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1862 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1863 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1864 1865 /* MIB Counter Clear Mode set */ 1866 reg |= YU_PAR_MIB_CLR; 1867 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1868 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1869 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1870 1871 /* MIB Counter Clear Mode clear */ 1872 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1873 reg &= ~YU_PAR_MIB_CLR; 1874 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1875 1876 /* receive control reg */ 1877 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1878 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1879 1880 /* transmit parameter register */ 1881 DPRINTFN(6, ("msk_init_yukon: 8\n")); 1882 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 1883 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 1884 1885 /* serial mode register */ 1886 DPRINTFN(6, ("msk_init_yukon: 9\n")); 1887 reg = YU_SMR_DATA_BLIND(0x1c) | 1888 YU_SMR_MFL_VLAN | 1889 YU_SMR_IPG_DATA(0x1e); 1890 1891 if (sc->sk_type != SK_YUKON_FE) 1892 reg |= YU_SMR_MFL_JUMBO; 1893 1894 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 1895 1896 DPRINTFN(6, ("msk_init_yukon: 10\n")); 1897 /* Setup Yukon's address */ 1898 for (i = 0; i < 3; i++) { 1899 /* Write Source Address 1 (unicast filter) */ 1900 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 1901 sc_if->arpcom.ac_enaddr[i * 2] | 1902 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 1903 } 1904 1905 for (i = 0; i < 3; i++) { 1906 reg = sk_win_read_2(sc_if->sk_softc, 1907 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 1908 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 1909 } 1910 1911 /* Set promiscuous mode */ 1912 msk_setpromisc(sc_if); 1913 1914 /* Set multicast filter */ 1915 DPRINTFN(6, ("msk_init_yukon: 11\n")); 1916 msk_setmulti(sc_if); 1917 1918 /* enable interrupt mask for counter overflows */ 1919 DPRINTFN(6, ("msk_init_yukon: 12\n")); 1920 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 1921 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 1922 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 1923 1924 /* Configure RX MAC FIFO Flush Mask */ 1925 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 1926 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 1927 YU_RXSTAT_JABBER; 1928 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 1929 1930 /* Configure RX MAC FIFO */ 1931 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 1932 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 1933 SK_RFCTL_FIFO_FLUSH_ON); 1934 1935 /* Increase flush threshould to 64 bytes */ 1936 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 1937 SK_RFCTL_FIFO_THRESHOLD + 1); 1938 1939 /* Configure TX MAC FIFO */ 1940 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 1941 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 1942 1943 #if 1 1944 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 1945 #endif 1946 DPRINTFN(6, ("msk_init_yukon: end\n")); 1947 } 1948 1949 /* 1950 * Note that to properly initialize any part of the GEnesis chip, 1951 * you first have to take it out of reset mode. 1952 */ 1953 void 1954 msk_init(void *xsc_if) 1955 { 1956 struct sk_if_softc *sc_if = xsc_if; 1957 struct sk_softc *sc = sc_if->sk_softc; 1958 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1959 struct mii_data *mii = &sc_if->sk_mii; 1960 int s; 1961 1962 DPRINTFN(2, ("msk_init\n")); 1963 1964 s = splnet(); 1965 1966 /* Cancel pending I/O and free all RX/TX buffers. */ 1967 msk_stop(sc_if); 1968 1969 /* Configure I2C registers */ 1970 1971 /* Configure XMAC(s) */ 1972 msk_init_yukon(sc_if); 1973 mii_mediachg(mii); 1974 1975 /* Configure transmit arbiter(s) */ 1976 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 1977 #if 0 1978 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 1979 #endif 1980 1981 /* Configure RAMbuffers */ 1982 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 1983 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 1984 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 1985 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 1986 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 1987 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 1988 1989 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 1990 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 1991 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 1992 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 1993 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 1994 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 1995 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 1996 1997 /* Configure BMUs */ 1998 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 1999 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2000 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2001 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_WATERMARK, 0x00000600); 2002 2003 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2004 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2005 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2006 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_WATERMARK, 0x00000600); 2007 2008 /* Make sure the sync transmit queue is disabled. */ 2009 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2010 2011 /* Init descriptors */ 2012 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2013 printf("%s: initialization failed: no " 2014 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2015 msk_stop(sc_if); 2016 splx(s); 2017 return; 2018 } 2019 2020 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2021 printf("%s: initialization failed: no " 2022 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2023 msk_stop(sc_if); 2024 splx(s); 2025 return; 2026 } 2027 2028 /* Initialize prefetch engine. */ 2029 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2030 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2031 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2032 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2033 MSK_RX_RING_ADDR(sc_if, 0)); 2034 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2035 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2036 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2037 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2038 2039 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2040 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2041 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2042 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2043 MSK_TX_RING_ADDR(sc_if, 0)); 2044 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2045 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2046 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2047 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2048 2049 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2050 sc_if->sk_cdata.sk_rx_prod); 2051 2052 /* Configure interrupt handling */ 2053 if (sc_if->sk_port == SK_PORT_A) 2054 sc->sk_intrmask |= SK_Y2_INTRS1; 2055 else 2056 sc->sk_intrmask |= SK_Y2_INTRS2; 2057 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2058 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2059 2060 ifp->if_flags |= IFF_RUNNING; 2061 ifp->if_flags &= ~IFF_OACTIVE; 2062 2063 timeout_add(&sc_if->sk_tick_ch, hz); 2064 2065 splx(s); 2066 } 2067 2068 void 2069 msk_stop(struct sk_if_softc *sc_if) 2070 { 2071 struct sk_softc *sc = sc_if->sk_softc; 2072 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2073 struct sk_txmap_entry *dma; 2074 int i; 2075 2076 DPRINTFN(2, ("msk_stop\n")); 2077 2078 timeout_del(&sc_if->sk_tick_ch); 2079 2080 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2081 2082 /* Stop transfer of Tx descriptors */ 2083 2084 /* Stop transfer of Rx descriptors */ 2085 2086 /* Turn off various components of this interface. */ 2087 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2088 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2089 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2090 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2091 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2092 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2093 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2094 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2095 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2096 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2097 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2098 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2099 2100 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2101 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2102 2103 /* Disable interrupts */ 2104 if (sc_if->sk_port == SK_PORT_A) 2105 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2106 else 2107 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2108 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2109 2110 SK_XM_READ_2(sc_if, XM_ISR); 2111 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2112 2113 /* Free RX and TX mbufs still in the queues. */ 2114 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2115 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2116 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2117 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2118 } 2119 } 2120 2121 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2122 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2123 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2124 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2125 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2126 sc_if->sk_cdata.sk_tx_map[i], link); 2127 sc_if->sk_cdata.sk_tx_map[i] = 0; 2128 } 2129 } 2130 2131 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2132 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2133 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2134 free(dma, M_DEVBUF); 2135 } 2136 } 2137 2138 struct cfattach mskc_ca = { 2139 sizeof(struct sk_softc), mskc_probe, mskc_attach, 2140 }; 2141 2142 struct cfdriver mskc_cd = { 2143 0, "mskc", DV_DULL 2144 }; 2145 2146 struct cfattach msk_ca = { 2147 sizeof(struct sk_if_softc), msk_probe, msk_attach, 2148 }; 2149 2150 struct cfdriver msk_cd = { 2151 0, "msk", DV_IFNET 2152 }; 2153 2154 #ifdef MSK_DEBUG 2155 void 2156 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2157 { 2158 #define DESC_PRINT(X) \ 2159 if (X) \ 2160 printf("txdesc[%d]." #X "=%#x\n", \ 2161 idx, X); 2162 2163 DESC_PRINT(letoh32(le->sk_addr)); 2164 DESC_PRINT(letoh16(le->sk_len)); 2165 DESC_PRINT(le->sk_ctl); 2166 DESC_PRINT(le->sk_opcode); 2167 #undef DESC_PRINT 2168 } 2169 2170 void 2171 msk_dump_bytes(const char *data, int len) 2172 { 2173 int c, i, j; 2174 2175 for (i = 0; i < len; i += 16) { 2176 printf("%08x ", i); 2177 c = len - i; 2178 if (c > 16) c = 16; 2179 2180 for (j = 0; j < c; j++) { 2181 printf("%02x ", data[i + j] & 0xff); 2182 if ((j & 0xf) == 7 && j > 0) 2183 printf(" "); 2184 } 2185 2186 for (; j < 16; j++) 2187 printf(" "); 2188 printf(" "); 2189 2190 for (j = 0; j < c; j++) { 2191 int ch = data[i + j] & 0xff; 2192 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2193 } 2194 2195 printf("\n"); 2196 2197 if (c < 16) 2198 break; 2199 } 2200 } 2201 2202 void 2203 msk_dump_mbuf(struct mbuf *m) 2204 { 2205 int count = m->m_pkthdr.len; 2206 2207 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2208 2209 while (count > 0 && m) { 2210 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2211 m, m->m_data, m->m_len); 2212 msk_dump_bytes(mtod(m, char *), m->m_len); 2213 2214 count -= m->m_len; 2215 m = m->m_next; 2216 } 2217 } 2218 #endif 2219