1 /* $OpenBSD: if_msk.c,v 1.105 2014/07/12 18:48:51 tedu Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include "bpfilter.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/timeout.h> 99 #include <sys/device.h> 100 #include <sys/queue.h> 101 102 #include <net/if.h> 103 #include <net/if_dl.h> 104 #include <net/if_types.h> 105 106 #ifdef INET 107 #include <netinet/in.h> 108 #include <netinet/in_systm.h> 109 #include <netinet/ip.h> 110 #include <netinet/udp.h> 111 #include <netinet/tcp.h> 112 #include <netinet/if_ether.h> 113 #endif 114 115 #include <net/if_media.h> 116 #include <net/if_vlan_var.h> 117 118 #if NBPFILTER > 0 119 #include <net/bpf.h> 120 #endif 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/brgphyreg.h> 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 #include <dev/pci/pcidevs.h> 129 130 #include <dev/pci/if_skreg.h> 131 #include <dev/pci/if_mskvar.h> 132 133 int mskc_probe(struct device *, void *, void *); 134 void mskc_attach(struct device *, struct device *self, void *aux); 135 int mskc_detach(struct device *, int); 136 int mskc_activate(struct device *, int); 137 void mskc_reset(struct sk_softc *); 138 int msk_probe(struct device *, void *, void *); 139 void msk_attach(struct device *, struct device *self, void *aux); 140 int msk_detach(struct device *, int); 141 int msk_activate(struct device *, int); 142 void msk_reset(struct sk_if_softc *); 143 int mskcprint(void *, const char *); 144 int msk_intr(void *); 145 void msk_intr_yukon(struct sk_if_softc *); 146 static __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 147 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 148 void msk_txeof(struct sk_if_softc *); 149 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 150 void msk_start(struct ifnet *); 151 int msk_ioctl(struct ifnet *, u_long, caddr_t); 152 void msk_init(void *); 153 void msk_init_yukon(struct sk_if_softc *); 154 void msk_stop(struct sk_if_softc *, int); 155 void msk_watchdog(struct ifnet *); 156 int msk_ifmedia_upd(struct ifnet *); 157 void msk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 158 int msk_newbuf(struct sk_if_softc *); 159 int msk_init_rx_ring(struct sk_if_softc *); 160 int msk_init_tx_ring(struct sk_if_softc *); 161 void msk_fill_rx_ring(struct sk_if_softc *); 162 163 int msk_miibus_readreg(struct device *, int, int); 164 void msk_miibus_writereg(struct device *, int, int, int); 165 void msk_miibus_statchg(struct device *); 166 167 void msk_iff(struct sk_if_softc *); 168 void msk_tick(void *); 169 170 #ifdef MSK_DEBUG 171 #define DPRINTF(x) if (mskdebug) printf x 172 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 173 int mskdebug = 0; 174 175 void msk_dump_txdesc(struct msk_tx_desc *, int); 176 void msk_dump_mbuf(struct mbuf *); 177 void msk_dump_bytes(const char *, int); 178 #else 179 #define DPRINTF(x) 180 #define DPRINTFN(n,x) 181 #endif 182 183 /* supported device vendors */ 184 const struct pci_matchid mskc_devices[] = { 185 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 186 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 187 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 188 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8021CU }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8021X }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8022CU }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8022X }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 200 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 201 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 202 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 203 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 204 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 205 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 206 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 207 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 208 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 209 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 210 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8061CU }, 211 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8061X }, 212 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8062CU }, 213 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8062X }, 214 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 215 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 216 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 217 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 218 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 219 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 220 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 221 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 222 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 223 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Exx }, 224 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Sxx } 225 }; 226 227 static inline u_int32_t 228 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 229 { 230 return CSR_READ_4(sc, reg); 231 } 232 233 static inline u_int16_t 234 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 235 { 236 return CSR_READ_2(sc, reg); 237 } 238 239 static inline u_int8_t 240 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 241 { 242 return CSR_READ_1(sc, reg); 243 } 244 245 static inline void 246 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 247 { 248 CSR_WRITE_4(sc, reg, x); 249 } 250 251 static inline void 252 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 253 { 254 CSR_WRITE_2(sc, reg, x); 255 } 256 257 static inline void 258 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 259 { 260 CSR_WRITE_1(sc, reg, x); 261 } 262 263 int 264 msk_miibus_readreg(struct device *dev, int phy, int reg) 265 { 266 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 267 u_int16_t val; 268 int i; 269 270 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 271 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 272 273 for (i = 0; i < SK_TIMEOUT; i++) { 274 DELAY(1); 275 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 276 if (val & YU_SMICR_READ_VALID) 277 break; 278 } 279 280 if (i == SK_TIMEOUT) { 281 printf("%s: phy failed to come ready\n", 282 sc_if->sk_dev.dv_xname); 283 return (0); 284 } 285 286 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 287 SK_TIMEOUT)); 288 289 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 290 291 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 292 phy, reg, val)); 293 294 return (val); 295 } 296 297 void 298 msk_miibus_writereg(struct device *dev, int phy, int reg, int val) 299 { 300 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 301 int i; 302 303 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 304 phy, reg, val)); 305 306 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 307 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 308 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 309 310 for (i = 0; i < SK_TIMEOUT; i++) { 311 DELAY(1); 312 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 313 break; 314 } 315 316 if (i == SK_TIMEOUT) 317 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 318 } 319 320 void 321 msk_miibus_statchg(struct device *dev) 322 { 323 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 324 struct mii_data *mii = &sc_if->sk_mii; 325 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 326 int gpcr; 327 328 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 329 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 330 331 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 332 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 333 /* Set speed. */ 334 gpcr |= YU_GPCR_SPEED_DIS; 335 switch (IFM_SUBTYPE(mii->mii_media_active)) { 336 case IFM_1000_SX: 337 case IFM_1000_LX: 338 case IFM_1000_CX: 339 case IFM_1000_T: 340 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 341 break; 342 case IFM_100_TX: 343 gpcr |= YU_GPCR_SPEED; 344 break; 345 } 346 347 /* Set duplex. */ 348 gpcr |= YU_GPCR_DPLX_DIS; 349 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 350 gpcr |= YU_GPCR_DUPLEX; 351 352 /* Disable flow control. */ 353 gpcr |= YU_GPCR_FCTL_DIS; 354 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 355 } 356 357 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 358 359 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 360 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 361 } 362 363 void 364 msk_iff(struct sk_if_softc *sc_if) 365 { 366 struct ifnet *ifp = &sc_if->arpcom.ac_if; 367 struct arpcom *ac = &sc_if->arpcom; 368 struct ether_multi *enm; 369 struct ether_multistep step; 370 u_int32_t hashes[2]; 371 u_int16_t rcr; 372 int h; 373 374 rcr = SK_YU_READ_2(sc_if, YUKON_RCR); 375 rcr &= ~(YU_RCR_MUFLEN | YU_RCR_UFLEN); 376 ifp->if_flags &= ~IFF_ALLMULTI; 377 378 /* 379 * Always accept frames destined to our station address. 380 */ 381 rcr |= YU_RCR_UFLEN; 382 383 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 384 ifp->if_flags |= IFF_ALLMULTI; 385 if (ifp->if_flags & IFF_PROMISC) 386 rcr &= ~YU_RCR_UFLEN; 387 else 388 rcr |= YU_RCR_MUFLEN; 389 hashes[0] = hashes[1] = 0xFFFFFFFF; 390 } else { 391 rcr |= YU_RCR_MUFLEN; 392 /* Program new filter. */ 393 bzero(hashes, sizeof(hashes)); 394 395 ETHER_FIRST_MULTI(step, ac, enm); 396 while (enm != NULL) { 397 h = ether_crc32_be(enm->enm_addrlo, 398 ETHER_ADDR_LEN) & ((1 << SK_HASH_BITS) - 1); 399 400 if (h < 32) 401 hashes[0] |= (1 << h); 402 else 403 hashes[1] |= (1 << (h - 32)); 404 405 ETHER_NEXT_MULTI(step, enm); 406 } 407 } 408 409 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 410 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 411 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 412 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 413 SK_YU_WRITE_2(sc_if, YUKON_RCR, rcr); 414 } 415 416 int 417 msk_init_rx_ring(struct sk_if_softc *sc_if) 418 { 419 struct msk_chain_data *cd = &sc_if->sk_cdata; 420 struct msk_ring_data *rd = sc_if->sk_rdata; 421 int i, nexti; 422 423 bzero(rd->sk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 424 425 for (i = 0; i < MSK_RX_RING_CNT; i++) { 426 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 427 if (i == (MSK_RX_RING_CNT - 1)) 428 nexti = 0; 429 else 430 nexti = i + 1; 431 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 432 } 433 434 sc_if->sk_cdata.sk_rx_prod = 0; 435 sc_if->sk_cdata.sk_rx_cons = 0; 436 437 if_rxr_init(&sc_if->sk_cdata.sk_rx_ring, 2, MSK_RX_RING_CNT); 438 439 msk_fill_rx_ring(sc_if); 440 return (0); 441 } 442 443 int 444 msk_init_tx_ring(struct sk_if_softc *sc_if) 445 { 446 struct sk_softc *sc = sc_if->sk_softc; 447 struct msk_chain_data *cd = &sc_if->sk_cdata; 448 struct msk_ring_data *rd = sc_if->sk_rdata; 449 bus_dmamap_t dmamap; 450 struct sk_txmap_entry *entry; 451 int i, nexti; 452 453 bzero(sc_if->sk_rdata->sk_tx_ring, 454 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 455 456 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 457 for (i = 0; i < MSK_TX_RING_CNT; i++) { 458 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 459 if (i == (MSK_TX_RING_CNT - 1)) 460 nexti = 0; 461 else 462 nexti = i + 1; 463 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 464 465 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 466 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 467 return (ENOBUFS); 468 469 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 470 if (!entry) { 471 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 472 return (ENOBUFS); 473 } 474 entry->dmamap = dmamap; 475 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 476 } 477 478 sc_if->sk_cdata.sk_tx_prod = 0; 479 sc_if->sk_cdata.sk_tx_cons = 0; 480 sc_if->sk_cdata.sk_tx_cnt = 0; 481 482 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 483 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 484 485 return (0); 486 } 487 488 int 489 msk_newbuf(struct sk_if_softc *sc_if) 490 { 491 struct sk_chain *c; 492 struct msk_rx_desc *r; 493 struct mbuf *m; 494 bus_dmamap_t dmamap; 495 int error; 496 int i, head; 497 498 m = MCLGETI(NULL, M_DONTWAIT, NULL, sc_if->sk_pktlen); 499 if (m == NULL) 500 return (0); 501 m->m_len = m->m_pkthdr.len = sc_if->sk_pktlen; 502 m_adj(m, ETHER_ALIGN); 503 504 dmamap = sc_if->sk_cdata.sk_rx_map[sc_if->sk_cdata.sk_rx_prod]; 505 506 error = bus_dmamap_load_mbuf(sc_if->sk_softc->sc_dmatag, dmamap, m, 507 BUS_DMA_READ|BUS_DMA_NOWAIT); 508 if (error) { 509 m_freem(m); 510 return (0); 511 } 512 513 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 514 dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 515 516 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 517 head = sc_if->sk_cdata.sk_rx_prod; 518 r = c->sk_le; 519 c->sk_mbuf = m; 520 521 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr); 522 r->sk_len = htole16(dmamap->dm_segs[0].ds_len); 523 r->sk_ctl = 0; 524 525 MSK_CDRXSYNC(sc_if, head, BUS_DMASYNC_PREWRITE); 526 527 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 528 529 for (i = 1; i < dmamap->dm_nsegs; i++) { 530 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 531 r = c->sk_le; 532 c->sk_mbuf = NULL; 533 534 r->sk_addr = htole32(dmamap->dm_segs[i].ds_addr); 535 r->sk_len = htole16(dmamap->dm_segs[i].ds_len); 536 r->sk_ctl = 0; 537 538 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 539 BUS_DMASYNC_PREWRITE); 540 541 r->sk_opcode = SK_Y2_RXOPC_BUFFER | SK_Y2_RXOPC_OWN; 542 543 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 544 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 545 546 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 547 } 548 549 c = &sc_if->sk_cdata.sk_rx_chain[head]; 550 r = c->sk_le; 551 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 552 553 MSK_CDRXSYNC(sc_if, head, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 554 555 return (dmamap->dm_nsegs); 556 } 557 558 /* 559 * Set media options. 560 */ 561 int 562 msk_ifmedia_upd(struct ifnet *ifp) 563 { 564 struct sk_if_softc *sc_if = ifp->if_softc; 565 566 mii_mediachg(&sc_if->sk_mii); 567 return (0); 568 } 569 570 /* 571 * Report current media status. 572 */ 573 void 574 msk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 575 { 576 struct sk_if_softc *sc_if = ifp->if_softc; 577 578 mii_pollstat(&sc_if->sk_mii); 579 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 580 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 581 } 582 583 int 584 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 585 { 586 struct sk_if_softc *sc_if = ifp->if_softc; 587 struct ifaddr *ifa = (struct ifaddr *) data; 588 struct ifreq *ifr = (struct ifreq *) data; 589 struct mii_data *mii; 590 int s, error = 0; 591 592 s = splnet(); 593 594 switch(command) { 595 case SIOCSIFADDR: 596 ifp->if_flags |= IFF_UP; 597 if (!(ifp->if_flags & IFF_RUNNING)) 598 msk_init(sc_if); 599 #ifdef INET 600 if (ifa->ifa_addr->sa_family == AF_INET) 601 arp_ifinit(&sc_if->arpcom, ifa); 602 #endif 603 break; 604 605 case SIOCSIFFLAGS: 606 if (ifp->if_flags & IFF_UP) { 607 if (ifp->if_flags & IFF_RUNNING) 608 error = ENETRESET; 609 else 610 msk_init(sc_if); 611 } else { 612 if (ifp->if_flags & IFF_RUNNING) 613 msk_stop(sc_if, 0); 614 } 615 break; 616 617 case SIOCGIFMEDIA: 618 case SIOCSIFMEDIA: 619 mii = &sc_if->sk_mii; 620 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 621 break; 622 623 default: 624 error = ether_ioctl(ifp, &sc_if->arpcom, command, data); 625 } 626 627 if (error == ENETRESET) { 628 if (ifp->if_flags & IFF_RUNNING) 629 msk_iff(sc_if); 630 error = 0; 631 } 632 633 splx(s); 634 return (error); 635 } 636 637 /* 638 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 639 * IDs against our list and return a device name if we find a match. 640 */ 641 int 642 mskc_probe(struct device *parent, void *match, void *aux) 643 { 644 return (pci_matchbyid((struct pci_attach_args *)aux, mskc_devices, 645 nitems(mskc_devices))); 646 } 647 648 /* 649 * Force the GEnesis into reset, then bring it out of reset. 650 */ 651 void 652 mskc_reset(struct sk_softc *sc) 653 { 654 u_int32_t imtimer_ticks, reg1; 655 int reg; 656 657 DPRINTFN(2, ("mskc_reset\n")); 658 659 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 660 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 661 662 DELAY(1000); 663 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 664 DELAY(2); 665 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 666 667 sk_win_write_1(sc, SK_TESTCTL1, 2); 668 669 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 670 sc->sk_type >= SK_YUKON_FE_P) { 671 /* enable all clocks. */ 672 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 673 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 674 reg1 &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 675 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 676 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 677 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 678 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), reg1); 679 680 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5)); 681 reg1 &= SK_Y2_REG5_TIM_VMAIN_AV_MASK; 682 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), reg1); 683 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_CFGREG1), 0); 684 685 /* 686 * Disable status race, workaround for Yukon EC Ultra & 687 * Yukon EX. 688 */ 689 reg1 = sk_win_read_4(sc, SK_GPIO); 690 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 691 sk_win_write_4(sc, SK_GPIO, reg1); 692 sk_win_read_4(sc, SK_GPIO); 693 } 694 695 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 696 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 697 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 698 else 699 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 700 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 701 702 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 703 sk_win_write_1(sc, SK_Y2_CLKGATE, 704 SK_Y2_CLKGATE_LINK1_GATE_DIS | 705 SK_Y2_CLKGATE_LINK2_GATE_DIS | 706 SK_Y2_CLKGATE_LINK1_CORE_DIS | 707 SK_Y2_CLKGATE_LINK2_CORE_DIS | 708 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 709 else 710 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 711 712 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 713 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 714 DELAY(1000); 715 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 716 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 717 718 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 719 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 720 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 721 } 722 723 sk_win_write_1(sc, SK_TESTCTL1, 1); 724 725 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 726 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 727 CSR_READ_2(sc, SK_LINK_CTRL))); 728 729 /* Disable ASF */ 730 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 731 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 732 733 /* Clear I2C IRQ noise */ 734 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 735 736 /* Disable hardware timer */ 737 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 738 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 739 740 /* Disable descriptor polling */ 741 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 742 743 /* Disable time stamps */ 744 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 745 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 746 747 /* Enable RAM interface */ 748 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 749 for (reg = SK_TO0;reg <= SK_TO11; reg++) 750 sk_win_write_1(sc, reg, 36); 751 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 752 for (reg = SK_TO0;reg <= SK_TO11; reg++) 753 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 754 755 /* 756 * Configure interrupt moderation. The moderation timer 757 * defers interrupts specified in the interrupt moderation 758 * timer mask based on the timeout specified in the interrupt 759 * moderation timer init register. Each bit in the timer 760 * register represents one tick, so to specify a timeout in 761 * microseconds, we have to multiply by the correct number of 762 * ticks-per-microsecond. 763 */ 764 switch (sc->sk_type) { 765 case SK_YUKON_EC: 766 case SK_YUKON_EC_U: 767 case SK_YUKON_EX: 768 case SK_YUKON_SUPR: 769 case SK_YUKON_ULTRA2: 770 case SK_YUKON_OPTIMA: 771 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 772 break; 773 case SK_YUKON_FE: 774 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 775 break; 776 case SK_YUKON_FE_P: 777 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 778 break; 779 case SK_YUKON_XL: 780 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 781 break; 782 default: 783 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 784 break; 785 } 786 787 /* Reset status ring. */ 788 bzero(sc->sk_status_ring, 789 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 790 sc->sk_status_idx = 0; 791 792 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 793 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 794 795 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 796 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 797 sc->sk_status_map->dm_segs[0].ds_addr); 798 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 799 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 800 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 10); 801 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 16); 802 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 16); 803 804 #if 0 805 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 806 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 807 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(20)); 808 #else 809 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(4)); 810 #endif 811 812 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 813 814 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 815 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 816 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 817 } 818 819 int 820 msk_probe(struct device *parent, void *match, void *aux) 821 { 822 struct skc_attach_args *sa = aux; 823 824 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 825 return (0); 826 827 switch (sa->skc_type) { 828 case SK_YUKON_XL: 829 case SK_YUKON_EC_U: 830 case SK_YUKON_EX: 831 case SK_YUKON_EC: 832 case SK_YUKON_FE: 833 case SK_YUKON_FE_P: 834 case SK_YUKON_SUPR: 835 case SK_YUKON_ULTRA2: 836 case SK_YUKON_OPTIMA: 837 return (1); 838 } 839 840 return (0); 841 } 842 843 void 844 msk_reset(struct sk_if_softc *sc_if) 845 { 846 /* GMAC and GPHY Reset */ 847 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 848 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 849 DELAY(1000); 850 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 851 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 852 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 853 } 854 855 /* 856 * Each XMAC chip is attached as a separate logical IP interface. 857 * Single port cards will have only one logical interface of course. 858 */ 859 void 860 msk_attach(struct device *parent, struct device *self, void *aux) 861 { 862 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 863 struct sk_softc *sc = (struct sk_softc *)parent; 864 struct skc_attach_args *sa = aux; 865 struct ifnet *ifp; 866 caddr_t kva; 867 int i; 868 u_int32_t chunk; 869 int mii_flags; 870 int error; 871 872 sc_if->sk_port = sa->skc_port; 873 sc_if->sk_softc = sc; 874 sc->sk_if[sa->skc_port] = sc_if; 875 876 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 877 878 /* 879 * Get station address for this interface. Note that 880 * dual port cards actually come with three station 881 * addresses: one for each port, plus an extra. The 882 * extra one is used by the SysKonnect driver software 883 * as a 'virtual' station address for when both ports 884 * are operating in failover mode. Currently we don't 885 * use this extra address. 886 */ 887 for (i = 0; i < ETHER_ADDR_LEN; i++) 888 sc_if->arpcom.ac_enaddr[i] = 889 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 890 891 printf(": address %s\n", 892 ether_sprintf(sc_if->arpcom.ac_enaddr)); 893 894 /* 895 * Set up RAM buffer addresses. The Yukon2 has a small amount 896 * of SRAM on it, somewhere between 4K and 48K. We need to 897 * divide this up between the transmitter and receiver. We 898 * give the receiver 2/3 of the memory (rounded down), and the 899 * transmitter whatever remains. 900 */ 901 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 902 sc_if->sk_rx_ramstart = 0; 903 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 904 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 905 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 906 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 907 908 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 909 " tx_ramstart=%#x tx_ramend=%#x\n", 910 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 911 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 912 913 /* Allocate the descriptor queues. */ 914 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 915 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 916 BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 917 printf(": can't alloc rx buffers\n"); 918 goto fail; 919 } 920 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 921 sc_if->sk_ring_nseg, 922 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 923 printf(": can't map dma buffers (%lu bytes)\n", 924 (ulong)sizeof(struct msk_ring_data)); 925 goto fail_1; 926 } 927 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 928 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 929 &sc_if->sk_ring_map)) { 930 printf(": can't create dma map\n"); 931 goto fail_2; 932 } 933 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 934 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 935 printf(": can't load dma map\n"); 936 goto fail_3; 937 } 938 sc_if->sk_rdata = (struct msk_ring_data *)kva; 939 940 if (sc->sk_type != SK_YUKON_FE && 941 sc->sk_type != SK_YUKON_FE_P) 942 sc_if->sk_pktlen = SK_JLEN; 943 else 944 sc_if->sk_pktlen = MCLBYTES; 945 946 for (i = 0; i < MSK_RX_RING_CNT; i++) { 947 if ((error = bus_dmamap_create(sc->sc_dmatag, 948 sc_if->sk_pktlen, SK_NRXSEG, sc_if->sk_pktlen, 949 0, 0, &sc_if->sk_cdata.sk_rx_map[i])) != 0) { 950 printf("\n%s: unable to create rx DMA map %d, " 951 "error = %d\n", sc->sk_dev.dv_xname, i, error); 952 goto fail_4; 953 } 954 } 955 956 ifp = &sc_if->arpcom.ac_if; 957 ifp->if_softc = sc_if; 958 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 959 ifp->if_ioctl = msk_ioctl; 960 ifp->if_start = msk_start; 961 ifp->if_watchdog = msk_watchdog; 962 if (sc->sk_type != SK_YUKON_FE && 963 sc->sk_type != SK_YUKON_FE_P) 964 ifp->if_hardmtu = SK_JUMBO_MTU; 965 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 966 IFQ_SET_READY(&ifp->if_snd); 967 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 968 969 ifp->if_capabilities = IFCAP_VLAN_MTU; 970 971 msk_reset(sc_if); 972 973 /* 974 * Do miibus setup. 975 */ 976 msk_init_yukon(sc_if); 977 978 DPRINTFN(2, ("msk_attach: 1\n")); 979 980 sc_if->sk_mii.mii_ifp = ifp; 981 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 982 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 983 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 984 985 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 986 msk_ifmedia_upd, msk_ifmedia_sts); 987 mii_flags = MIIF_DOPAUSE; 988 if (sc->sk_fibertype) 989 mii_flags |= MIIF_HAVEFIBER; 990 mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0, 991 MII_OFFSET_ANY, mii_flags); 992 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 993 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 994 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 995 0, NULL); 996 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 997 } else 998 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 999 1000 timeout_set(&sc_if->sk_tick_ch, msk_tick, sc_if); 1001 1002 /* 1003 * Call MI attach routines. 1004 */ 1005 if_attach(ifp); 1006 ether_ifattach(ifp); 1007 1008 DPRINTFN(2, ("msk_attach: end\n")); 1009 return; 1010 1011 fail_4: 1012 for (i = 0; i < MSK_RX_RING_CNT; i++) { 1013 if (sc_if->sk_cdata.sk_rx_map[i] != NULL) 1014 bus_dmamap_destroy(sc->sc_dmatag, 1015 sc_if->sk_cdata.sk_rx_map[i]); 1016 } 1017 1018 fail_3: 1019 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1020 fail_2: 1021 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1022 fail_1: 1023 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1024 fail: 1025 sc->sk_if[sa->skc_port] = NULL; 1026 } 1027 1028 int 1029 msk_detach(struct device *self, int flags) 1030 { 1031 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 1032 struct sk_softc *sc = sc_if->sk_softc; 1033 struct ifnet *ifp= &sc_if->arpcom.ac_if; 1034 1035 if (sc->sk_if[sc_if->sk_port] == NULL) 1036 return (0); 1037 1038 msk_stop(sc_if, 1); 1039 1040 /* Detach any PHYs we might have. */ 1041 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1042 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1043 1044 /* Delete any remaining media. */ 1045 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1046 1047 ether_ifdetach(ifp); 1048 if_detach(ifp); 1049 1050 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc_if->sk_rdata, 1051 sizeof(struct msk_ring_data)); 1052 bus_dmamem_free(sc->sc_dmatag, 1053 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1054 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1055 sc->sk_if[sc_if->sk_port] = NULL; 1056 1057 return (0); 1058 } 1059 1060 int 1061 msk_activate(struct device *self, int act) 1062 { 1063 struct sk_if_softc *sc_if = (void *)self; 1064 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1065 int rv = 0; 1066 1067 switch (act) { 1068 case DVACT_RESUME: 1069 msk_reset(sc_if); 1070 if (ifp->if_flags & IFF_RUNNING) 1071 msk_init(sc_if); 1072 break; 1073 default: 1074 rv = config_activate_children(self, act); 1075 break; 1076 } 1077 return (rv); 1078 } 1079 1080 int 1081 mskcprint(void *aux, const char *pnp) 1082 { 1083 struct skc_attach_args *sa = aux; 1084 1085 if (pnp) 1086 printf("msk port %c at %s", 1087 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1088 else 1089 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1090 return (UNCONF); 1091 } 1092 1093 /* 1094 * Attach the interface. Allocate softc structures, do ifmedia 1095 * setup and ethernet/BPF attach. 1096 */ 1097 void 1098 mskc_attach(struct device *parent, struct device *self, void *aux) 1099 { 1100 struct sk_softc *sc = (struct sk_softc *)self; 1101 struct pci_attach_args *pa = aux; 1102 struct skc_attach_args skca; 1103 pci_chipset_tag_t pc = pa->pa_pc; 1104 pcireg_t memtype; 1105 pci_intr_handle_t ih; 1106 const char *intrstr = NULL; 1107 u_int8_t hw, pmd; 1108 char *revstr = NULL; 1109 caddr_t kva; 1110 1111 DPRINTFN(2, ("begin mskc_attach\n")); 1112 1113 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 1114 1115 /* 1116 * Map control/status registers. 1117 */ 1118 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1119 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1120 &sc->sk_bhandle, NULL, &sc->sk_bsize, 0)) { 1121 printf(": can't map mem space\n"); 1122 return; 1123 } 1124 1125 sc->sc_dmatag = pa->pa_dmat; 1126 1127 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1128 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1129 1130 /* bail out here if chip is not recognized */ 1131 if (!(SK_IS_YUKON2(sc))) { 1132 printf(": unknown chip type: %d\n", sc->sk_type); 1133 goto fail_1; 1134 } 1135 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1136 1137 /* Allocate interrupt */ 1138 if (pci_intr_map(pa, &ih)) { 1139 printf(": couldn't map interrupt\n"); 1140 goto fail_1; 1141 } 1142 1143 intrstr = pci_intr_string(pc, ih); 1144 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc, 1145 self->dv_xname); 1146 if (sc->sk_intrhand == NULL) { 1147 printf(": couldn't establish interrupt"); 1148 if (intrstr != NULL) 1149 printf(" at %s", intrstr); 1150 printf("\n"); 1151 goto fail_1; 1152 } 1153 sc->sk_pc = pc; 1154 1155 if (bus_dmamem_alloc(sc->sc_dmatag, 1156 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1157 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1158 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, 1159 BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 1160 printf(": can't alloc status buffers\n"); 1161 goto fail_2; 1162 } 1163 1164 if (bus_dmamem_map(sc->sc_dmatag, 1165 &sc->sk_status_seg, sc->sk_status_nseg, 1166 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1167 &kva, BUS_DMA_NOWAIT)) { 1168 printf(": can't map dma buffers (%lu bytes)\n", 1169 (ulong)(MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc))); 1170 goto fail_3; 1171 } 1172 if (bus_dmamap_create(sc->sc_dmatag, 1173 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1174 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1175 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1176 printf(": can't create dma map\n"); 1177 goto fail_4; 1178 } 1179 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1180 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1181 NULL, BUS_DMA_NOWAIT)) { 1182 printf(": can't load dma map\n"); 1183 goto fail_5; 1184 } 1185 sc->sk_status_ring = (struct msk_status_desc *)kva; 1186 1187 /* Reset the adapter. */ 1188 mskc_reset(sc); 1189 1190 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1191 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1192 1193 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1194 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1195 sc->sk_fibertype = 1; 1196 1197 switch (sc->sk_type) { 1198 case SK_YUKON_XL: 1199 sc->sk_name = "Yukon-2 XL"; 1200 break; 1201 case SK_YUKON_EC_U: 1202 sc->sk_name = "Yukon-2 EC Ultra"; 1203 break; 1204 case SK_YUKON_EX: 1205 sc->sk_name = "Yukon-2 Extreme"; 1206 break; 1207 case SK_YUKON_EC: 1208 sc->sk_name = "Yukon-2 EC"; 1209 break; 1210 case SK_YUKON_FE: 1211 sc->sk_name = "Yukon-2 FE"; 1212 break; 1213 case SK_YUKON_FE_P: 1214 sc->sk_name = "Yukon-2 FE+"; 1215 break; 1216 case SK_YUKON_SUPR: 1217 sc->sk_name = "Yukon-2 Supreme"; 1218 break; 1219 case SK_YUKON_ULTRA2: 1220 sc->sk_name = "Yukon-2 Ultra2"; 1221 break; 1222 case SK_YUKON_OPTIMA: 1223 sc->sk_name = "Yukon-2 Optima"; 1224 break; 1225 default: 1226 sc->sk_name = "Yukon (Unknown)"; 1227 } 1228 1229 if (sc->sk_type == SK_YUKON_XL) { 1230 switch (sc->sk_rev) { 1231 case SK_YUKON_XL_REV_A0: 1232 revstr = "A0"; 1233 break; 1234 case SK_YUKON_XL_REV_A1: 1235 revstr = "A1"; 1236 break; 1237 case SK_YUKON_XL_REV_A2: 1238 revstr = "A2"; 1239 break; 1240 case SK_YUKON_XL_REV_A3: 1241 revstr = "A3"; 1242 break; 1243 default: 1244 ; 1245 } 1246 } 1247 1248 if (sc->sk_type == SK_YUKON_EC) { 1249 switch (sc->sk_rev) { 1250 case SK_YUKON_EC_REV_A1: 1251 revstr = "A1"; 1252 break; 1253 case SK_YUKON_EC_REV_A2: 1254 revstr = "A2"; 1255 break; 1256 case SK_YUKON_EC_REV_A3: 1257 revstr = "A3"; 1258 break; 1259 default: 1260 ; 1261 } 1262 } 1263 1264 if (sc->sk_type == SK_YUKON_EC_U) { 1265 switch (sc->sk_rev) { 1266 case SK_YUKON_EC_U_REV_A0: 1267 revstr = "A0"; 1268 break; 1269 case SK_YUKON_EC_U_REV_A1: 1270 revstr = "A1"; 1271 break; 1272 case SK_YUKON_EC_U_REV_B0: 1273 revstr = "B0"; 1274 break; 1275 default: 1276 ; 1277 } 1278 } 1279 1280 if (sc->sk_type == SK_YUKON_FE) { 1281 switch (sc->sk_rev) { 1282 case SK_YUKON_FE_REV_A1: 1283 revstr = "A1"; 1284 break; 1285 case SK_YUKON_FE_REV_A2: 1286 revstr = "A2"; 1287 break; 1288 default: 1289 ; 1290 } 1291 } 1292 1293 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1294 revstr = "A0"; 1295 1296 if (sc->sk_type == SK_YUKON_EX) { 1297 switch (sc->sk_rev) { 1298 case SK_YUKON_EX_REV_A0: 1299 revstr = "A0"; 1300 break; 1301 case SK_YUKON_EX_REV_B0: 1302 revstr = "B0"; 1303 break; 1304 default: 1305 ; 1306 } 1307 } 1308 1309 if (sc->sk_type == SK_YUKON_SUPR && sc->sk_rev == SK_YUKON_SUPR_REV_A0) 1310 revstr = "A0"; 1311 1312 1313 /* Announce the product name. */ 1314 printf(", %s", sc->sk_name); 1315 if (revstr != NULL) 1316 printf(" rev. %s", revstr); 1317 printf(" (0x%x): %s\n", sc->sk_rev, intrstr); 1318 1319 sc->sk_macs = 1; 1320 1321 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1322 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1323 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1324 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1325 sc->sk_macs++; 1326 } 1327 1328 skca.skc_port = SK_PORT_A; 1329 skca.skc_type = sc->sk_type; 1330 skca.skc_rev = sc->sk_rev; 1331 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1332 1333 if (sc->sk_macs > 1) { 1334 skca.skc_port = SK_PORT_B; 1335 skca.skc_type = sc->sk_type; 1336 skca.skc_rev = sc->sk_rev; 1337 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1338 } 1339 1340 /* Turn on the 'driver is loaded' LED. */ 1341 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1342 1343 return; 1344 1345 fail_4: 1346 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sk_status_ring, 1347 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1348 fail_3: 1349 bus_dmamem_free(sc->sc_dmatag, 1350 &sc->sk_status_seg, sc->sk_status_nseg); 1351 sc->sk_status_nseg = 0; 1352 fail_5: 1353 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1354 fail_2: 1355 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1356 sc->sk_intrhand = NULL; 1357 fail_1: 1358 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1359 sc->sk_bsize = 0; 1360 } 1361 1362 int 1363 mskc_detach(struct device *self, int flags) 1364 { 1365 struct sk_softc *sc = (struct sk_softc *)self; 1366 int rv; 1367 1368 if (sc->sk_intrhand) 1369 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1370 1371 rv = config_detach_children(self, flags); 1372 if (rv != 0) 1373 return (rv); 1374 1375 if (sc->sk_status_nseg > 0) { 1376 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1377 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sk_status_ring, 1378 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1379 bus_dmamem_free(sc->sc_dmatag, 1380 &sc->sk_status_seg, sc->sk_status_nseg); 1381 } 1382 1383 if (sc->sk_bsize > 0) 1384 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1385 1386 return(0); 1387 } 1388 1389 int 1390 mskc_activate(struct device *self, int act) 1391 { 1392 struct sk_softc *sc = (void *)self; 1393 int rv = 0; 1394 1395 switch (act) { 1396 case DVACT_RESUME: 1397 mskc_reset(sc); 1398 rv = config_activate_children(self, act); 1399 break; 1400 default: 1401 rv = config_activate_children(self, act); 1402 break; 1403 } 1404 return (rv); 1405 } 1406 1407 int 1408 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1409 { 1410 struct sk_softc *sc = sc_if->sk_softc; 1411 struct msk_tx_desc *f = NULL; 1412 u_int32_t frag, cur; 1413 int i; 1414 struct sk_txmap_entry *entry; 1415 bus_dmamap_t txmap; 1416 1417 DPRINTFN(2, ("msk_encap\n")); 1418 1419 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1420 if (entry == NULL) { 1421 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1422 return (ENOBUFS); 1423 } 1424 txmap = entry->dmamap; 1425 1426 cur = frag = *txidx; 1427 1428 #ifdef MSK_DEBUG 1429 if (mskdebug >= 2) 1430 msk_dump_mbuf(m_head); 1431 #endif 1432 1433 /* 1434 * Start packing the mbufs in this chain into 1435 * the fragment pointers. Stop when we run out 1436 * of fragments or hit the end of the mbuf chain. 1437 */ 1438 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1439 BUS_DMA_NOWAIT)) { 1440 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1441 return (ENOBUFS); 1442 } 1443 1444 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1445 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1446 bus_dmamap_unload(sc->sc_dmatag, txmap); 1447 return (ENOBUFS); 1448 } 1449 1450 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1451 1452 /* Sync the DMA map. */ 1453 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1454 BUS_DMASYNC_PREWRITE); 1455 1456 for (i = 0; i < txmap->dm_nsegs; i++) { 1457 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1458 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1459 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1460 f->sk_ctl = 0; 1461 if (i == 0) 1462 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1463 else 1464 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1465 cur = frag; 1466 SK_INC(frag, MSK_TX_RING_CNT); 1467 } 1468 1469 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1470 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1471 1472 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1473 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1474 1475 /* Sync descriptors before handing to chip */ 1476 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1477 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1478 1479 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1480 1481 /* Sync first descriptor to hand it off */ 1482 MSK_CDTXSYNC(sc_if, *txidx, 1, 1483 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1484 1485 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1486 1487 #ifdef MSK_DEBUG 1488 if (mskdebug >= 2) { 1489 struct msk_tx_desc *le; 1490 u_int32_t idx; 1491 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1492 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1493 msk_dump_txdesc(le, idx); 1494 } 1495 } 1496 #endif 1497 1498 *txidx = frag; 1499 1500 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1501 1502 return (0); 1503 } 1504 1505 void 1506 msk_start(struct ifnet *ifp) 1507 { 1508 struct sk_if_softc *sc_if = ifp->if_softc; 1509 struct mbuf *m_head = NULL; 1510 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1511 int pkts = 0; 1512 1513 DPRINTFN(2, ("msk_start\n")); 1514 1515 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1516 IFQ_POLL(&ifp->if_snd, m_head); 1517 if (m_head == NULL) 1518 break; 1519 1520 /* 1521 * Pack the data into the transmit ring. If we 1522 * don't have room, set the OACTIVE flag and wait 1523 * for the NIC to drain the ring. 1524 */ 1525 if (msk_encap(sc_if, m_head, &idx)) { 1526 ifp->if_flags |= IFF_OACTIVE; 1527 break; 1528 } 1529 1530 /* now we are committed to transmit the packet */ 1531 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1532 pkts++; 1533 1534 /* 1535 * If there's a BPF listener, bounce a copy of this frame 1536 * to him. 1537 */ 1538 #if NBPFILTER > 0 1539 if (ifp->if_bpf) 1540 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1541 #endif 1542 } 1543 if (pkts == 0) 1544 return; 1545 1546 /* Transmit */ 1547 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1548 sc_if->sk_cdata.sk_tx_prod = idx; 1549 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1550 1551 /* Set a timeout in case the chip goes out to lunch. */ 1552 ifp->if_timer = 5; 1553 } 1554 } 1555 1556 void 1557 msk_watchdog(struct ifnet *ifp) 1558 { 1559 struct sk_if_softc *sc_if = ifp->if_softc; 1560 1561 /* 1562 * Reclaim first as there is a possibility of losing Tx completion 1563 * interrupts. 1564 */ 1565 msk_txeof(sc_if); 1566 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1567 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1568 1569 ifp->if_oerrors++; 1570 1571 /* XXX Resets both ports; we shouldn't do that. */ 1572 mskc_reset(sc_if->sk_softc); 1573 msk_reset(sc_if); 1574 msk_init(sc_if); 1575 } 1576 } 1577 1578 static __inline int 1579 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1580 { 1581 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1582 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1583 YU_RXSTAT_JABBER)) != 0 || 1584 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1585 YU_RXSTAT_BYTES(stat) != len) 1586 return (0); 1587 1588 return (1); 1589 } 1590 1591 void 1592 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1593 { 1594 struct sk_softc *sc = sc_if->sk_softc; 1595 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1596 struct mbuf *m; 1597 struct sk_chain *cur_rx; 1598 int i, cur, total_len = len; 1599 bus_dmamap_t dmamap; 1600 1601 DPRINTFN(2, ("msk_rxeof\n")); 1602 1603 cur = sc_if->sk_cdata.sk_rx_cons; 1604 1605 /* Sync the descriptor */ 1606 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1607 1608 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1609 if (cur_rx->sk_mbuf == NULL) 1610 return; 1611 1612 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1613 for (i = 0; i < dmamap->dm_nsegs; i++) { 1614 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1615 } 1616 if_rxr_put(&sc_if->sk_cdata.sk_rx_ring, dmamap->dm_nsegs); 1617 1618 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1619 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1620 bus_dmamap_unload(sc_if->sk_softc->sc_dmatag, dmamap); 1621 1622 m = cur_rx->sk_mbuf; 1623 cur_rx->sk_mbuf = NULL; 1624 1625 if (total_len < SK_MIN_FRAMELEN || 1626 total_len > SK_JUMBO_FRAMELEN || 1627 msk_rxvalid(sc, rxstat, total_len) == 0) { 1628 ifp->if_ierrors++; 1629 m_freem(m); 1630 return; 1631 } 1632 1633 m->m_pkthdr.rcvif = ifp; 1634 m->m_pkthdr.len = m->m_len = total_len; 1635 1636 ifp->if_ipackets++; 1637 1638 #if NBPFILTER > 0 1639 if (ifp->if_bpf) 1640 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1641 #endif 1642 1643 /* pass it on. */ 1644 ether_input_mbuf(ifp, m); 1645 } 1646 1647 void 1648 msk_txeof(struct sk_if_softc *sc_if) 1649 { 1650 struct sk_softc *sc = sc_if->sk_softc; 1651 struct msk_tx_desc *cur_tx; 1652 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1653 u_int32_t idx, reg, sk_ctl; 1654 struct sk_txmap_entry *entry; 1655 1656 DPRINTFN(2, ("msk_txeof\n")); 1657 1658 if (sc_if->sk_port == SK_PORT_A) 1659 reg = SK_STAT_BMU_TXA1_RIDX; 1660 else 1661 reg = SK_STAT_BMU_TXA2_RIDX; 1662 1663 /* 1664 * Go through our tx ring and free mbufs for those 1665 * frames that have been sent. 1666 */ 1667 idx = sc_if->sk_cdata.sk_tx_cons; 1668 while (idx != sk_win_read_2(sc, reg)) { 1669 MSK_CDTXSYNC(sc_if, idx, 1, 1670 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1671 1672 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1673 sk_ctl = cur_tx->sk_ctl; 1674 #ifdef MSK_DEBUG 1675 if (mskdebug >= 2) 1676 msk_dump_txdesc(cur_tx, idx); 1677 #endif 1678 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1679 ifp->if_opackets++; 1680 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1681 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1682 1683 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1684 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1685 1686 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1687 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1688 1689 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1690 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1691 link); 1692 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1693 } 1694 sc_if->sk_cdata.sk_tx_cnt--; 1695 SK_INC(idx, MSK_TX_RING_CNT); 1696 } 1697 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1698 1699 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1700 ifp->if_flags &= ~IFF_OACTIVE; 1701 1702 sc_if->sk_cdata.sk_tx_cons = idx; 1703 } 1704 1705 void 1706 msk_fill_rx_ring(struct sk_if_softc *sc_if) 1707 { 1708 u_int slots, used; 1709 1710 slots = if_rxr_get(&sc_if->sk_cdata.sk_rx_ring, MSK_RX_RING_CNT); 1711 while (slots > 0) { 1712 used = msk_newbuf(sc_if); 1713 if (used == 0) 1714 break; 1715 1716 slots -= used; 1717 } 1718 if_rxr_put(&sc_if->sk_cdata.sk_rx_ring, slots); 1719 } 1720 1721 void 1722 msk_tick(void *xsc_if) 1723 { 1724 struct sk_if_softc *sc_if = xsc_if; 1725 struct mii_data *mii = &sc_if->sk_mii; 1726 int s; 1727 1728 s = splnet(); 1729 mii_tick(mii); 1730 splx(s); 1731 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1732 } 1733 1734 void 1735 msk_intr_yukon(struct sk_if_softc *sc_if) 1736 { 1737 u_int8_t status; 1738 1739 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1740 /* RX overrun */ 1741 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1742 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1743 SK_RFCTL_RX_FIFO_OVER); 1744 } 1745 /* TX underrun */ 1746 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1747 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1748 SK_TFCTL_TX_FIFO_UNDER); 1749 } 1750 1751 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1752 } 1753 1754 int 1755 msk_intr(void *xsc) 1756 { 1757 struct sk_softc *sc = xsc; 1758 struct sk_if_softc *sc_if; 1759 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1760 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1761 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1762 int claimed = 0, rx[2] = {0, 0}; 1763 u_int32_t status; 1764 struct msk_status_desc *cur_st; 1765 1766 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1767 if (status == 0xffffffff) 1768 return (0); 1769 if (status == 0) { 1770 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1771 return (0); 1772 } 1773 1774 status = CSR_READ_4(sc, SK_ISR); 1775 1776 if (sc_if0 != NULL) 1777 ifp0 = &sc_if0->arpcom.ac_if; 1778 if (sc_if1 != NULL) 1779 ifp1 = &sc_if1->arpcom.ac_if; 1780 1781 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1782 (ifp0->if_flags & IFF_RUNNING)) { 1783 msk_intr_yukon(sc_if0); 1784 } 1785 1786 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1787 (ifp1->if_flags & IFF_RUNNING)) { 1788 msk_intr_yukon(sc_if1); 1789 } 1790 1791 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1792 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1793 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1794 1795 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 1796 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1797 switch (cur_st->sk_opcode) { 1798 case SK_Y2_STOPC_RXSTAT: 1799 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 1800 rx[cur_st->sk_link & 0x01] = 1; 1801 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 1802 letoh32(cur_st->sk_status)); 1803 break; 1804 case SK_Y2_STOPC_TXSTAT: 1805 if (sc_if0) 1806 msk_txeof(sc_if0); 1807 if (sc_if1) 1808 msk_txeof(sc_if1); 1809 break; 1810 default: 1811 printf("opcode=0x%x\n", cur_st->sk_opcode); 1812 break; 1813 } 1814 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1815 1816 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1817 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1818 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1819 } 1820 1821 if (status & SK_Y2_IMR_BMU) { 1822 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1823 claimed = 1; 1824 } 1825 1826 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1827 1828 if (rx[0]) { 1829 msk_fill_rx_ring(sc_if0); 1830 SK_IF_WRITE_2(sc_if0, 0, SK_RXQ1_Y2_PREF_PUTIDX, 1831 sc_if0->sk_cdata.sk_rx_prod); 1832 } 1833 if (rx[1]) { 1834 msk_fill_rx_ring(sc_if1); 1835 SK_IF_WRITE_2(sc_if1, 0, SK_RXQ1_Y2_PREF_PUTIDX, 1836 sc_if1->sk_cdata.sk_rx_prod); 1837 } 1838 1839 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1840 msk_start(ifp0); 1841 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1842 msk_start(ifp1); 1843 1844 return (claimed); 1845 } 1846 1847 void 1848 msk_init_yukon(struct sk_if_softc *sc_if) 1849 { 1850 u_int32_t v; 1851 u_int16_t reg; 1852 struct sk_softc *sc; 1853 int i; 1854 1855 sc = sc_if->sk_softc; 1856 1857 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1858 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1859 1860 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1861 1862 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1863 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1864 1865 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1866 1867 /* unused read of the interrupt source register */ 1868 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1869 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1870 1871 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1872 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1873 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1874 1875 /* MIB Counter Clear Mode set */ 1876 reg |= YU_PAR_MIB_CLR; 1877 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1878 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1879 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1880 1881 /* MIB Counter Clear Mode clear */ 1882 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1883 reg &= ~YU_PAR_MIB_CLR; 1884 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1885 1886 /* receive control reg */ 1887 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1888 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1889 1890 /* transmit parameter register */ 1891 DPRINTFN(6, ("msk_init_yukon: 8\n")); 1892 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 1893 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 1894 1895 /* serial mode register */ 1896 DPRINTFN(6, ("msk_init_yukon: 9\n")); 1897 reg = YU_SMR_DATA_BLIND(0x1c) | 1898 YU_SMR_MFL_VLAN | 1899 YU_SMR_IPG_DATA(0x1e); 1900 1901 if (sc->sk_type != SK_YUKON_FE && 1902 sc->sk_type != SK_YUKON_FE_P) 1903 reg |= YU_SMR_MFL_JUMBO; 1904 1905 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 1906 1907 DPRINTFN(6, ("msk_init_yukon: 10\n")); 1908 /* Setup Yukon's address */ 1909 for (i = 0; i < 3; i++) { 1910 /* Write Source Address 1 (unicast filter) */ 1911 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 1912 sc_if->arpcom.ac_enaddr[i * 2] | 1913 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 1914 } 1915 1916 for (i = 0; i < 3; i++) { 1917 reg = sk_win_read_2(sc_if->sk_softc, 1918 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 1919 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 1920 } 1921 1922 /* Program promiscuous mode and multicast filters */ 1923 DPRINTFN(6, ("msk_init_yukon: 11\n")); 1924 msk_iff(sc_if); 1925 1926 /* enable interrupt mask for counter overflows */ 1927 DPRINTFN(6, ("msk_init_yukon: 12\n")); 1928 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 1929 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 1930 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 1931 1932 /* Configure RX MAC FIFO Flush Mask */ 1933 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 1934 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 1935 YU_RXSTAT_JABBER; 1936 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 1937 1938 /* Configure RX MAC FIFO */ 1939 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 1940 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 1941 SK_RFCTL_FIFO_FLUSH_ON); 1942 1943 /* Increase flush threshould to 64 bytes */ 1944 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 1945 SK_RFCTL_FIFO_THRESHOLD + 1); 1946 1947 /* Configure TX MAC FIFO */ 1948 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 1949 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 1950 1951 #if 1 1952 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 1953 #endif 1954 DPRINTFN(6, ("msk_init_yukon: end\n")); 1955 } 1956 1957 /* 1958 * Note that to properly initialize any part of the GEnesis chip, 1959 * you first have to take it out of reset mode. 1960 */ 1961 void 1962 msk_init(void *xsc_if) 1963 { 1964 struct sk_if_softc *sc_if = xsc_if; 1965 struct sk_softc *sc = sc_if->sk_softc; 1966 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1967 struct mii_data *mii = &sc_if->sk_mii; 1968 int s; 1969 1970 DPRINTFN(2, ("msk_init\n")); 1971 1972 s = splnet(); 1973 1974 /* Cancel pending I/O and free all RX/TX buffers. */ 1975 msk_stop(sc_if, 0); 1976 1977 /* Configure I2C registers */ 1978 1979 /* Configure XMAC(s) */ 1980 msk_init_yukon(sc_if); 1981 mii_mediachg(mii); 1982 1983 /* Configure transmit arbiter(s) */ 1984 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 1985 #if 0 1986 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 1987 #endif 1988 1989 /* Configure RAMbuffers */ 1990 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 1991 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 1992 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 1993 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 1994 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 1995 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 1996 1997 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 1998 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 1999 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2000 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2001 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2002 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2003 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2004 2005 /* Configure BMUs */ 2006 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2007 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2008 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2009 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_WATERMARK, 0x00000600); 2010 2011 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2012 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2013 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2014 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_WATERMARK, 0x00000600); 2015 2016 /* Make sure the sync transmit queue is disabled. */ 2017 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2018 2019 /* Init descriptors */ 2020 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2021 printf("%s: initialization failed: no " 2022 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2023 msk_stop(sc_if, 0); 2024 splx(s); 2025 return; 2026 } 2027 2028 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2029 printf("%s: initialization failed: no " 2030 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2031 msk_stop(sc_if, 0); 2032 splx(s); 2033 return; 2034 } 2035 2036 /* Initialize prefetch engine. */ 2037 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2038 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2039 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2040 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2041 MSK_RX_RING_ADDR(sc_if, 0)); 2042 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2043 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2044 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2045 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2046 2047 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2048 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2049 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2050 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2051 MSK_TX_RING_ADDR(sc_if, 0)); 2052 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2053 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2054 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2055 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2056 2057 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2058 sc_if->sk_cdata.sk_rx_prod); 2059 2060 /* Configure interrupt handling */ 2061 if (sc_if->sk_port == SK_PORT_A) 2062 sc->sk_intrmask |= SK_Y2_INTRS1; 2063 else 2064 sc->sk_intrmask |= SK_Y2_INTRS2; 2065 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2066 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2067 2068 ifp->if_flags |= IFF_RUNNING; 2069 ifp->if_flags &= ~IFF_OACTIVE; 2070 2071 timeout_add_sec(&sc_if->sk_tick_ch, 1); 2072 2073 splx(s); 2074 } 2075 2076 void 2077 msk_stop(struct sk_if_softc *sc_if, int softonly) 2078 { 2079 struct sk_softc *sc = sc_if->sk_softc; 2080 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2081 struct sk_txmap_entry *dma; 2082 int i; 2083 2084 DPRINTFN(2, ("msk_stop\n")); 2085 2086 timeout_del(&sc_if->sk_tick_ch); 2087 2088 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2089 2090 /* Stop transfer of Tx descriptors */ 2091 2092 /* Stop transfer of Rx descriptors */ 2093 2094 if (!softonly) { 2095 /* Turn off various components of this interface. */ 2096 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2097 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2098 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2099 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2100 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2101 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2102 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2103 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2104 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2105 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2106 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2107 2108 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2109 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2110 2111 /* Disable interrupts */ 2112 if (sc_if->sk_port == SK_PORT_A) 2113 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2114 else 2115 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2116 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2117 } 2118 2119 /* Free RX and TX mbufs still in the queues. */ 2120 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2121 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2122 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2123 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2124 } 2125 } 2126 2127 sc_if->sk_cdata.sk_rx_prod = 0; 2128 sc_if->sk_cdata.sk_rx_cons = 0; 2129 2130 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2131 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2132 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2133 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2134 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2135 sc_if->sk_cdata.sk_tx_map[i], link); 2136 sc_if->sk_cdata.sk_tx_map[i] = 0; 2137 } 2138 } 2139 2140 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2141 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2142 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2143 free(dma, M_DEVBUF, 0); 2144 } 2145 } 2146 2147 struct cfattach mskc_ca = { 2148 sizeof(struct sk_softc), mskc_probe, mskc_attach, mskc_detach, 2149 mskc_activate 2150 }; 2151 2152 struct cfdriver mskc_cd = { 2153 NULL, "mskc", DV_DULL 2154 }; 2155 2156 struct cfattach msk_ca = { 2157 sizeof(struct sk_if_softc), msk_probe, msk_attach, msk_detach, 2158 msk_activate 2159 }; 2160 2161 struct cfdriver msk_cd = { 2162 NULL, "msk", DV_IFNET 2163 }; 2164 2165 #ifdef MSK_DEBUG 2166 void 2167 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2168 { 2169 #define DESC_PRINT(X) \ 2170 if (X) \ 2171 printf("txdesc[%d]." #X "=%#x\n", \ 2172 idx, X); 2173 2174 DESC_PRINT(letoh32(le->sk_addr)); 2175 DESC_PRINT(letoh16(le->sk_len)); 2176 DESC_PRINT(le->sk_ctl); 2177 DESC_PRINT(le->sk_opcode); 2178 #undef DESC_PRINT 2179 } 2180 2181 void 2182 msk_dump_bytes(const char *data, int len) 2183 { 2184 int c, i, j; 2185 2186 for (i = 0; i < len; i += 16) { 2187 printf("%08x ", i); 2188 c = len - i; 2189 if (c > 16) c = 16; 2190 2191 for (j = 0; j < c; j++) { 2192 printf("%02x ", data[i + j] & 0xff); 2193 if ((j & 0xf) == 7 && j > 0) 2194 printf(" "); 2195 } 2196 2197 for (; j < 16; j++) 2198 printf(" "); 2199 printf(" "); 2200 2201 for (j = 0; j < c; j++) { 2202 int ch = data[i + j] & 0xff; 2203 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2204 } 2205 2206 printf("\n"); 2207 2208 if (c < 16) 2209 break; 2210 } 2211 } 2212 2213 void 2214 msk_dump_mbuf(struct mbuf *m) 2215 { 2216 int count = m->m_pkthdr.len; 2217 2218 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2219 2220 while (count > 0 && m) { 2221 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2222 m, m->m_data, m->m_len); 2223 msk_dump_bytes(mtod(m, char *), m->m_len); 2224 2225 count -= m->m_len; 2226 m = m->m_next; 2227 } 2228 } 2229 #endif 2230