1 /* $OpenBSD: if_msk.c,v 1.78 2009/10/04 18:32:02 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include "bpfilter.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/timeout.h> 99 #include <sys/device.h> 100 #include <sys/queue.h> 101 102 #include <net/if.h> 103 #include <net/if_dl.h> 104 #include <net/if_types.h> 105 106 #ifdef INET 107 #include <netinet/in.h> 108 #include <netinet/in_systm.h> 109 #include <netinet/in_var.h> 110 #include <netinet/ip.h> 111 #include <netinet/udp.h> 112 #include <netinet/tcp.h> 113 #include <netinet/if_ether.h> 114 #endif 115 116 #include <net/if_media.h> 117 #include <net/if_vlan_var.h> 118 119 #if NBPFILTER > 0 120 #include <net/bpf.h> 121 #endif 122 123 #include <dev/mii/mii.h> 124 #include <dev/mii/miivar.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/pcidevs.h> 130 131 #include <dev/pci/if_skreg.h> 132 #include <dev/pci/if_mskvar.h> 133 134 int mskc_probe(struct device *, void *, void *); 135 void mskc_attach(struct device *, struct device *self, void *aux); 136 int mskc_detach(struct device *, int); 137 void mskc_reset(struct sk_softc *); 138 void mskc_shutdown(void *); 139 int msk_probe(struct device *, void *, void *); 140 void msk_attach(struct device *, struct device *self, void *aux); 141 int msk_detach(struct device *, int); 142 void msk_reset(struct sk_if_softc *); 143 int mskcprint(void *, const char *); 144 int msk_intr(void *); 145 void msk_intr_yukon(struct sk_if_softc *); 146 static __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 147 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 148 void msk_txeof(struct sk_if_softc *); 149 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 150 void msk_start(struct ifnet *); 151 int msk_ioctl(struct ifnet *, u_long, caddr_t); 152 void msk_init(void *); 153 void msk_init_yukon(struct sk_if_softc *); 154 void msk_stop(struct sk_if_softc *); 155 void msk_watchdog(struct ifnet *); 156 int msk_ifmedia_upd(struct ifnet *); 157 void msk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 158 int msk_newbuf(struct sk_if_softc *); 159 int msk_init_rx_ring(struct sk_if_softc *); 160 int msk_init_tx_ring(struct sk_if_softc *); 161 void msk_fill_rx_ring(struct sk_if_softc *); 162 163 int msk_miibus_readreg(struct device *, int, int); 164 void msk_miibus_writereg(struct device *, int, int, int); 165 void msk_miibus_statchg(struct device *); 166 167 void msk_setmulti(struct sk_if_softc *); 168 void msk_setpromisc(struct sk_if_softc *); 169 void msk_tick(void *); 170 171 #ifdef MSK_DEBUG 172 #define DPRINTF(x) if (mskdebug) printf x 173 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 174 int mskdebug = 0; 175 176 void msk_dump_txdesc(struct msk_tx_desc *, int); 177 void msk_dump_mbuf(struct mbuf *); 178 void msk_dump_bytes(const char *, int); 179 #else 180 #define DPRINTF(x) 181 #define DPRINTFN(n,x) 182 #endif 183 184 /* supported device vendors */ 185 const struct pci_matchid mskc_devices[] = { 186 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 187 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 188 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 189 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8021CU }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8021X }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8022CU }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8022X }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 200 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 201 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 202 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 203 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 204 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 205 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 206 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 207 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 208 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 209 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 210 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 211 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 212 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 213 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 214 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8061CU }, 215 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8061X }, 216 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8062CU }, 217 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8062X }, 218 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 219 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 220 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 221 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 222 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 223 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Sxx }, 224 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Exx } 225 }; 226 227 static inline u_int32_t 228 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 229 { 230 return CSR_READ_4(sc, reg); 231 } 232 233 static inline u_int16_t 234 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 235 { 236 return CSR_READ_2(sc, reg); 237 } 238 239 static inline u_int8_t 240 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 241 { 242 return CSR_READ_1(sc, reg); 243 } 244 245 static inline void 246 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 247 { 248 CSR_WRITE_4(sc, reg, x); 249 } 250 251 static inline void 252 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 253 { 254 CSR_WRITE_2(sc, reg, x); 255 } 256 257 static inline void 258 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 259 { 260 CSR_WRITE_1(sc, reg, x); 261 } 262 263 int 264 msk_miibus_readreg(struct device *dev, int phy, int reg) 265 { 266 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 267 u_int16_t val; 268 int i; 269 270 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 271 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 272 273 for (i = 0; i < SK_TIMEOUT; i++) { 274 DELAY(1); 275 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 276 if (val & YU_SMICR_READ_VALID) 277 break; 278 } 279 280 if (i == SK_TIMEOUT) { 281 printf("%s: phy failed to come ready\n", 282 sc_if->sk_dev.dv_xname); 283 return (0); 284 } 285 286 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 287 SK_TIMEOUT)); 288 289 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 290 291 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 292 phy, reg, val)); 293 294 return (val); 295 } 296 297 void 298 msk_miibus_writereg(struct device *dev, int phy, int reg, int val) 299 { 300 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 301 int i; 302 303 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 304 phy, reg, val)); 305 306 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 307 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 308 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 309 310 for (i = 0; i < SK_TIMEOUT; i++) { 311 DELAY(1); 312 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 313 break; 314 } 315 316 if (i == SK_TIMEOUT) 317 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 318 } 319 320 void 321 msk_miibus_statchg(struct device *dev) 322 { 323 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 324 struct mii_data *mii = &sc_if->sk_mii; 325 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 326 int gpcr; 327 328 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 329 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 330 331 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 332 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 333 /* Set speed. */ 334 gpcr |= YU_GPCR_SPEED_DIS; 335 switch (IFM_SUBTYPE(mii->mii_media_active)) { 336 case IFM_1000_SX: 337 case IFM_1000_LX: 338 case IFM_1000_CX: 339 case IFM_1000_T: 340 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 341 break; 342 case IFM_100_TX: 343 gpcr |= YU_GPCR_SPEED; 344 break; 345 } 346 347 /* Set duplex. */ 348 gpcr |= YU_GPCR_DPLX_DIS; 349 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 350 gpcr |= YU_GPCR_DUPLEX; 351 352 /* Disable flow control. */ 353 gpcr |= YU_GPCR_FCTL_DIS; 354 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 355 } 356 357 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 358 359 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 360 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 361 } 362 363 void 364 msk_setmulti(struct sk_if_softc *sc_if) 365 { 366 struct ifnet *ifp= &sc_if->arpcom.ac_if; 367 u_int32_t hashes[2] = { 0, 0 }; 368 int h; 369 struct arpcom *ac = &sc_if->arpcom; 370 struct ether_multi *enm; 371 struct ether_multistep step; 372 373 /* First, zot all the existing filters. */ 374 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 375 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 376 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 377 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 378 379 380 /* Now program new ones. */ 381 allmulti: 382 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 383 hashes[0] = 0xFFFFFFFF; 384 hashes[1] = 0xFFFFFFFF; 385 } else { 386 /* First find the tail of the list. */ 387 ETHER_FIRST_MULTI(step, ac, enm); 388 while (enm != NULL) { 389 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 390 ETHER_ADDR_LEN)) { 391 ifp->if_flags |= IFF_ALLMULTI; 392 goto allmulti; 393 } 394 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 395 ((1 << SK_HASH_BITS) - 1); 396 if (h < 32) 397 hashes[0] |= (1 << h); 398 else 399 hashes[1] |= (1 << (h - 32)); 400 401 ETHER_NEXT_MULTI(step, enm); 402 } 403 } 404 405 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 406 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 407 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 408 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 409 } 410 411 void 412 msk_setpromisc(struct sk_if_softc *sc_if) 413 { 414 struct ifnet *ifp = &sc_if->arpcom.ac_if; 415 416 if (ifp->if_flags & IFF_PROMISC) 417 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 418 YU_RCR_UFLEN | YU_RCR_MUFLEN); 419 else 420 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 421 YU_RCR_UFLEN | YU_RCR_MUFLEN); 422 } 423 424 int 425 msk_init_rx_ring(struct sk_if_softc *sc_if) 426 { 427 struct msk_chain_data *cd = &sc_if->sk_cdata; 428 struct msk_ring_data *rd = sc_if->sk_rdata; 429 int i, nexti; 430 431 bzero((char *)rd->sk_rx_ring, 432 sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 433 434 for (i = 0; i < MSK_RX_RING_CNT; i++) { 435 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 436 if (i == (MSK_RX_RING_CNT - 1)) 437 nexti = 0; 438 else 439 nexti = i + 1; 440 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 441 } 442 443 sc_if->sk_cdata.sk_rx_prod = 0; 444 sc_if->sk_cdata.sk_rx_cons = 0; 445 sc_if->sk_cdata.sk_rx_cnt = 0; 446 447 msk_fill_rx_ring(sc_if); 448 return (0); 449 } 450 451 int 452 msk_init_tx_ring(struct sk_if_softc *sc_if) 453 { 454 struct sk_softc *sc = sc_if->sk_softc; 455 struct msk_chain_data *cd = &sc_if->sk_cdata; 456 struct msk_ring_data *rd = sc_if->sk_rdata; 457 bus_dmamap_t dmamap; 458 struct sk_txmap_entry *entry; 459 int i, nexti; 460 461 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 462 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 463 464 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 465 for (i = 0; i < MSK_TX_RING_CNT; i++) { 466 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 467 if (i == (MSK_TX_RING_CNT - 1)) 468 nexti = 0; 469 else 470 nexti = i + 1; 471 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 472 473 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 474 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 475 return (ENOBUFS); 476 477 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 478 if (!entry) { 479 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 480 return (ENOBUFS); 481 } 482 entry->dmamap = dmamap; 483 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 484 } 485 486 sc_if->sk_cdata.sk_tx_prod = 0; 487 sc_if->sk_cdata.sk_tx_cons = 0; 488 sc_if->sk_cdata.sk_tx_cnt = 0; 489 490 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 491 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 492 493 return (0); 494 } 495 496 int 497 msk_newbuf(struct sk_if_softc *sc_if) 498 { 499 struct sk_chain *c; 500 struct msk_rx_desc *r; 501 struct mbuf *m; 502 bus_dmamap_t dmamap; 503 int error; 504 int opcode, i; 505 506 m = MCLGETI(NULL, M_DONTWAIT, &sc_if->arpcom.ac_if, sc_if->sk_pktlen); 507 if (!m) 508 return (ENOBUFS); 509 m->m_len = m->m_pkthdr.len = sc_if->sk_pktlen; 510 m_adj(m, ETHER_ALIGN); 511 512 dmamap = sc_if->sk_cdata.sk_rx_map[sc_if->sk_cdata.sk_rx_prod]; 513 514 error = bus_dmamap_load_mbuf(sc_if->sk_softc->sc_dmatag, dmamap, m, 515 BUS_DMA_READ|BUS_DMA_NOWAIT); 516 if (error) { 517 m_freem(m); 518 return (ENOBUFS); 519 } 520 521 if (dmamap->dm_nsegs > (MSK_RX_RING_CNT - sc_if->sk_cdata.sk_rx_cnt)) { 522 bus_dmamap_unload(sc_if->sk_softc->sc_dmatag, dmamap); 523 m_freem(m); 524 return (ENOBUFS); 525 } 526 527 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 528 dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 529 530 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 531 r = c->sk_le; 532 c->sk_mbuf = m; 533 534 opcode = SK_Y2_RXOPC_PACKET; 535 for (i = 0; i < dmamap->dm_nsegs; i++) { 536 r->sk_addr = htole32(dmamap->dm_segs[i].ds_addr); 537 r->sk_len = htole16(dmamap->dm_segs[i].ds_len); 538 r->sk_ctl = 0; 539 r->sk_opcode = opcode | SK_Y2_RXOPC_OWN; 540 opcode = SK_Y2_RXOPC_BUFFER; 541 542 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 543 sc_if->sk_cdata.sk_rx_cnt++; 544 545 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 546 r = c->sk_le; 547 c->sk_mbuf = NULL; 548 } 549 550 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 551 552 return (0); 553 } 554 555 /* 556 * Set media options. 557 */ 558 int 559 msk_ifmedia_upd(struct ifnet *ifp) 560 { 561 struct sk_if_softc *sc_if = ifp->if_softc; 562 563 mii_mediachg(&sc_if->sk_mii); 564 return (0); 565 } 566 567 /* 568 * Report current media status. 569 */ 570 void 571 msk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 572 { 573 struct sk_if_softc *sc_if = ifp->if_softc; 574 575 mii_pollstat(&sc_if->sk_mii); 576 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 577 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 578 } 579 580 int 581 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 582 { 583 struct sk_if_softc *sc_if = ifp->if_softc; 584 struct ifaddr *ifa = (struct ifaddr *) data; 585 struct ifreq *ifr = (struct ifreq *) data; 586 struct mii_data *mii; 587 int s, error = 0; 588 589 s = splnet(); 590 591 switch(command) { 592 case SIOCSIFADDR: 593 ifp->if_flags |= IFF_UP; 594 if (!(ifp->if_flags & IFF_RUNNING)) 595 msk_init(sc_if); 596 #ifdef INET 597 if (ifa->ifa_addr->sa_family == AF_INET) 598 arp_ifinit(&sc_if->arpcom, ifa); 599 #endif /* INET */ 600 break; 601 602 case SIOCSIFFLAGS: 603 if (ifp->if_flags & IFF_UP) { 604 if (ifp->if_flags & IFF_RUNNING && 605 (sc_if->sk_if_flags ^ ifp->if_flags) & 606 IFF_PROMISC) { 607 msk_setpromisc(sc_if); 608 msk_setmulti(sc_if); 609 } else { 610 if (!(ifp->if_flags & IFF_RUNNING)) 611 msk_init(sc_if); 612 } 613 } else { 614 if (ifp->if_flags & IFF_RUNNING) 615 msk_stop(sc_if); 616 } 617 sc_if->sk_if_flags = ifp->if_flags; 618 break; 619 620 case SIOCGIFMEDIA: 621 case SIOCSIFMEDIA: 622 mii = &sc_if->sk_mii; 623 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 624 break; 625 626 default: 627 error = ether_ioctl(ifp, &sc_if->arpcom, command, data); 628 } 629 630 if (error == ENETRESET) { 631 if (ifp->if_flags & IFF_RUNNING) 632 msk_setmulti(sc_if); 633 error = 0; 634 } 635 636 splx(s); 637 return (error); 638 } 639 640 /* 641 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 642 * IDs against our list and return a device name if we find a match. 643 */ 644 int 645 mskc_probe(struct device *parent, void *match, void *aux) 646 { 647 return (pci_matchbyid((struct pci_attach_args *)aux, mskc_devices, 648 sizeof(mskc_devices)/sizeof(mskc_devices[0]))); 649 } 650 651 /* 652 * Force the GEnesis into reset, then bring it out of reset. 653 */ 654 void 655 mskc_reset(struct sk_softc *sc) 656 { 657 u_int32_t imtimer_ticks, reg1; 658 int reg; 659 660 DPRINTFN(2, ("mskc_reset\n")); 661 662 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 663 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 664 665 DELAY(1000); 666 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 667 DELAY(2); 668 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 669 670 sk_win_write_1(sc, SK_TESTCTL1, 2); 671 672 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 673 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 674 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 675 else 676 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 677 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 678 679 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 680 sk_win_write_1(sc, SK_Y2_CLKGATE, 681 SK_Y2_CLKGATE_LINK1_GATE_DIS | 682 SK_Y2_CLKGATE_LINK2_GATE_DIS | 683 SK_Y2_CLKGATE_LINK1_CORE_DIS | 684 SK_Y2_CLKGATE_LINK2_CORE_DIS | 685 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 686 else 687 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 688 689 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 690 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 691 DELAY(1000); 692 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 693 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 694 695 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 696 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 697 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 698 } 699 700 sk_win_write_1(sc, SK_TESTCTL1, 1); 701 702 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 703 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 704 CSR_READ_2(sc, SK_LINK_CTRL))); 705 706 /* Disable ASF */ 707 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 708 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 709 710 /* Clear I2C IRQ noise */ 711 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 712 713 /* Disable hardware timer */ 714 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 715 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 716 717 /* Disable descriptor polling */ 718 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 719 720 /* Disable time stamps */ 721 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 722 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 723 724 /* Enable RAM interface */ 725 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 726 for (reg = SK_TO0;reg <= SK_TO11; reg++) 727 sk_win_write_1(sc, reg, 36); 728 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 729 for (reg = SK_TO0;reg <= SK_TO11; reg++) 730 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 731 732 /* 733 * Configure interrupt moderation. The moderation timer 734 * defers interrupts specified in the interrupt moderation 735 * timer mask based on the timeout specified in the interrupt 736 * moderation timer init register. Each bit in the timer 737 * register represents one tick, so to specify a timeout in 738 * microseconds, we have to multiply by the correct number of 739 * ticks-per-microsecond. 740 */ 741 switch (sc->sk_type) { 742 case SK_YUKON_EC: 743 case SK_YUKON_XL: 744 case SK_YUKON_FE: 745 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 746 break; 747 default: 748 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 749 } 750 751 /* Reset status ring. */ 752 bzero((char *)sc->sk_status_ring, 753 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 754 sc->sk_status_idx = 0; 755 756 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 757 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 758 759 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 760 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 761 sc->sk_status_map->dm_segs[0].ds_addr); 762 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 763 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 764 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 10); 765 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 16); 766 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 16); 767 768 #if 0 769 sk_win_write_4(sc, SK_Y2_LEV_TIMERINIT, SK_IM_USECS(100)); 770 sk_win_write_4(sc, 0x0ec0, SK_IM_USECS(1000)); 771 772 sk_win_write_4(sc, 0x0ed0, SK_IM_USECS(20)); 773 #else 774 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(4)); 775 #endif 776 777 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 778 779 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 780 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 781 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 782 } 783 784 int 785 msk_probe(struct device *parent, void *match, void *aux) 786 { 787 struct skc_attach_args *sa = aux; 788 789 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 790 return (0); 791 792 switch (sa->skc_type) { 793 case SK_YUKON_XL: 794 case SK_YUKON_EC_U: 795 case SK_YUKON_EX: 796 case SK_YUKON_EC: 797 case SK_YUKON_FE: 798 case SK_YUKON_FE_P: 799 case SK_YUKON_SUPR: 800 case SK_YUKON_ULTRA2: 801 return (1); 802 } 803 804 return (0); 805 } 806 807 void 808 msk_reset(struct sk_if_softc *sc_if) 809 { 810 /* GMAC and GPHY Reset */ 811 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 812 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 813 DELAY(1000); 814 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 815 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 816 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 817 } 818 819 /* 820 * Each XMAC chip is attached as a separate logical IP interface. 821 * Single port cards will have only one logical interface of course. 822 */ 823 void 824 msk_attach(struct device *parent, struct device *self, void *aux) 825 { 826 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 827 struct sk_softc *sc = (struct sk_softc *)parent; 828 struct skc_attach_args *sa = aux; 829 struct ifnet *ifp; 830 caddr_t kva; 831 int i; 832 u_int32_t chunk; 833 int mii_flags; 834 int error; 835 836 sc_if->sk_port = sa->skc_port; 837 sc_if->sk_softc = sc; 838 sc->sk_if[sa->skc_port] = sc_if; 839 840 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 841 842 /* 843 * Get station address for this interface. Note that 844 * dual port cards actually come with three station 845 * addresses: one for each port, plus an extra. The 846 * extra one is used by the SysKonnect driver software 847 * as a 'virtual' station address for when both ports 848 * are operating in failover mode. Currently we don't 849 * use this extra address. 850 */ 851 for (i = 0; i < ETHER_ADDR_LEN; i++) 852 sc_if->arpcom.ac_enaddr[i] = 853 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 854 855 printf(": address %s\n", 856 ether_sprintf(sc_if->arpcom.ac_enaddr)); 857 858 /* 859 * Set up RAM buffer addresses. The Yukon2 has a small amount 860 * of SRAM on it, somewhere between 4K and 48K. We need to 861 * divide this up between the transmitter and receiver. We 862 * give the receiver 2/3 of the memory (rounded down), and the 863 * transmitter whatever remains. 864 */ 865 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 866 sc_if->sk_rx_ramstart = 0; 867 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 868 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 869 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 870 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 871 872 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 873 " tx_ramstart=%#x tx_ramend=%#x\n", 874 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 875 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 876 877 /* Allocate the descriptor queues. */ 878 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 879 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 880 BUS_DMA_NOWAIT)) { 881 printf(": can't alloc rx buffers\n"); 882 goto fail; 883 } 884 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 885 sc_if->sk_ring_nseg, 886 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 887 printf(": can't map dma buffers (%lu bytes)\n", 888 (ulong)sizeof(struct msk_ring_data)); 889 goto fail_1; 890 } 891 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 892 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 893 &sc_if->sk_ring_map)) { 894 printf(": can't create dma map\n"); 895 goto fail_2; 896 } 897 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 898 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 899 printf(": can't load dma map\n"); 900 goto fail_3; 901 } 902 sc_if->sk_rdata = (struct msk_ring_data *)kva; 903 bzero(sc_if->sk_rdata, sizeof(struct msk_ring_data)); 904 905 if (sc->sk_type != SK_YUKON_FE && 906 sc->sk_type != SK_YUKON_FE_P) 907 sc_if->sk_pktlen = SK_JLEN; 908 else 909 sc_if->sk_pktlen = MCLBYTES; 910 911 for (i = 0; i < MSK_RX_RING_CNT; i++) { 912 if ((error = bus_dmamap_create(sc->sc_dmatag, 913 sc_if->sk_pktlen, 4, sc_if->sk_pktlen, 914 0, 0, &sc_if->sk_cdata.sk_rx_map[i])) != 0) { 915 printf("\n%s: unable to create rx DMA map %d, " 916 "error = %d\n", sc->sk_dev.dv_xname, i, error); 917 goto fail_4; 918 } 919 } 920 921 ifp = &sc_if->arpcom.ac_if; 922 ifp->if_softc = sc_if; 923 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 924 ifp->if_ioctl = msk_ioctl; 925 ifp->if_start = msk_start; 926 ifp->if_watchdog = msk_watchdog; 927 ifp->if_baudrate = 1000000000; 928 if (sc->sk_type != SK_YUKON_FE && 929 sc->sk_type != SK_YUKON_FE_P) 930 ifp->if_hardmtu = SK_JUMBO_MTU; 931 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 932 IFQ_SET_READY(&ifp->if_snd); 933 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 934 935 ifp->if_capabilities = IFCAP_VLAN_MTU; 936 937 msk_reset(sc_if); 938 939 /* 940 * Do miibus setup. 941 */ 942 msk_init_yukon(sc_if); 943 944 DPRINTFN(2, ("msk_attach: 1\n")); 945 946 sc_if->sk_mii.mii_ifp = ifp; 947 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 948 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 949 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 950 951 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 952 msk_ifmedia_upd, msk_ifmedia_sts); 953 mii_flags = MIIF_DOPAUSE; 954 if (sc->sk_fibertype) 955 mii_flags |= MIIF_HAVEFIBER; 956 mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0, 957 MII_OFFSET_ANY, mii_flags); 958 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 959 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 960 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 961 0, NULL); 962 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 963 } else 964 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 965 966 timeout_set(&sc_if->sk_tick_ch, msk_tick, sc_if); 967 968 /* 969 * Call MI attach routines. 970 */ 971 if_attach(ifp); 972 ether_ifattach(ifp); 973 974 sc_if->sk_sdhook = shutdownhook_establish(mskc_shutdown, sc); 975 976 DPRINTFN(2, ("msk_attach: end\n")); 977 return; 978 979 fail_4: 980 for (i = 0; i < MSK_RX_RING_CNT; i++) { 981 if (sc_if->sk_cdata.sk_rx_map[i] != NULL) 982 bus_dmamap_destroy(sc->sc_dmatag, 983 sc_if->sk_cdata.sk_rx_map[i]); 984 } 985 986 fail_3: 987 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 988 fail_2: 989 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 990 fail_1: 991 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 992 fail: 993 sc->sk_if[sa->skc_port] = NULL; 994 } 995 996 int 997 msk_detach(struct device *self, int flags) 998 { 999 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 1000 struct sk_softc *sc = sc_if->sk_softc; 1001 struct ifnet *ifp= &sc_if->arpcom.ac_if; 1002 1003 if (sc->sk_if[sc_if->sk_port] == NULL) 1004 return (0); 1005 1006 timeout_del(&sc_if->sk_tick_ch); 1007 1008 /* Detach any PHYs we might have. */ 1009 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1010 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1011 1012 /* Delete any remaining media. */ 1013 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1014 1015 if (sc_if->sk_sdhook != NULL) 1016 shutdownhook_disestablish(sc_if->sk_sdhook); 1017 1018 ether_ifdetach(ifp); 1019 if_detach(ifp); 1020 1021 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1022 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc_if->sk_rdata, 1023 sizeof(struct msk_ring_data)); 1024 bus_dmamem_free(sc->sc_dmatag, 1025 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1026 sc->sk_if[sc_if->sk_port] = NULL; 1027 1028 return (0); 1029 } 1030 1031 int 1032 mskcprint(void *aux, const char *pnp) 1033 { 1034 struct skc_attach_args *sa = aux; 1035 1036 if (pnp) 1037 printf("msk port %c at %s", 1038 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1039 else 1040 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1041 return (UNCONF); 1042 } 1043 1044 /* 1045 * Attach the interface. Allocate softc structures, do ifmedia 1046 * setup and ethernet/BPF attach. 1047 */ 1048 void 1049 mskc_attach(struct device *parent, struct device *self, void *aux) 1050 { 1051 struct sk_softc *sc = (struct sk_softc *)self; 1052 struct pci_attach_args *pa = aux; 1053 struct skc_attach_args skca; 1054 pci_chipset_tag_t pc = pa->pa_pc; 1055 pcireg_t command, memtype; 1056 pci_intr_handle_t ih; 1057 const char *intrstr = NULL; 1058 u_int8_t hw, pmd; 1059 char *revstr = NULL; 1060 caddr_t kva; 1061 1062 DPRINTFN(2, ("begin mskc_attach\n")); 1063 1064 /* 1065 * Handle power management nonsense. 1066 */ 1067 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1068 1069 if (command == 0x01) { 1070 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1071 if (command & SK_PSTATE_MASK) { 1072 u_int32_t iobase, membase, irq; 1073 1074 /* Save important PCI config data. */ 1075 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1076 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1077 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1078 1079 /* Reset the power state. */ 1080 printf("%s chip is in D%d power mode " 1081 "-- setting to D0\n", sc->sk_dev.dv_xname, 1082 command & SK_PSTATE_MASK); 1083 command &= 0xFFFFFFFC; 1084 pci_conf_write(pc, pa->pa_tag, 1085 SK_PCI_PWRMGMTCTRL, command); 1086 1087 /* Restore PCI config data. */ 1088 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1089 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1090 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1091 } 1092 } 1093 1094 /* 1095 * Map control/status registers. 1096 */ 1097 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1098 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1099 &sc->sk_bhandle, NULL, &sc->sk_bsize, 0)) { 1100 printf(": can't map mem space\n"); 1101 return; 1102 } 1103 1104 sc->sc_dmatag = pa->pa_dmat; 1105 1106 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1107 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1108 1109 /* bail out here if chip is not recognized */ 1110 if (!(SK_IS_YUKON2(sc))) { 1111 printf(": unknown chip type: %d\n", sc->sk_type); 1112 goto fail_1; 1113 } 1114 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1115 1116 /* Allocate interrupt */ 1117 if (pci_intr_map(pa, &ih)) { 1118 printf(": couldn't map interrupt\n"); 1119 goto fail_1; 1120 } 1121 1122 intrstr = pci_intr_string(pc, ih); 1123 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc, 1124 self->dv_xname); 1125 if (sc->sk_intrhand == NULL) { 1126 printf(": couldn't establish interrupt"); 1127 if (intrstr != NULL) 1128 printf(" at %s", intrstr); 1129 printf("\n"); 1130 goto fail_1; 1131 } 1132 sc->sk_pc = pc; 1133 1134 if (bus_dmamem_alloc(sc->sc_dmatag, 1135 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1136 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1137 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1138 printf(": can't alloc status buffers\n"); 1139 goto fail_2; 1140 } 1141 1142 if (bus_dmamem_map(sc->sc_dmatag, 1143 &sc->sk_status_seg, sc->sk_status_nseg, 1144 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1145 &kva, BUS_DMA_NOWAIT)) { 1146 printf(": can't map dma buffers (%lu bytes)\n", 1147 (ulong)(MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc))); 1148 goto fail_3; 1149 } 1150 if (bus_dmamap_create(sc->sc_dmatag, 1151 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1152 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1153 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1154 printf(": can't create dma map\n"); 1155 goto fail_4; 1156 } 1157 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1158 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1159 NULL, BUS_DMA_NOWAIT)) { 1160 printf(": can't load dma map\n"); 1161 goto fail_5; 1162 } 1163 sc->sk_status_ring = (struct msk_status_desc *)kva; 1164 bzero(sc->sk_status_ring, 1165 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1166 1167 /* Reset the adapter. */ 1168 mskc_reset(sc); 1169 1170 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1171 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1172 1173 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1174 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1175 sc->sk_fibertype = 1; 1176 1177 switch (sc->sk_type) { 1178 case SK_YUKON_XL: 1179 sc->sk_name = "Yukon-2 XL"; 1180 break; 1181 case SK_YUKON_EC_U: 1182 sc->sk_name = "Yukon-2 EC Ultra"; 1183 break; 1184 case SK_YUKON_EX: 1185 sc->sk_name = "Yukon-2 Extreme"; 1186 break; 1187 case SK_YUKON_EC: 1188 sc->sk_name = "Yukon-2 EC"; 1189 break; 1190 case SK_YUKON_FE: 1191 sc->sk_name = "Yukon-2 FE"; 1192 break; 1193 case SK_YUKON_FE_P: 1194 sc->sk_name = "Yukon-2 FE+"; 1195 break; 1196 case SK_YUKON_SUPR: 1197 sc->sk_name = "Yukon-2 Supreme"; 1198 break; 1199 case SK_YUKON_ULTRA2: 1200 sc->sk_name = "Yukon-2 Ultra2"; 1201 break; 1202 default: 1203 sc->sk_name = "Yukon (Unknown)"; 1204 } 1205 1206 if (sc->sk_type == SK_YUKON_XL) { 1207 switch (sc->sk_rev) { 1208 case SK_YUKON_XL_REV_A0: 1209 revstr = "A0"; 1210 break; 1211 case SK_YUKON_XL_REV_A1: 1212 revstr = "A1"; 1213 break; 1214 case SK_YUKON_XL_REV_A2: 1215 revstr = "A2"; 1216 break; 1217 case SK_YUKON_XL_REV_A3: 1218 revstr = "A3"; 1219 break; 1220 default: 1221 ; 1222 } 1223 } 1224 1225 if (sc->sk_type == SK_YUKON_EC) { 1226 switch (sc->sk_rev) { 1227 case SK_YUKON_EC_REV_A1: 1228 revstr = "A1"; 1229 break; 1230 case SK_YUKON_EC_REV_A2: 1231 revstr = "A2"; 1232 break; 1233 case SK_YUKON_EC_REV_A3: 1234 revstr = "A3"; 1235 break; 1236 default: 1237 ; 1238 } 1239 } 1240 1241 if (sc->sk_type == SK_YUKON_EC_U) { 1242 switch (sc->sk_rev) { 1243 case SK_YUKON_EC_U_REV_A0: 1244 revstr = "A0"; 1245 break; 1246 case SK_YUKON_EC_U_REV_A1: 1247 revstr = "A1"; 1248 break; 1249 case SK_YUKON_EC_U_REV_B0: 1250 revstr = "B0"; 1251 break; 1252 default: 1253 ; 1254 } 1255 } 1256 1257 if (sc->sk_type == SK_YUKON_FE) { 1258 switch (sc->sk_rev) { 1259 case SK_YUKON_FE_REV_A1: 1260 revstr = "A1"; 1261 break; 1262 case SK_YUKON_FE_REV_A2: 1263 revstr = "A2"; 1264 break; 1265 default: 1266 ; 1267 } 1268 } 1269 1270 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1271 revstr = "A0"; 1272 1273 if (sc->sk_type == SK_YUKON_EX) { 1274 switch (sc->sk_rev) { 1275 case SK_YUKON_EX_REV_A0: 1276 revstr = "A0"; 1277 break; 1278 case SK_YUKON_EX_REV_B0: 1279 revstr = "B0"; 1280 break; 1281 default: 1282 ; 1283 } 1284 } 1285 1286 if (sc->sk_type == SK_YUKON_SUPR && sc->sk_rev == SK_YUKON_SUPR_REV_A0) 1287 revstr = "A0"; 1288 1289 1290 /* Announce the product name. */ 1291 printf(", %s", sc->sk_name); 1292 if (revstr != NULL) 1293 printf(" rev. %s", revstr); 1294 printf(" (0x%x): %s\n", sc->sk_rev, intrstr); 1295 1296 sc->sk_macs = 1; 1297 1298 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1299 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1300 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1301 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1302 sc->sk_macs++; 1303 } 1304 1305 skca.skc_port = SK_PORT_A; 1306 skca.skc_type = sc->sk_type; 1307 skca.skc_rev = sc->sk_rev; 1308 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1309 1310 if (sc->sk_macs > 1) { 1311 skca.skc_port = SK_PORT_B; 1312 skca.skc_type = sc->sk_type; 1313 skca.skc_rev = sc->sk_rev; 1314 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1315 } 1316 1317 /* Turn on the 'driver is loaded' LED. */ 1318 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1319 1320 return; 1321 1322 fail_5: 1323 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1324 fail_4: 1325 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sk_status_ring, 1326 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1327 fail_3: 1328 bus_dmamem_free(sc->sc_dmatag, 1329 &sc->sk_status_seg, sc->sk_status_nseg); 1330 sc->sk_status_nseg = 0; 1331 fail_2: 1332 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1333 sc->sk_intrhand = NULL; 1334 fail_1: 1335 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1336 sc->sk_bsize = 0; 1337 } 1338 1339 int 1340 mskc_detach(struct device *self, int flags) 1341 { 1342 struct sk_softc *sc = (struct sk_softc *)self; 1343 int rv; 1344 1345 rv = config_detach_children(self, flags); 1346 if (rv != 0) 1347 return (rv); 1348 1349 if (sc->sk_status_nseg > 0) { 1350 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1351 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sk_status_ring, 1352 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1353 bus_dmamem_free(sc->sc_dmatag, 1354 &sc->sk_status_seg, sc->sk_status_nseg); 1355 } 1356 1357 if (sc->sk_intrhand) 1358 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1359 1360 if (sc->sk_bsize > 0) 1361 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1362 1363 return(0); 1364 } 1365 1366 int 1367 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1368 { 1369 struct sk_softc *sc = sc_if->sk_softc; 1370 struct msk_tx_desc *f = NULL; 1371 u_int32_t frag, cur; 1372 int i; 1373 struct sk_txmap_entry *entry; 1374 bus_dmamap_t txmap; 1375 1376 DPRINTFN(2, ("msk_encap\n")); 1377 1378 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1379 if (entry == NULL) { 1380 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1381 return (ENOBUFS); 1382 } 1383 txmap = entry->dmamap; 1384 1385 cur = frag = *txidx; 1386 1387 #ifdef MSK_DEBUG 1388 if (mskdebug >= 2) 1389 msk_dump_mbuf(m_head); 1390 #endif 1391 1392 /* 1393 * Start packing the mbufs in this chain into 1394 * the fragment pointers. Stop when we run out 1395 * of fragments or hit the end of the mbuf chain. 1396 */ 1397 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1398 BUS_DMA_NOWAIT)) { 1399 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1400 return (ENOBUFS); 1401 } 1402 1403 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1404 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1405 bus_dmamap_unload(sc->sc_dmatag, txmap); 1406 return (ENOBUFS); 1407 } 1408 1409 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1410 1411 /* Sync the DMA map. */ 1412 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1413 BUS_DMASYNC_PREWRITE); 1414 1415 for (i = 0; i < txmap->dm_nsegs; i++) { 1416 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1417 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1418 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1419 f->sk_ctl = 0; 1420 if (i == 0) 1421 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1422 else 1423 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1424 cur = frag; 1425 SK_INC(frag, MSK_TX_RING_CNT); 1426 } 1427 1428 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1429 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1430 1431 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1432 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1433 1434 /* Sync descriptors before handing to chip */ 1435 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1436 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1437 1438 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1439 1440 /* Sync first descriptor to hand it off */ 1441 MSK_CDTXSYNC(sc_if, *txidx, 1, 1442 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1443 1444 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1445 1446 #ifdef MSK_DEBUG 1447 if (mskdebug >= 2) { 1448 struct msk_tx_desc *le; 1449 u_int32_t idx; 1450 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1451 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1452 msk_dump_txdesc(le, idx); 1453 } 1454 } 1455 #endif 1456 1457 *txidx = frag; 1458 1459 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1460 1461 return (0); 1462 } 1463 1464 void 1465 msk_start(struct ifnet *ifp) 1466 { 1467 struct sk_if_softc *sc_if = ifp->if_softc; 1468 struct mbuf *m_head = NULL; 1469 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1470 int pkts = 0; 1471 1472 DPRINTFN(2, ("msk_start\n")); 1473 1474 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1475 IFQ_POLL(&ifp->if_snd, m_head); 1476 if (m_head == NULL) 1477 break; 1478 1479 /* 1480 * Pack the data into the transmit ring. If we 1481 * don't have room, set the OACTIVE flag and wait 1482 * for the NIC to drain the ring. 1483 */ 1484 if (msk_encap(sc_if, m_head, &idx)) { 1485 ifp->if_flags |= IFF_OACTIVE; 1486 break; 1487 } 1488 1489 /* now we are committed to transmit the packet */ 1490 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1491 pkts++; 1492 1493 /* 1494 * If there's a BPF listener, bounce a copy of this frame 1495 * to him. 1496 */ 1497 #if NBPFILTER > 0 1498 if (ifp->if_bpf) 1499 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1500 #endif 1501 } 1502 if (pkts == 0) 1503 return; 1504 1505 /* Transmit */ 1506 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1507 sc_if->sk_cdata.sk_tx_prod = idx; 1508 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1509 1510 /* Set a timeout in case the chip goes out to lunch. */ 1511 ifp->if_timer = 5; 1512 } 1513 } 1514 1515 void 1516 msk_watchdog(struct ifnet *ifp) 1517 { 1518 struct sk_if_softc *sc_if = ifp->if_softc; 1519 1520 /* 1521 * Reclaim first as there is a possibility of losing Tx completion 1522 * interrupts. 1523 */ 1524 msk_txeof(sc_if); 1525 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1526 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1527 1528 ifp->if_oerrors++; 1529 1530 /* XXX Resets both ports; we shouldn't do that. */ 1531 mskc_reset(sc_if->sk_softc); 1532 msk_reset(sc_if); 1533 msk_init(sc_if); 1534 } 1535 } 1536 1537 void 1538 mskc_shutdown(void *v) 1539 { 1540 struct sk_softc *sc = v; 1541 1542 DPRINTFN(2, ("msk_shutdown\n")); 1543 1544 /* Turn off the 'driver is loaded' LED. */ 1545 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1546 1547 /* 1548 * Reset the GEnesis controller. Doing this should also 1549 * assert the resets on the attached XMAC(s). 1550 */ 1551 mskc_reset(sc); 1552 } 1553 1554 static __inline int 1555 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1556 { 1557 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1558 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1559 YU_RXSTAT_JABBER)) != 0 || 1560 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1561 YU_RXSTAT_BYTES(stat) != len) 1562 return (0); 1563 1564 return (1); 1565 } 1566 1567 void 1568 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1569 { 1570 struct sk_softc *sc = sc_if->sk_softc; 1571 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1572 struct mbuf *m; 1573 struct sk_chain *cur_rx; 1574 int i, cur, total_len = len; 1575 bus_dmamap_t dmamap; 1576 1577 DPRINTFN(2, ("msk_rxeof\n")); 1578 1579 cur = sc_if->sk_cdata.sk_rx_cons; 1580 1581 /* Sync the descriptor */ 1582 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1583 1584 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1585 if (cur_rx->sk_mbuf == NULL) 1586 return; 1587 1588 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1589 for (i = 0; i < dmamap->dm_nsegs; i++) { 1590 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1591 sc_if->sk_cdata.sk_rx_cnt--; 1592 } 1593 1594 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1595 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1596 bus_dmamap_unload(sc_if->sk_softc->sc_dmatag, dmamap); 1597 1598 m = cur_rx->sk_mbuf; 1599 cur_rx->sk_mbuf = NULL; 1600 1601 if (total_len < SK_MIN_FRAMELEN || 1602 total_len > SK_JUMBO_FRAMELEN || 1603 msk_rxvalid(sc, rxstat, total_len) == 0) { 1604 ifp->if_ierrors++; 1605 m_freem(m); 1606 return; 1607 } 1608 1609 m->m_pkthdr.rcvif = ifp; 1610 m->m_pkthdr.len = m->m_len = total_len; 1611 1612 ifp->if_ipackets++; 1613 1614 #if NBPFILTER > 0 1615 if (ifp->if_bpf) 1616 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1617 #endif 1618 1619 /* pass it on. */ 1620 ether_input_mbuf(ifp, m); 1621 } 1622 1623 void 1624 msk_txeof(struct sk_if_softc *sc_if) 1625 { 1626 struct sk_softc *sc = sc_if->sk_softc; 1627 struct msk_tx_desc *cur_tx; 1628 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1629 u_int32_t idx, reg, sk_ctl; 1630 struct sk_txmap_entry *entry; 1631 1632 DPRINTFN(2, ("msk_txeof\n")); 1633 1634 if (sc_if->sk_port == SK_PORT_A) 1635 reg = SK_STAT_BMU_TXA1_RIDX; 1636 else 1637 reg = SK_STAT_BMU_TXA2_RIDX; 1638 1639 /* 1640 * Go through our tx ring and free mbufs for those 1641 * frames that have been sent. 1642 */ 1643 idx = sc_if->sk_cdata.sk_tx_cons; 1644 while (idx != sk_win_read_2(sc, reg)) { 1645 MSK_CDTXSYNC(sc_if, idx, 1, 1646 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1647 1648 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1649 sk_ctl = cur_tx->sk_ctl; 1650 #ifdef MSK_DEBUG 1651 if (mskdebug >= 2) 1652 msk_dump_txdesc(cur_tx, idx); 1653 #endif 1654 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1655 ifp->if_opackets++; 1656 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1657 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1658 1659 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1660 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1661 1662 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1663 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1664 1665 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1666 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1667 link); 1668 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1669 } 1670 sc_if->sk_cdata.sk_tx_cnt--; 1671 SK_INC(idx, MSK_TX_RING_CNT); 1672 } 1673 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1674 1675 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1676 ifp->if_flags &= ~IFF_OACTIVE; 1677 1678 sc_if->sk_cdata.sk_tx_cons = idx; 1679 } 1680 1681 void 1682 msk_fill_rx_ring(struct sk_if_softc *sc_if) 1683 { 1684 while (sc_if->sk_cdata.sk_rx_cnt < MSK_RX_RING_CNT) { 1685 if (msk_newbuf(sc_if) == ENOBUFS) 1686 break; 1687 } 1688 } 1689 1690 void 1691 msk_tick(void *xsc_if) 1692 { 1693 struct sk_if_softc *sc_if = xsc_if; 1694 struct mii_data *mii = &sc_if->sk_mii; 1695 int s; 1696 1697 s = splnet(); 1698 mii_tick(mii); 1699 splx(s); 1700 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1701 } 1702 1703 void 1704 msk_intr_yukon(struct sk_if_softc *sc_if) 1705 { 1706 u_int8_t status; 1707 1708 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1709 /* RX overrun */ 1710 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1711 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1712 SK_RFCTL_RX_FIFO_OVER); 1713 } 1714 /* TX underrun */ 1715 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1716 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1717 SK_TFCTL_TX_FIFO_UNDER); 1718 } 1719 1720 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1721 } 1722 1723 int 1724 msk_intr(void *xsc) 1725 { 1726 struct sk_softc *sc = xsc; 1727 struct sk_if_softc *sc_if; 1728 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1729 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1730 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1731 int claimed = 0; 1732 u_int32_t status; 1733 struct msk_status_desc *cur_st; 1734 1735 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1736 if (status == 0) { 1737 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1738 return (0); 1739 } 1740 1741 status = CSR_READ_4(sc, SK_ISR); 1742 1743 if (sc_if0 != NULL) 1744 ifp0 = &sc_if0->arpcom.ac_if; 1745 if (sc_if1 != NULL) 1746 ifp1 = &sc_if1->arpcom.ac_if; 1747 1748 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1749 (ifp0->if_flags & IFF_RUNNING)) { 1750 msk_intr_yukon(sc_if0); 1751 } 1752 1753 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1754 (ifp1->if_flags & IFF_RUNNING)) { 1755 msk_intr_yukon(sc_if1); 1756 } 1757 1758 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1759 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1760 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1761 1762 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 1763 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1764 switch (cur_st->sk_opcode) { 1765 case SK_Y2_STOPC_RXSTAT: 1766 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 1767 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 1768 letoh32(cur_st->sk_status)); 1769 msk_fill_rx_ring(sc_if); 1770 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 1771 sc_if->sk_cdata.sk_rx_prod); 1772 break; 1773 case SK_Y2_STOPC_TXSTAT: 1774 if (sc_if0) 1775 msk_txeof(sc_if0); 1776 if (sc_if1) 1777 msk_txeof(sc_if1); 1778 break; 1779 default: 1780 printf("opcode=0x%x\n", cur_st->sk_opcode); 1781 break; 1782 } 1783 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1784 1785 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1786 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1787 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1788 } 1789 1790 if (status & SK_Y2_IMR_BMU) { 1791 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1792 claimed = 1; 1793 } 1794 1795 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1796 1797 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1798 msk_start(ifp0); 1799 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1800 msk_start(ifp1); 1801 1802 return (claimed); 1803 } 1804 1805 void 1806 msk_init_yukon(struct sk_if_softc *sc_if) 1807 { 1808 u_int32_t v; 1809 u_int16_t reg; 1810 struct sk_softc *sc; 1811 int i; 1812 1813 sc = sc_if->sk_softc; 1814 1815 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1816 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1817 1818 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1819 1820 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1821 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1822 1823 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1824 1825 /* unused read of the interrupt source register */ 1826 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1827 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1828 1829 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1830 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1831 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1832 1833 /* MIB Counter Clear Mode set */ 1834 reg |= YU_PAR_MIB_CLR; 1835 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1836 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1837 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1838 1839 /* MIB Counter Clear Mode clear */ 1840 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1841 reg &= ~YU_PAR_MIB_CLR; 1842 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1843 1844 /* receive control reg */ 1845 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1846 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1847 1848 /* transmit parameter register */ 1849 DPRINTFN(6, ("msk_init_yukon: 8\n")); 1850 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 1851 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 1852 1853 /* serial mode register */ 1854 DPRINTFN(6, ("msk_init_yukon: 9\n")); 1855 reg = YU_SMR_DATA_BLIND(0x1c) | 1856 YU_SMR_MFL_VLAN | 1857 YU_SMR_IPG_DATA(0x1e); 1858 1859 if (sc->sk_type != SK_YUKON_FE && 1860 sc->sk_type != SK_YUKON_FE_P) 1861 reg |= YU_SMR_MFL_JUMBO; 1862 1863 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 1864 1865 DPRINTFN(6, ("msk_init_yukon: 10\n")); 1866 /* Setup Yukon's address */ 1867 for (i = 0; i < 3; i++) { 1868 /* Write Source Address 1 (unicast filter) */ 1869 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 1870 sc_if->arpcom.ac_enaddr[i * 2] | 1871 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 1872 } 1873 1874 for (i = 0; i < 3; i++) { 1875 reg = sk_win_read_2(sc_if->sk_softc, 1876 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 1877 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 1878 } 1879 1880 /* Set promiscuous mode */ 1881 msk_setpromisc(sc_if); 1882 1883 /* Set multicast filter */ 1884 DPRINTFN(6, ("msk_init_yukon: 11\n")); 1885 msk_setmulti(sc_if); 1886 1887 /* enable interrupt mask for counter overflows */ 1888 DPRINTFN(6, ("msk_init_yukon: 12\n")); 1889 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 1890 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 1891 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 1892 1893 /* Configure RX MAC FIFO Flush Mask */ 1894 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 1895 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 1896 YU_RXSTAT_JABBER; 1897 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 1898 1899 /* Configure RX MAC FIFO */ 1900 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 1901 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 1902 SK_RFCTL_FIFO_FLUSH_ON); 1903 1904 /* Increase flush threshould to 64 bytes */ 1905 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 1906 SK_RFCTL_FIFO_THRESHOLD + 1); 1907 1908 /* Configure TX MAC FIFO */ 1909 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 1910 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 1911 1912 #if 1 1913 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 1914 #endif 1915 DPRINTFN(6, ("msk_init_yukon: end\n")); 1916 } 1917 1918 /* 1919 * Note that to properly initialize any part of the GEnesis chip, 1920 * you first have to take it out of reset mode. 1921 */ 1922 void 1923 msk_init(void *xsc_if) 1924 { 1925 struct sk_if_softc *sc_if = xsc_if; 1926 struct sk_softc *sc = sc_if->sk_softc; 1927 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1928 struct mii_data *mii = &sc_if->sk_mii; 1929 int s; 1930 1931 DPRINTFN(2, ("msk_init\n")); 1932 1933 s = splnet(); 1934 1935 /* Cancel pending I/O and free all RX/TX buffers. */ 1936 msk_stop(sc_if); 1937 1938 /* Configure I2C registers */ 1939 1940 /* Configure XMAC(s) */ 1941 msk_init_yukon(sc_if); 1942 mii_mediachg(mii); 1943 1944 /* Configure transmit arbiter(s) */ 1945 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 1946 #if 0 1947 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 1948 #endif 1949 1950 /* Configure RAMbuffers */ 1951 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 1952 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 1953 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 1954 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 1955 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 1956 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 1957 1958 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 1959 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 1960 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 1961 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 1962 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 1963 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 1964 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 1965 1966 /* Configure BMUs */ 1967 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 1968 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 1969 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 1970 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_WATERMARK, 0x00000600); 1971 1972 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 1973 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 1974 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 1975 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_WATERMARK, 0x00000600); 1976 1977 /* Make sure the sync transmit queue is disabled. */ 1978 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 1979 1980 /* Init descriptors */ 1981 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 1982 printf("%s: initialization failed: no " 1983 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 1984 msk_stop(sc_if); 1985 splx(s); 1986 return; 1987 } 1988 1989 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 1990 printf("%s: initialization failed: no " 1991 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 1992 msk_stop(sc_if); 1993 splx(s); 1994 return; 1995 } 1996 1997 /* Initialize prefetch engine. */ 1998 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 1999 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2000 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2001 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2002 MSK_RX_RING_ADDR(sc_if, 0)); 2003 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2004 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2005 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2006 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2007 2008 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2009 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2010 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2011 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2012 MSK_TX_RING_ADDR(sc_if, 0)); 2013 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2014 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2015 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2016 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2017 2018 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2019 sc_if->sk_cdata.sk_rx_prod); 2020 2021 /* Configure interrupt handling */ 2022 if (sc_if->sk_port == SK_PORT_A) 2023 sc->sk_intrmask |= SK_Y2_INTRS1; 2024 else 2025 sc->sk_intrmask |= SK_Y2_INTRS2; 2026 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2027 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2028 2029 ifp->if_flags |= IFF_RUNNING; 2030 ifp->if_flags &= ~IFF_OACTIVE; 2031 2032 timeout_add_sec(&sc_if->sk_tick_ch, 1); 2033 2034 splx(s); 2035 } 2036 2037 void 2038 msk_stop(struct sk_if_softc *sc_if) 2039 { 2040 struct sk_softc *sc = sc_if->sk_softc; 2041 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2042 struct sk_txmap_entry *dma; 2043 int i; 2044 2045 DPRINTFN(2, ("msk_stop\n")); 2046 2047 timeout_del(&sc_if->sk_tick_ch); 2048 2049 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2050 2051 /* Stop transfer of Tx descriptors */ 2052 2053 /* Stop transfer of Rx descriptors */ 2054 2055 /* Turn off various components of this interface. */ 2056 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2057 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2058 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2059 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2060 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2061 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2062 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2063 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2064 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2065 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2066 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2067 2068 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2069 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2070 2071 /* Disable interrupts */ 2072 if (sc_if->sk_port == SK_PORT_A) 2073 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2074 else 2075 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2076 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2077 2078 /* Free RX and TX mbufs still in the queues. */ 2079 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2080 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2081 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2082 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2083 } 2084 } 2085 2086 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2087 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2088 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2089 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2090 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2091 sc_if->sk_cdata.sk_tx_map[i], link); 2092 sc_if->sk_cdata.sk_tx_map[i] = 0; 2093 } 2094 } 2095 2096 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2097 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2098 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2099 free(dma, M_DEVBUF); 2100 } 2101 } 2102 2103 struct cfattach mskc_ca = { 2104 sizeof(struct sk_softc), mskc_probe, mskc_attach, mskc_detach 2105 }; 2106 2107 struct cfdriver mskc_cd = { 2108 NULL, "mskc", DV_DULL 2109 }; 2110 2111 struct cfattach msk_ca = { 2112 sizeof(struct sk_if_softc), msk_probe, msk_attach, msk_detach 2113 }; 2114 2115 struct cfdriver msk_cd = { 2116 NULL, "msk", DV_IFNET 2117 }; 2118 2119 #ifdef MSK_DEBUG 2120 void 2121 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2122 { 2123 #define DESC_PRINT(X) \ 2124 if (X) \ 2125 printf("txdesc[%d]." #X "=%#x\n", \ 2126 idx, X); 2127 2128 DESC_PRINT(letoh32(le->sk_addr)); 2129 DESC_PRINT(letoh16(le->sk_len)); 2130 DESC_PRINT(le->sk_ctl); 2131 DESC_PRINT(le->sk_opcode); 2132 #undef DESC_PRINT 2133 } 2134 2135 void 2136 msk_dump_bytes(const char *data, int len) 2137 { 2138 int c, i, j; 2139 2140 for (i = 0; i < len; i += 16) { 2141 printf("%08x ", i); 2142 c = len - i; 2143 if (c > 16) c = 16; 2144 2145 for (j = 0; j < c; j++) { 2146 printf("%02x ", data[i + j] & 0xff); 2147 if ((j & 0xf) == 7 && j > 0) 2148 printf(" "); 2149 } 2150 2151 for (; j < 16; j++) 2152 printf(" "); 2153 printf(" "); 2154 2155 for (j = 0; j < c; j++) { 2156 int ch = data[i + j] & 0xff; 2157 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2158 } 2159 2160 printf("\n"); 2161 2162 if (c < 16) 2163 break; 2164 } 2165 } 2166 2167 void 2168 msk_dump_mbuf(struct mbuf *m) 2169 { 2170 int count = m->m_pkthdr.len; 2171 2172 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2173 2174 while (count > 0 && m) { 2175 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2176 m, m->m_data, m->m_len); 2177 msk_dump_bytes(mtod(m, char *), m->m_len); 2178 2179 count -= m->m_len; 2180 m = m->m_next; 2181 } 2182 } 2183 #endif 2184