1 /* $OpenBSD: if_msk.c,v 1.75 2009/03/29 14:36:34 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include "bpfilter.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/timeout.h> 99 #include <sys/device.h> 100 #include <sys/queue.h> 101 102 #include <net/if.h> 103 #include <net/if_dl.h> 104 #include <net/if_types.h> 105 106 #ifdef INET 107 #include <netinet/in.h> 108 #include <netinet/in_systm.h> 109 #include <netinet/in_var.h> 110 #include <netinet/ip.h> 111 #include <netinet/udp.h> 112 #include <netinet/tcp.h> 113 #include <netinet/if_ether.h> 114 #endif 115 116 #include <net/if_media.h> 117 #include <net/if_vlan_var.h> 118 119 #if NBPFILTER > 0 120 #include <net/bpf.h> 121 #endif 122 123 #include <dev/mii/mii.h> 124 #include <dev/mii/miivar.h> 125 #include <dev/mii/brgphyreg.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/pcidevs.h> 130 131 #include <dev/pci/if_skreg.h> 132 #include <dev/pci/if_mskvar.h> 133 134 int mskc_probe(struct device *, void *, void *); 135 void mskc_attach(struct device *, struct device *self, void *aux); 136 int mskc_detach(struct device *, int); 137 void mskc_reset(struct sk_softc *); 138 void mskc_shutdown(void *); 139 int msk_probe(struct device *, void *, void *); 140 void msk_attach(struct device *, struct device *self, void *aux); 141 int msk_detach(struct device *, int); 142 void msk_reset(struct sk_if_softc *); 143 int mskcprint(void *, const char *); 144 int msk_intr(void *); 145 void msk_intr_yukon(struct sk_if_softc *); 146 static __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 147 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 148 void msk_txeof(struct sk_if_softc *); 149 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 150 void msk_start(struct ifnet *); 151 int msk_ioctl(struct ifnet *, u_long, caddr_t); 152 void msk_init(void *); 153 void msk_init_yukon(struct sk_if_softc *); 154 void msk_stop(struct sk_if_softc *); 155 void msk_watchdog(struct ifnet *); 156 int msk_ifmedia_upd(struct ifnet *); 157 void msk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 158 int msk_newbuf(struct sk_if_softc *); 159 int msk_init_rx_ring(struct sk_if_softc *); 160 int msk_init_tx_ring(struct sk_if_softc *); 161 void msk_fill_rx_ring(struct sk_if_softc *); 162 163 int msk_miibus_readreg(struct device *, int, int); 164 void msk_miibus_writereg(struct device *, int, int, int); 165 void msk_miibus_statchg(struct device *); 166 167 void msk_setmulti(struct sk_if_softc *); 168 void msk_setpromisc(struct sk_if_softc *); 169 void msk_tick(void *); 170 171 #ifdef MSK_DEBUG 172 #define DPRINTF(x) if (mskdebug) printf x 173 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 174 int mskdebug = 0; 175 176 void msk_dump_txdesc(struct msk_tx_desc *, int); 177 void msk_dump_mbuf(struct mbuf *); 178 void msk_dump_bytes(const char *, int); 179 #else 180 #define DPRINTF(x) 181 #define DPRINTFN(n,x) 182 #endif 183 184 /* supported device vendors */ 185 const struct pci_matchid mskc_devices[] = { 186 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 187 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 188 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 189 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8021CU }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8021X }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8022CU }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8022X }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 200 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 201 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 202 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 203 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 204 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 205 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 206 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 207 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 208 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 209 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 210 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 211 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 212 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 213 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 214 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8061CU }, 215 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8061X }, 216 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8062CU }, 217 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8062X }, 218 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 219 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 220 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 221 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 222 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 223 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Sxx }, 224 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9Exx } 225 }; 226 227 static inline u_int32_t 228 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 229 { 230 return CSR_READ_4(sc, reg); 231 } 232 233 static inline u_int16_t 234 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 235 { 236 return CSR_READ_2(sc, reg); 237 } 238 239 static inline u_int8_t 240 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 241 { 242 return CSR_READ_1(sc, reg); 243 } 244 245 static inline void 246 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 247 { 248 CSR_WRITE_4(sc, reg, x); 249 } 250 251 static inline void 252 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 253 { 254 CSR_WRITE_2(sc, reg, x); 255 } 256 257 static inline void 258 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 259 { 260 CSR_WRITE_1(sc, reg, x); 261 } 262 263 int 264 msk_miibus_readreg(struct device *dev, int phy, int reg) 265 { 266 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 267 u_int16_t val; 268 int i; 269 270 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 271 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 272 273 for (i = 0; i < SK_TIMEOUT; i++) { 274 DELAY(1); 275 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 276 if (val & YU_SMICR_READ_VALID) 277 break; 278 } 279 280 if (i == SK_TIMEOUT) { 281 printf("%s: phy failed to come ready\n", 282 sc_if->sk_dev.dv_xname); 283 return (0); 284 } 285 286 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 287 SK_TIMEOUT)); 288 289 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 290 291 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 292 phy, reg, val)); 293 294 return (val); 295 } 296 297 void 298 msk_miibus_writereg(struct device *dev, int phy, int reg, int val) 299 { 300 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 301 int i; 302 303 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 304 phy, reg, val)); 305 306 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 307 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 308 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 309 310 for (i = 0; i < SK_TIMEOUT; i++) { 311 DELAY(1); 312 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 313 break; 314 } 315 316 if (i == SK_TIMEOUT) 317 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 318 } 319 320 void 321 msk_miibus_statchg(struct device *dev) 322 { 323 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 324 struct mii_data *mii = &sc_if->sk_mii; 325 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 326 int gpcr; 327 328 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 329 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 330 331 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 332 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 333 /* Set speed. */ 334 gpcr |= YU_GPCR_SPEED_DIS; 335 switch (IFM_SUBTYPE(mii->mii_media_active)) { 336 case IFM_1000_SX: 337 case IFM_1000_LX: 338 case IFM_1000_CX: 339 case IFM_1000_T: 340 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 341 break; 342 case IFM_100_TX: 343 gpcr |= YU_GPCR_SPEED; 344 break; 345 } 346 347 /* Set duplex. */ 348 gpcr |= YU_GPCR_DPLX_DIS; 349 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 350 gpcr |= YU_GPCR_DUPLEX; 351 352 /* Disable flow control. */ 353 gpcr |= YU_GPCR_FCTL_DIS; 354 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 355 } 356 357 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 358 359 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 360 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 361 } 362 363 void 364 msk_setmulti(struct sk_if_softc *sc_if) 365 { 366 struct ifnet *ifp= &sc_if->arpcom.ac_if; 367 u_int32_t hashes[2] = { 0, 0 }; 368 int h; 369 struct arpcom *ac = &sc_if->arpcom; 370 struct ether_multi *enm; 371 struct ether_multistep step; 372 373 /* First, zot all the existing filters. */ 374 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 375 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 376 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 377 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 378 379 380 /* Now program new ones. */ 381 allmulti: 382 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 383 hashes[0] = 0xFFFFFFFF; 384 hashes[1] = 0xFFFFFFFF; 385 } else { 386 /* First find the tail of the list. */ 387 ETHER_FIRST_MULTI(step, ac, enm); 388 while (enm != NULL) { 389 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 390 ETHER_ADDR_LEN)) { 391 ifp->if_flags |= IFF_ALLMULTI; 392 goto allmulti; 393 } 394 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 395 ((1 << SK_HASH_BITS) - 1); 396 if (h < 32) 397 hashes[0] |= (1 << h); 398 else 399 hashes[1] |= (1 << (h - 32)); 400 401 ETHER_NEXT_MULTI(step, enm); 402 } 403 } 404 405 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 406 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 407 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 408 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 409 } 410 411 void 412 msk_setpromisc(struct sk_if_softc *sc_if) 413 { 414 struct ifnet *ifp = &sc_if->arpcom.ac_if; 415 416 if (ifp->if_flags & IFF_PROMISC) 417 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 418 YU_RCR_UFLEN | YU_RCR_MUFLEN); 419 else 420 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 421 YU_RCR_UFLEN | YU_RCR_MUFLEN); 422 } 423 424 int 425 msk_init_rx_ring(struct sk_if_softc *sc_if) 426 { 427 struct msk_chain_data *cd = &sc_if->sk_cdata; 428 struct msk_ring_data *rd = sc_if->sk_rdata; 429 int i, nexti; 430 431 bzero((char *)rd->sk_rx_ring, 432 sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 433 434 for (i = 0; i < MSK_RX_RING_CNT; i++) { 435 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 436 if (i == (MSK_RX_RING_CNT - 1)) 437 nexti = 0; 438 else 439 nexti = i + 1; 440 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 441 } 442 443 sc_if->sk_cdata.sk_rx_prod = 0; 444 sc_if->sk_cdata.sk_rx_cons = 0; 445 sc_if->sk_cdata.sk_rx_cnt = 0; 446 447 msk_fill_rx_ring(sc_if); 448 return (0); 449 } 450 451 int 452 msk_init_tx_ring(struct sk_if_softc *sc_if) 453 { 454 struct sk_softc *sc = sc_if->sk_softc; 455 struct msk_chain_data *cd = &sc_if->sk_cdata; 456 struct msk_ring_data *rd = sc_if->sk_rdata; 457 bus_dmamap_t dmamap; 458 struct sk_txmap_entry *entry; 459 int i, nexti; 460 461 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 462 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 463 464 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 465 for (i = 0; i < MSK_TX_RING_CNT; i++) { 466 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 467 if (i == (MSK_TX_RING_CNT - 1)) 468 nexti = 0; 469 else 470 nexti = i + 1; 471 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 472 473 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 474 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 475 return (ENOBUFS); 476 477 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 478 if (!entry) { 479 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 480 return (ENOBUFS); 481 } 482 entry->dmamap = dmamap; 483 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 484 } 485 486 sc_if->sk_cdata.sk_tx_prod = 0; 487 sc_if->sk_cdata.sk_tx_cons = 0; 488 sc_if->sk_cdata.sk_tx_cnt = 0; 489 490 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 491 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 492 493 return (0); 494 } 495 496 int 497 msk_newbuf(struct sk_if_softc *sc_if) 498 { 499 struct sk_chain *c; 500 struct msk_rx_desc *r; 501 struct mbuf *m; 502 bus_dmamap_t dmamap; 503 int error; 504 int opcode, i; 505 506 MGETHDR(m, M_DONTWAIT, MT_DATA); 507 if (m == NULL) 508 return (ENOBUFS); 509 510 MCLGETI(m, M_DONTWAIT, &sc_if->arpcom.ac_if, sc_if->sk_pktlen); 511 if ((m->m_flags & M_EXT) == 0) { 512 m_freem(m); 513 return (ENOBUFS); 514 } 515 m->m_len = m->m_pkthdr.len = sc_if->sk_pktlen; 516 m_adj(m, ETHER_ALIGN); 517 518 dmamap = sc_if->sk_cdata.sk_rx_map[sc_if->sk_cdata.sk_rx_prod]; 519 520 error = bus_dmamap_load_mbuf(sc_if->sk_softc->sc_dmatag, dmamap, m, 521 BUS_DMA_READ|BUS_DMA_NOWAIT); 522 if (error) { 523 m_freem(m); 524 return (ENOBUFS); 525 } 526 527 if (dmamap->dm_nsegs > (MSK_RX_RING_CNT - sc_if->sk_cdata.sk_rx_cnt)) { 528 bus_dmamap_unload(sc_if->sk_softc->sc_dmatag, dmamap); 529 m_freem(m); 530 return (ENOBUFS); 531 } 532 533 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 534 dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 535 536 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 537 r = c->sk_le; 538 c->sk_mbuf = m; 539 540 opcode = SK_Y2_RXOPC_PACKET; 541 for (i = 0; i < dmamap->dm_nsegs; i++) { 542 r->sk_addr = htole32(dmamap->dm_segs[i].ds_addr); 543 r->sk_len = htole16(dmamap->dm_segs[i].ds_len); 544 r->sk_ctl = 0; 545 r->sk_opcode = opcode | SK_Y2_RXOPC_OWN; 546 opcode = SK_Y2_RXOPC_BUFFER; 547 548 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 549 sc_if->sk_cdata.sk_rx_cnt++; 550 551 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 552 r = c->sk_le; 553 c->sk_mbuf = NULL; 554 } 555 556 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 557 558 return (0); 559 } 560 561 /* 562 * Set media options. 563 */ 564 int 565 msk_ifmedia_upd(struct ifnet *ifp) 566 { 567 struct sk_if_softc *sc_if = ifp->if_softc; 568 569 mii_mediachg(&sc_if->sk_mii); 570 return (0); 571 } 572 573 /* 574 * Report current media status. 575 */ 576 void 577 msk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 578 { 579 struct sk_if_softc *sc_if = ifp->if_softc; 580 581 mii_pollstat(&sc_if->sk_mii); 582 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 583 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 584 } 585 586 int 587 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 588 { 589 struct sk_if_softc *sc_if = ifp->if_softc; 590 struct ifaddr *ifa = (struct ifaddr *) data; 591 struct ifreq *ifr = (struct ifreq *) data; 592 struct mii_data *mii; 593 int s, error = 0; 594 595 s = splnet(); 596 597 switch(command) { 598 case SIOCSIFADDR: 599 ifp->if_flags |= IFF_UP; 600 if (!(ifp->if_flags & IFF_RUNNING)) 601 msk_init(sc_if); 602 #ifdef INET 603 if (ifa->ifa_addr->sa_family == AF_INET) 604 arp_ifinit(&sc_if->arpcom, ifa); 605 #endif /* INET */ 606 break; 607 608 case SIOCSIFFLAGS: 609 if (ifp->if_flags & IFF_UP) { 610 if (ifp->if_flags & IFF_RUNNING && 611 (sc_if->sk_if_flags ^ ifp->if_flags) & 612 IFF_PROMISC) { 613 msk_setpromisc(sc_if); 614 msk_setmulti(sc_if); 615 } else { 616 if (!(ifp->if_flags & IFF_RUNNING)) 617 msk_init(sc_if); 618 } 619 } else { 620 if (ifp->if_flags & IFF_RUNNING) 621 msk_stop(sc_if); 622 } 623 sc_if->sk_if_flags = ifp->if_flags; 624 break; 625 626 case SIOCGIFMEDIA: 627 case SIOCSIFMEDIA: 628 mii = &sc_if->sk_mii; 629 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 630 break; 631 632 default: 633 error = ether_ioctl(ifp, &sc_if->arpcom, command, data); 634 } 635 636 if (error == ENETRESET) { 637 if (ifp->if_flags & IFF_RUNNING) 638 msk_setmulti(sc_if); 639 error = 0; 640 } 641 642 splx(s); 643 return (error); 644 } 645 646 /* 647 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 648 * IDs against our list and return a device name if we find a match. 649 */ 650 int 651 mskc_probe(struct device *parent, void *match, void *aux) 652 { 653 return (pci_matchbyid((struct pci_attach_args *)aux, mskc_devices, 654 sizeof(mskc_devices)/sizeof(mskc_devices[0]))); 655 } 656 657 /* 658 * Force the GEnesis into reset, then bring it out of reset. 659 */ 660 void 661 mskc_reset(struct sk_softc *sc) 662 { 663 u_int32_t imtimer_ticks, reg1; 664 int reg; 665 666 DPRINTFN(2, ("mskc_reset\n")); 667 668 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 669 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 670 671 DELAY(1000); 672 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 673 DELAY(2); 674 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 675 676 sk_win_write_1(sc, SK_TESTCTL1, 2); 677 678 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 679 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 680 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 681 else 682 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 683 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 684 685 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 686 sk_win_write_1(sc, SK_Y2_CLKGATE, 687 SK_Y2_CLKGATE_LINK1_GATE_DIS | 688 SK_Y2_CLKGATE_LINK2_GATE_DIS | 689 SK_Y2_CLKGATE_LINK1_CORE_DIS | 690 SK_Y2_CLKGATE_LINK2_CORE_DIS | 691 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 692 else 693 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 694 695 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 696 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 697 DELAY(1000); 698 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 699 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 700 701 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 702 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 703 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 704 } 705 706 sk_win_write_1(sc, SK_TESTCTL1, 1); 707 708 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 709 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 710 CSR_READ_2(sc, SK_LINK_CTRL))); 711 712 /* Disable ASF */ 713 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 714 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 715 716 /* Clear I2C IRQ noise */ 717 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 718 719 /* Disable hardware timer */ 720 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 721 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 722 723 /* Disable descriptor polling */ 724 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 725 726 /* Disable time stamps */ 727 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 728 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 729 730 /* Enable RAM interface */ 731 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 732 for (reg = SK_TO0;reg <= SK_TO11; reg++) 733 sk_win_write_1(sc, reg, 36); 734 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 735 for (reg = SK_TO0;reg <= SK_TO11; reg++) 736 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 737 738 /* 739 * Configure interrupt moderation. The moderation timer 740 * defers interrupts specified in the interrupt moderation 741 * timer mask based on the timeout specified in the interrupt 742 * moderation timer init register. Each bit in the timer 743 * register represents one tick, so to specify a timeout in 744 * microseconds, we have to multiply by the correct number of 745 * ticks-per-microsecond. 746 */ 747 switch (sc->sk_type) { 748 case SK_YUKON_EC: 749 case SK_YUKON_XL: 750 case SK_YUKON_FE: 751 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 752 break; 753 default: 754 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 755 } 756 757 /* Reset status ring. */ 758 bzero((char *)sc->sk_status_ring, 759 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 760 sc->sk_status_idx = 0; 761 762 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 763 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 764 765 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 766 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 767 sc->sk_status_map->dm_segs[0].ds_addr); 768 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 769 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 770 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 10); 771 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 16); 772 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 16); 773 774 #if 0 775 sk_win_write_4(sc, SK_Y2_LEV_TIMERINIT, SK_IM_USECS(100)); 776 sk_win_write_4(sc, 0x0ec0, SK_IM_USECS(1000)); 777 778 sk_win_write_4(sc, 0x0ed0, SK_IM_USECS(20)); 779 #else 780 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(4)); 781 #endif 782 783 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 784 785 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 786 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 787 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 788 } 789 790 int 791 msk_probe(struct device *parent, void *match, void *aux) 792 { 793 struct skc_attach_args *sa = aux; 794 795 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 796 return (0); 797 798 switch (sa->skc_type) { 799 case SK_YUKON_XL: 800 case SK_YUKON_EC_U: 801 case SK_YUKON_EX: 802 case SK_YUKON_EC: 803 case SK_YUKON_FE: 804 case SK_YUKON_FE_P: 805 case SK_YUKON_SUPR: 806 case SK_YUKON_ULTRA2: 807 return (1); 808 } 809 810 return (0); 811 } 812 813 void 814 msk_reset(struct sk_if_softc *sc_if) 815 { 816 /* GMAC and GPHY Reset */ 817 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 818 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 819 DELAY(1000); 820 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 821 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 822 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 823 } 824 825 /* 826 * Each XMAC chip is attached as a separate logical IP interface. 827 * Single port cards will have only one logical interface of course. 828 */ 829 void 830 msk_attach(struct device *parent, struct device *self, void *aux) 831 { 832 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 833 struct sk_softc *sc = (struct sk_softc *)parent; 834 struct skc_attach_args *sa = aux; 835 struct ifnet *ifp; 836 caddr_t kva; 837 bus_dma_segment_t seg; 838 int i, rseg; 839 u_int32_t chunk; 840 int mii_flags; 841 int error; 842 843 sc_if->sk_port = sa->skc_port; 844 sc_if->sk_softc = sc; 845 sc->sk_if[sa->skc_port] = sc_if; 846 847 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 848 849 /* 850 * Get station address for this interface. Note that 851 * dual port cards actually come with three station 852 * addresses: one for each port, plus an extra. The 853 * extra one is used by the SysKonnect driver software 854 * as a 'virtual' station address for when both ports 855 * are operating in failover mode. Currently we don't 856 * use this extra address. 857 */ 858 for (i = 0; i < ETHER_ADDR_LEN; i++) 859 sc_if->arpcom.ac_enaddr[i] = 860 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 861 862 printf(": address %s\n", 863 ether_sprintf(sc_if->arpcom.ac_enaddr)); 864 865 /* 866 * Set up RAM buffer addresses. The Yukon2 has a small amount 867 * of SRAM on it, somewhere between 4K and 48K. We need to 868 * divide this up between the transmitter and receiver. We 869 * give the receiver 2/3 of the memory (rounded down), and the 870 * transmitter whatever remains. 871 */ 872 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 873 sc_if->sk_rx_ramstart = 0; 874 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 875 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 876 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 877 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 878 879 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 880 " tx_ramstart=%#x tx_ramend=%#x\n", 881 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 882 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 883 884 /* Allocate the descriptor queues. */ 885 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 886 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 887 printf(": can't alloc rx buffers\n"); 888 goto fail; 889 } 890 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 891 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 892 printf(": can't map dma buffers (%lu bytes)\n", 893 (ulong)sizeof(struct msk_ring_data)); 894 goto fail_1; 895 } 896 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 897 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 898 &sc_if->sk_ring_map)) { 899 printf(": can't create dma map\n"); 900 goto fail_2; 901 } 902 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 903 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 904 printf(": can't load dma map\n"); 905 goto fail_3; 906 } 907 sc_if->sk_rdata = (struct msk_ring_data *)kva; 908 bzero(sc_if->sk_rdata, sizeof(struct msk_ring_data)); 909 910 if (sc->sk_type != SK_YUKON_FE && 911 sc->sk_type != SK_YUKON_FE_P) 912 sc_if->sk_pktlen = SK_JLEN; 913 else 914 sc_if->sk_pktlen = MCLBYTES; 915 916 for (i = 0; i < MSK_RX_RING_CNT; i++) { 917 if ((error = bus_dmamap_create(sc->sc_dmatag, 918 sc_if->sk_pktlen, 4, sc_if->sk_pktlen, 919 0, 0, &sc_if->sk_cdata.sk_rx_map[i])) != 0) { 920 printf("\n%s: unable to create rx DMA map %d, " 921 "error = %d\n", sc->sk_dev.dv_xname, i, error); 922 goto fail_4; 923 } 924 } 925 926 ifp = &sc_if->arpcom.ac_if; 927 ifp->if_softc = sc_if; 928 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 929 ifp->if_ioctl = msk_ioctl; 930 ifp->if_start = msk_start; 931 ifp->if_watchdog = msk_watchdog; 932 ifp->if_baudrate = 1000000000; 933 if (sc->sk_type != SK_YUKON_FE && 934 sc->sk_type != SK_YUKON_FE_P) 935 ifp->if_hardmtu = SK_JUMBO_MTU; 936 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 937 IFQ_SET_READY(&ifp->if_snd); 938 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 939 940 ifp->if_capabilities = IFCAP_VLAN_MTU; 941 942 msk_reset(sc_if); 943 944 /* 945 * Do miibus setup. 946 */ 947 msk_init_yukon(sc_if); 948 949 DPRINTFN(2, ("msk_attach: 1\n")); 950 951 sc_if->sk_mii.mii_ifp = ifp; 952 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 953 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 954 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 955 956 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 957 msk_ifmedia_upd, msk_ifmedia_sts); 958 mii_flags = MIIF_DOPAUSE; 959 if (sc->sk_fibertype) 960 mii_flags |= MIIF_HAVEFIBER; 961 mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0, 962 MII_OFFSET_ANY, mii_flags); 963 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 964 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 965 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 966 0, NULL); 967 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 968 } else 969 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 970 971 timeout_set(&sc_if->sk_tick_ch, msk_tick, sc_if); 972 973 /* 974 * Call MI attach routines. 975 */ 976 if_attach(ifp); 977 ether_ifattach(ifp); 978 979 sc_if->sk_sdhook = shutdownhook_establish(mskc_shutdown, sc); 980 981 DPRINTFN(2, ("msk_attach: end\n")); 982 return; 983 984 fail_4: 985 for (i = 0; i < MSK_RX_RING_CNT; i++) { 986 if (sc_if->sk_cdata.sk_rx_map[i] != NULL) 987 bus_dmamap_destroy(sc->sc_dmatag, 988 sc_if->sk_cdata.sk_rx_map[i]); 989 } 990 991 fail_3: 992 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 993 fail_2: 994 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 995 fail_1: 996 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 997 fail: 998 sc->sk_if[sa->skc_port] = NULL; 999 } 1000 1001 int 1002 msk_detach(struct device *self, int flags) 1003 { 1004 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 1005 struct sk_softc *sc = sc_if->sk_softc; 1006 struct ifnet *ifp= &sc_if->arpcom.ac_if; 1007 1008 if (sc->sk_if[sc_if->sk_port] == NULL) 1009 return (0); 1010 1011 timeout_del(&sc_if->sk_tick_ch); 1012 1013 /* Detach any PHYs we might have. */ 1014 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1015 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1016 1017 /* Delete any remaining media. */ 1018 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1019 1020 if (sc_if->sk_sdhook != NULL) 1021 shutdownhook_disestablish(sc_if->sk_sdhook); 1022 1023 ether_ifdetach(ifp); 1024 if_detach(ifp); 1025 1026 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1027 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc_if->sk_rdata, 1028 sizeof(struct msk_ring_data)); 1029 bus_dmamem_free(sc->sc_dmatag, 1030 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1031 sc->sk_if[sc_if->sk_port] = NULL; 1032 1033 return (0); 1034 } 1035 1036 int 1037 mskcprint(void *aux, const char *pnp) 1038 { 1039 struct skc_attach_args *sa = aux; 1040 1041 if (pnp) 1042 printf("msk port %c at %s", 1043 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1044 else 1045 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1046 return (UNCONF); 1047 } 1048 1049 /* 1050 * Attach the interface. Allocate softc structures, do ifmedia 1051 * setup and ethernet/BPF attach. 1052 */ 1053 void 1054 mskc_attach(struct device *parent, struct device *self, void *aux) 1055 { 1056 struct sk_softc *sc = (struct sk_softc *)self; 1057 struct pci_attach_args *pa = aux; 1058 struct skc_attach_args skca; 1059 pci_chipset_tag_t pc = pa->pa_pc; 1060 pcireg_t command, memtype; 1061 pci_intr_handle_t ih; 1062 const char *intrstr = NULL; 1063 u_int8_t hw, pmd; 1064 char *revstr = NULL; 1065 caddr_t kva; 1066 1067 DPRINTFN(2, ("begin mskc_attach\n")); 1068 1069 /* 1070 * Handle power management nonsense. 1071 */ 1072 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1073 1074 if (command == 0x01) { 1075 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1076 if (command & SK_PSTATE_MASK) { 1077 u_int32_t iobase, membase, irq; 1078 1079 /* Save important PCI config data. */ 1080 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1081 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1082 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1083 1084 /* Reset the power state. */ 1085 printf("%s chip is in D%d power mode " 1086 "-- setting to D0\n", sc->sk_dev.dv_xname, 1087 command & SK_PSTATE_MASK); 1088 command &= 0xFFFFFFFC; 1089 pci_conf_write(pc, pa->pa_tag, 1090 SK_PCI_PWRMGMTCTRL, command); 1091 1092 /* Restore PCI config data. */ 1093 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1094 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1095 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1096 } 1097 } 1098 1099 /* 1100 * Map control/status registers. 1101 */ 1102 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1103 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1104 &sc->sk_bhandle, NULL, &sc->sk_bsize, 0)) { 1105 printf(": can't map mem space\n"); 1106 return; 1107 } 1108 1109 sc->sc_dmatag = pa->pa_dmat; 1110 1111 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1112 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1113 1114 /* bail out here if chip is not recognized */ 1115 if (!(SK_IS_YUKON2(sc))) { 1116 printf(": unknown chip type: %d\n", sc->sk_type); 1117 goto fail_1; 1118 } 1119 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1120 1121 /* Allocate interrupt */ 1122 if (pci_intr_map(pa, &ih)) { 1123 printf(": couldn't map interrupt\n"); 1124 goto fail_1; 1125 } 1126 1127 intrstr = pci_intr_string(pc, ih); 1128 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc, 1129 self->dv_xname); 1130 if (sc->sk_intrhand == NULL) { 1131 printf(": couldn't establish interrupt"); 1132 if (intrstr != NULL) 1133 printf(" at %s", intrstr); 1134 printf("\n"); 1135 goto fail_1; 1136 } 1137 sc->sk_pc = pc; 1138 1139 if (bus_dmamem_alloc(sc->sc_dmatag, 1140 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1141 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1142 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1143 printf(": can't alloc status buffers\n"); 1144 goto fail_2; 1145 } 1146 1147 if (bus_dmamem_map(sc->sc_dmatag, 1148 &sc->sk_status_seg, sc->sk_status_nseg, 1149 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1150 &kva, BUS_DMA_NOWAIT)) { 1151 printf(": can't map dma buffers (%lu bytes)\n", 1152 (ulong)(MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc))); 1153 goto fail_3; 1154 } 1155 if (bus_dmamap_create(sc->sc_dmatag, 1156 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1157 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1158 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1159 printf(": can't create dma map\n"); 1160 goto fail_4; 1161 } 1162 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1163 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1164 NULL, BUS_DMA_NOWAIT)) { 1165 printf(": can't load dma map\n"); 1166 goto fail_5; 1167 } 1168 sc->sk_status_ring = (struct msk_status_desc *)kva; 1169 bzero(sc->sk_status_ring, 1170 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1171 1172 /* Reset the adapter. */ 1173 mskc_reset(sc); 1174 1175 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1176 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1177 1178 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1179 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1180 sc->sk_fibertype = 1; 1181 1182 switch (sc->sk_type) { 1183 case SK_YUKON_XL: 1184 sc->sk_name = "Yukon-2 XL"; 1185 break; 1186 case SK_YUKON_EC_U: 1187 sc->sk_name = "Yukon-2 EC Ultra"; 1188 break; 1189 case SK_YUKON_EX: 1190 sc->sk_name = "Yukon-2 Extreme"; 1191 break; 1192 case SK_YUKON_EC: 1193 sc->sk_name = "Yukon-2 EC"; 1194 break; 1195 case SK_YUKON_FE: 1196 sc->sk_name = "Yukon-2 FE"; 1197 break; 1198 case SK_YUKON_FE_P: 1199 sc->sk_name = "Yukon-2 FE+"; 1200 break; 1201 case SK_YUKON_SUPR: 1202 sc->sk_name = "Yukon-2 Supreme"; 1203 break; 1204 case SK_YUKON_ULTRA2: 1205 sc->sk_name = "Yukon-2 Ultra2"; 1206 break; 1207 default: 1208 sc->sk_name = "Yukon (Unknown)"; 1209 } 1210 1211 if (sc->sk_type == SK_YUKON_XL) { 1212 switch (sc->sk_rev) { 1213 case SK_YUKON_XL_REV_A0: 1214 revstr = "A0"; 1215 break; 1216 case SK_YUKON_XL_REV_A1: 1217 revstr = "A1"; 1218 break; 1219 case SK_YUKON_XL_REV_A2: 1220 revstr = "A2"; 1221 break; 1222 case SK_YUKON_XL_REV_A3: 1223 revstr = "A3"; 1224 break; 1225 default: 1226 ; 1227 } 1228 } 1229 1230 if (sc->sk_type == SK_YUKON_EC) { 1231 switch (sc->sk_rev) { 1232 case SK_YUKON_EC_REV_A1: 1233 revstr = "A1"; 1234 break; 1235 case SK_YUKON_EC_REV_A2: 1236 revstr = "A2"; 1237 break; 1238 case SK_YUKON_EC_REV_A3: 1239 revstr = "A3"; 1240 break; 1241 default: 1242 ; 1243 } 1244 } 1245 1246 if (sc->sk_type == SK_YUKON_EC_U) { 1247 switch (sc->sk_rev) { 1248 case SK_YUKON_EC_U_REV_A0: 1249 revstr = "A0"; 1250 break; 1251 case SK_YUKON_EC_U_REV_A1: 1252 revstr = "A1"; 1253 break; 1254 case SK_YUKON_EC_U_REV_B0: 1255 revstr = "B0"; 1256 break; 1257 default: 1258 ; 1259 } 1260 } 1261 1262 if (sc->sk_type == SK_YUKON_FE) { 1263 switch (sc->sk_rev) { 1264 case SK_YUKON_FE_REV_A1: 1265 revstr = "A1"; 1266 break; 1267 case SK_YUKON_FE_REV_A2: 1268 revstr = "A2"; 1269 break; 1270 default: 1271 ; 1272 } 1273 } 1274 1275 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1276 revstr = "A0"; 1277 1278 if (sc->sk_type == SK_YUKON_EX) { 1279 switch (sc->sk_rev) { 1280 case SK_YUKON_EX_REV_A0: 1281 revstr = "A0"; 1282 break; 1283 case SK_YUKON_EX_REV_B0: 1284 revstr = "B0"; 1285 break; 1286 default: 1287 ; 1288 } 1289 } 1290 1291 if (sc->sk_type == SK_YUKON_SUPR && sc->sk_rev == SK_YUKON_SUPR_REV_A0) 1292 revstr = "A0"; 1293 1294 1295 /* Announce the product name. */ 1296 printf(", %s", sc->sk_name); 1297 if (revstr != NULL) 1298 printf(" rev. %s", revstr); 1299 printf(" (0x%x): %s\n", sc->sk_rev, intrstr); 1300 1301 sc->sk_macs = 1; 1302 1303 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1304 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1305 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1306 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1307 sc->sk_macs++; 1308 } 1309 1310 skca.skc_port = SK_PORT_A; 1311 skca.skc_type = sc->sk_type; 1312 skca.skc_rev = sc->sk_rev; 1313 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1314 1315 if (sc->sk_macs > 1) { 1316 skca.skc_port = SK_PORT_B; 1317 skca.skc_type = sc->sk_type; 1318 skca.skc_rev = sc->sk_rev; 1319 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1320 } 1321 1322 /* Turn on the 'driver is loaded' LED. */ 1323 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1324 1325 return; 1326 1327 fail_5: 1328 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1329 fail_4: 1330 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sk_status_ring, 1331 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1332 fail_3: 1333 bus_dmamem_free(sc->sc_dmatag, 1334 &sc->sk_status_seg, sc->sk_status_nseg); 1335 sc->sk_status_nseg = 0; 1336 fail_2: 1337 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1338 sc->sk_intrhand = NULL; 1339 fail_1: 1340 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1341 sc->sk_bsize = 0; 1342 } 1343 1344 int 1345 mskc_detach(struct device *self, int flags) 1346 { 1347 struct sk_softc *sc = (struct sk_softc *)self; 1348 int rv; 1349 1350 rv = config_detach_children(self, flags); 1351 if (rv != 0) 1352 return (rv); 1353 1354 if (sc->sk_status_nseg > 0) { 1355 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1356 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sk_status_ring, 1357 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1358 bus_dmamem_free(sc->sc_dmatag, 1359 &sc->sk_status_seg, sc->sk_status_nseg); 1360 } 1361 1362 if (sc->sk_intrhand) 1363 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1364 1365 if (sc->sk_bsize > 0) 1366 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1367 1368 return(0); 1369 } 1370 1371 int 1372 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1373 { 1374 struct sk_softc *sc = sc_if->sk_softc; 1375 struct msk_tx_desc *f = NULL; 1376 u_int32_t frag, cur; 1377 int i; 1378 struct sk_txmap_entry *entry; 1379 bus_dmamap_t txmap; 1380 1381 DPRINTFN(2, ("msk_encap\n")); 1382 1383 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1384 if (entry == NULL) { 1385 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1386 return (ENOBUFS); 1387 } 1388 txmap = entry->dmamap; 1389 1390 cur = frag = *txidx; 1391 1392 #ifdef MSK_DEBUG 1393 if (mskdebug >= 2) 1394 msk_dump_mbuf(m_head); 1395 #endif 1396 1397 /* 1398 * Start packing the mbufs in this chain into 1399 * the fragment pointers. Stop when we run out 1400 * of fragments or hit the end of the mbuf chain. 1401 */ 1402 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1403 BUS_DMA_NOWAIT)) { 1404 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1405 return (ENOBUFS); 1406 } 1407 1408 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1409 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1410 bus_dmamap_unload(sc->sc_dmatag, txmap); 1411 return (ENOBUFS); 1412 } 1413 1414 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1415 1416 /* Sync the DMA map. */ 1417 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1418 BUS_DMASYNC_PREWRITE); 1419 1420 for (i = 0; i < txmap->dm_nsegs; i++) { 1421 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1422 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1423 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1424 f->sk_ctl = 0; 1425 if (i == 0) 1426 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1427 else 1428 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1429 cur = frag; 1430 SK_INC(frag, MSK_TX_RING_CNT); 1431 } 1432 1433 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1434 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1435 1436 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1437 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1438 1439 /* Sync descriptors before handing to chip */ 1440 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1441 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1442 1443 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1444 1445 /* Sync first descriptor to hand it off */ 1446 MSK_CDTXSYNC(sc_if, *txidx, 1, 1447 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1448 1449 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1450 1451 #ifdef MSK_DEBUG 1452 if (mskdebug >= 2) { 1453 struct msk_tx_desc *le; 1454 u_int32_t idx; 1455 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1456 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1457 msk_dump_txdesc(le, idx); 1458 } 1459 } 1460 #endif 1461 1462 *txidx = frag; 1463 1464 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1465 1466 return (0); 1467 } 1468 1469 void 1470 msk_start(struct ifnet *ifp) 1471 { 1472 struct sk_if_softc *sc_if = ifp->if_softc; 1473 struct mbuf *m_head = NULL; 1474 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1475 int pkts = 0; 1476 1477 DPRINTFN(2, ("msk_start\n")); 1478 1479 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1480 IFQ_POLL(&ifp->if_snd, m_head); 1481 if (m_head == NULL) 1482 break; 1483 1484 /* 1485 * Pack the data into the transmit ring. If we 1486 * don't have room, set the OACTIVE flag and wait 1487 * for the NIC to drain the ring. 1488 */ 1489 if (msk_encap(sc_if, m_head, &idx)) { 1490 ifp->if_flags |= IFF_OACTIVE; 1491 break; 1492 } 1493 1494 /* now we are committed to transmit the packet */ 1495 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1496 pkts++; 1497 1498 /* 1499 * If there's a BPF listener, bounce a copy of this frame 1500 * to him. 1501 */ 1502 #if NBPFILTER > 0 1503 if (ifp->if_bpf) 1504 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1505 #endif 1506 } 1507 if (pkts == 0) 1508 return; 1509 1510 /* Transmit */ 1511 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1512 sc_if->sk_cdata.sk_tx_prod = idx; 1513 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1514 1515 /* Set a timeout in case the chip goes out to lunch. */ 1516 ifp->if_timer = 5; 1517 } 1518 } 1519 1520 void 1521 msk_watchdog(struct ifnet *ifp) 1522 { 1523 struct sk_if_softc *sc_if = ifp->if_softc; 1524 1525 /* 1526 * Reclaim first as there is a possibility of losing Tx completion 1527 * interrupts. 1528 */ 1529 msk_txeof(sc_if); 1530 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1531 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1532 1533 ifp->if_oerrors++; 1534 1535 /* XXX Resets both ports; we shouldn't do that. */ 1536 mskc_reset(sc_if->sk_softc); 1537 msk_reset(sc_if); 1538 msk_init(sc_if); 1539 } 1540 } 1541 1542 void 1543 mskc_shutdown(void *v) 1544 { 1545 struct sk_softc *sc = v; 1546 1547 DPRINTFN(2, ("msk_shutdown\n")); 1548 1549 /* Turn off the 'driver is loaded' LED. */ 1550 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1551 1552 /* 1553 * Reset the GEnesis controller. Doing this should also 1554 * assert the resets on the attached XMAC(s). 1555 */ 1556 mskc_reset(sc); 1557 } 1558 1559 static __inline int 1560 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1561 { 1562 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1563 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1564 YU_RXSTAT_JABBER)) != 0 || 1565 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1566 YU_RXSTAT_BYTES(stat) != len) 1567 return (0); 1568 1569 return (1); 1570 } 1571 1572 void 1573 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1574 { 1575 struct sk_softc *sc = sc_if->sk_softc; 1576 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1577 struct mbuf *m; 1578 struct sk_chain *cur_rx; 1579 int i, cur, total_len = len; 1580 bus_dmamap_t dmamap; 1581 1582 DPRINTFN(2, ("msk_rxeof\n")); 1583 1584 cur = sc_if->sk_cdata.sk_rx_cons; 1585 1586 /* Sync the descriptor */ 1587 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1588 1589 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1590 if (cur_rx->sk_mbuf == NULL) 1591 return; 1592 1593 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1594 for (i = 0; i < dmamap->dm_nsegs; i++) { 1595 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1596 sc_if->sk_cdata.sk_rx_cnt--; 1597 } 1598 1599 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1600 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1601 bus_dmamap_unload(sc_if->sk_softc->sc_dmatag, dmamap); 1602 1603 m = cur_rx->sk_mbuf; 1604 cur_rx->sk_mbuf = NULL; 1605 1606 if (total_len < SK_MIN_FRAMELEN || 1607 total_len > SK_JUMBO_FRAMELEN || 1608 msk_rxvalid(sc, rxstat, total_len) == 0) { 1609 ifp->if_ierrors++; 1610 m_freem(m); 1611 return; 1612 } 1613 1614 m->m_pkthdr.rcvif = ifp; 1615 m->m_pkthdr.len = m->m_len = total_len; 1616 1617 ifp->if_ipackets++; 1618 1619 #if NBPFILTER > 0 1620 if (ifp->if_bpf) 1621 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1622 #endif 1623 1624 /* pass it on. */ 1625 ether_input_mbuf(ifp, m); 1626 } 1627 1628 void 1629 msk_txeof(struct sk_if_softc *sc_if) 1630 { 1631 struct sk_softc *sc = sc_if->sk_softc; 1632 struct msk_tx_desc *cur_tx; 1633 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1634 u_int32_t idx, reg, sk_ctl; 1635 struct sk_txmap_entry *entry; 1636 1637 DPRINTFN(2, ("msk_txeof\n")); 1638 1639 if (sc_if->sk_port == SK_PORT_A) 1640 reg = SK_STAT_BMU_TXA1_RIDX; 1641 else 1642 reg = SK_STAT_BMU_TXA2_RIDX; 1643 1644 /* 1645 * Go through our tx ring and free mbufs for those 1646 * frames that have been sent. 1647 */ 1648 idx = sc_if->sk_cdata.sk_tx_cons; 1649 while (idx != sk_win_read_2(sc, reg)) { 1650 MSK_CDTXSYNC(sc_if, idx, 1, 1651 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1652 1653 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1654 sk_ctl = cur_tx->sk_ctl; 1655 #ifdef MSK_DEBUG 1656 if (mskdebug >= 2) 1657 msk_dump_txdesc(cur_tx, idx); 1658 #endif 1659 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1660 ifp->if_opackets++; 1661 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1662 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1663 1664 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1665 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1666 1667 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1668 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1669 1670 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1671 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1672 link); 1673 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1674 } 1675 sc_if->sk_cdata.sk_tx_cnt--; 1676 SK_INC(idx, MSK_TX_RING_CNT); 1677 } 1678 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1679 1680 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1681 ifp->if_flags &= ~IFF_OACTIVE; 1682 1683 sc_if->sk_cdata.sk_tx_cons = idx; 1684 } 1685 1686 void 1687 msk_fill_rx_ring(struct sk_if_softc *sc_if) 1688 { 1689 while (sc_if->sk_cdata.sk_rx_cnt < MSK_RX_RING_CNT) { 1690 if (msk_newbuf(sc_if) == ENOBUFS) 1691 break; 1692 } 1693 } 1694 1695 void 1696 msk_tick(void *xsc_if) 1697 { 1698 struct sk_if_softc *sc_if = xsc_if; 1699 struct mii_data *mii = &sc_if->sk_mii; 1700 int s; 1701 1702 s = splnet(); 1703 mii_tick(mii); 1704 splx(s); 1705 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1706 } 1707 1708 void 1709 msk_intr_yukon(struct sk_if_softc *sc_if) 1710 { 1711 u_int8_t status; 1712 1713 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1714 /* RX overrun */ 1715 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1716 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1717 SK_RFCTL_RX_FIFO_OVER); 1718 } 1719 /* TX underrun */ 1720 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1721 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1722 SK_TFCTL_TX_FIFO_UNDER); 1723 } 1724 1725 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1726 } 1727 1728 int 1729 msk_intr(void *xsc) 1730 { 1731 struct sk_softc *sc = xsc; 1732 struct sk_if_softc *sc_if; 1733 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1734 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1735 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1736 int claimed = 0; 1737 u_int32_t status; 1738 struct msk_status_desc *cur_st; 1739 1740 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1741 if (status == 0) { 1742 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1743 return (0); 1744 } 1745 1746 status = CSR_READ_4(sc, SK_ISR); 1747 1748 if (sc_if0 != NULL) 1749 ifp0 = &sc_if0->arpcom.ac_if; 1750 if (sc_if1 != NULL) 1751 ifp1 = &sc_if1->arpcom.ac_if; 1752 1753 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1754 (ifp0->if_flags & IFF_RUNNING)) { 1755 msk_intr_yukon(sc_if0); 1756 } 1757 1758 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1759 (ifp1->if_flags & IFF_RUNNING)) { 1760 msk_intr_yukon(sc_if1); 1761 } 1762 1763 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1764 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1765 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1766 1767 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 1768 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1769 switch (cur_st->sk_opcode) { 1770 case SK_Y2_STOPC_RXSTAT: 1771 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 1772 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 1773 letoh32(cur_st->sk_status)); 1774 msk_fill_rx_ring(sc_if); 1775 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 1776 sc_if->sk_cdata.sk_rx_prod); 1777 break; 1778 case SK_Y2_STOPC_TXSTAT: 1779 if (sc_if0) 1780 msk_txeof(sc_if0); 1781 if (sc_if1) 1782 msk_txeof(sc_if1); 1783 break; 1784 default: 1785 printf("opcode=0x%x\n", cur_st->sk_opcode); 1786 break; 1787 } 1788 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1789 1790 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1791 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1792 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1793 } 1794 1795 if (status & SK_Y2_IMR_BMU) { 1796 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1797 claimed = 1; 1798 } 1799 1800 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1801 1802 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1803 msk_start(ifp0); 1804 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1805 msk_start(ifp1); 1806 1807 return (claimed); 1808 } 1809 1810 void 1811 msk_init_yukon(struct sk_if_softc *sc_if) 1812 { 1813 u_int32_t v; 1814 u_int16_t reg; 1815 struct sk_softc *sc; 1816 int i; 1817 1818 sc = sc_if->sk_softc; 1819 1820 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1821 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1822 1823 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1824 1825 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1826 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1827 1828 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1829 1830 /* unused read of the interrupt source register */ 1831 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1832 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1833 1834 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1835 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1836 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1837 1838 /* MIB Counter Clear Mode set */ 1839 reg |= YU_PAR_MIB_CLR; 1840 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1841 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1842 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1843 1844 /* MIB Counter Clear Mode clear */ 1845 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1846 reg &= ~YU_PAR_MIB_CLR; 1847 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1848 1849 /* receive control reg */ 1850 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1851 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1852 1853 /* transmit parameter register */ 1854 DPRINTFN(6, ("msk_init_yukon: 8\n")); 1855 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 1856 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 1857 1858 /* serial mode register */ 1859 DPRINTFN(6, ("msk_init_yukon: 9\n")); 1860 reg = YU_SMR_DATA_BLIND(0x1c) | 1861 YU_SMR_MFL_VLAN | 1862 YU_SMR_IPG_DATA(0x1e); 1863 1864 if (sc->sk_type != SK_YUKON_FE && 1865 sc->sk_type != SK_YUKON_FE_P) 1866 reg |= YU_SMR_MFL_JUMBO; 1867 1868 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 1869 1870 DPRINTFN(6, ("msk_init_yukon: 10\n")); 1871 /* Setup Yukon's address */ 1872 for (i = 0; i < 3; i++) { 1873 /* Write Source Address 1 (unicast filter) */ 1874 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 1875 sc_if->arpcom.ac_enaddr[i * 2] | 1876 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 1877 } 1878 1879 for (i = 0; i < 3; i++) { 1880 reg = sk_win_read_2(sc_if->sk_softc, 1881 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 1882 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 1883 } 1884 1885 /* Set promiscuous mode */ 1886 msk_setpromisc(sc_if); 1887 1888 /* Set multicast filter */ 1889 DPRINTFN(6, ("msk_init_yukon: 11\n")); 1890 msk_setmulti(sc_if); 1891 1892 /* enable interrupt mask for counter overflows */ 1893 DPRINTFN(6, ("msk_init_yukon: 12\n")); 1894 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 1895 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 1896 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 1897 1898 /* Configure RX MAC FIFO Flush Mask */ 1899 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 1900 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 1901 YU_RXSTAT_JABBER; 1902 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 1903 1904 /* Configure RX MAC FIFO */ 1905 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 1906 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 1907 SK_RFCTL_FIFO_FLUSH_ON); 1908 1909 /* Increase flush threshould to 64 bytes */ 1910 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 1911 SK_RFCTL_FIFO_THRESHOLD + 1); 1912 1913 /* Configure TX MAC FIFO */ 1914 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 1915 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 1916 1917 #if 1 1918 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 1919 #endif 1920 DPRINTFN(6, ("msk_init_yukon: end\n")); 1921 } 1922 1923 /* 1924 * Note that to properly initialize any part of the GEnesis chip, 1925 * you first have to take it out of reset mode. 1926 */ 1927 void 1928 msk_init(void *xsc_if) 1929 { 1930 struct sk_if_softc *sc_if = xsc_if; 1931 struct sk_softc *sc = sc_if->sk_softc; 1932 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1933 struct mii_data *mii = &sc_if->sk_mii; 1934 int s; 1935 1936 DPRINTFN(2, ("msk_init\n")); 1937 1938 s = splnet(); 1939 1940 /* Cancel pending I/O and free all RX/TX buffers. */ 1941 msk_stop(sc_if); 1942 1943 /* Configure I2C registers */ 1944 1945 /* Configure XMAC(s) */ 1946 msk_init_yukon(sc_if); 1947 mii_mediachg(mii); 1948 1949 /* Configure transmit arbiter(s) */ 1950 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 1951 #if 0 1952 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 1953 #endif 1954 1955 /* Configure RAMbuffers */ 1956 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 1957 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 1958 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 1959 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 1960 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 1961 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 1962 1963 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 1964 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 1965 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 1966 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 1967 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 1968 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 1969 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 1970 1971 /* Configure BMUs */ 1972 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 1973 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 1974 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 1975 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_WATERMARK, 0x00000600); 1976 1977 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 1978 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 1979 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 1980 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_WATERMARK, 0x00000600); 1981 1982 /* Make sure the sync transmit queue is disabled. */ 1983 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 1984 1985 /* Init descriptors */ 1986 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 1987 printf("%s: initialization failed: no " 1988 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 1989 msk_stop(sc_if); 1990 splx(s); 1991 return; 1992 } 1993 1994 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 1995 printf("%s: initialization failed: no " 1996 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 1997 msk_stop(sc_if); 1998 splx(s); 1999 return; 2000 } 2001 2002 /* Initialize prefetch engine. */ 2003 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2004 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2005 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2006 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2007 MSK_RX_RING_ADDR(sc_if, 0)); 2008 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2009 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2010 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2011 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2012 2013 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2014 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2015 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2016 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2017 MSK_TX_RING_ADDR(sc_if, 0)); 2018 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2019 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2020 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2021 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2022 2023 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2024 sc_if->sk_cdata.sk_rx_prod); 2025 2026 /* Configure interrupt handling */ 2027 if (sc_if->sk_port == SK_PORT_A) 2028 sc->sk_intrmask |= SK_Y2_INTRS1; 2029 else 2030 sc->sk_intrmask |= SK_Y2_INTRS2; 2031 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2032 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2033 2034 ifp->if_flags |= IFF_RUNNING; 2035 ifp->if_flags &= ~IFF_OACTIVE; 2036 2037 timeout_add_sec(&sc_if->sk_tick_ch, 1); 2038 2039 splx(s); 2040 } 2041 2042 void 2043 msk_stop(struct sk_if_softc *sc_if) 2044 { 2045 struct sk_softc *sc = sc_if->sk_softc; 2046 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2047 struct sk_txmap_entry *dma; 2048 int i; 2049 2050 DPRINTFN(2, ("msk_stop\n")); 2051 2052 timeout_del(&sc_if->sk_tick_ch); 2053 2054 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2055 2056 /* Stop transfer of Tx descriptors */ 2057 2058 /* Stop transfer of Rx descriptors */ 2059 2060 /* Turn off various components of this interface. */ 2061 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2062 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2063 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2064 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2065 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2066 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2067 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2068 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2069 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2070 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2071 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2072 2073 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2074 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2075 2076 /* Disable interrupts */ 2077 if (sc_if->sk_port == SK_PORT_A) 2078 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2079 else 2080 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2081 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2082 2083 /* Free RX and TX mbufs still in the queues. */ 2084 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2085 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2086 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2087 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2088 } 2089 } 2090 2091 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2092 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2093 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2094 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2095 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2096 sc_if->sk_cdata.sk_tx_map[i], link); 2097 sc_if->sk_cdata.sk_tx_map[i] = 0; 2098 } 2099 } 2100 2101 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2102 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2103 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2104 free(dma, M_DEVBUF); 2105 } 2106 } 2107 2108 struct cfattach mskc_ca = { 2109 sizeof(struct sk_softc), mskc_probe, mskc_attach, mskc_detach 2110 }; 2111 2112 struct cfdriver mskc_cd = { 2113 0, "mskc", DV_DULL 2114 }; 2115 2116 struct cfattach msk_ca = { 2117 sizeof(struct sk_if_softc), msk_probe, msk_attach, msk_detach 2118 }; 2119 2120 struct cfdriver msk_cd = { 2121 0, "msk", DV_IFNET 2122 }; 2123 2124 #ifdef MSK_DEBUG 2125 void 2126 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2127 { 2128 #define DESC_PRINT(X) \ 2129 if (X) \ 2130 printf("txdesc[%d]." #X "=%#x\n", \ 2131 idx, X); 2132 2133 DESC_PRINT(letoh32(le->sk_addr)); 2134 DESC_PRINT(letoh16(le->sk_len)); 2135 DESC_PRINT(le->sk_ctl); 2136 DESC_PRINT(le->sk_opcode); 2137 #undef DESC_PRINT 2138 } 2139 2140 void 2141 msk_dump_bytes(const char *data, int len) 2142 { 2143 int c, i, j; 2144 2145 for (i = 0; i < len; i += 16) { 2146 printf("%08x ", i); 2147 c = len - i; 2148 if (c > 16) c = 16; 2149 2150 for (j = 0; j < c; j++) { 2151 printf("%02x ", data[i + j] & 0xff); 2152 if ((j & 0xf) == 7 && j > 0) 2153 printf(" "); 2154 } 2155 2156 for (; j < 16; j++) 2157 printf(" "); 2158 printf(" "); 2159 2160 for (j = 0; j < c; j++) { 2161 int ch = data[i + j] & 0xff; 2162 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2163 } 2164 2165 printf("\n"); 2166 2167 if (c < 16) 2168 break; 2169 } 2170 } 2171 2172 void 2173 msk_dump_mbuf(struct mbuf *m) 2174 { 2175 int count = m->m_pkthdr.len; 2176 2177 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2178 2179 while (count > 0 && m) { 2180 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2181 m, m->m_data, m->m_len); 2182 msk_dump_bytes(mtod(m, char *), m->m_len); 2183 2184 count -= m->m_len; 2185 m = m->m_next; 2186 } 2187 } 2188 #endif 2189