1 /* $OpenBSD: if_lii.c,v 1.18 2008/09/10 14:01:22 blambert Exp $ */ 2 3 /* 4 * Copyright (c) 2007 The NetBSD Foundation. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Driver for Attansic/Atheros's L2 Fast Ethernet controller 31 */ 32 33 #include "bpfilter.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/malloc.h> 42 #include <sys/device.h> 43 #include <sys/timeout.h> 44 45 #include <machine/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 52 #if NBPFILTER > 0 53 #include <net/bpf.h> 54 #endif 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/if_ether.h> 59 #endif 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 #include <dev/pci/pcidevs.h> 67 68 #include <dev/pci/if_liireg.h> 69 70 /*#define LII_DEBUG*/ 71 #ifdef LII_DEBUG 72 #define DPRINTF(x) printf x 73 #else 74 #define DPRINTF(x) 75 #endif 76 77 struct lii_softc { 78 struct device sc_dev; 79 pci_chipset_tag_t sc_pc; 80 pcitag_t sc_tag; 81 82 bus_space_tag_t sc_mmiot; 83 bus_space_handle_t sc_mmioh; 84 bus_size_t sc_mmios; 85 86 /* 87 * We allocate a big chunk of DMA-safe memory for all data exchanges. 88 * It is unfortunate that this chip doesn't seem to do scatter-gather. 89 */ 90 bus_dma_tag_t sc_dmat; 91 bus_dmamap_t sc_ringmap; 92 bus_dma_segment_t sc_ringseg; 93 94 uint8_t *sc_ring; /* the whole area */ 95 size_t sc_ringsize; 96 97 struct rx_pkt *sc_rxp; /* the part used for RX */ 98 struct tx_pkt_status *sc_txs; /* the parts used for TX */ 99 bus_addr_t sc_txsp; 100 char *sc_txdbase; 101 bus_addr_t sc_txdp; 102 103 unsigned int sc_rxcur; 104 /* the active area is [ack; cur[ */ 105 int sc_txs_cur; 106 int sc_txs_ack; 107 int sc_txd_cur; 108 int sc_txd_ack; 109 int sc_free_tx_slots; 110 111 void *sc_ih; 112 113 struct arpcom sc_ac; 114 struct mii_data sc_mii; 115 struct timeout sc_tick; 116 117 int (*sc_memread)(struct lii_softc *, uint32_t, 118 uint32_t *); 119 }; 120 121 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 122 123 int lii_match(struct device *, void *, void *); 124 void lii_attach(struct device *, struct device *, void *); 125 126 struct cfdriver lii_cd = { 127 0, 128 "lii", 129 DV_IFNET 130 }; 131 132 struct cfattach lii_ca = { 133 sizeof(struct lii_softc), 134 lii_match, 135 lii_attach 136 }; 137 138 int lii_reset(struct lii_softc *); 139 int lii_eeprom_present(struct lii_softc *); 140 int lii_read_macaddr(struct lii_softc *, uint8_t *); 141 int lii_eeprom_read(struct lii_softc *, uint32_t, uint32_t *); 142 void lii_spi_configure(struct lii_softc *); 143 int lii_spi_read(struct lii_softc *, uint32_t, uint32_t *); 144 void lii_iff(struct lii_softc *); 145 void lii_tick(void *); 146 147 int lii_alloc_rings(struct lii_softc *); 148 int lii_free_tx_space(struct lii_softc *); 149 void lii_tx_put(struct lii_softc *, struct mbuf *); 150 151 int lii_mii_readreg(struct device *, int, int); 152 void lii_mii_writereg(struct device *, int, int, int); 153 void lii_mii_statchg(struct device *); 154 155 int lii_media_change(struct ifnet *); 156 void lii_media_status(struct ifnet *, struct ifmediareq *); 157 158 int lii_init(struct ifnet *); 159 void lii_start(struct ifnet *); 160 void lii_stop(struct ifnet *); 161 void lii_watchdog(struct ifnet *); 162 int lii_ioctl(struct ifnet *, u_long, caddr_t); 163 164 int lii_intr(void *); 165 void lii_rxintr(struct lii_softc *); 166 void lii_txintr(struct lii_softc *); 167 168 const struct pci_matchid lii_devices[] = { 169 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2 } 170 }; 171 172 #define LII_READ_4(sc,reg) \ 173 bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 174 #define LII_READ_2(sc,reg) \ 175 bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 176 #define LII_READ_1(sc,reg) \ 177 bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 178 #define LII_WRITE_4(sc,reg,val) \ 179 bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 180 #define LII_WRITE_2(sc,reg,val) \ 181 bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 182 #define LII_WRITE_1(sc,reg,val) \ 183 bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 184 185 /* 186 * Those are the default Linux parameters. 187 */ 188 189 #define AT_TXD_NUM 64 190 #define AT_TXD_BUFFER_SIZE 8192 191 #define AT_RXD_NUM 64 192 193 /* Pad the RXD buffer so that the packets are on a 128-byte boundary. */ 194 #define AT_RXD_PADDING 120 195 196 int 197 lii_match(struct device *parent, void *match, void *aux) 198 { 199 return (pci_matchbyid((struct pci_attach_args *)aux, lii_devices, 200 sizeof(lii_devices)/sizeof(lii_devices[0]))); 201 } 202 203 void 204 lii_attach(struct device *parent, struct device *self, void *aux) 205 { 206 struct lii_softc *sc = (struct lii_softc *)self; 207 struct pci_attach_args *pa = aux; 208 struct ifnet *ifp = &sc->sc_ac.ac_if; 209 pci_intr_handle_t ih; 210 pcireg_t memtype; 211 212 sc->sc_pc = pa->pa_pc; 213 sc->sc_tag = pa->pa_tag; 214 sc->sc_dmat = pa->pa_dmat; 215 216 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, PCI_MAPREG_START); 217 if (pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &sc->sc_mmiot, 218 &sc->sc_mmioh, NULL, &sc->sc_mmios, 0)) { 219 printf(": failed to map memory!\n"); 220 return; 221 } 222 223 if (lii_reset(sc)) 224 goto unmap; 225 226 lii_spi_configure(sc); 227 228 if (lii_eeprom_present(sc)) 229 sc->sc_memread = lii_eeprom_read; 230 else 231 sc->sc_memread = lii_spi_read; 232 233 if (lii_read_macaddr(sc, sc->sc_ac.ac_enaddr)) 234 goto unmap; 235 236 if (pci_intr_map(pa, &ih) != 0) { 237 printf(": failed to map interrupt!\n"); 238 goto unmap; 239 } 240 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, 241 lii_intr, sc, DEVNAME(sc)); 242 if (sc->sc_ih == NULL) { 243 printf(": failed to establish interrupt!\n"); 244 goto unmap; 245 } 246 247 if (lii_alloc_rings(sc)) 248 goto deintr; 249 250 printf(": %s, address %s\n", pci_intr_string(sc->sc_pc, ih), 251 ether_sprintf(sc->sc_ac.ac_enaddr)); 252 253 timeout_set(&sc->sc_tick, lii_tick, sc); 254 255 sc->sc_mii.mii_ifp = ifp; 256 sc->sc_mii.mii_readreg = lii_mii_readreg; 257 sc->sc_mii.mii_writereg = lii_mii_writereg; 258 sc->sc_mii.mii_statchg = lii_mii_statchg; 259 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, lii_media_change, 260 lii_media_status); 261 mii_attach(self, &sc->sc_mii, 0xffffffff, 1, 262 MII_OFFSET_ANY, 0); 263 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 264 265 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 266 ifp->if_softc = sc; 267 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 268 ifp->if_capabilities = IFCAP_VLAN_MTU; 269 ifp->if_ioctl = lii_ioctl; 270 ifp->if_start = lii_start; 271 ifp->if_watchdog = lii_watchdog; 272 ifp->if_init = lii_init; 273 IFQ_SET_READY(&ifp->if_snd); 274 275 if_attach(ifp); 276 ether_ifattach(ifp); 277 278 return; 279 280 deintr: 281 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 282 unmap: 283 bus_space_unmap(sc->sc_mmiot, sc->sc_mmioh, sc->sc_mmios); 284 return; 285 } 286 287 int 288 lii_reset(struct lii_softc *sc) 289 { 290 int i; 291 292 DPRINTF(("lii_reset\n")); 293 294 LII_WRITE_4(sc, LII_SMC, SMC_SOFT_RST); 295 DELAY(1000); 296 297 for (i = 0; i < 10; ++i) { 298 if (LII_READ_4(sc, LII_BIS) == 0) 299 break; 300 DELAY(1000); 301 } 302 303 if (i == 10) { 304 printf("%s: reset failed\n", DEVNAME(sc)); 305 return 1; 306 } 307 308 LII_WRITE_4(sc, LII_PHYC, PHYC_ENABLE); 309 DELAY(10); 310 311 /* Init PCI-Express module */ 312 /* Magic Numbers Warning */ 313 LII_WRITE_4(sc, 0x12fc, 0x00006500); 314 LII_WRITE_4(sc, 0x1008, 0x00008000 | 315 LII_READ_4(sc, 0x1008)); 316 317 return 0; 318 } 319 320 int 321 lii_eeprom_present(struct lii_softc *sc) 322 { 323 uint32_t val; 324 325 val = LII_READ_4(sc, LII_SFC); 326 if (val & SFC_EN_VPD) 327 LII_WRITE_4(sc, LII_SFC, val & ~(SFC_EN_VPD)); 328 329 return pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_VPD, 330 NULL, NULL) == 1; 331 } 332 333 int 334 lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 335 { 336 return pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val); 337 } 338 339 void 340 lii_spi_configure(struct lii_softc *sc) 341 { 342 /* 343 * We don't offer a way to configure the SPI Flash vendor parameter, so 344 * the table is given for reference 345 */ 346 static const struct lii_spi_flash_vendor { 347 const char *sfv_name; 348 const uint8_t sfv_opcodes[9]; 349 } lii_sfv[] = { 350 { "Atmel", { 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 } }, 351 { "SST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 } }, 352 { "ST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xab, 0xd8, 0xc7 } }, 353 }; 354 #define SF_OPCODE_WRSR 0 355 #define SF_OPCODE_READ 1 356 #define SF_OPCODE_PRGM 2 357 #define SF_OPCODE_WREN 3 358 #define SF_OPCODE_WRDI 4 359 #define SF_OPCODE_RDSR 5 360 #define SF_OPCODE_RDID 6 361 #define SF_OPCODE_SECT_ER 7 362 #define SF_OPCODE_CHIP_ER 8 363 364 #define SF_DEFAULT_VENDOR 0 365 static const uint8_t vendor = SF_DEFAULT_VENDOR; 366 367 /* 368 * Why isn't WRDI used? Heck if I know. 369 */ 370 371 LII_WRITE_1(sc, LII_SFOP_WRSR, 372 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WRSR]); 373 LII_WRITE_1(sc, LII_SFOP_READ, 374 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_READ]); 375 LII_WRITE_1(sc, LII_SFOP_PROGRAM, 376 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_PRGM]); 377 LII_WRITE_1(sc, LII_SFOP_WREN, 378 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WREN]); 379 LII_WRITE_1(sc, LII_SFOP_RDSR, 380 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDSR]); 381 LII_WRITE_1(sc, LII_SFOP_RDID, 382 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDID]); 383 LII_WRITE_1(sc, LII_SFOP_SC_ERASE, 384 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_SECT_ER]); 385 LII_WRITE_1(sc, LII_SFOP_CHIP_ERASE, 386 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_CHIP_ER]); 387 } 388 389 #define MAKE_SFC(cssetup, clkhi, clklo, cshold, cshi, ins) \ 390 ( (((cssetup) & SFC_CS_SETUP_MASK) \ 391 << SFC_CS_SETUP_SHIFT) \ 392 | (((clkhi) & SFC_CLK_HI_MASK) \ 393 << SFC_CLK_HI_SHIFT) \ 394 | (((clklo) & SFC_CLK_LO_MASK) \ 395 << SFC_CLK_LO_SHIFT) \ 396 | (((cshold) & SFC_CS_HOLD_MASK) \ 397 << SFC_CS_HOLD_SHIFT) \ 398 | (((cshi) & SFC_CS_HI_MASK) \ 399 << SFC_CS_HI_SHIFT) \ 400 | (((ins) & SFC_INS_MASK) \ 401 << SFC_INS_SHIFT)) 402 403 #define CUSTOM_SPI_CS_SETUP 2 404 #define CUSTOM_SPI_CLK_HI 2 405 #define CUSTOM_SPI_CLK_LO 2 406 #define CUSTOM_SPI_CS_HOLD 2 407 #define CUSTOM_SPI_CS_HI 3 408 409 int 410 lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 411 { 412 uint32_t v; 413 int i; 414 415 LII_WRITE_4(sc, LII_SF_DATA, 0); 416 LII_WRITE_4(sc, LII_SF_ADDR, reg); 417 418 v = SFC_WAIT_READY | 419 MAKE_SFC(CUSTOM_SPI_CS_SETUP, CUSTOM_SPI_CLK_HI, 420 CUSTOM_SPI_CLK_LO, CUSTOM_SPI_CS_HOLD, CUSTOM_SPI_CS_HI, 1); 421 422 LII_WRITE_4(sc, LII_SFC, v); 423 v |= SFC_START; 424 LII_WRITE_4(sc, LII_SFC, v); 425 426 for (i = 0; i < 10; ++i) { 427 DELAY(1000); 428 if (!(LII_READ_4(sc, LII_SFC) & SFC_START)) 429 break; 430 } 431 if (i == 10) 432 return EBUSY; 433 434 *val = LII_READ_4(sc, LII_SF_DATA); 435 return 0; 436 } 437 438 int 439 lii_read_macaddr(struct lii_softc *sc, uint8_t *ea) 440 { 441 uint32_t offset = 0x100; 442 uint32_t val, val1, addr0 = 0, addr1 = 0; 443 uint8_t found = 0; 444 445 while ((*sc->sc_memread)(sc, offset, &val) == 0) { 446 offset += 4; 447 448 /* Each chunk of data starts with a signature */ 449 if ((val & 0xff) != 0x5a) 450 break; 451 if ((*sc->sc_memread)(sc, offset, &val1)) 452 break; 453 454 offset += 4; 455 456 val >>= 16; 457 switch (val) { 458 case LII_MAC_ADDR_0: 459 addr0 = val1; 460 ++found; 461 break; 462 case LII_MAC_ADDR_1: 463 addr1 = val1; 464 ++found; 465 break; 466 default: 467 continue; 468 } 469 } 470 471 if (found < 2) { 472 printf(": error reading MAC address\n"); 473 return 1; 474 } 475 476 addr0 = htole32(addr0); 477 addr1 = htole32(addr1); 478 479 if ((addr0 == 0xffffff && (addr1 & 0xffff) == 0xffff) || 480 (addr0 == 0 && (addr1 & 0xffff) == 0)) { 481 addr0 = htole32(LII_READ_4(sc, LII_MAC_ADDR_0)); 482 addr1 = htole32(LII_READ_4(sc, LII_MAC_ADDR_1)); 483 } 484 485 ea[0] = (addr1 & 0x0000ff00) >> 8; 486 ea[1] = (addr1 & 0x000000ff); 487 ea[2] = (addr0 & 0xff000000) >> 24; 488 ea[3] = (addr0 & 0x00ff0000) >> 16; 489 ea[4] = (addr0 & 0x0000ff00) >> 8; 490 ea[5] = (addr0 & 0x000000ff); 491 492 return 0; 493 } 494 495 int 496 lii_mii_readreg(struct device *dev, int phy, int reg) 497 { 498 struct lii_softc *sc = (struct lii_softc *)dev; 499 uint32_t val; 500 int i; 501 502 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 503 504 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 505 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 506 507 val |= MDIOC_READ; 508 509 LII_WRITE_4(sc, LII_MDIOC, val); 510 511 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 512 DELAY(2); 513 val = LII_READ_4(sc, LII_MDIOC); 514 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 515 break; 516 } 517 518 if (i == MDIO_WAIT_TIMES) { 519 printf("%s: timeout reading PHY %d reg %d\n", DEVNAME(sc), phy, 520 reg); 521 } 522 523 return (val & 0x0000ffff); 524 } 525 526 void 527 lii_mii_writereg(struct device *dev, int phy, int reg, int data) 528 { 529 struct lii_softc *sc = (struct lii_softc *)dev; 530 uint32_t val; 531 int i; 532 533 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 534 val |= (data & MDIOC_DATA_MASK) << MDIOC_DATA_SHIFT; 535 536 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 537 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 538 539 /* val |= MDIOC_WRITE; */ 540 541 LII_WRITE_4(sc, LII_MDIOC, val); 542 543 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 544 DELAY(2); 545 val = LII_READ_4(sc, LII_MDIOC); 546 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 547 break; 548 } 549 550 if (i == MDIO_WAIT_TIMES) { 551 printf("%s: timeout writing PHY %d reg %d\n", DEVNAME(sc), phy, 552 reg); 553 } 554 } 555 556 void 557 lii_mii_statchg(struct device *dev) 558 { 559 struct lii_softc *sc = (struct lii_softc *)dev; 560 uint32_t val; 561 562 DPRINTF(("lii_mii_statchg\n")); 563 564 val = LII_READ_4(sc, LII_MACC); 565 566 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) 567 val |= MACC_FDX; 568 else 569 val &= ~MACC_FDX; 570 571 LII_WRITE_4(sc, LII_MACC, val); 572 } 573 574 int 575 lii_media_change(struct ifnet *ifp) 576 { 577 struct lii_softc *sc = ifp->if_softc; 578 579 DPRINTF(("lii_media_change\n")); 580 581 if (ifp->if_flags & IFF_UP) 582 mii_mediachg(&sc->sc_mii); 583 return 0; 584 } 585 586 void 587 lii_media_status(struct ifnet *ifp, struct ifmediareq *imr) 588 { 589 struct lii_softc *sc = ifp->if_softc; 590 591 DPRINTF(("lii_media_status\n")); 592 593 mii_pollstat(&sc->sc_mii); 594 imr->ifm_status = sc->sc_mii.mii_media_status; 595 imr->ifm_active = sc->sc_mii.mii_media_active; 596 } 597 598 int 599 lii_init(struct ifnet *ifp) 600 { 601 struct lii_softc *sc = ifp->if_softc; 602 uint32_t val; 603 int error; 604 605 DPRINTF(("lii_init\n")); 606 607 lii_stop(ifp); 608 609 memset(sc->sc_ring, 0, sc->sc_ringsize); 610 611 /* Disable all interrupts */ 612 LII_WRITE_4(sc, LII_ISR, 0xffffffff); 613 614 LII_WRITE_4(sc, LII_DESC_BASE_ADDR_HI, 0); 615 /* XXX 616 sc->sc_ringmap->dm_segs[0].ds_addr >> 32); 617 */ 618 LII_WRITE_4(sc, LII_RXD_BASE_ADDR_LO, 619 (sc->sc_ringmap->dm_segs[0].ds_addr & 0xffffffff) 620 + AT_RXD_PADDING); 621 LII_WRITE_4(sc, LII_TXS_BASE_ADDR_LO, 622 sc->sc_txsp & 0xffffffff); 623 LII_WRITE_4(sc, LII_TXD_BASE_ADDR_LO, 624 sc->sc_txdp & 0xffffffff); 625 626 LII_WRITE_2(sc, LII_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4); 627 LII_WRITE_2(sc, LII_TXS_NUM_ENTRIES, AT_TXD_NUM); 628 LII_WRITE_2(sc, LII_RXD_NUM_ENTRIES, AT_RXD_NUM); 629 630 /* 631 * Inter Paket Gap Time = 0x60 (IPGT) 632 * Minimum inter-frame gap for RX = 0x50 (MIFG) 633 * 64-bit Carrier-Sense window = 0x40 (IPGR1) 634 * 96-bit IPG window = 0x60 (IPGR2) 635 */ 636 LII_WRITE_4(sc, LII_MIPFG, 0x60405060); 637 638 /* 639 * Collision window = 0x37 (LCOL) 640 * Maximum # of retrans = 0xf (RETRY) 641 * Maximum binary expansion # = 0xa (ABEBT) 642 * IPG to start jam = 0x7 (JAMIPG) 643 */ 644 LII_WRITE_4(sc, LII_MHDC, 0x07a0f037 | 645 MHDC_EXC_DEF_EN); 646 647 /* 100 means 200us */ 648 LII_WRITE_2(sc, LII_IMTIV, 100); 649 LII_WRITE_2(sc, LII_SMC, SMC_ITIMER_EN); 650 651 /* 500000 means 100ms */ 652 LII_WRITE_2(sc, LII_IALTIV, 50000); 653 654 LII_WRITE_4(sc, LII_MTU, ifp->if_mtu + ETHER_HDR_LEN 655 + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 656 657 /* unit unknown for TX cur-through threshold */ 658 LII_WRITE_4(sc, LII_TX_CUT_THRESH, 0x177); 659 660 LII_WRITE_2(sc, LII_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8); 661 LII_WRITE_2(sc, LII_PAUSE_OFF_TH, AT_RXD_NUM / 12); 662 663 sc->sc_rxcur = 0; 664 sc->sc_txs_cur = sc->sc_txs_ack = 0; 665 sc->sc_txd_cur = sc->sc_txd_ack = 0; 666 sc->sc_free_tx_slots = 1; 667 LII_WRITE_2(sc, LII_MB_TXD_WR_IDX, sc->sc_txd_cur); 668 LII_WRITE_2(sc, LII_MB_RXD_RD_IDX, sc->sc_rxcur); 669 670 LII_WRITE_1(sc, LII_DMAR, DMAR_EN); 671 LII_WRITE_1(sc, LII_DMAW, DMAW_EN); 672 673 LII_WRITE_4(sc, LII_SMC, LII_READ_4(sc, LII_SMC) | SMC_MANUAL_INT); 674 675 error = ((LII_READ_4(sc, LII_ISR) & ISR_PHY_LINKDOWN) != 0); 676 LII_WRITE_4(sc, LII_ISR, 0x3fffffff); 677 LII_WRITE_4(sc, LII_ISR, 0); 678 if (error) { 679 printf("%s: init failed\n", DEVNAME(sc)); 680 goto out; 681 } 682 683 /* 684 * Initialise MAC. 685 */ 686 val = LII_READ_4(sc, LII_MACC) & MACC_FDX; 687 688 val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY | 689 MACC_TX_FLOW_EN | MACC_RX_FLOW_EN | 690 MACC_ADD_CRC | MACC_PAD | MACC_BCAST_EN; 691 692 val |= 7 << MACC_PREAMBLE_LEN_SHIFT; 693 val |= 2 << MACC_HDX_LEFT_BUF_SHIFT; 694 695 LII_WRITE_4(sc, LII_MACC, val); 696 697 /* Program promiscuous mode and multicast filters. */ 698 lii_iff(sc); 699 700 mii_mediachg(&sc->sc_mii); 701 702 LII_WRITE_4(sc, LII_IMR, IMR_NORMAL_MASK); 703 704 timeout_add_sec(&sc->sc_tick, 1); 705 706 ifp->if_flags |= IFF_RUNNING; 707 ifp->if_flags &= ~IFF_OACTIVE; 708 709 out: 710 return error; 711 } 712 713 void 714 lii_tx_put(struct lii_softc *sc, struct mbuf *m) 715 { 716 int left; 717 struct tx_pkt_header *tph = 718 (struct tx_pkt_header *)(sc->sc_txdbase + sc->sc_txd_cur); 719 720 memset(tph, 0, sizeof *tph); 721 tph->txph_size = m->m_pkthdr.len; 722 723 sc->sc_txd_cur = (sc->sc_txd_cur + 4) % AT_TXD_BUFFER_SIZE; 724 725 /* 726 * We already know we have enough space, so if there is a part of the 727 * space ahead of txd_cur that is active, it doesn't matter because 728 * left will be large enough even without it. 729 */ 730 left = AT_TXD_BUFFER_SIZE - sc->sc_txd_cur; 731 732 if (left > m->m_pkthdr.len) { 733 m_copydata(m, 0, m->m_pkthdr.len, 734 sc->sc_txdbase + sc->sc_txd_cur); 735 sc->sc_txd_cur += m->m_pkthdr.len; 736 } else { 737 m_copydata(m, 0, left, sc->sc_txdbase + sc->sc_txd_cur); 738 m_copydata(m, left, m->m_pkthdr.len - left, sc->sc_txdbase); 739 sc->sc_txd_cur = m->m_pkthdr.len - left; 740 } 741 742 /* Round to a 32-bit boundary */ 743 sc->sc_txd_cur = ((sc->sc_txd_cur + 3) & ~3) % AT_TXD_BUFFER_SIZE; 744 if (sc->sc_txd_cur == sc->sc_txd_ack) 745 sc->sc_free_tx_slots = 0; 746 } 747 748 int 749 lii_free_tx_space(struct lii_softc *sc) 750 { 751 int space; 752 753 if (sc->sc_txd_cur >= sc->sc_txd_ack) 754 space = (AT_TXD_BUFFER_SIZE - sc->sc_txd_cur) + 755 sc->sc_txd_ack; 756 else 757 space = sc->sc_txd_ack - sc->sc_txd_cur; 758 759 /* Account for the tx_pkt_header */ 760 return (space - 4); 761 } 762 763 void 764 lii_start(struct ifnet *ifp) 765 { 766 struct lii_softc *sc = ifp->if_softc; 767 struct mbuf *m0; 768 769 DPRINTF(("lii_start\n")); 770 771 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 772 return; 773 774 for (;;) { 775 IFQ_POLL(&ifp->if_snd, m0); 776 if (m0 == NULL) 777 break; 778 779 if (!sc->sc_free_tx_slots || 780 lii_free_tx_space(sc) < m0->m_pkthdr.len) { 781 ifp->if_flags |= IFF_OACTIVE; 782 break; 783 } 784 785 lii_tx_put(sc, m0); 786 787 DPRINTF(("lii_start: put %d\n", sc->sc_txs_cur)); 788 789 sc->sc_txs[sc->sc_txs_cur].txps_update = 0; 790 sc->sc_txs_cur = (sc->sc_txs_cur + 1) % AT_TXD_NUM; 791 if (sc->sc_txs_cur == sc->sc_txs_ack) 792 sc->sc_free_tx_slots = 0; 793 794 LII_WRITE_2(sc, LII_MB_TXD_WR_IDX, sc->sc_txd_cur/4); 795 796 IFQ_DEQUEUE(&ifp->if_snd, m0); 797 798 #if NBPFILTER > 0 799 if (ifp->if_bpf != NULL) 800 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 801 #endif 802 m_freem(m0); 803 } 804 } 805 806 void 807 lii_stop(struct ifnet *ifp) 808 { 809 struct lii_softc *sc = ifp->if_softc; 810 811 timeout_del(&sc->sc_tick); 812 813 ifp->if_timer = 0; 814 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 815 816 mii_down(&sc->sc_mii); 817 818 lii_reset(sc); 819 820 LII_WRITE_4(sc, LII_IMR, 0); 821 } 822 823 int 824 lii_intr(void *v) 825 { 826 struct lii_softc *sc = v; 827 uint32_t status; 828 829 status = LII_READ_4(sc, LII_ISR); 830 if (status == 0) 831 return 0; 832 833 DPRINTF(("lii_intr (%x)\n", status)); 834 835 /* Clear the interrupt and disable them */ 836 LII_WRITE_4(sc, LII_ISR, status | ISR_DIS_INT); 837 838 if (status & (ISR_PHY | ISR_MANUAL)) { 839 /* Ack PHY interrupt. Magic register */ 840 if (status & ISR_PHY) 841 (void)lii_mii_readreg(&sc->sc_dev, 1, 19); 842 mii_mediachg(&sc->sc_mii); 843 } 844 845 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | ISR_PHY_LINKDOWN)) { 846 lii_init(&sc->sc_ac.ac_if); 847 return 1; 848 } 849 850 if (status & ISR_RX_EVENT) { 851 #ifdef LII_DEBUG 852 if (!(status & ISR_RS_UPDATE)) 853 printf("rxintr %08x\n", status); 854 #endif 855 lii_rxintr(sc); 856 } 857 858 if (status & ISR_TX_EVENT) 859 lii_txintr(sc); 860 861 /* Re-enable interrupts */ 862 LII_WRITE_4(sc, LII_ISR, 0); 863 864 return 1; 865 } 866 867 void 868 lii_rxintr(struct lii_softc *sc) 869 { 870 struct ifnet *ifp = &sc->sc_ac.ac_if; 871 struct rx_pkt *rxp; 872 struct mbuf *m; 873 uint16_t size; 874 875 DPRINTF(("lii_rxintr\n")); 876 877 for (;;) { 878 rxp = &sc->sc_rxp[sc->sc_rxcur]; 879 if (rxp->rxp_update == 0) 880 break; 881 882 DPRINTF(("lii_rxintr: getting %u (%u) [%x]\n", sc->sc_rxcur, 883 rxp->rxp_size, rxp->rxp_flags)); 884 sc->sc_rxcur = (sc->sc_rxcur + 1) % AT_RXD_NUM; 885 rxp->rxp_update = 0; 886 if (!(rxp->rxp_flags & LII_RXF_SUCCESS)) { 887 ++ifp->if_ierrors; 888 continue; 889 } 890 891 MGETHDR(m, M_DONTWAIT, MT_DATA); 892 if (m == NULL) { 893 ++ifp->if_ierrors; 894 continue; 895 } 896 size = rxp->rxp_size - ETHER_CRC_LEN; 897 if (size > MHLEN) { 898 MCLGET(m, M_DONTWAIT); 899 if ((m->m_flags & M_EXT) == 0) { 900 m_freem(m); 901 ++ifp->if_ierrors; 902 continue; 903 } 904 } 905 906 m->m_pkthdr.rcvif = ifp; 907 /* Copy the packet withhout the FCS */ 908 m->m_pkthdr.len = m->m_len = size; 909 memcpy(mtod(m, void *), &rxp->rxp_data[0], size); 910 ++ifp->if_ipackets; 911 912 #if NBPFILTER > 0 913 if (ifp->if_bpf) 914 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 915 #endif 916 917 ether_input_mbuf(ifp, m); 918 } 919 920 LII_WRITE_4(sc, LII_MB_RXD_RD_IDX, sc->sc_rxcur); 921 } 922 923 void 924 lii_txintr(struct lii_softc *sc) 925 { 926 struct ifnet *ifp = &sc->sc_ac.ac_if; 927 struct tx_pkt_status *txs; 928 struct tx_pkt_header *txph; 929 930 DPRINTF(("lii_txintr\n")); 931 932 for (;;) { 933 txs = &sc->sc_txs[sc->sc_txs_ack]; 934 if (txs->txps_update == 0) 935 break; 936 DPRINTF(("lii_txintr: ack'd %d\n", sc->sc_txs_ack)); 937 sc->sc_txs_ack = (sc->sc_txs_ack + 1) % AT_TXD_NUM; 938 sc->sc_free_tx_slots = 1; 939 940 txs->txps_update = 0; 941 942 txph = (struct tx_pkt_header *) 943 (sc->sc_txdbase + sc->sc_txd_ack); 944 945 if (txph->txph_size != txs->txps_size) { 946 printf("%s: mismatched status and packet\n", 947 DEVNAME(sc)); 948 } 949 950 /* 951 * Move ack by the packet size, taking the packet header in 952 * account and round to the next 32-bit boundary 953 * (7 = sizeof(header) + 3) 954 */ 955 sc->sc_txd_ack = (sc->sc_txd_ack + txph->txph_size + 7 ) & ~3; 956 sc->sc_txd_ack %= AT_TXD_BUFFER_SIZE; 957 958 if (txs->txps_flags & LII_TXF_SUCCESS) 959 ++ifp->if_opackets; 960 else 961 ++ifp->if_oerrors; 962 ifp->if_flags &= ~IFF_OACTIVE; 963 } 964 965 if (sc->sc_free_tx_slots) 966 lii_start(ifp); 967 } 968 969 int 970 lii_alloc_rings(struct lii_softc *sc) 971 { 972 int nsegs; 973 bus_size_t bs; 974 975 /* 976 * We need a big chunk of DMA-friendly memory because descriptors 977 * are not separate from data on that crappy hardware, which means 978 * we'll have to copy data from and to that memory zone to and from 979 * the mbufs. 980 * 981 * How lame is that? Using the default values from the Linux driver, 982 * we allocate space for receiving up to 64 full-size Ethernet frames, 983 * and only 8kb for transmitting up to 64 Ethernet frames. 984 */ 985 986 sc->sc_ringsize = bs = AT_RXD_PADDING 987 + AT_RXD_NUM * sizeof(struct rx_pkt) 988 + AT_TXD_NUM * sizeof(struct tx_pkt_status) 989 + AT_TXD_BUFFER_SIZE; 990 991 if (bus_dmamap_create(sc->sc_dmat, bs, 1, bs, (1<<30), 992 BUS_DMA_NOWAIT, &sc->sc_ringmap) != 0) { 993 printf(": failed to create DMA map!\n"); 994 return 1; 995 } 996 997 if (bus_dmamem_alloc(sc->sc_dmat, bs, PAGE_SIZE, (1<<30), 998 &sc->sc_ringseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) { 999 printf(": failed to allocate DMA memory!\n"); 1000 goto destroy; 1001 } 1002 1003 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_ringseg, nsegs, bs, 1004 (caddr_t *)&sc->sc_ring, BUS_DMA_NOWAIT) != 0) { 1005 printf(": failed to map DMA memory!\n"); 1006 goto free; 1007 } 1008 1009 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ringmap, sc->sc_ring, 1010 bs, NULL, BUS_DMA_NOWAIT) != 0) { 1011 printf(": failed to load DMA memory!\n"); 1012 goto unmap; 1013 } 1014 1015 sc->sc_rxp = (void *)(sc->sc_ring + AT_RXD_PADDING); 1016 sc->sc_txs = (void *)(sc->sc_ring + AT_RXD_PADDING 1017 + AT_RXD_NUM * sizeof(struct rx_pkt)); 1018 sc->sc_txdbase = ((char *)sc->sc_txs) 1019 + AT_TXD_NUM * sizeof(struct tx_pkt_status); 1020 sc->sc_txsp = sc->sc_ringmap->dm_segs[0].ds_addr 1021 + ((char *)sc->sc_txs - (char *)sc->sc_ring); 1022 sc->sc_txdp = sc->sc_ringmap->dm_segs[0].ds_addr 1023 + ((char *)sc->sc_txdbase - (char *)sc->sc_ring); 1024 1025 return 0; 1026 1027 unmap: 1028 bus_dmamem_unmap(sc->sc_dmat, sc->sc_ring, bs); 1029 free: 1030 bus_dmamem_free(sc->sc_dmat, &sc->sc_ringseg, nsegs); 1031 destroy: 1032 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ringmap); 1033 return 1; 1034 } 1035 1036 void 1037 lii_watchdog(struct ifnet *ifp) 1038 { 1039 struct lii_softc *sc = ifp->if_softc; 1040 1041 printf("%s: watchdog timeout\n", DEVNAME(sc)); 1042 ++ifp->if_oerrors; 1043 lii_init(ifp); 1044 } 1045 1046 int 1047 lii_ioctl(struct ifnet *ifp, u_long cmd, caddr_t addr) 1048 { 1049 struct lii_softc *sc = ifp->if_softc; 1050 struct ifreq *ifr = (struct ifreq *)addr; 1051 struct ifaddr *ifa; 1052 int s, error; 1053 1054 s = splnet(); 1055 1056 error = ether_ioctl(ifp, &sc->sc_ac, cmd, addr); 1057 if (error > 0) 1058 goto err; 1059 1060 switch(cmd) { 1061 case SIOCSIFADDR: 1062 SET(ifp->if_flags, IFF_UP); 1063 #ifdef INET 1064 ifa = (struct ifaddr *)addr; 1065 if (ifa->ifa_addr->sa_family == AF_INET) 1066 arp_ifinit(&sc->sc_ac, ifa); 1067 #endif 1068 /* FALLTHROUGH */ 1069 case SIOCSIFFLAGS: 1070 if (ISSET(ifp->if_flags, IFF_UP)) { 1071 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1072 error = ENETRESET; 1073 else 1074 lii_init(ifp); 1075 } else { 1076 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1077 lii_stop(ifp); 1078 } 1079 break; 1080 1081 case SIOCADDMULTI: 1082 error = ether_addmulti(ifr, &sc->sc_ac); 1083 break; 1084 case SIOCDELMULTI: 1085 error = ether_delmulti(ifr, &sc->sc_ac); 1086 break; 1087 1088 case SIOCSIFMEDIA: 1089 case SIOCGIFMEDIA: 1090 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1091 break; 1092 default: 1093 error = ENOTTY; 1094 break; 1095 } 1096 1097 err: 1098 if (error == ENETRESET) { 1099 if (ifp->if_flags & IFF_RUNNING) 1100 lii_iff(sc); 1101 error = 0; 1102 } 1103 splx(s); 1104 1105 return error; 1106 } 1107 1108 void 1109 lii_iff(struct lii_softc *sc) 1110 { 1111 struct ifnet *ifp = &sc->sc_ac.ac_if; 1112 struct arpcom *ac = &sc->sc_ac; 1113 struct ether_multi *enm; 1114 struct ether_multistep step; 1115 uint32_t hashes[2] = { 0, 0 }; 1116 uint32_t crc, val; 1117 1118 val = LII_READ_4(sc, LII_MACC); 1119 val &= ~(MACC_PROMISC_EN | MACC_ALLMULTI_EN); 1120 ifp->if_flags &= ~IFF_ALLMULTI; 1121 1122 if (ifp->if_flags & IFF_PROMISC) { 1123 ifp ->if_flags |= IFF_ALLMULTI; 1124 val |= MACC_PROMISC_EN; 1125 } else if (ac->ac_multirangecnt > 0) { 1126 ifp ->if_flags |= IFF_ALLMULTI; 1127 val |= MACC_ALLMULTI_EN; 1128 } else { 1129 /* Clear multicast hash table. */ 1130 LII_WRITE_4(sc, LII_MHT, 0); 1131 LII_WRITE_4(sc, LII_MHT + 4, 0); 1132 1133 /* Calculate multicast hashes. */ 1134 ETHER_FIRST_MULTI(step, ac, enm); 1135 while (enm != NULL) { 1136 crc = ether_crc32_be(enm->enm_addrlo, 1137 ETHER_ADDR_LEN); 1138 hashes[((crc >> 31) & 0x1)] |= 1139 (1 << ((crc >> 26) & 0x1f)); 1140 1141 ETHER_NEXT_MULTI(step, enm); 1142 } 1143 } 1144 1145 /* Write new hashes to multicast hash table. */ 1146 LII_WRITE_4(sc, LII_MHT, hashes[0]); 1147 LII_WRITE_4(sc, LII_MHT + 4, hashes[1]); 1148 1149 LII_WRITE_4(sc, LII_MACC, val); 1150 } 1151 1152 void 1153 lii_tick(void *v) 1154 { 1155 struct lii_softc *sc = v; 1156 int s; 1157 1158 s = splnet(); 1159 mii_tick(&sc->sc_mii); 1160 splx(s); 1161 1162 timeout_add_sec(&sc->sc_tick, 1); 1163 } 1164