1 /* $OpenBSD: if_lii.c,v 1.32 2013/12/28 03:34:54 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 2007 The NetBSD Foundation. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Driver for Attansic/Atheros's L2 Fast Ethernet controller 31 */ 32 33 #include "bpfilter.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/malloc.h> 42 #include <sys/device.h> 43 #include <sys/timeout.h> 44 45 #include <machine/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 52 #if NBPFILTER > 0 53 #include <net/bpf.h> 54 #endif 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/if_ether.h> 59 #endif 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 #include <dev/pci/pcidevs.h> 67 68 #include <dev/pci/if_liireg.h> 69 70 /*#define LII_DEBUG*/ 71 #ifdef LII_DEBUG 72 #define DPRINTF(x) printf x 73 #else 74 #define DPRINTF(x) 75 #endif 76 77 struct lii_softc { 78 struct device sc_dev; 79 pci_chipset_tag_t sc_pc; 80 pcitag_t sc_tag; 81 82 bus_space_tag_t sc_mmiot; 83 bus_space_handle_t sc_mmioh; 84 bus_size_t sc_mmios; 85 86 /* 87 * We allocate a big chunk of DMA-safe memory for all data exchanges. 88 * It is unfortunate that this chip doesn't seem to do scatter-gather. 89 */ 90 bus_dma_tag_t sc_dmat; 91 bus_dmamap_t sc_ringmap; 92 bus_dma_segment_t sc_ringseg; 93 94 uint8_t *sc_ring; /* the whole area */ 95 size_t sc_ringsize; 96 97 struct rx_pkt *sc_rxp; /* the part used for RX */ 98 struct tx_pkt_status *sc_txs; /* the parts used for TX */ 99 bus_addr_t sc_txsp; 100 char *sc_txdbase; 101 bus_addr_t sc_txdp; 102 103 unsigned int sc_rxcur; 104 /* the active area is [ack; cur[ */ 105 int sc_txs_cur; 106 int sc_txs_ack; 107 int sc_txd_cur; 108 int sc_txd_ack; 109 int sc_free_tx_slots; 110 111 void *sc_ih; 112 113 struct arpcom sc_ac; 114 struct mii_data sc_mii; 115 struct timeout sc_tick; 116 117 int (*sc_memread)(struct lii_softc *, uint32_t, 118 uint32_t *); 119 }; 120 121 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 122 123 int lii_match(struct device *, void *, void *); 124 void lii_attach(struct device *, struct device *, void *); 125 int lii_activate(struct device *, int); 126 127 struct cfdriver lii_cd = { 128 0, 129 "lii", 130 DV_IFNET 131 }; 132 133 struct cfattach lii_ca = { 134 sizeof(struct lii_softc), 135 lii_match, 136 lii_attach, 137 NULL, 138 lii_activate 139 }; 140 141 int lii_reset(struct lii_softc *); 142 int lii_eeprom_present(struct lii_softc *); 143 void lii_read_macaddr(struct lii_softc *, uint8_t *); 144 int lii_eeprom_read(struct lii_softc *, uint32_t, uint32_t *); 145 void lii_spi_configure(struct lii_softc *); 146 int lii_spi_read(struct lii_softc *, uint32_t, uint32_t *); 147 void lii_iff(struct lii_softc *); 148 void lii_tick(void *); 149 150 int lii_alloc_rings(struct lii_softc *); 151 int lii_free_tx_space(struct lii_softc *); 152 void lii_tx_put(struct lii_softc *, struct mbuf *); 153 154 int lii_mii_readreg(struct device *, int, int); 155 void lii_mii_writereg(struct device *, int, int, int); 156 void lii_mii_statchg(struct device *); 157 158 int lii_media_change(struct ifnet *); 159 void lii_media_status(struct ifnet *, struct ifmediareq *); 160 161 int lii_init(struct ifnet *); 162 void lii_start(struct ifnet *); 163 void lii_stop(struct ifnet *); 164 void lii_watchdog(struct ifnet *); 165 int lii_ioctl(struct ifnet *, u_long, caddr_t); 166 167 int lii_intr(void *); 168 void lii_rxintr(struct lii_softc *); 169 void lii_txintr(struct lii_softc *); 170 171 const struct pci_matchid lii_devices[] = { 172 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2 } 173 }; 174 175 #define LII_READ_4(sc,reg) \ 176 bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 177 #define LII_READ_2(sc,reg) \ 178 bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 179 #define LII_READ_1(sc,reg) \ 180 bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 181 #define LII_WRITE_4(sc,reg,val) \ 182 bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 183 #define LII_WRITE_2(sc,reg,val) \ 184 bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 185 #define LII_WRITE_1(sc,reg,val) \ 186 bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 187 188 /* 189 * Those are the default Linux parameters. 190 */ 191 192 #define AT_TXD_NUM 64 193 #define AT_TXD_BUFFER_SIZE 8192 194 #define AT_RXD_NUM 64 195 196 /* Pad the RXD buffer so that the packets are on a 128-byte boundary. */ 197 #define AT_RXD_PADDING 120 198 199 int 200 lii_match(struct device *parent, void *match, void *aux) 201 { 202 return (pci_matchbyid((struct pci_attach_args *)aux, lii_devices, 203 nitems(lii_devices))); 204 } 205 206 void 207 lii_attach(struct device *parent, struct device *self, void *aux) 208 { 209 struct lii_softc *sc = (struct lii_softc *)self; 210 struct pci_attach_args *pa = aux; 211 struct ifnet *ifp = &sc->sc_ac.ac_if; 212 pci_intr_handle_t ih; 213 pcireg_t memtype; 214 215 sc->sc_pc = pa->pa_pc; 216 sc->sc_tag = pa->pa_tag; 217 sc->sc_dmat = pa->pa_dmat; 218 219 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, PCI_MAPREG_START); 220 if (pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &sc->sc_mmiot, 221 &sc->sc_mmioh, NULL, &sc->sc_mmios, 0)) { 222 printf(": can't map mem space\n"); 223 return; 224 } 225 226 if (lii_reset(sc)) 227 goto unmap; 228 229 lii_spi_configure(sc); 230 231 if (lii_eeprom_present(sc)) 232 sc->sc_memread = lii_eeprom_read; 233 else 234 sc->sc_memread = lii_spi_read; 235 236 lii_read_macaddr(sc, sc->sc_ac.ac_enaddr); 237 238 if (pci_intr_map(pa, &ih) != 0) { 239 printf(": can't map interrupt\n"); 240 goto unmap; 241 } 242 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, 243 lii_intr, sc, DEVNAME(sc)); 244 if (sc->sc_ih == NULL) { 245 printf(": can't establish interrupt\n"); 246 goto unmap; 247 } 248 249 if (lii_alloc_rings(sc)) 250 goto deintr; 251 252 printf(": %s, address %s\n", pci_intr_string(sc->sc_pc, ih), 253 ether_sprintf(sc->sc_ac.ac_enaddr)); 254 255 timeout_set(&sc->sc_tick, lii_tick, sc); 256 257 sc->sc_mii.mii_ifp = ifp; 258 sc->sc_mii.mii_readreg = lii_mii_readreg; 259 sc->sc_mii.mii_writereg = lii_mii_writereg; 260 sc->sc_mii.mii_statchg = lii_mii_statchg; 261 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, lii_media_change, 262 lii_media_status); 263 mii_attach(self, &sc->sc_mii, 0xffffffff, 1, 264 MII_OFFSET_ANY, 0); 265 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 266 267 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 268 ifp->if_softc = sc; 269 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 270 ifp->if_capabilities = IFCAP_VLAN_MTU; 271 ifp->if_ioctl = lii_ioctl; 272 ifp->if_start = lii_start; 273 ifp->if_watchdog = lii_watchdog; 274 IFQ_SET_READY(&ifp->if_snd); 275 276 if_attach(ifp); 277 ether_ifattach(ifp); 278 279 return; 280 281 deintr: 282 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 283 unmap: 284 bus_space_unmap(sc->sc_mmiot, sc->sc_mmioh, sc->sc_mmios); 285 return; 286 } 287 288 int 289 lii_activate(struct device *self, int act) 290 { 291 struct lii_softc *sc = (struct lii_softc *)self; 292 struct ifnet *ifp = &sc->sc_ac.ac_if; 293 int rv = 0; 294 295 switch (act) { 296 case DVACT_SUSPEND: 297 if (ifp->if_flags & IFF_RUNNING) 298 lii_stop(ifp); 299 rv = config_activate_children(self, act); 300 break; 301 case DVACT_RESUME: 302 if (ifp->if_flags & IFF_UP) 303 lii_init(ifp); 304 break; 305 default: 306 rv = config_activate_children(self, act); 307 break; 308 } 309 return (rv); 310 } 311 312 int 313 lii_reset(struct lii_softc *sc) 314 { 315 int i; 316 317 DPRINTF(("lii_reset\n")); 318 319 LII_WRITE_4(sc, LII_SMC, SMC_SOFT_RST); 320 DELAY(1000); 321 322 for (i = 0; i < 10; ++i) { 323 if (LII_READ_4(sc, LII_BIS) == 0) 324 break; 325 DELAY(1000); 326 } 327 328 if (i == 10) { 329 printf("%s: reset failed\n", DEVNAME(sc)); 330 return 1; 331 } 332 333 LII_WRITE_4(sc, LII_PHYC, PHYC_ENABLE); 334 DELAY(10); 335 336 /* Init PCI-Express module */ 337 /* Magic Numbers Warning */ 338 LII_WRITE_4(sc, 0x12fc, 0x00006500); 339 LII_WRITE_4(sc, 0x1008, 0x00008000 | 340 LII_READ_4(sc, 0x1008)); 341 342 return 0; 343 } 344 345 int 346 lii_eeprom_present(struct lii_softc *sc) 347 { 348 uint32_t val; 349 350 val = LII_READ_4(sc, LII_SFC); 351 if (val & SFC_EN_VPD) 352 LII_WRITE_4(sc, LII_SFC, val & ~(SFC_EN_VPD)); 353 354 return pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_VPD, 355 NULL, NULL) == 1; 356 } 357 358 int 359 lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 360 { 361 return pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val); 362 } 363 364 void 365 lii_spi_configure(struct lii_softc *sc) 366 { 367 /* 368 * We don't offer a way to configure the SPI Flash vendor parameter, so 369 * the table is given for reference 370 */ 371 static const struct lii_spi_flash_vendor { 372 const char *sfv_name; 373 const uint8_t sfv_opcodes[9]; 374 } lii_sfv[] = { 375 { "Atmel", { 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 } }, 376 { "SST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 } }, 377 { "ST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xab, 0xd8, 0xc7 } }, 378 }; 379 #define SF_OPCODE_WRSR 0 380 #define SF_OPCODE_READ 1 381 #define SF_OPCODE_PRGM 2 382 #define SF_OPCODE_WREN 3 383 #define SF_OPCODE_WRDI 4 384 #define SF_OPCODE_RDSR 5 385 #define SF_OPCODE_RDID 6 386 #define SF_OPCODE_SECT_ER 7 387 #define SF_OPCODE_CHIP_ER 8 388 389 #define SF_DEFAULT_VENDOR 0 390 static const uint8_t vendor = SF_DEFAULT_VENDOR; 391 392 /* 393 * Why isn't WRDI used? Heck if I know. 394 */ 395 396 LII_WRITE_1(sc, LII_SFOP_WRSR, 397 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WRSR]); 398 LII_WRITE_1(sc, LII_SFOP_READ, 399 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_READ]); 400 LII_WRITE_1(sc, LII_SFOP_PROGRAM, 401 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_PRGM]); 402 LII_WRITE_1(sc, LII_SFOP_WREN, 403 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WREN]); 404 LII_WRITE_1(sc, LII_SFOP_RDSR, 405 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDSR]); 406 LII_WRITE_1(sc, LII_SFOP_RDID, 407 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDID]); 408 LII_WRITE_1(sc, LII_SFOP_SC_ERASE, 409 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_SECT_ER]); 410 LII_WRITE_1(sc, LII_SFOP_CHIP_ERASE, 411 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_CHIP_ER]); 412 } 413 414 #define MAKE_SFC(cssetup, clkhi, clklo, cshold, cshi, ins) \ 415 ( (((cssetup) & SFC_CS_SETUP_MASK) \ 416 << SFC_CS_SETUP_SHIFT) \ 417 | (((clkhi) & SFC_CLK_HI_MASK) \ 418 << SFC_CLK_HI_SHIFT) \ 419 | (((clklo) & SFC_CLK_LO_MASK) \ 420 << SFC_CLK_LO_SHIFT) \ 421 | (((cshold) & SFC_CS_HOLD_MASK) \ 422 << SFC_CS_HOLD_SHIFT) \ 423 | (((cshi) & SFC_CS_HI_MASK) \ 424 << SFC_CS_HI_SHIFT) \ 425 | (((ins) & SFC_INS_MASK) \ 426 << SFC_INS_SHIFT)) 427 428 #define CUSTOM_SPI_CS_SETUP 2 429 #define CUSTOM_SPI_CLK_HI 2 430 #define CUSTOM_SPI_CLK_LO 2 431 #define CUSTOM_SPI_CS_HOLD 2 432 #define CUSTOM_SPI_CS_HI 3 433 434 int 435 lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 436 { 437 uint32_t v; 438 int i; 439 440 LII_WRITE_4(sc, LII_SF_DATA, 0); 441 LII_WRITE_4(sc, LII_SF_ADDR, reg); 442 443 v = SFC_WAIT_READY | 444 MAKE_SFC(CUSTOM_SPI_CS_SETUP, CUSTOM_SPI_CLK_HI, 445 CUSTOM_SPI_CLK_LO, CUSTOM_SPI_CS_HOLD, CUSTOM_SPI_CS_HI, 1); 446 447 LII_WRITE_4(sc, LII_SFC, v); 448 v |= SFC_START; 449 LII_WRITE_4(sc, LII_SFC, v); 450 451 for (i = 0; i < 10; ++i) { 452 DELAY(1000); 453 if (!(LII_READ_4(sc, LII_SFC) & SFC_START)) 454 break; 455 } 456 if (i == 10) 457 return EBUSY; 458 459 *val = LII_READ_4(sc, LII_SF_DATA); 460 return 0; 461 } 462 463 void 464 lii_read_macaddr(struct lii_softc *sc, uint8_t *ea) 465 { 466 uint32_t offset = 0x100; 467 uint32_t val, val1, addr0 = 0, addr1 = 0; 468 uint8_t found = 0; 469 470 while ((*sc->sc_memread)(sc, offset, &val) == 0) { 471 offset += 4; 472 473 /* Each chunk of data starts with a signature */ 474 if ((val & 0xff) != 0x5a) 475 break; 476 if ((*sc->sc_memread)(sc, offset, &val1)) 477 break; 478 479 offset += 4; 480 481 val >>= 16; 482 switch (val) { 483 case LII_MAC_ADDR_0: 484 addr0 = val1; 485 ++found; 486 break; 487 case LII_MAC_ADDR_1: 488 addr1 = val1; 489 ++found; 490 break; 491 default: 492 continue; 493 } 494 } 495 496 #ifdef LII_DEBUG 497 if (found < 2) 498 printf(": error reading MAC address, using registers...\n"); 499 #endif 500 501 addr0 = htole32(addr0); 502 addr1 = htole32(addr1); 503 504 if ((addr0 == 0xffffff && (addr1 & 0xffff) == 0xffff) || 505 (addr0 == 0 && (addr1 & 0xffff) == 0)) { 506 addr0 = htole32(LII_READ_4(sc, LII_MAC_ADDR_0)); 507 addr1 = htole32(LII_READ_4(sc, LII_MAC_ADDR_1)); 508 } 509 510 ea[0] = (addr1 & 0x0000ff00) >> 8; 511 ea[1] = (addr1 & 0x000000ff); 512 ea[2] = (addr0 & 0xff000000) >> 24; 513 ea[3] = (addr0 & 0x00ff0000) >> 16; 514 ea[4] = (addr0 & 0x0000ff00) >> 8; 515 ea[5] = (addr0 & 0x000000ff); 516 } 517 518 int 519 lii_mii_readreg(struct device *dev, int phy, int reg) 520 { 521 struct lii_softc *sc = (struct lii_softc *)dev; 522 uint32_t val; 523 int i; 524 525 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 526 527 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 528 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 529 530 val |= MDIOC_READ; 531 532 LII_WRITE_4(sc, LII_MDIOC, val); 533 534 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 535 DELAY(2); 536 val = LII_READ_4(sc, LII_MDIOC); 537 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 538 break; 539 } 540 541 if (i == MDIO_WAIT_TIMES) { 542 printf("%s: timeout reading PHY %d reg %d\n", DEVNAME(sc), phy, 543 reg); 544 } 545 546 return (val & 0x0000ffff); 547 } 548 549 void 550 lii_mii_writereg(struct device *dev, int phy, int reg, int data) 551 { 552 struct lii_softc *sc = (struct lii_softc *)dev; 553 uint32_t val; 554 int i; 555 556 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 557 val |= (data & MDIOC_DATA_MASK) << MDIOC_DATA_SHIFT; 558 559 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 560 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 561 562 /* val |= MDIOC_WRITE; */ 563 564 LII_WRITE_4(sc, LII_MDIOC, val); 565 566 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 567 DELAY(2); 568 val = LII_READ_4(sc, LII_MDIOC); 569 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 570 break; 571 } 572 573 if (i == MDIO_WAIT_TIMES) { 574 printf("%s: timeout writing PHY %d reg %d\n", DEVNAME(sc), phy, 575 reg); 576 } 577 } 578 579 void 580 lii_mii_statchg(struct device *dev) 581 { 582 struct lii_softc *sc = (struct lii_softc *)dev; 583 uint32_t val; 584 585 DPRINTF(("lii_mii_statchg\n")); 586 587 val = LII_READ_4(sc, LII_MACC); 588 589 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) 590 val |= MACC_FDX; 591 else 592 val &= ~MACC_FDX; 593 594 LII_WRITE_4(sc, LII_MACC, val); 595 } 596 597 int 598 lii_media_change(struct ifnet *ifp) 599 { 600 struct lii_softc *sc = ifp->if_softc; 601 602 DPRINTF(("lii_media_change\n")); 603 604 if (ifp->if_flags & IFF_UP) 605 mii_mediachg(&sc->sc_mii); 606 return 0; 607 } 608 609 void 610 lii_media_status(struct ifnet *ifp, struct ifmediareq *imr) 611 { 612 struct lii_softc *sc = ifp->if_softc; 613 614 DPRINTF(("lii_media_status\n")); 615 616 mii_pollstat(&sc->sc_mii); 617 imr->ifm_status = sc->sc_mii.mii_media_status; 618 imr->ifm_active = sc->sc_mii.mii_media_active; 619 } 620 621 int 622 lii_init(struct ifnet *ifp) 623 { 624 struct lii_softc *sc = ifp->if_softc; 625 uint32_t val; 626 int error; 627 628 DPRINTF(("lii_init\n")); 629 630 lii_stop(ifp); 631 632 memset(sc->sc_ring, 0, sc->sc_ringsize); 633 634 /* Disable all interrupts */ 635 LII_WRITE_4(sc, LII_ISR, 0xffffffff); 636 637 LII_WRITE_4(sc, LII_DESC_BASE_ADDR_HI, 0); 638 /* XXX 639 sc->sc_ringmap->dm_segs[0].ds_addr >> 32); 640 */ 641 LII_WRITE_4(sc, LII_RXD_BASE_ADDR_LO, 642 (sc->sc_ringmap->dm_segs[0].ds_addr & 0xffffffff) 643 + AT_RXD_PADDING); 644 LII_WRITE_4(sc, LII_TXS_BASE_ADDR_LO, 645 sc->sc_txsp & 0xffffffff); 646 LII_WRITE_4(sc, LII_TXD_BASE_ADDR_LO, 647 sc->sc_txdp & 0xffffffff); 648 649 LII_WRITE_2(sc, LII_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4); 650 LII_WRITE_2(sc, LII_TXS_NUM_ENTRIES, AT_TXD_NUM); 651 LII_WRITE_2(sc, LII_RXD_NUM_ENTRIES, AT_RXD_NUM); 652 653 /* 654 * Inter Paket Gap Time = 0x60 (IPGT) 655 * Minimum inter-frame gap for RX = 0x50 (MIFG) 656 * 64-bit Carrier-Sense window = 0x40 (IPGR1) 657 * 96-bit IPG window = 0x60 (IPGR2) 658 */ 659 LII_WRITE_4(sc, LII_MIPFG, 0x60405060); 660 661 /* 662 * Collision window = 0x37 (LCOL) 663 * Maximum # of retrans = 0xf (RETRY) 664 * Maximum binary expansion # = 0xa (ABEBT) 665 * IPG to start jam = 0x7 (JAMIPG) 666 */ 667 LII_WRITE_4(sc, LII_MHDC, 0x07a0f037 | 668 MHDC_EXC_DEF_EN); 669 670 /* 100 means 200us */ 671 LII_WRITE_2(sc, LII_IMTIV, 100); 672 LII_WRITE_2(sc, LII_SMC, SMC_ITIMER_EN); 673 674 /* 500000 means 100ms */ 675 LII_WRITE_2(sc, LII_IALTIV, 50000); 676 677 LII_WRITE_4(sc, LII_MTU, ifp->if_mtu + ETHER_HDR_LEN 678 + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 679 680 /* unit unknown for TX cur-through threshold */ 681 LII_WRITE_4(sc, LII_TX_CUT_THRESH, 0x177); 682 683 LII_WRITE_2(sc, LII_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8); 684 LII_WRITE_2(sc, LII_PAUSE_OFF_TH, AT_RXD_NUM / 12); 685 686 sc->sc_rxcur = 0; 687 sc->sc_txs_cur = sc->sc_txs_ack = 0; 688 sc->sc_txd_cur = sc->sc_txd_ack = 0; 689 sc->sc_free_tx_slots = 1; 690 LII_WRITE_2(sc, LII_MB_TXD_WR_IDX, sc->sc_txd_cur); 691 LII_WRITE_2(sc, LII_MB_RXD_RD_IDX, sc->sc_rxcur); 692 693 LII_WRITE_1(sc, LII_DMAR, DMAR_EN); 694 LII_WRITE_1(sc, LII_DMAW, DMAW_EN); 695 696 LII_WRITE_4(sc, LII_SMC, LII_READ_4(sc, LII_SMC) | SMC_MANUAL_INT); 697 698 error = ((LII_READ_4(sc, LII_ISR) & ISR_PHY_LINKDOWN) != 0); 699 LII_WRITE_4(sc, LII_ISR, 0x3fffffff); 700 LII_WRITE_4(sc, LII_ISR, 0); 701 if (error) { 702 printf("%s: init failed\n", DEVNAME(sc)); 703 goto out; 704 } 705 706 /* 707 * Initialise MAC. 708 */ 709 val = LII_READ_4(sc, LII_MACC) & MACC_FDX; 710 711 val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY | 712 MACC_TX_FLOW_EN | MACC_RX_FLOW_EN | MACC_ADD_CRC | 713 MACC_PAD; 714 715 val |= 7 << MACC_PREAMBLE_LEN_SHIFT; 716 val |= 2 << MACC_HDX_LEFT_BUF_SHIFT; 717 718 LII_WRITE_4(sc, LII_MACC, val); 719 720 /* Set the hardware MAC address. */ 721 LII_WRITE_4(sc, LII_MAC_ADDR_0, letoh32((sc->sc_ac.ac_enaddr[2] << 24) | 722 (sc->sc_ac.ac_enaddr[3] << 16) | (sc->sc_ac.ac_enaddr[4] << 8) | 723 sc->sc_ac.ac_enaddr[5])); 724 LII_WRITE_4(sc, LII_MAC_ADDR_1, 725 letoh32((sc->sc_ac.ac_enaddr[0] << 8) | sc->sc_ac.ac_enaddr[1])); 726 727 /* Program promiscuous mode and multicast filters. */ 728 lii_iff(sc); 729 730 mii_mediachg(&sc->sc_mii); 731 732 LII_WRITE_4(sc, LII_IMR, IMR_NORMAL_MASK); 733 734 timeout_add_sec(&sc->sc_tick, 1); 735 736 ifp->if_flags |= IFF_RUNNING; 737 ifp->if_flags &= ~IFF_OACTIVE; 738 739 out: 740 return error; 741 } 742 743 void 744 lii_tx_put(struct lii_softc *sc, struct mbuf *m) 745 { 746 int left; 747 struct tx_pkt_header *tph = 748 (struct tx_pkt_header *)(sc->sc_txdbase + sc->sc_txd_cur); 749 750 memset(tph, 0, sizeof *tph); 751 tph->txph_size = m->m_pkthdr.len; 752 753 sc->sc_txd_cur = (sc->sc_txd_cur + 4) % AT_TXD_BUFFER_SIZE; 754 755 /* 756 * We already know we have enough space, so if there is a part of the 757 * space ahead of txd_cur that is active, it doesn't matter because 758 * left will be large enough even without it. 759 */ 760 left = AT_TXD_BUFFER_SIZE - sc->sc_txd_cur; 761 762 if (left > m->m_pkthdr.len) { 763 m_copydata(m, 0, m->m_pkthdr.len, 764 sc->sc_txdbase + sc->sc_txd_cur); 765 sc->sc_txd_cur += m->m_pkthdr.len; 766 } else { 767 m_copydata(m, 0, left, sc->sc_txdbase + sc->sc_txd_cur); 768 m_copydata(m, left, m->m_pkthdr.len - left, sc->sc_txdbase); 769 sc->sc_txd_cur = m->m_pkthdr.len - left; 770 } 771 772 /* Round to a 32-bit boundary */ 773 sc->sc_txd_cur = ((sc->sc_txd_cur + 3) & ~3) % AT_TXD_BUFFER_SIZE; 774 if (sc->sc_txd_cur == sc->sc_txd_ack) 775 sc->sc_free_tx_slots = 0; 776 } 777 778 int 779 lii_free_tx_space(struct lii_softc *sc) 780 { 781 int space; 782 783 if (sc->sc_txd_cur >= sc->sc_txd_ack) 784 space = (AT_TXD_BUFFER_SIZE - sc->sc_txd_cur) + 785 sc->sc_txd_ack; 786 else 787 space = sc->sc_txd_ack - sc->sc_txd_cur; 788 789 /* Account for the tx_pkt_header */ 790 return (space - 4); 791 } 792 793 void 794 lii_start(struct ifnet *ifp) 795 { 796 struct lii_softc *sc = ifp->if_softc; 797 struct mbuf *m0; 798 799 DPRINTF(("lii_start\n")); 800 801 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 802 return; 803 804 for (;;) { 805 IFQ_POLL(&ifp->if_snd, m0); 806 if (m0 == NULL) 807 break; 808 809 if (!sc->sc_free_tx_slots || 810 lii_free_tx_space(sc) < m0->m_pkthdr.len) { 811 ifp->if_flags |= IFF_OACTIVE; 812 break; 813 } 814 815 lii_tx_put(sc, m0); 816 817 DPRINTF(("lii_start: put %d\n", sc->sc_txs_cur)); 818 819 sc->sc_txs[sc->sc_txs_cur].txps_update = 0; 820 sc->sc_txs_cur = (sc->sc_txs_cur + 1) % AT_TXD_NUM; 821 if (sc->sc_txs_cur == sc->sc_txs_ack) 822 sc->sc_free_tx_slots = 0; 823 824 LII_WRITE_2(sc, LII_MB_TXD_WR_IDX, sc->sc_txd_cur/4); 825 826 IFQ_DEQUEUE(&ifp->if_snd, m0); 827 828 #if NBPFILTER > 0 829 if (ifp->if_bpf != NULL) 830 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 831 #endif 832 m_freem(m0); 833 } 834 } 835 836 void 837 lii_stop(struct ifnet *ifp) 838 { 839 struct lii_softc *sc = ifp->if_softc; 840 841 timeout_del(&sc->sc_tick); 842 843 ifp->if_timer = 0; 844 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 845 846 mii_down(&sc->sc_mii); 847 848 lii_reset(sc); 849 850 LII_WRITE_4(sc, LII_IMR, 0); 851 } 852 853 int 854 lii_intr(void *v) 855 { 856 struct lii_softc *sc = v; 857 uint32_t status; 858 859 status = LII_READ_4(sc, LII_ISR); 860 if (status == 0) 861 return 0; 862 863 DPRINTF(("lii_intr (%x)\n", status)); 864 865 /* Clear the interrupt and disable them */ 866 LII_WRITE_4(sc, LII_ISR, status | ISR_DIS_INT); 867 868 if (status & (ISR_PHY | ISR_MANUAL)) { 869 /* Ack PHY interrupt. Magic register */ 870 if (status & ISR_PHY) 871 (void)lii_mii_readreg(&sc->sc_dev, 1, 19); 872 mii_mediachg(&sc->sc_mii); 873 } 874 875 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | ISR_PHY_LINKDOWN)) { 876 lii_init(&sc->sc_ac.ac_if); 877 return 1; 878 } 879 880 if (status & ISR_RX_EVENT) { 881 #ifdef LII_DEBUG 882 if (!(status & ISR_RS_UPDATE)) 883 printf("rxintr %08x\n", status); 884 #endif 885 lii_rxintr(sc); 886 } 887 888 if (status & ISR_TX_EVENT) 889 lii_txintr(sc); 890 891 /* Re-enable interrupts */ 892 LII_WRITE_4(sc, LII_ISR, 0); 893 894 return 1; 895 } 896 897 void 898 lii_rxintr(struct lii_softc *sc) 899 { 900 struct ifnet *ifp = &sc->sc_ac.ac_if; 901 struct rx_pkt *rxp; 902 struct mbuf *m; 903 uint16_t size; 904 905 DPRINTF(("lii_rxintr\n")); 906 907 for (;;) { 908 rxp = &sc->sc_rxp[sc->sc_rxcur]; 909 if (rxp->rxp_update == 0) 910 break; 911 912 DPRINTF(("lii_rxintr: getting %u (%u) [%x]\n", sc->sc_rxcur, 913 rxp->rxp_size, rxp->rxp_flags)); 914 sc->sc_rxcur = (sc->sc_rxcur + 1) % AT_RXD_NUM; 915 rxp->rxp_update = 0; 916 if (!(rxp->rxp_flags & LII_RXF_SUCCESS)) { 917 ++ifp->if_ierrors; 918 continue; 919 } 920 921 MGETHDR(m, M_DONTWAIT, MT_DATA); 922 if (m == NULL) { 923 ++ifp->if_ierrors; 924 continue; 925 } 926 size = rxp->rxp_size - ETHER_CRC_LEN; 927 if (size > MHLEN) { 928 MCLGET(m, M_DONTWAIT); 929 if ((m->m_flags & M_EXT) == 0) { 930 m_freem(m); 931 ++ifp->if_ierrors; 932 continue; 933 } 934 } 935 936 m->m_pkthdr.rcvif = ifp; 937 /* Copy the packet withhout the FCS */ 938 m->m_pkthdr.len = m->m_len = size; 939 memcpy(mtod(m, void *), &rxp->rxp_data[0], size); 940 ++ifp->if_ipackets; 941 942 #if NBPFILTER > 0 943 if (ifp->if_bpf) 944 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 945 #endif 946 947 ether_input_mbuf(ifp, m); 948 } 949 950 LII_WRITE_4(sc, LII_MB_RXD_RD_IDX, sc->sc_rxcur); 951 } 952 953 void 954 lii_txintr(struct lii_softc *sc) 955 { 956 struct ifnet *ifp = &sc->sc_ac.ac_if; 957 struct tx_pkt_status *txs; 958 struct tx_pkt_header *txph; 959 960 DPRINTF(("lii_txintr\n")); 961 962 for (;;) { 963 txs = &sc->sc_txs[sc->sc_txs_ack]; 964 if (txs->txps_update == 0) 965 break; 966 DPRINTF(("lii_txintr: ack'd %d\n", sc->sc_txs_ack)); 967 sc->sc_txs_ack = (sc->sc_txs_ack + 1) % AT_TXD_NUM; 968 sc->sc_free_tx_slots = 1; 969 970 txs->txps_update = 0; 971 972 txph = (struct tx_pkt_header *) 973 (sc->sc_txdbase + sc->sc_txd_ack); 974 975 if (txph->txph_size != txs->txps_size) { 976 printf("%s: mismatched status and packet\n", 977 DEVNAME(sc)); 978 } 979 980 /* 981 * Move ack by the packet size, taking the packet header in 982 * account and round to the next 32-bit boundary 983 * (7 = sizeof(header) + 3) 984 */ 985 sc->sc_txd_ack = (sc->sc_txd_ack + txph->txph_size + 7 ) & ~3; 986 sc->sc_txd_ack %= AT_TXD_BUFFER_SIZE; 987 988 if (txs->txps_flags & LII_TXF_SUCCESS) 989 ++ifp->if_opackets; 990 else 991 ++ifp->if_oerrors; 992 ifp->if_flags &= ~IFF_OACTIVE; 993 } 994 995 if (sc->sc_free_tx_slots) 996 lii_start(ifp); 997 } 998 999 int 1000 lii_alloc_rings(struct lii_softc *sc) 1001 { 1002 int nsegs; 1003 bus_size_t bs; 1004 1005 /* 1006 * We need a big chunk of DMA-friendly memory because descriptors 1007 * are not separate from data on that crappy hardware, which means 1008 * we'll have to copy data from and to that memory zone to and from 1009 * the mbufs. 1010 * 1011 * How lame is that? Using the default values from the Linux driver, 1012 * we allocate space for receiving up to 64 full-size Ethernet frames, 1013 * and only 8kb for transmitting up to 64 Ethernet frames. 1014 */ 1015 1016 sc->sc_ringsize = bs = AT_RXD_PADDING 1017 + AT_RXD_NUM * sizeof(struct rx_pkt) 1018 + AT_TXD_NUM * sizeof(struct tx_pkt_status) 1019 + AT_TXD_BUFFER_SIZE; 1020 1021 if (bus_dmamap_create(sc->sc_dmat, bs, 1, bs, (1<<30), 1022 BUS_DMA_NOWAIT, &sc->sc_ringmap) != 0) { 1023 printf(": failed to create DMA map\n"); 1024 return 1; 1025 } 1026 1027 if (bus_dmamem_alloc(sc->sc_dmat, bs, PAGE_SIZE, (1<<30), 1028 &sc->sc_ringseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) { 1029 printf(": failed to allocate DMA memory\n"); 1030 goto destroy; 1031 } 1032 1033 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_ringseg, nsegs, bs, 1034 (caddr_t *)&sc->sc_ring, BUS_DMA_NOWAIT) != 0) { 1035 printf(": failed to map DMA memory\n"); 1036 goto free; 1037 } 1038 1039 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ringmap, sc->sc_ring, 1040 bs, NULL, BUS_DMA_NOWAIT) != 0) { 1041 printf(": failed to load DMA memory\n"); 1042 goto unmap; 1043 } 1044 1045 sc->sc_rxp = (void *)(sc->sc_ring + AT_RXD_PADDING); 1046 sc->sc_txs = (void *)(sc->sc_ring + AT_RXD_PADDING 1047 + AT_RXD_NUM * sizeof(struct rx_pkt)); 1048 sc->sc_txdbase = ((char *)sc->sc_txs) 1049 + AT_TXD_NUM * sizeof(struct tx_pkt_status); 1050 sc->sc_txsp = sc->sc_ringmap->dm_segs[0].ds_addr 1051 + ((char *)sc->sc_txs - (char *)sc->sc_ring); 1052 sc->sc_txdp = sc->sc_ringmap->dm_segs[0].ds_addr 1053 + ((char *)sc->sc_txdbase - (char *)sc->sc_ring); 1054 1055 return 0; 1056 1057 unmap: 1058 bus_dmamem_unmap(sc->sc_dmat, sc->sc_ring, bs); 1059 free: 1060 bus_dmamem_free(sc->sc_dmat, &sc->sc_ringseg, nsegs); 1061 destroy: 1062 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ringmap); 1063 return 1; 1064 } 1065 1066 void 1067 lii_watchdog(struct ifnet *ifp) 1068 { 1069 struct lii_softc *sc = ifp->if_softc; 1070 1071 printf("%s: watchdog timeout\n", DEVNAME(sc)); 1072 ++ifp->if_oerrors; 1073 lii_init(ifp); 1074 } 1075 1076 int 1077 lii_ioctl(struct ifnet *ifp, u_long cmd, caddr_t addr) 1078 { 1079 struct lii_softc *sc = ifp->if_softc; 1080 struct ifaddr *ifa = (struct ifaddr *)addr; 1081 struct ifreq *ifr = (struct ifreq *)addr; 1082 int s, error = 0; 1083 1084 s = splnet(); 1085 1086 switch(cmd) { 1087 case SIOCSIFADDR: 1088 SET(ifp->if_flags, IFF_UP); 1089 #ifdef INET 1090 if (ifa->ifa_addr->sa_family == AF_INET) 1091 arp_ifinit(&sc->sc_ac, ifa); 1092 #endif 1093 /* FALLTHROUGH */ 1094 1095 case SIOCSIFFLAGS: 1096 if (ISSET(ifp->if_flags, IFF_UP)) { 1097 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1098 error = ENETRESET; 1099 else 1100 lii_init(ifp); 1101 } else { 1102 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1103 lii_stop(ifp); 1104 } 1105 break; 1106 1107 case SIOCSIFMEDIA: 1108 case SIOCGIFMEDIA: 1109 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1110 break; 1111 1112 default: 1113 error = ether_ioctl(ifp, &sc->sc_ac, cmd, addr); 1114 } 1115 1116 if (error == ENETRESET) { 1117 if (ifp->if_flags & IFF_RUNNING) 1118 lii_iff(sc); 1119 error = 0; 1120 } 1121 1122 splx(s); 1123 return error; 1124 } 1125 1126 void 1127 lii_iff(struct lii_softc *sc) 1128 { 1129 struct ifnet *ifp = &sc->sc_ac.ac_if; 1130 struct arpcom *ac = &sc->sc_ac; 1131 struct ether_multi *enm; 1132 struct ether_multistep step; 1133 uint32_t hashes[2]; 1134 uint32_t crc, val; 1135 1136 val = LII_READ_4(sc, LII_MACC); 1137 val &= ~(MACC_ALLMULTI_EN | MACC_BCAST_EN | MACC_PROMISC_EN); 1138 ifp->if_flags &= ~IFF_ALLMULTI; 1139 1140 /* 1141 * Always accept broadcast frames. 1142 */ 1143 val |= MACC_BCAST_EN; 1144 1145 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 1146 ifp->if_flags |= IFF_ALLMULTI; 1147 if (ifp->if_flags & IFF_PROMISC) 1148 val |= MACC_PROMISC_EN; 1149 else 1150 val |= MACC_ALLMULTI_EN; 1151 hashes[0] = hashes[1] = 0xFFFFFFFF; 1152 } else { 1153 /* Program new filter. */ 1154 bzero(hashes, sizeof(hashes)); 1155 1156 ETHER_FIRST_MULTI(step, ac, enm); 1157 while (enm != NULL) { 1158 crc = ether_crc32_be(enm->enm_addrlo, 1159 ETHER_ADDR_LEN); 1160 1161 hashes[((crc >> 31) & 0x1)] |= 1162 (1 << ((crc >> 26) & 0x1f)); 1163 1164 ETHER_NEXT_MULTI(step, enm); 1165 } 1166 } 1167 1168 LII_WRITE_4(sc, LII_MHT, hashes[0]); 1169 LII_WRITE_4(sc, LII_MHT + 4, hashes[1]); 1170 LII_WRITE_4(sc, LII_MACC, val); 1171 } 1172 1173 void 1174 lii_tick(void *v) 1175 { 1176 struct lii_softc *sc = v; 1177 int s; 1178 1179 s = splnet(); 1180 mii_tick(&sc->sc_mii); 1181 splx(s); 1182 1183 timeout_add_sec(&sc->sc_tick, 1); 1184 } 1185