1 /* $OpenBSD: if_lge.c,v 1.55 2011/06/22 16:44:27 tedu Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 5 * Bill Paul <william.paul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.6 2001/06/20 19:47:55 bmilekic Exp $ 35 */ 36 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * Written by Bill Paul <william.paul@windriver.com> 42 * Wind River Systems 43 */ 44 45 /* 46 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 47 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 48 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 49 * are three supported methods for data transfer between host and 50 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 51 * Propulsion Technology (tm) DMA. The latter mechanism is a form 52 * of double buffer DMA where the packet data is copied to a 53 * pre-allocated DMA buffer who's physical address has been loaded 54 * into a table at device initialization time. The rationale is that 55 * the virtual to physical address translation needed for normal 56 * scatter/gather DMA is more expensive than the data copy needed 57 * for double buffering. This may be true in Windows NT and the like, 58 * but it isn't true for us, at least on the x86 arch. This driver 59 * uses the scatter/gather I/O method for both TX and RX. 60 * 61 * The LXT1001 only supports TCP/IP checksum offload on receive. 62 * Also, the VLAN tagging is done using a 16-entry table which allows 63 * the chip to perform hardware filtering based on VLAN tags. Sadly, 64 * our vlan support doesn't currently play well with this kind of 65 * hardware support. 66 * 67 * Special thanks to: 68 * - Jeff James at Intel, for arranging to have the LXT1001 manual 69 * released (at long last) 70 * - Beny Chen at D-Link, for actually sending it to me 71 * - Brad Short and Keith Alexis at SMC, for sending me sample 72 * SMC9462SX and SMC9462TX adapters for testing 73 * - Paul Saab at Y!, for not killing me (though it remains to be seen 74 * if in fact he did me much of a favor) 75 */ 76 77 #include "bpfilter.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/sockio.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/device.h> 86 #include <sys/socket.h> 87 88 #include <net/if.h> 89 #include <net/if_dl.h> 90 #include <net/if_media.h> 91 92 #ifdef INET 93 #include <netinet/in.h> 94 #include <netinet/in_systm.h> 95 #include <netinet/in_var.h> 96 #include <netinet/ip.h> 97 #include <netinet/if_ether.h> 98 #endif 99 100 #if NBPFILTER > 0 101 #include <net/bpf.h> 102 #endif 103 104 #include <uvm/uvm_extern.h> /* for vtophys */ 105 #define VTOPHYS(v) vtophys((vaddr_t)(v)) 106 107 #include <dev/pci/pcireg.h> 108 #include <dev/pci/pcivar.h> 109 #include <dev/pci/pcidevs.h> 110 111 #include <dev/mii/mii.h> 112 #include <dev/mii/miivar.h> 113 114 #define LGE_USEIOSPACE 115 116 #include <dev/pci/if_lgereg.h> 117 118 int lge_probe(struct device *, void *, void *); 119 void lge_attach(struct device *, struct device *, void *); 120 121 struct cfattach lge_ca = { 122 sizeof(struct lge_softc), lge_probe, lge_attach 123 }; 124 125 struct cfdriver lge_cd = { 126 NULL, "lge", DV_IFNET 127 }; 128 129 int lge_alloc_jumbo_mem(struct lge_softc *); 130 void *lge_jalloc(struct lge_softc *); 131 void lge_jfree(caddr_t, u_int, void *); 132 133 int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, 134 struct mbuf *); 135 int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 136 void lge_rxeof(struct lge_softc *, int); 137 void lge_txeof(struct lge_softc *); 138 int lge_intr(void *); 139 void lge_tick(void *); 140 void lge_start(struct ifnet *); 141 int lge_ioctl(struct ifnet *, u_long, caddr_t); 142 void lge_init(void *); 143 void lge_stop(struct lge_softc *); 144 void lge_watchdog(struct ifnet *); 145 int lge_ifmedia_upd(struct ifnet *); 146 void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 147 148 void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 149 void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 150 151 int lge_miibus_readreg(struct device *, int, int); 152 void lge_miibus_writereg(struct device *, int, int, int); 153 void lge_miibus_statchg(struct device *); 154 155 void lge_setmulti(struct lge_softc *); 156 void lge_reset(struct lge_softc *); 157 int lge_list_rx_init(struct lge_softc *); 158 int lge_list_tx_init(struct lge_softc *); 159 160 #ifdef LGE_DEBUG 161 #define DPRINTF(x) if (lgedebug) printf x 162 #define DPRINTFN(n,x) if (lgedebug >= (n)) printf x 163 int lgedebug = 0; 164 #else 165 #define DPRINTF(x) 166 #define DPRINTFN(n,x) 167 #endif 168 169 const struct pci_matchid lge_devices[] = { 170 { PCI_VENDOR_LEVEL1, PCI_PRODUCT_LEVEL1_LXT1001 } 171 }; 172 173 #define LGE_SETBIT(sc, reg, x) \ 174 CSR_WRITE_4(sc, reg, \ 175 CSR_READ_4(sc, reg) | (x)) 176 177 #define LGE_CLRBIT(sc, reg, x) \ 178 CSR_WRITE_4(sc, reg, \ 179 CSR_READ_4(sc, reg) & ~(x)) 180 181 #define SIO_SET(x) \ 182 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 183 184 #define SIO_CLR(x) \ 185 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 186 187 /* 188 * Read a word of data stored in the EEPROM at address 'addr.' 189 */ 190 void 191 lge_eeprom_getword(struct lge_softc *sc, int addr, u_int16_t *dest) 192 { 193 int i; 194 u_int32_t val; 195 196 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 197 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 198 199 for (i = 0; i < LGE_TIMEOUT; i++) 200 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 201 break; 202 203 if (i == LGE_TIMEOUT) { 204 printf("%s: EEPROM read timed out\n", sc->sc_dv.dv_xname); 205 return; 206 } 207 208 val = CSR_READ_4(sc, LGE_EEDATA); 209 210 if (addr & 1) 211 *dest = (val >> 16) & 0xFFFF; 212 else 213 *dest = val & 0xFFFF; 214 } 215 216 /* 217 * Read a sequence of words from the EEPROM. 218 */ 219 void 220 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, 221 int cnt, int swap) 222 { 223 int i; 224 u_int16_t word = 0, *ptr; 225 226 for (i = 0; i < cnt; i++) { 227 lge_eeprom_getword(sc, off + i, &word); 228 ptr = (u_int16_t *)(dest + (i * 2)); 229 if (swap) 230 *ptr = ntohs(word); 231 else 232 *ptr = word; 233 } 234 } 235 236 int 237 lge_miibus_readreg(struct device *dev, int phy, int reg) 238 { 239 struct lge_softc *sc = (struct lge_softc *)dev; 240 int i; 241 242 /* 243 * If we have a non-PCS PHY, pretend that the internal 244 * autoneg stuff at PHY address 0 isn't there so that 245 * the miibus code will find only the GMII PHY. 246 */ 247 if (sc->lge_pcs == 0 && phy == 0) 248 return (0); 249 250 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 251 252 for (i = 0; i < LGE_TIMEOUT; i++) 253 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 254 break; 255 256 if (i == LGE_TIMEOUT) { 257 printf("%s: PHY read timed out\n", sc->sc_dv.dv_xname); 258 return (0); 259 } 260 261 return (CSR_READ_4(sc, LGE_GMIICTL) >> 16); 262 } 263 264 void 265 lge_miibus_writereg(struct device *dev, int phy, int reg, int data) 266 { 267 struct lge_softc *sc = (struct lge_softc *)dev; 268 int i; 269 270 CSR_WRITE_4(sc, LGE_GMIICTL, 271 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 272 273 for (i = 0; i < LGE_TIMEOUT; i++) 274 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 275 break; 276 277 if (i == LGE_TIMEOUT) { 278 printf("%s: PHY write timed out\n", sc->sc_dv.dv_xname); 279 } 280 } 281 282 void 283 lge_miibus_statchg(struct device *dev) 284 { 285 struct lge_softc *sc = (struct lge_softc *)dev; 286 struct mii_data *mii = &sc->lge_mii; 287 288 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 289 switch (IFM_SUBTYPE(mii->mii_media_active)) { 290 case IFM_1000_T: 291 case IFM_1000_SX: 292 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 293 break; 294 case IFM_100_TX: 295 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 296 break; 297 case IFM_10_T: 298 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 299 break; 300 default: 301 /* 302 * Choose something, even if it's wrong. Clearing 303 * all the bits will hose autoneg on the internal 304 * PHY. 305 */ 306 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 307 break; 308 } 309 310 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 311 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 312 } else { 313 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 314 } 315 } 316 317 void 318 lge_setmulti(struct lge_softc *sc) 319 { 320 struct arpcom *ac = &sc->arpcom; 321 struct ifnet *ifp = &ac->ac_if; 322 struct ether_multi *enm; 323 struct ether_multistep step; 324 u_int32_t h = 0, hashes[2] = { 0, 0 }; 325 326 /* Make sure multicast hash table is enabled. */ 327 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 328 329 allmulti: 330 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 331 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 332 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 333 return; 334 } 335 336 /* first, zot all the existing hash bits */ 337 CSR_WRITE_4(sc, LGE_MAR0, 0); 338 CSR_WRITE_4(sc, LGE_MAR1, 0); 339 340 /* now program new ones */ 341 ETHER_FIRST_MULTI(step, ac, enm); 342 while (enm != NULL) { 343 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 344 ifp->if_flags |= IFF_ALLMULTI; 345 goto allmulti; 346 } 347 h = (ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26) & 348 0x0000003F; 349 if (h < 32) 350 hashes[0] |= (1 << h); 351 else 352 hashes[1] |= (1 << (h - 32)); 353 ETHER_NEXT_MULTI(step, enm); 354 } 355 356 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 357 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 358 } 359 360 void 361 lge_reset(struct lge_softc *sc) 362 { 363 int i; 364 365 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 366 367 for (i = 0; i < LGE_TIMEOUT; i++) { 368 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 369 break; 370 } 371 372 if (i == LGE_TIMEOUT) 373 printf("%s: reset never completed\n", sc->sc_dv.dv_xname); 374 375 /* Wait a little while for the chip to get its brains in order. */ 376 DELAY(1000); 377 } 378 379 /* 380 * Probe for a Level 1 chip. Check the PCI vendor and device 381 * IDs against our list and return a device name if we find a match. 382 */ 383 int 384 lge_probe(struct device *parent, void *match, void *aux) 385 { 386 return (pci_matchbyid((struct pci_attach_args *)aux, lge_devices, 387 nitems(lge_devices))); 388 } 389 390 /* 391 * Attach the interface. Allocate softc structures, do ifmedia 392 * setup and ethernet/BPF attach. 393 */ 394 void 395 lge_attach(struct device *parent, struct device *self, void *aux) 396 { 397 struct lge_softc *sc = (struct lge_softc *)self; 398 struct pci_attach_args *pa = aux; 399 pci_chipset_tag_t pc = pa->pa_pc; 400 pci_intr_handle_t ih; 401 const char *intrstr = NULL; 402 bus_size_t size; 403 bus_dma_segment_t seg; 404 bus_dmamap_t dmamap; 405 int rseg; 406 u_char eaddr[ETHER_ADDR_LEN]; 407 pcireg_t command; 408 #ifndef LGE_USEIOSPACE 409 pcireg_t memtype; 410 #endif 411 struct ifnet *ifp; 412 caddr_t kva; 413 414 /* 415 * Handle power management nonsense. 416 */ 417 DPRINTFN(5, ("Preparing for conf read\n")); 418 command = pci_conf_read(pc, pa->pa_tag, LGE_PCI_CAPID) & 0x000000FF; 419 if (command == 0x01) { 420 command = pci_conf_read(pc, pa->pa_tag, LGE_PCI_PWRMGMTCTRL); 421 if (command & LGE_PSTATE_MASK) { 422 pcireg_t iobase, membase, irq; 423 424 /* Save important PCI config data. */ 425 iobase = pci_conf_read(pc, pa->pa_tag, LGE_PCI_LOIO); 426 membase = pci_conf_read(pc, pa->pa_tag, LGE_PCI_LOMEM); 427 irq = pci_conf_read(pc, pa->pa_tag, LGE_PCI_INTLINE); 428 429 /* Reset the power state. */ 430 printf("%s: chip is in D%d power mode " 431 "-- setting to D0\n", sc->sc_dv.dv_xname, 432 command & LGE_PSTATE_MASK); 433 command &= 0xFFFFFFFC; 434 pci_conf_write(pc, pa->pa_tag, 435 LGE_PCI_PWRMGMTCTRL, command); 436 437 /* Restore PCI config data. */ 438 pci_conf_write(pc, pa->pa_tag, LGE_PCI_LOIO, iobase); 439 pci_conf_write(pc, pa->pa_tag, LGE_PCI_LOMEM, membase); 440 pci_conf_write(pc, pa->pa_tag, LGE_PCI_INTLINE, irq); 441 } 442 } 443 444 /* 445 * Map control/status registers. 446 */ 447 DPRINTFN(5, ("Map control/status regs\n")); 448 449 DPRINTFN(5, ("pci_mapreg_map\n")); 450 #ifdef LGE_USEIOSPACE 451 if (pci_mapreg_map(pa, LGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 452 &sc->lge_btag, &sc->lge_bhandle, NULL, &size, 0)) { 453 printf(": can't map i/o space\n"); 454 return; 455 } 456 #else 457 memtype = pci_mapreg_type(pc, pa->pa_tag, LGE_PCI_LOMEM); 458 if (pci_mapreg_map(pa, LGE_PCI_LOMEM, memtype, 0, &sc->lge_btag, 459 &sc->lge_bhandle, NULL, &size, 0)) { 460 printf(": can't map mem space\n"); 461 return; 462 } 463 #endif 464 465 DPRINTFN(5, ("pci_intr_map\n")); 466 if (pci_intr_map(pa, &ih)) { 467 printf(": couldn't map interrupt\n"); 468 goto fail_1; 469 } 470 471 DPRINTFN(5, ("pci_intr_string\n")); 472 intrstr = pci_intr_string(pc, ih); 473 DPRINTFN(5, ("pci_intr_establish\n")); 474 sc->lge_intrhand = pci_intr_establish(pc, ih, IPL_NET, lge_intr, sc, 475 sc->sc_dv.dv_xname); 476 if (sc->lge_intrhand == NULL) { 477 printf(": couldn't establish interrupt"); 478 if (intrstr != NULL) 479 printf(" at %s", intrstr); 480 printf("\n"); 481 goto fail_1; 482 } 483 printf(": %s", intrstr); 484 485 /* Reset the adapter. */ 486 DPRINTFN(5, ("lge_reset\n")); 487 lge_reset(sc); 488 489 /* 490 * Get station address from the EEPROM. 491 */ 492 DPRINTFN(5, ("lge_read_eeprom\n")); 493 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 494 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 495 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 496 497 /* 498 * A Level 1 chip was detected. Inform the world. 499 */ 500 printf(", address %s\n", ether_sprintf(eaddr)); 501 502 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 503 504 sc->sc_dmatag = pa->pa_dmat; 505 DPRINTFN(5, ("bus_dmamem_alloc\n")); 506 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct lge_list_data), 507 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 508 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 509 goto fail_2; 510 } 511 DPRINTFN(5, ("bus_dmamem_map\n")); 512 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 513 sizeof(struct lge_list_data), &kva, 514 BUS_DMA_NOWAIT)) { 515 printf("%s: can't map dma buffers (%d bytes)\n", 516 sc->sc_dv.dv_xname, sizeof(struct lge_list_data)); 517 goto fail_3; 518 } 519 DPRINTFN(5, ("bus_dmamem_create\n")); 520 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct lge_list_data), 1, 521 sizeof(struct lge_list_data), 0, 522 BUS_DMA_NOWAIT, &dmamap)) { 523 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 524 goto fail_4; 525 } 526 DPRINTFN(5, ("bus_dmamem_load\n")); 527 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, 528 sizeof(struct lge_list_data), NULL, 529 BUS_DMA_NOWAIT)) { 530 goto fail_5; 531 } 532 533 DPRINTFN(5, ("bzero\n")); 534 sc->lge_ldata = (struct lge_list_data *)kva; 535 536 /* Try to allocate memory for jumbo buffers. */ 537 DPRINTFN(5, ("lge_alloc_jumbo_mem\n")); 538 if (lge_alloc_jumbo_mem(sc)) { 539 printf("%s: jumbo buffer allocation failed\n", 540 sc->sc_dv.dv_xname); 541 goto fail_5; 542 } 543 544 ifp = &sc->arpcom.ac_if; 545 ifp->if_softc = sc; 546 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 547 ifp->if_ioctl = lge_ioctl; 548 ifp->if_start = lge_start; 549 ifp->if_watchdog = lge_watchdog; 550 ifp->if_baudrate = 1000000000; 551 ifp->if_hardmtu = LGE_JUMBO_MTU; 552 IFQ_SET_MAXLEN(&ifp->if_snd, LGE_TX_LIST_CNT - 1); 553 IFQ_SET_READY(&ifp->if_snd); 554 DPRINTFN(5, ("bcopy\n")); 555 bcopy(sc->sc_dv.dv_xname, ifp->if_xname, IFNAMSIZ); 556 557 ifp->if_capabilities = IFCAP_VLAN_MTU; 558 559 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 560 sc->lge_pcs = 1; 561 else 562 sc->lge_pcs = 0; 563 564 /* 565 * Do MII setup. 566 */ 567 DPRINTFN(5, ("mii setup\n")); 568 sc->lge_mii.mii_ifp = ifp; 569 sc->lge_mii.mii_readreg = lge_miibus_readreg; 570 sc->lge_mii.mii_writereg = lge_miibus_writereg; 571 sc->lge_mii.mii_statchg = lge_miibus_statchg; 572 ifmedia_init(&sc->lge_mii.mii_media, 0, lge_ifmedia_upd, 573 lge_ifmedia_sts); 574 mii_attach(&sc->sc_dv, &sc->lge_mii, 0xffffffff, MII_PHY_ANY, 575 MII_OFFSET_ANY, 0); 576 577 if (LIST_FIRST(&sc->lge_mii.mii_phys) == NULL) { 578 printf("%s: no PHY found!\n", sc->sc_dv.dv_xname); 579 ifmedia_add(&sc->lge_mii.mii_media, IFM_ETHER|IFM_MANUAL, 580 0, NULL); 581 ifmedia_set(&sc->lge_mii.mii_media, IFM_ETHER|IFM_MANUAL); 582 } else { 583 DPRINTFN(5, ("ifmedia_set\n")); 584 ifmedia_set(&sc->lge_mii.mii_media, IFM_ETHER|IFM_AUTO); 585 } 586 587 /* 588 * Call MI attach routine. 589 */ 590 DPRINTFN(5, ("if_attach\n")); 591 if_attach(ifp); 592 DPRINTFN(5, ("ether_ifattach\n")); 593 ether_ifattach(ifp); 594 DPRINTFN(5, ("timeout_set\n")); 595 timeout_set(&sc->lge_timeout, lge_tick, sc); 596 timeout_add_sec(&sc->lge_timeout, 1); 597 return; 598 599 fail_5: 600 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 601 602 fail_4: 603 bus_dmamem_unmap(sc->sc_dmatag, kva, 604 sizeof(struct lge_list_data)); 605 606 fail_3: 607 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 608 609 fail_2: 610 pci_intr_disestablish(pc, sc->lge_intrhand); 611 612 fail_1: 613 bus_space_unmap(sc->lge_btag, sc->lge_bhandle, size); 614 } 615 616 /* 617 * Initialize the transmit descriptors. 618 */ 619 int 620 lge_list_tx_init(struct lge_softc *sc) 621 { 622 struct lge_list_data *ld; 623 struct lge_ring_data *cd; 624 int i; 625 626 cd = &sc->lge_cdata; 627 ld = sc->lge_ldata; 628 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 629 ld->lge_tx_list[i].lge_mbuf = NULL; 630 ld->lge_tx_list[i].lge_ctl = 0; 631 } 632 633 cd->lge_tx_prod = cd->lge_tx_cons = 0; 634 635 return (0); 636 } 637 638 639 /* 640 * Initialize the RX descriptors and allocate mbufs for them. Note that 641 * we arrange the descriptors in a closed ring, so that the last descriptor 642 * points back to the first. 643 */ 644 int 645 lge_list_rx_init(struct lge_softc *sc) 646 { 647 struct lge_list_data *ld; 648 struct lge_ring_data *cd; 649 int i; 650 651 ld = sc->lge_ldata; 652 cd = &sc->lge_cdata; 653 654 cd->lge_rx_prod = cd->lge_rx_cons = 0; 655 656 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 657 658 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 659 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 660 break; 661 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 662 return (ENOBUFS); 663 } 664 665 /* Clear possible 'rx command queue empty' interrupt. */ 666 CSR_READ_4(sc, LGE_ISR); 667 668 return (0); 669 } 670 671 /* 672 * Initialize a RX descriptor and attach a MBUF cluster. 673 */ 674 int 675 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m) 676 { 677 struct mbuf *m_new = NULL; 678 679 if (m == NULL) { 680 caddr_t buf = NULL; 681 682 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 683 if (m_new == NULL) 684 return (ENOBUFS); 685 686 /* Allocate the jumbo buffer */ 687 buf = lge_jalloc(sc); 688 if (buf == NULL) { 689 m_freem(m_new); 690 return (ENOBUFS); 691 } 692 693 /* Attach the buffer to the mbuf */ 694 m_new->m_len = m_new->m_pkthdr.len = LGE_JLEN; 695 MEXTADD(m_new, buf, LGE_JLEN, 0, lge_jfree, sc); 696 } else { 697 /* 698 * We're re-using a previously allocated mbuf; 699 * be sure to re-init pointers and lengths to 700 * default values. 701 */ 702 m_new = m; 703 m_new->m_len = m_new->m_pkthdr.len = LGE_JLEN; 704 m_new->m_data = m_new->m_ext.ext_buf; 705 } 706 707 /* 708 * Adjust alignment so packet payload begins on a 709 * longword boundary. Mandatory for Alpha, useful on 710 * x86 too. 711 */ 712 m_adj(m_new, ETHER_ALIGN); 713 714 c->lge_mbuf = m_new; 715 c->lge_fragptr_hi = 0; 716 c->lge_fragptr_lo = VTOPHYS(mtod(m_new, caddr_t)); 717 c->lge_fraglen = m_new->m_len; 718 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 719 c->lge_sts = 0; 720 721 /* 722 * Put this buffer in the RX command FIFO. To do this, 723 * we just write the physical address of the descriptor 724 * into the RX descriptor address registers. Note that 725 * there are two registers, one high DWORD and one low 726 * DWORD, which lets us specify a 64-bit address if 727 * desired. We only use a 32-bit address for now. 728 * Writing to the low DWORD register is what actually 729 * causes the command to be issued, so we do that 730 * last. 731 */ 732 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, VTOPHYS(c)); 733 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 734 735 return (0); 736 } 737 738 int 739 lge_alloc_jumbo_mem(struct lge_softc *sc) 740 { 741 caddr_t ptr, kva; 742 bus_dma_segment_t seg; 743 bus_dmamap_t dmamap; 744 int i, rseg, state, error; 745 struct lge_jpool_entry *entry; 746 747 state = error = 0; 748 749 /* Grab a big chunk o' storage. */ 750 if (bus_dmamem_alloc(sc->sc_dmatag, LGE_JMEM, PAGE_SIZE, 0, 751 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 752 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 753 return (ENOBUFS); 754 } 755 756 state = 1; 757 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, LGE_JMEM, &kva, 758 BUS_DMA_NOWAIT)) { 759 printf("%s: can't map dma buffers (%d bytes)\n", 760 sc->sc_dv.dv_xname, LGE_JMEM); 761 error = ENOBUFS; 762 goto out; 763 } 764 765 state = 2; 766 if (bus_dmamap_create(sc->sc_dmatag, LGE_JMEM, 1, 767 LGE_JMEM, 0, BUS_DMA_NOWAIT, &dmamap)) { 768 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 769 error = ENOBUFS; 770 goto out; 771 } 772 773 state = 3; 774 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, LGE_JMEM, 775 NULL, BUS_DMA_NOWAIT)) { 776 printf("%s: can't load dma map\n", sc->sc_dv.dv_xname); 777 error = ENOBUFS; 778 goto out; 779 } 780 781 state = 4; 782 sc->lge_cdata.lge_jumbo_buf = (caddr_t)kva; 783 DPRINTFN(1,("lge_jumbo_buf = 0x%08X\n", sc->lge_cdata.lge_jumbo_buf)); 784 DPRINTFN(1,("LGE_JLEN = 0x%08X\n", LGE_JLEN)); 785 786 LIST_INIT(&sc->lge_jfree_listhead); 787 LIST_INIT(&sc->lge_jinuse_listhead); 788 789 /* 790 * Now divide it up into 9K pieces and save the addresses 791 * in an array. 792 */ 793 ptr = sc->lge_cdata.lge_jumbo_buf; 794 for (i = 0; i < LGE_JSLOTS; i++) { 795 sc->lge_cdata.lge_jslots[i] = ptr; 796 ptr += LGE_JLEN; 797 entry = malloc(sizeof(struct lge_jpool_entry), 798 M_DEVBUF, M_NOWAIT); 799 if (entry == NULL) { 800 sc->lge_cdata.lge_jumbo_buf = NULL; 801 printf("%s: no memory for jumbo buffer queue!\n", 802 sc->sc_dv.dv_xname); 803 error = ENOBUFS; 804 goto out; 805 } 806 entry->slot = i; 807 LIST_INSERT_HEAD(&sc->lge_jfree_listhead, 808 entry, jpool_entries); 809 } 810 out: 811 if (error != 0) { 812 switch (state) { 813 case 4: 814 bus_dmamap_unload(sc->sc_dmatag, dmamap); 815 case 3: 816 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 817 case 2: 818 bus_dmamem_unmap(sc->sc_dmatag, kva, LGE_JMEM); 819 case 1: 820 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 821 break; 822 default: 823 break; 824 } 825 } 826 827 return (error); 828 } 829 830 /* 831 * Allocate a jumbo buffer. 832 */ 833 void * 834 lge_jalloc(struct lge_softc *sc) 835 { 836 struct lge_jpool_entry *entry; 837 838 entry = LIST_FIRST(&sc->lge_jfree_listhead); 839 840 if (entry == NULL) 841 return (NULL); 842 843 LIST_REMOVE(entry, jpool_entries); 844 LIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 845 return (sc->lge_cdata.lge_jslots[entry->slot]); 846 } 847 848 /* 849 * Release a jumbo buffer. 850 */ 851 void 852 lge_jfree(caddr_t buf, u_int size, void *arg) 853 { 854 struct lge_softc *sc; 855 int i; 856 struct lge_jpool_entry *entry; 857 858 /* Extract the softc struct pointer. */ 859 sc = (struct lge_softc *)arg; 860 861 if (sc == NULL) 862 panic("lge_jfree: can't find softc pointer!"); 863 864 /* calculate the slot this buffer belongs to */ 865 i = ((vaddr_t)buf - (vaddr_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 866 867 if ((i < 0) || (i >= LGE_JSLOTS)) 868 panic("lge_jfree: asked to free buffer that we don't manage!"); 869 870 entry = LIST_FIRST(&sc->lge_jinuse_listhead); 871 if (entry == NULL) 872 panic("lge_jfree: buffer not in use!"); 873 entry->slot = i; 874 LIST_REMOVE(entry, jpool_entries); 875 LIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 876 } 877 878 /* 879 * A frame has been uploaded: pass the resulting mbuf chain up to 880 * the higher level protocols. 881 */ 882 void 883 lge_rxeof(struct lge_softc *sc, int cnt) 884 { 885 struct mbuf *m; 886 struct ifnet *ifp; 887 struct lge_rx_desc *cur_rx; 888 int c, i, total_len = 0; 889 u_int32_t rxsts, rxctl; 890 891 ifp = &sc->arpcom.ac_if; 892 893 /* Find out how many frames were processed. */ 894 c = cnt; 895 i = sc->lge_cdata.lge_rx_cons; 896 897 /* Suck them in. */ 898 while(c) { 899 struct mbuf *m0 = NULL; 900 901 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 902 rxctl = cur_rx->lge_ctl; 903 rxsts = cur_rx->lge_sts; 904 m = cur_rx->lge_mbuf; 905 cur_rx->lge_mbuf = NULL; 906 total_len = LGE_RXBYTES(cur_rx); 907 LGE_INC(i, LGE_RX_LIST_CNT); 908 c--; 909 910 /* 911 * If an error occurs, update stats, clear the 912 * status word and leave the mbuf cluster in place: 913 * it should simply get re-used next time this descriptor 914 * comes up in the ring. 915 */ 916 if (rxctl & LGE_RXCTL_ERRMASK) { 917 ifp->if_ierrors++; 918 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 919 continue; 920 } 921 922 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 923 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 924 ifp, NULL); 925 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 926 if (m0 == NULL) { 927 ifp->if_ierrors++; 928 continue; 929 } 930 m = m0; 931 } else { 932 m->m_pkthdr.rcvif = ifp; 933 m->m_pkthdr.len = m->m_len = total_len; 934 } 935 936 ifp->if_ipackets++; 937 938 #if NBPFILTER > 0 939 /* 940 * Handle BPF listeners. Let the BPF user see the packet. 941 */ 942 if (ifp->if_bpf) 943 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 944 #endif 945 946 /* Do IP checksum checking. */ 947 if (rxsts & LGE_RXSTS_ISIP) { 948 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 949 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 950 } 951 if (rxsts & LGE_RXSTS_ISTCP) { 952 if (!(rxsts & LGE_RXSTS_TCPCSUMERR)) 953 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 954 } 955 if (rxsts & LGE_RXSTS_ISUDP) { 956 if (!(rxsts & LGE_RXSTS_UDPCSUMERR)) 957 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 958 } 959 960 ether_input_mbuf(ifp, m); 961 } 962 963 sc->lge_cdata.lge_rx_cons = i; 964 } 965 966 /* 967 * A frame was downloaded to the chip. It's safe for us to clean up 968 * the list buffers. 969 */ 970 971 void 972 lge_txeof(struct lge_softc *sc) 973 { 974 struct lge_tx_desc *cur_tx = NULL; 975 struct ifnet *ifp; 976 u_int32_t idx, txdone; 977 978 ifp = &sc->arpcom.ac_if; 979 980 /* Clear the timeout timer. */ 981 ifp->if_timer = 0; 982 983 /* 984 * Go through our tx list and free mbufs for those 985 * frames that have been transmitted. 986 */ 987 idx = sc->lge_cdata.lge_tx_cons; 988 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 989 990 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 991 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 992 993 ifp->if_opackets++; 994 if (cur_tx->lge_mbuf != NULL) { 995 m_freem(cur_tx->lge_mbuf); 996 cur_tx->lge_mbuf = NULL; 997 } 998 cur_tx->lge_ctl = 0; 999 1000 txdone--; 1001 LGE_INC(idx, LGE_TX_LIST_CNT); 1002 ifp->if_timer = 0; 1003 } 1004 1005 sc->lge_cdata.lge_tx_cons = idx; 1006 1007 if (cur_tx != NULL) 1008 ifp->if_flags &= ~IFF_OACTIVE; 1009 } 1010 1011 void 1012 lge_tick(void *xsc) 1013 { 1014 struct lge_softc *sc = xsc; 1015 struct mii_data *mii = &sc->lge_mii; 1016 struct ifnet *ifp = &sc->arpcom.ac_if; 1017 int s; 1018 1019 s = splnet(); 1020 1021 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1022 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1023 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1024 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1025 1026 if (!sc->lge_link) { 1027 mii_tick(mii); 1028 if (mii->mii_media_status & IFM_ACTIVE && 1029 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1030 sc->lge_link++; 1031 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1032 lge_start(ifp); 1033 } 1034 } 1035 1036 timeout_add_sec(&sc->lge_timeout, 1); 1037 1038 splx(s); 1039 } 1040 1041 int 1042 lge_intr(void *arg) 1043 { 1044 struct lge_softc *sc; 1045 struct ifnet *ifp; 1046 u_int32_t status; 1047 int claimed = 0; 1048 1049 sc = arg; 1050 ifp = &sc->arpcom.ac_if; 1051 1052 /* Suppress unwanted interrupts */ 1053 if (!(ifp->if_flags & IFF_UP)) { 1054 lge_stop(sc); 1055 return (0); 1056 } 1057 1058 for (;;) { 1059 /* 1060 * Reading the ISR register clears all interrupts, and 1061 * clears the 'interrupts enabled' bit in the IMR 1062 * register. 1063 */ 1064 status = CSR_READ_4(sc, LGE_ISR); 1065 1066 if ((status & LGE_INTRS) == 0) 1067 break; 1068 1069 claimed = 1; 1070 1071 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1072 lge_txeof(sc); 1073 1074 if (status & LGE_ISR_RXDMA_DONE) 1075 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1076 1077 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1078 lge_init(sc); 1079 1080 if (status & LGE_ISR_PHY_INTR) { 1081 sc->lge_link = 0; 1082 timeout_del(&sc->lge_timeout); 1083 lge_tick(sc); 1084 } 1085 } 1086 1087 /* Re-enable interrupts. */ 1088 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1089 1090 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1091 lge_start(ifp); 1092 1093 return (claimed); 1094 } 1095 1096 /* 1097 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1098 * pointers to the fragment pointers. 1099 */ 1100 int 1101 lge_encap(struct lge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1102 { 1103 struct lge_frag *f = NULL; 1104 struct lge_tx_desc *cur_tx; 1105 struct mbuf *m; 1106 int frag = 0, tot_len = 0; 1107 1108 /* 1109 * Start packing the mbufs in this chain into 1110 * the fragment pointers. Stop when we run out 1111 * of fragments or hit the end of the mbuf chain. 1112 */ 1113 m = m_head; 1114 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1115 frag = 0; 1116 1117 for (m = m_head; m != NULL; m = m->m_next) { 1118 if (m->m_len != 0) { 1119 tot_len += m->m_len; 1120 f = &cur_tx->lge_frags[frag]; 1121 f->lge_fraglen = m->m_len; 1122 f->lge_fragptr_lo = VTOPHYS(mtod(m, vaddr_t)); 1123 f->lge_fragptr_hi = 0; 1124 frag++; 1125 } 1126 } 1127 1128 if (m != NULL) 1129 return (ENOBUFS); 1130 1131 cur_tx->lge_mbuf = m_head; 1132 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1133 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1134 1135 /* Queue for transmit */ 1136 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, VTOPHYS(cur_tx)); 1137 1138 return (0); 1139 } 1140 1141 /* 1142 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1143 * to the mbuf data regions directly in the transmit lists. We also save a 1144 * copy of the pointers since the transmit list fragment pointers are 1145 * physical addresses. 1146 */ 1147 1148 void 1149 lge_start(struct ifnet *ifp) 1150 { 1151 struct lge_softc *sc; 1152 struct mbuf *m_head = NULL; 1153 u_int32_t idx; 1154 int pkts = 0; 1155 1156 sc = ifp->if_softc; 1157 1158 if (!sc->lge_link) 1159 return; 1160 1161 idx = sc->lge_cdata.lge_tx_prod; 1162 1163 if (ifp->if_flags & IFF_OACTIVE) 1164 return; 1165 1166 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1167 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1168 break; 1169 1170 IFQ_POLL(&ifp->if_snd, m_head); 1171 if (m_head == NULL) 1172 break; 1173 1174 if (lge_encap(sc, m_head, &idx)) { 1175 ifp->if_flags |= IFF_OACTIVE; 1176 break; 1177 } 1178 1179 /* now we are committed to transmit the packet */ 1180 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1181 pkts++; 1182 1183 #if NBPFILTER > 0 1184 /* 1185 * If there's a BPF listener, bounce a copy of this frame 1186 * to him. 1187 */ 1188 if (ifp->if_bpf) 1189 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1190 #endif 1191 } 1192 if (pkts == 0) 1193 return; 1194 1195 sc->lge_cdata.lge_tx_prod = idx; 1196 1197 /* 1198 * Set a timeout in case the chip goes out to lunch. 1199 */ 1200 ifp->if_timer = 5; 1201 } 1202 1203 void 1204 lge_init(void *xsc) 1205 { 1206 struct lge_softc *sc = xsc; 1207 struct ifnet *ifp = &sc->arpcom.ac_if; 1208 int s; 1209 1210 s = splnet(); 1211 1212 /* 1213 * Cancel pending I/O and free all RX/TX buffers. 1214 */ 1215 lge_stop(sc); 1216 lge_reset(sc); 1217 1218 /* Set MAC address */ 1219 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1220 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1221 1222 /* Init circular RX list. */ 1223 if (lge_list_rx_init(sc) == ENOBUFS) { 1224 printf("%s: initialization failed: no " 1225 "memory for rx buffers\n", sc->sc_dv.dv_xname); 1226 lge_stop(sc); 1227 splx(s); 1228 return; 1229 } 1230 1231 /* 1232 * Init tx descriptors. 1233 */ 1234 lge_list_tx_init(sc); 1235 1236 /* Set initial value for MODE1 register. */ 1237 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1238 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1239 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1240 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1241 1242 /* If we want promiscuous mode, set the allframes bit. */ 1243 if (ifp->if_flags & IFF_PROMISC) { 1244 CSR_WRITE_4(sc, LGE_MODE1, 1245 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1246 } else { 1247 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1248 } 1249 1250 /* 1251 * Set the capture broadcast bit to capture broadcast frames. 1252 */ 1253 if (ifp->if_flags & IFF_BROADCAST) { 1254 CSR_WRITE_4(sc, LGE_MODE1, 1255 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1256 } else { 1257 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1258 } 1259 1260 /* Packet padding workaround? */ 1261 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1262 1263 /* No error frames */ 1264 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1265 1266 /* Receive large frames */ 1267 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1268 1269 /* Workaround: disable RX/TX flow control */ 1270 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1271 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1272 1273 /* Make sure to strip CRC from received frames */ 1274 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1275 1276 /* Turn off magic packet mode */ 1277 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1278 1279 /* Turn off all VLAN stuff */ 1280 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1281 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1282 1283 /* Workarond: FIFO overflow */ 1284 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1285 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1286 1287 /* 1288 * Load the multicast filter. 1289 */ 1290 lge_setmulti(sc); 1291 1292 /* 1293 * Enable hardware checksum validation for all received IPv4 1294 * packets, do not reject packets with bad checksums. 1295 */ 1296 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1297 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1298 LGE_MODE2_RX_ERRCSUM); 1299 1300 /* 1301 * Enable the delivery of PHY interrupts based on 1302 * link/speed/duplex status chalges. 1303 */ 1304 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1305 1306 /* Enable receiver and transmitter. */ 1307 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1308 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1309 1310 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1311 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1312 1313 /* 1314 * Enable interrupts. 1315 */ 1316 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1317 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1318 1319 lge_ifmedia_upd(ifp); 1320 1321 ifp->if_flags |= IFF_RUNNING; 1322 ifp->if_flags &= ~IFF_OACTIVE; 1323 1324 splx(s); 1325 1326 timeout_add_sec(&sc->lge_timeout, 1); 1327 } 1328 1329 /* 1330 * Set media options. 1331 */ 1332 int 1333 lge_ifmedia_upd(struct ifnet *ifp) 1334 { 1335 struct lge_softc *sc = ifp->if_softc; 1336 struct mii_data *mii = &sc->lge_mii; 1337 1338 sc->lge_link = 0; 1339 if (mii->mii_instance) { 1340 struct mii_softc *miisc; 1341 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1342 mii_phy_reset(miisc); 1343 } 1344 mii_mediachg(mii); 1345 1346 return (0); 1347 } 1348 1349 /* 1350 * Report current media status. 1351 */ 1352 void 1353 lge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1354 { 1355 struct lge_softc *sc = ifp->if_softc; 1356 struct mii_data *mii = &sc->lge_mii; 1357 1358 mii_pollstat(mii); 1359 ifmr->ifm_active = mii->mii_media_active; 1360 ifmr->ifm_status = mii->mii_media_status; 1361 } 1362 1363 int 1364 lge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1365 { 1366 struct lge_softc *sc = ifp->if_softc; 1367 struct ifaddr *ifa = (struct ifaddr *) data; 1368 struct ifreq *ifr = (struct ifreq *) data; 1369 struct mii_data *mii; 1370 int s, error = 0; 1371 1372 s = splnet(); 1373 1374 switch(command) { 1375 case SIOCSIFADDR: 1376 ifp->if_flags |= IFF_UP; 1377 if (!(ifp->if_flags & IFF_RUNNING)) 1378 lge_init(sc); 1379 #ifdef INET 1380 if (ifa->ifa_addr->sa_family == AF_INET) 1381 arp_ifinit(&sc->arpcom, ifa); 1382 #endif /* INET */ 1383 break; 1384 1385 case SIOCSIFFLAGS: 1386 if (ifp->if_flags & IFF_UP) { 1387 if (ifp->if_flags & IFF_RUNNING && 1388 ifp->if_flags & IFF_PROMISC && 1389 !(sc->lge_if_flags & IFF_PROMISC)) { 1390 CSR_WRITE_4(sc, LGE_MODE1, 1391 LGE_MODE1_SETRST_CTL1| 1392 LGE_MODE1_RX_PROMISC); 1393 lge_setmulti(sc); 1394 } else if (ifp->if_flags & IFF_RUNNING && 1395 !(ifp->if_flags & IFF_PROMISC) && 1396 sc->lge_if_flags & IFF_PROMISC) { 1397 CSR_WRITE_4(sc, LGE_MODE1, 1398 LGE_MODE1_RX_PROMISC); 1399 lge_setmulti(sc); 1400 } else if (ifp->if_flags & IFF_RUNNING && 1401 (ifp->if_flags ^ sc->lge_if_flags) & IFF_ALLMULTI) { 1402 lge_setmulti(sc); 1403 } else { 1404 if (!(ifp->if_flags & IFF_RUNNING)) 1405 lge_init(sc); 1406 } 1407 } else { 1408 if (ifp->if_flags & IFF_RUNNING) 1409 lge_stop(sc); 1410 } 1411 sc->lge_if_flags = ifp->if_flags; 1412 break; 1413 1414 case SIOCGIFMEDIA: 1415 case SIOCSIFMEDIA: 1416 mii = &sc->lge_mii; 1417 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1418 break; 1419 1420 default: 1421 error = ether_ioctl(ifp, &sc->arpcom, command, data); 1422 } 1423 1424 if (error == ENETRESET) { 1425 if (ifp->if_flags & IFF_RUNNING) 1426 lge_setmulti(sc); 1427 error = 0; 1428 } 1429 1430 splx(s); 1431 return (error); 1432 } 1433 1434 void 1435 lge_watchdog(struct ifnet *ifp) 1436 { 1437 struct lge_softc *sc; 1438 1439 sc = ifp->if_softc; 1440 1441 ifp->if_oerrors++; 1442 printf("%s: watchdog timeout\n", sc->sc_dv.dv_xname); 1443 1444 lge_stop(sc); 1445 lge_reset(sc); 1446 lge_init(sc); 1447 1448 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1449 lge_start(ifp); 1450 } 1451 1452 /* 1453 * Stop the adapter and free any mbufs allocated to the 1454 * RX and TX lists. 1455 */ 1456 void 1457 lge_stop(struct lge_softc *sc) 1458 { 1459 int i; 1460 struct ifnet *ifp; 1461 1462 ifp = &sc->arpcom.ac_if; 1463 ifp->if_timer = 0; 1464 timeout_del(&sc->lge_timeout); 1465 1466 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1467 1468 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1469 1470 /* Disable receiver and transmitter. */ 1471 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1472 sc->lge_link = 0; 1473 1474 /* 1475 * Free data in the RX lists. 1476 */ 1477 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1478 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1479 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1480 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1481 } 1482 } 1483 bzero(&sc->lge_ldata->lge_rx_list, sizeof(sc->lge_ldata->lge_rx_list)); 1484 1485 /* 1486 * Free the TX list buffers. 1487 */ 1488 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1489 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1490 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1491 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1492 } 1493 } 1494 1495 bzero(&sc->lge_ldata->lge_tx_list, sizeof(sc->lge_ldata->lge_tx_list)); 1496 } 1497