1 /* $OpenBSD: if_lge.c,v 1.50 2008/11/28 02:44:18 brad Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 5 * Bill Paul <william.paul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.6 2001/06/20 19:47:55 bmilekic Exp $ 35 */ 36 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * Written by Bill Paul <william.paul@windriver.com> 42 * Wind River Systems 43 */ 44 45 /* 46 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 47 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 48 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 49 * are three supported methods for data transfer between host and 50 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 51 * Propulsion Technology (tm) DMA. The latter mechanism is a form 52 * of double buffer DMA where the packet data is copied to a 53 * pre-allocated DMA buffer who's physical address has been loaded 54 * into a table at device initialization time. The rationale is that 55 * the virtual to physical address translation needed for normal 56 * scatter/gather DMA is more expensive than the data copy needed 57 * for double buffering. This may be true in Windows NT and the like, 58 * but it isn't true for us, at least on the x86 arch. This driver 59 * uses the scatter/gather I/O method for both TX and RX. 60 * 61 * The LXT1001 only supports TCP/IP checksum offload on receive. 62 * Also, the VLAN tagging is done using a 16-entry table which allows 63 * the chip to perform hardware filtering based on VLAN tags. Sadly, 64 * our vlan support doesn't currently play well with this kind of 65 * hardware support. 66 * 67 * Special thanks to: 68 * - Jeff James at Intel, for arranging to have the LXT1001 manual 69 * released (at long last) 70 * - Beny Chen at D-Link, for actually sending it to me 71 * - Brad Short and Keith Alexis at SMC, for sending me sample 72 * SMC9462SX and SMC9462TX adapters for testing 73 * - Paul Saab at Y!, for not killing me (though it remains to be seen 74 * if in fact he did me much of a favor) 75 */ 76 77 #include "bpfilter.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/sockio.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/device.h> 86 #include <sys/socket.h> 87 88 #include <net/if.h> 89 #include <net/if_dl.h> 90 #include <net/if_media.h> 91 92 #ifdef INET 93 #include <netinet/in.h> 94 #include <netinet/in_systm.h> 95 #include <netinet/in_var.h> 96 #include <netinet/ip.h> 97 #include <netinet/if_ether.h> 98 #endif 99 100 #if NBPFILTER > 0 101 #include <net/bpf.h> 102 #endif 103 104 #include <uvm/uvm_extern.h> /* for vtophys */ 105 #define VTOPHYS(v) vtophys((vaddr_t)(v)) 106 107 #include <dev/pci/pcireg.h> 108 #include <dev/pci/pcivar.h> 109 #include <dev/pci/pcidevs.h> 110 111 #include <dev/mii/mii.h> 112 #include <dev/mii/miivar.h> 113 114 #define LGE_USEIOSPACE 115 116 #include <dev/pci/if_lgereg.h> 117 118 int lge_probe(struct device *, void *, void *); 119 void lge_attach(struct device *, struct device *, void *); 120 121 struct cfattach lge_ca = { 122 sizeof(struct lge_softc), lge_probe, lge_attach 123 }; 124 125 struct cfdriver lge_cd = { 126 0, "lge", DV_IFNET 127 }; 128 129 int lge_alloc_jumbo_mem(struct lge_softc *); 130 void *lge_jalloc(struct lge_softc *); 131 void lge_jfree(caddr_t, u_int, void *); 132 133 int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, 134 struct mbuf *); 135 int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 136 void lge_rxeof(struct lge_softc *, int); 137 void lge_txeof(struct lge_softc *); 138 int lge_intr(void *); 139 void lge_tick(void *); 140 void lge_start(struct ifnet *); 141 int lge_ioctl(struct ifnet *, u_long, caddr_t); 142 void lge_init(void *); 143 void lge_stop(struct lge_softc *); 144 void lge_watchdog(struct ifnet *); 145 void lge_shutdown(void *); 146 int lge_ifmedia_upd(struct ifnet *); 147 void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 148 149 void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 150 void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 151 152 int lge_miibus_readreg(struct device *, int, int); 153 void lge_miibus_writereg(struct device *, int, int, int); 154 void lge_miibus_statchg(struct device *); 155 156 void lge_setmulti(struct lge_softc *); 157 void lge_reset(struct lge_softc *); 158 int lge_list_rx_init(struct lge_softc *); 159 int lge_list_tx_init(struct lge_softc *); 160 161 #ifdef LGE_DEBUG 162 #define DPRINTF(x) if (lgedebug) printf x 163 #define DPRINTFN(n,x) if (lgedebug >= (n)) printf x 164 int lgedebug = 0; 165 #else 166 #define DPRINTF(x) 167 #define DPRINTFN(n,x) 168 #endif 169 170 const struct pci_matchid lge_devices[] = { 171 { PCI_VENDOR_LEVEL1, PCI_PRODUCT_LEVEL1_LXT1001 } 172 }; 173 174 #define LGE_SETBIT(sc, reg, x) \ 175 CSR_WRITE_4(sc, reg, \ 176 CSR_READ_4(sc, reg) | (x)) 177 178 #define LGE_CLRBIT(sc, reg, x) \ 179 CSR_WRITE_4(sc, reg, \ 180 CSR_READ_4(sc, reg) & ~(x)) 181 182 #define SIO_SET(x) \ 183 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 184 185 #define SIO_CLR(x) \ 186 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 187 188 /* 189 * Read a word of data stored in the EEPROM at address 'addr.' 190 */ 191 void 192 lge_eeprom_getword(struct lge_softc *sc, int addr, u_int16_t *dest) 193 { 194 int i; 195 u_int32_t val; 196 197 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 198 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 199 200 for (i = 0; i < LGE_TIMEOUT; i++) 201 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 202 break; 203 204 if (i == LGE_TIMEOUT) { 205 printf("%s: EEPROM read timed out\n", sc->sc_dv.dv_xname); 206 return; 207 } 208 209 val = CSR_READ_4(sc, LGE_EEDATA); 210 211 if (addr & 1) 212 *dest = (val >> 16) & 0xFFFF; 213 else 214 *dest = val & 0xFFFF; 215 } 216 217 /* 218 * Read a sequence of words from the EEPROM. 219 */ 220 void 221 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, 222 int cnt, int swap) 223 { 224 int i; 225 u_int16_t word = 0, *ptr; 226 227 for (i = 0; i < cnt; i++) { 228 lge_eeprom_getword(sc, off + i, &word); 229 ptr = (u_int16_t *)(dest + (i * 2)); 230 if (swap) 231 *ptr = ntohs(word); 232 else 233 *ptr = word; 234 } 235 } 236 237 int 238 lge_miibus_readreg(struct device *dev, int phy, int reg) 239 { 240 struct lge_softc *sc = (struct lge_softc *)dev; 241 int i; 242 243 /* 244 * If we have a non-PCS PHY, pretend that the internal 245 * autoneg stuff at PHY address 0 isn't there so that 246 * the miibus code will find only the GMII PHY. 247 */ 248 if (sc->lge_pcs == 0 && phy == 0) 249 return (0); 250 251 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 252 253 for (i = 0; i < LGE_TIMEOUT; i++) 254 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 255 break; 256 257 if (i == LGE_TIMEOUT) { 258 printf("%s: PHY read timed out\n", sc->sc_dv.dv_xname); 259 return (0); 260 } 261 262 return (CSR_READ_4(sc, LGE_GMIICTL) >> 16); 263 } 264 265 void 266 lge_miibus_writereg(struct device *dev, int phy, int reg, int data) 267 { 268 struct lge_softc *sc = (struct lge_softc *)dev; 269 int i; 270 271 CSR_WRITE_4(sc, LGE_GMIICTL, 272 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 273 274 for (i = 0; i < LGE_TIMEOUT; i++) 275 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 276 break; 277 278 if (i == LGE_TIMEOUT) { 279 printf("%s: PHY write timed out\n", sc->sc_dv.dv_xname); 280 } 281 } 282 283 void 284 lge_miibus_statchg(struct device *dev) 285 { 286 struct lge_softc *sc = (struct lge_softc *)dev; 287 struct mii_data *mii = &sc->lge_mii; 288 289 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 290 switch (IFM_SUBTYPE(mii->mii_media_active)) { 291 case IFM_1000_T: 292 case IFM_1000_SX: 293 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 294 break; 295 case IFM_100_TX: 296 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 297 break; 298 case IFM_10_T: 299 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 300 break; 301 default: 302 /* 303 * Choose something, even if it's wrong. Clearing 304 * all the bits will hose autoneg on the internal 305 * PHY. 306 */ 307 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 308 break; 309 } 310 311 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 312 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 313 } else { 314 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 315 } 316 } 317 318 void 319 lge_setmulti(struct lge_softc *sc) 320 { 321 struct arpcom *ac = &sc->arpcom; 322 struct ifnet *ifp = &ac->ac_if; 323 struct ether_multi *enm; 324 struct ether_multistep step; 325 u_int32_t h = 0, hashes[2] = { 0, 0 }; 326 327 /* Make sure multicast hash table is enabled. */ 328 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 329 330 allmulti: 331 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 332 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 333 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 334 return; 335 } 336 337 /* first, zot all the existing hash bits */ 338 CSR_WRITE_4(sc, LGE_MAR0, 0); 339 CSR_WRITE_4(sc, LGE_MAR1, 0); 340 341 /* now program new ones */ 342 ETHER_FIRST_MULTI(step, ac, enm); 343 while (enm != NULL) { 344 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 345 ifp->if_flags |= IFF_ALLMULTI; 346 goto allmulti; 347 } 348 h = (ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26) & 349 0x0000003F; 350 if (h < 32) 351 hashes[0] |= (1 << h); 352 else 353 hashes[1] |= (1 << (h - 32)); 354 ETHER_NEXT_MULTI(step, enm); 355 } 356 357 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 358 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 359 } 360 361 void 362 lge_reset(struct lge_softc *sc) 363 { 364 int i; 365 366 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 367 368 for (i = 0; i < LGE_TIMEOUT; i++) { 369 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 370 break; 371 } 372 373 if (i == LGE_TIMEOUT) 374 printf("%s: reset never completed\n", sc->sc_dv.dv_xname); 375 376 /* Wait a little while for the chip to get its brains in order. */ 377 DELAY(1000); 378 } 379 380 /* 381 * Probe for a Level 1 chip. Check the PCI vendor and device 382 * IDs against our list and return a device name if we find a match. 383 */ 384 int 385 lge_probe(struct device *parent, void *match, void *aux) 386 { 387 return (pci_matchbyid((struct pci_attach_args *)aux, lge_devices, 388 sizeof(lge_devices)/sizeof(lge_devices[0]))); 389 } 390 391 /* 392 * Attach the interface. Allocate softc structures, do ifmedia 393 * setup and ethernet/BPF attach. 394 */ 395 void 396 lge_attach(struct device *parent, struct device *self, void *aux) 397 { 398 struct lge_softc *sc = (struct lge_softc *)self; 399 struct pci_attach_args *pa = aux; 400 pci_chipset_tag_t pc = pa->pa_pc; 401 pci_intr_handle_t ih; 402 const char *intrstr = NULL; 403 bus_size_t size; 404 bus_dma_segment_t seg; 405 bus_dmamap_t dmamap; 406 int rseg; 407 u_char eaddr[ETHER_ADDR_LEN]; 408 pcireg_t command; 409 #ifndef LGE_USEIOSPACE 410 pcireg_t memtype; 411 #endif 412 struct ifnet *ifp; 413 caddr_t kva; 414 415 /* 416 * Handle power management nonsense. 417 */ 418 DPRINTFN(5, ("Preparing for conf read\n")); 419 command = pci_conf_read(pc, pa->pa_tag, LGE_PCI_CAPID) & 0x000000FF; 420 if (command == 0x01) { 421 command = pci_conf_read(pc, pa->pa_tag, LGE_PCI_PWRMGMTCTRL); 422 if (command & LGE_PSTATE_MASK) { 423 pcireg_t iobase, membase, irq; 424 425 /* Save important PCI config data. */ 426 iobase = pci_conf_read(pc, pa->pa_tag, LGE_PCI_LOIO); 427 membase = pci_conf_read(pc, pa->pa_tag, LGE_PCI_LOMEM); 428 irq = pci_conf_read(pc, pa->pa_tag, LGE_PCI_INTLINE); 429 430 /* Reset the power state. */ 431 printf("%s: chip is in D%d power mode " 432 "-- setting to D0\n", sc->sc_dv.dv_xname, 433 command & LGE_PSTATE_MASK); 434 command &= 0xFFFFFFFC; 435 pci_conf_write(pc, pa->pa_tag, 436 LGE_PCI_PWRMGMTCTRL, command); 437 438 /* Restore PCI config data. */ 439 pci_conf_write(pc, pa->pa_tag, LGE_PCI_LOIO, iobase); 440 pci_conf_write(pc, pa->pa_tag, LGE_PCI_LOMEM, membase); 441 pci_conf_write(pc, pa->pa_tag, LGE_PCI_INTLINE, irq); 442 } 443 } 444 445 /* 446 * Map control/status registers. 447 */ 448 DPRINTFN(5, ("Map control/status regs\n")); 449 450 DPRINTFN(5, ("pci_mapreg_map\n")); 451 #ifdef LGE_USEIOSPACE 452 if (pci_mapreg_map(pa, LGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 453 &sc->lge_btag, &sc->lge_bhandle, NULL, &size, 0)) { 454 printf(": can't map i/o space\n"); 455 return; 456 } 457 #else 458 memtype = pci_mapreg_type(pc, pa->pa_tag, LGE_PCI_LOMEM); 459 if (pci_mapreg_map(pa, LGE_PCI_LOMEM, memtype, 0, &sc->lge_btag, 460 &sc->lge_bhandle, NULL, &size, 0)) { 461 printf(": can't map mem space\n"); 462 return; 463 } 464 #endif 465 466 DPRINTFN(5, ("pci_intr_map\n")); 467 if (pci_intr_map(pa, &ih)) { 468 printf(": couldn't map interrupt\n"); 469 goto fail_1; 470 } 471 472 DPRINTFN(5, ("pci_intr_string\n")); 473 intrstr = pci_intr_string(pc, ih); 474 DPRINTFN(5, ("pci_intr_establish\n")); 475 sc->lge_intrhand = pci_intr_establish(pc, ih, IPL_NET, lge_intr, sc, 476 sc->sc_dv.dv_xname); 477 if (sc->lge_intrhand == NULL) { 478 printf(": couldn't establish interrupt"); 479 if (intrstr != NULL) 480 printf(" at %s", intrstr); 481 printf("\n"); 482 goto fail_1; 483 } 484 printf(": %s", intrstr); 485 486 /* Reset the adapter. */ 487 DPRINTFN(5, ("lge_reset\n")); 488 lge_reset(sc); 489 490 /* 491 * Get station address from the EEPROM. 492 */ 493 DPRINTFN(5, ("lge_read_eeprom\n")); 494 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 495 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 496 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 497 498 /* 499 * A Level 1 chip was detected. Inform the world. 500 */ 501 printf(", address %s\n", ether_sprintf(eaddr)); 502 503 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 504 505 sc->sc_dmatag = pa->pa_dmat; 506 DPRINTFN(5, ("bus_dmamem_alloc\n")); 507 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct lge_list_data), 508 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 509 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 510 goto fail_2; 511 } 512 DPRINTFN(5, ("bus_dmamem_map\n")); 513 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 514 sizeof(struct lge_list_data), &kva, 515 BUS_DMA_NOWAIT)) { 516 printf("%s: can't map dma buffers (%d bytes)\n", 517 sc->sc_dv.dv_xname, sizeof(struct lge_list_data)); 518 goto fail_3; 519 } 520 DPRINTFN(5, ("bus_dmamem_create\n")); 521 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct lge_list_data), 1, 522 sizeof(struct lge_list_data), 0, 523 BUS_DMA_NOWAIT, &dmamap)) { 524 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 525 goto fail_4; 526 } 527 DPRINTFN(5, ("bus_dmamem_load\n")); 528 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, 529 sizeof(struct lge_list_data), NULL, 530 BUS_DMA_NOWAIT)) { 531 goto fail_5; 532 } 533 534 DPRINTFN(5, ("bzero\n")); 535 sc->lge_ldata = (struct lge_list_data *)kva; 536 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 537 538 /* Try to allocate memory for jumbo buffers. */ 539 DPRINTFN(5, ("lge_alloc_jumbo_mem\n")); 540 if (lge_alloc_jumbo_mem(sc)) { 541 printf("%s: jumbo buffer allocation failed\n", 542 sc->sc_dv.dv_xname); 543 goto fail_5; 544 } 545 546 ifp = &sc->arpcom.ac_if; 547 ifp->if_softc = sc; 548 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 549 ifp->if_ioctl = lge_ioctl; 550 ifp->if_start = lge_start; 551 ifp->if_watchdog = lge_watchdog; 552 ifp->if_baudrate = 1000000000; 553 ifp->if_hardmtu = LGE_JUMBO_MTU; 554 IFQ_SET_MAXLEN(&ifp->if_snd, LGE_TX_LIST_CNT - 1); 555 IFQ_SET_READY(&ifp->if_snd); 556 DPRINTFN(5, ("bcopy\n")); 557 bcopy(sc->sc_dv.dv_xname, ifp->if_xname, IFNAMSIZ); 558 559 ifp->if_capabilities = IFCAP_VLAN_MTU; 560 561 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 562 sc->lge_pcs = 1; 563 else 564 sc->lge_pcs = 0; 565 566 /* 567 * Do MII setup. 568 */ 569 DPRINTFN(5, ("mii setup\n")); 570 sc->lge_mii.mii_ifp = ifp; 571 sc->lge_mii.mii_readreg = lge_miibus_readreg; 572 sc->lge_mii.mii_writereg = lge_miibus_writereg; 573 sc->lge_mii.mii_statchg = lge_miibus_statchg; 574 ifmedia_init(&sc->lge_mii.mii_media, 0, lge_ifmedia_upd, 575 lge_ifmedia_sts); 576 mii_attach(&sc->sc_dv, &sc->lge_mii, 0xffffffff, MII_PHY_ANY, 577 MII_OFFSET_ANY, 0); 578 579 if (LIST_FIRST(&sc->lge_mii.mii_phys) == NULL) { 580 printf("%s: no PHY found!\n", sc->sc_dv.dv_xname); 581 ifmedia_add(&sc->lge_mii.mii_media, IFM_ETHER|IFM_MANUAL, 582 0, NULL); 583 ifmedia_set(&sc->lge_mii.mii_media, IFM_ETHER|IFM_MANUAL); 584 } else { 585 DPRINTFN(5, ("ifmedia_set\n")); 586 ifmedia_set(&sc->lge_mii.mii_media, IFM_ETHER|IFM_AUTO); 587 } 588 589 /* 590 * Call MI attach routine. 591 */ 592 DPRINTFN(5, ("if_attach\n")); 593 if_attach(ifp); 594 DPRINTFN(5, ("ether_ifattach\n")); 595 ether_ifattach(ifp); 596 DPRINTFN(5, ("timeout_set\n")); 597 timeout_set(&sc->lge_timeout, lge_tick, sc); 598 timeout_add_sec(&sc->lge_timeout, 1); 599 return; 600 601 fail_5: 602 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 603 604 fail_4: 605 bus_dmamem_unmap(sc->sc_dmatag, kva, 606 sizeof(struct lge_list_data)); 607 608 fail_3: 609 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 610 611 fail_2: 612 pci_intr_disestablish(pc, sc->lge_intrhand); 613 614 fail_1: 615 bus_space_unmap(sc->lge_btag, sc->lge_bhandle, size); 616 } 617 618 /* 619 * Initialize the transmit descriptors. 620 */ 621 int 622 lge_list_tx_init(struct lge_softc *sc) 623 { 624 struct lge_list_data *ld; 625 struct lge_ring_data *cd; 626 int i; 627 628 cd = &sc->lge_cdata; 629 ld = sc->lge_ldata; 630 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 631 ld->lge_tx_list[i].lge_mbuf = NULL; 632 ld->lge_tx_list[i].lge_ctl = 0; 633 } 634 635 cd->lge_tx_prod = cd->lge_tx_cons = 0; 636 637 return (0); 638 } 639 640 641 /* 642 * Initialize the RX descriptors and allocate mbufs for them. Note that 643 * we arrange the descriptors in a closed ring, so that the last descriptor 644 * points back to the first. 645 */ 646 int 647 lge_list_rx_init(struct lge_softc *sc) 648 { 649 struct lge_list_data *ld; 650 struct lge_ring_data *cd; 651 int i; 652 653 ld = sc->lge_ldata; 654 cd = &sc->lge_cdata; 655 656 cd->lge_rx_prod = cd->lge_rx_cons = 0; 657 658 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 659 660 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 661 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 662 break; 663 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 664 return (ENOBUFS); 665 } 666 667 /* Clear possible 'rx command queue empty' interrupt. */ 668 CSR_READ_4(sc, LGE_ISR); 669 670 return (0); 671 } 672 673 /* 674 * Initialize a RX descriptor and attach a MBUF cluster. 675 */ 676 int 677 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m) 678 { 679 struct mbuf *m_new = NULL; 680 681 if (m == NULL) { 682 caddr_t buf = NULL; 683 684 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 685 if (m_new == NULL) 686 return (ENOBUFS); 687 688 /* Allocate the jumbo buffer */ 689 buf = lge_jalloc(sc); 690 if (buf == NULL) { 691 m_freem(m_new); 692 return (ENOBUFS); 693 } 694 695 /* Attach the buffer to the mbuf */ 696 m_new->m_len = m_new->m_pkthdr.len = LGE_JLEN; 697 MEXTADD(m_new, buf, LGE_JLEN, 0, lge_jfree, sc); 698 } else { 699 /* 700 * We're re-using a previously allocated mbuf; 701 * be sure to re-init pointers and lengths to 702 * default values. 703 */ 704 m_new = m; 705 m_new->m_len = m_new->m_pkthdr.len = LGE_JLEN; 706 m_new->m_data = m_new->m_ext.ext_buf; 707 } 708 709 /* 710 * Adjust alignment so packet payload begins on a 711 * longword boundary. Mandatory for Alpha, useful on 712 * x86 too. 713 */ 714 m_adj(m_new, ETHER_ALIGN); 715 716 c->lge_mbuf = m_new; 717 c->lge_fragptr_hi = 0; 718 c->lge_fragptr_lo = VTOPHYS(mtod(m_new, caddr_t)); 719 c->lge_fraglen = m_new->m_len; 720 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 721 c->lge_sts = 0; 722 723 /* 724 * Put this buffer in the RX command FIFO. To do this, 725 * we just write the physical address of the descriptor 726 * into the RX descriptor address registers. Note that 727 * there are two registers, one high DWORD and one low 728 * DWORD, which lets us specify a 64-bit address if 729 * desired. We only use a 32-bit address for now. 730 * Writing to the low DWORD register is what actually 731 * causes the command to be issued, so we do that 732 * last. 733 */ 734 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, VTOPHYS(c)); 735 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 736 737 return (0); 738 } 739 740 int 741 lge_alloc_jumbo_mem(struct lge_softc *sc) 742 { 743 caddr_t ptr, kva; 744 bus_dma_segment_t seg; 745 bus_dmamap_t dmamap; 746 int i, rseg, state, error; 747 struct lge_jpool_entry *entry; 748 749 state = error = 0; 750 751 /* Grab a big chunk o' storage. */ 752 if (bus_dmamem_alloc(sc->sc_dmatag, LGE_JMEM, PAGE_SIZE, 0, 753 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 754 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 755 return (ENOBUFS); 756 } 757 758 state = 1; 759 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, LGE_JMEM, &kva, 760 BUS_DMA_NOWAIT)) { 761 printf("%s: can't map dma buffers (%d bytes)\n", 762 sc->sc_dv.dv_xname, LGE_JMEM); 763 error = ENOBUFS; 764 goto out; 765 } 766 767 state = 2; 768 if (bus_dmamap_create(sc->sc_dmatag, LGE_JMEM, 1, 769 LGE_JMEM, 0, BUS_DMA_NOWAIT, &dmamap)) { 770 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 771 error = ENOBUFS; 772 goto out; 773 } 774 775 state = 3; 776 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, LGE_JMEM, 777 NULL, BUS_DMA_NOWAIT)) { 778 printf("%s: can't load dma map\n", sc->sc_dv.dv_xname); 779 error = ENOBUFS; 780 goto out; 781 } 782 783 state = 4; 784 sc->lge_cdata.lge_jumbo_buf = (caddr_t)kva; 785 DPRINTFN(1,("lge_jumbo_buf = 0x%08X\n", sc->lge_cdata.lge_jumbo_buf)); 786 DPRINTFN(1,("LGE_JLEN = 0x%08X\n", LGE_JLEN)); 787 788 LIST_INIT(&sc->lge_jfree_listhead); 789 LIST_INIT(&sc->lge_jinuse_listhead); 790 791 /* 792 * Now divide it up into 9K pieces and save the addresses 793 * in an array. 794 */ 795 ptr = sc->lge_cdata.lge_jumbo_buf; 796 for (i = 0; i < LGE_JSLOTS; i++) { 797 sc->lge_cdata.lge_jslots[i] = ptr; 798 ptr += LGE_JLEN; 799 entry = malloc(sizeof(struct lge_jpool_entry), 800 M_DEVBUF, M_NOWAIT); 801 if (entry == NULL) { 802 sc->lge_cdata.lge_jumbo_buf = NULL; 803 printf("%s: no memory for jumbo buffer queue!\n", 804 sc->sc_dv.dv_xname); 805 error = ENOBUFS; 806 goto out; 807 } 808 entry->slot = i; 809 LIST_INSERT_HEAD(&sc->lge_jfree_listhead, 810 entry, jpool_entries); 811 } 812 out: 813 if (error != 0) { 814 switch (state) { 815 case 4: 816 bus_dmamap_unload(sc->sc_dmatag, dmamap); 817 case 3: 818 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 819 case 2: 820 bus_dmamem_unmap(sc->sc_dmatag, kva, LGE_JMEM); 821 case 1: 822 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 823 break; 824 default: 825 break; 826 } 827 } 828 829 return (error); 830 } 831 832 /* 833 * Allocate a jumbo buffer. 834 */ 835 void * 836 lge_jalloc(struct lge_softc *sc) 837 { 838 struct lge_jpool_entry *entry; 839 840 entry = LIST_FIRST(&sc->lge_jfree_listhead); 841 842 if (entry == NULL) 843 return (NULL); 844 845 LIST_REMOVE(entry, jpool_entries); 846 LIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 847 return (sc->lge_cdata.lge_jslots[entry->slot]); 848 } 849 850 /* 851 * Release a jumbo buffer. 852 */ 853 void 854 lge_jfree(caddr_t buf, u_int size, void *arg) 855 { 856 struct lge_softc *sc; 857 int i; 858 struct lge_jpool_entry *entry; 859 860 /* Extract the softc struct pointer. */ 861 sc = (struct lge_softc *)arg; 862 863 if (sc == NULL) 864 panic("lge_jfree: can't find softc pointer!"); 865 866 /* calculate the slot this buffer belongs to */ 867 i = ((vaddr_t)buf - (vaddr_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 868 869 if ((i < 0) || (i >= LGE_JSLOTS)) 870 panic("lge_jfree: asked to free buffer that we don't manage!"); 871 872 entry = LIST_FIRST(&sc->lge_jinuse_listhead); 873 if (entry == NULL) 874 panic("lge_jfree: buffer not in use!"); 875 entry->slot = i; 876 LIST_REMOVE(entry, jpool_entries); 877 LIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 878 } 879 880 /* 881 * A frame has been uploaded: pass the resulting mbuf chain up to 882 * the higher level protocols. 883 */ 884 void 885 lge_rxeof(struct lge_softc *sc, int cnt) 886 { 887 struct mbuf *m; 888 struct ifnet *ifp; 889 struct lge_rx_desc *cur_rx; 890 int c, i, total_len = 0; 891 u_int32_t rxsts, rxctl; 892 893 ifp = &sc->arpcom.ac_if; 894 895 /* Find out how many frames were processed. */ 896 c = cnt; 897 i = sc->lge_cdata.lge_rx_cons; 898 899 /* Suck them in. */ 900 while(c) { 901 struct mbuf *m0 = NULL; 902 903 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 904 rxctl = cur_rx->lge_ctl; 905 rxsts = cur_rx->lge_sts; 906 m = cur_rx->lge_mbuf; 907 cur_rx->lge_mbuf = NULL; 908 total_len = LGE_RXBYTES(cur_rx); 909 LGE_INC(i, LGE_RX_LIST_CNT); 910 c--; 911 912 /* 913 * If an error occurs, update stats, clear the 914 * status word and leave the mbuf cluster in place: 915 * it should simply get re-used next time this descriptor 916 * comes up in the ring. 917 */ 918 if (rxctl & LGE_RXCTL_ERRMASK) { 919 ifp->if_ierrors++; 920 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 921 continue; 922 } 923 924 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 925 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 926 ifp, NULL); 927 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 928 if (m0 == NULL) { 929 ifp->if_ierrors++; 930 continue; 931 } 932 m = m0; 933 } else { 934 m->m_pkthdr.rcvif = ifp; 935 m->m_pkthdr.len = m->m_len = total_len; 936 } 937 938 ifp->if_ipackets++; 939 940 #if NBPFILTER > 0 941 /* 942 * Handle BPF listeners. Let the BPF user see the packet. 943 */ 944 if (ifp->if_bpf) 945 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 946 #endif 947 948 /* Do IP checksum checking. */ 949 if (rxsts & LGE_RXSTS_ISIP) { 950 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 951 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 952 } 953 if (rxsts & LGE_RXSTS_ISTCP) { 954 if (!(rxsts & LGE_RXSTS_TCPCSUMERR)) 955 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 956 } 957 if (rxsts & LGE_RXSTS_ISUDP) { 958 if (!(rxsts & LGE_RXSTS_UDPCSUMERR)) 959 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 960 } 961 962 ether_input_mbuf(ifp, m); 963 } 964 965 sc->lge_cdata.lge_rx_cons = i; 966 } 967 968 /* 969 * A frame was downloaded to the chip. It's safe for us to clean up 970 * the list buffers. 971 */ 972 973 void 974 lge_txeof(struct lge_softc *sc) 975 { 976 struct lge_tx_desc *cur_tx = NULL; 977 struct ifnet *ifp; 978 u_int32_t idx, txdone; 979 980 ifp = &sc->arpcom.ac_if; 981 982 /* Clear the timeout timer. */ 983 ifp->if_timer = 0; 984 985 /* 986 * Go through our tx list and free mbufs for those 987 * frames that have been transmitted. 988 */ 989 idx = sc->lge_cdata.lge_tx_cons; 990 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 991 992 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 993 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 994 995 ifp->if_opackets++; 996 if (cur_tx->lge_mbuf != NULL) { 997 m_freem(cur_tx->lge_mbuf); 998 cur_tx->lge_mbuf = NULL; 999 } 1000 cur_tx->lge_ctl = 0; 1001 1002 txdone--; 1003 LGE_INC(idx, LGE_TX_LIST_CNT); 1004 ifp->if_timer = 0; 1005 } 1006 1007 sc->lge_cdata.lge_tx_cons = idx; 1008 1009 if (cur_tx != NULL) 1010 ifp->if_flags &= ~IFF_OACTIVE; 1011 } 1012 1013 void 1014 lge_tick(void *xsc) 1015 { 1016 struct lge_softc *sc = xsc; 1017 struct mii_data *mii = &sc->lge_mii; 1018 struct ifnet *ifp = &sc->arpcom.ac_if; 1019 int s; 1020 1021 s = splnet(); 1022 1023 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1024 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1025 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1026 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1027 1028 if (!sc->lge_link) { 1029 mii_tick(mii); 1030 if (mii->mii_media_status & IFM_ACTIVE && 1031 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1032 sc->lge_link++; 1033 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1034 lge_start(ifp); 1035 } 1036 } 1037 1038 timeout_add_sec(&sc->lge_timeout, 1); 1039 1040 splx(s); 1041 } 1042 1043 int 1044 lge_intr(void *arg) 1045 { 1046 struct lge_softc *sc; 1047 struct ifnet *ifp; 1048 u_int32_t status; 1049 int claimed = 0; 1050 1051 sc = arg; 1052 ifp = &sc->arpcom.ac_if; 1053 1054 /* Suppress unwanted interrupts */ 1055 if (!(ifp->if_flags & IFF_UP)) { 1056 lge_stop(sc); 1057 return (0); 1058 } 1059 1060 for (;;) { 1061 /* 1062 * Reading the ISR register clears all interrupts, and 1063 * clears the 'interrupts enabled' bit in the IMR 1064 * register. 1065 */ 1066 status = CSR_READ_4(sc, LGE_ISR); 1067 1068 if ((status & LGE_INTRS) == 0) 1069 break; 1070 1071 claimed = 1; 1072 1073 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1074 lge_txeof(sc); 1075 1076 if (status & LGE_ISR_RXDMA_DONE) 1077 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1078 1079 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1080 lge_init(sc); 1081 1082 if (status & LGE_ISR_PHY_INTR) { 1083 sc->lge_link = 0; 1084 timeout_del(&sc->lge_timeout); 1085 lge_tick(sc); 1086 } 1087 } 1088 1089 /* Re-enable interrupts. */ 1090 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1091 1092 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1093 lge_start(ifp); 1094 1095 return (claimed); 1096 } 1097 1098 /* 1099 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1100 * pointers to the fragment pointers. 1101 */ 1102 int 1103 lge_encap(struct lge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1104 { 1105 struct lge_frag *f = NULL; 1106 struct lge_tx_desc *cur_tx; 1107 struct mbuf *m; 1108 int frag = 0, tot_len = 0; 1109 1110 /* 1111 * Start packing the mbufs in this chain into 1112 * the fragment pointers. Stop when we run out 1113 * of fragments or hit the end of the mbuf chain. 1114 */ 1115 m = m_head; 1116 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1117 frag = 0; 1118 1119 for (m = m_head; m != NULL; m = m->m_next) { 1120 if (m->m_len != 0) { 1121 tot_len += m->m_len; 1122 f = &cur_tx->lge_frags[frag]; 1123 f->lge_fraglen = m->m_len; 1124 f->lge_fragptr_lo = VTOPHYS(mtod(m, vaddr_t)); 1125 f->lge_fragptr_hi = 0; 1126 frag++; 1127 } 1128 } 1129 1130 if (m != NULL) 1131 return (ENOBUFS); 1132 1133 cur_tx->lge_mbuf = m_head; 1134 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1135 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1136 1137 /* Queue for transmit */ 1138 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, VTOPHYS(cur_tx)); 1139 1140 return (0); 1141 } 1142 1143 /* 1144 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1145 * to the mbuf data regions directly in the transmit lists. We also save a 1146 * copy of the pointers since the transmit list fragment pointers are 1147 * physical addresses. 1148 */ 1149 1150 void 1151 lge_start(struct ifnet *ifp) 1152 { 1153 struct lge_softc *sc; 1154 struct mbuf *m_head = NULL; 1155 u_int32_t idx; 1156 int pkts = 0; 1157 1158 sc = ifp->if_softc; 1159 1160 if (!sc->lge_link) 1161 return; 1162 1163 idx = sc->lge_cdata.lge_tx_prod; 1164 1165 if (ifp->if_flags & IFF_OACTIVE) 1166 return; 1167 1168 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1169 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1170 break; 1171 1172 IFQ_POLL(&ifp->if_snd, m_head); 1173 if (m_head == NULL) 1174 break; 1175 1176 if (lge_encap(sc, m_head, &idx)) { 1177 ifp->if_flags |= IFF_OACTIVE; 1178 break; 1179 } 1180 1181 /* now we are committed to transmit the packet */ 1182 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1183 pkts++; 1184 1185 #if NBPFILTER > 0 1186 /* 1187 * If there's a BPF listener, bounce a copy of this frame 1188 * to him. 1189 */ 1190 if (ifp->if_bpf) 1191 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1192 #endif 1193 } 1194 if (pkts == 0) 1195 return; 1196 1197 sc->lge_cdata.lge_tx_prod = idx; 1198 1199 /* 1200 * Set a timeout in case the chip goes out to lunch. 1201 */ 1202 ifp->if_timer = 5; 1203 } 1204 1205 void 1206 lge_init(void *xsc) 1207 { 1208 struct lge_softc *sc = xsc; 1209 struct ifnet *ifp = &sc->arpcom.ac_if; 1210 int s; 1211 1212 s = splnet(); 1213 1214 /* 1215 * Cancel pending I/O and free all RX/TX buffers. 1216 */ 1217 lge_stop(sc); 1218 lge_reset(sc); 1219 1220 /* Set MAC address */ 1221 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1222 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1223 1224 /* Init circular RX list. */ 1225 if (lge_list_rx_init(sc) == ENOBUFS) { 1226 printf("%s: initialization failed: no " 1227 "memory for rx buffers\n", sc->sc_dv.dv_xname); 1228 lge_stop(sc); 1229 splx(s); 1230 return; 1231 } 1232 1233 /* 1234 * Init tx descriptors. 1235 */ 1236 lge_list_tx_init(sc); 1237 1238 /* Set initial value for MODE1 register. */ 1239 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1240 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1241 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1242 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1243 1244 /* If we want promiscuous mode, set the allframes bit. */ 1245 if (ifp->if_flags & IFF_PROMISC) { 1246 CSR_WRITE_4(sc, LGE_MODE1, 1247 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1248 } else { 1249 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1250 } 1251 1252 /* 1253 * Set the capture broadcast bit to capture broadcast frames. 1254 */ 1255 if (ifp->if_flags & IFF_BROADCAST) { 1256 CSR_WRITE_4(sc, LGE_MODE1, 1257 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1258 } else { 1259 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1260 } 1261 1262 /* Packet padding workaround? */ 1263 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1264 1265 /* No error frames */ 1266 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1267 1268 /* Receive large frames */ 1269 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1270 1271 /* Workaround: disable RX/TX flow control */ 1272 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1273 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1274 1275 /* Make sure to strip CRC from received frames */ 1276 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1277 1278 /* Turn off magic packet mode */ 1279 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1280 1281 /* Turn off all VLAN stuff */ 1282 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1283 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1284 1285 /* Workarond: FIFO overflow */ 1286 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1287 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1288 1289 /* 1290 * Load the multicast filter. 1291 */ 1292 lge_setmulti(sc); 1293 1294 /* 1295 * Enable hardware checksum validation for all received IPv4 1296 * packets, do not reject packets with bad checksums. 1297 */ 1298 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1299 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1300 LGE_MODE2_RX_ERRCSUM); 1301 1302 /* 1303 * Enable the delivery of PHY interrupts based on 1304 * link/speed/duplex status chalges. 1305 */ 1306 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1307 1308 /* Enable receiver and transmitter. */ 1309 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1310 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1311 1312 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1313 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1314 1315 /* 1316 * Enable interrupts. 1317 */ 1318 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1319 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1320 1321 lge_ifmedia_upd(ifp); 1322 1323 ifp->if_flags |= IFF_RUNNING; 1324 ifp->if_flags &= ~IFF_OACTIVE; 1325 1326 splx(s); 1327 1328 timeout_add_sec(&sc->lge_timeout, 1); 1329 } 1330 1331 /* 1332 * Set media options. 1333 */ 1334 int 1335 lge_ifmedia_upd(struct ifnet *ifp) 1336 { 1337 struct lge_softc *sc = ifp->if_softc; 1338 struct mii_data *mii = &sc->lge_mii; 1339 1340 sc->lge_link = 0; 1341 if (mii->mii_instance) { 1342 struct mii_softc *miisc; 1343 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1344 mii_phy_reset(miisc); 1345 } 1346 mii_mediachg(mii); 1347 1348 return (0); 1349 } 1350 1351 /* 1352 * Report current media status. 1353 */ 1354 void 1355 lge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1356 { 1357 struct lge_softc *sc = ifp->if_softc; 1358 struct mii_data *mii = &sc->lge_mii; 1359 1360 mii_pollstat(mii); 1361 ifmr->ifm_active = mii->mii_media_active; 1362 ifmr->ifm_status = mii->mii_media_status; 1363 } 1364 1365 int 1366 lge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1367 { 1368 struct lge_softc *sc = ifp->if_softc; 1369 struct ifaddr *ifa = (struct ifaddr *) data; 1370 struct ifreq *ifr = (struct ifreq *) data; 1371 struct mii_data *mii; 1372 int s, error = 0; 1373 1374 s = splnet(); 1375 1376 switch(command) { 1377 case SIOCSIFADDR: 1378 ifp->if_flags |= IFF_UP; 1379 if (!(ifp->if_flags & IFF_RUNNING)) 1380 lge_init(sc); 1381 #ifdef INET 1382 if (ifa->ifa_addr->sa_family == AF_INET) 1383 arp_ifinit(&sc->arpcom, ifa); 1384 #endif /* INET */ 1385 break; 1386 1387 case SIOCSIFFLAGS: 1388 if (ifp->if_flags & IFF_UP) { 1389 if (ifp->if_flags & IFF_RUNNING && 1390 ifp->if_flags & IFF_PROMISC && 1391 !(sc->lge_if_flags & IFF_PROMISC)) { 1392 CSR_WRITE_4(sc, LGE_MODE1, 1393 LGE_MODE1_SETRST_CTL1| 1394 LGE_MODE1_RX_PROMISC); 1395 lge_setmulti(sc); 1396 } else if (ifp->if_flags & IFF_RUNNING && 1397 !(ifp->if_flags & IFF_PROMISC) && 1398 sc->lge_if_flags & IFF_PROMISC) { 1399 CSR_WRITE_4(sc, LGE_MODE1, 1400 LGE_MODE1_RX_PROMISC); 1401 lge_setmulti(sc); 1402 } else if (ifp->if_flags & IFF_RUNNING && 1403 (ifp->if_flags ^ sc->lge_if_flags) & IFF_ALLMULTI) { 1404 lge_setmulti(sc); 1405 } else { 1406 if (!(ifp->if_flags & IFF_RUNNING)) 1407 lge_init(sc); 1408 } 1409 } else { 1410 if (ifp->if_flags & IFF_RUNNING) 1411 lge_stop(sc); 1412 } 1413 sc->lge_if_flags = ifp->if_flags; 1414 break; 1415 1416 case SIOCGIFMEDIA: 1417 case SIOCSIFMEDIA: 1418 mii = &sc->lge_mii; 1419 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1420 break; 1421 1422 default: 1423 error = ether_ioctl(ifp, &sc->arpcom, command, data); 1424 } 1425 1426 if (error == ENETRESET) { 1427 if (ifp->if_flags & IFF_RUNNING) 1428 lge_setmulti(sc); 1429 error = 0; 1430 } 1431 1432 splx(s); 1433 return (error); 1434 } 1435 1436 void 1437 lge_watchdog(struct ifnet *ifp) 1438 { 1439 struct lge_softc *sc; 1440 1441 sc = ifp->if_softc; 1442 1443 ifp->if_oerrors++; 1444 printf("%s: watchdog timeout\n", sc->sc_dv.dv_xname); 1445 1446 lge_stop(sc); 1447 lge_reset(sc); 1448 lge_init(sc); 1449 1450 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1451 lge_start(ifp); 1452 } 1453 1454 /* 1455 * Stop the adapter and free any mbufs allocated to the 1456 * RX and TX lists. 1457 */ 1458 void 1459 lge_stop(struct lge_softc *sc) 1460 { 1461 int i; 1462 struct ifnet *ifp; 1463 1464 ifp = &sc->arpcom.ac_if; 1465 ifp->if_timer = 0; 1466 timeout_del(&sc->lge_timeout); 1467 1468 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1469 1470 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1471 1472 /* Disable receiver and transmitter. */ 1473 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1474 sc->lge_link = 0; 1475 1476 /* 1477 * Free data in the RX lists. 1478 */ 1479 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1480 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1481 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1482 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1483 } 1484 } 1485 bzero((char *)&sc->lge_ldata->lge_rx_list, 1486 sizeof(sc->lge_ldata->lge_rx_list)); 1487 1488 /* 1489 * Free the TX list buffers. 1490 */ 1491 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1492 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1493 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1494 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1495 } 1496 } 1497 1498 bzero((char *)&sc->lge_ldata->lge_tx_list, 1499 sizeof(sc->lge_ldata->lge_tx_list)); 1500 } 1501 1502 /* 1503 * Stop all chip I/O so that the kernel's probe routines don't 1504 * get confused by errant DMAs when rebooting. 1505 */ 1506 void 1507 lge_shutdown(void *xsc) 1508 { 1509 struct lge_softc *sc = (struct lge_softc *)xsc; 1510 1511 lge_reset(sc); 1512 lge_stop(sc); 1513 } 1514