1 /* $OpenBSD: if_lge.c,v 1.13 2003/10/06 06:43:12 david Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 5 * Bill Paul <william.paul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.6 2001/06/20 19:47:55 bmilekic Exp $ 35 */ 36 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * Written by Bill Paul <william.paul@windriver.com> 42 * Wind River Systems 43 */ 44 45 /* 46 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 47 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 48 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 49 * are three supported methods for data transfer between host and 50 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 51 * Propulsion Technology (tm) DMA. The latter mechanism is a form 52 * of double buffer DMA where the packet data is copied to a 53 * pre-allocated DMA buffer who's physical address has been loaded 54 * into a table at device initialization time. The rationale is that 55 * the virtual to physical address translation needed for normal 56 * scatter/gather DMA is more expensive than the data copy needed 57 * for double buffering. This may be true in Windows NT and the like, 58 * but it isn't true for us, at least on the x86 arch. This driver 59 * uses the scatter/gather I/O method for both TX and RX. 60 * 61 * The LXT1001 only supports TCP/IP checksum offload on receive. 62 * Also, the VLAN tagging is done using a 16-entry table which allows 63 * the chip to perform hardware filtering based on VLAN tags. Sadly, 64 * our vlan support doesn't currently play well with this kind of 65 * hardware support. 66 * 67 * Special thanks to: 68 * - Jeff James at Intel, for arranging to have the LXT1001 manual 69 * released (at long last) 70 * - Beny Chen at D-Link, for actually sending it to me 71 * - Brad Short and Keith Alexis at SMC, for sending me sample 72 * SMC9462SX and SMC9462TX adapters for testing 73 * - Paul Saab at Y!, for not killing me (though it remains to be seen 74 * if in fact he did me much of a favor) 75 */ 76 77 #include "bpfilter.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/sockio.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/device.h> 86 #include <sys/socket.h> 87 88 #include <net/if.h> 89 #include <net/if_dl.h> 90 #include <net/if_media.h> 91 92 #ifdef INET 93 #include <netinet/in.h> 94 #include <netinet/in_systm.h> 95 #include <netinet/in_var.h> 96 #include <netinet/ip.h> 97 #include <netinet/if_ether.h> 98 #endif 99 100 #if NVLAN > 0 101 #include <net/if_types.h> 102 #include <net/if_vlan_var.h> 103 #endif 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <uvm/uvm_extern.h> /* for vtophys */ 110 #include <uvm/uvm_pmap.h> /* for vtophys */ 111 112 #include <dev/pci/pcireg.h> 113 #include <dev/pci/pcivar.h> 114 #include <dev/pci/pcidevs.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 119 #define LGE_USEIOSPACE 120 121 #include <dev/pci/if_lgereg.h> 122 123 int lge_probe(struct device *, void *, void *); 124 void lge_attach(struct device *, struct device *, void *); 125 126 int lge_alloc_jumbo_mem(struct lge_softc *); 127 void lge_free_jumbo_mem(struct lge_softc *); 128 void *lge_jalloc(struct lge_softc *); 129 void lge_jfree(caddr_t, u_int, void *); 130 131 int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, 132 struct mbuf *); 133 int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 134 void lge_rxeof(struct lge_softc *, int); 135 void lge_rxeoc(struct lge_softc *); 136 void lge_txeof(struct lge_softc *); 137 int lge_intr(void *); 138 void lge_tick(void *); 139 void lge_start(struct ifnet *); 140 int lge_ioctl(struct ifnet *, u_long, caddr_t); 141 void lge_init(void *); 142 void lge_stop(struct lge_softc *); 143 void lge_watchdog(struct ifnet *); 144 void lge_shutdown(void *); 145 int lge_ifmedia_upd(struct ifnet *); 146 void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 147 148 void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 149 void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 150 151 int lge_miibus_readreg(struct device *, int, int); 152 void lge_miibus_writereg(struct device *, int, int, int); 153 void lge_miibus_statchg(struct device *); 154 155 void lge_setmulti(struct lge_softc *); 156 u_int32_t lge_crc(struct lge_softc *, caddr_t); 157 void lge_reset(struct lge_softc *); 158 int lge_list_rx_init(struct lge_softc *); 159 int lge_list_tx_init(struct lge_softc *); 160 161 #ifdef LGE_USEIOSPACE 162 #define LGE_RES SYS_RES_IOPORT 163 #define LGE_RID LGE_PCI_LOIO 164 #else 165 #define LGE_RES SYS_RES_MEMORY 166 #define LGE_RID LGE_PCI_LOMEM 167 #endif 168 169 #ifdef LGE_DEBUG 170 #define DPRINTF(x) if (lgedebug) printf x 171 #define DPRINTFN(n,x) if (lgedebug >= (n)) printf x 172 int lgedebug = 0; 173 #else 174 #define DPRINTF(x) 175 #define DPRINTFN(n,x) 176 #endif 177 178 #define LGE_SETBIT(sc, reg, x) \ 179 CSR_WRITE_4(sc, reg, \ 180 CSR_READ_4(sc, reg) | (x)) 181 182 #define LGE_CLRBIT(sc, reg, x) \ 183 CSR_WRITE_4(sc, reg, \ 184 CSR_READ_4(sc, reg) & ~(x)) 185 186 #define SIO_SET(x) \ 187 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 188 189 #define SIO_CLR(x) \ 190 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 191 192 /* 193 * Read a word of data stored in the EEPROM at address 'addr.' 194 */ 195 void lge_eeprom_getword(sc, addr, dest) 196 struct lge_softc *sc; 197 int addr; 198 u_int16_t *dest; 199 { 200 register int i; 201 u_int32_t val; 202 203 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 204 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 205 206 for (i = 0; i < LGE_TIMEOUT; i++) 207 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 208 break; 209 210 if (i == LGE_TIMEOUT) { 211 printf("%s: EEPROM read timed out\n", sc->sc_dv.dv_xname); 212 return; 213 } 214 215 val = CSR_READ_4(sc, LGE_EEDATA); 216 217 if (addr & 1) 218 *dest = (val >> 16) & 0xFFFF; 219 else 220 *dest = val & 0xFFFF; 221 222 return; 223 } 224 225 /* 226 * Read a sequence of words from the EEPROM. 227 */ 228 void lge_read_eeprom(sc, dest, off, cnt, swap) 229 struct lge_softc *sc; 230 caddr_t dest; 231 int off; 232 int cnt; 233 int swap; 234 { 235 int i; 236 u_int16_t word = 0, *ptr; 237 238 for (i = 0; i < cnt; i++) { 239 lge_eeprom_getword(sc, off + i, &word); 240 ptr = (u_int16_t *)(dest + (i * 2)); 241 if (swap) 242 *ptr = ntohs(word); 243 else 244 *ptr = word; 245 } 246 247 return; 248 } 249 250 int lge_miibus_readreg(dev, phy, reg) 251 struct device * dev; 252 int phy, reg; 253 { 254 struct lge_softc *sc = (struct lge_softc *)dev; 255 int i; 256 257 /* 258 * If we have a non-PCS PHY, pretend that the internal 259 * autoneg stuff at PHY address 0 isn't there so that 260 * the miibus code will find only the GMII PHY. 261 */ 262 if (sc->lge_pcs == 0 && phy == 0) 263 return(0); 264 265 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 266 267 for (i = 0; i < LGE_TIMEOUT; i++) 268 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 269 break; 270 271 if (i == LGE_TIMEOUT) { 272 printf("%s: PHY read timed out\n", sc->sc_dv.dv_xname); 273 return(0); 274 } 275 276 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 277 } 278 279 void lge_miibus_writereg(dev, phy, reg, data) 280 struct device * dev; 281 int phy, reg, data; 282 { 283 struct lge_softc *sc = (struct lge_softc *)dev; 284 int i; 285 286 CSR_WRITE_4(sc, LGE_GMIICTL, 287 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 288 289 for (i = 0; i < LGE_TIMEOUT; i++) 290 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 291 break; 292 293 if (i == LGE_TIMEOUT) { 294 printf("%s: PHY write timed out\n", sc->sc_dv.dv_xname); 295 } 296 } 297 298 void lge_miibus_statchg(dev) 299 struct device * dev; 300 { 301 struct lge_softc *sc = (struct lge_softc *)dev; 302 struct mii_data *mii = &sc->lge_mii; 303 304 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 305 switch (IFM_SUBTYPE(mii->mii_media_active)) { 306 case IFM_1000_T: 307 case IFM_1000_SX: 308 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 309 break; 310 case IFM_100_TX: 311 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 312 break; 313 case IFM_10_T: 314 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 315 break; 316 default: 317 /* 318 * Choose something, even if it's wrong. Clearing 319 * all the bits will hose autoneg on the internal 320 * PHY. 321 */ 322 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 323 break; 324 } 325 326 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 327 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 328 } else { 329 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 330 } 331 332 return; 333 } 334 335 u_int32_t lge_crc(sc, addr) 336 struct lge_softc *sc; 337 caddr_t addr; 338 { 339 u_int32_t crc, carry; 340 int i, j; 341 u_int8_t c; 342 343 /* Compute CRC for the address value. */ 344 crc = 0xFFFFFFFF; /* initial value */ 345 346 for (i = 0; i < 6; i++) { 347 c = *(addr + i); 348 for (j = 0; j < 8; j++) { 349 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 350 crc <<= 1; 351 c >>= 1; 352 if (carry) 353 crc = (crc ^ 0x04c11db6) | carry; 354 } 355 } 356 357 /* 358 * return the filter bit position 359 */ 360 return((crc >> 26) & 0x0000003F); 361 } 362 363 void lge_setmulti(sc) 364 struct lge_softc *sc; 365 { 366 struct arpcom *ac = &sc->arpcom; 367 struct ifnet *ifp = &ac->ac_if; 368 struct ether_multi *enm; 369 struct ether_multistep step; 370 u_int32_t h = 0, hashes[2] = { 0, 0 }; 371 372 /* Make sure multicast hash table is enabled. */ 373 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 374 375 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 376 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 377 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 378 return; 379 } 380 381 /* first, zot all the existing hash bits */ 382 CSR_WRITE_4(sc, LGE_MAR0, 0); 383 CSR_WRITE_4(sc, LGE_MAR1, 0); 384 385 /* now program new ones */ 386 ETHER_FIRST_MULTI(step, ac, enm); 387 while (enm != NULL) { 388 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) 389 continue; 390 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)enm->enm_addrlo)); 391 if (h < 32) 392 hashes[0] |= (1 << h); 393 else 394 hashes[1] |= (1 << (h - 32)); 395 ETHER_NEXT_MULTI(step, enm); 396 } 397 398 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 399 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 400 401 return; 402 } 403 404 void lge_reset(sc) 405 struct lge_softc *sc; 406 { 407 register int i; 408 409 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 410 411 for (i = 0; i < LGE_TIMEOUT; i++) { 412 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 413 break; 414 } 415 416 if (i == LGE_TIMEOUT) 417 printf("%s: reset never completed\n", sc->sc_dv.dv_xname); 418 419 /* Wait a little while for the chip to get its brains in order. */ 420 DELAY(1000); 421 422 return; 423 } 424 425 /* 426 * Probe for a Level 1 chip. Check the PCI vendor and device 427 * IDs against our list and return a device name if we find a match. 428 */ 429 int lge_probe(parent, match, aux) 430 struct device *parent; 431 void *match; 432 void *aux; 433 { 434 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 435 436 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LEVEL1 && 437 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LEVEL1_LXT1001) 438 return (1); 439 440 return (0); 441 } 442 443 /* 444 * Attach the interface. Allocate softc structures, do ifmedia 445 * setup and ethernet/BPF attach. 446 */ 447 void lge_attach(parent, self, aux) 448 struct device *parent, *self; 449 void *aux; 450 { 451 struct lge_softc *sc = (struct lge_softc *)self; 452 struct pci_attach_args *pa = aux; 453 pci_chipset_tag_t pc = pa->pa_pc; 454 pci_intr_handle_t ih; 455 const char *intrstr = NULL; 456 bus_addr_t iobase; 457 bus_size_t iosize; 458 bus_dma_segment_t seg; 459 bus_dmamap_t dmamap; 460 int s, rseg; 461 u_char eaddr[ETHER_ADDR_LEN]; 462 u_int32_t command; 463 struct ifnet *ifp; 464 int error = 0; 465 caddr_t kva; 466 467 s = splimp(); 468 469 bzero(sc, sizeof(struct lge_softc)); 470 471 /* 472 * Handle power management nonsense. 473 */ 474 DPRINTFN(5, ("Preparing for conf read\n")); 475 command = pci_conf_read(pc, pa->pa_tag, LGE_PCI_CAPID) & 0x000000FF; 476 if (command == 0x01) { 477 command = pci_conf_read(pc, pa->pa_tag, LGE_PCI_PWRMGMTCTRL); 478 if (command & LGE_PSTATE_MASK) { 479 u_int32_t iobase, membase, irq; 480 481 /* Save important PCI config data. */ 482 iobase = pci_conf_read(pc, pa->pa_tag, LGE_PCI_LOIO); 483 membase = pci_conf_read(pc, pa->pa_tag, LGE_PCI_LOMEM); 484 irq = pci_conf_read(pc, pa->pa_tag, LGE_PCI_INTLINE); 485 486 /* Reset the power state. */ 487 printf("%s: chip is in D%d power mode " 488 "-- setting to D0\n", sc->sc_dv.dv_xname, 489 command & LGE_PSTATE_MASK); 490 command &= 0xFFFFFFFC; 491 pci_conf_write(pc, pa->pa_tag, 492 LGE_PCI_PWRMGMTCTRL, command); 493 494 /* Restore PCI config data. */ 495 pci_conf_write(pc, pa->pa_tag, LGE_PCI_LOIO, iobase); 496 pci_conf_write(pc, pa->pa_tag, LGE_PCI_LOMEM, membase); 497 pci_conf_write(pc, pa->pa_tag, LGE_PCI_INTLINE, irq); 498 } 499 } 500 501 /* 502 * Map control/status registers. 503 */ 504 DPRINTFN(5, ("Map control/status regs\n")); 505 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 506 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 507 PCI_COMMAND_MASTER_ENABLE; 508 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 509 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 510 511 #ifdef LGE_USEIOSPACE 512 if (!(command & PCI_COMMAND_IO_ENABLE)) { 513 printf("%s: failed to enable I/O ports!\n", 514 sc->sc_dv.dv_xname); 515 error = ENXIO; 516 goto fail; 517 } 518 /* 519 * Map control/status registers. 520 */ 521 DPRINTFN(5, ("pci_io_find\n")); 522 if (pci_io_find(pc, pa->pa_tag, LGE_PCI_LOIO, &iobase, &iosize)) { 523 printf(": can't find i/o space\n"); 524 goto fail; 525 } 526 DPRINTFN(5, ("bus_space_map\n")); 527 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->lge_bhandle)) { 528 printf(": can't map i/o space\n"); 529 goto fail; 530 } 531 sc->lge_btag = pa->pa_iot; 532 #else 533 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 534 printf("%s: failed to enable memory mapping!\n", 535 sc->sc_dv.dv_xname); 536 error = ENXIO; 537 goto fail; 538 } 539 DPRINTFN(5, ("pci_mem_find\n")); 540 if (pci_mem_find(pc, pa->pa_tag, LGE_PCI_LOMEM, &iobase, 541 &iosize, NULL)) { 542 printf(": can't find mem space\n"); 543 goto fail; 544 } 545 DPRINTFN(5, ("bus_space_map\n")); 546 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->lge_bhandle)) { 547 printf(": can't map mem space\n"); 548 goto fail; 549 } 550 551 sc->lge_btag = pa->pa_memt; 552 #endif 553 554 DPRINTFN(5, ("pci_intr_map\n")); 555 if (pci_intr_map(pa, &ih)) { 556 printf(": couldn't map interrupt\n"); 557 goto fail; 558 } 559 560 DPRINTFN(5, ("pci_intr_string\n")); 561 intrstr = pci_intr_string(pc, ih); 562 DPRINTFN(5, ("pci_intr_establish\n")); 563 sc->lge_intrhand = pci_intr_establish(pc, ih, IPL_NET, lge_intr, sc, 564 sc->sc_dv.dv_xname); 565 if (sc->lge_intrhand == NULL) { 566 printf(": couldn't establish interrupt"); 567 if (intrstr != NULL) 568 printf(" at %s", intrstr); 569 printf("\n"); 570 goto fail; 571 } 572 printf(": %s", intrstr); 573 574 /* Reset the adapter. */ 575 DPRINTFN(5, ("lge_reset\n")); 576 lge_reset(sc); 577 578 /* 579 * Get station address from the EEPROM. 580 */ 581 DPRINTFN(5, ("lge_read_eeprom\n")); 582 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 583 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 584 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 585 586 /* 587 * A Level 1 chip was detected. Inform the world. 588 */ 589 printf(": address: %s\n", ether_sprintf(eaddr)); 590 591 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 592 593 sc->sc_dmatag = pa->pa_dmat; 594 DPRINTFN(5, ("bus_dmamem_alloc\n")); 595 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct lge_list_data), 596 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 597 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 598 goto fail; 599 } 600 DPRINTFN(5, ("bus_dmamem_map\n")); 601 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 602 sizeof(struct lge_list_data), &kva, 603 BUS_DMA_NOWAIT)) { 604 printf("%s: can't map dma buffers (%d bytes)\n", 605 sc->sc_dv.dv_xname, sizeof(struct lge_list_data)); 606 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 607 goto fail; 608 } 609 DPRINTFN(5, ("bus_dmamem_create\n")); 610 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct lge_list_data), 1, 611 sizeof(struct lge_list_data), 0, 612 BUS_DMA_NOWAIT, &dmamap)) { 613 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 614 bus_dmamem_unmap(sc->sc_dmatag, kva, 615 sizeof(struct lge_list_data)); 616 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 617 goto fail; 618 } 619 DPRINTFN(5, ("bus_dmamem_load\n")); 620 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, 621 sizeof(struct lge_list_data), NULL, 622 BUS_DMA_NOWAIT)) { 623 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 624 bus_dmamem_unmap(sc->sc_dmatag, kva, 625 sizeof(struct lge_list_data)); 626 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 627 goto fail; 628 } 629 630 DPRINTFN(5, ("bzero\n")); 631 sc->lge_ldata = (struct lge_list_data *)kva; 632 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 633 634 /* Try to allocate memory for jumbo buffers. */ 635 DPRINTFN(5, ("lge_alloc_jumbo_mem\n")); 636 if (lge_alloc_jumbo_mem(sc)) { 637 printf("%s: jumbo buffer allocation failed\n", 638 sc->sc_dv.dv_xname); 639 goto fail; 640 } 641 642 ifp = &sc->arpcom.ac_if; 643 ifp->if_softc = sc; 644 ifp->if_mtu = ETHERMTU; 645 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 646 ifp->if_ioctl = lge_ioctl; 647 ifp->if_output = ether_output; 648 ifp->if_start = lge_start; 649 ifp->if_watchdog = lge_watchdog; 650 ifp->if_baudrate = 1000000000; 651 IFQ_SET_MAXLEN(&ifp->if_snd, LGE_TX_LIST_CNT - 1); 652 IFQ_SET_READY(&ifp->if_snd); 653 DPRINTFN(5, ("bcopy\n")); 654 bcopy(sc->sc_dv.dv_xname, ifp->if_xname, IFNAMSIZ); 655 656 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 657 sc->lge_pcs = 1; 658 else 659 sc->lge_pcs = 0; 660 661 /* 662 * Do MII setup. 663 */ 664 DPRINTFN(5, ("mii setup\n")); 665 sc->lge_mii.mii_ifp = ifp; 666 sc->lge_mii.mii_readreg = lge_miibus_readreg; 667 sc->lge_mii.mii_writereg = lge_miibus_writereg; 668 sc->lge_mii.mii_statchg = lge_miibus_statchg; 669 ifmedia_init(&sc->lge_mii.mii_media, 0, lge_ifmedia_upd, 670 lge_ifmedia_sts); 671 mii_attach(&sc->sc_dv, &sc->lge_mii, 0xffffffff, MII_PHY_ANY, 672 MII_OFFSET_ANY, 0); 673 674 if (LIST_FIRST(&sc->lge_mii.mii_phys) == NULL) { 675 printf("%s: no PHY found!\n", sc->sc_dv.dv_xname); 676 ifmedia_add(&sc->lge_mii.mii_media, IFM_ETHER|IFM_MANUAL, 677 0, NULL); 678 ifmedia_set(&sc->lge_mii.mii_media, IFM_ETHER|IFM_MANUAL); 679 } 680 else 681 ifmedia_set(&sc->lge_mii.mii_media, IFM_ETHER|IFM_AUTO); 682 683 /* 684 * Call MI attach routine. 685 */ 686 DPRINTFN(5, ("if_attach\n")); 687 if_attach(ifp); 688 DPRINTFN(5, ("ether_ifattach\n")); 689 ether_ifattach(ifp); 690 DPRINTFN(5, ("timeout_set\n")); 691 timeout_set(&sc->lge_timeout, lge_tick, sc); 692 timeout_add(&sc->lge_timeout, hz); 693 694 fail: 695 splx(s); 696 } 697 698 /* 699 * Initialize the transmit descriptors. 700 */ 701 int lge_list_tx_init(sc) 702 struct lge_softc *sc; 703 { 704 struct lge_list_data *ld; 705 struct lge_ring_data *cd; 706 int i; 707 708 cd = &sc->lge_cdata; 709 ld = sc->lge_ldata; 710 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 711 ld->lge_tx_list[i].lge_mbuf = NULL; 712 ld->lge_tx_list[i].lge_ctl = 0; 713 } 714 715 cd->lge_tx_prod = cd->lge_tx_cons = 0; 716 717 return(0); 718 } 719 720 721 /* 722 * Initialize the RX descriptors and allocate mbufs for them. Note that 723 * we arralge the descriptors in a closed ring, so that the last descriptor 724 * points back to the first. 725 */ 726 int lge_list_rx_init(sc) 727 struct lge_softc *sc; 728 { 729 struct lge_list_data *ld; 730 struct lge_ring_data *cd; 731 int i; 732 733 ld = sc->lge_ldata; 734 cd = &sc->lge_cdata; 735 736 cd->lge_rx_prod = cd->lge_rx_cons = 0; 737 738 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 739 740 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 741 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 742 break; 743 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 744 return(ENOBUFS); 745 } 746 747 /* Clear possible 'rx command queue empty' interrupt. */ 748 CSR_READ_4(sc, LGE_ISR); 749 750 return(0); 751 } 752 753 /* 754 * Initialize an RX descriptor and attach an MBUF cluster. 755 */ 756 int lge_newbuf(sc, c, m) 757 struct lge_softc *sc; 758 struct lge_rx_desc *c; 759 struct mbuf *m; 760 { 761 struct mbuf *m_new = NULL; 762 caddr_t *buf = NULL; 763 764 if (m == NULL) { 765 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 766 if (m_new == NULL) { 767 printf("%s: no memory for rx list " 768 "-- packet dropped!\n", sc->sc_dv.dv_xname); 769 return(ENOBUFS); 770 } 771 772 /* Allocate the jumbo buffer */ 773 buf = lge_jalloc(sc); 774 if (buf == NULL) { 775 #ifdef LGE_VERBOSE 776 printf("%s: jumbo allocation failed " 777 "-- packet dropped!\n", sc->sc_dv.dv_xname); 778 #endif 779 m_freem(m_new); 780 return(ENOBUFS); 781 } 782 /* Attach the buffer to the mbuf */ 783 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 784 m_new->m_flags |= M_EXT; 785 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 786 m_new->m_len = LGE_JLEN; 787 m_new->m_ext.ext_free = lge_jfree; 788 m_new->m_ext.ext_arg = sc; 789 MCLINITREFERENCE(m_new); 790 } else { 791 m_new = m; 792 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 793 m_new->m_data = m_new->m_ext.ext_buf; 794 } 795 796 /* 797 * Adjust alignment so packet payload begins on a 798 * longword boundary. Mandatory for Alpha, useful on 799 * x86 too. 800 */ 801 m_adj(m_new, ETHER_ALIGN); 802 803 c->lge_mbuf = m_new; 804 c->lge_fragptr_hi = 0; 805 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 806 c->lge_fraglen = m_new->m_len; 807 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 808 c->lge_sts = 0; 809 810 /* 811 * Put this buffer in the RX command FIFO. To do this, 812 * we just write the physical address of the descriptor 813 * into the RX descriptor address registers. Note that 814 * there are two registers, one high DWORD and one low 815 * DWORD, which lets us specify a 64-bit address if 816 * desired. We only use a 32-bit address for now. 817 * Writing to the low DWORD register is what actually 818 * causes the command to be issued, so we do that 819 * last. 820 */ 821 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 822 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 823 824 return(0); 825 } 826 827 int lge_alloc_jumbo_mem(sc) 828 struct lge_softc *sc; 829 { 830 caddr_t ptr, kva; 831 bus_dma_segment_t seg; 832 bus_dmamap_t dmamap; 833 int i, rseg; 834 struct lge_jpool_entry *entry; 835 836 /* Grab a big chunk o' storage. */ 837 if (bus_dmamem_alloc(sc->sc_dmatag, LGE_JMEM, PAGE_SIZE, 0, 838 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 839 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 840 return (ENOBUFS); 841 } 842 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, LGE_JMEM, &kva, 843 BUS_DMA_NOWAIT)) { 844 printf("%s: can't map dma buffers (%d bytes)\n", 845 sc->sc_dv.dv_xname, LGE_JMEM); 846 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 847 return (ENOBUFS); 848 } 849 if (bus_dmamap_create(sc->sc_dmatag, LGE_JMEM, 1, 850 LGE_JMEM, 0, BUS_DMA_NOWAIT, &dmamap)) { 851 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 852 bus_dmamem_unmap(sc->sc_dmatag, kva, LGE_JMEM); 853 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 854 return (ENOBUFS); 855 } 856 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, LGE_JMEM, 857 NULL, BUS_DMA_NOWAIT)) { 858 printf("%s: can't load dma map\n", sc->sc_dv.dv_xname); 859 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 860 bus_dmamem_unmap(sc->sc_dmatag, kva, LGE_JMEM); 861 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 862 return (ENOBUFS); 863 } 864 sc->lge_cdata.lge_jumbo_buf = (caddr_t)kva; 865 DPRINTFN(1,("lge_jumbo_buf = 0x%08X\n", sc->lge_cdata.lge_jumbo_buf)); 866 DPRINTFN(1,("LGE_JLEN = 0x%08X\n", LGE_JLEN)); 867 868 LIST_INIT(&sc->lge_jfree_listhead); 869 LIST_INIT(&sc->lge_jinuse_listhead); 870 871 /* 872 * Now divide it up into 9K pieces and save the addresses 873 * in an array. 874 */ 875 ptr = sc->lge_cdata.lge_jumbo_buf; 876 for (i = 0; i < LGE_JSLOTS; i++) { 877 sc->lge_cdata.lge_jslots[i] = ptr; 878 ptr += LGE_JLEN; 879 entry = malloc(sizeof(struct lge_jpool_entry), 880 M_DEVBUF, M_NOWAIT); 881 if (entry == NULL) { 882 bus_dmamap_unload(sc->sc_dmatag, dmamap); 883 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 884 bus_dmamem_unmap(sc->sc_dmatag, kva, LGE_JMEM); 885 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 886 sc->lge_cdata.lge_jumbo_buf = NULL; 887 printf("%s: no memory for jumbo buffer queue!\n", 888 sc->sc_dv.dv_xname); 889 return(ENOBUFS); 890 } 891 entry->slot = i; 892 LIST_INSERT_HEAD(&sc->lge_jfree_listhead, 893 entry, jpool_entries); 894 } 895 896 return(0); 897 } 898 899 /* 900 * Allocate a jumbo buffer. 901 */ 902 void *lge_jalloc(sc) 903 struct lge_softc *sc; 904 { 905 struct lge_jpool_entry *entry; 906 907 entry = LIST_FIRST(&sc->lge_jfree_listhead); 908 909 if (entry == NULL) { 910 #ifdef LGE_VERBOSE 911 printf("%s: no free jumbo buffers\n", sc->sc_dv.dv_xname); 912 #endif 913 return(NULL); 914 } 915 916 LIST_REMOVE(entry, jpool_entries); 917 LIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 918 return(sc->lge_cdata.lge_jslots[entry->slot]); 919 } 920 921 /* 922 * Release a jumbo buffer. 923 */ 924 void lge_jfree(buf, size, arg) 925 caddr_t buf; 926 u_int size; 927 void *arg; 928 { 929 struct lge_softc *sc; 930 int i; 931 struct lge_jpool_entry *entry; 932 933 /* Extract the softc struct pointer. */ 934 sc = (struct lge_softc *)arg; 935 936 if (sc == NULL) 937 panic("lge_jfree: can't find softc pointer!"); 938 939 /* calculate the slot this buffer belongs to */ 940 i = ((vaddr_t)buf - (vaddr_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 941 942 if ((i < 0) || (i >= LGE_JSLOTS)) 943 panic("lge_jfree: asked to free buffer that we don't manage!"); 944 945 entry = LIST_FIRST(&sc->lge_jinuse_listhead); 946 if (entry == NULL) 947 panic("lge_jfree: buffer not in use!"); 948 entry->slot = i; 949 LIST_REMOVE(entry, jpool_entries); 950 LIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 951 952 return; 953 } 954 955 /* 956 * A frame has been uploaded: pass the resulting mbuf chain up to 957 * the higher level protocols. 958 */ 959 void lge_rxeof(sc, cnt) 960 struct lge_softc *sc; 961 int cnt; 962 { 963 struct mbuf *m; 964 struct ifnet *ifp; 965 struct lge_rx_desc *cur_rx; 966 int c, i, total_len = 0; 967 u_int32_t rxsts, rxctl; 968 969 ifp = &sc->arpcom.ac_if; 970 971 /* Find out how many frames were processed. */ 972 c = cnt; 973 i = sc->lge_cdata.lge_rx_cons; 974 975 /* Suck them in. */ 976 while(c) { 977 struct mbuf *m0 = NULL; 978 979 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 980 rxctl = cur_rx->lge_ctl; 981 rxsts = cur_rx->lge_sts; 982 m = cur_rx->lge_mbuf; 983 cur_rx->lge_mbuf = NULL; 984 total_len = LGE_RXBYTES(cur_rx); 985 LGE_INC(i, LGE_RX_LIST_CNT); 986 c--; 987 988 /* 989 * If an error occurs, update stats, clear the 990 * status word and leave the mbuf cluster in place: 991 * it should simply get re-used next time this descriptor 992 * comes up in the ring. 993 */ 994 if (rxctl & LGE_RXCTL_ERRMASK) { 995 ifp->if_ierrors++; 996 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 997 continue; 998 } 999 1000 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 1001 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 1002 ifp, NULL); 1003 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 1004 if (m0 == NULL) { 1005 printf("%s: no receive buffers " 1006 "available -- packet dropped!\n", 1007 sc->sc_dv.dv_xname); 1008 ifp->if_ierrors++; 1009 continue; 1010 } 1011 m = m0; 1012 } else { 1013 m->m_pkthdr.rcvif = ifp; 1014 m->m_pkthdr.len = m->m_len = total_len; 1015 } 1016 1017 ifp->if_ipackets++; 1018 1019 #if NBPFILTER > 0 1020 /* 1021 * Handle BPF listeners. Let the BPF user see the packet. 1022 */ 1023 if (ifp->if_bpf) 1024 bpf_mtap(ifp->if_bpf, m); 1025 #endif 1026 1027 /* Do IP checksum checking. */ 1028 #if 0 1029 if (rxsts & LGE_RXSTS_ISIP) 1030 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1031 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 1032 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1033 if ((rxsts & LGE_RXSTS_ISTCP && 1034 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 1035 (rxsts & LGE_RXSTS_ISUDP && 1036 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 1037 m->m_pkthdr.csum_flags |= 1038 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1039 m->m_pkthdr.csum_data = 0xffff; 1040 } 1041 #endif 1042 1043 if (rxsts & LGE_RXSTS_ISIP) { 1044 if (rxsts & LGE_RXSTS_IPCSUMERR) 1045 m->m_pkthdr.csum |= M_IPV4_CSUM_IN_BAD; 1046 else 1047 m->m_pkthdr.csum |= M_IPV4_CSUM_IN_OK; 1048 } 1049 if (rxsts & LGE_RXSTS_ISTCP) { 1050 if (rxsts & LGE_RXSTS_TCPCSUMERR) 1051 m->m_pkthdr.csum |= M_TCP_CSUM_IN_BAD; 1052 else 1053 m->m_pkthdr.csum |= M_TCP_CSUM_IN_OK; 1054 } 1055 if (rxsts & LGE_RXSTS_ISUDP) { 1056 if (rxsts & LGE_RXSTS_UDPCSUMERR) 1057 m->m_pkthdr.csum |= M_UDP_CSUM_IN_BAD; 1058 else 1059 m->m_pkthdr.csum |= M_UDP_CSUM_IN_OK; 1060 } 1061 1062 ether_input_mbuf(ifp, m); 1063 } 1064 1065 sc->lge_cdata.lge_rx_cons = i; 1066 1067 return; 1068 } 1069 1070 void lge_rxeoc(sc) 1071 struct lge_softc *sc; 1072 { 1073 struct ifnet *ifp; 1074 1075 ifp = &sc->arpcom.ac_if; 1076 ifp->if_flags &= ~IFF_RUNNING; 1077 lge_init(sc); 1078 return; 1079 } 1080 1081 /* 1082 * A frame was downloaded to the chip. It's safe for us to clean up 1083 * the list buffers. 1084 */ 1085 1086 void lge_txeof(sc) 1087 struct lge_softc *sc; 1088 { 1089 struct lge_tx_desc *cur_tx = NULL; 1090 struct ifnet *ifp; 1091 u_int32_t idx, txdone; 1092 1093 ifp = &sc->arpcom.ac_if; 1094 1095 /* Clear the timeout timer. */ 1096 ifp->if_timer = 0; 1097 1098 /* 1099 * Go through our tx list and free mbufs for those 1100 * frames that have been transmitted. 1101 */ 1102 idx = sc->lge_cdata.lge_tx_cons; 1103 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1104 1105 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1106 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1107 1108 ifp->if_opackets++; 1109 if (cur_tx->lge_mbuf != NULL) { 1110 m_freem(cur_tx->lge_mbuf); 1111 cur_tx->lge_mbuf = NULL; 1112 } 1113 cur_tx->lge_ctl = 0; 1114 1115 txdone--; 1116 LGE_INC(idx, LGE_TX_LIST_CNT); 1117 ifp->if_timer = 0; 1118 } 1119 1120 sc->lge_cdata.lge_tx_cons = idx; 1121 1122 if (cur_tx != NULL) 1123 ifp->if_flags &= ~IFF_OACTIVE; 1124 1125 return; 1126 } 1127 1128 void lge_tick(xsc) 1129 void *xsc; 1130 { 1131 struct lge_softc *sc = xsc; 1132 struct mii_data *mii = &sc->lge_mii; 1133 struct ifnet *ifp = &sc->arpcom.ac_if; 1134 int s; 1135 1136 s = splimp(); 1137 1138 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1139 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1140 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1141 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1142 1143 if (!sc->lge_link) { 1144 mii_tick(mii); 1145 mii_pollstat(mii); 1146 if (mii->mii_media_status & IFM_ACTIVE && 1147 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1148 sc->lge_link++; 1149 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1150 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1151 printf("%s: gigabit link up\n", 1152 sc->sc_dv.dv_xname); 1153 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1154 lge_start(ifp); 1155 } 1156 } 1157 1158 timeout_add(&sc->lge_timeout, hz); 1159 1160 splx(s); 1161 1162 return; 1163 } 1164 1165 int lge_intr(arg) 1166 void *arg; 1167 { 1168 struct lge_softc *sc; 1169 struct ifnet *ifp; 1170 u_int32_t status; 1171 int claimed = 0; 1172 1173 sc = arg; 1174 ifp = &sc->arpcom.ac_if; 1175 1176 /* Supress unwanted interrupts */ 1177 if (!(ifp->if_flags & IFF_UP)) { 1178 lge_stop(sc); 1179 return (0); 1180 } 1181 1182 for (;;) { 1183 /* 1184 * Reading the ISR register clears all interrupts, and 1185 * clears the 'interrupts enabled' bit in the IMR 1186 * register. 1187 */ 1188 status = CSR_READ_4(sc, LGE_ISR); 1189 1190 if ((status & LGE_INTRS) == 0) 1191 break; 1192 1193 claimed = 1; 1194 1195 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1196 lge_txeof(sc); 1197 1198 if (status & LGE_ISR_RXDMA_DONE) 1199 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1200 1201 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1202 lge_rxeoc(sc); 1203 1204 if (status & LGE_ISR_PHY_INTR) { 1205 sc->lge_link = 0; 1206 timeout_del(&sc->lge_timeout); 1207 lge_tick(sc); 1208 } 1209 } 1210 1211 /* Re-enable interrupts. */ 1212 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1213 1214 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1215 lge_start(ifp); 1216 1217 return claimed; 1218 } 1219 1220 /* 1221 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1222 * pointers to the fragment pointers. 1223 */ 1224 int lge_encap(sc, m_head, txidx) 1225 struct lge_softc *sc; 1226 struct mbuf *m_head; 1227 u_int32_t *txidx; 1228 { 1229 struct lge_frag *f = NULL; 1230 struct lge_tx_desc *cur_tx; 1231 struct mbuf *m; 1232 int frag = 0, tot_len = 0; 1233 1234 /* 1235 * Start packing the mbufs in this chain into 1236 * the fragment pointers. Stop when we run out 1237 * of fragments or hit the end of the mbuf chain. 1238 */ 1239 m = m_head; 1240 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1241 frag = 0; 1242 1243 for (m = m_head; m != NULL; m = m->m_next) { 1244 if (m->m_len != 0) { 1245 tot_len += m->m_len; 1246 f = &cur_tx->lge_frags[frag]; 1247 f->lge_fraglen = m->m_len; 1248 f->lge_fragptr_lo = vtophys(mtod(m, vaddr_t)); 1249 f->lge_fragptr_hi = 0; 1250 frag++; 1251 } 1252 } 1253 1254 if (m != NULL) 1255 return(ENOBUFS); 1256 1257 cur_tx->lge_mbuf = m_head; 1258 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1259 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1260 1261 /* Queue for transmit */ 1262 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1263 1264 return(0); 1265 } 1266 1267 /* 1268 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1269 * to the mbuf data regions directly in the transmit lists. We also save a 1270 * copy of the pointers since the transmit list fragment pointers are 1271 * physical addresses. 1272 */ 1273 1274 void lge_start(ifp) 1275 struct ifnet *ifp; 1276 { 1277 struct lge_softc *sc; 1278 struct mbuf *m_head = NULL; 1279 u_int32_t idx; 1280 int pkts = 0; 1281 1282 sc = ifp->if_softc; 1283 1284 if (!sc->lge_link) 1285 return; 1286 1287 idx = sc->lge_cdata.lge_tx_prod; 1288 1289 if (ifp->if_flags & IFF_OACTIVE) 1290 return; 1291 1292 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1293 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1294 break; 1295 1296 IFQ_POLL(&ifp->if_snd, m_head); 1297 if (m_head == NULL) 1298 break; 1299 1300 if (lge_encap(sc, m_head, &idx)) { 1301 ifp->if_flags |= IFF_OACTIVE; 1302 break; 1303 } 1304 1305 /* now we are committed to transmit the packet */ 1306 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1307 pkts++; 1308 1309 #if NBPFILTER > 0 1310 /* 1311 * If there's a BPF listener, bounce a copy of this frame 1312 * to him. 1313 */ 1314 if (ifp->if_bpf) 1315 bpf_mtap(ifp->if_bpf, m_head); 1316 #endif 1317 } 1318 if (pkts == 0) 1319 return; 1320 1321 sc->lge_cdata.lge_tx_prod = idx; 1322 1323 /* 1324 * Set a timeout in case the chip goes out to lunch. 1325 */ 1326 ifp->if_timer = 5; 1327 1328 return; 1329 } 1330 1331 void lge_init(xsc) 1332 void *xsc; 1333 { 1334 struct lge_softc *sc = xsc; 1335 struct ifnet *ifp = &sc->arpcom.ac_if; 1336 int s; 1337 1338 if (ifp->if_flags & IFF_RUNNING) 1339 return; 1340 1341 s = splimp(); 1342 1343 /* 1344 * Cancel pending I/O and free all RX/TX buffers. 1345 */ 1346 lge_stop(sc); 1347 lge_reset(sc); 1348 1349 /* Set MAC address */ 1350 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1351 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1352 1353 /* Init circular RX list. */ 1354 if (lge_list_rx_init(sc) == ENOBUFS) { 1355 printf("%s: initialization failed: no " 1356 "memory for rx buffers\n", sc->sc_dv.dv_xname); 1357 lge_stop(sc); 1358 splx(s); 1359 return; 1360 } 1361 1362 /* 1363 * Init tx descriptors. 1364 */ 1365 lge_list_tx_init(sc); 1366 1367 /* Set initial value for MODE1 register. */ 1368 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1369 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1370 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1371 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1372 1373 /* If we want promiscuous mode, set the allframes bit. */ 1374 if (ifp->if_flags & IFF_PROMISC) { 1375 CSR_WRITE_4(sc, LGE_MODE1, 1376 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1377 } else { 1378 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1379 } 1380 1381 /* 1382 * Set the capture broadcast bit to capture broadcast frames. 1383 */ 1384 if (ifp->if_flags & IFF_BROADCAST) { 1385 CSR_WRITE_4(sc, LGE_MODE1, 1386 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1387 } else { 1388 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1389 } 1390 1391 /* Packet padding workaround? */ 1392 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1393 1394 /* No error frames */ 1395 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1396 1397 /* Receive large frames */ 1398 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1399 1400 /* Workaround: disable RX/TX flow control */ 1401 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1402 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1403 1404 /* Make sure to strip CRC from received frames */ 1405 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1406 1407 /* Turn off magic packet mode */ 1408 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1409 1410 /* Turn off all VLAN stuff */ 1411 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1412 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1413 1414 /* Workarond: FIFO overflow */ 1415 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1416 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1417 1418 /* 1419 * Load the multicast filter. 1420 */ 1421 lge_setmulti(sc); 1422 1423 /* 1424 * Enable hardware checksum validation for all received IPv4 1425 * packets, do not reject packets with bad checksums. 1426 */ 1427 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1428 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1429 LGE_MODE2_RX_ERRCSUM); 1430 1431 /* 1432 * Enable the delivery of PHY interrupts based on 1433 * link/speed/duplex status chalges. 1434 */ 1435 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1436 1437 /* Enable receiver and transmitter. */ 1438 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1439 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1440 1441 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1442 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1443 1444 /* 1445 * Enable interrupts. 1446 */ 1447 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1448 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1449 1450 lge_ifmedia_upd(ifp); 1451 1452 ifp->if_flags |= IFF_RUNNING; 1453 ifp->if_flags &= ~IFF_OACTIVE; 1454 1455 splx(s); 1456 1457 timeout_add(&sc->lge_timeout, hz); 1458 1459 return; 1460 } 1461 1462 /* 1463 * Set media options. 1464 */ 1465 int lge_ifmedia_upd(ifp) 1466 struct ifnet *ifp; 1467 { 1468 struct lge_softc *sc = ifp->if_softc; 1469 struct mii_data *mii = &sc->lge_mii; 1470 1471 sc->lge_link = 0; 1472 if (mii->mii_instance) { 1473 struct mii_softc *miisc; 1474 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1475 miisc = LIST_NEXT(miisc, mii_list)) 1476 mii_phy_reset(miisc); 1477 } 1478 mii_mediachg(mii); 1479 1480 return(0); 1481 } 1482 1483 /* 1484 * Report current media status. 1485 */ 1486 void lge_ifmedia_sts(ifp, ifmr) 1487 struct ifnet *ifp; 1488 struct ifmediareq *ifmr; 1489 { 1490 struct lge_softc *sc = ifp->if_softc; 1491 struct mii_data *mii = &sc->lge_mii; 1492 1493 mii_pollstat(mii); 1494 ifmr->ifm_active = mii->mii_media_active; 1495 ifmr->ifm_status = mii->mii_media_status; 1496 1497 return; 1498 } 1499 1500 int lge_ioctl(ifp, command, data) 1501 struct ifnet *ifp; 1502 u_long command; 1503 caddr_t data; 1504 { 1505 struct lge_softc *sc = ifp->if_softc; 1506 struct ifreq *ifr = (struct ifreq *) data; 1507 struct ifaddr *ifa = (struct ifaddr *)data; 1508 struct mii_data *mii; 1509 int s, error = 0; 1510 1511 s = splimp(); 1512 1513 switch(command) { 1514 case SIOCSIFADDR: 1515 ifp->if_flags |= IFF_UP; 1516 switch (ifa->ifa_addr->sa_family) { 1517 #ifdef INET 1518 case AF_INET: 1519 lge_init(sc); 1520 arp_ifinit(&sc->arpcom, ifa); 1521 break; 1522 #endif /* INET */ 1523 default: 1524 lge_init(sc); 1525 break; 1526 } 1527 break; 1528 case SIOCSIFMTU: 1529 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1530 error = EINVAL; 1531 else 1532 ifp->if_mtu = ifr->ifr_mtu; 1533 break; 1534 case SIOCSIFFLAGS: 1535 if (ifp->if_flags & IFF_UP) { 1536 if (ifp->if_flags & IFF_RUNNING && 1537 ifp->if_flags & IFF_PROMISC && 1538 !(sc->lge_if_flags & IFF_PROMISC)) { 1539 CSR_WRITE_4(sc, LGE_MODE1, 1540 LGE_MODE1_SETRST_CTL1| 1541 LGE_MODE1_RX_PROMISC); 1542 } else if (ifp->if_flags & IFF_RUNNING && 1543 !(ifp->if_flags & IFF_PROMISC) && 1544 sc->lge_if_flags & IFF_PROMISC) { 1545 CSR_WRITE_4(sc, LGE_MODE1, 1546 LGE_MODE1_RX_PROMISC); 1547 } else { 1548 ifp->if_flags &= ~IFF_RUNNING; 1549 lge_init(sc); 1550 } 1551 } else { 1552 if (ifp->if_flags & IFF_RUNNING) 1553 lge_stop(sc); 1554 } 1555 sc->lge_if_flags = ifp->if_flags; 1556 error = 0; 1557 break; 1558 case SIOCADDMULTI: 1559 case SIOCDELMULTI: 1560 error = (command == SIOCADDMULTI) 1561 ? ether_addmulti(ifr, &sc->arpcom) 1562 : ether_delmulti(ifr, &sc->arpcom); 1563 1564 if (error == ENETRESET) { 1565 if (ifp->if_flags & IFF_RUNNING) 1566 lge_setmulti(sc); 1567 error = 0; 1568 } 1569 break; 1570 case SIOCGIFMEDIA: 1571 case SIOCSIFMEDIA: 1572 mii = &sc->lge_mii; 1573 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1574 break; 1575 default: 1576 error = EINVAL; 1577 break; 1578 } 1579 1580 splx(s); 1581 1582 return(error); 1583 } 1584 1585 void lge_watchdog(ifp) 1586 struct ifnet *ifp; 1587 { 1588 struct lge_softc *sc; 1589 1590 sc = ifp->if_softc; 1591 1592 ifp->if_oerrors++; 1593 printf("%s: watchdog timeout\n", sc->sc_dv.dv_xname); 1594 1595 lge_stop(sc); 1596 lge_reset(sc); 1597 ifp->if_flags &= ~IFF_RUNNING; 1598 lge_init(sc); 1599 1600 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1601 lge_start(ifp); 1602 1603 return; 1604 } 1605 1606 /* 1607 * Stop the adapter and free any mbufs allocated to the 1608 * RX and TX lists. 1609 */ 1610 void lge_stop(sc) 1611 struct lge_softc *sc; 1612 { 1613 register int i; 1614 struct ifnet *ifp; 1615 1616 ifp = &sc->arpcom.ac_if; 1617 ifp->if_timer = 0; 1618 timeout_del(&sc->lge_timeout); 1619 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1620 1621 /* Disable receiver and transmitter. */ 1622 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1623 sc->lge_link = 0; 1624 1625 /* 1626 * Free data in the RX lists. 1627 */ 1628 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1629 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1630 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1631 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1632 } 1633 } 1634 bzero((char *)&sc->lge_ldata->lge_rx_list, 1635 sizeof(sc->lge_ldata->lge_rx_list)); 1636 1637 /* 1638 * Free the TX list buffers. 1639 */ 1640 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1641 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1642 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1643 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1644 } 1645 } 1646 1647 bzero((char *)&sc->lge_ldata->lge_tx_list, 1648 sizeof(sc->lge_ldata->lge_tx_list)); 1649 1650 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1651 1652 return; 1653 } 1654 1655 /* 1656 * Stop all chip I/O so that the kernel's probe routines don't 1657 * get confused by errant DMAs when rebooting. 1658 */ 1659 void lge_shutdown(xsc) 1660 void *xsc; 1661 { 1662 struct lge_softc *sc = (struct lge_softc *)xsc; 1663 1664 lge_reset(sc); 1665 lge_stop(sc); 1666 1667 return; 1668 } 1669 1670 struct cfattach lge_ca = { 1671 sizeof(struct lge_softc), lge_probe, lge_attach 1672 }; 1673 1674 struct cfdriver lge_cd = { 1675 0, "lge", DV_IFNET 1676 }; 1677