1 /* $OpenBSD: if_lge.c,v 1.52 2009/08/13 14:24:47 jasper Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 5 * Bill Paul <william.paul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.6 2001/06/20 19:47:55 bmilekic Exp $ 35 */ 36 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * Written by Bill Paul <william.paul@windriver.com> 42 * Wind River Systems 43 */ 44 45 /* 46 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 47 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 48 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 49 * are three supported methods for data transfer between host and 50 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 51 * Propulsion Technology (tm) DMA. The latter mechanism is a form 52 * of double buffer DMA where the packet data is copied to a 53 * pre-allocated DMA buffer who's physical address has been loaded 54 * into a table at device initialization time. The rationale is that 55 * the virtual to physical address translation needed for normal 56 * scatter/gather DMA is more expensive than the data copy needed 57 * for double buffering. This may be true in Windows NT and the like, 58 * but it isn't true for us, at least on the x86 arch. This driver 59 * uses the scatter/gather I/O method for both TX and RX. 60 * 61 * The LXT1001 only supports TCP/IP checksum offload on receive. 62 * Also, the VLAN tagging is done using a 16-entry table which allows 63 * the chip to perform hardware filtering based on VLAN tags. Sadly, 64 * our vlan support doesn't currently play well with this kind of 65 * hardware support. 66 * 67 * Special thanks to: 68 * - Jeff James at Intel, for arranging to have the LXT1001 manual 69 * released (at long last) 70 * - Beny Chen at D-Link, for actually sending it to me 71 * - Brad Short and Keith Alexis at SMC, for sending me sample 72 * SMC9462SX and SMC9462TX adapters for testing 73 * - Paul Saab at Y!, for not killing me (though it remains to be seen 74 * if in fact he did me much of a favor) 75 */ 76 77 #include "bpfilter.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/sockio.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/device.h> 86 #include <sys/socket.h> 87 88 #include <net/if.h> 89 #include <net/if_dl.h> 90 #include <net/if_media.h> 91 92 #ifdef INET 93 #include <netinet/in.h> 94 #include <netinet/in_systm.h> 95 #include <netinet/in_var.h> 96 #include <netinet/ip.h> 97 #include <netinet/if_ether.h> 98 #endif 99 100 #if NBPFILTER > 0 101 #include <net/bpf.h> 102 #endif 103 104 #include <uvm/uvm_extern.h> /* for vtophys */ 105 #define VTOPHYS(v) vtophys((vaddr_t)(v)) 106 107 #include <dev/pci/pcireg.h> 108 #include <dev/pci/pcivar.h> 109 #include <dev/pci/pcidevs.h> 110 111 #include <dev/mii/mii.h> 112 #include <dev/mii/miivar.h> 113 114 #define LGE_USEIOSPACE 115 116 #include <dev/pci/if_lgereg.h> 117 118 int lge_probe(struct device *, void *, void *); 119 void lge_attach(struct device *, struct device *, void *); 120 121 struct cfattach lge_ca = { 122 sizeof(struct lge_softc), lge_probe, lge_attach 123 }; 124 125 struct cfdriver lge_cd = { 126 NULL, "lge", DV_IFNET 127 }; 128 129 int lge_alloc_jumbo_mem(struct lge_softc *); 130 void *lge_jalloc(struct lge_softc *); 131 void lge_jfree(caddr_t, u_int, void *); 132 133 int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, 134 struct mbuf *); 135 int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 136 void lge_rxeof(struct lge_softc *, int); 137 void lge_txeof(struct lge_softc *); 138 int lge_intr(void *); 139 void lge_tick(void *); 140 void lge_start(struct ifnet *); 141 int lge_ioctl(struct ifnet *, u_long, caddr_t); 142 void lge_init(void *); 143 void lge_stop(struct lge_softc *); 144 void lge_watchdog(struct ifnet *); 145 int lge_ifmedia_upd(struct ifnet *); 146 void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 147 148 void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 149 void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 150 151 int lge_miibus_readreg(struct device *, int, int); 152 void lge_miibus_writereg(struct device *, int, int, int); 153 void lge_miibus_statchg(struct device *); 154 155 void lge_setmulti(struct lge_softc *); 156 void lge_reset(struct lge_softc *); 157 int lge_list_rx_init(struct lge_softc *); 158 int lge_list_tx_init(struct lge_softc *); 159 160 #ifdef LGE_DEBUG 161 #define DPRINTF(x) if (lgedebug) printf x 162 #define DPRINTFN(n,x) if (lgedebug >= (n)) printf x 163 int lgedebug = 0; 164 #else 165 #define DPRINTF(x) 166 #define DPRINTFN(n,x) 167 #endif 168 169 const struct pci_matchid lge_devices[] = { 170 { PCI_VENDOR_LEVEL1, PCI_PRODUCT_LEVEL1_LXT1001 } 171 }; 172 173 #define LGE_SETBIT(sc, reg, x) \ 174 CSR_WRITE_4(sc, reg, \ 175 CSR_READ_4(sc, reg) | (x)) 176 177 #define LGE_CLRBIT(sc, reg, x) \ 178 CSR_WRITE_4(sc, reg, \ 179 CSR_READ_4(sc, reg) & ~(x)) 180 181 #define SIO_SET(x) \ 182 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 183 184 #define SIO_CLR(x) \ 185 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 186 187 /* 188 * Read a word of data stored in the EEPROM at address 'addr.' 189 */ 190 void 191 lge_eeprom_getword(struct lge_softc *sc, int addr, u_int16_t *dest) 192 { 193 int i; 194 u_int32_t val; 195 196 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 197 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 198 199 for (i = 0; i < LGE_TIMEOUT; i++) 200 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 201 break; 202 203 if (i == LGE_TIMEOUT) { 204 printf("%s: EEPROM read timed out\n", sc->sc_dv.dv_xname); 205 return; 206 } 207 208 val = CSR_READ_4(sc, LGE_EEDATA); 209 210 if (addr & 1) 211 *dest = (val >> 16) & 0xFFFF; 212 else 213 *dest = val & 0xFFFF; 214 } 215 216 /* 217 * Read a sequence of words from the EEPROM. 218 */ 219 void 220 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, 221 int cnt, int swap) 222 { 223 int i; 224 u_int16_t word = 0, *ptr; 225 226 for (i = 0; i < cnt; i++) { 227 lge_eeprom_getword(sc, off + i, &word); 228 ptr = (u_int16_t *)(dest + (i * 2)); 229 if (swap) 230 *ptr = ntohs(word); 231 else 232 *ptr = word; 233 } 234 } 235 236 int 237 lge_miibus_readreg(struct device *dev, int phy, int reg) 238 { 239 struct lge_softc *sc = (struct lge_softc *)dev; 240 int i; 241 242 /* 243 * If we have a non-PCS PHY, pretend that the internal 244 * autoneg stuff at PHY address 0 isn't there so that 245 * the miibus code will find only the GMII PHY. 246 */ 247 if (sc->lge_pcs == 0 && phy == 0) 248 return (0); 249 250 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 251 252 for (i = 0; i < LGE_TIMEOUT; i++) 253 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 254 break; 255 256 if (i == LGE_TIMEOUT) { 257 printf("%s: PHY read timed out\n", sc->sc_dv.dv_xname); 258 return (0); 259 } 260 261 return (CSR_READ_4(sc, LGE_GMIICTL) >> 16); 262 } 263 264 void 265 lge_miibus_writereg(struct device *dev, int phy, int reg, int data) 266 { 267 struct lge_softc *sc = (struct lge_softc *)dev; 268 int i; 269 270 CSR_WRITE_4(sc, LGE_GMIICTL, 271 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 272 273 for (i = 0; i < LGE_TIMEOUT; i++) 274 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 275 break; 276 277 if (i == LGE_TIMEOUT) { 278 printf("%s: PHY write timed out\n", sc->sc_dv.dv_xname); 279 } 280 } 281 282 void 283 lge_miibus_statchg(struct device *dev) 284 { 285 struct lge_softc *sc = (struct lge_softc *)dev; 286 struct mii_data *mii = &sc->lge_mii; 287 288 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 289 switch (IFM_SUBTYPE(mii->mii_media_active)) { 290 case IFM_1000_T: 291 case IFM_1000_SX: 292 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 293 break; 294 case IFM_100_TX: 295 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 296 break; 297 case IFM_10_T: 298 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 299 break; 300 default: 301 /* 302 * Choose something, even if it's wrong. Clearing 303 * all the bits will hose autoneg on the internal 304 * PHY. 305 */ 306 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 307 break; 308 } 309 310 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 311 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 312 } else { 313 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 314 } 315 } 316 317 void 318 lge_setmulti(struct lge_softc *sc) 319 { 320 struct arpcom *ac = &sc->arpcom; 321 struct ifnet *ifp = &ac->ac_if; 322 struct ether_multi *enm; 323 struct ether_multistep step; 324 u_int32_t h = 0, hashes[2] = { 0, 0 }; 325 326 /* Make sure multicast hash table is enabled. */ 327 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 328 329 allmulti: 330 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 331 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 332 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 333 return; 334 } 335 336 /* first, zot all the existing hash bits */ 337 CSR_WRITE_4(sc, LGE_MAR0, 0); 338 CSR_WRITE_4(sc, LGE_MAR1, 0); 339 340 /* now program new ones */ 341 ETHER_FIRST_MULTI(step, ac, enm); 342 while (enm != NULL) { 343 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 344 ifp->if_flags |= IFF_ALLMULTI; 345 goto allmulti; 346 } 347 h = (ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26) & 348 0x0000003F; 349 if (h < 32) 350 hashes[0] |= (1 << h); 351 else 352 hashes[1] |= (1 << (h - 32)); 353 ETHER_NEXT_MULTI(step, enm); 354 } 355 356 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 357 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 358 } 359 360 void 361 lge_reset(struct lge_softc *sc) 362 { 363 int i; 364 365 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 366 367 for (i = 0; i < LGE_TIMEOUT; i++) { 368 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 369 break; 370 } 371 372 if (i == LGE_TIMEOUT) 373 printf("%s: reset never completed\n", sc->sc_dv.dv_xname); 374 375 /* Wait a little while for the chip to get its brains in order. */ 376 DELAY(1000); 377 } 378 379 /* 380 * Probe for a Level 1 chip. Check the PCI vendor and device 381 * IDs against our list and return a device name if we find a match. 382 */ 383 int 384 lge_probe(struct device *parent, void *match, void *aux) 385 { 386 return (pci_matchbyid((struct pci_attach_args *)aux, lge_devices, 387 sizeof(lge_devices)/sizeof(lge_devices[0]))); 388 } 389 390 /* 391 * Attach the interface. Allocate softc structures, do ifmedia 392 * setup and ethernet/BPF attach. 393 */ 394 void 395 lge_attach(struct device *parent, struct device *self, void *aux) 396 { 397 struct lge_softc *sc = (struct lge_softc *)self; 398 struct pci_attach_args *pa = aux; 399 pci_chipset_tag_t pc = pa->pa_pc; 400 pci_intr_handle_t ih; 401 const char *intrstr = NULL; 402 bus_size_t size; 403 bus_dma_segment_t seg; 404 bus_dmamap_t dmamap; 405 int rseg; 406 u_char eaddr[ETHER_ADDR_LEN]; 407 pcireg_t command; 408 #ifndef LGE_USEIOSPACE 409 pcireg_t memtype; 410 #endif 411 struct ifnet *ifp; 412 caddr_t kva; 413 414 /* 415 * Handle power management nonsense. 416 */ 417 DPRINTFN(5, ("Preparing for conf read\n")); 418 command = pci_conf_read(pc, pa->pa_tag, LGE_PCI_CAPID) & 0x000000FF; 419 if (command == 0x01) { 420 command = pci_conf_read(pc, pa->pa_tag, LGE_PCI_PWRMGMTCTRL); 421 if (command & LGE_PSTATE_MASK) { 422 pcireg_t iobase, membase, irq; 423 424 /* Save important PCI config data. */ 425 iobase = pci_conf_read(pc, pa->pa_tag, LGE_PCI_LOIO); 426 membase = pci_conf_read(pc, pa->pa_tag, LGE_PCI_LOMEM); 427 irq = pci_conf_read(pc, pa->pa_tag, LGE_PCI_INTLINE); 428 429 /* Reset the power state. */ 430 printf("%s: chip is in D%d power mode " 431 "-- setting to D0\n", sc->sc_dv.dv_xname, 432 command & LGE_PSTATE_MASK); 433 command &= 0xFFFFFFFC; 434 pci_conf_write(pc, pa->pa_tag, 435 LGE_PCI_PWRMGMTCTRL, command); 436 437 /* Restore PCI config data. */ 438 pci_conf_write(pc, pa->pa_tag, LGE_PCI_LOIO, iobase); 439 pci_conf_write(pc, pa->pa_tag, LGE_PCI_LOMEM, membase); 440 pci_conf_write(pc, pa->pa_tag, LGE_PCI_INTLINE, irq); 441 } 442 } 443 444 /* 445 * Map control/status registers. 446 */ 447 DPRINTFN(5, ("Map control/status regs\n")); 448 449 DPRINTFN(5, ("pci_mapreg_map\n")); 450 #ifdef LGE_USEIOSPACE 451 if (pci_mapreg_map(pa, LGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 452 &sc->lge_btag, &sc->lge_bhandle, NULL, &size, 0)) { 453 printf(": can't map i/o space\n"); 454 return; 455 } 456 #else 457 memtype = pci_mapreg_type(pc, pa->pa_tag, LGE_PCI_LOMEM); 458 if (pci_mapreg_map(pa, LGE_PCI_LOMEM, memtype, 0, &sc->lge_btag, 459 &sc->lge_bhandle, NULL, &size, 0)) { 460 printf(": can't map mem space\n"); 461 return; 462 } 463 #endif 464 465 DPRINTFN(5, ("pci_intr_map\n")); 466 if (pci_intr_map(pa, &ih)) { 467 printf(": couldn't map interrupt\n"); 468 goto fail_1; 469 } 470 471 DPRINTFN(5, ("pci_intr_string\n")); 472 intrstr = pci_intr_string(pc, ih); 473 DPRINTFN(5, ("pci_intr_establish\n")); 474 sc->lge_intrhand = pci_intr_establish(pc, ih, IPL_NET, lge_intr, sc, 475 sc->sc_dv.dv_xname); 476 if (sc->lge_intrhand == NULL) { 477 printf(": couldn't establish interrupt"); 478 if (intrstr != NULL) 479 printf(" at %s", intrstr); 480 printf("\n"); 481 goto fail_1; 482 } 483 printf(": %s", intrstr); 484 485 /* Reset the adapter. */ 486 DPRINTFN(5, ("lge_reset\n")); 487 lge_reset(sc); 488 489 /* 490 * Get station address from the EEPROM. 491 */ 492 DPRINTFN(5, ("lge_read_eeprom\n")); 493 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 494 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 495 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 496 497 /* 498 * A Level 1 chip was detected. Inform the world. 499 */ 500 printf(", address %s\n", ether_sprintf(eaddr)); 501 502 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 503 504 sc->sc_dmatag = pa->pa_dmat; 505 DPRINTFN(5, ("bus_dmamem_alloc\n")); 506 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct lge_list_data), 507 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 508 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 509 goto fail_2; 510 } 511 DPRINTFN(5, ("bus_dmamem_map\n")); 512 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 513 sizeof(struct lge_list_data), &kva, 514 BUS_DMA_NOWAIT)) { 515 printf("%s: can't map dma buffers (%d bytes)\n", 516 sc->sc_dv.dv_xname, sizeof(struct lge_list_data)); 517 goto fail_3; 518 } 519 DPRINTFN(5, ("bus_dmamem_create\n")); 520 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct lge_list_data), 1, 521 sizeof(struct lge_list_data), 0, 522 BUS_DMA_NOWAIT, &dmamap)) { 523 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 524 goto fail_4; 525 } 526 DPRINTFN(5, ("bus_dmamem_load\n")); 527 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, 528 sizeof(struct lge_list_data), NULL, 529 BUS_DMA_NOWAIT)) { 530 goto fail_5; 531 } 532 533 DPRINTFN(5, ("bzero\n")); 534 sc->lge_ldata = (struct lge_list_data *)kva; 535 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 536 537 /* Try to allocate memory for jumbo buffers. */ 538 DPRINTFN(5, ("lge_alloc_jumbo_mem\n")); 539 if (lge_alloc_jumbo_mem(sc)) { 540 printf("%s: jumbo buffer allocation failed\n", 541 sc->sc_dv.dv_xname); 542 goto fail_5; 543 } 544 545 ifp = &sc->arpcom.ac_if; 546 ifp->if_softc = sc; 547 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 548 ifp->if_ioctl = lge_ioctl; 549 ifp->if_start = lge_start; 550 ifp->if_watchdog = lge_watchdog; 551 ifp->if_baudrate = 1000000000; 552 ifp->if_hardmtu = LGE_JUMBO_MTU; 553 IFQ_SET_MAXLEN(&ifp->if_snd, LGE_TX_LIST_CNT - 1); 554 IFQ_SET_READY(&ifp->if_snd); 555 DPRINTFN(5, ("bcopy\n")); 556 bcopy(sc->sc_dv.dv_xname, ifp->if_xname, IFNAMSIZ); 557 558 ifp->if_capabilities = IFCAP_VLAN_MTU; 559 560 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 561 sc->lge_pcs = 1; 562 else 563 sc->lge_pcs = 0; 564 565 /* 566 * Do MII setup. 567 */ 568 DPRINTFN(5, ("mii setup\n")); 569 sc->lge_mii.mii_ifp = ifp; 570 sc->lge_mii.mii_readreg = lge_miibus_readreg; 571 sc->lge_mii.mii_writereg = lge_miibus_writereg; 572 sc->lge_mii.mii_statchg = lge_miibus_statchg; 573 ifmedia_init(&sc->lge_mii.mii_media, 0, lge_ifmedia_upd, 574 lge_ifmedia_sts); 575 mii_attach(&sc->sc_dv, &sc->lge_mii, 0xffffffff, MII_PHY_ANY, 576 MII_OFFSET_ANY, 0); 577 578 if (LIST_FIRST(&sc->lge_mii.mii_phys) == NULL) { 579 printf("%s: no PHY found!\n", sc->sc_dv.dv_xname); 580 ifmedia_add(&sc->lge_mii.mii_media, IFM_ETHER|IFM_MANUAL, 581 0, NULL); 582 ifmedia_set(&sc->lge_mii.mii_media, IFM_ETHER|IFM_MANUAL); 583 } else { 584 DPRINTFN(5, ("ifmedia_set\n")); 585 ifmedia_set(&sc->lge_mii.mii_media, IFM_ETHER|IFM_AUTO); 586 } 587 588 /* 589 * Call MI attach routine. 590 */ 591 DPRINTFN(5, ("if_attach\n")); 592 if_attach(ifp); 593 DPRINTFN(5, ("ether_ifattach\n")); 594 ether_ifattach(ifp); 595 DPRINTFN(5, ("timeout_set\n")); 596 timeout_set(&sc->lge_timeout, lge_tick, sc); 597 timeout_add_sec(&sc->lge_timeout, 1); 598 return; 599 600 fail_5: 601 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 602 603 fail_4: 604 bus_dmamem_unmap(sc->sc_dmatag, kva, 605 sizeof(struct lge_list_data)); 606 607 fail_3: 608 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 609 610 fail_2: 611 pci_intr_disestablish(pc, sc->lge_intrhand); 612 613 fail_1: 614 bus_space_unmap(sc->lge_btag, sc->lge_bhandle, size); 615 } 616 617 /* 618 * Initialize the transmit descriptors. 619 */ 620 int 621 lge_list_tx_init(struct lge_softc *sc) 622 { 623 struct lge_list_data *ld; 624 struct lge_ring_data *cd; 625 int i; 626 627 cd = &sc->lge_cdata; 628 ld = sc->lge_ldata; 629 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 630 ld->lge_tx_list[i].lge_mbuf = NULL; 631 ld->lge_tx_list[i].lge_ctl = 0; 632 } 633 634 cd->lge_tx_prod = cd->lge_tx_cons = 0; 635 636 return (0); 637 } 638 639 640 /* 641 * Initialize the RX descriptors and allocate mbufs for them. Note that 642 * we arrange the descriptors in a closed ring, so that the last descriptor 643 * points back to the first. 644 */ 645 int 646 lge_list_rx_init(struct lge_softc *sc) 647 { 648 struct lge_list_data *ld; 649 struct lge_ring_data *cd; 650 int i; 651 652 ld = sc->lge_ldata; 653 cd = &sc->lge_cdata; 654 655 cd->lge_rx_prod = cd->lge_rx_cons = 0; 656 657 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 658 659 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 660 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 661 break; 662 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 663 return (ENOBUFS); 664 } 665 666 /* Clear possible 'rx command queue empty' interrupt. */ 667 CSR_READ_4(sc, LGE_ISR); 668 669 return (0); 670 } 671 672 /* 673 * Initialize a RX descriptor and attach a MBUF cluster. 674 */ 675 int 676 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m) 677 { 678 struct mbuf *m_new = NULL; 679 680 if (m == NULL) { 681 caddr_t buf = NULL; 682 683 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 684 if (m_new == NULL) 685 return (ENOBUFS); 686 687 /* Allocate the jumbo buffer */ 688 buf = lge_jalloc(sc); 689 if (buf == NULL) { 690 m_freem(m_new); 691 return (ENOBUFS); 692 } 693 694 /* Attach the buffer to the mbuf */ 695 m_new->m_len = m_new->m_pkthdr.len = LGE_JLEN; 696 MEXTADD(m_new, buf, LGE_JLEN, 0, lge_jfree, sc); 697 } else { 698 /* 699 * We're re-using a previously allocated mbuf; 700 * be sure to re-init pointers and lengths to 701 * default values. 702 */ 703 m_new = m; 704 m_new->m_len = m_new->m_pkthdr.len = LGE_JLEN; 705 m_new->m_data = m_new->m_ext.ext_buf; 706 } 707 708 /* 709 * Adjust alignment so packet payload begins on a 710 * longword boundary. Mandatory for Alpha, useful on 711 * x86 too. 712 */ 713 m_adj(m_new, ETHER_ALIGN); 714 715 c->lge_mbuf = m_new; 716 c->lge_fragptr_hi = 0; 717 c->lge_fragptr_lo = VTOPHYS(mtod(m_new, caddr_t)); 718 c->lge_fraglen = m_new->m_len; 719 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 720 c->lge_sts = 0; 721 722 /* 723 * Put this buffer in the RX command FIFO. To do this, 724 * we just write the physical address of the descriptor 725 * into the RX descriptor address registers. Note that 726 * there are two registers, one high DWORD and one low 727 * DWORD, which lets us specify a 64-bit address if 728 * desired. We only use a 32-bit address for now. 729 * Writing to the low DWORD register is what actually 730 * causes the command to be issued, so we do that 731 * last. 732 */ 733 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, VTOPHYS(c)); 734 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 735 736 return (0); 737 } 738 739 int 740 lge_alloc_jumbo_mem(struct lge_softc *sc) 741 { 742 caddr_t ptr, kva; 743 bus_dma_segment_t seg; 744 bus_dmamap_t dmamap; 745 int i, rseg, state, error; 746 struct lge_jpool_entry *entry; 747 748 state = error = 0; 749 750 /* Grab a big chunk o' storage. */ 751 if (bus_dmamem_alloc(sc->sc_dmatag, LGE_JMEM, PAGE_SIZE, 0, 752 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 753 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 754 return (ENOBUFS); 755 } 756 757 state = 1; 758 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, LGE_JMEM, &kva, 759 BUS_DMA_NOWAIT)) { 760 printf("%s: can't map dma buffers (%d bytes)\n", 761 sc->sc_dv.dv_xname, LGE_JMEM); 762 error = ENOBUFS; 763 goto out; 764 } 765 766 state = 2; 767 if (bus_dmamap_create(sc->sc_dmatag, LGE_JMEM, 1, 768 LGE_JMEM, 0, BUS_DMA_NOWAIT, &dmamap)) { 769 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 770 error = ENOBUFS; 771 goto out; 772 } 773 774 state = 3; 775 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, LGE_JMEM, 776 NULL, BUS_DMA_NOWAIT)) { 777 printf("%s: can't load dma map\n", sc->sc_dv.dv_xname); 778 error = ENOBUFS; 779 goto out; 780 } 781 782 state = 4; 783 sc->lge_cdata.lge_jumbo_buf = (caddr_t)kva; 784 DPRINTFN(1,("lge_jumbo_buf = 0x%08X\n", sc->lge_cdata.lge_jumbo_buf)); 785 DPRINTFN(1,("LGE_JLEN = 0x%08X\n", LGE_JLEN)); 786 787 LIST_INIT(&sc->lge_jfree_listhead); 788 LIST_INIT(&sc->lge_jinuse_listhead); 789 790 /* 791 * Now divide it up into 9K pieces and save the addresses 792 * in an array. 793 */ 794 ptr = sc->lge_cdata.lge_jumbo_buf; 795 for (i = 0; i < LGE_JSLOTS; i++) { 796 sc->lge_cdata.lge_jslots[i] = ptr; 797 ptr += LGE_JLEN; 798 entry = malloc(sizeof(struct lge_jpool_entry), 799 M_DEVBUF, M_NOWAIT); 800 if (entry == NULL) { 801 sc->lge_cdata.lge_jumbo_buf = NULL; 802 printf("%s: no memory for jumbo buffer queue!\n", 803 sc->sc_dv.dv_xname); 804 error = ENOBUFS; 805 goto out; 806 } 807 entry->slot = i; 808 LIST_INSERT_HEAD(&sc->lge_jfree_listhead, 809 entry, jpool_entries); 810 } 811 out: 812 if (error != 0) { 813 switch (state) { 814 case 4: 815 bus_dmamap_unload(sc->sc_dmatag, dmamap); 816 case 3: 817 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 818 case 2: 819 bus_dmamem_unmap(sc->sc_dmatag, kva, LGE_JMEM); 820 case 1: 821 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 822 break; 823 default: 824 break; 825 } 826 } 827 828 return (error); 829 } 830 831 /* 832 * Allocate a jumbo buffer. 833 */ 834 void * 835 lge_jalloc(struct lge_softc *sc) 836 { 837 struct lge_jpool_entry *entry; 838 839 entry = LIST_FIRST(&sc->lge_jfree_listhead); 840 841 if (entry == NULL) 842 return (NULL); 843 844 LIST_REMOVE(entry, jpool_entries); 845 LIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 846 return (sc->lge_cdata.lge_jslots[entry->slot]); 847 } 848 849 /* 850 * Release a jumbo buffer. 851 */ 852 void 853 lge_jfree(caddr_t buf, u_int size, void *arg) 854 { 855 struct lge_softc *sc; 856 int i; 857 struct lge_jpool_entry *entry; 858 859 /* Extract the softc struct pointer. */ 860 sc = (struct lge_softc *)arg; 861 862 if (sc == NULL) 863 panic("lge_jfree: can't find softc pointer!"); 864 865 /* calculate the slot this buffer belongs to */ 866 i = ((vaddr_t)buf - (vaddr_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 867 868 if ((i < 0) || (i >= LGE_JSLOTS)) 869 panic("lge_jfree: asked to free buffer that we don't manage!"); 870 871 entry = LIST_FIRST(&sc->lge_jinuse_listhead); 872 if (entry == NULL) 873 panic("lge_jfree: buffer not in use!"); 874 entry->slot = i; 875 LIST_REMOVE(entry, jpool_entries); 876 LIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 877 } 878 879 /* 880 * A frame has been uploaded: pass the resulting mbuf chain up to 881 * the higher level protocols. 882 */ 883 void 884 lge_rxeof(struct lge_softc *sc, int cnt) 885 { 886 struct mbuf *m; 887 struct ifnet *ifp; 888 struct lge_rx_desc *cur_rx; 889 int c, i, total_len = 0; 890 u_int32_t rxsts, rxctl; 891 892 ifp = &sc->arpcom.ac_if; 893 894 /* Find out how many frames were processed. */ 895 c = cnt; 896 i = sc->lge_cdata.lge_rx_cons; 897 898 /* Suck them in. */ 899 while(c) { 900 struct mbuf *m0 = NULL; 901 902 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 903 rxctl = cur_rx->lge_ctl; 904 rxsts = cur_rx->lge_sts; 905 m = cur_rx->lge_mbuf; 906 cur_rx->lge_mbuf = NULL; 907 total_len = LGE_RXBYTES(cur_rx); 908 LGE_INC(i, LGE_RX_LIST_CNT); 909 c--; 910 911 /* 912 * If an error occurs, update stats, clear the 913 * status word and leave the mbuf cluster in place: 914 * it should simply get re-used next time this descriptor 915 * comes up in the ring. 916 */ 917 if (rxctl & LGE_RXCTL_ERRMASK) { 918 ifp->if_ierrors++; 919 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 920 continue; 921 } 922 923 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 924 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 925 ifp, NULL); 926 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 927 if (m0 == NULL) { 928 ifp->if_ierrors++; 929 continue; 930 } 931 m = m0; 932 } else { 933 m->m_pkthdr.rcvif = ifp; 934 m->m_pkthdr.len = m->m_len = total_len; 935 } 936 937 ifp->if_ipackets++; 938 939 #if NBPFILTER > 0 940 /* 941 * Handle BPF listeners. Let the BPF user see the packet. 942 */ 943 if (ifp->if_bpf) 944 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 945 #endif 946 947 /* Do IP checksum checking. */ 948 if (rxsts & LGE_RXSTS_ISIP) { 949 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 950 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 951 } 952 if (rxsts & LGE_RXSTS_ISTCP) { 953 if (!(rxsts & LGE_RXSTS_TCPCSUMERR)) 954 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 955 } 956 if (rxsts & LGE_RXSTS_ISUDP) { 957 if (!(rxsts & LGE_RXSTS_UDPCSUMERR)) 958 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 959 } 960 961 ether_input_mbuf(ifp, m); 962 } 963 964 sc->lge_cdata.lge_rx_cons = i; 965 } 966 967 /* 968 * A frame was downloaded to the chip. It's safe for us to clean up 969 * the list buffers. 970 */ 971 972 void 973 lge_txeof(struct lge_softc *sc) 974 { 975 struct lge_tx_desc *cur_tx = NULL; 976 struct ifnet *ifp; 977 u_int32_t idx, txdone; 978 979 ifp = &sc->arpcom.ac_if; 980 981 /* Clear the timeout timer. */ 982 ifp->if_timer = 0; 983 984 /* 985 * Go through our tx list and free mbufs for those 986 * frames that have been transmitted. 987 */ 988 idx = sc->lge_cdata.lge_tx_cons; 989 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 990 991 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 992 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 993 994 ifp->if_opackets++; 995 if (cur_tx->lge_mbuf != NULL) { 996 m_freem(cur_tx->lge_mbuf); 997 cur_tx->lge_mbuf = NULL; 998 } 999 cur_tx->lge_ctl = 0; 1000 1001 txdone--; 1002 LGE_INC(idx, LGE_TX_LIST_CNT); 1003 ifp->if_timer = 0; 1004 } 1005 1006 sc->lge_cdata.lge_tx_cons = idx; 1007 1008 if (cur_tx != NULL) 1009 ifp->if_flags &= ~IFF_OACTIVE; 1010 } 1011 1012 void 1013 lge_tick(void *xsc) 1014 { 1015 struct lge_softc *sc = xsc; 1016 struct mii_data *mii = &sc->lge_mii; 1017 struct ifnet *ifp = &sc->arpcom.ac_if; 1018 int s; 1019 1020 s = splnet(); 1021 1022 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1023 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1024 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1025 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1026 1027 if (!sc->lge_link) { 1028 mii_tick(mii); 1029 if (mii->mii_media_status & IFM_ACTIVE && 1030 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1031 sc->lge_link++; 1032 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1033 lge_start(ifp); 1034 } 1035 } 1036 1037 timeout_add_sec(&sc->lge_timeout, 1); 1038 1039 splx(s); 1040 } 1041 1042 int 1043 lge_intr(void *arg) 1044 { 1045 struct lge_softc *sc; 1046 struct ifnet *ifp; 1047 u_int32_t status; 1048 int claimed = 0; 1049 1050 sc = arg; 1051 ifp = &sc->arpcom.ac_if; 1052 1053 /* Suppress unwanted interrupts */ 1054 if (!(ifp->if_flags & IFF_UP)) { 1055 lge_stop(sc); 1056 return (0); 1057 } 1058 1059 for (;;) { 1060 /* 1061 * Reading the ISR register clears all interrupts, and 1062 * clears the 'interrupts enabled' bit in the IMR 1063 * register. 1064 */ 1065 status = CSR_READ_4(sc, LGE_ISR); 1066 1067 if ((status & LGE_INTRS) == 0) 1068 break; 1069 1070 claimed = 1; 1071 1072 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1073 lge_txeof(sc); 1074 1075 if (status & LGE_ISR_RXDMA_DONE) 1076 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1077 1078 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1079 lge_init(sc); 1080 1081 if (status & LGE_ISR_PHY_INTR) { 1082 sc->lge_link = 0; 1083 timeout_del(&sc->lge_timeout); 1084 lge_tick(sc); 1085 } 1086 } 1087 1088 /* Re-enable interrupts. */ 1089 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1090 1091 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1092 lge_start(ifp); 1093 1094 return (claimed); 1095 } 1096 1097 /* 1098 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1099 * pointers to the fragment pointers. 1100 */ 1101 int 1102 lge_encap(struct lge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1103 { 1104 struct lge_frag *f = NULL; 1105 struct lge_tx_desc *cur_tx; 1106 struct mbuf *m; 1107 int frag = 0, tot_len = 0; 1108 1109 /* 1110 * Start packing the mbufs in this chain into 1111 * the fragment pointers. Stop when we run out 1112 * of fragments or hit the end of the mbuf chain. 1113 */ 1114 m = m_head; 1115 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1116 frag = 0; 1117 1118 for (m = m_head; m != NULL; m = m->m_next) { 1119 if (m->m_len != 0) { 1120 tot_len += m->m_len; 1121 f = &cur_tx->lge_frags[frag]; 1122 f->lge_fraglen = m->m_len; 1123 f->lge_fragptr_lo = VTOPHYS(mtod(m, vaddr_t)); 1124 f->lge_fragptr_hi = 0; 1125 frag++; 1126 } 1127 } 1128 1129 if (m != NULL) 1130 return (ENOBUFS); 1131 1132 cur_tx->lge_mbuf = m_head; 1133 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1134 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1135 1136 /* Queue for transmit */ 1137 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, VTOPHYS(cur_tx)); 1138 1139 return (0); 1140 } 1141 1142 /* 1143 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1144 * to the mbuf data regions directly in the transmit lists. We also save a 1145 * copy of the pointers since the transmit list fragment pointers are 1146 * physical addresses. 1147 */ 1148 1149 void 1150 lge_start(struct ifnet *ifp) 1151 { 1152 struct lge_softc *sc; 1153 struct mbuf *m_head = NULL; 1154 u_int32_t idx; 1155 int pkts = 0; 1156 1157 sc = ifp->if_softc; 1158 1159 if (!sc->lge_link) 1160 return; 1161 1162 idx = sc->lge_cdata.lge_tx_prod; 1163 1164 if (ifp->if_flags & IFF_OACTIVE) 1165 return; 1166 1167 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1168 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1169 break; 1170 1171 IFQ_POLL(&ifp->if_snd, m_head); 1172 if (m_head == NULL) 1173 break; 1174 1175 if (lge_encap(sc, m_head, &idx)) { 1176 ifp->if_flags |= IFF_OACTIVE; 1177 break; 1178 } 1179 1180 /* now we are committed to transmit the packet */ 1181 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1182 pkts++; 1183 1184 #if NBPFILTER > 0 1185 /* 1186 * If there's a BPF listener, bounce a copy of this frame 1187 * to him. 1188 */ 1189 if (ifp->if_bpf) 1190 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1191 #endif 1192 } 1193 if (pkts == 0) 1194 return; 1195 1196 sc->lge_cdata.lge_tx_prod = idx; 1197 1198 /* 1199 * Set a timeout in case the chip goes out to lunch. 1200 */ 1201 ifp->if_timer = 5; 1202 } 1203 1204 void 1205 lge_init(void *xsc) 1206 { 1207 struct lge_softc *sc = xsc; 1208 struct ifnet *ifp = &sc->arpcom.ac_if; 1209 int s; 1210 1211 s = splnet(); 1212 1213 /* 1214 * Cancel pending I/O and free all RX/TX buffers. 1215 */ 1216 lge_stop(sc); 1217 lge_reset(sc); 1218 1219 /* Set MAC address */ 1220 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1221 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1222 1223 /* Init circular RX list. */ 1224 if (lge_list_rx_init(sc) == ENOBUFS) { 1225 printf("%s: initialization failed: no " 1226 "memory for rx buffers\n", sc->sc_dv.dv_xname); 1227 lge_stop(sc); 1228 splx(s); 1229 return; 1230 } 1231 1232 /* 1233 * Init tx descriptors. 1234 */ 1235 lge_list_tx_init(sc); 1236 1237 /* Set initial value for MODE1 register. */ 1238 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1239 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1240 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1241 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1242 1243 /* If we want promiscuous mode, set the allframes bit. */ 1244 if (ifp->if_flags & IFF_PROMISC) { 1245 CSR_WRITE_4(sc, LGE_MODE1, 1246 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1247 } else { 1248 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1249 } 1250 1251 /* 1252 * Set the capture broadcast bit to capture broadcast frames. 1253 */ 1254 if (ifp->if_flags & IFF_BROADCAST) { 1255 CSR_WRITE_4(sc, LGE_MODE1, 1256 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1257 } else { 1258 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1259 } 1260 1261 /* Packet padding workaround? */ 1262 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1263 1264 /* No error frames */ 1265 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1266 1267 /* Receive large frames */ 1268 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1269 1270 /* Workaround: disable RX/TX flow control */ 1271 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1272 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1273 1274 /* Make sure to strip CRC from received frames */ 1275 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1276 1277 /* Turn off magic packet mode */ 1278 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1279 1280 /* Turn off all VLAN stuff */ 1281 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1282 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1283 1284 /* Workarond: FIFO overflow */ 1285 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1286 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1287 1288 /* 1289 * Load the multicast filter. 1290 */ 1291 lge_setmulti(sc); 1292 1293 /* 1294 * Enable hardware checksum validation for all received IPv4 1295 * packets, do not reject packets with bad checksums. 1296 */ 1297 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1298 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1299 LGE_MODE2_RX_ERRCSUM); 1300 1301 /* 1302 * Enable the delivery of PHY interrupts based on 1303 * link/speed/duplex status chalges. 1304 */ 1305 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1306 1307 /* Enable receiver and transmitter. */ 1308 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1309 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1310 1311 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1312 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1313 1314 /* 1315 * Enable interrupts. 1316 */ 1317 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1318 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1319 1320 lge_ifmedia_upd(ifp); 1321 1322 ifp->if_flags |= IFF_RUNNING; 1323 ifp->if_flags &= ~IFF_OACTIVE; 1324 1325 splx(s); 1326 1327 timeout_add_sec(&sc->lge_timeout, 1); 1328 } 1329 1330 /* 1331 * Set media options. 1332 */ 1333 int 1334 lge_ifmedia_upd(struct ifnet *ifp) 1335 { 1336 struct lge_softc *sc = ifp->if_softc; 1337 struct mii_data *mii = &sc->lge_mii; 1338 1339 sc->lge_link = 0; 1340 if (mii->mii_instance) { 1341 struct mii_softc *miisc; 1342 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1343 mii_phy_reset(miisc); 1344 } 1345 mii_mediachg(mii); 1346 1347 return (0); 1348 } 1349 1350 /* 1351 * Report current media status. 1352 */ 1353 void 1354 lge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1355 { 1356 struct lge_softc *sc = ifp->if_softc; 1357 struct mii_data *mii = &sc->lge_mii; 1358 1359 mii_pollstat(mii); 1360 ifmr->ifm_active = mii->mii_media_active; 1361 ifmr->ifm_status = mii->mii_media_status; 1362 } 1363 1364 int 1365 lge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1366 { 1367 struct lge_softc *sc = ifp->if_softc; 1368 struct ifaddr *ifa = (struct ifaddr *) data; 1369 struct ifreq *ifr = (struct ifreq *) data; 1370 struct mii_data *mii; 1371 int s, error = 0; 1372 1373 s = splnet(); 1374 1375 switch(command) { 1376 case SIOCSIFADDR: 1377 ifp->if_flags |= IFF_UP; 1378 if (!(ifp->if_flags & IFF_RUNNING)) 1379 lge_init(sc); 1380 #ifdef INET 1381 if (ifa->ifa_addr->sa_family == AF_INET) 1382 arp_ifinit(&sc->arpcom, ifa); 1383 #endif /* INET */ 1384 break; 1385 1386 case SIOCSIFFLAGS: 1387 if (ifp->if_flags & IFF_UP) { 1388 if (ifp->if_flags & IFF_RUNNING && 1389 ifp->if_flags & IFF_PROMISC && 1390 !(sc->lge_if_flags & IFF_PROMISC)) { 1391 CSR_WRITE_4(sc, LGE_MODE1, 1392 LGE_MODE1_SETRST_CTL1| 1393 LGE_MODE1_RX_PROMISC); 1394 lge_setmulti(sc); 1395 } else if (ifp->if_flags & IFF_RUNNING && 1396 !(ifp->if_flags & IFF_PROMISC) && 1397 sc->lge_if_flags & IFF_PROMISC) { 1398 CSR_WRITE_4(sc, LGE_MODE1, 1399 LGE_MODE1_RX_PROMISC); 1400 lge_setmulti(sc); 1401 } else if (ifp->if_flags & IFF_RUNNING && 1402 (ifp->if_flags ^ sc->lge_if_flags) & IFF_ALLMULTI) { 1403 lge_setmulti(sc); 1404 } else { 1405 if (!(ifp->if_flags & IFF_RUNNING)) 1406 lge_init(sc); 1407 } 1408 } else { 1409 if (ifp->if_flags & IFF_RUNNING) 1410 lge_stop(sc); 1411 } 1412 sc->lge_if_flags = ifp->if_flags; 1413 break; 1414 1415 case SIOCGIFMEDIA: 1416 case SIOCSIFMEDIA: 1417 mii = &sc->lge_mii; 1418 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1419 break; 1420 1421 default: 1422 error = ether_ioctl(ifp, &sc->arpcom, command, data); 1423 } 1424 1425 if (error == ENETRESET) { 1426 if (ifp->if_flags & IFF_RUNNING) 1427 lge_setmulti(sc); 1428 error = 0; 1429 } 1430 1431 splx(s); 1432 return (error); 1433 } 1434 1435 void 1436 lge_watchdog(struct ifnet *ifp) 1437 { 1438 struct lge_softc *sc; 1439 1440 sc = ifp->if_softc; 1441 1442 ifp->if_oerrors++; 1443 printf("%s: watchdog timeout\n", sc->sc_dv.dv_xname); 1444 1445 lge_stop(sc); 1446 lge_reset(sc); 1447 lge_init(sc); 1448 1449 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1450 lge_start(ifp); 1451 } 1452 1453 /* 1454 * Stop the adapter and free any mbufs allocated to the 1455 * RX and TX lists. 1456 */ 1457 void 1458 lge_stop(struct lge_softc *sc) 1459 { 1460 int i; 1461 struct ifnet *ifp; 1462 1463 ifp = &sc->arpcom.ac_if; 1464 ifp->if_timer = 0; 1465 timeout_del(&sc->lge_timeout); 1466 1467 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1468 1469 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1470 1471 /* Disable receiver and transmitter. */ 1472 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1473 sc->lge_link = 0; 1474 1475 /* 1476 * Free data in the RX lists. 1477 */ 1478 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1479 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1480 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1481 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1482 } 1483 } 1484 bzero((char *)&sc->lge_ldata->lge_rx_list, 1485 sizeof(sc->lge_ldata->lge_rx_list)); 1486 1487 /* 1488 * Free the TX list buffers. 1489 */ 1490 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1491 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1492 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1493 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1494 } 1495 } 1496 1497 bzero((char *)&sc->lge_ldata->lge_tx_list, 1498 sizeof(sc->lge_ldata->lge_tx_list)); 1499 } 1500