xref: /openbsd-src/sys/dev/pci/if_jmevar.h (revision 0a4809d7170a85b622828ec581dc8597567d6119)
1*0a4809d7Sbrad /*	$OpenBSD: if_jmevar.h,v 1.6 2013/12/07 07:22:37 brad Exp $	*/
21f90365dSjsg /*-
31f90365dSjsg  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
41f90365dSjsg  * All rights reserved.
51f90365dSjsg  *
61f90365dSjsg  * Redistribution and use in source and binary forms, with or without
71f90365dSjsg  * modification, are permitted provided that the following conditions
81f90365dSjsg  * are met:
91f90365dSjsg  * 1. Redistributions of source code must retain the above copyright
101f90365dSjsg  *    notice unmodified, this list of conditions, and the following
111f90365dSjsg  *    disclaimer.
121f90365dSjsg  * 2. Redistributions in binary form must reproduce the above copyright
131f90365dSjsg  *    notice, this list of conditions and the following disclaimer in the
141f90365dSjsg  *    documentation and/or other materials provided with the distribution.
151f90365dSjsg  *
161f90365dSjsg  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
171f90365dSjsg  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
181f90365dSjsg  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
191f90365dSjsg  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
201f90365dSjsg  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
211f90365dSjsg  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
221f90365dSjsg  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
231f90365dSjsg  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
241f90365dSjsg  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
251f90365dSjsg  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
261f90365dSjsg  * SUCH DAMAGE.
271f90365dSjsg  *
281f90365dSjsg  * $FreeBSD: src/sys/dev/jme/if_jmevar.h,v 1.1 2008/05/27 01:42:01 yongari Exp $
291f90365dSjsg  * $DragonFly: src/sys/dev/netif/jme/if_jmevar.h,v 1.4 2008/09/13 04:04:39 sephe Exp $
301f90365dSjsg  */
311f90365dSjsg 
321f90365dSjsg #ifndef	_IF_JMEVAR_H
331f90365dSjsg #define	_IF_JMEVAR_H
341f90365dSjsg 
351f90365dSjsg /*
361f90365dSjsg  * JMC250 supports upto 1024 descriptors and the number of
371f90365dSjsg  * descriptors should be multiple of 16.
381f90365dSjsg  */
391f90365dSjsg #define	JME_TX_RING_CNT		384
401f90365dSjsg #define	JME_RX_RING_CNT		256
411f90365dSjsg /*
421f90365dSjsg  * Tx/Rx descriptor queue base should be 16bytes aligned and
431f90365dSjsg  * should not cross 4G bytes boundary on the 64bits address
441f90365dSjsg  * mode.
451f90365dSjsg  */
461f90365dSjsg #define	JME_TX_RING_ALIGN	16
471f90365dSjsg #define	JME_RX_RING_ALIGN	16
481f90365dSjsg #define	JME_TSO_MAXSEGSIZE	4096
491f90365dSjsg #define	JME_TSO_MAXSIZE		(65535 + sizeof(struct ether_vlan_header))
501f90365dSjsg #define	JME_MAXTXSEGS		32
511f90365dSjsg #define	JME_RX_BUF_ALIGN	sizeof(uint64_t)
521f90365dSjsg #define	JME_SSB_ALIGN		16
531f90365dSjsg 
541f90365dSjsg #define	JME_ADDR_LO(x)		((uint64_t) (x) & 0xFFFFFFFF)
551f90365dSjsg #define	JME_ADDR_HI(x)		((uint64_t) (x) >> 32)
561f90365dSjsg 
571f90365dSjsg #define	JME_MSI_MESSAGES	8
581f90365dSjsg #define	JME_MSIX_MESSAGES	8
591f90365dSjsg 
601f90365dSjsg /* Water mark to kick reclaiming Tx buffers. */
611f90365dSjsg #define	JME_TX_DESC_HIWAT	(JME_TX_RING_CNT - (((JME_TX_RING_CNT) * 3) / 10))
621f90365dSjsg 
631f90365dSjsg /*
641f90365dSjsg  * JMC250 can send 9K jumbo frame on Tx path and can receive
651f90365dSjsg  * 65535 bytes.
661f90365dSjsg  */
671f90365dSjsg #define JME_JUMBO_FRAMELEN	9216
681f90365dSjsg #define JME_JUMBO_MTU							\
691f90365dSjsg 	(JME_JUMBO_FRAMELEN - sizeof(struct ether_vlan_header) -	\
701f90365dSjsg 	 ETHER_HDR_LEN - ETHER_CRC_LEN)
711f90365dSjsg #define	JME_MAX_MTU							\
721f90365dSjsg 	(ETHER_MAX_LEN + sizeof(struct ether_vlan_header) -		\
731f90365dSjsg 	 ETHER_HDR_LEN - ETHER_CRC_LEN)
741f90365dSjsg /*
751f90365dSjsg  * JMC250 can't handle Tx checksum offload/TSO if frame length
761f90365dSjsg  * is larger than its FIFO size(2K). It's also good idea to not
771f90365dSjsg  * use jumbo frame if hardware is running at half-duplex media.
781f90365dSjsg  * Because the jumbo frame may not fit into the Tx FIFO,
791f90365dSjsg  * collisions make hardware fetch frame from host memory with
801f90365dSjsg  * DMA again which in turn slows down Tx performance
811f90365dSjsg  * significantly.
821f90365dSjsg  */
831f90365dSjsg #define	JME_TX_FIFO_SIZE	2000
841f90365dSjsg /*
851f90365dSjsg  * JMC250 has just 4K Rx FIFO. To support jumbo frame that is
861f90365dSjsg  * larger than 4K bytes in length, Rx FIFO threshold should be
871f90365dSjsg  * adjusted to minimize Rx FIFO overrun.
881f90365dSjsg  */
891f90365dSjsg #define	JME_RX_FIFO_SIZE	4000
901f90365dSjsg 
911f90365dSjsg #define	JME_DESC_INC(x, y)	((x) = ((x) + 1) % (y))
921f90365dSjsg 
931f90365dSjsg #define	JME_PROC_MIN		10
941f90365dSjsg #define	JME_PROC_DEFAULT	(JME_RX_RING_CNT / 2)
951f90365dSjsg #define	JME_PROC_MAX		(JME_RX_RING_CNT - 1)
961f90365dSjsg 
971f90365dSjsg struct jme_txdesc {
981f90365dSjsg 	struct mbuf		*tx_m;
991f90365dSjsg 	bus_dmamap_t		tx_dmamap;
1001f90365dSjsg 	int			tx_ndesc;
1011f90365dSjsg 	struct jme_desc		*tx_desc;
1021f90365dSjsg };
1031f90365dSjsg 
1041f90365dSjsg struct jme_rxdesc {
1051f90365dSjsg 	struct mbuf 		*rx_m;
1061f90365dSjsg 	bus_dmamap_t		rx_dmamap;
1071f90365dSjsg 	struct jme_desc		*rx_desc;
1081f90365dSjsg };
1091f90365dSjsg 
1101f90365dSjsg struct jme_chain_data{
1111f90365dSjsg 	bus_dma_tag_t		jme_ring_tag;
1121f90365dSjsg 	bus_dma_tag_t		jme_buffer_tag;
1131f90365dSjsg 	bus_dma_tag_t		jme_ssb_tag;
1141f90365dSjsg 	bus_dmamap_t		jme_ssb_map;
1151f90365dSjsg 	struct jme_txdesc	jme_txdesc[JME_TX_RING_CNT];
1161f90365dSjsg 	bus_dma_tag_t		jme_rx_tag;
1171f90365dSjsg 	struct jme_rxdesc	jme_rxdesc[JME_RX_RING_CNT];
1181f90365dSjsg 	bus_dmamap_t		jme_tx_ring_map;
1191f90365dSjsg 	bus_dma_segment_t	jme_tx_ring_seg;
1201f90365dSjsg 	bus_dmamap_t		jme_rx_ring_map;
1211f90365dSjsg 	bus_dma_segment_t	jme_rx_ring_seg;
1221f90365dSjsg 	bus_dmamap_t		jme_rx_sparemap;
1231f90365dSjsg 
1241f90365dSjsg 	int			jme_tx_prod;
1251f90365dSjsg 	int			jme_tx_cons;
1261f90365dSjsg 	int			jme_tx_cnt;
1271f90365dSjsg 
1281f90365dSjsg 	int			jme_rx_cons;
1291f90365dSjsg 	int			jme_rxlen;
1301f90365dSjsg 	struct mbuf		*jme_rxhead;
1311f90365dSjsg 	struct mbuf		*jme_rxtail;
1321f90365dSjsg };
1331f90365dSjsg 
1341f90365dSjsg struct jme_ring_data {
1351f90365dSjsg 	struct jme_desc		*jme_tx_ring;
1361f90365dSjsg 	bus_dma_segment_t	jme_tx_ring_seg;
1371f90365dSjsg 	bus_addr_t		jme_tx_ring_paddr;
1381f90365dSjsg 	struct jme_desc		*jme_rx_ring;
1391f90365dSjsg 	bus_dma_segment_t	jme_rx_ring_seg;
1401f90365dSjsg 	bus_addr_t		jme_rx_ring_paddr;
1411f90365dSjsg 	struct jme_ssb		*jme_ssb_block;
1421f90365dSjsg 	bus_dma_segment_t	jme_ssb_block_seg;
1431f90365dSjsg 	bus_addr_t		jme_ssb_block_paddr;
1441f90365dSjsg };
1451f90365dSjsg 
1461f90365dSjsg #define JME_TX_RING_ADDR(sc, i)	\
1471f90365dSjsg     ((sc)->jme_rdata.jme_tx_ring_paddr + sizeof(struct jme_desc) * (i))
1481f90365dSjsg #define JME_RX_RING_ADDR(sc, i)	\
1491f90365dSjsg     ((sc)->jme_rdata.jme_rx_ring_paddr + sizeof(struct jme_desc) * (i))
1501f90365dSjsg 
1511f90365dSjsg #define JME_TX_RING_SIZE	\
1521f90365dSjsg     (sizeof(struct jme_desc) * JME_TX_RING_CNT)
1531f90365dSjsg #define JME_RX_RING_SIZE	\
1541f90365dSjsg     (sizeof(struct jme_desc) * JME_RX_RING_CNT)
1551f90365dSjsg #define	JME_SSB_SIZE		sizeof(struct jme_ssb)
1561f90365dSjsg 
1571f90365dSjsg struct jme_dmamap_ctx {
1581f90365dSjsg 	int			nsegs;
1591f90365dSjsg 	bus_dma_segment_t	*segs;
1601f90365dSjsg };
1611f90365dSjsg 
1621f90365dSjsg /*
1631f90365dSjsg  * Software state per device.
1641f90365dSjsg  */
1651f90365dSjsg struct jme_softc {
1661f90365dSjsg 	struct device		sc_dev;
1671f90365dSjsg 	struct arpcom		sc_arpcom;
1681f90365dSjsg 
1691f90365dSjsg 	int			jme_mem_rid;
1701f90365dSjsg 	struct resource		*jme_mem_res;
1711f90365dSjsg 	bus_space_tag_t		jme_mem_bt;
1721f90365dSjsg 	bus_space_handle_t	jme_mem_bh;
1731f90365dSjsg 	bus_size_t		jme_mem_size;
1741f90365dSjsg 	bus_dma_tag_t		sc_dmat;
1751f90365dSjsg 	pci_chipset_tag_t	jme_pct;
1761f90365dSjsg 	pcitag_t		jme_pcitag;
1770cbacf38Sjsg 	uint8_t			jme_revfm;
1781f90365dSjsg 
1791f90365dSjsg 	int			jme_irq_rid;
1801f90365dSjsg 	struct resource		*jme_irq_res;
1811f90365dSjsg 	void			*sc_irq_handle;
1821f90365dSjsg 
1831f90365dSjsg 	struct mii_data		sc_miibus;
1841f90365dSjsg 	int			jme_phyaddr;
1851f90365dSjsg 
1861f90365dSjsg 	uint32_t		jme_tx_dma_size;
1871f90365dSjsg 	uint32_t		jme_rx_dma_size;
1881f90365dSjsg 
1891f90365dSjsg 	uint32_t		jme_caps;
1901f90365dSjsg #define	JME_CAP_FPGA		0x0001
1911f90365dSjsg #define	JME_CAP_PCIE		0x0002
1921f90365dSjsg #define	JME_CAP_PMCAP		0x0004
1931f90365dSjsg #define	JME_CAP_FASTETH		0x0008
1941f90365dSjsg #define	JME_CAP_JUMBO		0x0010
1954a879f88Sbrad 
1964a879f88Sbrad 	uint32_t		jme_workaround;
1974a879f88Sbrad #define JME_WA_CRCERRORS	0x0001
1984a879f88Sbrad #define JME_WA_PACKETLOSS	0x0002
1991f90365dSjsg 
2001f90365dSjsg 	uint32_t		jme_flags;
2011f90365dSjsg #define	JME_FLAG_MSI		0x0001
2021f90365dSjsg #define	JME_FLAG_MSIX		0x0002
2031f90365dSjsg #define	JME_FLAG_DETACH		0x0004
2041f90365dSjsg #define	JME_FLAG_LINK		0x0008
2051f90365dSjsg 
2061f90365dSjsg 	struct timeout		jme_tick_ch;
2071f90365dSjsg 	struct jme_chain_data	jme_cdata;
2081f90365dSjsg 	struct jme_ring_data	jme_rdata;
2091f90365dSjsg 	uint32_t		jme_txcsr;
2101f90365dSjsg 	uint32_t		jme_rxcsr;
2111f90365dSjsg 
2121f90365dSjsg 	/*
2131f90365dSjsg 	 * Sysctl variables
2141f90365dSjsg 	 */
2151f90365dSjsg 	int			jme_process_limit;
2161f90365dSjsg 	int			jme_tx_coal_to;
2171f90365dSjsg 	int			jme_tx_coal_pkt;
2181f90365dSjsg 	int			jme_rx_coal_to;
2191f90365dSjsg 	int			jme_rx_coal_pkt;
2201f90365dSjsg };
2211f90365dSjsg 
2221f90365dSjsg /* Register access macros. */
2231f90365dSjsg #define CSR_WRITE_4(_sc, reg, val)	\
2241f90365dSjsg 	bus_space_write_4((_sc)->jme_mem_bt, (_sc)->jme_mem_bh, (reg), (val))
2251f90365dSjsg #define CSR_READ_4(_sc, reg)		\
2261f90365dSjsg 	bus_space_read_4((_sc)->jme_mem_bt, (_sc)->jme_mem_bh, (reg))
2271f90365dSjsg 
2281f90365dSjsg #define	JME_MAXERR	5
2291f90365dSjsg 
2301f90365dSjsg #define	JME_RXCHAIN_RESET(_sc)						\
2311f90365dSjsg do {									\
2321f90365dSjsg 	(_sc)->jme_cdata.jme_rxhead = NULL;				\
2331f90365dSjsg 	(_sc)->jme_cdata.jme_rxtail = NULL;				\
2341f90365dSjsg 	(_sc)->jme_cdata.jme_rxlen = 0;					\
2351f90365dSjsg } while (0)
2361f90365dSjsg 
2371f90365dSjsg #define	JME_TX_TIMEOUT		5
2381f90365dSjsg #define JME_TIMEOUT		1000
2391f90365dSjsg #define JME_PHY_TIMEOUT		1000
2401f90365dSjsg #define JME_EEPROM_TIMEOUT	1000
2411f90365dSjsg 
2421f90365dSjsg #define JME_TXD_RSVD		1
2431f90365dSjsg 
2441f90365dSjsg #endif
245