1 /* $OpenBSD: if_ixl.c,v 1.71 2020/12/22 06:55:16 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 2013-2015, Intel Corporation 5 * All rights reserved. 6 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 2016,2017 David Gwynne <dlg@openbsd.org> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50 #include "bpfilter.h" 51 #include "kstat.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/proc.h> 56 #include <sys/sockio.h> 57 #include <sys/mbuf.h> 58 #include <sys/kernel.h> 59 #include <sys/socket.h> 60 #include <sys/device.h> 61 #include <sys/pool.h> 62 #include <sys/queue.h> 63 #include <sys/timeout.h> 64 #include <sys/task.h> 65 #include <sys/syslog.h> 66 #include <sys/intrmap.h> 67 68 #include <machine/bus.h> 69 #include <machine/intr.h> 70 71 #include <net/if.h> 72 #include <net/if_dl.h> 73 #include <net/if_media.h> 74 #include <net/toeplitz.h> 75 76 #if NBPFILTER > 0 77 #include <net/bpf.h> 78 #endif 79 80 #if NKSTAT > 0 81 #include <sys/kstat.h> 82 #endif 83 84 #include <netinet/in.h> 85 #include <netinet/if_ether.h> 86 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/pcidevs.h> 90 91 #ifdef __sparc64__ 92 #include <dev/ofw/openfirm.h> 93 #endif 94 95 #ifndef CACHE_LINE_SIZE 96 #define CACHE_LINE_SIZE 64 97 #endif 98 99 #define IXL_MAX_VECTORS 8 /* XXX this is pretty arbitrary */ 100 101 #define I40E_MASK(mask, shift) ((mask) << (shift)) 102 #define I40E_PF_RESET_WAIT_COUNT 200 103 #define I40E_AQ_LARGE_BUF 512 104 105 /* bitfields for Tx queue mapping in QTX_CTL */ 106 #define I40E_QTX_CTL_VF_QUEUE 0x0 107 #define I40E_QTX_CTL_VM_QUEUE 0x1 108 #define I40E_QTX_CTL_PF_QUEUE 0x2 109 110 #define I40E_QUEUE_TYPE_EOL 0x7ff 111 #define I40E_INTR_NOTX_QUEUE 0 112 113 #define I40E_QUEUE_TYPE_RX 0x0 114 #define I40E_QUEUE_TYPE_TX 0x1 115 #define I40E_QUEUE_TYPE_PE_CEQ 0x2 116 #define I40E_QUEUE_TYPE_UNKNOWN 0x3 117 118 #define I40E_ITR_INDEX_RX 0x0 119 #define I40E_ITR_INDEX_TX 0x1 120 #define I40E_ITR_INDEX_OTHER 0x2 121 #define I40E_ITR_INDEX_NONE 0x3 122 123 #include <dev/pci/if_ixlreg.h> 124 125 #define I40E_INTR_NOTX_QUEUE 0 126 #define I40E_INTR_NOTX_INTR 0 127 #define I40E_INTR_NOTX_RX_QUEUE 0 128 #define I40E_INTR_NOTX_TX_QUEUE 1 129 #define I40E_INTR_NOTX_RX_MASK I40E_PFINT_ICR0_QUEUE_0_MASK 130 #define I40E_INTR_NOTX_TX_MASK I40E_PFINT_ICR0_QUEUE_1_MASK 131 132 struct ixl_aq_desc { 133 uint16_t iaq_flags; 134 #define IXL_AQ_DD (1U << 0) 135 #define IXL_AQ_CMP (1U << 1) 136 #define IXL_AQ_ERR (1U << 2) 137 #define IXL_AQ_VFE (1U << 3) 138 #define IXL_AQ_LB (1U << 9) 139 #define IXL_AQ_RD (1U << 10) 140 #define IXL_AQ_VFC (1U << 11) 141 #define IXL_AQ_BUF (1U << 12) 142 #define IXL_AQ_SI (1U << 13) 143 #define IXL_AQ_EI (1U << 14) 144 #define IXL_AQ_FE (1U << 15) 145 146 #define IXL_AQ_FLAGS_FMT "\020" "\020FE" "\017EI" "\016SI" "\015BUF" \ 147 "\014VFC" "\013DB" "\012LB" "\004VFE" \ 148 "\003ERR" "\002CMP" "\001DD" 149 150 uint16_t iaq_opcode; 151 152 uint16_t iaq_datalen; 153 uint16_t iaq_retval; 154 155 uint64_t iaq_cookie; 156 157 uint32_t iaq_param[4]; 158 /* iaq_data_hi iaq_param[2] */ 159 /* iaq_data_lo iaq_param[3] */ 160 } __packed __aligned(8); 161 162 /* aq commands */ 163 #define IXL_AQ_OP_GET_VERSION 0x0001 164 #define IXL_AQ_OP_DRIVER_VERSION 0x0002 165 #define IXL_AQ_OP_QUEUE_SHUTDOWN 0x0003 166 #define IXL_AQ_OP_SET_PF_CONTEXT 0x0004 167 #define IXL_AQ_OP_GET_AQ_ERR_REASON 0x0005 168 #define IXL_AQ_OP_REQUEST_RESOURCE 0x0008 169 #define IXL_AQ_OP_RELEASE_RESOURCE 0x0009 170 #define IXL_AQ_OP_LIST_FUNC_CAP 0x000a 171 #define IXL_AQ_OP_LIST_DEV_CAP 0x000b 172 #define IXL_AQ_OP_MAC_ADDRESS_READ 0x0107 173 #define IXL_AQ_OP_CLEAR_PXE_MODE 0x0110 174 #define IXL_AQ_OP_SWITCH_GET_CONFIG 0x0200 175 #define IXL_AQ_OP_RX_CTL_READ 0x0206 176 #define IXL_AQ_OP_RX_CTL_WRITE 0x0207 177 #define IXL_AQ_OP_ADD_VSI 0x0210 178 #define IXL_AQ_OP_UPD_VSI_PARAMS 0x0211 179 #define IXL_AQ_OP_GET_VSI_PARAMS 0x0212 180 #define IXL_AQ_OP_ADD_VEB 0x0230 181 #define IXL_AQ_OP_UPD_VEB_PARAMS 0x0231 182 #define IXL_AQ_OP_GET_VEB_PARAMS 0x0232 183 #define IXL_AQ_OP_ADD_MACVLAN 0x0250 184 #define IXL_AQ_OP_REMOVE_MACVLAN 0x0251 185 #define IXL_AQ_OP_SET_VSI_PROMISC 0x0254 186 #define IXL_AQ_OP_PHY_GET_ABILITIES 0x0600 187 #define IXL_AQ_OP_PHY_SET_CONFIG 0x0601 188 #define IXL_AQ_OP_PHY_SET_MAC_CONFIG 0x0603 189 #define IXL_AQ_OP_PHY_RESTART_AN 0x0605 190 #define IXL_AQ_OP_PHY_LINK_STATUS 0x0607 191 #define IXL_AQ_OP_PHY_SET_EVENT_MASK 0x0613 192 #define IXL_AQ_OP_PHY_SET_REGISTER 0x0628 193 #define IXL_AQ_OP_PHY_GET_REGISTER 0x0629 194 #define IXL_AQ_OP_LLDP_GET_MIB 0x0a00 195 #define IXL_AQ_OP_LLDP_MIB_CHG_EV 0x0a01 196 #define IXL_AQ_OP_LLDP_ADD_TLV 0x0a02 197 #define IXL_AQ_OP_LLDP_UPD_TLV 0x0a03 198 #define IXL_AQ_OP_LLDP_DEL_TLV 0x0a04 199 #define IXL_AQ_OP_LLDP_STOP_AGENT 0x0a05 200 #define IXL_AQ_OP_LLDP_START_AGENT 0x0a06 201 #define IXL_AQ_OP_LLDP_GET_CEE_DCBX 0x0a07 202 #define IXL_AQ_OP_LLDP_SPECIFIC_AGENT 0x0a09 203 #define IXL_AQ_OP_SET_RSS_KEY 0x0b02 /* 722 only */ 204 #define IXL_AQ_OP_SET_RSS_LUT 0x0b03 /* 722 only */ 205 #define IXL_AQ_OP_GET_RSS_KEY 0x0b04 /* 722 only */ 206 #define IXL_AQ_OP_GET_RSS_LUT 0x0b05 /* 722 only */ 207 208 struct ixl_aq_mac_addresses { 209 uint8_t pf_lan[ETHER_ADDR_LEN]; 210 uint8_t pf_san[ETHER_ADDR_LEN]; 211 uint8_t port[ETHER_ADDR_LEN]; 212 uint8_t pf_wol[ETHER_ADDR_LEN]; 213 } __packed; 214 215 #define IXL_AQ_MAC_PF_LAN_VALID (1U << 4) 216 #define IXL_AQ_MAC_PF_SAN_VALID (1U << 5) 217 #define IXL_AQ_MAC_PORT_VALID (1U << 6) 218 #define IXL_AQ_MAC_PF_WOL_VALID (1U << 7) 219 220 struct ixl_aq_capability { 221 uint16_t cap_id; 222 #define IXL_AQ_CAP_SWITCH_MODE 0x0001 223 #define IXL_AQ_CAP_MNG_MODE 0x0002 224 #define IXL_AQ_CAP_NPAR_ACTIVE 0x0003 225 #define IXL_AQ_CAP_OS2BMC_CAP 0x0004 226 #define IXL_AQ_CAP_FUNCTIONS_VALID 0x0005 227 #define IXL_AQ_CAP_ALTERNATE_RAM 0x0006 228 #define IXL_AQ_CAP_WOL_AND_PROXY 0x0008 229 #define IXL_AQ_CAP_SRIOV 0x0012 230 #define IXL_AQ_CAP_VF 0x0013 231 #define IXL_AQ_CAP_VMDQ 0x0014 232 #define IXL_AQ_CAP_8021QBG 0x0015 233 #define IXL_AQ_CAP_8021QBR 0x0016 234 #define IXL_AQ_CAP_VSI 0x0017 235 #define IXL_AQ_CAP_DCB 0x0018 236 #define IXL_AQ_CAP_FCOE 0x0021 237 #define IXL_AQ_CAP_ISCSI 0x0022 238 #define IXL_AQ_CAP_RSS 0x0040 239 #define IXL_AQ_CAP_RXQ 0x0041 240 #define IXL_AQ_CAP_TXQ 0x0042 241 #define IXL_AQ_CAP_MSIX 0x0043 242 #define IXL_AQ_CAP_VF_MSIX 0x0044 243 #define IXL_AQ_CAP_FLOW_DIRECTOR 0x0045 244 #define IXL_AQ_CAP_1588 0x0046 245 #define IXL_AQ_CAP_IWARP 0x0051 246 #define IXL_AQ_CAP_LED 0x0061 247 #define IXL_AQ_CAP_SDP 0x0062 248 #define IXL_AQ_CAP_MDIO 0x0063 249 #define IXL_AQ_CAP_WSR_PROT 0x0064 250 #define IXL_AQ_CAP_NVM_MGMT 0x0080 251 #define IXL_AQ_CAP_FLEX10 0x00F1 252 #define IXL_AQ_CAP_CEM 0x00F2 253 uint8_t major_rev; 254 uint8_t minor_rev; 255 uint32_t number; 256 uint32_t logical_id; 257 uint32_t phys_id; 258 uint8_t _reserved[16]; 259 } __packed __aligned(4); 260 261 #define IXL_LLDP_SHUTDOWN 0x1 262 263 struct ixl_aq_switch_config { 264 uint16_t num_reported; 265 uint16_t num_total; 266 uint8_t _reserved[12]; 267 } __packed __aligned(4); 268 269 struct ixl_aq_switch_config_element { 270 uint8_t type; 271 #define IXL_AQ_SW_ELEM_TYPE_MAC 1 272 #define IXL_AQ_SW_ELEM_TYPE_PF 2 273 #define IXL_AQ_SW_ELEM_TYPE_VF 3 274 #define IXL_AQ_SW_ELEM_TYPE_EMP 4 275 #define IXL_AQ_SW_ELEM_TYPE_BMC 5 276 #define IXL_AQ_SW_ELEM_TYPE_PV 16 277 #define IXL_AQ_SW_ELEM_TYPE_VEB 17 278 #define IXL_AQ_SW_ELEM_TYPE_PA 18 279 #define IXL_AQ_SW_ELEM_TYPE_VSI 19 280 uint8_t revision; 281 #define IXL_AQ_SW_ELEM_REV_1 1 282 uint16_t seid; 283 284 uint16_t uplink_seid; 285 uint16_t downlink_seid; 286 287 uint8_t _reserved[3]; 288 uint8_t connection_type; 289 #define IXL_AQ_CONN_TYPE_REGULAR 0x1 290 #define IXL_AQ_CONN_TYPE_DEFAULT 0x2 291 #define IXL_AQ_CONN_TYPE_CASCADED 0x3 292 293 uint16_t scheduler_id; 294 uint16_t element_info; 295 } __packed __aligned(4); 296 297 #define IXL_PHY_TYPE_SGMII 0x00 298 #define IXL_PHY_TYPE_1000BASE_KX 0x01 299 #define IXL_PHY_TYPE_10GBASE_KX4 0x02 300 #define IXL_PHY_TYPE_10GBASE_KR 0x03 301 #define IXL_PHY_TYPE_40GBASE_KR4 0x04 302 #define IXL_PHY_TYPE_XAUI 0x05 303 #define IXL_PHY_TYPE_XFI 0x06 304 #define IXL_PHY_TYPE_SFI 0x07 305 #define IXL_PHY_TYPE_XLAUI 0x08 306 #define IXL_PHY_TYPE_XLPPI 0x09 307 #define IXL_PHY_TYPE_40GBASE_CR4_CU 0x0a 308 #define IXL_PHY_TYPE_10GBASE_CR1_CU 0x0b 309 #define IXL_PHY_TYPE_10GBASE_AOC 0x0c 310 #define IXL_PHY_TYPE_40GBASE_AOC 0x0d 311 #define IXL_PHY_TYPE_100BASE_TX 0x11 312 #define IXL_PHY_TYPE_1000BASE_T 0x12 313 #define IXL_PHY_TYPE_10GBASE_T 0x13 314 #define IXL_PHY_TYPE_10GBASE_SR 0x14 315 #define IXL_PHY_TYPE_10GBASE_LR 0x15 316 #define IXL_PHY_TYPE_10GBASE_SFPP_CU 0x16 317 #define IXL_PHY_TYPE_10GBASE_CR1 0x17 318 #define IXL_PHY_TYPE_40GBASE_CR4 0x18 319 #define IXL_PHY_TYPE_40GBASE_SR4 0x19 320 #define IXL_PHY_TYPE_40GBASE_LR4 0x1a 321 #define IXL_PHY_TYPE_1000BASE_SX 0x1b 322 #define IXL_PHY_TYPE_1000BASE_LX 0x1c 323 #define IXL_PHY_TYPE_1000BASE_T_OPTICAL 0x1d 324 #define IXL_PHY_TYPE_20GBASE_KR2 0x1e 325 326 #define IXL_PHY_TYPE_25GBASE_KR 0x1f 327 #define IXL_PHY_TYPE_25GBASE_CR 0x20 328 #define IXL_PHY_TYPE_25GBASE_SR 0x21 329 #define IXL_PHY_TYPE_25GBASE_LR 0x22 330 #define IXL_PHY_TYPE_25GBASE_AOC 0x23 331 #define IXL_PHY_TYPE_25GBASE_ACC 0x24 332 333 struct ixl_aq_module_desc { 334 uint8_t oui[3]; 335 uint8_t _reserved1; 336 uint8_t part_number[16]; 337 uint8_t revision[4]; 338 uint8_t _reserved2[8]; 339 } __packed __aligned(4); 340 341 struct ixl_aq_phy_abilities { 342 uint32_t phy_type; 343 344 uint8_t link_speed; 345 #define IXL_AQ_PHY_LINK_SPEED_100MB (1 << 1) 346 #define IXL_AQ_PHY_LINK_SPEED_1000MB (1 << 2) 347 #define IXL_AQ_PHY_LINK_SPEED_10GB (1 << 3) 348 #define IXL_AQ_PHY_LINK_SPEED_40GB (1 << 4) 349 #define IXL_AQ_PHY_LINK_SPEED_20GB (1 << 5) 350 #define IXL_AQ_PHY_LINK_SPEED_25GB (1 << 6) 351 uint8_t abilities; 352 uint16_t eee_capability; 353 354 uint32_t eeer_val; 355 356 uint8_t d3_lpan; 357 uint8_t phy_type_ext; 358 #define IXL_AQ_PHY_TYPE_EXT_25G_KR 0x01 359 #define IXL_AQ_PHY_TYPE_EXT_25G_CR 0x02 360 #define IXL_AQ_PHY_TYPE_EXT_25G_SR 0x04 361 #define IXL_AQ_PHY_TYPE_EXT_25G_LR 0x08 362 uint8_t fec_cfg_curr_mod_ext_info; 363 #define IXL_AQ_ENABLE_FEC_KR 0x01 364 #define IXL_AQ_ENABLE_FEC_RS 0x02 365 #define IXL_AQ_REQUEST_FEC_KR 0x04 366 #define IXL_AQ_REQUEST_FEC_RS 0x08 367 #define IXL_AQ_ENABLE_FEC_AUTO 0x10 368 #define IXL_AQ_MODULE_TYPE_EXT_MASK 0xe0 369 #define IXL_AQ_MODULE_TYPE_EXT_SHIFT 5 370 uint8_t ext_comp_code; 371 372 uint8_t phy_id[4]; 373 374 uint8_t module_type[3]; 375 #define IXL_SFF8024_ID_SFP 0x03 376 #define IXL_SFF8024_ID_QSFP 0x0c 377 #define IXL_SFF8024_ID_QSFP_PLUS 0x0d 378 #define IXL_SFF8024_ID_QSFP28 0x11 379 uint8_t qualified_module_count; 380 #define IXL_AQ_PHY_MAX_QMS 16 381 struct ixl_aq_module_desc 382 qualified_module[IXL_AQ_PHY_MAX_QMS]; 383 } __packed __aligned(4); 384 385 struct ixl_aq_link_param { 386 uint8_t notify; 387 #define IXL_AQ_LINK_NOTIFY 0x03 388 uint8_t _reserved1; 389 uint8_t phy; 390 uint8_t speed; 391 uint8_t status; 392 uint8_t _reserved2[11]; 393 } __packed __aligned(4); 394 395 struct ixl_aq_vsi_param { 396 uint16_t uplink_seid; 397 uint8_t connect_type; 398 #define IXL_AQ_VSI_CONN_TYPE_NORMAL (0x1) 399 #define IXL_AQ_VSI_CONN_TYPE_DEFAULT (0x2) 400 #define IXL_AQ_VSI_CONN_TYPE_CASCADED (0x3) 401 uint8_t _reserved1; 402 403 uint8_t vf_id; 404 uint8_t _reserved2; 405 uint16_t vsi_flags; 406 #define IXL_AQ_VSI_TYPE_SHIFT 0x0 407 #define IXL_AQ_VSI_TYPE_MASK (0x3 << IXL_AQ_VSI_TYPE_SHIFT) 408 #define IXL_AQ_VSI_TYPE_VF 0x0 409 #define IXL_AQ_VSI_TYPE_VMDQ2 0x1 410 #define IXL_AQ_VSI_TYPE_PF 0x2 411 #define IXL_AQ_VSI_TYPE_EMP_MNG 0x3 412 #define IXL_AQ_VSI_FLAG_CASCADED_PV 0x4 413 414 uint32_t addr_hi; 415 uint32_t addr_lo; 416 } __packed __aligned(16); 417 418 struct ixl_aq_add_macvlan { 419 uint16_t num_addrs; 420 uint16_t seid0; 421 uint16_t seid1; 422 uint16_t seid2; 423 uint32_t addr_hi; 424 uint32_t addr_lo; 425 } __packed __aligned(16); 426 427 struct ixl_aq_add_macvlan_elem { 428 uint8_t macaddr[6]; 429 uint16_t vlan; 430 uint16_t flags; 431 #define IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH 0x0001 432 #define IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN 0x0004 433 uint16_t queue; 434 uint32_t _reserved; 435 } __packed __aligned(16); 436 437 struct ixl_aq_remove_macvlan { 438 uint16_t num_addrs; 439 uint16_t seid0; 440 uint16_t seid1; 441 uint16_t seid2; 442 uint32_t addr_hi; 443 uint32_t addr_lo; 444 } __packed __aligned(16); 445 446 struct ixl_aq_remove_macvlan_elem { 447 uint8_t macaddr[6]; 448 uint16_t vlan; 449 uint8_t flags; 450 #define IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH 0x0001 451 #define IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN 0x0008 452 uint8_t _reserved[7]; 453 } __packed __aligned(16); 454 455 struct ixl_aq_vsi_reply { 456 uint16_t seid; 457 uint16_t vsi_number; 458 459 uint16_t vsis_used; 460 uint16_t vsis_free; 461 462 uint32_t addr_hi; 463 uint32_t addr_lo; 464 } __packed __aligned(16); 465 466 struct ixl_aq_vsi_data { 467 /* first 96 byte are written by SW */ 468 uint16_t valid_sections; 469 #define IXL_AQ_VSI_VALID_SWITCH (1 << 0) 470 #define IXL_AQ_VSI_VALID_SECURITY (1 << 1) 471 #define IXL_AQ_VSI_VALID_VLAN (1 << 2) 472 #define IXL_AQ_VSI_VALID_CAS_PV (1 << 3) 473 #define IXL_AQ_VSI_VALID_INGRESS_UP (1 << 4) 474 #define IXL_AQ_VSI_VALID_EGRESS_UP (1 << 5) 475 #define IXL_AQ_VSI_VALID_QUEUE_MAP (1 << 6) 476 #define IXL_AQ_VSI_VALID_QUEUE_OPT (1 << 7) 477 #define IXL_AQ_VSI_VALID_OUTER_UP (1 << 8) 478 #define IXL_AQ_VSI_VALID_SCHED (1 << 9) 479 /* switch section */ 480 uint16_t switch_id; 481 #define IXL_AQ_VSI_SWITCH_ID_SHIFT 0 482 #define IXL_AQ_VSI_SWITCH_ID_MASK (0xfff << IXL_AQ_VSI_SWITCH_ID_SHIFT) 483 #define IXL_AQ_VSI_SWITCH_NOT_STAG (1 << 12) 484 #define IXL_AQ_VSI_SWITCH_LOCAL_LB (1 << 14) 485 486 uint8_t _reserved1[2]; 487 /* security section */ 488 uint8_t sec_flags; 489 #define IXL_AQ_VSI_SEC_ALLOW_DEST_OVRD (1 << 0) 490 #define IXL_AQ_VSI_SEC_ENABLE_VLAN_CHK (1 << 1) 491 #define IXL_AQ_VSI_SEC_ENABLE_MAC_CHK (1 << 2) 492 uint8_t _reserved2; 493 494 /* vlan section */ 495 uint16_t pvid; 496 uint16_t fcoe_pvid; 497 498 uint8_t port_vlan_flags; 499 #define IXL_AQ_VSI_PVLAN_MODE_SHIFT 0 500 #define IXL_AQ_VSI_PVLAN_MODE_MASK (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 501 #define IXL_AQ_VSI_PVLAN_MODE_TAGGED (0x1 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 502 #define IXL_AQ_VSI_PVLAN_MODE_UNTAGGED (0x2 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 503 #define IXL_AQ_VSI_PVLAN_MODE_ALL (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 504 #define IXL_AQ_VSI_PVLAN_INSERT_PVID (0x4 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 505 #define IXL_AQ_VSI_PVLAN_EMOD_SHIFT 0x3 506 #define IXL_AQ_VSI_PVLAN_EMOD_MASK (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 507 #define IXL_AQ_VSI_PVLAN_EMOD_STR_BOTH (0x0 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 508 #define IXL_AQ_VSI_PVLAN_EMOD_STR_UP (0x1 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 509 #define IXL_AQ_VSI_PVLAN_EMOD_STR (0x2 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 510 #define IXL_AQ_VSI_PVLAN_EMOD_NOTHING (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 511 uint8_t _reserved3[3]; 512 513 /* ingress egress up section */ 514 uint32_t ingress_table; 515 #define IXL_AQ_VSI_UP_SHIFT(_up) ((_up) * 3) 516 #define IXL_AQ_VSI_UP_MASK(_up) (0x7 << (IXL_AQ_VSI_UP_SHIFT(_up)) 517 uint32_t egress_table; 518 519 /* cascaded pv section */ 520 uint16_t cas_pv_tag; 521 uint8_t cas_pv_flags; 522 #define IXL_AQ_VSI_CAS_PV_TAGX_SHIFT 0 523 #define IXL_AQ_VSI_CAS_PV_TAGX_MASK (0x3 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 524 #define IXL_AQ_VSI_CAS_PV_TAGX_LEAVE (0x0 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 525 #define IXL_AQ_VSI_CAS_PV_TAGX_REMOVE (0x1 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 526 #define IXL_AQ_VSI_CAS_PV_TAGX_COPY (0x2 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 527 #define IXL_AQ_VSI_CAS_PV_INSERT_TAG (1 << 4) 528 #define IXL_AQ_VSI_CAS_PV_ETAG_PRUNE (1 << 5) 529 #define IXL_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG \ 530 (1 << 6) 531 uint8_t _reserved4; 532 533 /* queue mapping section */ 534 uint16_t mapping_flags; 535 #define IXL_AQ_VSI_QUE_MAP_MASK 0x1 536 #define IXL_AQ_VSI_QUE_MAP_CONTIG 0x0 537 #define IXL_AQ_VSI_QUE_MAP_NONCONTIG 0x1 538 uint16_t queue_mapping[16]; 539 #define IXL_AQ_VSI_QUEUE_SHIFT 0x0 540 #define IXL_AQ_VSI_QUEUE_MASK (0x7ff << IXL_AQ_VSI_QUEUE_SHIFT) 541 uint16_t tc_mapping[8]; 542 #define IXL_AQ_VSI_TC_Q_OFFSET_SHIFT 0 543 #define IXL_AQ_VSI_TC_Q_OFFSET_MASK (0x1ff << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) 544 #define IXL_AQ_VSI_TC_Q_NUMBER_SHIFT 9 545 #define IXL_AQ_VSI_TC_Q_NUMBER_MASK (0x7 << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT) 546 547 /* queueing option section */ 548 uint8_t queueing_opt_flags; 549 #define IXL_AQ_VSI_QUE_OPT_MCAST_UDP_EN (1 << 2) 550 #define IXL_AQ_VSI_QUE_OPT_UCAST_UDP_EN (1 << 3) 551 #define IXL_AQ_VSI_QUE_OPT_TCP_EN (1 << 4) 552 #define IXL_AQ_VSI_QUE_OPT_FCOE_EN (1 << 5) 553 #define IXL_AQ_VSI_QUE_OPT_RSS_LUT_PF 0 554 #define IXL_AQ_VSI_QUE_OPT_RSS_LUT_VSI (1 << 6) 555 uint8_t _reserved5[3]; 556 557 /* scheduler section */ 558 uint8_t up_enable_bits; 559 uint8_t _reserved6; 560 561 /* outer up section */ 562 uint32_t outer_up_table; /* same as ingress/egress tables */ 563 uint8_t _reserved7[8]; 564 565 /* last 32 bytes are written by FW */ 566 uint16_t qs_handle[8]; 567 #define IXL_AQ_VSI_QS_HANDLE_INVALID 0xffff 568 uint16_t stat_counter_idx; 569 uint16_t sched_id; 570 571 uint8_t _reserved8[12]; 572 } __packed __aligned(8); 573 574 CTASSERT(sizeof(struct ixl_aq_vsi_data) == 128); 575 576 struct ixl_aq_vsi_promisc_param { 577 uint16_t flags; 578 uint16_t valid_flags; 579 #define IXL_AQ_VSI_PROMISC_FLAG_UCAST (1 << 0) 580 #define IXL_AQ_VSI_PROMISC_FLAG_MCAST (1 << 1) 581 #define IXL_AQ_VSI_PROMISC_FLAG_BCAST (1 << 2) 582 #define IXL_AQ_VSI_PROMISC_FLAG_DFLT (1 << 3) 583 #define IXL_AQ_VSI_PROMISC_FLAG_VLAN (1 << 4) 584 #define IXL_AQ_VSI_PROMISC_FLAG_RXONLY (1 << 15) 585 586 uint16_t seid; 587 #define IXL_AQ_VSI_PROMISC_SEID_VALID (1 << 15) 588 uint16_t vlan; 589 #define IXL_AQ_VSI_PROMISC_VLAN_VALID (1 << 15) 590 uint32_t reserved[2]; 591 } __packed __aligned(8); 592 593 struct ixl_aq_veb_param { 594 uint16_t uplink_seid; 595 uint16_t downlink_seid; 596 uint16_t veb_flags; 597 #define IXL_AQ_ADD_VEB_FLOATING (1 << 0) 598 #define IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT 1 599 #define IXL_AQ_ADD_VEB_PORT_TYPE_MASK (0x3 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 600 #define IXL_AQ_ADD_VEB_PORT_TYPE_DEFAULT \ 601 (0x2 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 602 #define IXL_AQ_ADD_VEB_PORT_TYPE_DATA (0x4 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 603 #define IXL_AQ_ADD_VEB_ENABLE_L2_FILTER (1 << 3) /* deprecated */ 604 #define IXL_AQ_ADD_VEB_DISABLE_STATS (1 << 4) 605 uint8_t enable_tcs; 606 uint8_t _reserved[9]; 607 } __packed __aligned(16); 608 609 struct ixl_aq_veb_reply { 610 uint16_t _reserved1; 611 uint16_t _reserved2; 612 uint16_t _reserved3; 613 uint16_t switch_seid; 614 uint16_t veb_seid; 615 #define IXL_AQ_VEB_ERR_FLAG_NO_VEB (1 << 0) 616 #define IXL_AQ_VEB_ERR_FLAG_NO_SCHED (1 << 1) 617 #define IXL_AQ_VEB_ERR_FLAG_NO_COUNTER (1 << 2) 618 #define IXL_AQ_VEB_ERR_FLAG_NO_ENTRY (1 << 3); 619 uint16_t statistic_index; 620 uint16_t vebs_used; 621 uint16_t vebs_free; 622 } __packed __aligned(16); 623 624 /* GET PHY ABILITIES param[0] */ 625 #define IXL_AQ_PHY_REPORT_QUAL (1 << 0) 626 #define IXL_AQ_PHY_REPORT_INIT (1 << 1) 627 628 struct ixl_aq_phy_reg_access { 629 uint8_t phy_iface; 630 #define IXL_AQ_PHY_IF_INTERNAL 0 631 #define IXL_AQ_PHY_IF_EXTERNAL 1 632 #define IXL_AQ_PHY_IF_MODULE 2 633 uint8_t dev_addr; 634 uint16_t recall; 635 #define IXL_AQ_PHY_QSFP_DEV_ADDR 0 636 #define IXL_AQ_PHY_QSFP_LAST 1 637 uint32_t reg; 638 uint32_t val; 639 uint32_t _reserved2; 640 } __packed __aligned(16); 641 642 /* RESTART_AN param[0] */ 643 #define IXL_AQ_PHY_RESTART_AN (1 << 1) 644 #define IXL_AQ_PHY_LINK_ENABLE (1 << 2) 645 646 struct ixl_aq_link_status { /* this occupies the iaq_param space */ 647 uint16_t command_flags; /* only field set on command */ 648 #define IXL_AQ_LSE_MASK 0x3 649 #define IXL_AQ_LSE_NOP 0x0 650 #define IXL_AQ_LSE_DISABLE 0x2 651 #define IXL_AQ_LSE_ENABLE 0x3 652 #define IXL_AQ_LSE_IS_ENABLED 0x1 /* only set in response */ 653 uint8_t phy_type; 654 uint8_t link_speed; 655 #define IXL_AQ_LINK_SPEED_1GB (1 << 2) 656 #define IXL_AQ_LINK_SPEED_10GB (1 << 3) 657 #define IXL_AQ_LINK_SPEED_40GB (1 << 4) 658 #define IXL_AQ_LINK_SPEED_25GB (1 << 6) 659 uint8_t link_info; 660 #define IXL_AQ_LINK_UP_FUNCTION 0x01 661 #define IXL_AQ_LINK_FAULT 0x02 662 #define IXL_AQ_LINK_FAULT_TX 0x04 663 #define IXL_AQ_LINK_FAULT_RX 0x08 664 #define IXL_AQ_LINK_FAULT_REMOTE 0x10 665 #define IXL_AQ_LINK_UP_PORT 0x20 666 #define IXL_AQ_MEDIA_AVAILABLE 0x40 667 #define IXL_AQ_SIGNAL_DETECT 0x80 668 uint8_t an_info; 669 #define IXL_AQ_AN_COMPLETED 0x01 670 #define IXL_AQ_LP_AN_ABILITY 0x02 671 #define IXL_AQ_PD_FAULT 0x04 672 #define IXL_AQ_FEC_EN 0x08 673 #define IXL_AQ_PHY_LOW_POWER 0x10 674 #define IXL_AQ_LINK_PAUSE_TX 0x20 675 #define IXL_AQ_LINK_PAUSE_RX 0x40 676 #define IXL_AQ_QUALIFIED_MODULE 0x80 677 678 uint8_t ext_info; 679 #define IXL_AQ_LINK_PHY_TEMP_ALARM 0x01 680 #define IXL_AQ_LINK_XCESSIVE_ERRORS 0x02 681 #define IXL_AQ_LINK_TX_SHIFT 0x02 682 #define IXL_AQ_LINK_TX_MASK (0x03 << IXL_AQ_LINK_TX_SHIFT) 683 #define IXL_AQ_LINK_TX_ACTIVE 0x00 684 #define IXL_AQ_LINK_TX_DRAINED 0x01 685 #define IXL_AQ_LINK_TX_FLUSHED 0x03 686 #define IXL_AQ_LINK_FORCED_40G 0x10 687 /* 25G Error Codes */ 688 #define IXL_AQ_25G_NO_ERR 0X00 689 #define IXL_AQ_25G_NOT_PRESENT 0X01 690 #define IXL_AQ_25G_NVM_CRC_ERR 0X02 691 #define IXL_AQ_25G_SBUS_UCODE_ERR 0X03 692 #define IXL_AQ_25G_SERDES_UCODE_ERR 0X04 693 #define IXL_AQ_25G_NIMB_UCODE_ERR 0X05 694 uint8_t loopback; 695 uint16_t max_frame_size; 696 697 uint8_t config; 698 #define IXL_AQ_CONFIG_FEC_KR_ENA 0x01 699 #define IXL_AQ_CONFIG_FEC_RS_ENA 0x02 700 #define IXL_AQ_CONFIG_CRC_ENA 0x04 701 #define IXL_AQ_CONFIG_PACING_MASK 0x78 702 uint8_t power_desc; 703 #define IXL_AQ_LINK_POWER_CLASS_1 0x00 704 #define IXL_AQ_LINK_POWER_CLASS_2 0x01 705 #define IXL_AQ_LINK_POWER_CLASS_3 0x02 706 #define IXL_AQ_LINK_POWER_CLASS_4 0x03 707 #define IXL_AQ_PWR_CLASS_MASK 0x03 708 709 uint8_t reserved[4]; 710 } __packed __aligned(4); 711 /* event mask command flags for param[2] */ 712 #define IXL_AQ_PHY_EV_MASK 0x3ff 713 #define IXL_AQ_PHY_EV_LINK_UPDOWN (1 << 1) 714 #define IXL_AQ_PHY_EV_MEDIA_NA (1 << 2) 715 #define IXL_AQ_PHY_EV_LINK_FAULT (1 << 3) 716 #define IXL_AQ_PHY_EV_PHY_TEMP_ALARM (1 << 4) 717 #define IXL_AQ_PHY_EV_EXCESS_ERRORS (1 << 5) 718 #define IXL_AQ_PHY_EV_SIGNAL_DETECT (1 << 6) 719 #define IXL_AQ_PHY_EV_AN_COMPLETED (1 << 7) 720 #define IXL_AQ_PHY_EV_MODULE_QUAL_FAIL (1 << 8) 721 #define IXL_AQ_PHY_EV_PORT_TX_SUSPENDED (1 << 9) 722 723 struct ixl_aq_rss_lut { /* 722 */ 724 #define IXL_AQ_SET_RSS_LUT_VSI_VALID (1 << 15) 725 #define IXL_AQ_SET_RSS_LUT_VSI_ID_SHIFT 0 726 #define IXL_AQ_SET_RSS_LUT_VSI_ID_MASK \ 727 (0x3FF << IXL_AQ_SET_RSS_LUT_VSI_ID_SHIFT) 728 729 uint16_t vsi_number; 730 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 731 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_MASK \ 732 (0x1 << IXL_AQ_SET_RSS_LUT_TABLE_TYPE_SHIFT) 733 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_VSI 0 734 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_PF 1 735 uint16_t flags; 736 uint8_t _reserved[4]; 737 uint32_t addr_hi; 738 uint32_t addr_lo; 739 } __packed __aligned(16); 740 741 struct ixl_aq_get_set_rss_key { /* 722 */ 742 #define IXL_AQ_SET_RSS_KEY_VSI_VALID (1 << 15) 743 #define IXL_AQ_SET_RSS_KEY_VSI_ID_SHIFT 0 744 #define IXL_AQ_SET_RSS_KEY_VSI_ID_MASK \ 745 (0x3FF << IXL_AQ_SET_RSS_KEY_VSI_ID_SHIFT) 746 uint16_t vsi_number; 747 uint8_t _reserved[6]; 748 uint32_t addr_hi; 749 uint32_t addr_lo; 750 } __packed __aligned(16); 751 752 /* aq response codes */ 753 #define IXL_AQ_RC_OK 0 /* success */ 754 #define IXL_AQ_RC_EPERM 1 /* Operation not permitted */ 755 #define IXL_AQ_RC_ENOENT 2 /* No such element */ 756 #define IXL_AQ_RC_ESRCH 3 /* Bad opcode */ 757 #define IXL_AQ_RC_EINTR 4 /* operation interrupted */ 758 #define IXL_AQ_RC_EIO 5 /* I/O error */ 759 #define IXL_AQ_RC_ENXIO 6 /* No such resource */ 760 #define IXL_AQ_RC_E2BIG 7 /* Arg too long */ 761 #define IXL_AQ_RC_EAGAIN 8 /* Try again */ 762 #define IXL_AQ_RC_ENOMEM 9 /* Out of memory */ 763 #define IXL_AQ_RC_EACCES 10 /* Permission denied */ 764 #define IXL_AQ_RC_EFAULT 11 /* Bad address */ 765 #define IXL_AQ_RC_EBUSY 12 /* Device or resource busy */ 766 #define IXL_AQ_RC_EEXIST 13 /* object already exists */ 767 #define IXL_AQ_RC_EINVAL 14 /* invalid argument */ 768 #define IXL_AQ_RC_ENOTTY 15 /* not a typewriter */ 769 #define IXL_AQ_RC_ENOSPC 16 /* No space or alloc failure */ 770 #define IXL_AQ_RC_ENOSYS 17 /* function not implemented */ 771 #define IXL_AQ_RC_ERANGE 18 /* parameter out of range */ 772 #define IXL_AQ_RC_EFLUSHED 19 /* cmd flushed due to prev error */ 773 #define IXL_AQ_RC_BAD_ADDR 20 /* contains a bad pointer */ 774 #define IXL_AQ_RC_EMODE 21 /* not allowed in current mode */ 775 #define IXL_AQ_RC_EFBIG 22 /* file too large */ 776 777 struct ixl_tx_desc { 778 uint64_t addr; 779 uint64_t cmd; 780 #define IXL_TX_DESC_DTYPE_SHIFT 0 781 #define IXL_TX_DESC_DTYPE_MASK (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 782 #define IXL_TX_DESC_DTYPE_DATA (0x0ULL << IXL_TX_DESC_DTYPE_SHIFT) 783 #define IXL_TX_DESC_DTYPE_NOP (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 784 #define IXL_TX_DESC_DTYPE_CONTEXT (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 785 #define IXL_TX_DESC_DTYPE_FCOE_CTX (0x2ULL << IXL_TX_DESC_DTYPE_SHIFT) 786 #define IXL_TX_DESC_DTYPE_FD (0x8ULL << IXL_TX_DESC_DTYPE_SHIFT) 787 #define IXL_TX_DESC_DTYPE_DDP_CTX (0x9ULL << IXL_TX_DESC_DTYPE_SHIFT) 788 #define IXL_TX_DESC_DTYPE_FLEX_DATA (0xbULL << IXL_TX_DESC_DTYPE_SHIFT) 789 #define IXL_TX_DESC_DTYPE_FLEX_CTX_1 (0xcULL << IXL_TX_DESC_DTYPE_SHIFT) 790 #define IXL_TX_DESC_DTYPE_FLEX_CTX_2 (0xdULL << IXL_TX_DESC_DTYPE_SHIFT) 791 #define IXL_TX_DESC_DTYPE_DONE (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 792 793 #define IXL_TX_DESC_CMD_SHIFT 4 794 #define IXL_TX_DESC_CMD_MASK (0x3ffULL << IXL_TX_DESC_CMD_SHIFT) 795 #define IXL_TX_DESC_CMD_EOP (0x001 << IXL_TX_DESC_CMD_SHIFT) 796 #define IXL_TX_DESC_CMD_RS (0x002 << IXL_TX_DESC_CMD_SHIFT) 797 #define IXL_TX_DESC_CMD_ICRC (0x004 << IXL_TX_DESC_CMD_SHIFT) 798 #define IXL_TX_DESC_CMD_IL2TAG1 (0x008 << IXL_TX_DESC_CMD_SHIFT) 799 #define IXL_TX_DESC_CMD_DUMMY (0x010 << IXL_TX_DESC_CMD_SHIFT) 800 #define IXL_TX_DESC_CMD_IIPT_MASK (0x060 << IXL_TX_DESC_CMD_SHIFT) 801 #define IXL_TX_DESC_CMD_IIPT_NONIP (0x000 << IXL_TX_DESC_CMD_SHIFT) 802 #define IXL_TX_DESC_CMD_IIPT_IPV6 (0x020 << IXL_TX_DESC_CMD_SHIFT) 803 #define IXL_TX_DESC_CMD_IIPT_IPV4 (0x040 << IXL_TX_DESC_CMD_SHIFT) 804 #define IXL_TX_DESC_CMD_IIPT_IPV4_CSUM (0x060 << IXL_TX_DESC_CMD_SHIFT) 805 #define IXL_TX_DESC_CMD_FCOET (0x080 << IXL_TX_DESC_CMD_SHIFT) 806 #define IXL_TX_DESC_CMD_L4T_EOFT_MASK (0x300 << IXL_TX_DESC_CMD_SHIFT) 807 #define IXL_TX_DESC_CMD_L4T_EOFT_UNK (0x000 << IXL_TX_DESC_CMD_SHIFT) 808 #define IXL_TX_DESC_CMD_L4T_EOFT_TCP (0x100 << IXL_TX_DESC_CMD_SHIFT) 809 #define IXL_TX_DESC_CMD_L4T_EOFT_SCTP (0x200 << IXL_TX_DESC_CMD_SHIFT) 810 #define IXL_TX_DESC_CMD_L4T_EOFT_UDP (0x300 << IXL_TX_DESC_CMD_SHIFT) 811 812 #define IXL_TX_DESC_MACLEN_SHIFT 16 813 #define IXL_TX_DESC_MACLEN_MASK (0x7fULL << IXL_TX_DESC_MACLEN_SHIFT) 814 #define IXL_TX_DESC_IPLEN_SHIFT 23 815 #define IXL_TX_DESC_IPLEN_MASK (0x7fULL << IXL_TX_DESC_IPLEN_SHIFT) 816 #define IXL_TX_DESC_L4LEN_SHIFT 30 817 #define IXL_TX_DESC_L4LEN_MASK (0xfULL << IXL_TX_DESC_L4LEN_SHIFT) 818 #define IXL_TX_DESC_FCLEN_SHIFT 30 819 #define IXL_TX_DESC_FCLEN_MASK (0xfULL << IXL_TX_DESC_FCLEN_SHIFT) 820 821 #define IXL_TX_DESC_BSIZE_SHIFT 34 822 #define IXL_TX_DESC_BSIZE_MAX 0x3fffULL 823 #define IXL_TX_DESC_BSIZE_MASK \ 824 (IXL_TX_DESC_BSIZE_MAX << IXL_TX_DESC_BSIZE_SHIFT) 825 } __packed __aligned(16); 826 827 struct ixl_rx_rd_desc_16 { 828 uint64_t paddr; /* packet addr */ 829 uint64_t haddr; /* header addr */ 830 } __packed __aligned(16); 831 832 struct ixl_rx_rd_desc_32 { 833 uint64_t paddr; /* packet addr */ 834 uint64_t haddr; /* header addr */ 835 uint64_t _reserved1; 836 uint64_t _reserved2; 837 } __packed __aligned(16); 838 839 struct ixl_rx_wb_desc_16 { 840 uint64_t qword0; 841 uint64_t qword1; 842 #define IXL_RX_DESC_DD (1 << 0) 843 #define IXL_RX_DESC_EOP (1 << 1) 844 #define IXL_RX_DESC_L2TAG1P (1 << 2) 845 #define IXL_RX_DESC_L3L4P (1 << 3) 846 #define IXL_RX_DESC_CRCP (1 << 4) 847 #define IXL_RX_DESC_TSYNINDX_SHIFT 5 /* TSYNINDX */ 848 #define IXL_RX_DESC_TSYNINDX_MASK (7 << IXL_RX_DESC_TSYNINDX_SHIFT) 849 #define IXL_RX_DESC_UMB_SHIFT 9 850 #define IXL_RX_DESC_UMB_MASK (0x3 << IXL_RX_DESC_UMB_SHIFT) 851 #define IXL_RX_DESC_UMB_UCAST (0x0 << IXL_RX_DESC_UMB_SHIFT) 852 #define IXL_RX_DESC_UMB_MCAST (0x1 << IXL_RX_DESC_UMB_SHIFT) 853 #define IXL_RX_DESC_UMB_BCAST (0x2 << IXL_RX_DESC_UMB_SHIFT) 854 #define IXL_RX_DESC_UMB_MIRROR (0x3 << IXL_RX_DESC_UMB_SHIFT) 855 #define IXL_RX_DESC_FLM (1 << 11) 856 #define IXL_RX_DESC_FLTSTAT_SHIFT 12 857 #define IXL_RX_DESC_FLTSTAT_MASK (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 858 #define IXL_RX_DESC_FLTSTAT_NODATA (0x0 << IXL_RX_DESC_FLTSTAT_SHIFT) 859 #define IXL_RX_DESC_FLTSTAT_FDFILTID (0x1 << IXL_RX_DESC_FLTSTAT_SHIFT) 860 #define IXL_RX_DESC_FLTSTAT_RSS (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 861 #define IXL_RX_DESC_LPBK (1 << 14) 862 #define IXL_RX_DESC_IPV6EXTADD (1 << 15) 863 #define IXL_RX_DESC_INT_UDP_0 (1 << 18) 864 865 #define IXL_RX_DESC_RXE (1 << 19) 866 #define IXL_RX_DESC_HBO (1 << 21) 867 #define IXL_RX_DESC_IPE (1 << 22) 868 #define IXL_RX_DESC_L4E (1 << 23) 869 #define IXL_RX_DESC_EIPE (1 << 24) 870 #define IXL_RX_DESC_OVERSIZE (1 << 25) 871 872 #define IXL_RX_DESC_PTYPE_SHIFT 30 873 #define IXL_RX_DESC_PTYPE_MASK (0xffULL << IXL_RX_DESC_PTYPE_SHIFT) 874 875 #define IXL_RX_DESC_PLEN_SHIFT 38 876 #define IXL_RX_DESC_PLEN_MASK (0x3fffULL << IXL_RX_DESC_PLEN_SHIFT) 877 #define IXL_RX_DESC_HLEN_SHIFT 42 878 #define IXL_RX_DESC_HLEN_MASK (0x7ffULL << IXL_RX_DESC_HLEN_SHIFT) 879 } __packed __aligned(16); 880 881 struct ixl_rx_wb_desc_32 { 882 uint64_t qword0; 883 uint64_t qword1; 884 uint64_t qword2; 885 uint64_t qword3; 886 } __packed __aligned(16); 887 888 #define IXL_TX_PKT_DESCS 8 889 #define IXL_TX_QUEUE_ALIGN 128 890 #define IXL_RX_QUEUE_ALIGN 128 891 892 #define IXL_HARDMTU 9712 /* 9726 - ETHER_HDR_LEN */ 893 894 #define IXL_PCIREG PCI_MAPREG_START 895 896 #define IXL_ITR0 0x0 897 #define IXL_ITR1 0x1 898 #define IXL_ITR2 0x2 899 #define IXL_NOITR 0x2 900 901 #define IXL_AQ_NUM 256 902 #define IXL_AQ_MASK (IXL_AQ_NUM - 1) 903 #define IXL_AQ_ALIGN 64 /* lol */ 904 #define IXL_AQ_BUFLEN 4096 905 906 /* Packet Classifier Types for filters */ 907 /* bits 0-28 are reserved for future use */ 908 #define IXL_PCT_NONF_IPV4_UDP_UCAST (1ULL << 29) /* 722 */ 909 #define IXL_PCT_NONF_IPV4_UDP_MCAST (1ULL << 30) /* 722 */ 910 #define IXL_PCT_NONF_IPV4_UDP (1ULL << 31) 911 #define IXL_PCT_NONF_IPV4_TCP_SYN_NOACK (1ULL << 32) /* 722 */ 912 #define IXL_PCT_NONF_IPV4_TCP (1ULL << 33) 913 #define IXL_PCT_NONF_IPV4_SCTP (1ULL << 34) 914 #define IXL_PCT_NONF_IPV4_OTHER (1ULL << 35) 915 #define IXL_PCT_FRAG_IPV4 (1ULL << 36) 916 /* bits 37-38 are reserved for future use */ 917 #define IXL_PCT_NONF_IPV6_UDP_UCAST (1ULL << 39) /* 722 */ 918 #define IXL_PCT_NONF_IPV6_UDP_MCAST (1ULL << 40) /* 722 */ 919 #define IXL_PCT_NONF_IPV6_UDP (1ULL << 41) 920 #define IXL_PCT_NONF_IPV6_TCP_SYN_NOACK (1ULL << 42) /* 722 */ 921 #define IXL_PCT_NONF_IPV6_TCP (1ULL << 43) 922 #define IXL_PCT_NONF_IPV6_SCTP (1ULL << 44) 923 #define IXL_PCT_NONF_IPV6_OTHER (1ULL << 45) 924 #define IXL_PCT_FRAG_IPV6 (1ULL << 46) 925 /* bit 47 is reserved for future use */ 926 #define IXL_PCT_FCOE_OX (1ULL << 48) 927 #define IXL_PCT_FCOE_RX (1ULL << 49) 928 #define IXL_PCT_FCOE_OTHER (1ULL << 50) 929 /* bits 51-62 are reserved for future use */ 930 #define IXL_PCT_L2_PAYLOAD (1ULL << 63) 931 932 #define IXL_RSS_HENA_BASE_DEFAULT \ 933 IXL_PCT_NONF_IPV4_UDP | \ 934 IXL_PCT_NONF_IPV4_TCP | \ 935 IXL_PCT_NONF_IPV4_SCTP | \ 936 IXL_PCT_NONF_IPV4_OTHER | \ 937 IXL_PCT_FRAG_IPV4 | \ 938 IXL_PCT_NONF_IPV6_UDP | \ 939 IXL_PCT_NONF_IPV6_TCP | \ 940 IXL_PCT_NONF_IPV6_SCTP | \ 941 IXL_PCT_NONF_IPV6_OTHER | \ 942 IXL_PCT_FRAG_IPV6 | \ 943 IXL_PCT_L2_PAYLOAD 944 945 #define IXL_RSS_HENA_BASE_710 IXL_RSS_HENA_BASE_DEFAULT 946 #define IXL_RSS_HENA_BASE_722 IXL_RSS_HENA_BASE_DEFAULT | \ 947 IXL_PCT_NONF_IPV4_UDP_UCAST | \ 948 IXL_PCT_NONF_IPV4_UDP_MCAST | \ 949 IXL_PCT_NONF_IPV6_UDP_UCAST | \ 950 IXL_PCT_NONF_IPV6_UDP_MCAST | \ 951 IXL_PCT_NONF_IPV4_TCP_SYN_NOACK | \ 952 IXL_PCT_NONF_IPV6_TCP_SYN_NOACK 953 954 #define IXL_HMC_ROUNDUP 512 955 #define IXL_HMC_PGSIZE 4096 956 #define IXL_HMC_DVASZ sizeof(uint64_t) 957 #define IXL_HMC_PGS (IXL_HMC_PGSIZE / IXL_HMC_DVASZ) 958 #define IXL_HMC_L2SZ (IXL_HMC_PGSIZE * IXL_HMC_PGS) 959 #define IXL_HMC_PDVALID 1ULL 960 961 struct ixl_aq_regs { 962 bus_size_t atq_tail; 963 bus_size_t atq_head; 964 bus_size_t atq_len; 965 bus_size_t atq_bal; 966 bus_size_t atq_bah; 967 968 bus_size_t arq_tail; 969 bus_size_t arq_head; 970 bus_size_t arq_len; 971 bus_size_t arq_bal; 972 bus_size_t arq_bah; 973 974 uint32_t atq_len_enable; 975 uint32_t atq_tail_mask; 976 uint32_t atq_head_mask; 977 978 uint32_t arq_len_enable; 979 uint32_t arq_tail_mask; 980 uint32_t arq_head_mask; 981 }; 982 983 struct ixl_phy_type { 984 uint64_t phy_type; 985 uint64_t ifm_type; 986 }; 987 988 struct ixl_speed_type { 989 uint8_t dev_speed; 990 uint64_t net_speed; 991 }; 992 993 struct ixl_aq_buf { 994 SIMPLEQ_ENTRY(ixl_aq_buf) 995 aqb_entry; 996 void *aqb_data; 997 bus_dmamap_t aqb_map; 998 }; 999 SIMPLEQ_HEAD(ixl_aq_bufs, ixl_aq_buf); 1000 1001 struct ixl_dmamem { 1002 bus_dmamap_t ixm_map; 1003 bus_dma_segment_t ixm_seg; 1004 int ixm_nsegs; 1005 size_t ixm_size; 1006 caddr_t ixm_kva; 1007 }; 1008 #define IXL_DMA_MAP(_ixm) ((_ixm)->ixm_map) 1009 #define IXL_DMA_DVA(_ixm) ((_ixm)->ixm_map->dm_segs[0].ds_addr) 1010 #define IXL_DMA_KVA(_ixm) ((void *)(_ixm)->ixm_kva) 1011 #define IXL_DMA_LEN(_ixm) ((_ixm)->ixm_size) 1012 1013 struct ixl_hmc_entry { 1014 uint64_t hmc_base; 1015 uint32_t hmc_count; 1016 uint32_t hmc_size; 1017 }; 1018 1019 #define IXL_HMC_LAN_TX 0 1020 #define IXL_HMC_LAN_RX 1 1021 #define IXL_HMC_FCOE_CTX 2 1022 #define IXL_HMC_FCOE_FILTER 3 1023 #define IXL_HMC_COUNT 4 1024 1025 struct ixl_hmc_pack { 1026 uint16_t offset; 1027 uint16_t width; 1028 uint16_t lsb; 1029 }; 1030 1031 /* 1032 * these hmc objects have weird sizes and alignments, so these are abstract 1033 * representations of them that are nice for c to populate. 1034 * 1035 * the packing code relies on little-endian values being stored in the fields, 1036 * no high bits in the fields being set, and the fields must be packed in the 1037 * same order as they are in the ctx structure. 1038 */ 1039 1040 struct ixl_hmc_rxq { 1041 uint16_t head; 1042 uint8_t cpuid; 1043 uint64_t base; 1044 #define IXL_HMC_RXQ_BASE_UNIT 128 1045 uint16_t qlen; 1046 uint16_t dbuff; 1047 #define IXL_HMC_RXQ_DBUFF_UNIT 128 1048 uint8_t hbuff; 1049 #define IXL_HMC_RXQ_HBUFF_UNIT 64 1050 uint8_t dtype; 1051 #define IXL_HMC_RXQ_DTYPE_NOSPLIT 0x0 1052 #define IXL_HMC_RXQ_DTYPE_HSPLIT 0x1 1053 #define IXL_HMC_RXQ_DTYPE_SPLIT_ALWAYS 0x2 1054 uint8_t dsize; 1055 #define IXL_HMC_RXQ_DSIZE_16 0 1056 #define IXL_HMC_RXQ_DSIZE_32 1 1057 uint8_t crcstrip; 1058 uint8_t fc_ena; 1059 uint8_t l2sel; 1060 uint8_t hsplit_0; 1061 uint8_t hsplit_1; 1062 uint8_t showiv; 1063 uint16_t rxmax; 1064 uint8_t tphrdesc_ena; 1065 uint8_t tphwdesc_ena; 1066 uint8_t tphdata_ena; 1067 uint8_t tphhead_ena; 1068 uint8_t lrxqthresh; 1069 uint8_t prefena; 1070 }; 1071 1072 static const struct ixl_hmc_pack ixl_hmc_pack_rxq[] = { 1073 { offsetof(struct ixl_hmc_rxq, head), 13, 0 }, 1074 { offsetof(struct ixl_hmc_rxq, cpuid), 8, 13 }, 1075 { offsetof(struct ixl_hmc_rxq, base), 57, 32 }, 1076 { offsetof(struct ixl_hmc_rxq, qlen), 13, 89 }, 1077 { offsetof(struct ixl_hmc_rxq, dbuff), 7, 102 }, 1078 { offsetof(struct ixl_hmc_rxq, hbuff), 5, 109 }, 1079 { offsetof(struct ixl_hmc_rxq, dtype), 2, 114 }, 1080 { offsetof(struct ixl_hmc_rxq, dsize), 1, 116 }, 1081 { offsetof(struct ixl_hmc_rxq, crcstrip), 1, 117 }, 1082 { offsetof(struct ixl_hmc_rxq, fc_ena), 1, 118 }, 1083 { offsetof(struct ixl_hmc_rxq, l2sel), 1, 119 }, 1084 { offsetof(struct ixl_hmc_rxq, hsplit_0), 4, 120 }, 1085 { offsetof(struct ixl_hmc_rxq, hsplit_1), 2, 124 }, 1086 { offsetof(struct ixl_hmc_rxq, showiv), 1, 127 }, 1087 { offsetof(struct ixl_hmc_rxq, rxmax), 14, 174 }, 1088 { offsetof(struct ixl_hmc_rxq, tphrdesc_ena), 1, 193 }, 1089 { offsetof(struct ixl_hmc_rxq, tphwdesc_ena), 1, 194 }, 1090 { offsetof(struct ixl_hmc_rxq, tphdata_ena), 1, 195 }, 1091 { offsetof(struct ixl_hmc_rxq, tphhead_ena), 1, 196 }, 1092 { offsetof(struct ixl_hmc_rxq, lrxqthresh), 3, 198 }, 1093 { offsetof(struct ixl_hmc_rxq, prefena), 1, 201 }, 1094 }; 1095 1096 #define IXL_HMC_RXQ_MINSIZE (201 + 1) 1097 1098 struct ixl_hmc_txq { 1099 uint16_t head; 1100 uint8_t new_context; 1101 uint64_t base; 1102 #define IXL_HMC_TXQ_BASE_UNIT 128 1103 uint8_t fc_ena; 1104 uint8_t timesync_ena; 1105 uint8_t fd_ena; 1106 uint8_t alt_vlan_ena; 1107 uint16_t thead_wb; 1108 uint8_t cpuid; 1109 uint8_t head_wb_ena; 1110 #define IXL_HMC_TXQ_DESC_WB 0 1111 #define IXL_HMC_TXQ_HEAD_WB 1 1112 uint16_t qlen; 1113 uint8_t tphrdesc_ena; 1114 uint8_t tphrpacket_ena; 1115 uint8_t tphwdesc_ena; 1116 uint64_t head_wb_addr; 1117 uint32_t crc; 1118 uint16_t rdylist; 1119 uint8_t rdylist_act; 1120 }; 1121 1122 static const struct ixl_hmc_pack ixl_hmc_pack_txq[] = { 1123 { offsetof(struct ixl_hmc_txq, head), 13, 0 }, 1124 { offsetof(struct ixl_hmc_txq, new_context), 1, 30 }, 1125 { offsetof(struct ixl_hmc_txq, base), 57, 32 }, 1126 { offsetof(struct ixl_hmc_txq, fc_ena), 1, 89 }, 1127 { offsetof(struct ixl_hmc_txq, timesync_ena), 1, 90 }, 1128 { offsetof(struct ixl_hmc_txq, fd_ena), 1, 91 }, 1129 { offsetof(struct ixl_hmc_txq, alt_vlan_ena), 1, 92 }, 1130 { offsetof(struct ixl_hmc_txq, cpuid), 8, 96 }, 1131 /* line 1 */ 1132 { offsetof(struct ixl_hmc_txq, thead_wb), 13, 0 + 128 }, 1133 { offsetof(struct ixl_hmc_txq, head_wb_ena), 1, 32 + 128 }, 1134 { offsetof(struct ixl_hmc_txq, qlen), 13, 33 + 128 }, 1135 { offsetof(struct ixl_hmc_txq, tphrdesc_ena), 1, 46 + 128 }, 1136 { offsetof(struct ixl_hmc_txq, tphrpacket_ena), 1, 47 + 128 }, 1137 { offsetof(struct ixl_hmc_txq, tphwdesc_ena), 1, 48 + 128 }, 1138 { offsetof(struct ixl_hmc_txq, head_wb_addr), 64, 64 + 128 }, 1139 /* line 7 */ 1140 { offsetof(struct ixl_hmc_txq, crc), 32, 0 + (7*128) }, 1141 { offsetof(struct ixl_hmc_txq, rdylist), 10, 84 + (7*128) }, 1142 { offsetof(struct ixl_hmc_txq, rdylist_act), 1, 94 + (7*128) }, 1143 }; 1144 1145 #define IXL_HMC_TXQ_MINSIZE (94 + (7*128) + 1) 1146 1147 struct ixl_rss_key { 1148 uint32_t key[13]; 1149 }; 1150 1151 struct ixl_rss_lut_128 { 1152 uint32_t entries[128 / sizeof(uint32_t)]; 1153 }; 1154 1155 struct ixl_rss_lut_512 { 1156 uint32_t entries[512 / sizeof(uint32_t)]; 1157 }; 1158 1159 /* driver structures */ 1160 1161 struct ixl_vector; 1162 struct ixl_chip; 1163 1164 struct ixl_tx_map { 1165 struct mbuf *txm_m; 1166 bus_dmamap_t txm_map; 1167 unsigned int txm_eop; 1168 }; 1169 1170 struct ixl_tx_ring { 1171 struct ixl_softc *txr_sc; 1172 struct ixl_vector *txr_vector; 1173 struct ifqueue *txr_ifq; 1174 1175 unsigned int txr_prod; 1176 unsigned int txr_cons; 1177 1178 struct ixl_tx_map *txr_maps; 1179 struct ixl_dmamem txr_mem; 1180 1181 bus_size_t txr_tail; 1182 unsigned int txr_qid; 1183 } __aligned(CACHE_LINE_SIZE); 1184 1185 struct ixl_rx_map { 1186 struct mbuf *rxm_m; 1187 bus_dmamap_t rxm_map; 1188 }; 1189 1190 struct ixl_rx_ring { 1191 struct ixl_softc *rxr_sc; 1192 struct ixl_vector *rxr_vector; 1193 struct ifiqueue *rxr_ifiq; 1194 1195 struct if_rxring rxr_acct; 1196 struct timeout rxr_refill; 1197 1198 unsigned int rxr_prod; 1199 unsigned int rxr_cons; 1200 1201 struct ixl_rx_map *rxr_maps; 1202 struct ixl_dmamem rxr_mem; 1203 1204 struct mbuf *rxr_m_head; 1205 struct mbuf **rxr_m_tail; 1206 1207 bus_size_t rxr_tail; 1208 unsigned int rxr_qid; 1209 } __aligned(CACHE_LINE_SIZE); 1210 1211 struct ixl_atq { 1212 struct ixl_aq_desc iatq_desc; 1213 void *iatq_arg; 1214 void (*iatq_fn)(struct ixl_softc *, void *); 1215 }; 1216 SIMPLEQ_HEAD(ixl_atq_list, ixl_atq); 1217 1218 struct ixl_vector { 1219 struct ixl_softc *iv_sc; 1220 struct ixl_rx_ring *iv_rxr; 1221 struct ixl_tx_ring *iv_txr; 1222 int iv_qid; 1223 void *iv_ihc; 1224 char iv_name[16]; 1225 } __aligned(CACHE_LINE_SIZE); 1226 1227 struct ixl_softc { 1228 struct device sc_dev; 1229 const struct ixl_chip *sc_chip; 1230 struct arpcom sc_ac; 1231 struct ifmedia sc_media; 1232 uint64_t sc_media_status; 1233 uint64_t sc_media_active; 1234 1235 pci_chipset_tag_t sc_pc; 1236 pci_intr_handle_t sc_ih; 1237 void *sc_ihc; 1238 pcitag_t sc_tag; 1239 1240 bus_dma_tag_t sc_dmat; 1241 bus_space_tag_t sc_memt; 1242 bus_space_handle_t sc_memh; 1243 bus_size_t sc_mems; 1244 1245 uint16_t sc_api_major; 1246 uint16_t sc_api_minor; 1247 uint8_t sc_pf_id; 1248 uint16_t sc_uplink_seid; /* le */ 1249 uint16_t sc_downlink_seid; /* le */ 1250 uint16_t sc_veb_seid; /* le */ 1251 uint16_t sc_vsi_number; /* le */ 1252 uint16_t sc_seid; 1253 unsigned int sc_base_queue; 1254 unsigned int sc_port; 1255 1256 struct ixl_dmamem sc_scratch; 1257 1258 const struct ixl_aq_regs * 1259 sc_aq_regs; 1260 1261 struct ixl_dmamem sc_atq; 1262 unsigned int sc_atq_prod; 1263 unsigned int sc_atq_cons; 1264 1265 struct ixl_dmamem sc_arq; 1266 struct task sc_arq_task; 1267 struct ixl_aq_bufs sc_arq_idle; 1268 struct ixl_aq_bufs sc_arq_live; 1269 struct if_rxring sc_arq_ring; 1270 unsigned int sc_arq_prod; 1271 unsigned int sc_arq_cons; 1272 1273 struct mutex sc_link_state_mtx; 1274 struct task sc_link_state_task; 1275 struct ixl_atq sc_link_state_atq; 1276 1277 struct ixl_dmamem sc_hmc_sd; 1278 struct ixl_dmamem sc_hmc_pd; 1279 struct ixl_hmc_entry sc_hmc_entries[IXL_HMC_COUNT]; 1280 1281 unsigned int sc_tx_ring_ndescs; 1282 unsigned int sc_rx_ring_ndescs; 1283 unsigned int sc_nqueues; /* 1 << sc_nqueues */ 1284 1285 struct intrmap *sc_intrmap; 1286 struct ixl_vector *sc_vectors; 1287 1288 struct rwlock sc_cfg_lock; 1289 unsigned int sc_dead; 1290 1291 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 1292 1293 #if NKSTAT > 0 1294 struct mutex sc_kstat_mtx; 1295 struct timeout sc_kstat_tmo; 1296 struct kstat *sc_port_kstat; 1297 struct kstat *sc_vsi_kstat; 1298 #endif 1299 }; 1300 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) 1301 1302 #define delaymsec(_ms) delay(1000 * (_ms)) 1303 1304 static void ixl_clear_hw(struct ixl_softc *); 1305 static int ixl_pf_reset(struct ixl_softc *); 1306 1307 static int ixl_dmamem_alloc(struct ixl_softc *, struct ixl_dmamem *, 1308 bus_size_t, u_int); 1309 static void ixl_dmamem_free(struct ixl_softc *, struct ixl_dmamem *); 1310 1311 static int ixl_arq_fill(struct ixl_softc *); 1312 static void ixl_arq_unfill(struct ixl_softc *); 1313 1314 static int ixl_atq_poll(struct ixl_softc *, struct ixl_aq_desc *, 1315 unsigned int); 1316 static void ixl_atq_set(struct ixl_atq *, 1317 void (*)(struct ixl_softc *, void *), void *); 1318 static void ixl_atq_post(struct ixl_softc *, struct ixl_atq *); 1319 static void ixl_atq_done(struct ixl_softc *); 1320 static void ixl_atq_exec(struct ixl_softc *, struct ixl_atq *, 1321 const char *); 1322 static int ixl_get_version(struct ixl_softc *); 1323 static int ixl_pxe_clear(struct ixl_softc *); 1324 static int ixl_lldp_shut(struct ixl_softc *); 1325 static int ixl_get_mac(struct ixl_softc *); 1326 static int ixl_get_switch_config(struct ixl_softc *); 1327 static int ixl_phy_mask_ints(struct ixl_softc *); 1328 static int ixl_get_phy_types(struct ixl_softc *, uint64_t *); 1329 static int ixl_restart_an(struct ixl_softc *); 1330 static int ixl_hmc(struct ixl_softc *); 1331 static void ixl_hmc_free(struct ixl_softc *); 1332 static int ixl_get_vsi(struct ixl_softc *); 1333 static int ixl_set_vsi(struct ixl_softc *); 1334 static int ixl_get_link_status(struct ixl_softc *); 1335 static int ixl_set_link_status(struct ixl_softc *, 1336 const struct ixl_aq_desc *); 1337 static int ixl_add_macvlan(struct ixl_softc *, uint8_t *, uint16_t, 1338 uint16_t); 1339 static int ixl_remove_macvlan(struct ixl_softc *, uint8_t *, uint16_t, 1340 uint16_t); 1341 static void ixl_link_state_update(void *); 1342 static void ixl_arq(void *); 1343 static void ixl_hmc_pack(void *, const void *, 1344 const struct ixl_hmc_pack *, unsigned int); 1345 1346 static int ixl_get_sffpage(struct ixl_softc *, struct if_sffpage *); 1347 static int ixl_sff_get_byte(struct ixl_softc *, uint8_t, uint32_t, 1348 uint8_t *); 1349 static int ixl_sff_set_byte(struct ixl_softc *, uint8_t, uint32_t, 1350 uint8_t); 1351 1352 static int ixl_match(struct device *, void *, void *); 1353 static void ixl_attach(struct device *, struct device *, void *); 1354 1355 static void ixl_media_add(struct ixl_softc *, uint64_t); 1356 static int ixl_media_change(struct ifnet *); 1357 static void ixl_media_status(struct ifnet *, struct ifmediareq *); 1358 static void ixl_watchdog(struct ifnet *); 1359 static int ixl_ioctl(struct ifnet *, u_long, caddr_t); 1360 static void ixl_start(struct ifqueue *); 1361 static int ixl_intr0(void *); 1362 static int ixl_intr_vector(void *); 1363 static int ixl_up(struct ixl_softc *); 1364 static int ixl_down(struct ixl_softc *); 1365 static int ixl_iff(struct ixl_softc *); 1366 1367 static struct ixl_tx_ring * 1368 ixl_txr_alloc(struct ixl_softc *, unsigned int); 1369 static void ixl_txr_qdis(struct ixl_softc *, struct ixl_tx_ring *, int); 1370 static void ixl_txr_config(struct ixl_softc *, struct ixl_tx_ring *); 1371 static int ixl_txr_enabled(struct ixl_softc *, struct ixl_tx_ring *); 1372 static int ixl_txr_disabled(struct ixl_softc *, struct ixl_tx_ring *); 1373 static void ixl_txr_unconfig(struct ixl_softc *, struct ixl_tx_ring *); 1374 static void ixl_txr_clean(struct ixl_softc *, struct ixl_tx_ring *); 1375 static void ixl_txr_free(struct ixl_softc *, struct ixl_tx_ring *); 1376 static int ixl_txeof(struct ixl_softc *, struct ixl_tx_ring *); 1377 1378 static struct ixl_rx_ring * 1379 ixl_rxr_alloc(struct ixl_softc *, unsigned int); 1380 static void ixl_rxr_config(struct ixl_softc *, struct ixl_rx_ring *); 1381 static int ixl_rxr_enabled(struct ixl_softc *, struct ixl_rx_ring *); 1382 static int ixl_rxr_disabled(struct ixl_softc *, struct ixl_rx_ring *); 1383 static void ixl_rxr_unconfig(struct ixl_softc *, struct ixl_rx_ring *); 1384 static void ixl_rxr_clean(struct ixl_softc *, struct ixl_rx_ring *); 1385 static void ixl_rxr_free(struct ixl_softc *, struct ixl_rx_ring *); 1386 static int ixl_rxeof(struct ixl_softc *, struct ixl_rx_ring *); 1387 static void ixl_rxfill(struct ixl_softc *, struct ixl_rx_ring *); 1388 static void ixl_rxrefill(void *); 1389 static int ixl_rxrinfo(struct ixl_softc *, struct if_rxrinfo *); 1390 1391 #if NKSTAT > 0 1392 static void ixl_kstat_attach(struct ixl_softc *); 1393 #endif 1394 1395 struct cfdriver ixl_cd = { 1396 NULL, 1397 "ixl", 1398 DV_IFNET, 1399 }; 1400 1401 struct cfattach ixl_ca = { 1402 sizeof(struct ixl_softc), 1403 ixl_match, 1404 ixl_attach, 1405 }; 1406 1407 static const struct ixl_phy_type ixl_phy_type_map[] = { 1408 { 1ULL << IXL_PHY_TYPE_SGMII, IFM_1000_SGMII }, 1409 { 1ULL << IXL_PHY_TYPE_1000BASE_KX, IFM_1000_KX }, 1410 { 1ULL << IXL_PHY_TYPE_10GBASE_KX4, IFM_10G_KX4 }, 1411 { 1ULL << IXL_PHY_TYPE_10GBASE_KR, IFM_10G_KR }, 1412 { 1ULL << IXL_PHY_TYPE_40GBASE_KR4, IFM_40G_KR4 }, 1413 { 1ULL << IXL_PHY_TYPE_XAUI | 1414 1ULL << IXL_PHY_TYPE_XFI, IFM_10G_CX4 }, 1415 { 1ULL << IXL_PHY_TYPE_SFI, IFM_10G_SFI }, 1416 { 1ULL << IXL_PHY_TYPE_XLAUI | 1417 1ULL << IXL_PHY_TYPE_XLPPI, IFM_40G_XLPPI }, 1418 { 1ULL << IXL_PHY_TYPE_40GBASE_CR4_CU | 1419 1ULL << IXL_PHY_TYPE_40GBASE_CR4, IFM_40G_CR4 }, 1420 { 1ULL << IXL_PHY_TYPE_10GBASE_CR1_CU | 1421 1ULL << IXL_PHY_TYPE_10GBASE_CR1, IFM_10G_CR1 }, 1422 { 1ULL << IXL_PHY_TYPE_10GBASE_AOC, IFM_10G_AOC }, 1423 { 1ULL << IXL_PHY_TYPE_40GBASE_AOC, IFM_40G_AOC }, 1424 { 1ULL << IXL_PHY_TYPE_100BASE_TX, IFM_100_TX }, 1425 { 1ULL << IXL_PHY_TYPE_1000BASE_T_OPTICAL | 1426 1ULL << IXL_PHY_TYPE_1000BASE_T, IFM_1000_T }, 1427 { 1ULL << IXL_PHY_TYPE_10GBASE_T, IFM_10G_T }, 1428 { 1ULL << IXL_PHY_TYPE_10GBASE_SR, IFM_10G_SR }, 1429 { 1ULL << IXL_PHY_TYPE_10GBASE_LR, IFM_10G_LR }, 1430 { 1ULL << IXL_PHY_TYPE_10GBASE_SFPP_CU, IFM_10G_SFP_CU }, 1431 { 1ULL << IXL_PHY_TYPE_40GBASE_SR4, IFM_40G_SR4 }, 1432 { 1ULL << IXL_PHY_TYPE_40GBASE_LR4, IFM_40G_LR4 }, 1433 { 1ULL << IXL_PHY_TYPE_1000BASE_SX, IFM_1000_SX }, 1434 { 1ULL << IXL_PHY_TYPE_1000BASE_LX, IFM_1000_LX }, 1435 { 1ULL << IXL_PHY_TYPE_20GBASE_KR2, IFM_20G_KR2 }, 1436 { 1ULL << IXL_PHY_TYPE_25GBASE_KR, IFM_25G_KR }, 1437 { 1ULL << IXL_PHY_TYPE_25GBASE_CR, IFM_25G_CR }, 1438 { 1ULL << IXL_PHY_TYPE_25GBASE_SR, IFM_25G_SR }, 1439 { 1ULL << IXL_PHY_TYPE_25GBASE_LR, IFM_25G_LR }, 1440 { 1ULL << IXL_PHY_TYPE_25GBASE_AOC, IFM_25G_AOC }, 1441 { 1ULL << IXL_PHY_TYPE_25GBASE_ACC, IFM_25G_CR }, 1442 }; 1443 1444 static const struct ixl_speed_type ixl_speed_type_map[] = { 1445 { IXL_AQ_LINK_SPEED_40GB, IF_Gbps(40) }, 1446 { IXL_AQ_LINK_SPEED_25GB, IF_Gbps(25) }, 1447 { IXL_AQ_LINK_SPEED_10GB, IF_Gbps(10) }, 1448 { IXL_AQ_LINK_SPEED_1GB, IF_Gbps(1) }, 1449 }; 1450 1451 static const struct ixl_aq_regs ixl_pf_aq_regs = { 1452 .atq_tail = I40E_PF_ATQT, 1453 .atq_tail_mask = I40E_PF_ATQT_ATQT_MASK, 1454 .atq_head = I40E_PF_ATQH, 1455 .atq_head_mask = I40E_PF_ATQH_ATQH_MASK, 1456 .atq_len = I40E_PF_ATQLEN, 1457 .atq_bal = I40E_PF_ATQBAL, 1458 .atq_bah = I40E_PF_ATQBAH, 1459 .atq_len_enable = I40E_PF_ATQLEN_ATQENABLE_MASK, 1460 1461 .arq_tail = I40E_PF_ARQT, 1462 .arq_tail_mask = I40E_PF_ARQT_ARQT_MASK, 1463 .arq_head = I40E_PF_ARQH, 1464 .arq_head_mask = I40E_PF_ARQH_ARQH_MASK, 1465 .arq_len = I40E_PF_ARQLEN, 1466 .arq_bal = I40E_PF_ARQBAL, 1467 .arq_bah = I40E_PF_ARQBAH, 1468 .arq_len_enable = I40E_PF_ARQLEN_ARQENABLE_MASK, 1469 }; 1470 1471 #define ixl_rd(_s, _r) \ 1472 bus_space_read_4((_s)->sc_memt, (_s)->sc_memh, (_r)) 1473 #define ixl_wr(_s, _r, _v) \ 1474 bus_space_write_4((_s)->sc_memt, (_s)->sc_memh, (_r), (_v)) 1475 #define ixl_barrier(_s, _r, _l, _o) \ 1476 bus_space_barrier((_s)->sc_memt, (_s)->sc_memh, (_r), (_l), (_o)) 1477 #define ixl_intr_enable(_s) \ 1478 ixl_wr((_s), I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_INTENA_MASK | \ 1479 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | \ 1480 (IXL_NOITR << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)) 1481 1482 #define ixl_nqueues(_sc) (1 << (_sc)->sc_nqueues) 1483 1484 #ifdef __LP64__ 1485 #define ixl_dmamem_hi(_ixm) (uint32_t)(IXL_DMA_DVA(_ixm) >> 32) 1486 #else 1487 #define ixl_dmamem_hi(_ixm) 0 1488 #endif 1489 1490 #define ixl_dmamem_lo(_ixm) (uint32_t)IXL_DMA_DVA(_ixm) 1491 1492 static inline void 1493 ixl_aq_dva(struct ixl_aq_desc *iaq, bus_addr_t addr) 1494 { 1495 #ifdef __LP64__ 1496 htolem32(&iaq->iaq_param[2], addr >> 32); 1497 #else 1498 iaq->iaq_param[2] = htole32(0); 1499 #endif 1500 htolem32(&iaq->iaq_param[3], addr); 1501 } 1502 1503 #if _BYTE_ORDER == _BIG_ENDIAN 1504 #define HTOLE16(_x) (uint16_t)(((_x) & 0xff) << 8 | ((_x) & 0xff00) >> 8) 1505 #else 1506 #define HTOLE16(_x) (_x) 1507 #endif 1508 1509 static struct rwlock ixl_sff_lock = RWLOCK_INITIALIZER("ixlsff"); 1510 1511 /* deal with differences between chips */ 1512 1513 struct ixl_chip { 1514 uint64_t ic_rss_hena; 1515 uint32_t (*ic_rd_ctl)(struct ixl_softc *, uint32_t); 1516 void (*ic_wr_ctl)(struct ixl_softc *, uint32_t, 1517 uint32_t); 1518 1519 int (*ic_set_rss_key)(struct ixl_softc *, 1520 const struct ixl_rss_key *); 1521 int (*ic_set_rss_lut)(struct ixl_softc *, 1522 const struct ixl_rss_lut_128 *); 1523 }; 1524 1525 static inline uint64_t 1526 ixl_rss_hena(struct ixl_softc *sc) 1527 { 1528 return (sc->sc_chip->ic_rss_hena); 1529 } 1530 1531 static inline uint32_t 1532 ixl_rd_ctl(struct ixl_softc *sc, uint32_t r) 1533 { 1534 return ((*sc->sc_chip->ic_rd_ctl)(sc, r)); 1535 } 1536 1537 static inline void 1538 ixl_wr_ctl(struct ixl_softc *sc, uint32_t r, uint32_t v) 1539 { 1540 (*sc->sc_chip->ic_wr_ctl)(sc, r, v); 1541 } 1542 1543 static inline int 1544 ixl_set_rss_key(struct ixl_softc *sc, const struct ixl_rss_key *rsskey) 1545 { 1546 return ((*sc->sc_chip->ic_set_rss_key)(sc, rsskey)); 1547 } 1548 1549 static inline int 1550 ixl_set_rss_lut(struct ixl_softc *sc, const struct ixl_rss_lut_128 *lut) 1551 { 1552 return ((*sc->sc_chip->ic_set_rss_lut)(sc, lut)); 1553 } 1554 1555 /* 710 chip specifics */ 1556 1557 static uint32_t ixl_710_rd_ctl(struct ixl_softc *, uint32_t); 1558 static void ixl_710_wr_ctl(struct ixl_softc *, uint32_t, uint32_t); 1559 static int ixl_710_set_rss_key(struct ixl_softc *, 1560 const struct ixl_rss_key *); 1561 static int ixl_710_set_rss_lut(struct ixl_softc *, 1562 const struct ixl_rss_lut_128 *); 1563 1564 static const struct ixl_chip ixl_710 = { 1565 .ic_rss_hena = IXL_RSS_HENA_BASE_710, 1566 .ic_rd_ctl = ixl_710_rd_ctl, 1567 .ic_wr_ctl = ixl_710_wr_ctl, 1568 .ic_set_rss_key = ixl_710_set_rss_key, 1569 .ic_set_rss_lut = ixl_710_set_rss_lut, 1570 }; 1571 1572 /* 722 chip specifics */ 1573 1574 static uint32_t ixl_722_rd_ctl(struct ixl_softc *, uint32_t); 1575 static void ixl_722_wr_ctl(struct ixl_softc *, uint32_t, uint32_t); 1576 static int ixl_722_set_rss_key(struct ixl_softc *, 1577 const struct ixl_rss_key *); 1578 static int ixl_722_set_rss_lut(struct ixl_softc *, 1579 const struct ixl_rss_lut_128 *); 1580 1581 static const struct ixl_chip ixl_722 = { 1582 .ic_rss_hena = IXL_RSS_HENA_BASE_722, 1583 .ic_rd_ctl = ixl_722_rd_ctl, 1584 .ic_wr_ctl = ixl_722_wr_ctl, 1585 .ic_set_rss_key = ixl_722_set_rss_key, 1586 .ic_set_rss_lut = ixl_722_set_rss_lut, 1587 }; 1588 1589 /* 1590 * 710 chips using an older firmware/API use the same ctl ops as 1591 * 722 chips. or 722 chips use the same ctl ops as 710 chips in early 1592 * firmware/API versions? 1593 */ 1594 1595 static const struct ixl_chip ixl_710_decrepit = { 1596 .ic_rss_hena = IXL_RSS_HENA_BASE_710, 1597 .ic_rd_ctl = ixl_722_rd_ctl, 1598 .ic_wr_ctl = ixl_722_wr_ctl, 1599 .ic_set_rss_key = ixl_710_set_rss_key, 1600 .ic_set_rss_lut = ixl_710_set_rss_lut, 1601 }; 1602 1603 /* driver code */ 1604 1605 struct ixl_device { 1606 const struct ixl_chip *id_chip; 1607 pci_vendor_id_t id_vid; 1608 pci_product_id_t id_pid; 1609 }; 1610 1611 static const struct ixl_device ixl_devices[] = { 1612 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_SFP }, 1613 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_40G_BP }, 1614 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_BP, }, 1615 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_1 }, 1616 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_2 }, 1617 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_QSFP }, 1618 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_BASET }, 1619 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_1 }, 1620 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_2 }, 1621 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_T4_10G }, 1622 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XXV710_25G_BP }, 1623 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XXV710_25G_SFP28, }, 1624 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_KX }, 1625 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_QSFP }, 1626 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_SFP_1 }, 1627 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_1G }, 1628 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_T }, 1629 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_SFP_2 }, 1630 }; 1631 1632 static const struct ixl_device * 1633 ixl_device_lookup(struct pci_attach_args *pa) 1634 { 1635 pci_vendor_id_t vid = PCI_VENDOR(pa->pa_id); 1636 pci_product_id_t pid = PCI_PRODUCT(pa->pa_id); 1637 const struct ixl_device *id; 1638 unsigned int i; 1639 1640 for (i = 0; i < nitems(ixl_devices); i++) { 1641 id = &ixl_devices[i]; 1642 if (id->id_vid == vid && id->id_pid == pid) 1643 return (id); 1644 } 1645 1646 return (NULL); 1647 } 1648 1649 static int 1650 ixl_match(struct device *parent, void *match, void *aux) 1651 { 1652 return (ixl_device_lookup(aux) != NULL); 1653 } 1654 1655 void 1656 ixl_attach(struct device *parent, struct device *self, void *aux) 1657 { 1658 struct ixl_softc *sc = (struct ixl_softc *)self; 1659 struct ifnet *ifp = &sc->sc_ac.ac_if; 1660 struct pci_attach_args *pa = aux; 1661 pcireg_t memtype; 1662 uint32_t port, ari, func; 1663 uint64_t phy_types = 0; 1664 unsigned int nqueues, i; 1665 int tries; 1666 1667 rw_init(&sc->sc_cfg_lock, "ixlcfg"); 1668 1669 sc->sc_chip = ixl_device_lookup(pa)->id_chip; 1670 sc->sc_pc = pa->pa_pc; 1671 sc->sc_tag = pa->pa_tag; 1672 sc->sc_dmat = pa->pa_dmat; 1673 sc->sc_aq_regs = &ixl_pf_aq_regs; 1674 1675 sc->sc_nqueues = 0; /* 1 << 0 is 1 queue */ 1676 sc->sc_tx_ring_ndescs = 1024; 1677 sc->sc_rx_ring_ndescs = 1024; 1678 1679 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, IXL_PCIREG); 1680 if (pci_mapreg_map(pa, IXL_PCIREG, memtype, 0, 1681 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems, 0)) { 1682 printf(": unable to map registers\n"); 1683 return; 1684 } 1685 1686 sc->sc_base_queue = (ixl_rd(sc, I40E_PFLAN_QALLOC) & 1687 I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1688 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1689 1690 ixl_clear_hw(sc); 1691 if (ixl_pf_reset(sc) == -1) { 1692 /* error printed by ixl_pf_reset */ 1693 goto unmap; 1694 } 1695 1696 port = ixl_rd(sc, I40E_PFGEN_PORTNUM); 1697 port &= I40E_PFGEN_PORTNUM_PORT_NUM_MASK; 1698 port >>= I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 1699 sc->sc_port = port; 1700 printf(": port %u", port); 1701 1702 ari = ixl_rd(sc, I40E_GLPCI_CAPSUP); 1703 ari &= I40E_GLPCI_CAPSUP_ARI_EN_MASK; 1704 ari >>= I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 1705 1706 func = ixl_rd(sc, I40E_PF_FUNC_RID); 1707 sc->sc_pf_id = func & (ari ? 0xff : 0x7); 1708 1709 /* initialise the adminq */ 1710 1711 if (ixl_dmamem_alloc(sc, &sc->sc_atq, 1712 sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) { 1713 printf("\n" "%s: unable to allocate atq\n", DEVNAME(sc)); 1714 goto unmap; 1715 } 1716 1717 SIMPLEQ_INIT(&sc->sc_arq_idle); 1718 SIMPLEQ_INIT(&sc->sc_arq_live); 1719 if_rxr_init(&sc->sc_arq_ring, 2, IXL_AQ_NUM - 1); 1720 task_set(&sc->sc_arq_task, ixl_arq, sc); 1721 sc->sc_arq_cons = 0; 1722 sc->sc_arq_prod = 0; 1723 1724 if (ixl_dmamem_alloc(sc, &sc->sc_arq, 1725 sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) { 1726 printf("\n" "%s: unable to allocate arq\n", DEVNAME(sc)); 1727 goto free_atq; 1728 } 1729 1730 if (!ixl_arq_fill(sc)) { 1731 printf("\n" "%s: unable to fill arq descriptors\n", 1732 DEVNAME(sc)); 1733 goto free_arq; 1734 } 1735 1736 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 1737 0, IXL_DMA_LEN(&sc->sc_atq), 1738 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1739 1740 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 1741 0, IXL_DMA_LEN(&sc->sc_arq), 1742 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1743 1744 for (tries = 0; tries < 10; tries++) { 1745 int rv; 1746 1747 sc->sc_atq_cons = 0; 1748 sc->sc_atq_prod = 0; 1749 1750 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 1751 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 1752 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 1753 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 1754 1755 ixl_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 1756 1757 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 1758 ixl_dmamem_lo(&sc->sc_atq)); 1759 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 1760 ixl_dmamem_hi(&sc->sc_atq)); 1761 ixl_wr(sc, sc->sc_aq_regs->atq_len, 1762 sc->sc_aq_regs->atq_len_enable | IXL_AQ_NUM); 1763 1764 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 1765 ixl_dmamem_lo(&sc->sc_arq)); 1766 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 1767 ixl_dmamem_hi(&sc->sc_arq)); 1768 ixl_wr(sc, sc->sc_aq_regs->arq_len, 1769 sc->sc_aq_regs->arq_len_enable | IXL_AQ_NUM); 1770 1771 rv = ixl_get_version(sc); 1772 if (rv == 0) 1773 break; 1774 if (rv != ETIMEDOUT) { 1775 printf(", unable to get firmware version\n"); 1776 goto shutdown; 1777 } 1778 1779 delaymsec(100); 1780 } 1781 1782 ixl_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 1783 1784 if (ixl_pxe_clear(sc) != 0) { 1785 /* error printed by ixl_pxe_clear */ 1786 goto shutdown; 1787 } 1788 1789 if (ixl_get_mac(sc) != 0) { 1790 /* error printed by ixl_get_mac */ 1791 goto shutdown; 1792 } 1793 1794 if (pci_intr_map_msix(pa, 0, &sc->sc_ih) == 0) { 1795 int nmsix = pci_intr_msix_count(pa->pa_pc, pa->pa_tag); 1796 if (nmsix > 1) { /* we used 1 (the 0th) for the adminq */ 1797 nmsix--; 1798 1799 sc->sc_intrmap = intrmap_create(&sc->sc_dev, 1800 nmsix, IXL_MAX_VECTORS, INTRMAP_POWEROF2); 1801 nqueues = intrmap_count(sc->sc_intrmap); 1802 KASSERT(nqueues > 0); 1803 KASSERT(powerof2(nqueues)); 1804 sc->sc_nqueues = fls(nqueues) - 1; 1805 } 1806 } else { 1807 if (pci_intr_map_msi(pa, &sc->sc_ih) != 0 && 1808 pci_intr_map(pa, &sc->sc_ih) != 0) { 1809 printf(", unable to map interrupt\n"); 1810 goto shutdown; 1811 } 1812 } 1813 1814 nqueues = ixl_nqueues(sc); 1815 1816 printf(", %s, %d queue%s, address %s\n", 1817 pci_intr_string(sc->sc_pc, sc->sc_ih), ixl_nqueues(sc), 1818 (nqueues > 1 ? "s" : ""), 1819 ether_sprintf(sc->sc_ac.ac_enaddr)); 1820 1821 if (ixl_hmc(sc) != 0) { 1822 /* error printed by ixl_hmc */ 1823 goto shutdown; 1824 } 1825 1826 if (ixl_lldp_shut(sc) != 0) { 1827 /* error printed by ixl_lldp_shut */ 1828 goto free_hmc; 1829 } 1830 1831 if (ixl_phy_mask_ints(sc) != 0) { 1832 /* error printed by ixl_phy_mask_ints */ 1833 goto free_hmc; 1834 } 1835 1836 if (ixl_restart_an(sc) != 0) { 1837 /* error printed by ixl_restart_an */ 1838 goto free_hmc; 1839 } 1840 1841 if (ixl_get_switch_config(sc) != 0) { 1842 /* error printed by ixl_get_switch_config */ 1843 goto free_hmc; 1844 } 1845 1846 if (ixl_get_phy_types(sc, &phy_types) != 0) { 1847 /* error printed by ixl_get_phy_abilities */ 1848 goto free_hmc; 1849 } 1850 1851 if (ixl_get_link_status(sc) != 0) { 1852 /* error printed by ixl_get_link_status */ 1853 goto free_hmc; 1854 } 1855 1856 if (ixl_dmamem_alloc(sc, &sc->sc_scratch, 1857 sizeof(struct ixl_aq_vsi_data), 8) != 0) { 1858 printf("%s: unable to allocate scratch buffer\n", DEVNAME(sc)); 1859 goto free_hmc; 1860 } 1861 1862 if (ixl_get_vsi(sc) != 0) { 1863 /* error printed by ixl_get_vsi */ 1864 goto free_hmc; 1865 } 1866 1867 if (ixl_set_vsi(sc) != 0) { 1868 /* error printed by ixl_set_vsi */ 1869 goto free_scratch; 1870 } 1871 1872 sc->sc_ihc = pci_intr_establish(sc->sc_pc, sc->sc_ih, 1873 IPL_NET | IPL_MPSAFE, ixl_intr0, sc, DEVNAME(sc)); 1874 if (sc->sc_ihc == NULL) { 1875 printf("%s: unable to establish interrupt handler\n", 1876 DEVNAME(sc)); 1877 goto free_scratch; 1878 } 1879 1880 sc->sc_vectors = mallocarray(sizeof(*sc->sc_vectors), nqueues, 1881 M_DEVBUF, M_WAITOK|M_CANFAIL|M_ZERO); 1882 if (sc->sc_vectors == NULL) { 1883 printf("%s: unable to allocate vectors\n", DEVNAME(sc)); 1884 goto free_scratch; 1885 } 1886 1887 for (i = 0; i < nqueues; i++) { 1888 struct ixl_vector *iv = &sc->sc_vectors[i]; 1889 iv->iv_sc = sc; 1890 iv->iv_qid = i; 1891 snprintf(iv->iv_name, sizeof(iv->iv_name), 1892 "%s:%u", DEVNAME(sc), i); /* truncated? */ 1893 } 1894 1895 if (sc->sc_intrmap) { 1896 for (i = 0; i < nqueues; i++) { 1897 struct ixl_vector *iv = &sc->sc_vectors[i]; 1898 pci_intr_handle_t ih; 1899 int v = i + 1; /* 0 is used for adminq */ 1900 1901 if (pci_intr_map_msix(pa, v, &ih)) { 1902 printf("%s: unable to map msi-x vector %d\n", 1903 DEVNAME(sc), v); 1904 goto free_vectors; 1905 } 1906 1907 iv->iv_ihc = pci_intr_establish_cpu(sc->sc_pc, ih, 1908 IPL_NET | IPL_MPSAFE, 1909 intrmap_cpu(sc->sc_intrmap, i), 1910 ixl_intr_vector, iv, iv->iv_name); 1911 if (iv->iv_ihc == NULL) { 1912 printf("%s: unable to establish interrupt %d\n", 1913 DEVNAME(sc), v); 1914 goto free_vectors; 1915 } 1916 1917 ixl_wr(sc, I40E_PFINT_DYN_CTLN(i), 1918 I40E_PFINT_DYN_CTLN_INTENA_MASK | 1919 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1920 (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)); 1921 } 1922 } 1923 1924 /* fixup the chip ops for older fw releases */ 1925 if (sc->sc_chip == &ixl_710 && 1926 sc->sc_api_major == 1 && sc->sc_api_minor < 5) 1927 sc->sc_chip = &ixl_710_decrepit; 1928 1929 ifp->if_softc = sc; 1930 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1931 ifp->if_xflags = IFXF_MPSAFE; 1932 ifp->if_ioctl = ixl_ioctl; 1933 ifp->if_qstart = ixl_start; 1934 ifp->if_watchdog = ixl_watchdog; 1935 ifp->if_hardmtu = IXL_HARDMTU; 1936 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 1937 ifq_set_maxlen(&ifp->if_snd, sc->sc_tx_ring_ndescs); 1938 1939 ifp->if_capabilities = IFCAP_VLAN_MTU; 1940 #if 0 1941 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1942 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1943 IFCAP_CSUM_UDPv4; 1944 #endif 1945 1946 ifmedia_init(&sc->sc_media, 0, ixl_media_change, ixl_media_status); 1947 1948 ixl_media_add(sc, phy_types); 1949 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 1950 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 1951 1952 if_attach(ifp); 1953 ether_ifattach(ifp); 1954 1955 if_attach_queues(ifp, nqueues); 1956 if_attach_iqueues(ifp, nqueues); 1957 1958 mtx_init(&sc->sc_link_state_mtx, IPL_NET); 1959 task_set(&sc->sc_link_state_task, ixl_link_state_update, sc); 1960 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 1961 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | 1962 I40E_PFINT_ICR0_ENA_ADMINQ_MASK); 1963 ixl_wr(sc, I40E_PFINT_STAT_CTL0, 1964 IXL_NOITR << I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT); 1965 1966 /* remove default mac filter and replace it so we can see vlans */ 1967 ixl_remove_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 0); 1968 ixl_remove_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 1969 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1970 ixl_add_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 1971 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 1972 ixl_add_macvlan(sc, etherbroadcastaddr, 0, 1973 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 1974 memcpy(sc->sc_enaddr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 1975 1976 ixl_intr_enable(sc); 1977 1978 #if NKSTAT > 0 1979 ixl_kstat_attach(sc); 1980 #endif 1981 1982 return; 1983 free_vectors: 1984 if (sc->sc_intrmap != NULL) { 1985 for (i = 0; i < nqueues; i++) { 1986 struct ixl_vector *iv = &sc->sc_vectors[i]; 1987 if (iv->iv_ihc == NULL) 1988 continue; 1989 pci_intr_disestablish(sc->sc_pc, iv->iv_ihc); 1990 } 1991 } 1992 free(sc->sc_vectors, M_DEVBUF, nqueues * sizeof(*sc->sc_vectors)); 1993 free_scratch: 1994 ixl_dmamem_free(sc, &sc->sc_scratch); 1995 free_hmc: 1996 ixl_hmc_free(sc); 1997 shutdown: 1998 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 1999 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 2000 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 2001 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 2002 2003 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 0); 2004 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 0); 2005 ixl_wr(sc, sc->sc_aq_regs->atq_len, 0); 2006 2007 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 0); 2008 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 0); 2009 ixl_wr(sc, sc->sc_aq_regs->arq_len, 0); 2010 2011 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 2012 0, IXL_DMA_LEN(&sc->sc_arq), 2013 BUS_DMASYNC_POSTREAD); 2014 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 2015 0, IXL_DMA_LEN(&sc->sc_atq), 2016 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2017 2018 ixl_arq_unfill(sc); 2019 2020 free_arq: 2021 ixl_dmamem_free(sc, &sc->sc_arq); 2022 free_atq: 2023 ixl_dmamem_free(sc, &sc->sc_atq); 2024 unmap: 2025 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 2026 sc->sc_mems = 0; 2027 2028 if (sc->sc_intrmap != NULL) 2029 intrmap_destroy(sc->sc_intrmap); 2030 } 2031 2032 static void 2033 ixl_media_add(struct ixl_softc *sc, uint64_t phy_types) 2034 { 2035 struct ifmedia *ifm = &sc->sc_media; 2036 const struct ixl_phy_type *itype; 2037 unsigned int i; 2038 2039 for (i = 0; i < nitems(ixl_phy_type_map); i++) { 2040 itype = &ixl_phy_type_map[i]; 2041 2042 if (ISSET(phy_types, itype->phy_type)) 2043 ifmedia_add(ifm, IFM_ETHER | itype->ifm_type, 0, NULL); 2044 } 2045 } 2046 2047 static int 2048 ixl_media_change(struct ifnet *ifp) 2049 { 2050 /* ignore? */ 2051 return (EOPNOTSUPP); 2052 } 2053 2054 static void 2055 ixl_media_status(struct ifnet *ifp, struct ifmediareq *ifm) 2056 { 2057 struct ixl_softc *sc = ifp->if_softc; 2058 2059 NET_ASSERT_LOCKED(); 2060 2061 ifm->ifm_status = sc->sc_media_status; 2062 ifm->ifm_active = sc->sc_media_active; 2063 } 2064 2065 static void 2066 ixl_watchdog(struct ifnet *ifp) 2067 { 2068 2069 } 2070 2071 int 2072 ixl_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2073 { 2074 struct ixl_softc *sc = (struct ixl_softc *)ifp->if_softc; 2075 struct ifreq *ifr = (struct ifreq *)data; 2076 uint8_t addrhi[ETHER_ADDR_LEN], addrlo[ETHER_ADDR_LEN]; 2077 int aqerror, error = 0; 2078 2079 switch (cmd) { 2080 case SIOCSIFADDR: 2081 ifp->if_flags |= IFF_UP; 2082 /* FALLTHROUGH */ 2083 2084 case SIOCSIFFLAGS: 2085 if (ISSET(ifp->if_flags, IFF_UP)) { 2086 if (ISSET(ifp->if_flags, IFF_RUNNING)) 2087 error = ENETRESET; 2088 else 2089 error = ixl_up(sc); 2090 } else { 2091 if (ISSET(ifp->if_flags, IFF_RUNNING)) 2092 error = ixl_down(sc); 2093 } 2094 break; 2095 2096 case SIOCGIFMEDIA: 2097 case SIOCSIFMEDIA: 2098 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 2099 break; 2100 2101 case SIOCGIFRXR: 2102 error = ixl_rxrinfo(sc, (struct if_rxrinfo *)ifr->ifr_data); 2103 break; 2104 2105 case SIOCADDMULTI: 2106 if (ether_addmulti(ifr, &sc->sc_ac) == ENETRESET) { 2107 error = ether_multiaddr(&ifr->ifr_addr, addrlo, addrhi); 2108 if (error != 0) 2109 return (error); 2110 2111 aqerror = ixl_add_macvlan(sc, addrlo, 0, 2112 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 2113 if (aqerror == IXL_AQ_RC_ENOSPC) { 2114 ether_delmulti(ifr, &sc->sc_ac); 2115 error = ENOSPC; 2116 } 2117 2118 if (sc->sc_ac.ac_multirangecnt > 0) { 2119 SET(ifp->if_flags, IFF_ALLMULTI); 2120 error = ENETRESET; 2121 } 2122 } 2123 break; 2124 2125 case SIOCDELMULTI: 2126 if (ether_delmulti(ifr, &sc->sc_ac) == ENETRESET) { 2127 error = ether_multiaddr(&ifr->ifr_addr, addrlo, addrhi); 2128 if (error != 0) 2129 return (error); 2130 2131 ixl_remove_macvlan(sc, addrlo, 0, 2132 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 2133 2134 if (ISSET(ifp->if_flags, IFF_ALLMULTI) && 2135 sc->sc_ac.ac_multirangecnt == 0) { 2136 CLR(ifp->if_flags, IFF_ALLMULTI); 2137 error = ENETRESET; 2138 } 2139 } 2140 break; 2141 2142 case SIOCGIFSFFPAGE: 2143 error = rw_enter(&ixl_sff_lock, RW_WRITE|RW_INTR); 2144 if (error != 0) 2145 break; 2146 2147 error = ixl_get_sffpage(sc, (struct if_sffpage *)data); 2148 rw_exit(&ixl_sff_lock); 2149 break; 2150 2151 default: 2152 error = ether_ioctl(ifp, &sc->sc_ac, cmd, data); 2153 break; 2154 } 2155 2156 if (error == ENETRESET) 2157 error = ixl_iff(sc); 2158 2159 return (error); 2160 } 2161 2162 static inline void * 2163 ixl_hmc_kva(struct ixl_softc *sc, unsigned int type, unsigned int i) 2164 { 2165 uint8_t *kva = IXL_DMA_KVA(&sc->sc_hmc_pd); 2166 struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type]; 2167 2168 if (i >= e->hmc_count) 2169 return (NULL); 2170 2171 kva += e->hmc_base; 2172 kva += i * e->hmc_size; 2173 2174 return (kva); 2175 } 2176 2177 static inline size_t 2178 ixl_hmc_len(struct ixl_softc *sc, unsigned int type) 2179 { 2180 struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type]; 2181 2182 return (e->hmc_size); 2183 } 2184 2185 static int 2186 ixl_configure_rss(struct ixl_softc *sc) 2187 { 2188 struct ixl_rss_key rsskey; 2189 struct ixl_rss_lut_128 lut; 2190 uint8_t *lute = (uint8_t *)&lut; 2191 uint64_t rss_hena; 2192 unsigned int i, nqueues; 2193 int error; 2194 2195 #if 0 2196 /* if we want to do a 512 entry LUT, do this. */ 2197 uint32_t v = ixl_rd_ctl(sc, I40E_PFQF_CTL_0); 2198 SET(v, I40E_PFQF_CTL_0_HASHLUTSIZE_MASK); 2199 ixl_wr_ctl(sc, I40E_PFQF_CTL_0, v); 2200 #endif 2201 2202 stoeplitz_to_key(&rsskey, sizeof(rsskey)); 2203 2204 nqueues = ixl_nqueues(sc); 2205 for (i = 0; i < sizeof(lut); i++) { 2206 /* 2207 * ixl must have a power of 2 rings, so using mod 2208 * to populate the table is fine. 2209 */ 2210 lute[i] = i % nqueues; 2211 } 2212 2213 error = ixl_set_rss_key(sc, &rsskey); 2214 if (error != 0) 2215 return (error); 2216 2217 rss_hena = (uint64_t)ixl_rd_ctl(sc, I40E_PFQF_HENA(0)); 2218 rss_hena |= (uint64_t)ixl_rd_ctl(sc, I40E_PFQF_HENA(1)) << 32; 2219 rss_hena |= ixl_rss_hena(sc); 2220 ixl_wr_ctl(sc, I40E_PFQF_HENA(0), rss_hena); 2221 ixl_wr_ctl(sc, I40E_PFQF_HENA(1), rss_hena >> 32); 2222 2223 error = ixl_set_rss_lut(sc, &lut); 2224 if (error != 0) 2225 return (error); 2226 2227 /* nothing to clena up :( */ 2228 2229 return (0); 2230 } 2231 2232 static int 2233 ixl_up(struct ixl_softc *sc) 2234 { 2235 struct ifnet *ifp = &sc->sc_ac.ac_if; 2236 struct ifqueue *ifq; 2237 struct ifiqueue *ifiq; 2238 struct ixl_vector *iv; 2239 struct ixl_rx_ring *rxr; 2240 struct ixl_tx_ring *txr; 2241 unsigned int nqueues, i; 2242 uint32_t reg; 2243 int rv = ENOMEM; 2244 2245 nqueues = ixl_nqueues(sc); 2246 2247 rw_enter_write(&sc->sc_cfg_lock); 2248 if (sc->sc_dead) { 2249 rw_exit_write(&sc->sc_cfg_lock); 2250 return (ENXIO); 2251 } 2252 2253 /* allocation is the only thing that can fail, so do it up front */ 2254 for (i = 0; i < nqueues; i++) { 2255 rxr = ixl_rxr_alloc(sc, i); 2256 if (rxr == NULL) 2257 goto free; 2258 2259 txr = ixl_txr_alloc(sc, i); 2260 if (txr == NULL) { 2261 ixl_rxr_free(sc, rxr); 2262 goto free; 2263 } 2264 2265 /* wire everything together */ 2266 iv = &sc->sc_vectors[i]; 2267 iv->iv_rxr = rxr; 2268 iv->iv_txr = txr; 2269 2270 ifq = ifp->if_ifqs[i]; 2271 ifq->ifq_softc = txr; 2272 txr->txr_ifq = ifq; 2273 2274 ifiq = ifp->if_iqs[i]; 2275 ifiq->ifiq_softc = rxr; 2276 rxr->rxr_ifiq = ifiq; 2277 } 2278 2279 /* XXX wait 50ms from completion of last RX queue disable */ 2280 2281 for (i = 0; i < nqueues; i++) { 2282 iv = &sc->sc_vectors[i]; 2283 rxr = iv->iv_rxr; 2284 txr = iv->iv_txr; 2285 2286 ixl_txr_qdis(sc, txr, 1); 2287 2288 ixl_rxr_config(sc, rxr); 2289 ixl_txr_config(sc, txr); 2290 2291 ixl_wr(sc, I40E_QTX_CTL(i), I40E_QTX_CTL_PF_QUEUE | 2292 (sc->sc_pf_id << I40E_QTX_CTL_PF_INDX_SHIFT)); 2293 2294 ixl_wr(sc, rxr->rxr_tail, 0); 2295 ixl_rxfill(sc, rxr); 2296 2297 reg = ixl_rd(sc, I40E_QRX_ENA(i)); 2298 SET(reg, I40E_QRX_ENA_QENA_REQ_MASK); 2299 ixl_wr(sc, I40E_QRX_ENA(i), reg); 2300 2301 reg = ixl_rd(sc, I40E_QTX_ENA(i)); 2302 SET(reg, I40E_QTX_ENA_QENA_REQ_MASK); 2303 ixl_wr(sc, I40E_QTX_ENA(i), reg); 2304 } 2305 2306 for (i = 0; i < nqueues; i++) { 2307 iv = &sc->sc_vectors[i]; 2308 rxr = iv->iv_rxr; 2309 txr = iv->iv_txr; 2310 2311 if (ixl_rxr_enabled(sc, rxr) != 0) 2312 goto down; 2313 2314 if (ixl_txr_enabled(sc, txr) != 0) 2315 goto down; 2316 } 2317 2318 ixl_configure_rss(sc); 2319 2320 SET(ifp->if_flags, IFF_RUNNING); 2321 2322 if (sc->sc_intrmap == NULL) { 2323 ixl_wr(sc, I40E_PFINT_LNKLST0, 2324 (I40E_INTR_NOTX_QUEUE << 2325 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 2326 (I40E_QUEUE_TYPE_RX << 2327 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 2328 2329 ixl_wr(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), 2330 (I40E_INTR_NOTX_INTR << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 2331 (I40E_ITR_INDEX_RX << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 2332 (I40E_INTR_NOTX_RX_QUEUE << 2333 I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) | 2334 (I40E_INTR_NOTX_QUEUE << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 2335 (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 2336 I40E_QINT_RQCTL_CAUSE_ENA_MASK); 2337 2338 ixl_wr(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), 2339 (I40E_INTR_NOTX_INTR << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 2340 (I40E_ITR_INDEX_TX << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 2341 (I40E_INTR_NOTX_TX_QUEUE << 2342 I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) | 2343 (I40E_QUEUE_TYPE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 2344 (I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) | 2345 I40E_QINT_TQCTL_CAUSE_ENA_MASK); 2346 } else { 2347 /* vector 0 has no queues */ 2348 ixl_wr(sc, I40E_PFINT_LNKLST0, 2349 I40E_QUEUE_TYPE_EOL << 2350 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT); 2351 2352 /* queue n is mapped to vector n+1 */ 2353 for (i = 0; i < nqueues; i++) { 2354 /* LNKLSTN(i) configures vector i+1 */ 2355 ixl_wr(sc, I40E_PFINT_LNKLSTN(i), 2356 (i << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) | 2357 (I40E_QUEUE_TYPE_RX << 2358 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 2359 ixl_wr(sc, I40E_QINT_RQCTL(i), 2360 ((i+1) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 2361 (I40E_ITR_INDEX_RX << 2362 I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 2363 (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 2364 (I40E_QUEUE_TYPE_TX << 2365 I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 2366 I40E_QINT_RQCTL_CAUSE_ENA_MASK); 2367 ixl_wr(sc, I40E_QINT_TQCTL(i), 2368 ((i+1) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 2369 (I40E_ITR_INDEX_TX << 2370 I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 2371 (I40E_QUEUE_TYPE_EOL << 2372 I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 2373 (I40E_QUEUE_TYPE_RX << 2374 I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) | 2375 I40E_QINT_TQCTL_CAUSE_ENA_MASK); 2376 2377 ixl_wr(sc, I40E_PFINT_ITRN(0, i), 0x7a); 2378 ixl_wr(sc, I40E_PFINT_ITRN(1, i), 0x7a); 2379 ixl_wr(sc, I40E_PFINT_ITRN(2, i), 0); 2380 } 2381 } 2382 2383 ixl_wr(sc, I40E_PFINT_ITR0(0), 0x7a); 2384 ixl_wr(sc, I40E_PFINT_ITR0(1), 0x7a); 2385 ixl_wr(sc, I40E_PFINT_ITR0(2), 0); 2386 2387 rw_exit_write(&sc->sc_cfg_lock); 2388 2389 return (ENETRESET); 2390 2391 free: 2392 for (i = 0; i < nqueues; i++) { 2393 iv = &sc->sc_vectors[i]; 2394 rxr = iv->iv_rxr; 2395 txr = iv->iv_txr; 2396 2397 if (rxr == NULL) { 2398 /* 2399 * tx and rx get set at the same time, so if one 2400 * is NULL, the other is too. 2401 */ 2402 continue; 2403 } 2404 2405 ixl_txr_free(sc, txr); 2406 ixl_rxr_free(sc, rxr); 2407 } 2408 rw_exit_write(&sc->sc_cfg_lock); 2409 return (rv); 2410 down: 2411 rw_exit_write(&sc->sc_cfg_lock); 2412 ixl_down(sc); 2413 return (ETIMEDOUT); 2414 } 2415 2416 static int 2417 ixl_iff(struct ixl_softc *sc) 2418 { 2419 struct ifnet *ifp = &sc->sc_ac.ac_if; 2420 struct ixl_atq iatq; 2421 struct ixl_aq_desc *iaq; 2422 struct ixl_aq_vsi_promisc_param *param; 2423 2424 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 2425 return (0); 2426 2427 memset(&iatq, 0, sizeof(iatq)); 2428 2429 iaq = &iatq.iatq_desc; 2430 iaq->iaq_opcode = htole16(IXL_AQ_OP_SET_VSI_PROMISC); 2431 2432 param = (struct ixl_aq_vsi_promisc_param *)&iaq->iaq_param; 2433 param->flags = htole16(IXL_AQ_VSI_PROMISC_FLAG_BCAST | 2434 IXL_AQ_VSI_PROMISC_FLAG_VLAN); 2435 if (ISSET(ifp->if_flags, IFF_PROMISC)) { 2436 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST | 2437 IXL_AQ_VSI_PROMISC_FLAG_MCAST); 2438 } else if (ISSET(ifp->if_flags, IFF_ALLMULTI)) { 2439 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_MCAST); 2440 } 2441 param->valid_flags = htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST | 2442 IXL_AQ_VSI_PROMISC_FLAG_MCAST | IXL_AQ_VSI_PROMISC_FLAG_BCAST | 2443 IXL_AQ_VSI_PROMISC_FLAG_VLAN); 2444 param->seid = sc->sc_seid; 2445 2446 ixl_atq_exec(sc, &iatq, "ixliff"); 2447 2448 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK)) 2449 return (EIO); 2450 2451 if (memcmp(sc->sc_enaddr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN) != 0) { 2452 ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 2453 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 2454 ixl_add_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 2455 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 2456 memcpy(sc->sc_enaddr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 2457 } 2458 return (0); 2459 } 2460 2461 static int 2462 ixl_down(struct ixl_softc *sc) 2463 { 2464 struct ifnet *ifp = &sc->sc_ac.ac_if; 2465 struct ixl_vector *iv; 2466 struct ixl_rx_ring *rxr; 2467 struct ixl_tx_ring *txr; 2468 unsigned int nqueues, i; 2469 uint32_t reg; 2470 int error = 0; 2471 2472 nqueues = ixl_nqueues(sc); 2473 2474 rw_enter_write(&sc->sc_cfg_lock); 2475 2476 CLR(ifp->if_flags, IFF_RUNNING); 2477 2478 NET_UNLOCK(); 2479 2480 /* mask interrupts */ 2481 reg = ixl_rd(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE)); 2482 CLR(reg, I40E_QINT_RQCTL_CAUSE_ENA_MASK); 2483 ixl_wr(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), reg); 2484 2485 reg = ixl_rd(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE)); 2486 CLR(reg, I40E_QINT_TQCTL_CAUSE_ENA_MASK); 2487 ixl_wr(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), reg); 2488 2489 ixl_wr(sc, I40E_PFINT_LNKLST0, I40E_QUEUE_TYPE_EOL); 2490 2491 /* make sure the no hw generated work is still in flight */ 2492 intr_barrier(sc->sc_ihc); 2493 if (sc->sc_intrmap != NULL) { 2494 for (i = 0; i < nqueues; i++) { 2495 iv = &sc->sc_vectors[i]; 2496 rxr = iv->iv_rxr; 2497 txr = iv->iv_txr; 2498 2499 ixl_txr_qdis(sc, txr, 0); 2500 2501 ifq_barrier(txr->txr_ifq); 2502 2503 timeout_del_barrier(&rxr->rxr_refill); 2504 2505 intr_barrier(iv->iv_ihc); 2506 } 2507 } 2508 2509 /* XXX wait at least 400 usec for all tx queues in one go */ 2510 delay(500); 2511 2512 for (i = 0; i < nqueues; i++) { 2513 reg = ixl_rd(sc, I40E_QTX_ENA(i)); 2514 CLR(reg, I40E_QTX_ENA_QENA_REQ_MASK); 2515 ixl_wr(sc, I40E_QTX_ENA(i), reg); 2516 2517 reg = ixl_rd(sc, I40E_QRX_ENA(i)); 2518 CLR(reg, I40E_QRX_ENA_QENA_REQ_MASK); 2519 ixl_wr(sc, I40E_QRX_ENA(i), reg); 2520 } 2521 2522 for (i = 0; i < nqueues; i++) { 2523 iv = &sc->sc_vectors[i]; 2524 rxr = iv->iv_rxr; 2525 txr = iv->iv_txr; 2526 2527 if (ixl_txr_disabled(sc, txr) != 0) 2528 goto die; 2529 2530 if (ixl_rxr_disabled(sc, rxr) != 0) 2531 goto die; 2532 } 2533 2534 for (i = 0; i < nqueues; i++) { 2535 iv = &sc->sc_vectors[i]; 2536 rxr = iv->iv_rxr; 2537 txr = iv->iv_txr; 2538 2539 ixl_txr_unconfig(sc, txr); 2540 ixl_rxr_unconfig(sc, rxr); 2541 2542 ixl_txr_clean(sc, txr); 2543 ixl_rxr_clean(sc, rxr); 2544 2545 ixl_txr_free(sc, txr); 2546 ixl_rxr_free(sc, rxr); 2547 2548 ifp->if_iqs[i]->ifiq_softc = NULL; 2549 ifp->if_ifqs[i]->ifq_softc = NULL; 2550 } 2551 2552 out: 2553 rw_exit_write(&sc->sc_cfg_lock); 2554 NET_LOCK(); 2555 return (error); 2556 die: 2557 sc->sc_dead = 1; 2558 log(LOG_CRIT, "%s: failed to shut down rings", DEVNAME(sc)); 2559 error = ETIMEDOUT; 2560 goto out; 2561 } 2562 2563 static struct ixl_tx_ring * 2564 ixl_txr_alloc(struct ixl_softc *sc, unsigned int qid) 2565 { 2566 struct ixl_tx_ring *txr; 2567 struct ixl_tx_map *maps, *txm; 2568 unsigned int i; 2569 2570 txr = malloc(sizeof(*txr), M_DEVBUF, M_WAITOK|M_CANFAIL); 2571 if (txr == NULL) 2572 return (NULL); 2573 2574 maps = mallocarray(sizeof(*maps), 2575 sc->sc_tx_ring_ndescs, M_DEVBUF, M_WAITOK|M_CANFAIL|M_ZERO); 2576 if (maps == NULL) 2577 goto free; 2578 2579 if (ixl_dmamem_alloc(sc, &txr->txr_mem, 2580 sizeof(struct ixl_tx_desc) * sc->sc_tx_ring_ndescs, 2581 IXL_TX_QUEUE_ALIGN) != 0) 2582 goto freemap; 2583 2584 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2585 txm = &maps[i]; 2586 2587 if (bus_dmamap_create(sc->sc_dmat, 2588 IXL_HARDMTU, IXL_TX_PKT_DESCS, IXL_HARDMTU, 0, 2589 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 2590 &txm->txm_map) != 0) 2591 goto uncreate; 2592 2593 txm->txm_eop = -1; 2594 txm->txm_m = NULL; 2595 } 2596 2597 txr->txr_cons = txr->txr_prod = 0; 2598 txr->txr_maps = maps; 2599 2600 txr->txr_tail = I40E_QTX_TAIL(qid); 2601 txr->txr_qid = qid; 2602 2603 return (txr); 2604 2605 uncreate: 2606 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2607 txm = &maps[i]; 2608 2609 if (txm->txm_map == NULL) 2610 continue; 2611 2612 bus_dmamap_destroy(sc->sc_dmat, txm->txm_map); 2613 } 2614 2615 ixl_dmamem_free(sc, &txr->txr_mem); 2616 freemap: 2617 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_tx_ring_ndescs); 2618 free: 2619 free(txr, M_DEVBUF, sizeof(*txr)); 2620 return (NULL); 2621 } 2622 2623 static void 2624 ixl_txr_qdis(struct ixl_softc *sc, struct ixl_tx_ring *txr, int enable) 2625 { 2626 unsigned int qid; 2627 bus_size_t reg; 2628 uint32_t r; 2629 2630 qid = txr->txr_qid + sc->sc_base_queue; 2631 reg = I40E_GLLAN_TXPRE_QDIS(qid / 128); 2632 qid %= 128; 2633 2634 r = ixl_rd(sc, reg); 2635 CLR(r, I40E_GLLAN_TXPRE_QDIS_QINDX_MASK); 2636 SET(r, qid << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 2637 SET(r, enable ? I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK : 2638 I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK); 2639 ixl_wr(sc, reg, r); 2640 } 2641 2642 static void 2643 ixl_txr_config(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2644 { 2645 struct ixl_hmc_txq txq; 2646 struct ixl_aq_vsi_data *data = IXL_DMA_KVA(&sc->sc_scratch); 2647 void *hmc; 2648 2649 memset(&txq, 0, sizeof(txq)); 2650 txq.head = htole16(0); 2651 txq.new_context = 1; 2652 htolem64(&txq.base, 2653 IXL_DMA_DVA(&txr->txr_mem) / IXL_HMC_TXQ_BASE_UNIT); 2654 txq.head_wb_ena = IXL_HMC_TXQ_DESC_WB; 2655 htolem16(&txq.qlen, sc->sc_tx_ring_ndescs); 2656 txq.tphrdesc_ena = 0; 2657 txq.tphrpacket_ena = 0; 2658 txq.tphwdesc_ena = 0; 2659 txq.rdylist = data->qs_handle[0]; 2660 2661 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid); 2662 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX)); 2663 ixl_hmc_pack(hmc, &txq, ixl_hmc_pack_txq, nitems(ixl_hmc_pack_txq)); 2664 } 2665 2666 static void 2667 ixl_txr_unconfig(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2668 { 2669 void *hmc; 2670 2671 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid); 2672 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX)); 2673 } 2674 2675 static void 2676 ixl_txr_clean(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2677 { 2678 struct ixl_tx_map *maps, *txm; 2679 bus_dmamap_t map; 2680 unsigned int i; 2681 2682 maps = txr->txr_maps; 2683 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2684 txm = &maps[i]; 2685 2686 if (txm->txm_m == NULL) 2687 continue; 2688 2689 map = txm->txm_map; 2690 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2691 BUS_DMASYNC_POSTWRITE); 2692 bus_dmamap_unload(sc->sc_dmat, map); 2693 2694 m_freem(txm->txm_m); 2695 txm->txm_m = NULL; 2696 } 2697 } 2698 2699 static int 2700 ixl_txr_enabled(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2701 { 2702 bus_size_t ena = I40E_QTX_ENA(txr->txr_qid); 2703 uint32_t reg; 2704 int i; 2705 2706 for (i = 0; i < 10; i++) { 2707 reg = ixl_rd(sc, ena); 2708 if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK)) 2709 return (0); 2710 2711 delaymsec(10); 2712 } 2713 2714 return (ETIMEDOUT); 2715 } 2716 2717 static int 2718 ixl_txr_disabled(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2719 { 2720 bus_size_t ena = I40E_QTX_ENA(txr->txr_qid); 2721 uint32_t reg; 2722 int i; 2723 2724 for (i = 0; i < 20; i++) { 2725 reg = ixl_rd(sc, ena); 2726 if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK) == 0) 2727 return (0); 2728 2729 delaymsec(10); 2730 } 2731 2732 return (ETIMEDOUT); 2733 } 2734 2735 static void 2736 ixl_txr_free(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2737 { 2738 struct ixl_tx_map *maps, *txm; 2739 unsigned int i; 2740 2741 maps = txr->txr_maps; 2742 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2743 txm = &maps[i]; 2744 2745 bus_dmamap_destroy(sc->sc_dmat, txm->txm_map); 2746 } 2747 2748 ixl_dmamem_free(sc, &txr->txr_mem); 2749 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_tx_ring_ndescs); 2750 free(txr, M_DEVBUF, sizeof(*txr)); 2751 } 2752 2753 static inline int 2754 ixl_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, struct mbuf *m) 2755 { 2756 int error; 2757 2758 error = bus_dmamap_load_mbuf(dmat, map, m, 2759 BUS_DMA_STREAMING | BUS_DMA_NOWAIT); 2760 if (error != EFBIG) 2761 return (error); 2762 2763 error = m_defrag(m, M_DONTWAIT); 2764 if (error != 0) 2765 return (error); 2766 2767 return (bus_dmamap_load_mbuf(dmat, map, m, 2768 BUS_DMA_STREAMING | BUS_DMA_NOWAIT)); 2769 } 2770 2771 static void 2772 ixl_start(struct ifqueue *ifq) 2773 { 2774 struct ifnet *ifp = ifq->ifq_if; 2775 struct ixl_softc *sc = ifp->if_softc; 2776 struct ixl_tx_ring *txr = ifq->ifq_softc; 2777 struct ixl_tx_desc *ring, *txd; 2778 struct ixl_tx_map *txm; 2779 bus_dmamap_t map; 2780 struct mbuf *m; 2781 uint64_t cmd; 2782 unsigned int prod, free, last, i; 2783 unsigned int mask; 2784 int post = 0; 2785 #if NBPFILTER > 0 2786 caddr_t if_bpf; 2787 #endif 2788 2789 if (!LINK_STATE_IS_UP(ifp->if_link_state)) { 2790 ifq_purge(ifq); 2791 return; 2792 } 2793 2794 prod = txr->txr_prod; 2795 free = txr->txr_cons; 2796 if (free <= prod) 2797 free += sc->sc_tx_ring_ndescs; 2798 free -= prod; 2799 2800 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2801 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTWRITE); 2802 2803 ring = IXL_DMA_KVA(&txr->txr_mem); 2804 mask = sc->sc_tx_ring_ndescs - 1; 2805 2806 for (;;) { 2807 if (free <= IXL_TX_PKT_DESCS) { 2808 ifq_set_oactive(ifq); 2809 break; 2810 } 2811 2812 m = ifq_dequeue(ifq); 2813 if (m == NULL) 2814 break; 2815 2816 txm = &txr->txr_maps[prod]; 2817 map = txm->txm_map; 2818 2819 if (ixl_load_mbuf(sc->sc_dmat, map, m) != 0) { 2820 ifq->ifq_errors++; 2821 m_freem(m); 2822 continue; 2823 } 2824 2825 bus_dmamap_sync(sc->sc_dmat, map, 0, 2826 map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2827 2828 for (i = 0; i < map->dm_nsegs; i++) { 2829 txd = &ring[prod]; 2830 2831 cmd = (uint64_t)map->dm_segs[i].ds_len << 2832 IXL_TX_DESC_BSIZE_SHIFT; 2833 cmd |= IXL_TX_DESC_DTYPE_DATA | IXL_TX_DESC_CMD_ICRC; 2834 2835 htolem64(&txd->addr, map->dm_segs[i].ds_addr); 2836 htolem64(&txd->cmd, cmd); 2837 2838 last = prod; 2839 2840 prod++; 2841 prod &= mask; 2842 } 2843 cmd |= IXL_TX_DESC_CMD_EOP | IXL_TX_DESC_CMD_RS; 2844 htolem64(&txd->cmd, cmd); 2845 2846 txm->txm_m = m; 2847 txm->txm_eop = last; 2848 2849 #if NBPFILTER > 0 2850 if_bpf = ifp->if_bpf; 2851 if (if_bpf) 2852 bpf_mtap_ether(if_bpf, m, BPF_DIRECTION_OUT); 2853 #endif 2854 2855 free -= i; 2856 post = 1; 2857 } 2858 2859 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2860 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREWRITE); 2861 2862 if (post) { 2863 txr->txr_prod = prod; 2864 ixl_wr(sc, txr->txr_tail, prod); 2865 } 2866 } 2867 2868 static int 2869 ixl_txeof(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2870 { 2871 struct ifqueue *ifq = txr->txr_ifq; 2872 struct ixl_tx_desc *ring, *txd; 2873 struct ixl_tx_map *txm; 2874 bus_dmamap_t map; 2875 unsigned int cons, prod, last; 2876 unsigned int mask; 2877 uint64_t dtype; 2878 int done = 0; 2879 2880 prod = txr->txr_prod; 2881 cons = txr->txr_cons; 2882 2883 if (cons == prod) 2884 return (0); 2885 2886 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2887 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTREAD); 2888 2889 ring = IXL_DMA_KVA(&txr->txr_mem); 2890 mask = sc->sc_tx_ring_ndescs - 1; 2891 2892 do { 2893 txm = &txr->txr_maps[cons]; 2894 last = txm->txm_eop; 2895 txd = &ring[last]; 2896 2897 dtype = txd->cmd & htole64(IXL_TX_DESC_DTYPE_MASK); 2898 if (dtype != htole64(IXL_TX_DESC_DTYPE_DONE)) 2899 break; 2900 2901 map = txm->txm_map; 2902 2903 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2904 BUS_DMASYNC_POSTWRITE); 2905 bus_dmamap_unload(sc->sc_dmat, map); 2906 m_freem(txm->txm_m); 2907 2908 txm->txm_m = NULL; 2909 txm->txm_eop = -1; 2910 2911 cons = last + 1; 2912 cons &= mask; 2913 2914 done = 1; 2915 } while (cons != prod); 2916 2917 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2918 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREREAD); 2919 2920 txr->txr_cons = cons; 2921 2922 //ixl_enable(sc, txr->txr_msix); 2923 2924 if (ifq_is_oactive(ifq)) 2925 ifq_restart(ifq); 2926 2927 return (done); 2928 } 2929 2930 static struct ixl_rx_ring * 2931 ixl_rxr_alloc(struct ixl_softc *sc, unsigned int qid) 2932 { 2933 struct ixl_rx_ring *rxr; 2934 struct ixl_rx_map *maps, *rxm; 2935 unsigned int i; 2936 2937 rxr = malloc(sizeof(*rxr), M_DEVBUF, M_WAITOK|M_CANFAIL); 2938 if (rxr == NULL) 2939 return (NULL); 2940 2941 maps = mallocarray(sizeof(*maps), 2942 sc->sc_rx_ring_ndescs, M_DEVBUF, M_WAITOK|M_CANFAIL|M_ZERO); 2943 if (maps == NULL) 2944 goto free; 2945 2946 if (ixl_dmamem_alloc(sc, &rxr->rxr_mem, 2947 sizeof(struct ixl_rx_rd_desc_16) * sc->sc_rx_ring_ndescs, 2948 IXL_RX_QUEUE_ALIGN) != 0) 2949 goto freemap; 2950 2951 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2952 rxm = &maps[i]; 2953 2954 if (bus_dmamap_create(sc->sc_dmat, 2955 IXL_HARDMTU, 1, IXL_HARDMTU, 0, 2956 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 2957 &rxm->rxm_map) != 0) 2958 goto uncreate; 2959 2960 rxm->rxm_m = NULL; 2961 } 2962 2963 rxr->rxr_sc = sc; 2964 if_rxr_init(&rxr->rxr_acct, 17, sc->sc_rx_ring_ndescs - 1); 2965 timeout_set(&rxr->rxr_refill, ixl_rxrefill, rxr); 2966 rxr->rxr_cons = rxr->rxr_prod = 0; 2967 rxr->rxr_m_head = NULL; 2968 rxr->rxr_m_tail = &rxr->rxr_m_head; 2969 rxr->rxr_maps = maps; 2970 2971 rxr->rxr_tail = I40E_QRX_TAIL(qid); 2972 rxr->rxr_qid = qid; 2973 2974 return (rxr); 2975 2976 uncreate: 2977 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2978 rxm = &maps[i]; 2979 2980 if (rxm->rxm_map == NULL) 2981 continue; 2982 2983 bus_dmamap_destroy(sc->sc_dmat, rxm->rxm_map); 2984 } 2985 2986 ixl_dmamem_free(sc, &rxr->rxr_mem); 2987 freemap: 2988 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_rx_ring_ndescs); 2989 free: 2990 free(rxr, M_DEVBUF, sizeof(*rxr)); 2991 return (NULL); 2992 } 2993 2994 static void 2995 ixl_rxr_clean(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 2996 { 2997 struct ixl_rx_map *maps, *rxm; 2998 bus_dmamap_t map; 2999 unsigned int i; 3000 3001 timeout_del_barrier(&rxr->rxr_refill); 3002 3003 maps = rxr->rxr_maps; 3004 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3005 rxm = &maps[i]; 3006 3007 if (rxm->rxm_m == NULL) 3008 continue; 3009 3010 map = rxm->rxm_map; 3011 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3012 BUS_DMASYNC_POSTWRITE); 3013 bus_dmamap_unload(sc->sc_dmat, map); 3014 3015 m_freem(rxm->rxm_m); 3016 rxm->rxm_m = NULL; 3017 } 3018 3019 m_freem(rxr->rxr_m_head); 3020 rxr->rxr_m_head = NULL; 3021 rxr->rxr_m_tail = &rxr->rxr_m_head; 3022 3023 rxr->rxr_prod = rxr->rxr_cons = 0; 3024 } 3025 3026 static int 3027 ixl_rxr_enabled(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3028 { 3029 bus_size_t ena = I40E_QRX_ENA(rxr->rxr_qid); 3030 uint32_t reg; 3031 int i; 3032 3033 for (i = 0; i < 10; i++) { 3034 reg = ixl_rd(sc, ena); 3035 if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK)) 3036 return (0); 3037 3038 delaymsec(10); 3039 } 3040 3041 return (ETIMEDOUT); 3042 } 3043 3044 static int 3045 ixl_rxr_disabled(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3046 { 3047 bus_size_t ena = I40E_QRX_ENA(rxr->rxr_qid); 3048 uint32_t reg; 3049 int i; 3050 3051 for (i = 0; i < 20; i++) { 3052 reg = ixl_rd(sc, ena); 3053 if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK) == 0) 3054 return (0); 3055 3056 delaymsec(10); 3057 } 3058 3059 return (ETIMEDOUT); 3060 } 3061 3062 static void 3063 ixl_rxr_config(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3064 { 3065 struct ixl_hmc_rxq rxq; 3066 void *hmc; 3067 3068 memset(&rxq, 0, sizeof(rxq)); 3069 3070 rxq.head = htole16(0); 3071 htolem64(&rxq.base, 3072 IXL_DMA_DVA(&rxr->rxr_mem) / IXL_HMC_RXQ_BASE_UNIT); 3073 htolem16(&rxq.qlen, sc->sc_rx_ring_ndescs); 3074 rxq.dbuff = htole16(MCLBYTES / IXL_HMC_RXQ_DBUFF_UNIT); 3075 rxq.hbuff = 0; 3076 rxq.dtype = IXL_HMC_RXQ_DTYPE_NOSPLIT; 3077 rxq.dsize = IXL_HMC_RXQ_DSIZE_16; 3078 rxq.crcstrip = 1; 3079 rxq.l2sel = 0; 3080 rxq.showiv = 0; 3081 rxq.rxmax = htole16(IXL_HARDMTU); 3082 rxq.tphrdesc_ena = 0; 3083 rxq.tphwdesc_ena = 0; 3084 rxq.tphdata_ena = 0; 3085 rxq.tphhead_ena = 0; 3086 rxq.lrxqthresh = 0; 3087 rxq.prefena = 1; 3088 3089 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_RX, rxr->rxr_qid); 3090 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_RX)); 3091 ixl_hmc_pack(hmc, &rxq, ixl_hmc_pack_rxq, nitems(ixl_hmc_pack_rxq)); 3092 } 3093 3094 static void 3095 ixl_rxr_unconfig(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3096 { 3097 void *hmc; 3098 3099 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_RX, rxr->rxr_qid); 3100 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_RX)); 3101 } 3102 3103 static void 3104 ixl_rxr_free(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3105 { 3106 struct ixl_rx_map *maps, *rxm; 3107 unsigned int i; 3108 3109 maps = rxr->rxr_maps; 3110 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3111 rxm = &maps[i]; 3112 3113 bus_dmamap_destroy(sc->sc_dmat, rxm->rxm_map); 3114 } 3115 3116 ixl_dmamem_free(sc, &rxr->rxr_mem); 3117 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_rx_ring_ndescs); 3118 free(rxr, M_DEVBUF, sizeof(*rxr)); 3119 } 3120 3121 static int 3122 ixl_rxeof(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3123 { 3124 struct ifiqueue *ifiq = rxr->rxr_ifiq; 3125 struct ifnet *ifp = &sc->sc_ac.ac_if; 3126 struct ixl_rx_wb_desc_16 *ring, *rxd; 3127 struct ixl_rx_map *rxm; 3128 bus_dmamap_t map; 3129 unsigned int cons, prod; 3130 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 3131 struct mbuf *m; 3132 uint64_t word; 3133 unsigned int len; 3134 unsigned int mask; 3135 int done = 0; 3136 3137 prod = rxr->rxr_prod; 3138 cons = rxr->rxr_cons; 3139 3140 if (cons == prod) 3141 return (0); 3142 3143 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 3144 0, IXL_DMA_LEN(&rxr->rxr_mem), 3145 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3146 3147 ring = IXL_DMA_KVA(&rxr->rxr_mem); 3148 mask = sc->sc_rx_ring_ndescs - 1; 3149 3150 do { 3151 rxd = &ring[cons]; 3152 3153 word = lemtoh64(&rxd->qword1); 3154 if (!ISSET(word, IXL_RX_DESC_DD)) 3155 break; 3156 3157 if_rxr_put(&rxr->rxr_acct, 1); 3158 3159 rxm = &rxr->rxr_maps[cons]; 3160 3161 map = rxm->rxm_map; 3162 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3163 BUS_DMASYNC_POSTREAD); 3164 bus_dmamap_unload(sc->sc_dmat, map); 3165 3166 m = rxm->rxm_m; 3167 rxm->rxm_m = NULL; 3168 3169 len = (word & IXL_RX_DESC_PLEN_MASK) >> IXL_RX_DESC_PLEN_SHIFT; 3170 m->m_len = len; 3171 m->m_pkthdr.len = 0; 3172 3173 m->m_next = NULL; 3174 *rxr->rxr_m_tail = m; 3175 rxr->rxr_m_tail = &m->m_next; 3176 3177 m = rxr->rxr_m_head; 3178 m->m_pkthdr.len += len; 3179 3180 if (ISSET(word, IXL_RX_DESC_EOP)) { 3181 if (!ISSET(word, 3182 IXL_RX_DESC_RXE | IXL_RX_DESC_OVERSIZE)) { 3183 ml_enqueue(&ml, m); 3184 } else { 3185 ifp->if_ierrors++; /* XXX */ 3186 m_freem(m); 3187 } 3188 3189 rxr->rxr_m_head = NULL; 3190 rxr->rxr_m_tail = &rxr->rxr_m_head; 3191 } 3192 3193 cons++; 3194 cons &= mask; 3195 3196 done = 1; 3197 } while (cons != prod); 3198 3199 if (done) { 3200 rxr->rxr_cons = cons; 3201 if (ifiq_input(ifiq, &ml)) 3202 if_rxr_livelocked(&rxr->rxr_acct); 3203 ixl_rxfill(sc, rxr); 3204 } 3205 3206 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 3207 0, IXL_DMA_LEN(&rxr->rxr_mem), 3208 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3209 3210 return (done); 3211 } 3212 3213 static void 3214 ixl_rxfill(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3215 { 3216 struct ixl_rx_rd_desc_16 *ring, *rxd; 3217 struct ixl_rx_map *rxm; 3218 bus_dmamap_t map; 3219 struct mbuf *m; 3220 unsigned int prod; 3221 unsigned int slots; 3222 unsigned int mask; 3223 int post = 0; 3224 3225 slots = if_rxr_get(&rxr->rxr_acct, sc->sc_rx_ring_ndescs); 3226 if (slots == 0) 3227 return; 3228 3229 prod = rxr->rxr_prod; 3230 3231 ring = IXL_DMA_KVA(&rxr->rxr_mem); 3232 mask = sc->sc_rx_ring_ndescs - 1; 3233 3234 do { 3235 rxm = &rxr->rxr_maps[prod]; 3236 3237 m = MCLGETL(NULL, M_DONTWAIT, MCLBYTES + ETHER_ALIGN); 3238 if (m == NULL) 3239 break; 3240 m->m_data += (m->m_ext.ext_size - (MCLBYTES + ETHER_ALIGN)); 3241 m->m_len = m->m_pkthdr.len = MCLBYTES + ETHER_ALIGN; 3242 3243 map = rxm->rxm_map; 3244 3245 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 3246 BUS_DMA_NOWAIT) != 0) { 3247 m_freem(m); 3248 break; 3249 } 3250 3251 rxm->rxm_m = m; 3252 3253 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3254 BUS_DMASYNC_PREREAD); 3255 3256 rxd = &ring[prod]; 3257 3258 htolem64(&rxd->paddr, map->dm_segs[0].ds_addr); 3259 rxd->haddr = htole64(0); 3260 3261 prod++; 3262 prod &= mask; 3263 3264 post = 1; 3265 } while (--slots); 3266 3267 if_rxr_put(&rxr->rxr_acct, slots); 3268 3269 if (if_rxr_inuse(&rxr->rxr_acct) == 0) 3270 timeout_add(&rxr->rxr_refill, 1); 3271 else if (post) { 3272 rxr->rxr_prod = prod; 3273 ixl_wr(sc, rxr->rxr_tail, prod); 3274 } 3275 } 3276 3277 void 3278 ixl_rxrefill(void *arg) 3279 { 3280 struct ixl_rx_ring *rxr = arg; 3281 struct ixl_softc *sc = rxr->rxr_sc; 3282 3283 ixl_rxfill(sc, rxr); 3284 } 3285 3286 static int 3287 ixl_rxrinfo(struct ixl_softc *sc, struct if_rxrinfo *ifri) 3288 { 3289 struct ifnet *ifp = &sc->sc_ac.ac_if; 3290 struct if_rxring_info *ifr; 3291 struct ixl_rx_ring *ring; 3292 int i, rv; 3293 3294 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 3295 return (ENOTTY); 3296 3297 ifr = mallocarray(sizeof(*ifr), ixl_nqueues(sc), M_TEMP, 3298 M_WAITOK|M_CANFAIL|M_ZERO); 3299 if (ifr == NULL) 3300 return (ENOMEM); 3301 3302 for (i = 0; i < ixl_nqueues(sc); i++) { 3303 ring = ifp->if_iqs[i]->ifiq_softc; 3304 ifr[i].ifr_size = MCLBYTES; 3305 snprintf(ifr[i].ifr_name, sizeof(ifr[i].ifr_name), "%d", i); 3306 ifr[i].ifr_info = ring->rxr_acct; 3307 } 3308 3309 rv = if_rxr_info_ioctl(ifri, ixl_nqueues(sc), ifr); 3310 free(ifr, M_TEMP, ixl_nqueues(sc) * sizeof(*ifr)); 3311 3312 return (rv); 3313 } 3314 3315 static int 3316 ixl_intr0(void *xsc) 3317 { 3318 struct ixl_softc *sc = xsc; 3319 struct ifnet *ifp = &sc->sc_ac.ac_if; 3320 uint32_t icr; 3321 int rv = 0; 3322 3323 ixl_intr_enable(sc); 3324 icr = ixl_rd(sc, I40E_PFINT_ICR0); 3325 3326 if (ISSET(icr, I40E_PFINT_ICR0_ADMINQ_MASK)) { 3327 ixl_atq_done(sc); 3328 task_add(systq, &sc->sc_arq_task); 3329 rv = 1; 3330 } 3331 3332 if (ISSET(icr, I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK)) { 3333 task_add(systq, &sc->sc_link_state_task); 3334 rv = 1; 3335 } 3336 3337 if (ISSET(ifp->if_flags, IFF_RUNNING)) { 3338 struct ixl_vector *iv = sc->sc_vectors; 3339 if (ISSET(icr, I40E_INTR_NOTX_RX_MASK)) 3340 rv |= ixl_rxeof(sc, iv->iv_rxr); 3341 if (ISSET(icr, I40E_INTR_NOTX_TX_MASK)) 3342 rv |= ixl_txeof(sc, iv->iv_txr); 3343 } 3344 3345 return (rv); 3346 } 3347 3348 static int 3349 ixl_intr_vector(void *v) 3350 { 3351 struct ixl_vector *iv = v; 3352 struct ixl_softc *sc = iv->iv_sc; 3353 struct ifnet *ifp = &sc->sc_ac.ac_if; 3354 int rv = 0; 3355 3356 if (ISSET(ifp->if_flags, IFF_RUNNING)) { 3357 rv |= ixl_rxeof(sc, iv->iv_rxr); 3358 rv |= ixl_txeof(sc, iv->iv_txr); 3359 } 3360 3361 ixl_wr(sc, I40E_PFINT_DYN_CTLN(iv->iv_qid), 3362 I40E_PFINT_DYN_CTLN_INTENA_MASK | 3363 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 3364 (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)); 3365 3366 return (rv); 3367 } 3368 3369 static void 3370 ixl_link_state_update_iaq(struct ixl_softc *sc, void *arg) 3371 { 3372 struct ifnet *ifp = &sc->sc_ac.ac_if; 3373 struct ixl_aq_desc *iaq = arg; 3374 uint16_t retval; 3375 int link_state; 3376 int change = 0; 3377 3378 retval = lemtoh16(&iaq->iaq_retval); 3379 if (retval != IXL_AQ_RC_OK) { 3380 printf("%s: LINK STATUS error %u\n", DEVNAME(sc), retval); 3381 return; 3382 } 3383 3384 link_state = ixl_set_link_status(sc, iaq); 3385 mtx_enter(&sc->sc_link_state_mtx); 3386 if (ifp->if_link_state != link_state) { 3387 ifp->if_link_state = link_state; 3388 change = 1; 3389 } 3390 mtx_leave(&sc->sc_link_state_mtx); 3391 3392 if (change) 3393 if_link_state_change(ifp); 3394 } 3395 3396 static void 3397 ixl_link_state_update(void *xsc) 3398 { 3399 struct ixl_softc *sc = xsc; 3400 struct ixl_aq_desc *iaq; 3401 struct ixl_aq_link_param *param; 3402 3403 memset(&sc->sc_link_state_atq, 0, sizeof(sc->sc_link_state_atq)); 3404 iaq = &sc->sc_link_state_atq.iatq_desc; 3405 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS); 3406 param = (struct ixl_aq_link_param *)iaq->iaq_param; 3407 param->notify = IXL_AQ_LINK_NOTIFY; 3408 3409 ixl_atq_set(&sc->sc_link_state_atq, ixl_link_state_update_iaq, iaq); 3410 ixl_atq_post(sc, &sc->sc_link_state_atq); 3411 } 3412 3413 #if 0 3414 static void 3415 ixl_aq_dump(const struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 3416 { 3417 printf("%s: flags %b opcode %04x\n", DEVNAME(sc), 3418 lemtoh16(&iaq->iaq_flags), IXL_AQ_FLAGS_FMT, 3419 lemtoh16(&iaq->iaq_opcode)); 3420 printf("%s: datalen %u retval %u\n", DEVNAME(sc), 3421 lemtoh16(&iaq->iaq_datalen), lemtoh16(&iaq->iaq_retval)); 3422 printf("%s: cookie %016llx\n", DEVNAME(sc), iaq->iaq_cookie); 3423 printf("%s: %08x %08x %08x %08x\n", DEVNAME(sc), 3424 lemtoh32(&iaq->iaq_param[0]), lemtoh32(&iaq->iaq_param[1]), 3425 lemtoh32(&iaq->iaq_param[2]), lemtoh32(&iaq->iaq_param[3])); 3426 } 3427 #endif 3428 3429 static void 3430 ixl_arq(void *xsc) 3431 { 3432 struct ixl_softc *sc = xsc; 3433 struct ixl_aq_desc *arq, *iaq; 3434 struct ixl_aq_buf *aqb; 3435 unsigned int cons = sc->sc_arq_cons; 3436 unsigned int prod; 3437 int done = 0; 3438 3439 prod = ixl_rd(sc, sc->sc_aq_regs->arq_head) & 3440 sc->sc_aq_regs->arq_head_mask; 3441 3442 if (cons == prod) 3443 goto done; 3444 3445 arq = IXL_DMA_KVA(&sc->sc_arq); 3446 3447 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3448 0, IXL_DMA_LEN(&sc->sc_arq), 3449 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3450 3451 do { 3452 iaq = &arq[cons]; 3453 3454 aqb = SIMPLEQ_FIRST(&sc->sc_arq_live); 3455 SIMPLEQ_REMOVE_HEAD(&sc->sc_arq_live, aqb_entry); 3456 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IXL_AQ_BUFLEN, 3457 BUS_DMASYNC_POSTREAD); 3458 3459 switch (iaq->iaq_opcode) { 3460 case HTOLE16(IXL_AQ_OP_PHY_LINK_STATUS): 3461 ixl_link_state_update_iaq(sc, iaq); 3462 break; 3463 } 3464 3465 memset(iaq, 0, sizeof(*iaq)); 3466 SIMPLEQ_INSERT_TAIL(&sc->sc_arq_idle, aqb, aqb_entry); 3467 if_rxr_put(&sc->sc_arq_ring, 1); 3468 3469 cons++; 3470 cons &= IXL_AQ_MASK; 3471 3472 done = 1; 3473 } while (cons != prod); 3474 3475 if (done && ixl_arq_fill(sc)) 3476 ixl_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 3477 3478 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3479 0, IXL_DMA_LEN(&sc->sc_arq), 3480 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3481 3482 sc->sc_arq_cons = cons; 3483 3484 done: 3485 ixl_intr_enable(sc); 3486 } 3487 3488 static void 3489 ixl_atq_set(struct ixl_atq *iatq, 3490 void (*fn)(struct ixl_softc *, void *), void *arg) 3491 { 3492 iatq->iatq_fn = fn; 3493 iatq->iatq_arg = arg; 3494 } 3495 3496 static void 3497 ixl_atq_post(struct ixl_softc *sc, struct ixl_atq *iatq) 3498 { 3499 struct ixl_aq_desc *atq, *slot; 3500 unsigned int prod; 3501 3502 /* assert locked */ 3503 3504 atq = IXL_DMA_KVA(&sc->sc_atq); 3505 prod = sc->sc_atq_prod; 3506 slot = atq + prod; 3507 3508 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3509 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 3510 3511 *slot = iatq->iatq_desc; 3512 slot->iaq_cookie = (uint64_t)iatq; 3513 3514 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3515 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 3516 3517 prod++; 3518 prod &= IXL_AQ_MASK; 3519 sc->sc_atq_prod = prod; 3520 ixl_wr(sc, sc->sc_aq_regs->atq_tail, prod); 3521 } 3522 3523 static void 3524 ixl_atq_done(struct ixl_softc *sc) 3525 { 3526 struct ixl_aq_desc *atq, *slot; 3527 struct ixl_atq *iatq; 3528 unsigned int cons; 3529 unsigned int prod; 3530 3531 prod = sc->sc_atq_prod; 3532 cons = sc->sc_atq_cons; 3533 3534 if (prod == cons) 3535 return; 3536 3537 atq = IXL_DMA_KVA(&sc->sc_atq); 3538 3539 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3540 0, IXL_DMA_LEN(&sc->sc_atq), 3541 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3542 3543 do { 3544 slot = &atq[cons]; 3545 if (!ISSET(slot->iaq_flags, htole16(IXL_AQ_DD))) 3546 break; 3547 3548 iatq = (struct ixl_atq *)slot->iaq_cookie; 3549 iatq->iatq_desc = *slot; 3550 3551 memset(slot, 0, sizeof(*slot)); 3552 3553 (*iatq->iatq_fn)(sc, iatq->iatq_arg); 3554 3555 cons++; 3556 cons &= IXL_AQ_MASK; 3557 } while (cons != prod); 3558 3559 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3560 0, IXL_DMA_LEN(&sc->sc_atq), 3561 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3562 3563 sc->sc_atq_cons = cons; 3564 } 3565 3566 static void 3567 ixl_wakeup(struct ixl_softc *sc, void *arg) 3568 { 3569 struct cond *c = arg; 3570 3571 cond_signal(c); 3572 } 3573 3574 static void 3575 ixl_atq_exec(struct ixl_softc *sc, struct ixl_atq *iatq, const char *wmesg) 3576 { 3577 struct cond c = COND_INITIALIZER(); 3578 3579 KASSERT(iatq->iatq_desc.iaq_cookie == 0); 3580 3581 ixl_atq_set(iatq, ixl_wakeup, &c); 3582 ixl_atq_post(sc, iatq); 3583 3584 cond_wait(&c, wmesg); 3585 } 3586 3587 static int 3588 ixl_atq_poll(struct ixl_softc *sc, struct ixl_aq_desc *iaq, unsigned int tm) 3589 { 3590 struct ixl_aq_desc *atq, *slot; 3591 unsigned int prod; 3592 unsigned int t = 0; 3593 3594 atq = IXL_DMA_KVA(&sc->sc_atq); 3595 prod = sc->sc_atq_prod; 3596 slot = atq + prod; 3597 3598 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3599 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 3600 3601 *slot = *iaq; 3602 slot->iaq_flags |= htole16(IXL_AQ_SI); 3603 3604 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3605 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 3606 3607 prod++; 3608 prod &= IXL_AQ_MASK; 3609 sc->sc_atq_prod = prod; 3610 ixl_wr(sc, sc->sc_aq_regs->atq_tail, prod); 3611 3612 while (ixl_rd(sc, sc->sc_aq_regs->atq_head) != prod) { 3613 delaymsec(1); 3614 3615 if (t++ > tm) 3616 return (ETIMEDOUT); 3617 } 3618 3619 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3620 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTREAD); 3621 *iaq = *slot; 3622 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3623 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREREAD); 3624 3625 sc->sc_atq_cons = prod; 3626 3627 return (0); 3628 } 3629 3630 static int 3631 ixl_get_version(struct ixl_softc *sc) 3632 { 3633 struct ixl_aq_desc iaq; 3634 uint32_t fwbuild, fwver, apiver; 3635 3636 memset(&iaq, 0, sizeof(iaq)); 3637 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VERSION); 3638 3639 if (ixl_atq_poll(sc, &iaq, 2000) != 0) 3640 return (ETIMEDOUT); 3641 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) 3642 return (EIO); 3643 3644 fwbuild = lemtoh32(&iaq.iaq_param[1]); 3645 fwver = lemtoh32(&iaq.iaq_param[2]); 3646 apiver = lemtoh32(&iaq.iaq_param[3]); 3647 3648 sc->sc_api_major = apiver & 0xffff; 3649 sc->sc_api_minor = (apiver >> 16) & 0xffff; 3650 3651 printf(", FW %hu.%hu.%05u API %hu.%hu", (uint16_t)fwver, 3652 (uint16_t)(fwver >> 16), fwbuild, 3653 sc->sc_api_major, sc->sc_api_minor); 3654 3655 return (0); 3656 } 3657 3658 static int 3659 ixl_pxe_clear(struct ixl_softc *sc) 3660 { 3661 struct ixl_aq_desc iaq; 3662 3663 memset(&iaq, 0, sizeof(iaq)); 3664 iaq.iaq_opcode = htole16(IXL_AQ_OP_CLEAR_PXE_MODE); 3665 iaq.iaq_param[0] = htole32(0x2); 3666 3667 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 3668 printf(", CLEAR PXE MODE timeout\n"); 3669 return (-1); 3670 } 3671 3672 switch (iaq.iaq_retval) { 3673 case HTOLE16(IXL_AQ_RC_OK): 3674 case HTOLE16(IXL_AQ_RC_EEXIST): 3675 break; 3676 default: 3677 printf(", CLEAR PXE MODE error\n"); 3678 return (-1); 3679 } 3680 3681 return (0); 3682 } 3683 3684 static int 3685 ixl_lldp_shut(struct ixl_softc *sc) 3686 { 3687 struct ixl_aq_desc iaq; 3688 3689 memset(&iaq, 0, sizeof(iaq)); 3690 iaq.iaq_opcode = htole16(IXL_AQ_OP_LLDP_STOP_AGENT); 3691 iaq.iaq_param[0] = htole32(IXL_LLDP_SHUTDOWN); 3692 3693 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 3694 printf(", STOP LLDP AGENT timeout\n"); 3695 return (-1); 3696 } 3697 3698 switch (iaq.iaq_retval) { 3699 case HTOLE16(IXL_AQ_RC_EMODE): 3700 case HTOLE16(IXL_AQ_RC_EPERM): 3701 /* ignore silently */ 3702 default: 3703 break; 3704 } 3705 3706 return (0); 3707 } 3708 3709 static int 3710 ixl_get_mac(struct ixl_softc *sc) 3711 { 3712 struct ixl_dmamem idm; 3713 struct ixl_aq_desc iaq; 3714 struct ixl_aq_mac_addresses *addrs; 3715 int rv; 3716 3717 #ifdef __sparc64__ 3718 if (OF_getprop(PCITAG_NODE(sc->sc_tag), "local-mac-address", 3719 sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN) == ETHER_ADDR_LEN) 3720 return (0); 3721 #endif 3722 3723 if (ixl_dmamem_alloc(sc, &idm, sizeof(*addrs), 0) != 0) { 3724 printf(", unable to allocate mac addresses\n"); 3725 return (-1); 3726 } 3727 3728 memset(&iaq, 0, sizeof(iaq)); 3729 iaq.iaq_flags = htole16(IXL_AQ_BUF); 3730 iaq.iaq_opcode = htole16(IXL_AQ_OP_MAC_ADDRESS_READ); 3731 iaq.iaq_datalen = htole16(sizeof(*addrs)); 3732 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 3733 3734 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3735 BUS_DMASYNC_PREREAD); 3736 3737 rv = ixl_atq_poll(sc, &iaq, 250); 3738 3739 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3740 BUS_DMASYNC_POSTREAD); 3741 3742 if (rv != 0) { 3743 printf(", MAC ADDRESS READ timeout\n"); 3744 rv = -1; 3745 goto done; 3746 } 3747 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 3748 printf(", MAC ADDRESS READ error\n"); 3749 rv = -1; 3750 goto done; 3751 } 3752 3753 addrs = IXL_DMA_KVA(&idm); 3754 if (!ISSET(iaq.iaq_param[0], htole32(IXL_AQ_MAC_PORT_VALID))) { 3755 printf(", port address is not valid\n"); 3756 goto done; 3757 } 3758 3759 memcpy(sc->sc_ac.ac_enaddr, addrs->port, ETHER_ADDR_LEN); 3760 rv = 0; 3761 3762 done: 3763 ixl_dmamem_free(sc, &idm); 3764 return (rv); 3765 } 3766 3767 static int 3768 ixl_get_switch_config(struct ixl_softc *sc) 3769 { 3770 struct ixl_dmamem idm; 3771 struct ixl_aq_desc iaq; 3772 struct ixl_aq_switch_config *hdr; 3773 struct ixl_aq_switch_config_element *elms, *elm; 3774 unsigned int nelm; 3775 int rv; 3776 3777 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) { 3778 printf("%s: unable to allocate switch config buffer\n", 3779 DEVNAME(sc)); 3780 return (-1); 3781 } 3782 3783 memset(&iaq, 0, sizeof(iaq)); 3784 iaq.iaq_flags = htole16(IXL_AQ_BUF | 3785 (IXL_AQ_BUFLEN > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 3786 iaq.iaq_opcode = htole16(IXL_AQ_OP_SWITCH_GET_CONFIG); 3787 iaq.iaq_datalen = htole16(IXL_AQ_BUFLEN); 3788 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 3789 3790 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3791 BUS_DMASYNC_PREREAD); 3792 3793 rv = ixl_atq_poll(sc, &iaq, 250); 3794 3795 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3796 BUS_DMASYNC_POSTREAD); 3797 3798 if (rv != 0) { 3799 printf("%s: GET SWITCH CONFIG timeout\n", DEVNAME(sc)); 3800 rv = -1; 3801 goto done; 3802 } 3803 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 3804 printf("%s: GET SWITCH CONFIG error\n", DEVNAME(sc)); 3805 rv = -1; 3806 goto done; 3807 } 3808 3809 hdr = IXL_DMA_KVA(&idm); 3810 elms = (struct ixl_aq_switch_config_element *)(hdr + 1); 3811 3812 nelm = lemtoh16(&hdr->num_reported); 3813 if (nelm < 1) { 3814 printf("%s: no switch config available\n", DEVNAME(sc)); 3815 rv = -1; 3816 goto done; 3817 } 3818 3819 #if 0 3820 for (i = 0; i < nelm; i++) { 3821 elm = &elms[i]; 3822 3823 printf("%s: type %x revision %u seid %04x\n", DEVNAME(sc), 3824 elm->type, elm->revision, lemtoh16(&elm->seid)); 3825 printf("%s: uplink %04x downlink %04x\n", DEVNAME(sc), 3826 lemtoh16(&elm->uplink_seid), 3827 lemtoh16(&elm->downlink_seid)); 3828 printf("%s: conntype %x scheduler %04x extra %04x\n", 3829 DEVNAME(sc), elm->connection_type, 3830 lemtoh16(&elm->scheduler_id), 3831 lemtoh16(&elm->element_info)); 3832 } 3833 #endif 3834 3835 elm = &elms[0]; 3836 3837 sc->sc_uplink_seid = elm->uplink_seid; 3838 sc->sc_downlink_seid = elm->downlink_seid; 3839 sc->sc_seid = elm->seid; 3840 3841 if ((sc->sc_uplink_seid == htole16(0)) != 3842 (sc->sc_downlink_seid == htole16(0))) { 3843 printf("%s: SEIDs are misconfigured\n", DEVNAME(sc)); 3844 rv = -1; 3845 goto done; 3846 } 3847 3848 done: 3849 ixl_dmamem_free(sc, &idm); 3850 return (rv); 3851 } 3852 3853 static int 3854 ixl_phy_mask_ints(struct ixl_softc *sc) 3855 { 3856 struct ixl_aq_desc iaq; 3857 3858 memset(&iaq, 0, sizeof(iaq)); 3859 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_EVENT_MASK); 3860 iaq.iaq_param[2] = htole32(IXL_AQ_PHY_EV_MASK & 3861 ~(IXL_AQ_PHY_EV_LINK_UPDOWN | IXL_AQ_PHY_EV_MODULE_QUAL_FAIL | 3862 IXL_AQ_PHY_EV_MEDIA_NA)); 3863 3864 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 3865 printf("%s: SET PHY EVENT MASK timeout\n", DEVNAME(sc)); 3866 return (-1); 3867 } 3868 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 3869 printf("%s: SET PHY EVENT MASK error\n", DEVNAME(sc)); 3870 return (-1); 3871 } 3872 3873 return (0); 3874 } 3875 3876 static int 3877 ixl_get_phy_abilities(struct ixl_softc *sc,struct ixl_dmamem *idm) 3878 { 3879 struct ixl_aq_desc iaq; 3880 int rv; 3881 3882 memset(&iaq, 0, sizeof(iaq)); 3883 iaq.iaq_flags = htole16(IXL_AQ_BUF | 3884 (IXL_DMA_LEN(idm) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 3885 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_GET_ABILITIES); 3886 htolem16(&iaq.iaq_datalen, IXL_DMA_LEN(idm)); 3887 iaq.iaq_param[0] = htole32(IXL_AQ_PHY_REPORT_INIT); 3888 ixl_aq_dva(&iaq, IXL_DMA_DVA(idm)); 3889 3890 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 3891 BUS_DMASYNC_PREREAD); 3892 3893 rv = ixl_atq_poll(sc, &iaq, 250); 3894 3895 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 3896 BUS_DMASYNC_POSTREAD); 3897 3898 if (rv != 0) 3899 return (-1); 3900 3901 return (lemtoh16(&iaq.iaq_retval)); 3902 } 3903 3904 static int 3905 ixl_get_phy_types(struct ixl_softc *sc, uint64_t *phy_types_ptr) 3906 { 3907 struct ixl_dmamem idm; 3908 struct ixl_aq_phy_abilities *phy; 3909 uint64_t phy_types; 3910 int rv; 3911 3912 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) { 3913 printf("%s: unable to allocate phy abilities buffer\n", 3914 DEVNAME(sc)); 3915 return (-1); 3916 } 3917 3918 rv = ixl_get_phy_abilities(sc, &idm); 3919 switch (rv) { 3920 case -1: 3921 printf("%s: GET PHY ABILITIES timeout\n", DEVNAME(sc)); 3922 goto err; 3923 case IXL_AQ_RC_OK: 3924 break; 3925 case IXL_AQ_RC_EIO: 3926 /* API is too old to handle this command */ 3927 phy_types = 0; 3928 goto done; 3929 default: 3930 printf("%s: GET PHY ABILITIIES error %u\n", DEVNAME(sc), rv); 3931 goto err; 3932 } 3933 3934 phy = IXL_DMA_KVA(&idm); 3935 3936 phy_types = lemtoh32(&phy->phy_type); 3937 phy_types |= (uint64_t)phy->phy_type_ext << 32; 3938 3939 done: 3940 *phy_types_ptr = phy_types; 3941 3942 rv = 0; 3943 3944 err: 3945 ixl_dmamem_free(sc, &idm); 3946 return (rv); 3947 } 3948 3949 /* 3950 * this returns -2 on software/driver failure, -1 for problems 3951 * talking to the hardware, or the sff module type. 3952 */ 3953 3954 static int 3955 ixl_get_module_type(struct ixl_softc *sc) 3956 { 3957 struct ixl_dmamem idm; 3958 struct ixl_aq_phy_abilities *phy; 3959 int rv; 3960 3961 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) 3962 return (-2); 3963 3964 rv = ixl_get_phy_abilities(sc, &idm); 3965 if (rv != IXL_AQ_RC_OK) { 3966 rv = -1; 3967 goto done; 3968 } 3969 3970 phy = IXL_DMA_KVA(&idm); 3971 3972 rv = phy->module_type[0]; 3973 3974 done: 3975 ixl_dmamem_free(sc, &idm); 3976 return (rv); 3977 } 3978 3979 static int 3980 ixl_get_link_status(struct ixl_softc *sc) 3981 { 3982 struct ixl_aq_desc iaq; 3983 struct ixl_aq_link_param *param; 3984 3985 memset(&iaq, 0, sizeof(iaq)); 3986 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS); 3987 param = (struct ixl_aq_link_param *)iaq.iaq_param; 3988 param->notify = IXL_AQ_LINK_NOTIFY; 3989 3990 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 3991 printf("%s: GET LINK STATUS timeout\n", DEVNAME(sc)); 3992 return (-1); 3993 } 3994 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 3995 printf("%s: GET LINK STATUS error\n", DEVNAME(sc)); 3996 return (0); 3997 } 3998 3999 sc->sc_ac.ac_if.if_link_state = ixl_set_link_status(sc, &iaq); 4000 4001 return (0); 4002 } 4003 4004 struct ixl_sff_ops { 4005 int (*open)(struct ixl_softc *sc, struct if_sffpage *, uint8_t *); 4006 int (*get)(struct ixl_softc *sc, struct if_sffpage *, size_t); 4007 int (*close)(struct ixl_softc *sc, struct if_sffpage *, uint8_t); 4008 }; 4009 4010 static int 4011 ixl_sfp_open(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t *page) 4012 { 4013 int error; 4014 4015 if (sff->sff_addr != IFSFF_ADDR_EEPROM) 4016 return (0); 4017 4018 error = ixl_sff_get_byte(sc, IFSFF_ADDR_EEPROM, 127, page); 4019 if (error != 0) 4020 return (error); 4021 if (*page == sff->sff_page) 4022 return (0); 4023 error = ixl_sff_set_byte(sc, IFSFF_ADDR_EEPROM, 127, sff->sff_page); 4024 if (error != 0) 4025 return (error); 4026 4027 return (0); 4028 } 4029 4030 static int 4031 ixl_sfp_get(struct ixl_softc *sc, struct if_sffpage *sff, size_t i) 4032 { 4033 return (ixl_sff_get_byte(sc, sff->sff_addr, i, &sff->sff_data[i])); 4034 } 4035 4036 static int 4037 ixl_sfp_close(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t page) 4038 { 4039 int error; 4040 4041 if (sff->sff_addr != IFSFF_ADDR_EEPROM) 4042 return (0); 4043 4044 if (page == sff->sff_page) 4045 return (0); 4046 4047 error = ixl_sff_set_byte(sc, IFSFF_ADDR_EEPROM, 127, page); 4048 if (error != 0) 4049 return (error); 4050 4051 return (0); 4052 } 4053 4054 static const struct ixl_sff_ops ixl_sfp_ops = { 4055 ixl_sfp_open, 4056 ixl_sfp_get, 4057 ixl_sfp_close, 4058 }; 4059 4060 static int 4061 ixl_qsfp_open(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t *page) 4062 { 4063 if (sff->sff_addr != IFSFF_ADDR_EEPROM) 4064 return (EIO); 4065 4066 return (0); 4067 } 4068 4069 static int 4070 ixl_qsfp_get(struct ixl_softc *sc, struct if_sffpage *sff, size_t i) 4071 { 4072 return (ixl_sff_get_byte(sc, sff->sff_page, i, &sff->sff_data[i])); 4073 } 4074 4075 static int 4076 ixl_qsfp_close(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t page) 4077 { 4078 return (0); 4079 } 4080 4081 static const struct ixl_sff_ops ixl_qsfp_ops = { 4082 ixl_qsfp_open, 4083 ixl_qsfp_get, 4084 ixl_qsfp_close, 4085 }; 4086 4087 static int 4088 ixl_get_sffpage(struct ixl_softc *sc, struct if_sffpage *sff) 4089 { 4090 const struct ixl_sff_ops *ops; 4091 uint8_t page; 4092 size_t i; 4093 int error; 4094 4095 switch (ixl_get_module_type(sc)) { 4096 case -2: 4097 return (ENOMEM); 4098 case -1: 4099 return (ENXIO); 4100 case IXL_SFF8024_ID_SFP: 4101 ops = &ixl_sfp_ops; 4102 break; 4103 case IXL_SFF8024_ID_QSFP: 4104 case IXL_SFF8024_ID_QSFP_PLUS: 4105 case IXL_SFF8024_ID_QSFP28: 4106 ops = &ixl_qsfp_ops; 4107 break; 4108 default: 4109 return (EOPNOTSUPP); 4110 } 4111 4112 error = (*ops->open)(sc, sff, &page); 4113 if (error != 0) 4114 return (error); 4115 4116 for (i = 0; i < sizeof(sff->sff_data); i++) { 4117 error = (*ops->get)(sc, sff, i); 4118 if (error != 0) 4119 return (error); 4120 } 4121 4122 error = (*ops->close)(sc, sff, page); 4123 4124 return (0); 4125 } 4126 4127 static int 4128 ixl_sff_get_byte(struct ixl_softc *sc, uint8_t dev, uint32_t reg, uint8_t *p) 4129 { 4130 struct ixl_atq iatq; 4131 struct ixl_aq_desc *iaq; 4132 struct ixl_aq_phy_reg_access *param; 4133 4134 memset(&iatq, 0, sizeof(iatq)); 4135 iaq = &iatq.iatq_desc; 4136 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_GET_REGISTER); 4137 param = (struct ixl_aq_phy_reg_access *)iaq->iaq_param; 4138 param->phy_iface = IXL_AQ_PHY_IF_MODULE; 4139 param->dev_addr = dev; 4140 htolem32(¶m->reg, reg); 4141 4142 ixl_atq_exec(sc, &iatq, "ixlsffget"); 4143 4144 if (ISSET(sc->sc_ac.ac_if.if_flags, IFF_DEBUG)) { 4145 printf("%s: %s(dev 0x%02x, reg 0x%02x) -> %04x\n", 4146 DEVNAME(sc), __func__, 4147 dev, reg, lemtoh16(&iaq->iaq_retval)); 4148 } 4149 4150 switch (iaq->iaq_retval) { 4151 case htole16(IXL_AQ_RC_OK): 4152 break; 4153 case htole16(IXL_AQ_RC_EBUSY): 4154 return (EBUSY); 4155 case htole16(IXL_AQ_RC_ESRCH): 4156 return (ENODEV); 4157 case htole16(IXL_AQ_RC_EIO): 4158 case htole16(IXL_AQ_RC_EINVAL): 4159 default: 4160 return (EIO); 4161 } 4162 4163 *p = lemtoh32(¶m->val); 4164 4165 return (0); 4166 } 4167 4168 static int 4169 ixl_sff_set_byte(struct ixl_softc *sc, uint8_t dev, uint32_t reg, uint8_t v) 4170 { 4171 struct ixl_atq iatq; 4172 struct ixl_aq_desc *iaq; 4173 struct ixl_aq_phy_reg_access *param; 4174 4175 memset(&iatq, 0, sizeof(iatq)); 4176 iaq = &iatq.iatq_desc; 4177 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_REGISTER); 4178 param = (struct ixl_aq_phy_reg_access *)iaq->iaq_param; 4179 param->phy_iface = IXL_AQ_PHY_IF_MODULE; 4180 param->dev_addr = dev; 4181 htolem32(¶m->reg, reg); 4182 htolem32(¶m->val, v); 4183 4184 ixl_atq_exec(sc, &iatq, "ixlsffset"); 4185 4186 if (ISSET(sc->sc_ac.ac_if.if_flags, IFF_DEBUG)) { 4187 printf("%s: %s(dev 0x%02x, reg 0x%02x, val 0x%02x) -> %04x\n", 4188 DEVNAME(sc), __func__, 4189 dev, reg, v, lemtoh16(&iaq->iaq_retval)); 4190 } 4191 4192 switch (iaq->iaq_retval) { 4193 case htole16(IXL_AQ_RC_OK): 4194 break; 4195 case htole16(IXL_AQ_RC_EBUSY): 4196 return (EBUSY); 4197 case htole16(IXL_AQ_RC_ESRCH): 4198 return (ENODEV); 4199 case htole16(IXL_AQ_RC_EIO): 4200 case htole16(IXL_AQ_RC_EINVAL): 4201 default: 4202 return (EIO); 4203 } 4204 4205 return (0); 4206 } 4207 4208 static int 4209 ixl_get_vsi(struct ixl_softc *sc) 4210 { 4211 struct ixl_dmamem *vsi = &sc->sc_scratch; 4212 struct ixl_aq_desc iaq; 4213 struct ixl_aq_vsi_param *param; 4214 struct ixl_aq_vsi_reply *reply; 4215 int rv; 4216 4217 /* grumble, vsi info isn't "known" at compile time */ 4218 4219 memset(&iaq, 0, sizeof(iaq)); 4220 htolem16(&iaq.iaq_flags, IXL_AQ_BUF | 4221 (IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4222 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VSI_PARAMS); 4223 htolem16(&iaq.iaq_datalen, IXL_DMA_LEN(vsi)); 4224 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi)); 4225 4226 param = (struct ixl_aq_vsi_param *)iaq.iaq_param; 4227 param->uplink_seid = sc->sc_seid; 4228 4229 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4230 BUS_DMASYNC_PREREAD); 4231 4232 rv = ixl_atq_poll(sc, &iaq, 250); 4233 4234 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4235 BUS_DMASYNC_POSTREAD); 4236 4237 if (rv != 0) { 4238 printf("%s: GET VSI timeout\n", DEVNAME(sc)); 4239 return (-1); 4240 } 4241 4242 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4243 printf("%s: GET VSI error %u\n", DEVNAME(sc), 4244 lemtoh16(&iaq.iaq_retval)); 4245 return (-1); 4246 } 4247 4248 reply = (struct ixl_aq_vsi_reply *)iaq.iaq_param; 4249 sc->sc_vsi_number = reply->vsi_number; 4250 4251 return (0); 4252 } 4253 4254 static int 4255 ixl_set_vsi(struct ixl_softc *sc) 4256 { 4257 struct ixl_dmamem *vsi = &sc->sc_scratch; 4258 struct ixl_aq_desc iaq; 4259 struct ixl_aq_vsi_param *param; 4260 struct ixl_aq_vsi_data *data = IXL_DMA_KVA(vsi); 4261 int rv; 4262 4263 data->valid_sections = htole16(IXL_AQ_VSI_VALID_QUEUE_MAP | 4264 IXL_AQ_VSI_VALID_VLAN); 4265 4266 CLR(data->mapping_flags, htole16(IXL_AQ_VSI_QUE_MAP_MASK)); 4267 SET(data->mapping_flags, htole16(IXL_AQ_VSI_QUE_MAP_CONTIG)); 4268 data->queue_mapping[0] = htole16(0); 4269 data->tc_mapping[0] = htole16((0 << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) | 4270 (sc->sc_nqueues << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT)); 4271 4272 CLR(data->port_vlan_flags, 4273 htole16(IXL_AQ_VSI_PVLAN_MODE_MASK | IXL_AQ_VSI_PVLAN_EMOD_MASK)); 4274 SET(data->port_vlan_flags, 4275 htole16(IXL_AQ_VSI_PVLAN_MODE_ALL | IXL_AQ_VSI_PVLAN_EMOD_NOTHING)); 4276 4277 /* grumble, vsi info isn't "known" at compile time */ 4278 4279 memset(&iaq, 0, sizeof(iaq)); 4280 htolem16(&iaq.iaq_flags, IXL_AQ_BUF | IXL_AQ_RD | 4281 (IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4282 iaq.iaq_opcode = htole16(IXL_AQ_OP_UPD_VSI_PARAMS); 4283 htolem16(&iaq.iaq_datalen, IXL_DMA_LEN(vsi)); 4284 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi)); 4285 4286 param = (struct ixl_aq_vsi_param *)iaq.iaq_param; 4287 param->uplink_seid = sc->sc_seid; 4288 4289 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4290 BUS_DMASYNC_PREWRITE); 4291 4292 rv = ixl_atq_poll(sc, &iaq, 250); 4293 4294 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4295 BUS_DMASYNC_POSTWRITE); 4296 4297 if (rv != 0) { 4298 printf("%s: UPDATE VSI timeout\n", DEVNAME(sc)); 4299 return (-1); 4300 } 4301 4302 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4303 printf("%s: UPDATE VSI error %u\n", DEVNAME(sc), 4304 lemtoh16(&iaq.iaq_retval)); 4305 return (-1); 4306 } 4307 4308 return (0); 4309 } 4310 4311 static const struct ixl_phy_type * 4312 ixl_search_phy_type(uint8_t phy_type) 4313 { 4314 const struct ixl_phy_type *itype; 4315 uint64_t mask; 4316 unsigned int i; 4317 4318 if (phy_type >= 64) 4319 return (NULL); 4320 4321 mask = 1ULL << phy_type; 4322 4323 for (i = 0; i < nitems(ixl_phy_type_map); i++) { 4324 itype = &ixl_phy_type_map[i]; 4325 4326 if (ISSET(itype->phy_type, mask)) 4327 return (itype); 4328 } 4329 4330 return (NULL); 4331 } 4332 4333 static uint64_t 4334 ixl_search_link_speed(uint8_t link_speed) 4335 { 4336 const struct ixl_speed_type *type; 4337 unsigned int i; 4338 4339 for (i = 0; i < nitems(ixl_speed_type_map); i++) { 4340 type = &ixl_speed_type_map[i]; 4341 4342 if (ISSET(type->dev_speed, link_speed)) 4343 return (type->net_speed); 4344 } 4345 4346 return (0); 4347 } 4348 4349 static int 4350 ixl_set_link_status(struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 4351 { 4352 const struct ixl_aq_link_status *status; 4353 const struct ixl_phy_type *itype; 4354 4355 uint64_t ifm_active = IFM_ETHER; 4356 uint64_t ifm_status = IFM_AVALID; 4357 int link_state = LINK_STATE_DOWN; 4358 uint64_t baudrate = 0; 4359 4360 status = (const struct ixl_aq_link_status *)iaq->iaq_param; 4361 if (!ISSET(status->link_info, IXL_AQ_LINK_UP_FUNCTION)) 4362 goto done; 4363 4364 ifm_active |= IFM_FDX; 4365 ifm_status |= IFM_ACTIVE; 4366 link_state = LINK_STATE_FULL_DUPLEX; 4367 4368 itype = ixl_search_phy_type(status->phy_type); 4369 if (itype != NULL) 4370 ifm_active |= itype->ifm_type; 4371 4372 if (ISSET(status->an_info, IXL_AQ_LINK_PAUSE_TX)) 4373 ifm_active |= IFM_ETH_TXPAUSE; 4374 if (ISSET(status->an_info, IXL_AQ_LINK_PAUSE_RX)) 4375 ifm_active |= IFM_ETH_RXPAUSE; 4376 4377 baudrate = ixl_search_link_speed(status->link_speed); 4378 4379 done: 4380 /* NET_ASSERT_LOCKED() except during attach */ 4381 sc->sc_media_active = ifm_active; 4382 sc->sc_media_status = ifm_status; 4383 sc->sc_ac.ac_if.if_baudrate = baudrate; 4384 4385 return (link_state); 4386 } 4387 4388 static int 4389 ixl_restart_an(struct ixl_softc *sc) 4390 { 4391 struct ixl_aq_desc iaq; 4392 4393 memset(&iaq, 0, sizeof(iaq)); 4394 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_RESTART_AN); 4395 iaq.iaq_param[0] = 4396 htole32(IXL_AQ_PHY_RESTART_AN | IXL_AQ_PHY_LINK_ENABLE); 4397 4398 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4399 printf("%s: RESTART AN timeout\n", DEVNAME(sc)); 4400 return (-1); 4401 } 4402 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4403 printf("%s: RESTART AN error\n", DEVNAME(sc)); 4404 return (-1); 4405 } 4406 4407 return (0); 4408 } 4409 4410 static int 4411 ixl_add_macvlan(struct ixl_softc *sc, uint8_t *macaddr, uint16_t vlan, uint16_t flags) 4412 { 4413 struct ixl_aq_desc iaq; 4414 struct ixl_aq_add_macvlan *param; 4415 struct ixl_aq_add_macvlan_elem *elem; 4416 4417 memset(&iaq, 0, sizeof(iaq)); 4418 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4419 iaq.iaq_opcode = htole16(IXL_AQ_OP_ADD_MACVLAN); 4420 iaq.iaq_datalen = htole16(sizeof(*elem)); 4421 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch)); 4422 4423 param = (struct ixl_aq_add_macvlan *)&iaq.iaq_param; 4424 param->num_addrs = htole16(1); 4425 param->seid0 = htole16(0x8000) | sc->sc_seid; 4426 param->seid1 = 0; 4427 param->seid2 = 0; 4428 4429 elem = IXL_DMA_KVA(&sc->sc_scratch); 4430 memset(elem, 0, sizeof(*elem)); 4431 memcpy(elem->macaddr, macaddr, ETHER_ADDR_LEN); 4432 elem->flags = htole16(IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH | flags); 4433 elem->vlan = htole16(vlan); 4434 4435 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4436 printf("%s: ADD_MACVLAN timeout\n", DEVNAME(sc)); 4437 return (IXL_AQ_RC_EINVAL); 4438 } 4439 4440 return letoh16(iaq.iaq_retval); 4441 } 4442 4443 static int 4444 ixl_remove_macvlan(struct ixl_softc *sc, uint8_t *macaddr, uint16_t vlan, uint16_t flags) 4445 { 4446 struct ixl_aq_desc iaq; 4447 struct ixl_aq_remove_macvlan *param; 4448 struct ixl_aq_remove_macvlan_elem *elem; 4449 4450 memset(&iaq, 0, sizeof(iaq)); 4451 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4452 iaq.iaq_opcode = htole16(IXL_AQ_OP_REMOVE_MACVLAN); 4453 iaq.iaq_datalen = htole16(sizeof(*elem)); 4454 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch)); 4455 4456 param = (struct ixl_aq_remove_macvlan *)&iaq.iaq_param; 4457 param->num_addrs = htole16(1); 4458 param->seid0 = htole16(0x8000) | sc->sc_seid; 4459 param->seid1 = 0; 4460 param->seid2 = 0; 4461 4462 elem = IXL_DMA_KVA(&sc->sc_scratch); 4463 memset(elem, 0, sizeof(*elem)); 4464 memcpy(elem->macaddr, macaddr, ETHER_ADDR_LEN); 4465 elem->flags = htole16(IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH | flags); 4466 elem->vlan = htole16(vlan); 4467 4468 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4469 printf("%s: REMOVE_MACVLAN timeout\n", DEVNAME(sc)); 4470 return (IXL_AQ_RC_EINVAL); 4471 } 4472 4473 return letoh16(iaq.iaq_retval); 4474 } 4475 4476 static int 4477 ixl_hmc(struct ixl_softc *sc) 4478 { 4479 struct { 4480 uint32_t count; 4481 uint32_t minsize; 4482 bus_size_t maxcnt; 4483 bus_size_t setoff; 4484 bus_size_t setcnt; 4485 } regs[] = { 4486 { 4487 0, 4488 IXL_HMC_TXQ_MINSIZE, 4489 I40E_GLHMC_LANTXOBJSZ, 4490 I40E_GLHMC_LANTXBASE(sc->sc_pf_id), 4491 I40E_GLHMC_LANTXCNT(sc->sc_pf_id), 4492 }, 4493 { 4494 0, 4495 IXL_HMC_RXQ_MINSIZE, 4496 I40E_GLHMC_LANRXOBJSZ, 4497 I40E_GLHMC_LANRXBASE(sc->sc_pf_id), 4498 I40E_GLHMC_LANRXCNT(sc->sc_pf_id), 4499 }, 4500 { 4501 0, 4502 0, 4503 I40E_GLHMC_FCOEMAX, 4504 I40E_GLHMC_FCOEDDPBASE(sc->sc_pf_id), 4505 I40E_GLHMC_FCOEDDPCNT(sc->sc_pf_id), 4506 }, 4507 { 4508 0, 4509 0, 4510 I40E_GLHMC_FCOEFMAX, 4511 I40E_GLHMC_FCOEFBASE(sc->sc_pf_id), 4512 I40E_GLHMC_FCOEFCNT(sc->sc_pf_id), 4513 }, 4514 }; 4515 struct ixl_hmc_entry *e; 4516 uint64_t size, dva; 4517 uint8_t *kva; 4518 uint64_t *sdpage; 4519 unsigned int i; 4520 int npages, tables; 4521 4522 CTASSERT(nitems(regs) <= nitems(sc->sc_hmc_entries)); 4523 4524 regs[IXL_HMC_LAN_TX].count = regs[IXL_HMC_LAN_RX].count = 4525 ixl_rd(sc, I40E_GLHMC_LANQMAX); 4526 4527 size = 0; 4528 for (i = 0; i < nitems(regs); i++) { 4529 e = &sc->sc_hmc_entries[i]; 4530 4531 e->hmc_count = regs[i].count; 4532 e->hmc_size = 1U << ixl_rd(sc, regs[i].maxcnt); 4533 e->hmc_base = size; 4534 4535 if ((e->hmc_size * 8) < regs[i].minsize) { 4536 printf("%s: kernel hmc entry is too big\n", 4537 DEVNAME(sc)); 4538 return (-1); 4539 } 4540 4541 size += roundup(e->hmc_size * e->hmc_count, IXL_HMC_ROUNDUP); 4542 } 4543 size = roundup(size, IXL_HMC_PGSIZE); 4544 npages = size / IXL_HMC_PGSIZE; 4545 4546 tables = roundup(size, IXL_HMC_L2SZ) / IXL_HMC_L2SZ; 4547 4548 if (ixl_dmamem_alloc(sc, &sc->sc_hmc_pd, size, IXL_HMC_PGSIZE) != 0) { 4549 printf("%s: unable to allocate hmc pd memory\n", DEVNAME(sc)); 4550 return (-1); 4551 } 4552 4553 if (ixl_dmamem_alloc(sc, &sc->sc_hmc_sd, tables * IXL_HMC_PGSIZE, 4554 IXL_HMC_PGSIZE) != 0) { 4555 printf("%s: unable to allocate hmc sd memory\n", DEVNAME(sc)); 4556 ixl_dmamem_free(sc, &sc->sc_hmc_pd); 4557 return (-1); 4558 } 4559 4560 kva = IXL_DMA_KVA(&sc->sc_hmc_pd); 4561 memset(kva, 0, IXL_DMA_LEN(&sc->sc_hmc_pd)); 4562 4563 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 4564 0, IXL_DMA_LEN(&sc->sc_hmc_pd), 4565 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4566 4567 dva = IXL_DMA_DVA(&sc->sc_hmc_pd); 4568 sdpage = IXL_DMA_KVA(&sc->sc_hmc_sd); 4569 for (i = 0; i < npages; i++) { 4570 htolem64(sdpage++, dva | IXL_HMC_PDVALID); 4571 4572 dva += IXL_HMC_PGSIZE; 4573 } 4574 4575 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_sd), 4576 0, IXL_DMA_LEN(&sc->sc_hmc_sd), 4577 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4578 4579 dva = IXL_DMA_DVA(&sc->sc_hmc_sd); 4580 for (i = 0; i < tables; i++) { 4581 uint32_t count; 4582 4583 KASSERT(npages >= 0); 4584 4585 count = (npages > IXL_HMC_PGS) ? IXL_HMC_PGS : npages; 4586 4587 ixl_wr(sc, I40E_PFHMC_SDDATAHIGH, dva >> 32); 4588 ixl_wr(sc, I40E_PFHMC_SDDATALOW, dva | 4589 (count << I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | 4590 (1U << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT)); 4591 ixl_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 4592 ixl_wr(sc, I40E_PFHMC_SDCMD, 4593 (1U << I40E_PFHMC_SDCMD_PMSDWR_SHIFT) | i); 4594 4595 npages -= IXL_HMC_PGS; 4596 dva += IXL_HMC_PGSIZE; 4597 } 4598 4599 for (i = 0; i < nitems(regs); i++) { 4600 e = &sc->sc_hmc_entries[i]; 4601 4602 ixl_wr(sc, regs[i].setoff, e->hmc_base / IXL_HMC_ROUNDUP); 4603 ixl_wr(sc, regs[i].setcnt, e->hmc_count); 4604 } 4605 4606 return (0); 4607 } 4608 4609 static void 4610 ixl_hmc_free(struct ixl_softc *sc) 4611 { 4612 ixl_dmamem_free(sc, &sc->sc_hmc_sd); 4613 ixl_dmamem_free(sc, &sc->sc_hmc_pd); 4614 } 4615 4616 static void 4617 ixl_hmc_pack(void *d, const void *s, const struct ixl_hmc_pack *packing, 4618 unsigned int npacking) 4619 { 4620 uint8_t *dst = d; 4621 const uint8_t *src = s; 4622 unsigned int i; 4623 4624 for (i = 0; i < npacking; i++) { 4625 const struct ixl_hmc_pack *pack = &packing[i]; 4626 unsigned int offset = pack->lsb / 8; 4627 unsigned int align = pack->lsb % 8; 4628 const uint8_t *in = src + pack->offset; 4629 uint8_t *out = dst + offset; 4630 int width = pack->width; 4631 unsigned int inbits = 0; 4632 4633 if (align) { 4634 inbits = (*in++) << align; 4635 *out++ |= (inbits & 0xff); 4636 inbits >>= 8; 4637 4638 width -= 8 - align; 4639 } 4640 4641 while (width >= 8) { 4642 inbits |= (*in++) << align; 4643 *out++ = (inbits & 0xff); 4644 inbits >>= 8; 4645 4646 width -= 8; 4647 } 4648 4649 if (width > 0) { 4650 inbits |= (*in) << align; 4651 *out |= (inbits & ((1 << width) - 1)); 4652 } 4653 } 4654 } 4655 4656 static struct ixl_aq_buf * 4657 ixl_aqb_alloc(struct ixl_softc *sc) 4658 { 4659 struct ixl_aq_buf *aqb; 4660 4661 aqb = malloc(sizeof(*aqb), M_DEVBUF, M_WAITOK); 4662 if (aqb == NULL) 4663 return (NULL); 4664 4665 aqb->aqb_data = dma_alloc(IXL_AQ_BUFLEN, PR_WAITOK); 4666 if (aqb->aqb_data == NULL) 4667 goto free; 4668 4669 if (bus_dmamap_create(sc->sc_dmat, IXL_AQ_BUFLEN, 1, 4670 IXL_AQ_BUFLEN, 0, 4671 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 4672 &aqb->aqb_map) != 0) 4673 goto dma_free; 4674 4675 if (bus_dmamap_load(sc->sc_dmat, aqb->aqb_map, aqb->aqb_data, 4676 IXL_AQ_BUFLEN, NULL, BUS_DMA_WAITOK) != 0) 4677 goto destroy; 4678 4679 return (aqb); 4680 4681 destroy: 4682 bus_dmamap_destroy(sc->sc_dmat, aqb->aqb_map); 4683 dma_free: 4684 dma_free(aqb->aqb_data, IXL_AQ_BUFLEN); 4685 free: 4686 free(aqb, M_DEVBUF, sizeof(*aqb)); 4687 4688 return (NULL); 4689 } 4690 4691 static void 4692 ixl_aqb_free(struct ixl_softc *sc, struct ixl_aq_buf *aqb) 4693 { 4694 bus_dmamap_unload(sc->sc_dmat, aqb->aqb_map); 4695 bus_dmamap_destroy(sc->sc_dmat, aqb->aqb_map); 4696 dma_free(aqb->aqb_data, IXL_AQ_BUFLEN); 4697 free(aqb, M_DEVBUF, sizeof(*aqb)); 4698 } 4699 4700 static int 4701 ixl_arq_fill(struct ixl_softc *sc) 4702 { 4703 struct ixl_aq_buf *aqb; 4704 struct ixl_aq_desc *arq, *iaq; 4705 unsigned int prod = sc->sc_arq_prod; 4706 unsigned int n; 4707 int post = 0; 4708 4709 n = if_rxr_get(&sc->sc_arq_ring, IXL_AQ_NUM); 4710 arq = IXL_DMA_KVA(&sc->sc_arq); 4711 4712 while (n > 0) { 4713 aqb = SIMPLEQ_FIRST(&sc->sc_arq_idle); 4714 if (aqb != NULL) 4715 SIMPLEQ_REMOVE_HEAD(&sc->sc_arq_idle, aqb_entry); 4716 else if ((aqb = ixl_aqb_alloc(sc)) == NULL) 4717 break; 4718 4719 memset(aqb->aqb_data, 0, IXL_AQ_BUFLEN); 4720 4721 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IXL_AQ_BUFLEN, 4722 BUS_DMASYNC_PREREAD); 4723 4724 iaq = &arq[prod]; 4725 iaq->iaq_flags = htole16(IXL_AQ_BUF | 4726 (IXL_AQ_BUFLEN > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4727 iaq->iaq_opcode = 0; 4728 iaq->iaq_datalen = htole16(IXL_AQ_BUFLEN); 4729 iaq->iaq_retval = 0; 4730 iaq->iaq_cookie = 0; 4731 iaq->iaq_param[0] = 0; 4732 iaq->iaq_param[1] = 0; 4733 ixl_aq_dva(iaq, aqb->aqb_map->dm_segs[0].ds_addr); 4734 4735 SIMPLEQ_INSERT_TAIL(&sc->sc_arq_live, aqb, aqb_entry); 4736 4737 prod++; 4738 prod &= IXL_AQ_MASK; 4739 4740 post = 1; 4741 4742 n--; 4743 } 4744 4745 if_rxr_put(&sc->sc_arq_ring, n); 4746 sc->sc_arq_prod = prod; 4747 4748 return (post); 4749 } 4750 4751 static void 4752 ixl_arq_unfill(struct ixl_softc *sc) 4753 { 4754 struct ixl_aq_buf *aqb; 4755 4756 while ((aqb = SIMPLEQ_FIRST(&sc->sc_arq_live)) != NULL) { 4757 SIMPLEQ_REMOVE_HEAD(&sc->sc_arq_live, aqb_entry); 4758 4759 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IXL_AQ_BUFLEN, 4760 BUS_DMASYNC_POSTREAD); 4761 ixl_aqb_free(sc, aqb); 4762 } 4763 } 4764 4765 static void 4766 ixl_clear_hw(struct ixl_softc *sc) 4767 { 4768 uint32_t num_queues, base_queue; 4769 uint32_t num_pf_int; 4770 uint32_t num_vf_int; 4771 uint32_t num_vfs; 4772 uint32_t i, j; 4773 uint32_t val; 4774 4775 /* get number of interrupts, queues, and vfs */ 4776 val = ixl_rd(sc, I40E_GLPCI_CNF2); 4777 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 4778 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 4779 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 4780 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 4781 4782 val = ixl_rd(sc, I40E_PFLAN_QALLOC); 4783 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 4784 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 4785 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 4786 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 4787 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 4788 num_queues = (j - base_queue) + 1; 4789 else 4790 num_queues = 0; 4791 4792 val = ixl_rd(sc, I40E_PF_VT_PFALLOC); 4793 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 4794 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 4795 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 4796 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 4797 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 4798 num_vfs = (j - i) + 1; 4799 else 4800 num_vfs = 0; 4801 4802 /* stop all the interrupts */ 4803 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 0); 4804 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 4805 for (i = 0; i < num_pf_int - 2; i++) 4806 ixl_wr(sc, I40E_PFINT_DYN_CTLN(i), val); 4807 4808 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 4809 val = I40E_QUEUE_TYPE_EOL << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 4810 ixl_wr(sc, I40E_PFINT_LNKLST0, val); 4811 for (i = 0; i < num_pf_int - 2; i++) 4812 ixl_wr(sc, I40E_PFINT_LNKLSTN(i), val); 4813 val = I40E_QUEUE_TYPE_EOL << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 4814 for (i = 0; i < num_vfs; i++) 4815 ixl_wr(sc, I40E_VPINT_LNKLST0(i), val); 4816 for (i = 0; i < num_vf_int - 2; i++) 4817 ixl_wr(sc, I40E_VPINT_LNKLSTN(i), val); 4818 4819 /* warn the HW of the coming Tx disables */ 4820 for (i = 0; i < num_queues; i++) { 4821 uint32_t abs_queue_idx = base_queue + i; 4822 uint32_t reg_block = 0; 4823 4824 if (abs_queue_idx >= 128) { 4825 reg_block = abs_queue_idx / 128; 4826 abs_queue_idx %= 128; 4827 } 4828 4829 val = ixl_rd(sc, I40E_GLLAN_TXPRE_QDIS(reg_block)); 4830 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 4831 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 4832 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 4833 4834 ixl_wr(sc, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 4835 } 4836 delaymsec(400); 4837 4838 /* stop all the queues */ 4839 for (i = 0; i < num_queues; i++) { 4840 ixl_wr(sc, I40E_QINT_TQCTL(i), 0); 4841 ixl_wr(sc, I40E_QTX_ENA(i), 0); 4842 ixl_wr(sc, I40E_QINT_RQCTL(i), 0); 4843 ixl_wr(sc, I40E_QRX_ENA(i), 0); 4844 } 4845 4846 /* short wait for all queue disables to settle */ 4847 delaymsec(50); 4848 } 4849 4850 static int 4851 ixl_pf_reset(struct ixl_softc *sc) 4852 { 4853 uint32_t cnt = 0; 4854 uint32_t cnt1 = 0; 4855 uint32_t reg = 0; 4856 uint32_t grst_del; 4857 4858 /* 4859 * Poll for Global Reset steady state in case of recent GRST. 4860 * The grst delay value is in 100ms units, and we'll wait a 4861 * couple counts longer to be sure we don't just miss the end. 4862 */ 4863 grst_del = ixl_rd(sc, I40E_GLGEN_RSTCTL); 4864 grst_del &= I40E_GLGEN_RSTCTL_GRSTDEL_MASK; 4865 grst_del >>= I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 4866 grst_del += 10; 4867 4868 for (cnt = 0; cnt < grst_del; cnt++) { 4869 reg = ixl_rd(sc, I40E_GLGEN_RSTAT); 4870 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 4871 break; 4872 delaymsec(100); 4873 } 4874 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 4875 printf(", Global reset polling failed to complete\n"); 4876 return (-1); 4877 } 4878 4879 /* Now Wait for the FW to be ready */ 4880 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 4881 reg = ixl_rd(sc, I40E_GLNVM_ULD); 4882 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 4883 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 4884 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 4885 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) 4886 break; 4887 4888 delaymsec(10); 4889 } 4890 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 4891 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 4892 printf(", wait for FW Reset complete timed out " 4893 "(I40E_GLNVM_ULD = 0x%x)\n", reg); 4894 return (-1); 4895 } 4896 4897 /* 4898 * If there was a Global Reset in progress when we got here, 4899 * we don't need to do the PF Reset 4900 */ 4901 if (cnt == 0) { 4902 reg = ixl_rd(sc, I40E_PFGEN_CTRL); 4903 ixl_wr(sc, I40E_PFGEN_CTRL, reg | I40E_PFGEN_CTRL_PFSWR_MASK); 4904 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 4905 reg = ixl_rd(sc, I40E_PFGEN_CTRL); 4906 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 4907 break; 4908 delaymsec(1); 4909 } 4910 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 4911 printf(", PF reset polling failed to complete" 4912 "(I40E_PFGEN_CTRL= 0x%x)\n", reg); 4913 return (-1); 4914 } 4915 } 4916 4917 return (0); 4918 } 4919 4920 static uint32_t 4921 ixl_710_rd_ctl(struct ixl_softc *sc, uint32_t r) 4922 { 4923 struct ixl_atq iatq; 4924 struct ixl_aq_desc *iaq; 4925 uint16_t retval; 4926 4927 memset(&iatq, 0, sizeof(iatq)); 4928 iaq = &iatq.iatq_desc; 4929 iaq->iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_READ); 4930 htolem32(&iaq->iaq_param[1], r); 4931 4932 ixl_atq_exec(sc, &iatq, "ixl710rd"); 4933 4934 retval = lemtoh16(&iaq->iaq_retval); 4935 if (retval != IXL_AQ_RC_OK) { 4936 printf("%s: %s failed (%u)\n", DEVNAME(sc), __func__, retval); 4937 return (~0U); 4938 } 4939 4940 return (lemtoh32(&iaq->iaq_param[3])); 4941 } 4942 4943 static void 4944 ixl_710_wr_ctl(struct ixl_softc *sc, uint32_t r, uint32_t v) 4945 { 4946 struct ixl_atq iatq; 4947 struct ixl_aq_desc *iaq; 4948 uint16_t retval; 4949 4950 memset(&iatq, 0, sizeof(iatq)); 4951 iaq = &iatq.iatq_desc; 4952 iaq->iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_WRITE); 4953 htolem32(&iaq->iaq_param[1], r); 4954 htolem32(&iaq->iaq_param[3], v); 4955 4956 ixl_atq_exec(sc, &iatq, "ixl710wr"); 4957 4958 retval = lemtoh16(&iaq->iaq_retval); 4959 if (retval != IXL_AQ_RC_OK) { 4960 printf("%s: %s %08x=%08x failed (%u)\n", 4961 DEVNAME(sc), __func__, r, v, retval); 4962 } 4963 } 4964 4965 static int 4966 ixl_710_set_rss_key(struct ixl_softc *sc, const struct ixl_rss_key *rsskey) 4967 { 4968 unsigned int i; 4969 4970 for (i = 0; i < nitems(rsskey->key); i++) 4971 ixl_wr_ctl(sc, I40E_PFQF_HKEY(i), rsskey->key[i]); 4972 4973 return (0); 4974 } 4975 4976 static int 4977 ixl_710_set_rss_lut(struct ixl_softc *sc, const struct ixl_rss_lut_128 *lut) 4978 { 4979 unsigned int i; 4980 4981 for (i = 0; i < nitems(lut->entries); i++) 4982 ixl_wr(sc, I40E_PFQF_HLUT(i), lut->entries[i]); 4983 4984 return (0); 4985 } 4986 4987 static uint32_t 4988 ixl_722_rd_ctl(struct ixl_softc *sc, uint32_t r) 4989 { 4990 return (ixl_rd(sc, r)); 4991 } 4992 4993 static void 4994 ixl_722_wr_ctl(struct ixl_softc *sc, uint32_t r, uint32_t v) 4995 { 4996 ixl_wr(sc, r, v); 4997 } 4998 4999 static int 5000 ixl_722_set_rss_key(struct ixl_softc *sc, const struct ixl_rss_key *rsskey) 5001 { 5002 /* XXX */ 5003 5004 return (0); 5005 } 5006 5007 static int 5008 ixl_722_set_rss_lut(struct ixl_softc *sc, const struct ixl_rss_lut_128 *lut) 5009 { 5010 /* XXX */ 5011 5012 return (0); 5013 } 5014 5015 static int 5016 ixl_dmamem_alloc(struct ixl_softc *sc, struct ixl_dmamem *ixm, 5017 bus_size_t size, u_int align) 5018 { 5019 ixm->ixm_size = size; 5020 5021 if (bus_dmamap_create(sc->sc_dmat, ixm->ixm_size, 1, 5022 ixm->ixm_size, 0, 5023 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 5024 &ixm->ixm_map) != 0) 5025 return (1); 5026 if (bus_dmamem_alloc(sc->sc_dmat, ixm->ixm_size, 5027 align, 0, &ixm->ixm_seg, 1, &ixm->ixm_nsegs, 5028 BUS_DMA_WAITOK | BUS_DMA_ZERO) != 0) 5029 goto destroy; 5030 if (bus_dmamem_map(sc->sc_dmat, &ixm->ixm_seg, ixm->ixm_nsegs, 5031 ixm->ixm_size, &ixm->ixm_kva, BUS_DMA_WAITOK) != 0) 5032 goto free; 5033 if (bus_dmamap_load(sc->sc_dmat, ixm->ixm_map, ixm->ixm_kva, 5034 ixm->ixm_size, NULL, BUS_DMA_WAITOK) != 0) 5035 goto unmap; 5036 5037 return (0); 5038 unmap: 5039 bus_dmamem_unmap(sc->sc_dmat, ixm->ixm_kva, ixm->ixm_size); 5040 free: 5041 bus_dmamem_free(sc->sc_dmat, &ixm->ixm_seg, 1); 5042 destroy: 5043 bus_dmamap_destroy(sc->sc_dmat, ixm->ixm_map); 5044 return (1); 5045 } 5046 5047 static void 5048 ixl_dmamem_free(struct ixl_softc *sc, struct ixl_dmamem *ixm) 5049 { 5050 bus_dmamap_unload(sc->sc_dmat, ixm->ixm_map); 5051 bus_dmamem_unmap(sc->sc_dmat, ixm->ixm_kva, ixm->ixm_size); 5052 bus_dmamem_free(sc->sc_dmat, &ixm->ixm_seg, 1); 5053 bus_dmamap_destroy(sc->sc_dmat, ixm->ixm_map); 5054 } 5055 5056 #if NKSTAT > 0 5057 5058 CTASSERT(KSTAT_KV_U_NONE <= 0xffU); 5059 CTASSERT(KSTAT_KV_U_PACKETS <= 0xffU); 5060 CTASSERT(KSTAT_KV_U_BYTES <= 0xffU); 5061 5062 struct ixl_counter { 5063 const char *c_name; 5064 uint32_t c_base; 5065 uint8_t c_width; 5066 uint8_t c_type; 5067 }; 5068 5069 const struct ixl_counter ixl_port_counters[] = { 5070 /* GORC */ 5071 { "rx bytes", 0x00300000, 48, KSTAT_KV_U_BYTES }, 5072 /* MLFC */ 5073 { "mac local errs", 0x00300020, 32, KSTAT_KV_U_NONE }, 5074 /* MRFC */ 5075 { "mac remote errs", 0x00300040, 32, KSTAT_KV_U_NONE }, 5076 /* MSPDC */ 5077 { "mac short", 0x00300060, 32, KSTAT_KV_U_PACKETS }, 5078 /* CRCERRS */ 5079 { "crc errs", 0x00300080, 32, KSTAT_KV_U_PACKETS }, 5080 /* RLEC */ 5081 { "rx len errs", 0x003000a0, 32, KSTAT_KV_U_PACKETS }, 5082 /* ERRBC */ 5083 { "byte errs", 0x003000c0, 32, KSTAT_KV_U_PACKETS }, 5084 /* ILLERRC */ 5085 { "illegal byte", 0x003000d0, 32, KSTAT_KV_U_PACKETS }, 5086 /* RUC */ 5087 { "rx undersize", 0x00300100, 32, KSTAT_KV_U_PACKETS }, 5088 /* ROC */ 5089 { "rx oversize", 0x00300120, 32, KSTAT_KV_U_PACKETS }, 5090 /* LXONRXCNT */ 5091 { "rx link xon", 0x00300140, 32, KSTAT_KV_U_PACKETS }, 5092 /* LXOFFRXCNT */ 5093 { "rx link xoff", 0x00300160, 32, KSTAT_KV_U_PACKETS }, 5094 5095 /* Priority XON Received Count */ 5096 /* Priority XOFF Received Count */ 5097 /* Priority XON to XOFF Count */ 5098 5099 /* PRC64 */ 5100 { "rx 64B", 0x00300480, 48, KSTAT_KV_U_PACKETS }, 5101 /* PRC127 */ 5102 { "rx 65-127B", 0x003004A0, 48, KSTAT_KV_U_PACKETS }, 5103 /* PRC255 */ 5104 { "rx 128-255B", 0x003004C0, 48, KSTAT_KV_U_PACKETS }, 5105 /* PRC511 */ 5106 { "rx 256-511B", 0x003004E0, 48, KSTAT_KV_U_PACKETS }, 5107 /* PRC1023 */ 5108 { "rx 512-1023B", 0x00300500, 48, KSTAT_KV_U_PACKETS }, 5109 /* PRC1522 */ 5110 { "rx 1024-1522B", 0x00300520, 48, KSTAT_KV_U_PACKETS }, 5111 /* PRC9522 */ 5112 { "rx 1523-9522B", 0x00300540, 48, KSTAT_KV_U_PACKETS }, 5113 /* ROC */ 5114 { "rx fragment", 0x00300560, 32, KSTAT_KV_U_PACKETS }, 5115 /* RJC */ 5116 { "rx jabber", 0x00300580, 32, KSTAT_KV_U_PACKETS }, 5117 /* UPRC */ 5118 { "rx ucasts", 0x003005a0, 48, KSTAT_KV_U_PACKETS }, 5119 /* MPRC */ 5120 { "rx mcasts", 0x003005c0, 48, KSTAT_KV_U_PACKETS }, 5121 /* BPRC */ 5122 { "rx bcasts", 0x003005e0, 48, KSTAT_KV_U_PACKETS }, 5123 /* RDPC */ 5124 { "rx discards", 0x00300600, 32, KSTAT_KV_U_PACKETS }, 5125 /* LDPC */ 5126 { "rx lo discards", 0x00300620, 32, KSTAT_KV_U_PACKETS }, 5127 /* RUPP */ 5128 { "rx no dest", 0x00300660, 32, KSTAT_KV_U_PACKETS }, 5129 5130 /* GOTC */ 5131 { "tx bytes", 0x00300680, 48, KSTAT_KV_U_BYTES }, 5132 /* PTC64 */ 5133 { "tx 64B", 0x003006A0, 48, KSTAT_KV_U_PACKETS }, 5134 /* PTC127 */ 5135 { "tx 65-127B", 0x003006C0, 48, KSTAT_KV_U_PACKETS }, 5136 /* PTC255 */ 5137 { "tx 128-255B", 0x003006E0, 48, KSTAT_KV_U_PACKETS }, 5138 /* PTC511 */ 5139 { "tx 256-511B", 0x00300700, 48, KSTAT_KV_U_PACKETS }, 5140 /* PTC1023 */ 5141 { "tx 512-1023B", 0x00300720, 48, KSTAT_KV_U_PACKETS }, 5142 /* PTC1522 */ 5143 { "tx 1024-1522B", 0x00300740, 48, KSTAT_KV_U_PACKETS }, 5144 /* PTC9522 */ 5145 { "tx 1523-9522B", 0x00300760, 48, KSTAT_KV_U_PACKETS }, 5146 5147 /* Priority XON Transmitted Count */ 5148 /* Priority XOFF Transmitted Count */ 5149 5150 /* LXONTXC */ 5151 { "tx link xon", 0x00300980, 48, KSTAT_KV_U_PACKETS }, 5152 /* LXOFFTXC */ 5153 { "tx link xoff", 0x003009a0, 48, KSTAT_KV_U_PACKETS }, 5154 /* UPTC */ 5155 { "tx ucasts", 0x003009c0, 48, KSTAT_KV_U_PACKETS }, 5156 /* MPTC */ 5157 { "tx mcasts", 0x003009e0, 48, KSTAT_KV_U_PACKETS }, 5158 /* BPTC */ 5159 { "tx bcasts", 0x00300a00, 48, KSTAT_KV_U_PACKETS }, 5160 /* TDOLD */ 5161 { "tx link down", 0x00300a20, 48, KSTAT_KV_U_PACKETS }, 5162 }; 5163 5164 const struct ixl_counter ixl_vsi_counters[] = { 5165 /* VSI RDPC */ 5166 { "rx discards", 0x00310000, 32, KSTAT_KV_U_PACKETS }, 5167 /* VSI GOTC */ 5168 { "tx bytes", 0x00328000, 48, KSTAT_KV_U_BYTES }, 5169 /* VSI UPTC */ 5170 { "tx ucasts", 0x0033c000, 48, KSTAT_KV_U_PACKETS }, 5171 /* VSI MPTC */ 5172 { "tx mcasts", 0x0033cc00, 48, KSTAT_KV_U_PACKETS }, 5173 /* VSI BPTC */ 5174 { "tx bcasts", 0x0033d800, 48, KSTAT_KV_U_PACKETS }, 5175 /* VSI TEPC */ 5176 { "tx errs", 0x00344000, 48, KSTAT_KV_U_PACKETS }, 5177 /* VSI TDPC */ 5178 { "tx discards", 0x00348000, 48, KSTAT_KV_U_PACKETS }, 5179 /* VSI GORC */ 5180 { "rx bytes", 0x00358000, 48, KSTAT_KV_U_BYTES }, 5181 /* VSI UPRC */ 5182 { "rx ucasts", 0x0036c000, 48, KSTAT_KV_U_PACKETS }, 5183 /* VSI MPRC */ 5184 { "rx mcasts", 0x0036cc00, 48, KSTAT_KV_U_PACKETS }, 5185 /* VSI BPRC */ 5186 { "rx bcasts", 0x0036d800, 48, KSTAT_KV_U_PACKETS }, 5187 /* VSI RUPP */ 5188 { "rx noproto", 0x0036e400, 32, KSTAT_KV_U_PACKETS }, 5189 }; 5190 5191 struct ixl_counter_state { 5192 const struct ixl_counter 5193 *counters; 5194 uint64_t *values; 5195 size_t n; 5196 uint32_t index; 5197 unsigned int gen; 5198 }; 5199 5200 static void 5201 ixl_rd_counters(struct ixl_softc *sc, const struct ixl_counter_state *state, 5202 uint64_t *vs) 5203 { 5204 const struct ixl_counter *c; 5205 bus_addr_t r; 5206 uint64_t v; 5207 size_t i; 5208 5209 for (i = 0; i < state->n; i++) { 5210 c = &state->counters[i]; 5211 5212 r = c->c_base + (state->index * 8); 5213 5214 if (c->c_width == 32) 5215 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, r); 5216 else 5217 v = bus_space_read_8(sc->sc_memt, sc->sc_memh, r); 5218 5219 vs[i] = v; 5220 } 5221 } 5222 5223 static int 5224 ixl_kstat_read(struct kstat *ks) 5225 { 5226 struct ixl_softc *sc = ks->ks_softc; 5227 struct kstat_kv *kvs = ks->ks_data; 5228 struct ixl_counter_state *state = ks->ks_ptr; 5229 unsigned int gen = (state->gen++) & 1; 5230 uint64_t *ovs = state->values + (gen * state->n); 5231 uint64_t *nvs = state->values + (!gen * state->n); 5232 size_t i; 5233 5234 ixl_rd_counters(sc, state, nvs); 5235 getnanouptime(&ks->ks_updated); 5236 5237 for (i = 0; i < state->n; i++) { 5238 const struct ixl_counter *c = &state->counters[i]; 5239 uint64_t n = nvs[i], o = ovs[i]; 5240 5241 if (c->c_width < 64) { 5242 if (n < o) 5243 n += (1ULL << c->c_width); 5244 } 5245 5246 kstat_kv_u64(&kvs[i]) += (n - o); 5247 } 5248 5249 return (0); 5250 } 5251 5252 static void 5253 ixl_kstat_tick(void *arg) 5254 { 5255 struct ixl_softc *sc = arg; 5256 5257 timeout_add_sec(&sc->sc_kstat_tmo, 4); 5258 5259 mtx_enter(&sc->sc_kstat_mtx); 5260 5261 ixl_kstat_read(sc->sc_port_kstat); 5262 ixl_kstat_read(sc->sc_vsi_kstat); 5263 5264 mtx_leave(&sc->sc_kstat_mtx); 5265 } 5266 5267 static struct kstat * 5268 ixl_kstat_create(struct ixl_softc *sc, const char *name, 5269 const struct ixl_counter *counters, size_t n, uint32_t index) 5270 { 5271 struct kstat *ks; 5272 struct kstat_kv *kvs; 5273 struct ixl_counter_state *state; 5274 const struct ixl_counter *c; 5275 unsigned int i; 5276 5277 ks = kstat_create(DEVNAME(sc), 0, name, 0, KSTAT_T_KV, 0); 5278 if (ks == NULL) { 5279 /* unable to create kstats */ 5280 return (NULL); 5281 } 5282 5283 kvs = mallocarray(n, sizeof(*kvs), M_DEVBUF, M_WAITOK|M_ZERO); 5284 for (i = 0; i < n; i++) { 5285 c = &counters[i]; 5286 5287 kstat_kv_unit_init(&kvs[i], c->c_name, 5288 KSTAT_KV_T_COUNTER64, c->c_type); 5289 } 5290 5291 ks->ks_data = kvs; 5292 ks->ks_datalen = n * sizeof(*kvs); 5293 ks->ks_read = ixl_kstat_read; 5294 5295 state = malloc(sizeof(*state), M_DEVBUF, M_WAITOK|M_ZERO); 5296 state->counters = counters; 5297 state->n = n; 5298 state->values = mallocarray(n * 2, sizeof(*state->values), 5299 M_DEVBUF, M_WAITOK|M_ZERO); 5300 state->index = index; 5301 ks->ks_ptr = state; 5302 5303 kstat_set_mutex(ks, &sc->sc_kstat_mtx); 5304 ks->ks_softc = sc; 5305 kstat_install(ks); 5306 5307 /* fetch a baseline */ 5308 ixl_rd_counters(sc, state, state->values); 5309 5310 return (ks); 5311 } 5312 5313 static void 5314 ixl_kstat_attach(struct ixl_softc *sc) 5315 { 5316 mtx_init(&sc->sc_kstat_mtx, IPL_SOFTCLOCK); 5317 timeout_set(&sc->sc_kstat_tmo, ixl_kstat_tick, sc); 5318 5319 sc->sc_port_kstat = ixl_kstat_create(sc, "ixl-port", 5320 ixl_port_counters, nitems(ixl_port_counters), sc->sc_port); 5321 sc->sc_vsi_kstat = ixl_kstat_create(sc, "ixl-vsi", 5322 ixl_vsi_counters, nitems(ixl_vsi_counters), 5323 lemtoh16(&sc->sc_vsi_number)); 5324 5325 /* ixl counters go up even when the interface is down */ 5326 timeout_add_sec(&sc->sc_kstat_tmo, 4); 5327 } 5328 5329 #endif /* NKSTAT > 0 */ 5330