1 /* $OpenBSD: if_ixl.c,v 1.83 2022/03/11 18:00:45 mpi Exp $ */ 2 3 /* 4 * Copyright (c) 2013-2015, Intel Corporation 5 * All rights reserved. 6 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 2016,2017 David Gwynne <dlg@openbsd.org> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50 #include "bpfilter.h" 51 #include "kstat.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/proc.h> 56 #include <sys/sockio.h> 57 #include <sys/mbuf.h> 58 #include <sys/kernel.h> 59 #include <sys/socket.h> 60 #include <sys/device.h> 61 #include <sys/pool.h> 62 #include <sys/queue.h> 63 #include <sys/timeout.h> 64 #include <sys/task.h> 65 #include <sys/syslog.h> 66 #include <sys/intrmap.h> 67 68 #include <machine/bus.h> 69 #include <machine/intr.h> 70 71 #include <net/if.h> 72 #include <net/if_dl.h> 73 #include <net/if_media.h> 74 #include <net/toeplitz.h> 75 76 #if NBPFILTER > 0 77 #include <net/bpf.h> 78 #endif 79 80 #if NKSTAT > 0 81 #include <sys/kstat.h> 82 #endif 83 84 #include <netinet/in.h> 85 #include <netinet/ip.h> 86 #include <netinet/ip6.h> 87 #include <netinet/tcp.h> 88 #include <netinet/udp.h> 89 #include <netinet/if_ether.h> 90 91 #include <dev/pci/pcireg.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/pcidevs.h> 94 95 #ifdef __sparc64__ 96 #include <dev/ofw/openfirm.h> 97 #endif 98 99 #ifndef CACHE_LINE_SIZE 100 #define CACHE_LINE_SIZE 64 101 #endif 102 103 #define IXL_MAX_VECTORS 8 /* XXX this is pretty arbitrary */ 104 105 #define I40E_MASK(mask, shift) ((mask) << (shift)) 106 #define I40E_PF_RESET_WAIT_COUNT 200 107 #define I40E_AQ_LARGE_BUF 512 108 109 /* bitfields for Tx queue mapping in QTX_CTL */ 110 #define I40E_QTX_CTL_VF_QUEUE 0x0 111 #define I40E_QTX_CTL_VM_QUEUE 0x1 112 #define I40E_QTX_CTL_PF_QUEUE 0x2 113 114 #define I40E_QUEUE_TYPE_EOL 0x7ff 115 #define I40E_INTR_NOTX_QUEUE 0 116 117 #define I40E_QUEUE_TYPE_RX 0x0 118 #define I40E_QUEUE_TYPE_TX 0x1 119 #define I40E_QUEUE_TYPE_PE_CEQ 0x2 120 #define I40E_QUEUE_TYPE_UNKNOWN 0x3 121 122 #define I40E_ITR_INDEX_RX 0x0 123 #define I40E_ITR_INDEX_TX 0x1 124 #define I40E_ITR_INDEX_OTHER 0x2 125 #define I40E_ITR_INDEX_NONE 0x3 126 127 #include <dev/pci/if_ixlreg.h> 128 129 #define I40E_INTR_NOTX_QUEUE 0 130 #define I40E_INTR_NOTX_INTR 0 131 #define I40E_INTR_NOTX_RX_QUEUE 0 132 #define I40E_INTR_NOTX_TX_QUEUE 1 133 #define I40E_INTR_NOTX_RX_MASK I40E_PFINT_ICR0_QUEUE_0_MASK 134 #define I40E_INTR_NOTX_TX_MASK I40E_PFINT_ICR0_QUEUE_1_MASK 135 136 struct ixl_aq_desc { 137 uint16_t iaq_flags; 138 #define IXL_AQ_DD (1U << 0) 139 #define IXL_AQ_CMP (1U << 1) 140 #define IXL_AQ_ERR (1U << 2) 141 #define IXL_AQ_VFE (1U << 3) 142 #define IXL_AQ_LB (1U << 9) 143 #define IXL_AQ_RD (1U << 10) 144 #define IXL_AQ_VFC (1U << 11) 145 #define IXL_AQ_BUF (1U << 12) 146 #define IXL_AQ_SI (1U << 13) 147 #define IXL_AQ_EI (1U << 14) 148 #define IXL_AQ_FE (1U << 15) 149 150 #define IXL_AQ_FLAGS_FMT "\020" "\020FE" "\017EI" "\016SI" "\015BUF" \ 151 "\014VFC" "\013DB" "\012LB" "\004VFE" \ 152 "\003ERR" "\002CMP" "\001DD" 153 154 uint16_t iaq_opcode; 155 156 uint16_t iaq_datalen; 157 uint16_t iaq_retval; 158 159 uint64_t iaq_cookie; 160 161 uint32_t iaq_param[4]; 162 /* iaq_data_hi iaq_param[2] */ 163 /* iaq_data_lo iaq_param[3] */ 164 } __packed __aligned(8); 165 166 /* aq commands */ 167 #define IXL_AQ_OP_GET_VERSION 0x0001 168 #define IXL_AQ_OP_DRIVER_VERSION 0x0002 169 #define IXL_AQ_OP_QUEUE_SHUTDOWN 0x0003 170 #define IXL_AQ_OP_SET_PF_CONTEXT 0x0004 171 #define IXL_AQ_OP_GET_AQ_ERR_REASON 0x0005 172 #define IXL_AQ_OP_REQUEST_RESOURCE 0x0008 173 #define IXL_AQ_OP_RELEASE_RESOURCE 0x0009 174 #define IXL_AQ_OP_LIST_FUNC_CAP 0x000a 175 #define IXL_AQ_OP_LIST_DEV_CAP 0x000b 176 #define IXL_AQ_OP_MAC_ADDRESS_READ 0x0107 177 #define IXL_AQ_OP_CLEAR_PXE_MODE 0x0110 178 #define IXL_AQ_OP_SWITCH_GET_CONFIG 0x0200 179 #define IXL_AQ_OP_RX_CTL_READ 0x0206 180 #define IXL_AQ_OP_RX_CTL_WRITE 0x0207 181 #define IXL_AQ_OP_ADD_VSI 0x0210 182 #define IXL_AQ_OP_UPD_VSI_PARAMS 0x0211 183 #define IXL_AQ_OP_GET_VSI_PARAMS 0x0212 184 #define IXL_AQ_OP_ADD_VEB 0x0230 185 #define IXL_AQ_OP_UPD_VEB_PARAMS 0x0231 186 #define IXL_AQ_OP_GET_VEB_PARAMS 0x0232 187 #define IXL_AQ_OP_ADD_MACVLAN 0x0250 188 #define IXL_AQ_OP_REMOVE_MACVLAN 0x0251 189 #define IXL_AQ_OP_SET_VSI_PROMISC 0x0254 190 #define IXL_AQ_OP_PHY_GET_ABILITIES 0x0600 191 #define IXL_AQ_OP_PHY_SET_CONFIG 0x0601 192 #define IXL_AQ_OP_PHY_SET_MAC_CONFIG 0x0603 193 #define IXL_AQ_OP_PHY_RESTART_AN 0x0605 194 #define IXL_AQ_OP_PHY_LINK_STATUS 0x0607 195 #define IXL_AQ_OP_PHY_SET_EVENT_MASK 0x0613 196 #define IXL_AQ_OP_PHY_SET_REGISTER 0x0628 197 #define IXL_AQ_OP_PHY_GET_REGISTER 0x0629 198 #define IXL_AQ_OP_LLDP_GET_MIB 0x0a00 199 #define IXL_AQ_OP_LLDP_MIB_CHG_EV 0x0a01 200 #define IXL_AQ_OP_LLDP_ADD_TLV 0x0a02 201 #define IXL_AQ_OP_LLDP_UPD_TLV 0x0a03 202 #define IXL_AQ_OP_LLDP_DEL_TLV 0x0a04 203 #define IXL_AQ_OP_LLDP_STOP_AGENT 0x0a05 204 #define IXL_AQ_OP_LLDP_START_AGENT 0x0a06 205 #define IXL_AQ_OP_LLDP_GET_CEE_DCBX 0x0a07 206 #define IXL_AQ_OP_LLDP_SPECIFIC_AGENT 0x0a09 207 #define IXL_AQ_OP_SET_RSS_KEY 0x0b02 /* 722 only */ 208 #define IXL_AQ_OP_SET_RSS_LUT 0x0b03 /* 722 only */ 209 #define IXL_AQ_OP_GET_RSS_KEY 0x0b04 /* 722 only */ 210 #define IXL_AQ_OP_GET_RSS_LUT 0x0b05 /* 722 only */ 211 212 struct ixl_aq_mac_addresses { 213 uint8_t pf_lan[ETHER_ADDR_LEN]; 214 uint8_t pf_san[ETHER_ADDR_LEN]; 215 uint8_t port[ETHER_ADDR_LEN]; 216 uint8_t pf_wol[ETHER_ADDR_LEN]; 217 } __packed; 218 219 #define IXL_AQ_MAC_PF_LAN_VALID (1U << 4) 220 #define IXL_AQ_MAC_PF_SAN_VALID (1U << 5) 221 #define IXL_AQ_MAC_PORT_VALID (1U << 6) 222 #define IXL_AQ_MAC_PF_WOL_VALID (1U << 7) 223 224 struct ixl_aq_capability { 225 uint16_t cap_id; 226 #define IXL_AQ_CAP_SWITCH_MODE 0x0001 227 #define IXL_AQ_CAP_MNG_MODE 0x0002 228 #define IXL_AQ_CAP_NPAR_ACTIVE 0x0003 229 #define IXL_AQ_CAP_OS2BMC_CAP 0x0004 230 #define IXL_AQ_CAP_FUNCTIONS_VALID 0x0005 231 #define IXL_AQ_CAP_ALTERNATE_RAM 0x0006 232 #define IXL_AQ_CAP_WOL_AND_PROXY 0x0008 233 #define IXL_AQ_CAP_SRIOV 0x0012 234 #define IXL_AQ_CAP_VF 0x0013 235 #define IXL_AQ_CAP_VMDQ 0x0014 236 #define IXL_AQ_CAP_8021QBG 0x0015 237 #define IXL_AQ_CAP_8021QBR 0x0016 238 #define IXL_AQ_CAP_VSI 0x0017 239 #define IXL_AQ_CAP_DCB 0x0018 240 #define IXL_AQ_CAP_FCOE 0x0021 241 #define IXL_AQ_CAP_ISCSI 0x0022 242 #define IXL_AQ_CAP_RSS 0x0040 243 #define IXL_AQ_CAP_RXQ 0x0041 244 #define IXL_AQ_CAP_TXQ 0x0042 245 #define IXL_AQ_CAP_MSIX 0x0043 246 #define IXL_AQ_CAP_VF_MSIX 0x0044 247 #define IXL_AQ_CAP_FLOW_DIRECTOR 0x0045 248 #define IXL_AQ_CAP_1588 0x0046 249 #define IXL_AQ_CAP_IWARP 0x0051 250 #define IXL_AQ_CAP_LED 0x0061 251 #define IXL_AQ_CAP_SDP 0x0062 252 #define IXL_AQ_CAP_MDIO 0x0063 253 #define IXL_AQ_CAP_WSR_PROT 0x0064 254 #define IXL_AQ_CAP_NVM_MGMT 0x0080 255 #define IXL_AQ_CAP_FLEX10 0x00F1 256 #define IXL_AQ_CAP_CEM 0x00F2 257 uint8_t major_rev; 258 uint8_t minor_rev; 259 uint32_t number; 260 uint32_t logical_id; 261 uint32_t phys_id; 262 uint8_t _reserved[16]; 263 } __packed __aligned(4); 264 265 #define IXL_LLDP_SHUTDOWN 0x1 266 267 struct ixl_aq_switch_config { 268 uint16_t num_reported; 269 uint16_t num_total; 270 uint8_t _reserved[12]; 271 } __packed __aligned(4); 272 273 struct ixl_aq_switch_config_element { 274 uint8_t type; 275 #define IXL_AQ_SW_ELEM_TYPE_MAC 1 276 #define IXL_AQ_SW_ELEM_TYPE_PF 2 277 #define IXL_AQ_SW_ELEM_TYPE_VF 3 278 #define IXL_AQ_SW_ELEM_TYPE_EMP 4 279 #define IXL_AQ_SW_ELEM_TYPE_BMC 5 280 #define IXL_AQ_SW_ELEM_TYPE_PV 16 281 #define IXL_AQ_SW_ELEM_TYPE_VEB 17 282 #define IXL_AQ_SW_ELEM_TYPE_PA 18 283 #define IXL_AQ_SW_ELEM_TYPE_VSI 19 284 uint8_t revision; 285 #define IXL_AQ_SW_ELEM_REV_1 1 286 uint16_t seid; 287 288 uint16_t uplink_seid; 289 uint16_t downlink_seid; 290 291 uint8_t _reserved[3]; 292 uint8_t connection_type; 293 #define IXL_AQ_CONN_TYPE_REGULAR 0x1 294 #define IXL_AQ_CONN_TYPE_DEFAULT 0x2 295 #define IXL_AQ_CONN_TYPE_CASCADED 0x3 296 297 uint16_t scheduler_id; 298 uint16_t element_info; 299 } __packed __aligned(4); 300 301 #define IXL_PHY_TYPE_SGMII 0x00 302 #define IXL_PHY_TYPE_1000BASE_KX 0x01 303 #define IXL_PHY_TYPE_10GBASE_KX4 0x02 304 #define IXL_PHY_TYPE_10GBASE_KR 0x03 305 #define IXL_PHY_TYPE_40GBASE_KR4 0x04 306 #define IXL_PHY_TYPE_XAUI 0x05 307 #define IXL_PHY_TYPE_XFI 0x06 308 #define IXL_PHY_TYPE_SFI 0x07 309 #define IXL_PHY_TYPE_XLAUI 0x08 310 #define IXL_PHY_TYPE_XLPPI 0x09 311 #define IXL_PHY_TYPE_40GBASE_CR4_CU 0x0a 312 #define IXL_PHY_TYPE_10GBASE_CR1_CU 0x0b 313 #define IXL_PHY_TYPE_10GBASE_AOC 0x0c 314 #define IXL_PHY_TYPE_40GBASE_AOC 0x0d 315 #define IXL_PHY_TYPE_100BASE_TX 0x11 316 #define IXL_PHY_TYPE_1000BASE_T 0x12 317 #define IXL_PHY_TYPE_10GBASE_T 0x13 318 #define IXL_PHY_TYPE_10GBASE_SR 0x14 319 #define IXL_PHY_TYPE_10GBASE_LR 0x15 320 #define IXL_PHY_TYPE_10GBASE_SFPP_CU 0x16 321 #define IXL_PHY_TYPE_10GBASE_CR1 0x17 322 #define IXL_PHY_TYPE_40GBASE_CR4 0x18 323 #define IXL_PHY_TYPE_40GBASE_SR4 0x19 324 #define IXL_PHY_TYPE_40GBASE_LR4 0x1a 325 #define IXL_PHY_TYPE_1000BASE_SX 0x1b 326 #define IXL_PHY_TYPE_1000BASE_LX 0x1c 327 #define IXL_PHY_TYPE_1000BASE_T_OPTICAL 0x1d 328 #define IXL_PHY_TYPE_20GBASE_KR2 0x1e 329 330 #define IXL_PHY_TYPE_25GBASE_KR 0x1f 331 #define IXL_PHY_TYPE_25GBASE_CR 0x20 332 #define IXL_PHY_TYPE_25GBASE_SR 0x21 333 #define IXL_PHY_TYPE_25GBASE_LR 0x22 334 #define IXL_PHY_TYPE_25GBASE_AOC 0x23 335 #define IXL_PHY_TYPE_25GBASE_ACC 0x24 336 337 struct ixl_aq_module_desc { 338 uint8_t oui[3]; 339 uint8_t _reserved1; 340 uint8_t part_number[16]; 341 uint8_t revision[4]; 342 uint8_t _reserved2[8]; 343 } __packed __aligned(4); 344 345 struct ixl_aq_phy_abilities { 346 uint32_t phy_type; 347 348 uint8_t link_speed; 349 #define IXL_AQ_PHY_LINK_SPEED_100MB (1 << 1) 350 #define IXL_AQ_PHY_LINK_SPEED_1000MB (1 << 2) 351 #define IXL_AQ_PHY_LINK_SPEED_10GB (1 << 3) 352 #define IXL_AQ_PHY_LINK_SPEED_40GB (1 << 4) 353 #define IXL_AQ_PHY_LINK_SPEED_20GB (1 << 5) 354 #define IXL_AQ_PHY_LINK_SPEED_25GB (1 << 6) 355 uint8_t abilities; 356 uint16_t eee_capability; 357 358 uint32_t eeer_val; 359 360 uint8_t d3_lpan; 361 uint8_t phy_type_ext; 362 #define IXL_AQ_PHY_TYPE_EXT_25G_KR 0x01 363 #define IXL_AQ_PHY_TYPE_EXT_25G_CR 0x02 364 #define IXL_AQ_PHY_TYPE_EXT_25G_SR 0x04 365 #define IXL_AQ_PHY_TYPE_EXT_25G_LR 0x08 366 uint8_t fec_cfg_curr_mod_ext_info; 367 #define IXL_AQ_ENABLE_FEC_KR 0x01 368 #define IXL_AQ_ENABLE_FEC_RS 0x02 369 #define IXL_AQ_REQUEST_FEC_KR 0x04 370 #define IXL_AQ_REQUEST_FEC_RS 0x08 371 #define IXL_AQ_ENABLE_FEC_AUTO 0x10 372 #define IXL_AQ_MODULE_TYPE_EXT_MASK 0xe0 373 #define IXL_AQ_MODULE_TYPE_EXT_SHIFT 5 374 uint8_t ext_comp_code; 375 376 uint8_t phy_id[4]; 377 378 uint8_t module_type[3]; 379 #define IXL_SFF8024_ID_SFP 0x03 380 #define IXL_SFF8024_ID_QSFP 0x0c 381 #define IXL_SFF8024_ID_QSFP_PLUS 0x0d 382 #define IXL_SFF8024_ID_QSFP28 0x11 383 uint8_t qualified_module_count; 384 #define IXL_AQ_PHY_MAX_QMS 16 385 struct ixl_aq_module_desc 386 qualified_module[IXL_AQ_PHY_MAX_QMS]; 387 } __packed __aligned(4); 388 389 struct ixl_aq_link_param { 390 uint8_t notify; 391 #define IXL_AQ_LINK_NOTIFY 0x03 392 uint8_t _reserved1; 393 uint8_t phy; 394 uint8_t speed; 395 uint8_t status; 396 uint8_t _reserved2[11]; 397 } __packed __aligned(4); 398 399 struct ixl_aq_vsi_param { 400 uint16_t uplink_seid; 401 uint8_t connect_type; 402 #define IXL_AQ_VSI_CONN_TYPE_NORMAL (0x1) 403 #define IXL_AQ_VSI_CONN_TYPE_DEFAULT (0x2) 404 #define IXL_AQ_VSI_CONN_TYPE_CASCADED (0x3) 405 uint8_t _reserved1; 406 407 uint8_t vf_id; 408 uint8_t _reserved2; 409 uint16_t vsi_flags; 410 #define IXL_AQ_VSI_TYPE_SHIFT 0x0 411 #define IXL_AQ_VSI_TYPE_MASK (0x3 << IXL_AQ_VSI_TYPE_SHIFT) 412 #define IXL_AQ_VSI_TYPE_VF 0x0 413 #define IXL_AQ_VSI_TYPE_VMDQ2 0x1 414 #define IXL_AQ_VSI_TYPE_PF 0x2 415 #define IXL_AQ_VSI_TYPE_EMP_MNG 0x3 416 #define IXL_AQ_VSI_FLAG_CASCADED_PV 0x4 417 418 uint32_t addr_hi; 419 uint32_t addr_lo; 420 } __packed __aligned(16); 421 422 struct ixl_aq_add_macvlan { 423 uint16_t num_addrs; 424 uint16_t seid0; 425 uint16_t seid1; 426 uint16_t seid2; 427 uint32_t addr_hi; 428 uint32_t addr_lo; 429 } __packed __aligned(16); 430 431 struct ixl_aq_add_macvlan_elem { 432 uint8_t macaddr[6]; 433 uint16_t vlan; 434 uint16_t flags; 435 #define IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH 0x0001 436 #define IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN 0x0004 437 uint16_t queue; 438 uint32_t _reserved; 439 } __packed __aligned(16); 440 441 struct ixl_aq_remove_macvlan { 442 uint16_t num_addrs; 443 uint16_t seid0; 444 uint16_t seid1; 445 uint16_t seid2; 446 uint32_t addr_hi; 447 uint32_t addr_lo; 448 } __packed __aligned(16); 449 450 struct ixl_aq_remove_macvlan_elem { 451 uint8_t macaddr[6]; 452 uint16_t vlan; 453 uint8_t flags; 454 #define IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH 0x0001 455 #define IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN 0x0008 456 uint8_t _reserved[7]; 457 } __packed __aligned(16); 458 459 struct ixl_aq_vsi_reply { 460 uint16_t seid; 461 uint16_t vsi_number; 462 463 uint16_t vsis_used; 464 uint16_t vsis_free; 465 466 uint32_t addr_hi; 467 uint32_t addr_lo; 468 } __packed __aligned(16); 469 470 struct ixl_aq_vsi_data { 471 /* first 96 byte are written by SW */ 472 uint16_t valid_sections; 473 #define IXL_AQ_VSI_VALID_SWITCH (1 << 0) 474 #define IXL_AQ_VSI_VALID_SECURITY (1 << 1) 475 #define IXL_AQ_VSI_VALID_VLAN (1 << 2) 476 #define IXL_AQ_VSI_VALID_CAS_PV (1 << 3) 477 #define IXL_AQ_VSI_VALID_INGRESS_UP (1 << 4) 478 #define IXL_AQ_VSI_VALID_EGRESS_UP (1 << 5) 479 #define IXL_AQ_VSI_VALID_QUEUE_MAP (1 << 6) 480 #define IXL_AQ_VSI_VALID_QUEUE_OPT (1 << 7) 481 #define IXL_AQ_VSI_VALID_OUTER_UP (1 << 8) 482 #define IXL_AQ_VSI_VALID_SCHED (1 << 9) 483 /* switch section */ 484 uint16_t switch_id; 485 #define IXL_AQ_VSI_SWITCH_ID_SHIFT 0 486 #define IXL_AQ_VSI_SWITCH_ID_MASK (0xfff << IXL_AQ_VSI_SWITCH_ID_SHIFT) 487 #define IXL_AQ_VSI_SWITCH_NOT_STAG (1 << 12) 488 #define IXL_AQ_VSI_SWITCH_LOCAL_LB (1 << 14) 489 490 uint8_t _reserved1[2]; 491 /* security section */ 492 uint8_t sec_flags; 493 #define IXL_AQ_VSI_SEC_ALLOW_DEST_OVRD (1 << 0) 494 #define IXL_AQ_VSI_SEC_ENABLE_VLAN_CHK (1 << 1) 495 #define IXL_AQ_VSI_SEC_ENABLE_MAC_CHK (1 << 2) 496 uint8_t _reserved2; 497 498 /* vlan section */ 499 uint16_t pvid; 500 uint16_t fcoe_pvid; 501 502 uint8_t port_vlan_flags; 503 #define IXL_AQ_VSI_PVLAN_MODE_SHIFT 0 504 #define IXL_AQ_VSI_PVLAN_MODE_MASK (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 505 #define IXL_AQ_VSI_PVLAN_MODE_TAGGED (0x1 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 506 #define IXL_AQ_VSI_PVLAN_MODE_UNTAGGED (0x2 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 507 #define IXL_AQ_VSI_PVLAN_MODE_ALL (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 508 #define IXL_AQ_VSI_PVLAN_INSERT_PVID (0x4 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 509 #define IXL_AQ_VSI_PVLAN_EMOD_SHIFT 0x3 510 #define IXL_AQ_VSI_PVLAN_EMOD_MASK (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 511 #define IXL_AQ_VSI_PVLAN_EMOD_STR_BOTH (0x0 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 512 #define IXL_AQ_VSI_PVLAN_EMOD_STR_UP (0x1 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 513 #define IXL_AQ_VSI_PVLAN_EMOD_STR (0x2 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 514 #define IXL_AQ_VSI_PVLAN_EMOD_NOTHING (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 515 uint8_t _reserved3[3]; 516 517 /* ingress egress up section */ 518 uint32_t ingress_table; 519 #define IXL_AQ_VSI_UP_SHIFT(_up) ((_up) * 3) 520 #define IXL_AQ_VSI_UP_MASK(_up) (0x7 << (IXL_AQ_VSI_UP_SHIFT(_up)) 521 uint32_t egress_table; 522 523 /* cascaded pv section */ 524 uint16_t cas_pv_tag; 525 uint8_t cas_pv_flags; 526 #define IXL_AQ_VSI_CAS_PV_TAGX_SHIFT 0 527 #define IXL_AQ_VSI_CAS_PV_TAGX_MASK (0x3 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 528 #define IXL_AQ_VSI_CAS_PV_TAGX_LEAVE (0x0 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 529 #define IXL_AQ_VSI_CAS_PV_TAGX_REMOVE (0x1 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 530 #define IXL_AQ_VSI_CAS_PV_TAGX_COPY (0x2 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 531 #define IXL_AQ_VSI_CAS_PV_INSERT_TAG (1 << 4) 532 #define IXL_AQ_VSI_CAS_PV_ETAG_PRUNE (1 << 5) 533 #define IXL_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG \ 534 (1 << 6) 535 uint8_t _reserved4; 536 537 /* queue mapping section */ 538 uint16_t mapping_flags; 539 #define IXL_AQ_VSI_QUE_MAP_MASK 0x1 540 #define IXL_AQ_VSI_QUE_MAP_CONTIG 0x0 541 #define IXL_AQ_VSI_QUE_MAP_NONCONTIG 0x1 542 uint16_t queue_mapping[16]; 543 #define IXL_AQ_VSI_QUEUE_SHIFT 0x0 544 #define IXL_AQ_VSI_QUEUE_MASK (0x7ff << IXL_AQ_VSI_QUEUE_SHIFT) 545 uint16_t tc_mapping[8]; 546 #define IXL_AQ_VSI_TC_Q_OFFSET_SHIFT 0 547 #define IXL_AQ_VSI_TC_Q_OFFSET_MASK (0x1ff << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) 548 #define IXL_AQ_VSI_TC_Q_NUMBER_SHIFT 9 549 #define IXL_AQ_VSI_TC_Q_NUMBER_MASK (0x7 << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT) 550 551 /* queueing option section */ 552 uint8_t queueing_opt_flags; 553 #define IXL_AQ_VSI_QUE_OPT_MCAST_UDP_EN (1 << 2) 554 #define IXL_AQ_VSI_QUE_OPT_UCAST_UDP_EN (1 << 3) 555 #define IXL_AQ_VSI_QUE_OPT_TCP_EN (1 << 4) 556 #define IXL_AQ_VSI_QUE_OPT_FCOE_EN (1 << 5) 557 #define IXL_AQ_VSI_QUE_OPT_RSS_LUT_PF 0 558 #define IXL_AQ_VSI_QUE_OPT_RSS_LUT_VSI (1 << 6) 559 uint8_t _reserved5[3]; 560 561 /* scheduler section */ 562 uint8_t up_enable_bits; 563 uint8_t _reserved6; 564 565 /* outer up section */ 566 uint32_t outer_up_table; /* same as ingress/egress tables */ 567 uint8_t _reserved7[8]; 568 569 /* last 32 bytes are written by FW */ 570 uint16_t qs_handle[8]; 571 #define IXL_AQ_VSI_QS_HANDLE_INVALID 0xffff 572 uint16_t stat_counter_idx; 573 uint16_t sched_id; 574 575 uint8_t _reserved8[12]; 576 } __packed __aligned(8); 577 578 CTASSERT(sizeof(struct ixl_aq_vsi_data) == 128); 579 580 struct ixl_aq_vsi_promisc_param { 581 uint16_t flags; 582 uint16_t valid_flags; 583 #define IXL_AQ_VSI_PROMISC_FLAG_UCAST (1 << 0) 584 #define IXL_AQ_VSI_PROMISC_FLAG_MCAST (1 << 1) 585 #define IXL_AQ_VSI_PROMISC_FLAG_BCAST (1 << 2) 586 #define IXL_AQ_VSI_PROMISC_FLAG_DFLT (1 << 3) 587 #define IXL_AQ_VSI_PROMISC_FLAG_VLAN (1 << 4) 588 #define IXL_AQ_VSI_PROMISC_FLAG_RXONLY (1 << 15) 589 590 uint16_t seid; 591 #define IXL_AQ_VSI_PROMISC_SEID_VALID (1 << 15) 592 uint16_t vlan; 593 #define IXL_AQ_VSI_PROMISC_VLAN_VALID (1 << 15) 594 uint32_t reserved[2]; 595 } __packed __aligned(8); 596 597 struct ixl_aq_veb_param { 598 uint16_t uplink_seid; 599 uint16_t downlink_seid; 600 uint16_t veb_flags; 601 #define IXL_AQ_ADD_VEB_FLOATING (1 << 0) 602 #define IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT 1 603 #define IXL_AQ_ADD_VEB_PORT_TYPE_MASK (0x3 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 604 #define IXL_AQ_ADD_VEB_PORT_TYPE_DEFAULT \ 605 (0x2 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 606 #define IXL_AQ_ADD_VEB_PORT_TYPE_DATA (0x4 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 607 #define IXL_AQ_ADD_VEB_ENABLE_L2_FILTER (1 << 3) /* deprecated */ 608 #define IXL_AQ_ADD_VEB_DISABLE_STATS (1 << 4) 609 uint8_t enable_tcs; 610 uint8_t _reserved[9]; 611 } __packed __aligned(16); 612 613 struct ixl_aq_veb_reply { 614 uint16_t _reserved1; 615 uint16_t _reserved2; 616 uint16_t _reserved3; 617 uint16_t switch_seid; 618 uint16_t veb_seid; 619 #define IXL_AQ_VEB_ERR_FLAG_NO_VEB (1 << 0) 620 #define IXL_AQ_VEB_ERR_FLAG_NO_SCHED (1 << 1) 621 #define IXL_AQ_VEB_ERR_FLAG_NO_COUNTER (1 << 2) 622 #define IXL_AQ_VEB_ERR_FLAG_NO_ENTRY (1 << 3); 623 uint16_t statistic_index; 624 uint16_t vebs_used; 625 uint16_t vebs_free; 626 } __packed __aligned(16); 627 628 /* GET PHY ABILITIES param[0] */ 629 #define IXL_AQ_PHY_REPORT_QUAL (1 << 0) 630 #define IXL_AQ_PHY_REPORT_INIT (1 << 1) 631 632 struct ixl_aq_phy_reg_access { 633 uint8_t phy_iface; 634 #define IXL_AQ_PHY_IF_INTERNAL 0 635 #define IXL_AQ_PHY_IF_EXTERNAL 1 636 #define IXL_AQ_PHY_IF_MODULE 2 637 uint8_t dev_addr; 638 uint16_t recall; 639 #define IXL_AQ_PHY_QSFP_DEV_ADDR 0 640 #define IXL_AQ_PHY_QSFP_LAST 1 641 uint32_t reg; 642 uint32_t val; 643 uint32_t _reserved2; 644 } __packed __aligned(16); 645 646 /* RESTART_AN param[0] */ 647 #define IXL_AQ_PHY_RESTART_AN (1 << 1) 648 #define IXL_AQ_PHY_LINK_ENABLE (1 << 2) 649 650 struct ixl_aq_link_status { /* this occupies the iaq_param space */ 651 uint16_t command_flags; /* only field set on command */ 652 #define IXL_AQ_LSE_MASK 0x3 653 #define IXL_AQ_LSE_NOP 0x0 654 #define IXL_AQ_LSE_DISABLE 0x2 655 #define IXL_AQ_LSE_ENABLE 0x3 656 #define IXL_AQ_LSE_IS_ENABLED 0x1 /* only set in response */ 657 uint8_t phy_type; 658 uint8_t link_speed; 659 #define IXL_AQ_LINK_SPEED_1GB (1 << 2) 660 #define IXL_AQ_LINK_SPEED_10GB (1 << 3) 661 #define IXL_AQ_LINK_SPEED_40GB (1 << 4) 662 #define IXL_AQ_LINK_SPEED_25GB (1 << 6) 663 uint8_t link_info; 664 #define IXL_AQ_LINK_UP_FUNCTION 0x01 665 #define IXL_AQ_LINK_FAULT 0x02 666 #define IXL_AQ_LINK_FAULT_TX 0x04 667 #define IXL_AQ_LINK_FAULT_RX 0x08 668 #define IXL_AQ_LINK_FAULT_REMOTE 0x10 669 #define IXL_AQ_LINK_UP_PORT 0x20 670 #define IXL_AQ_MEDIA_AVAILABLE 0x40 671 #define IXL_AQ_SIGNAL_DETECT 0x80 672 uint8_t an_info; 673 #define IXL_AQ_AN_COMPLETED 0x01 674 #define IXL_AQ_LP_AN_ABILITY 0x02 675 #define IXL_AQ_PD_FAULT 0x04 676 #define IXL_AQ_FEC_EN 0x08 677 #define IXL_AQ_PHY_LOW_POWER 0x10 678 #define IXL_AQ_LINK_PAUSE_TX 0x20 679 #define IXL_AQ_LINK_PAUSE_RX 0x40 680 #define IXL_AQ_QUALIFIED_MODULE 0x80 681 682 uint8_t ext_info; 683 #define IXL_AQ_LINK_PHY_TEMP_ALARM 0x01 684 #define IXL_AQ_LINK_XCESSIVE_ERRORS 0x02 685 #define IXL_AQ_LINK_TX_SHIFT 0x02 686 #define IXL_AQ_LINK_TX_MASK (0x03 << IXL_AQ_LINK_TX_SHIFT) 687 #define IXL_AQ_LINK_TX_ACTIVE 0x00 688 #define IXL_AQ_LINK_TX_DRAINED 0x01 689 #define IXL_AQ_LINK_TX_FLUSHED 0x03 690 #define IXL_AQ_LINK_FORCED_40G 0x10 691 /* 25G Error Codes */ 692 #define IXL_AQ_25G_NO_ERR 0X00 693 #define IXL_AQ_25G_NOT_PRESENT 0X01 694 #define IXL_AQ_25G_NVM_CRC_ERR 0X02 695 #define IXL_AQ_25G_SBUS_UCODE_ERR 0X03 696 #define IXL_AQ_25G_SERDES_UCODE_ERR 0X04 697 #define IXL_AQ_25G_NIMB_UCODE_ERR 0X05 698 uint8_t loopback; 699 uint16_t max_frame_size; 700 701 uint8_t config; 702 #define IXL_AQ_CONFIG_FEC_KR_ENA 0x01 703 #define IXL_AQ_CONFIG_FEC_RS_ENA 0x02 704 #define IXL_AQ_CONFIG_CRC_ENA 0x04 705 #define IXL_AQ_CONFIG_PACING_MASK 0x78 706 uint8_t power_desc; 707 #define IXL_AQ_LINK_POWER_CLASS_1 0x00 708 #define IXL_AQ_LINK_POWER_CLASS_2 0x01 709 #define IXL_AQ_LINK_POWER_CLASS_3 0x02 710 #define IXL_AQ_LINK_POWER_CLASS_4 0x03 711 #define IXL_AQ_PWR_CLASS_MASK 0x03 712 713 uint8_t reserved[4]; 714 } __packed __aligned(4); 715 /* event mask command flags for param[2] */ 716 #define IXL_AQ_PHY_EV_MASK 0x3ff 717 #define IXL_AQ_PHY_EV_LINK_UPDOWN (1 << 1) 718 #define IXL_AQ_PHY_EV_MEDIA_NA (1 << 2) 719 #define IXL_AQ_PHY_EV_LINK_FAULT (1 << 3) 720 #define IXL_AQ_PHY_EV_PHY_TEMP_ALARM (1 << 4) 721 #define IXL_AQ_PHY_EV_EXCESS_ERRORS (1 << 5) 722 #define IXL_AQ_PHY_EV_SIGNAL_DETECT (1 << 6) 723 #define IXL_AQ_PHY_EV_AN_COMPLETED (1 << 7) 724 #define IXL_AQ_PHY_EV_MODULE_QUAL_FAIL (1 << 8) 725 #define IXL_AQ_PHY_EV_PORT_TX_SUSPENDED (1 << 9) 726 727 struct ixl_aq_rss_lut { /* 722 */ 728 #define IXL_AQ_SET_RSS_LUT_VSI_VALID (1 << 15) 729 #define IXL_AQ_SET_RSS_LUT_VSI_ID_SHIFT 0 730 #define IXL_AQ_SET_RSS_LUT_VSI_ID_MASK \ 731 (0x3FF << IXL_AQ_SET_RSS_LUT_VSI_ID_SHIFT) 732 733 uint16_t vsi_number; 734 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 735 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_MASK \ 736 (0x1 << IXL_AQ_SET_RSS_LUT_TABLE_TYPE_SHIFT) 737 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_VSI 0 738 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_PF 1 739 uint16_t flags; 740 uint8_t _reserved[4]; 741 uint32_t addr_hi; 742 uint32_t addr_lo; 743 } __packed __aligned(16); 744 745 struct ixl_aq_get_set_rss_key { /* 722 */ 746 #define IXL_AQ_SET_RSS_KEY_VSI_VALID (1 << 15) 747 #define IXL_AQ_SET_RSS_KEY_VSI_ID_SHIFT 0 748 #define IXL_AQ_SET_RSS_KEY_VSI_ID_MASK \ 749 (0x3FF << IXL_AQ_SET_RSS_KEY_VSI_ID_SHIFT) 750 uint16_t vsi_number; 751 uint8_t _reserved[6]; 752 uint32_t addr_hi; 753 uint32_t addr_lo; 754 } __packed __aligned(16); 755 756 /* aq response codes */ 757 #define IXL_AQ_RC_OK 0 /* success */ 758 #define IXL_AQ_RC_EPERM 1 /* Operation not permitted */ 759 #define IXL_AQ_RC_ENOENT 2 /* No such element */ 760 #define IXL_AQ_RC_ESRCH 3 /* Bad opcode */ 761 #define IXL_AQ_RC_EINTR 4 /* operation interrupted */ 762 #define IXL_AQ_RC_EIO 5 /* I/O error */ 763 #define IXL_AQ_RC_ENXIO 6 /* No such resource */ 764 #define IXL_AQ_RC_E2BIG 7 /* Arg too long */ 765 #define IXL_AQ_RC_EAGAIN 8 /* Try again */ 766 #define IXL_AQ_RC_ENOMEM 9 /* Out of memory */ 767 #define IXL_AQ_RC_EACCES 10 /* Permission denied */ 768 #define IXL_AQ_RC_EFAULT 11 /* Bad address */ 769 #define IXL_AQ_RC_EBUSY 12 /* Device or resource busy */ 770 #define IXL_AQ_RC_EEXIST 13 /* object already exists */ 771 #define IXL_AQ_RC_EINVAL 14 /* invalid argument */ 772 #define IXL_AQ_RC_ENOTTY 15 /* not a typewriter */ 773 #define IXL_AQ_RC_ENOSPC 16 /* No space or alloc failure */ 774 #define IXL_AQ_RC_ENOSYS 17 /* function not implemented */ 775 #define IXL_AQ_RC_ERANGE 18 /* parameter out of range */ 776 #define IXL_AQ_RC_EFLUSHED 19 /* cmd flushed due to prev error */ 777 #define IXL_AQ_RC_BAD_ADDR 20 /* contains a bad pointer */ 778 #define IXL_AQ_RC_EMODE 21 /* not allowed in current mode */ 779 #define IXL_AQ_RC_EFBIG 22 /* file too large */ 780 781 struct ixl_tx_desc { 782 uint64_t addr; 783 uint64_t cmd; 784 #define IXL_TX_DESC_DTYPE_SHIFT 0 785 #define IXL_TX_DESC_DTYPE_MASK (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 786 #define IXL_TX_DESC_DTYPE_DATA (0x0ULL << IXL_TX_DESC_DTYPE_SHIFT) 787 #define IXL_TX_DESC_DTYPE_NOP (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 788 #define IXL_TX_DESC_DTYPE_CONTEXT (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 789 #define IXL_TX_DESC_DTYPE_FCOE_CTX (0x2ULL << IXL_TX_DESC_DTYPE_SHIFT) 790 #define IXL_TX_DESC_DTYPE_FD (0x8ULL << IXL_TX_DESC_DTYPE_SHIFT) 791 #define IXL_TX_DESC_DTYPE_DDP_CTX (0x9ULL << IXL_TX_DESC_DTYPE_SHIFT) 792 #define IXL_TX_DESC_DTYPE_FLEX_DATA (0xbULL << IXL_TX_DESC_DTYPE_SHIFT) 793 #define IXL_TX_DESC_DTYPE_FLEX_CTX_1 (0xcULL << IXL_TX_DESC_DTYPE_SHIFT) 794 #define IXL_TX_DESC_DTYPE_FLEX_CTX_2 (0xdULL << IXL_TX_DESC_DTYPE_SHIFT) 795 #define IXL_TX_DESC_DTYPE_DONE (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 796 797 #define IXL_TX_DESC_CMD_SHIFT 4 798 #define IXL_TX_DESC_CMD_MASK (0x3ffULL << IXL_TX_DESC_CMD_SHIFT) 799 #define IXL_TX_DESC_CMD_EOP (0x001 << IXL_TX_DESC_CMD_SHIFT) 800 #define IXL_TX_DESC_CMD_RS (0x002 << IXL_TX_DESC_CMD_SHIFT) 801 #define IXL_TX_DESC_CMD_ICRC (0x004 << IXL_TX_DESC_CMD_SHIFT) 802 #define IXL_TX_DESC_CMD_IL2TAG1 (0x008 << IXL_TX_DESC_CMD_SHIFT) 803 #define IXL_TX_DESC_CMD_DUMMY (0x010 << IXL_TX_DESC_CMD_SHIFT) 804 #define IXL_TX_DESC_CMD_IIPT_MASK (0x060 << IXL_TX_DESC_CMD_SHIFT) 805 #define IXL_TX_DESC_CMD_IIPT_NONIP (0x000 << IXL_TX_DESC_CMD_SHIFT) 806 #define IXL_TX_DESC_CMD_IIPT_IPV6 (0x020 << IXL_TX_DESC_CMD_SHIFT) 807 #define IXL_TX_DESC_CMD_IIPT_IPV4 (0x040 << IXL_TX_DESC_CMD_SHIFT) 808 #define IXL_TX_DESC_CMD_IIPT_IPV4_CSUM (0x060 << IXL_TX_DESC_CMD_SHIFT) 809 #define IXL_TX_DESC_CMD_FCOET (0x080 << IXL_TX_DESC_CMD_SHIFT) 810 #define IXL_TX_DESC_CMD_L4T_EOFT_MASK (0x300 << IXL_TX_DESC_CMD_SHIFT) 811 #define IXL_TX_DESC_CMD_L4T_EOFT_UNK (0x000 << IXL_TX_DESC_CMD_SHIFT) 812 #define IXL_TX_DESC_CMD_L4T_EOFT_TCP (0x100 << IXL_TX_DESC_CMD_SHIFT) 813 #define IXL_TX_DESC_CMD_L4T_EOFT_SCTP (0x200 << IXL_TX_DESC_CMD_SHIFT) 814 #define IXL_TX_DESC_CMD_L4T_EOFT_UDP (0x300 << IXL_TX_DESC_CMD_SHIFT) 815 816 #define IXL_TX_DESC_MACLEN_SHIFT 16 817 #define IXL_TX_DESC_MACLEN_MASK (0x7fULL << IXL_TX_DESC_MACLEN_SHIFT) 818 #define IXL_TX_DESC_IPLEN_SHIFT 23 819 #define IXL_TX_DESC_IPLEN_MASK (0x7fULL << IXL_TX_DESC_IPLEN_SHIFT) 820 #define IXL_TX_DESC_L4LEN_SHIFT 30 821 #define IXL_TX_DESC_L4LEN_MASK (0xfULL << IXL_TX_DESC_L4LEN_SHIFT) 822 #define IXL_TX_DESC_FCLEN_SHIFT 30 823 #define IXL_TX_DESC_FCLEN_MASK (0xfULL << IXL_TX_DESC_FCLEN_SHIFT) 824 825 #define IXL_TX_DESC_BSIZE_SHIFT 34 826 #define IXL_TX_DESC_BSIZE_MAX 0x3fffULL 827 #define IXL_TX_DESC_BSIZE_MASK \ 828 (IXL_TX_DESC_BSIZE_MAX << IXL_TX_DESC_BSIZE_SHIFT) 829 830 #define IXL_TX_DESC_L2TAG1_SHIFT 48 831 } __packed __aligned(16); 832 833 struct ixl_rx_rd_desc_16 { 834 uint64_t paddr; /* packet addr */ 835 uint64_t haddr; /* header addr */ 836 } __packed __aligned(16); 837 838 struct ixl_rx_rd_desc_32 { 839 uint64_t paddr; /* packet addr */ 840 uint64_t haddr; /* header addr */ 841 uint64_t _reserved1; 842 uint64_t _reserved2; 843 } __packed __aligned(16); 844 845 struct ixl_rx_wb_desc_16 { 846 uint16_t _reserved1; 847 uint16_t l2tag1; 848 uint32_t filter_status; 849 uint64_t qword1; 850 #define IXL_RX_DESC_DD (1 << 0) 851 #define IXL_RX_DESC_EOP (1 << 1) 852 #define IXL_RX_DESC_L2TAG1P (1 << 2) 853 #define IXL_RX_DESC_L3L4P (1 << 3) 854 #define IXL_RX_DESC_CRCP (1 << 4) 855 #define IXL_RX_DESC_TSYNINDX_SHIFT 5 /* TSYNINDX */ 856 #define IXL_RX_DESC_TSYNINDX_MASK (7 << IXL_RX_DESC_TSYNINDX_SHIFT) 857 #define IXL_RX_DESC_UMB_SHIFT 9 858 #define IXL_RX_DESC_UMB_MASK (0x3 << IXL_RX_DESC_UMB_SHIFT) 859 #define IXL_RX_DESC_UMB_UCAST (0x0 << IXL_RX_DESC_UMB_SHIFT) 860 #define IXL_RX_DESC_UMB_MCAST (0x1 << IXL_RX_DESC_UMB_SHIFT) 861 #define IXL_RX_DESC_UMB_BCAST (0x2 << IXL_RX_DESC_UMB_SHIFT) 862 #define IXL_RX_DESC_UMB_MIRROR (0x3 << IXL_RX_DESC_UMB_SHIFT) 863 #define IXL_RX_DESC_FLM (1 << 11) 864 #define IXL_RX_DESC_FLTSTAT_SHIFT 12 865 #define IXL_RX_DESC_FLTSTAT_MASK (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 866 #define IXL_RX_DESC_FLTSTAT_NODATA (0x0 << IXL_RX_DESC_FLTSTAT_SHIFT) 867 #define IXL_RX_DESC_FLTSTAT_FDFILTID (0x1 << IXL_RX_DESC_FLTSTAT_SHIFT) 868 #define IXL_RX_DESC_FLTSTAT_RSS (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 869 #define IXL_RX_DESC_LPBK (1 << 14) 870 #define IXL_RX_DESC_IPV6EXTADD (1 << 15) 871 #define IXL_RX_DESC_INT_UDP_0 (1 << 18) 872 873 #define IXL_RX_DESC_RXE (1 << 19) 874 #define IXL_RX_DESC_HBO (1 << 21) 875 #define IXL_RX_DESC_IPE (1 << 22) 876 #define IXL_RX_DESC_L4E (1 << 23) 877 #define IXL_RX_DESC_EIPE (1 << 24) 878 #define IXL_RX_DESC_OVERSIZE (1 << 25) 879 880 #define IXL_RX_DESC_PTYPE_SHIFT 30 881 #define IXL_RX_DESC_PTYPE_MASK (0xffULL << IXL_RX_DESC_PTYPE_SHIFT) 882 883 #define IXL_RX_DESC_PLEN_SHIFT 38 884 #define IXL_RX_DESC_PLEN_MASK (0x3fffULL << IXL_RX_DESC_PLEN_SHIFT) 885 #define IXL_RX_DESC_HLEN_SHIFT 42 886 #define IXL_RX_DESC_HLEN_MASK (0x7ffULL << IXL_RX_DESC_HLEN_SHIFT) 887 } __packed __aligned(16); 888 889 struct ixl_rx_wb_desc_32 { 890 uint64_t qword0; 891 uint64_t qword1; 892 uint64_t qword2; 893 uint64_t qword3; 894 } __packed __aligned(16); 895 896 #define IXL_TX_PKT_DESCS 8 897 #define IXL_TX_QUEUE_ALIGN 128 898 #define IXL_RX_QUEUE_ALIGN 128 899 900 #define IXL_HARDMTU 9712 /* 9726 - ETHER_HDR_LEN */ 901 902 #define IXL_PCIREG PCI_MAPREG_START 903 904 #define IXL_ITR0 0x0 905 #define IXL_ITR1 0x1 906 #define IXL_ITR2 0x2 907 #define IXL_NOITR 0x2 908 909 #define IXL_AQ_NUM 256 910 #define IXL_AQ_MASK (IXL_AQ_NUM - 1) 911 #define IXL_AQ_ALIGN 64 /* lol */ 912 #define IXL_AQ_BUFLEN 4096 913 914 /* Packet Classifier Types for filters */ 915 /* bits 0-28 are reserved for future use */ 916 #define IXL_PCT_NONF_IPV4_UDP_UCAST (1ULL << 29) /* 722 */ 917 #define IXL_PCT_NONF_IPV4_UDP_MCAST (1ULL << 30) /* 722 */ 918 #define IXL_PCT_NONF_IPV4_UDP (1ULL << 31) 919 #define IXL_PCT_NONF_IPV4_TCP_SYN_NOACK (1ULL << 32) /* 722 */ 920 #define IXL_PCT_NONF_IPV4_TCP (1ULL << 33) 921 #define IXL_PCT_NONF_IPV4_SCTP (1ULL << 34) 922 #define IXL_PCT_NONF_IPV4_OTHER (1ULL << 35) 923 #define IXL_PCT_FRAG_IPV4 (1ULL << 36) 924 /* bits 37-38 are reserved for future use */ 925 #define IXL_PCT_NONF_IPV6_UDP_UCAST (1ULL << 39) /* 722 */ 926 #define IXL_PCT_NONF_IPV6_UDP_MCAST (1ULL << 40) /* 722 */ 927 #define IXL_PCT_NONF_IPV6_UDP (1ULL << 41) 928 #define IXL_PCT_NONF_IPV6_TCP_SYN_NOACK (1ULL << 42) /* 722 */ 929 #define IXL_PCT_NONF_IPV6_TCP (1ULL << 43) 930 #define IXL_PCT_NONF_IPV6_SCTP (1ULL << 44) 931 #define IXL_PCT_NONF_IPV6_OTHER (1ULL << 45) 932 #define IXL_PCT_FRAG_IPV6 (1ULL << 46) 933 /* bit 47 is reserved for future use */ 934 #define IXL_PCT_FCOE_OX (1ULL << 48) 935 #define IXL_PCT_FCOE_RX (1ULL << 49) 936 #define IXL_PCT_FCOE_OTHER (1ULL << 50) 937 /* bits 51-62 are reserved for future use */ 938 #define IXL_PCT_L2_PAYLOAD (1ULL << 63) 939 940 #define IXL_RSS_HENA_BASE_DEFAULT \ 941 IXL_PCT_NONF_IPV4_UDP | \ 942 IXL_PCT_NONF_IPV4_TCP | \ 943 IXL_PCT_NONF_IPV4_SCTP | \ 944 IXL_PCT_NONF_IPV4_OTHER | \ 945 IXL_PCT_FRAG_IPV4 | \ 946 IXL_PCT_NONF_IPV6_UDP | \ 947 IXL_PCT_NONF_IPV6_TCP | \ 948 IXL_PCT_NONF_IPV6_SCTP | \ 949 IXL_PCT_NONF_IPV6_OTHER | \ 950 IXL_PCT_FRAG_IPV6 | \ 951 IXL_PCT_L2_PAYLOAD 952 953 #define IXL_RSS_HENA_BASE_710 IXL_RSS_HENA_BASE_DEFAULT 954 #define IXL_RSS_HENA_BASE_722 IXL_RSS_HENA_BASE_DEFAULT | \ 955 IXL_PCT_NONF_IPV4_UDP_UCAST | \ 956 IXL_PCT_NONF_IPV4_UDP_MCAST | \ 957 IXL_PCT_NONF_IPV6_UDP_UCAST | \ 958 IXL_PCT_NONF_IPV6_UDP_MCAST | \ 959 IXL_PCT_NONF_IPV4_TCP_SYN_NOACK | \ 960 IXL_PCT_NONF_IPV6_TCP_SYN_NOACK 961 962 #define IXL_HMC_ROUNDUP 512 963 #define IXL_HMC_PGSIZE 4096 964 #define IXL_HMC_DVASZ sizeof(uint64_t) 965 #define IXL_HMC_PGS (IXL_HMC_PGSIZE / IXL_HMC_DVASZ) 966 #define IXL_HMC_L2SZ (IXL_HMC_PGSIZE * IXL_HMC_PGS) 967 #define IXL_HMC_PDVALID 1ULL 968 969 struct ixl_aq_regs { 970 bus_size_t atq_tail; 971 bus_size_t atq_head; 972 bus_size_t atq_len; 973 bus_size_t atq_bal; 974 bus_size_t atq_bah; 975 976 bus_size_t arq_tail; 977 bus_size_t arq_head; 978 bus_size_t arq_len; 979 bus_size_t arq_bal; 980 bus_size_t arq_bah; 981 982 uint32_t atq_len_enable; 983 uint32_t atq_tail_mask; 984 uint32_t atq_head_mask; 985 986 uint32_t arq_len_enable; 987 uint32_t arq_tail_mask; 988 uint32_t arq_head_mask; 989 }; 990 991 struct ixl_phy_type { 992 uint64_t phy_type; 993 uint64_t ifm_type; 994 }; 995 996 struct ixl_speed_type { 997 uint8_t dev_speed; 998 uint64_t net_speed; 999 }; 1000 1001 struct ixl_aq_buf { 1002 SIMPLEQ_ENTRY(ixl_aq_buf) 1003 aqb_entry; 1004 void *aqb_data; 1005 bus_dmamap_t aqb_map; 1006 }; 1007 SIMPLEQ_HEAD(ixl_aq_bufs, ixl_aq_buf); 1008 1009 struct ixl_dmamem { 1010 bus_dmamap_t ixm_map; 1011 bus_dma_segment_t ixm_seg; 1012 int ixm_nsegs; 1013 size_t ixm_size; 1014 caddr_t ixm_kva; 1015 }; 1016 #define IXL_DMA_MAP(_ixm) ((_ixm)->ixm_map) 1017 #define IXL_DMA_DVA(_ixm) ((_ixm)->ixm_map->dm_segs[0].ds_addr) 1018 #define IXL_DMA_KVA(_ixm) ((void *)(_ixm)->ixm_kva) 1019 #define IXL_DMA_LEN(_ixm) ((_ixm)->ixm_size) 1020 1021 struct ixl_hmc_entry { 1022 uint64_t hmc_base; 1023 uint32_t hmc_count; 1024 uint32_t hmc_size; 1025 }; 1026 1027 #define IXL_HMC_LAN_TX 0 1028 #define IXL_HMC_LAN_RX 1 1029 #define IXL_HMC_FCOE_CTX 2 1030 #define IXL_HMC_FCOE_FILTER 3 1031 #define IXL_HMC_COUNT 4 1032 1033 struct ixl_hmc_pack { 1034 uint16_t offset; 1035 uint16_t width; 1036 uint16_t lsb; 1037 }; 1038 1039 /* 1040 * these hmc objects have weird sizes and alignments, so these are abstract 1041 * representations of them that are nice for c to populate. 1042 * 1043 * the packing code relies on little-endian values being stored in the fields, 1044 * no high bits in the fields being set, and the fields must be packed in the 1045 * same order as they are in the ctx structure. 1046 */ 1047 1048 struct ixl_hmc_rxq { 1049 uint16_t head; 1050 uint8_t cpuid; 1051 uint64_t base; 1052 #define IXL_HMC_RXQ_BASE_UNIT 128 1053 uint16_t qlen; 1054 uint16_t dbuff; 1055 #define IXL_HMC_RXQ_DBUFF_UNIT 128 1056 uint8_t hbuff; 1057 #define IXL_HMC_RXQ_HBUFF_UNIT 64 1058 uint8_t dtype; 1059 #define IXL_HMC_RXQ_DTYPE_NOSPLIT 0x0 1060 #define IXL_HMC_RXQ_DTYPE_HSPLIT 0x1 1061 #define IXL_HMC_RXQ_DTYPE_SPLIT_ALWAYS 0x2 1062 uint8_t dsize; 1063 #define IXL_HMC_RXQ_DSIZE_16 0 1064 #define IXL_HMC_RXQ_DSIZE_32 1 1065 uint8_t crcstrip; 1066 uint8_t fc_ena; 1067 uint8_t l2tsel; 1068 #define IXL_HMC_RXQ_L2TSEL_2ND_TAG_TO_L2TAG1 \ 1069 0 1070 #define IXL_HMC_RXQ_L2TSEL_1ST_TAG_TO_L2TAG1 \ 1071 1 1072 uint8_t hsplit_0; 1073 uint8_t hsplit_1; 1074 uint8_t showiv; 1075 uint16_t rxmax; 1076 uint8_t tphrdesc_ena; 1077 uint8_t tphwdesc_ena; 1078 uint8_t tphdata_ena; 1079 uint8_t tphhead_ena; 1080 uint8_t lrxqthresh; 1081 uint8_t prefena; 1082 }; 1083 1084 static const struct ixl_hmc_pack ixl_hmc_pack_rxq[] = { 1085 { offsetof(struct ixl_hmc_rxq, head), 13, 0 }, 1086 { offsetof(struct ixl_hmc_rxq, cpuid), 8, 13 }, 1087 { offsetof(struct ixl_hmc_rxq, base), 57, 32 }, 1088 { offsetof(struct ixl_hmc_rxq, qlen), 13, 89 }, 1089 { offsetof(struct ixl_hmc_rxq, dbuff), 7, 102 }, 1090 { offsetof(struct ixl_hmc_rxq, hbuff), 5, 109 }, 1091 { offsetof(struct ixl_hmc_rxq, dtype), 2, 114 }, 1092 { offsetof(struct ixl_hmc_rxq, dsize), 1, 116 }, 1093 { offsetof(struct ixl_hmc_rxq, crcstrip), 1, 117 }, 1094 { offsetof(struct ixl_hmc_rxq, fc_ena), 1, 118 }, 1095 { offsetof(struct ixl_hmc_rxq, l2tsel), 1, 119 }, 1096 { offsetof(struct ixl_hmc_rxq, hsplit_0), 4, 120 }, 1097 { offsetof(struct ixl_hmc_rxq, hsplit_1), 2, 124 }, 1098 { offsetof(struct ixl_hmc_rxq, showiv), 1, 127 }, 1099 { offsetof(struct ixl_hmc_rxq, rxmax), 14, 174 }, 1100 { offsetof(struct ixl_hmc_rxq, tphrdesc_ena), 1, 193 }, 1101 { offsetof(struct ixl_hmc_rxq, tphwdesc_ena), 1, 194 }, 1102 { offsetof(struct ixl_hmc_rxq, tphdata_ena), 1, 195 }, 1103 { offsetof(struct ixl_hmc_rxq, tphhead_ena), 1, 196 }, 1104 { offsetof(struct ixl_hmc_rxq, lrxqthresh), 3, 198 }, 1105 { offsetof(struct ixl_hmc_rxq, prefena), 1, 201 }, 1106 }; 1107 1108 #define IXL_HMC_RXQ_MINSIZE (201 + 1) 1109 1110 struct ixl_hmc_txq { 1111 uint16_t head; 1112 uint8_t new_context; 1113 uint64_t base; 1114 #define IXL_HMC_TXQ_BASE_UNIT 128 1115 uint8_t fc_ena; 1116 uint8_t timesync_ena; 1117 uint8_t fd_ena; 1118 uint8_t alt_vlan_ena; 1119 uint16_t thead_wb; 1120 uint8_t cpuid; 1121 uint8_t head_wb_ena; 1122 #define IXL_HMC_TXQ_DESC_WB 0 1123 #define IXL_HMC_TXQ_HEAD_WB 1 1124 uint16_t qlen; 1125 uint8_t tphrdesc_ena; 1126 uint8_t tphrpacket_ena; 1127 uint8_t tphwdesc_ena; 1128 uint64_t head_wb_addr; 1129 uint32_t crc; 1130 uint16_t rdylist; 1131 uint8_t rdylist_act; 1132 }; 1133 1134 static const struct ixl_hmc_pack ixl_hmc_pack_txq[] = { 1135 { offsetof(struct ixl_hmc_txq, head), 13, 0 }, 1136 { offsetof(struct ixl_hmc_txq, new_context), 1, 30 }, 1137 { offsetof(struct ixl_hmc_txq, base), 57, 32 }, 1138 { offsetof(struct ixl_hmc_txq, fc_ena), 1, 89 }, 1139 { offsetof(struct ixl_hmc_txq, timesync_ena), 1, 90 }, 1140 { offsetof(struct ixl_hmc_txq, fd_ena), 1, 91 }, 1141 { offsetof(struct ixl_hmc_txq, alt_vlan_ena), 1, 92 }, 1142 { offsetof(struct ixl_hmc_txq, cpuid), 8, 96 }, 1143 /* line 1 */ 1144 { offsetof(struct ixl_hmc_txq, thead_wb), 13, 0 + 128 }, 1145 { offsetof(struct ixl_hmc_txq, head_wb_ena), 1, 32 + 128 }, 1146 { offsetof(struct ixl_hmc_txq, qlen), 13, 33 + 128 }, 1147 { offsetof(struct ixl_hmc_txq, tphrdesc_ena), 1, 46 + 128 }, 1148 { offsetof(struct ixl_hmc_txq, tphrpacket_ena), 1, 47 + 128 }, 1149 { offsetof(struct ixl_hmc_txq, tphwdesc_ena), 1, 48 + 128 }, 1150 { offsetof(struct ixl_hmc_txq, head_wb_addr), 64, 64 + 128 }, 1151 /* line 7 */ 1152 { offsetof(struct ixl_hmc_txq, crc), 32, 0 + (7*128) }, 1153 { offsetof(struct ixl_hmc_txq, rdylist), 10, 84 + (7*128) }, 1154 { offsetof(struct ixl_hmc_txq, rdylist_act), 1, 94 + (7*128) }, 1155 }; 1156 1157 #define IXL_HMC_TXQ_MINSIZE (94 + (7*128) + 1) 1158 1159 struct ixl_rss_key { 1160 uint32_t key[13]; 1161 }; 1162 1163 struct ixl_rss_lut_128 { 1164 uint32_t entries[128 / sizeof(uint32_t)]; 1165 }; 1166 1167 struct ixl_rss_lut_512 { 1168 uint32_t entries[512 / sizeof(uint32_t)]; 1169 }; 1170 1171 /* driver structures */ 1172 1173 struct ixl_vector; 1174 struct ixl_chip; 1175 1176 struct ixl_tx_map { 1177 struct mbuf *txm_m; 1178 bus_dmamap_t txm_map; 1179 unsigned int txm_eop; 1180 }; 1181 1182 struct ixl_tx_ring { 1183 struct ixl_softc *txr_sc; 1184 struct ixl_vector *txr_vector; 1185 struct ifqueue *txr_ifq; 1186 1187 unsigned int txr_prod; 1188 unsigned int txr_cons; 1189 1190 struct ixl_tx_map *txr_maps; 1191 struct ixl_dmamem txr_mem; 1192 1193 bus_size_t txr_tail; 1194 unsigned int txr_qid; 1195 } __aligned(CACHE_LINE_SIZE); 1196 1197 struct ixl_rx_map { 1198 struct mbuf *rxm_m; 1199 bus_dmamap_t rxm_map; 1200 }; 1201 1202 struct ixl_rx_ring { 1203 struct ixl_softc *rxr_sc; 1204 struct ixl_vector *rxr_vector; 1205 struct ifiqueue *rxr_ifiq; 1206 1207 struct if_rxring rxr_acct; 1208 struct timeout rxr_refill; 1209 1210 unsigned int rxr_prod; 1211 unsigned int rxr_cons; 1212 1213 struct ixl_rx_map *rxr_maps; 1214 struct ixl_dmamem rxr_mem; 1215 1216 struct mbuf *rxr_m_head; 1217 struct mbuf **rxr_m_tail; 1218 1219 bus_size_t rxr_tail; 1220 unsigned int rxr_qid; 1221 } __aligned(CACHE_LINE_SIZE); 1222 1223 struct ixl_atq { 1224 struct ixl_aq_desc iatq_desc; 1225 void *iatq_arg; 1226 void (*iatq_fn)(struct ixl_softc *, void *); 1227 }; 1228 SIMPLEQ_HEAD(ixl_atq_list, ixl_atq); 1229 1230 struct ixl_vector { 1231 struct ixl_softc *iv_sc; 1232 struct ixl_rx_ring *iv_rxr; 1233 struct ixl_tx_ring *iv_txr; 1234 int iv_qid; 1235 void *iv_ihc; 1236 char iv_name[16]; 1237 } __aligned(CACHE_LINE_SIZE); 1238 1239 struct ixl_softc { 1240 struct device sc_dev; 1241 const struct ixl_chip *sc_chip; 1242 struct arpcom sc_ac; 1243 struct ifmedia sc_media; 1244 uint64_t sc_media_status; 1245 uint64_t sc_media_active; 1246 1247 pci_chipset_tag_t sc_pc; 1248 pci_intr_handle_t sc_ih; 1249 void *sc_ihc; 1250 pcitag_t sc_tag; 1251 1252 bus_dma_tag_t sc_dmat; 1253 bus_space_tag_t sc_memt; 1254 bus_space_handle_t sc_memh; 1255 bus_size_t sc_mems; 1256 1257 uint16_t sc_api_major; 1258 uint16_t sc_api_minor; 1259 uint8_t sc_pf_id; 1260 uint16_t sc_uplink_seid; /* le */ 1261 uint16_t sc_downlink_seid; /* le */ 1262 uint16_t sc_veb_seid; /* le */ 1263 uint16_t sc_vsi_number; /* le */ 1264 uint16_t sc_seid; 1265 unsigned int sc_base_queue; 1266 unsigned int sc_port; 1267 1268 struct ixl_dmamem sc_scratch; 1269 1270 const struct ixl_aq_regs * 1271 sc_aq_regs; 1272 1273 struct ixl_dmamem sc_atq; 1274 unsigned int sc_atq_prod; 1275 unsigned int sc_atq_cons; 1276 1277 struct ixl_dmamem sc_arq; 1278 struct task sc_arq_task; 1279 struct ixl_aq_bufs sc_arq_idle; 1280 struct ixl_aq_bufs sc_arq_live; 1281 struct if_rxring sc_arq_ring; 1282 unsigned int sc_arq_prod; 1283 unsigned int sc_arq_cons; 1284 1285 struct mutex sc_link_state_mtx; 1286 struct task sc_link_state_task; 1287 struct ixl_atq sc_link_state_atq; 1288 1289 struct ixl_dmamem sc_hmc_sd; 1290 struct ixl_dmamem sc_hmc_pd; 1291 struct ixl_hmc_entry sc_hmc_entries[IXL_HMC_COUNT]; 1292 1293 unsigned int sc_tx_ring_ndescs; 1294 unsigned int sc_rx_ring_ndescs; 1295 unsigned int sc_nqueues; /* 1 << sc_nqueues */ 1296 1297 struct intrmap *sc_intrmap; 1298 struct ixl_vector *sc_vectors; 1299 1300 struct rwlock sc_cfg_lock; 1301 unsigned int sc_dead; 1302 1303 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 1304 1305 #if NKSTAT > 0 1306 struct mutex sc_kstat_mtx; 1307 struct timeout sc_kstat_tmo; 1308 struct kstat *sc_port_kstat; 1309 struct kstat *sc_vsi_kstat; 1310 #endif 1311 }; 1312 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) 1313 1314 #define delaymsec(_ms) delay(1000 * (_ms)) 1315 1316 static void ixl_clear_hw(struct ixl_softc *); 1317 static int ixl_pf_reset(struct ixl_softc *); 1318 1319 static int ixl_dmamem_alloc(struct ixl_softc *, struct ixl_dmamem *, 1320 bus_size_t, u_int); 1321 static void ixl_dmamem_free(struct ixl_softc *, struct ixl_dmamem *); 1322 1323 static int ixl_arq_fill(struct ixl_softc *); 1324 static void ixl_arq_unfill(struct ixl_softc *); 1325 1326 static int ixl_atq_poll(struct ixl_softc *, struct ixl_aq_desc *, 1327 unsigned int); 1328 static void ixl_atq_set(struct ixl_atq *, 1329 void (*)(struct ixl_softc *, void *), void *); 1330 static void ixl_atq_post(struct ixl_softc *, struct ixl_atq *); 1331 static void ixl_atq_done(struct ixl_softc *); 1332 static void ixl_atq_exec(struct ixl_softc *, struct ixl_atq *, 1333 const char *); 1334 static int ixl_get_version(struct ixl_softc *); 1335 static int ixl_pxe_clear(struct ixl_softc *); 1336 static int ixl_lldp_shut(struct ixl_softc *); 1337 static int ixl_get_mac(struct ixl_softc *); 1338 static int ixl_get_switch_config(struct ixl_softc *); 1339 static int ixl_phy_mask_ints(struct ixl_softc *); 1340 static int ixl_get_phy_types(struct ixl_softc *, uint64_t *); 1341 static int ixl_restart_an(struct ixl_softc *); 1342 static int ixl_hmc(struct ixl_softc *); 1343 static void ixl_hmc_free(struct ixl_softc *); 1344 static int ixl_get_vsi(struct ixl_softc *); 1345 static int ixl_set_vsi(struct ixl_softc *); 1346 static int ixl_get_link_status(struct ixl_softc *); 1347 static int ixl_set_link_status(struct ixl_softc *, 1348 const struct ixl_aq_desc *); 1349 static int ixl_add_macvlan(struct ixl_softc *, uint8_t *, uint16_t, 1350 uint16_t); 1351 static int ixl_remove_macvlan(struct ixl_softc *, uint8_t *, uint16_t, 1352 uint16_t); 1353 static void ixl_link_state_update(void *); 1354 static void ixl_arq(void *); 1355 static void ixl_hmc_pack(void *, const void *, 1356 const struct ixl_hmc_pack *, unsigned int); 1357 1358 static int ixl_get_sffpage(struct ixl_softc *, struct if_sffpage *); 1359 static int ixl_sff_get_byte(struct ixl_softc *, uint8_t, uint32_t, 1360 uint8_t *); 1361 static int ixl_sff_set_byte(struct ixl_softc *, uint8_t, uint32_t, 1362 uint8_t); 1363 1364 static int ixl_match(struct device *, void *, void *); 1365 static void ixl_attach(struct device *, struct device *, void *); 1366 1367 static void ixl_media_add(struct ixl_softc *, uint64_t); 1368 static int ixl_media_change(struct ifnet *); 1369 static void ixl_media_status(struct ifnet *, struct ifmediareq *); 1370 static void ixl_watchdog(struct ifnet *); 1371 static int ixl_ioctl(struct ifnet *, u_long, caddr_t); 1372 static void ixl_start(struct ifqueue *); 1373 static int ixl_intr0(void *); 1374 static int ixl_intr_vector(void *); 1375 static int ixl_up(struct ixl_softc *); 1376 static int ixl_down(struct ixl_softc *); 1377 static int ixl_iff(struct ixl_softc *); 1378 1379 static struct ixl_tx_ring * 1380 ixl_txr_alloc(struct ixl_softc *, unsigned int); 1381 static void ixl_txr_qdis(struct ixl_softc *, struct ixl_tx_ring *, int); 1382 static void ixl_txr_config(struct ixl_softc *, struct ixl_tx_ring *); 1383 static int ixl_txr_enabled(struct ixl_softc *, struct ixl_tx_ring *); 1384 static int ixl_txr_disabled(struct ixl_softc *, struct ixl_tx_ring *); 1385 static void ixl_txr_unconfig(struct ixl_softc *, struct ixl_tx_ring *); 1386 static void ixl_txr_clean(struct ixl_softc *, struct ixl_tx_ring *); 1387 static void ixl_txr_free(struct ixl_softc *, struct ixl_tx_ring *); 1388 static int ixl_txeof(struct ixl_softc *, struct ixl_tx_ring *); 1389 1390 static struct ixl_rx_ring * 1391 ixl_rxr_alloc(struct ixl_softc *, unsigned int); 1392 static void ixl_rxr_config(struct ixl_softc *, struct ixl_rx_ring *); 1393 static int ixl_rxr_enabled(struct ixl_softc *, struct ixl_rx_ring *); 1394 static int ixl_rxr_disabled(struct ixl_softc *, struct ixl_rx_ring *); 1395 static void ixl_rxr_unconfig(struct ixl_softc *, struct ixl_rx_ring *); 1396 static void ixl_rxr_clean(struct ixl_softc *, struct ixl_rx_ring *); 1397 static void ixl_rxr_free(struct ixl_softc *, struct ixl_rx_ring *); 1398 static int ixl_rxeof(struct ixl_softc *, struct ixl_rx_ring *); 1399 static void ixl_rxfill(struct ixl_softc *, struct ixl_rx_ring *); 1400 static void ixl_rxrefill(void *); 1401 static int ixl_rxrinfo(struct ixl_softc *, struct if_rxrinfo *); 1402 static void ixl_rx_checksum(struct mbuf *, uint64_t); 1403 1404 #if NKSTAT > 0 1405 static void ixl_kstat_attach(struct ixl_softc *); 1406 #endif 1407 1408 struct cfdriver ixl_cd = { 1409 NULL, 1410 "ixl", 1411 DV_IFNET, 1412 }; 1413 1414 const struct cfattach ixl_ca = { 1415 sizeof(struct ixl_softc), 1416 ixl_match, 1417 ixl_attach, 1418 }; 1419 1420 static const struct ixl_phy_type ixl_phy_type_map[] = { 1421 { 1ULL << IXL_PHY_TYPE_SGMII, IFM_1000_SGMII }, 1422 { 1ULL << IXL_PHY_TYPE_1000BASE_KX, IFM_1000_KX }, 1423 { 1ULL << IXL_PHY_TYPE_10GBASE_KX4, IFM_10G_KX4 }, 1424 { 1ULL << IXL_PHY_TYPE_10GBASE_KR, IFM_10G_KR }, 1425 { 1ULL << IXL_PHY_TYPE_40GBASE_KR4, IFM_40G_KR4 }, 1426 { 1ULL << IXL_PHY_TYPE_XAUI | 1427 1ULL << IXL_PHY_TYPE_XFI, IFM_10G_CX4 }, 1428 { 1ULL << IXL_PHY_TYPE_SFI, IFM_10G_SFI }, 1429 { 1ULL << IXL_PHY_TYPE_XLAUI | 1430 1ULL << IXL_PHY_TYPE_XLPPI, IFM_40G_XLPPI }, 1431 { 1ULL << IXL_PHY_TYPE_40GBASE_CR4_CU | 1432 1ULL << IXL_PHY_TYPE_40GBASE_CR4, IFM_40G_CR4 }, 1433 { 1ULL << IXL_PHY_TYPE_10GBASE_CR1_CU | 1434 1ULL << IXL_PHY_TYPE_10GBASE_CR1, IFM_10G_CR1 }, 1435 { 1ULL << IXL_PHY_TYPE_10GBASE_AOC, IFM_10G_AOC }, 1436 { 1ULL << IXL_PHY_TYPE_40GBASE_AOC, IFM_40G_AOC }, 1437 { 1ULL << IXL_PHY_TYPE_100BASE_TX, IFM_100_TX }, 1438 { 1ULL << IXL_PHY_TYPE_1000BASE_T_OPTICAL | 1439 1ULL << IXL_PHY_TYPE_1000BASE_T, IFM_1000_T }, 1440 { 1ULL << IXL_PHY_TYPE_10GBASE_T, IFM_10G_T }, 1441 { 1ULL << IXL_PHY_TYPE_10GBASE_SR, IFM_10G_SR }, 1442 { 1ULL << IXL_PHY_TYPE_10GBASE_LR, IFM_10G_LR }, 1443 { 1ULL << IXL_PHY_TYPE_10GBASE_SFPP_CU, IFM_10G_SFP_CU }, 1444 { 1ULL << IXL_PHY_TYPE_40GBASE_SR4, IFM_40G_SR4 }, 1445 { 1ULL << IXL_PHY_TYPE_40GBASE_LR4, IFM_40G_LR4 }, 1446 { 1ULL << IXL_PHY_TYPE_1000BASE_SX, IFM_1000_SX }, 1447 { 1ULL << IXL_PHY_TYPE_1000BASE_LX, IFM_1000_LX }, 1448 { 1ULL << IXL_PHY_TYPE_20GBASE_KR2, IFM_20G_KR2 }, 1449 { 1ULL << IXL_PHY_TYPE_25GBASE_KR, IFM_25G_KR }, 1450 { 1ULL << IXL_PHY_TYPE_25GBASE_CR, IFM_25G_CR }, 1451 { 1ULL << IXL_PHY_TYPE_25GBASE_SR, IFM_25G_SR }, 1452 { 1ULL << IXL_PHY_TYPE_25GBASE_LR, IFM_25G_LR }, 1453 { 1ULL << IXL_PHY_TYPE_25GBASE_AOC, IFM_25G_AOC }, 1454 { 1ULL << IXL_PHY_TYPE_25GBASE_ACC, IFM_25G_CR }, 1455 }; 1456 1457 static const struct ixl_speed_type ixl_speed_type_map[] = { 1458 { IXL_AQ_LINK_SPEED_40GB, IF_Gbps(40) }, 1459 { IXL_AQ_LINK_SPEED_25GB, IF_Gbps(25) }, 1460 { IXL_AQ_LINK_SPEED_10GB, IF_Gbps(10) }, 1461 { IXL_AQ_LINK_SPEED_1GB, IF_Gbps(1) }, 1462 }; 1463 1464 static const struct ixl_aq_regs ixl_pf_aq_regs = { 1465 .atq_tail = I40E_PF_ATQT, 1466 .atq_tail_mask = I40E_PF_ATQT_ATQT_MASK, 1467 .atq_head = I40E_PF_ATQH, 1468 .atq_head_mask = I40E_PF_ATQH_ATQH_MASK, 1469 .atq_len = I40E_PF_ATQLEN, 1470 .atq_bal = I40E_PF_ATQBAL, 1471 .atq_bah = I40E_PF_ATQBAH, 1472 .atq_len_enable = I40E_PF_ATQLEN_ATQENABLE_MASK, 1473 1474 .arq_tail = I40E_PF_ARQT, 1475 .arq_tail_mask = I40E_PF_ARQT_ARQT_MASK, 1476 .arq_head = I40E_PF_ARQH, 1477 .arq_head_mask = I40E_PF_ARQH_ARQH_MASK, 1478 .arq_len = I40E_PF_ARQLEN, 1479 .arq_bal = I40E_PF_ARQBAL, 1480 .arq_bah = I40E_PF_ARQBAH, 1481 .arq_len_enable = I40E_PF_ARQLEN_ARQENABLE_MASK, 1482 }; 1483 1484 #define ixl_rd(_s, _r) \ 1485 bus_space_read_4((_s)->sc_memt, (_s)->sc_memh, (_r)) 1486 #define ixl_wr(_s, _r, _v) \ 1487 bus_space_write_4((_s)->sc_memt, (_s)->sc_memh, (_r), (_v)) 1488 #define ixl_barrier(_s, _r, _l, _o) \ 1489 bus_space_barrier((_s)->sc_memt, (_s)->sc_memh, (_r), (_l), (_o)) 1490 #define ixl_intr_enable(_s) \ 1491 ixl_wr((_s), I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_INTENA_MASK | \ 1492 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | \ 1493 (IXL_NOITR << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)) 1494 1495 #define ixl_nqueues(_sc) (1 << (_sc)->sc_nqueues) 1496 1497 #ifdef __LP64__ 1498 #define ixl_dmamem_hi(_ixm) (uint32_t)(IXL_DMA_DVA(_ixm) >> 32) 1499 #else 1500 #define ixl_dmamem_hi(_ixm) 0 1501 #endif 1502 1503 #define ixl_dmamem_lo(_ixm) (uint32_t)IXL_DMA_DVA(_ixm) 1504 1505 static inline void 1506 ixl_aq_dva(struct ixl_aq_desc *iaq, bus_addr_t addr) 1507 { 1508 #ifdef __LP64__ 1509 htolem32(&iaq->iaq_param[2], addr >> 32); 1510 #else 1511 iaq->iaq_param[2] = htole32(0); 1512 #endif 1513 htolem32(&iaq->iaq_param[3], addr); 1514 } 1515 1516 #if _BYTE_ORDER == _BIG_ENDIAN 1517 #define HTOLE16(_x) (uint16_t)(((_x) & 0xff) << 8 | ((_x) & 0xff00) >> 8) 1518 #else 1519 #define HTOLE16(_x) (_x) 1520 #endif 1521 1522 static struct rwlock ixl_sff_lock = RWLOCK_INITIALIZER("ixlsff"); 1523 1524 /* deal with differences between chips */ 1525 1526 struct ixl_chip { 1527 uint64_t ic_rss_hena; 1528 uint32_t (*ic_rd_ctl)(struct ixl_softc *, uint32_t); 1529 void (*ic_wr_ctl)(struct ixl_softc *, uint32_t, 1530 uint32_t); 1531 1532 int (*ic_set_rss_key)(struct ixl_softc *, 1533 const struct ixl_rss_key *); 1534 int (*ic_set_rss_lut)(struct ixl_softc *, 1535 const struct ixl_rss_lut_128 *); 1536 }; 1537 1538 static inline uint64_t 1539 ixl_rss_hena(struct ixl_softc *sc) 1540 { 1541 return (sc->sc_chip->ic_rss_hena); 1542 } 1543 1544 static inline uint32_t 1545 ixl_rd_ctl(struct ixl_softc *sc, uint32_t r) 1546 { 1547 return ((*sc->sc_chip->ic_rd_ctl)(sc, r)); 1548 } 1549 1550 static inline void 1551 ixl_wr_ctl(struct ixl_softc *sc, uint32_t r, uint32_t v) 1552 { 1553 (*sc->sc_chip->ic_wr_ctl)(sc, r, v); 1554 } 1555 1556 static inline int 1557 ixl_set_rss_key(struct ixl_softc *sc, const struct ixl_rss_key *rsskey) 1558 { 1559 return ((*sc->sc_chip->ic_set_rss_key)(sc, rsskey)); 1560 } 1561 1562 static inline int 1563 ixl_set_rss_lut(struct ixl_softc *sc, const struct ixl_rss_lut_128 *lut) 1564 { 1565 return ((*sc->sc_chip->ic_set_rss_lut)(sc, lut)); 1566 } 1567 1568 /* 710 chip specifics */ 1569 1570 static uint32_t ixl_710_rd_ctl(struct ixl_softc *, uint32_t); 1571 static void ixl_710_wr_ctl(struct ixl_softc *, uint32_t, uint32_t); 1572 static int ixl_710_set_rss_key(struct ixl_softc *, 1573 const struct ixl_rss_key *); 1574 static int ixl_710_set_rss_lut(struct ixl_softc *, 1575 const struct ixl_rss_lut_128 *); 1576 1577 static const struct ixl_chip ixl_710 = { 1578 .ic_rss_hena = IXL_RSS_HENA_BASE_710, 1579 .ic_rd_ctl = ixl_710_rd_ctl, 1580 .ic_wr_ctl = ixl_710_wr_ctl, 1581 .ic_set_rss_key = ixl_710_set_rss_key, 1582 .ic_set_rss_lut = ixl_710_set_rss_lut, 1583 }; 1584 1585 /* 722 chip specifics */ 1586 1587 static uint32_t ixl_722_rd_ctl(struct ixl_softc *, uint32_t); 1588 static void ixl_722_wr_ctl(struct ixl_softc *, uint32_t, uint32_t); 1589 static int ixl_722_set_rss_key(struct ixl_softc *, 1590 const struct ixl_rss_key *); 1591 static int ixl_722_set_rss_lut(struct ixl_softc *, 1592 const struct ixl_rss_lut_128 *); 1593 1594 static const struct ixl_chip ixl_722 = { 1595 .ic_rss_hena = IXL_RSS_HENA_BASE_722, 1596 .ic_rd_ctl = ixl_722_rd_ctl, 1597 .ic_wr_ctl = ixl_722_wr_ctl, 1598 .ic_set_rss_key = ixl_722_set_rss_key, 1599 .ic_set_rss_lut = ixl_722_set_rss_lut, 1600 }; 1601 1602 /* 1603 * 710 chips using an older firmware/API use the same ctl ops as 1604 * 722 chips. or 722 chips use the same ctl ops as 710 chips in early 1605 * firmware/API versions? 1606 */ 1607 1608 static const struct ixl_chip ixl_710_decrepit = { 1609 .ic_rss_hena = IXL_RSS_HENA_BASE_710, 1610 .ic_rd_ctl = ixl_722_rd_ctl, 1611 .ic_wr_ctl = ixl_722_wr_ctl, 1612 .ic_set_rss_key = ixl_710_set_rss_key, 1613 .ic_set_rss_lut = ixl_710_set_rss_lut, 1614 }; 1615 1616 /* driver code */ 1617 1618 struct ixl_device { 1619 const struct ixl_chip *id_chip; 1620 pci_vendor_id_t id_vid; 1621 pci_product_id_t id_pid; 1622 }; 1623 1624 static const struct ixl_device ixl_devices[] = { 1625 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_SFP }, 1626 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_SFP_2 }, 1627 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_40G_BP }, 1628 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_BP, }, 1629 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_1 }, 1630 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_2 }, 1631 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_QSFP }, 1632 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_BASET }, 1633 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_1 }, 1634 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_2 }, 1635 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_T4_10G }, 1636 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XXV710_25G_BP }, 1637 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XXV710_25G_SFP28, }, 1638 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_T, }, 1639 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_KX }, 1640 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_QSFP }, 1641 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_SFP_1 }, 1642 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_1G }, 1643 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_T }, 1644 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_SFP_2 }, 1645 }; 1646 1647 static const struct ixl_device * 1648 ixl_device_lookup(struct pci_attach_args *pa) 1649 { 1650 pci_vendor_id_t vid = PCI_VENDOR(pa->pa_id); 1651 pci_product_id_t pid = PCI_PRODUCT(pa->pa_id); 1652 const struct ixl_device *id; 1653 unsigned int i; 1654 1655 for (i = 0; i < nitems(ixl_devices); i++) { 1656 id = &ixl_devices[i]; 1657 if (id->id_vid == vid && id->id_pid == pid) 1658 return (id); 1659 } 1660 1661 return (NULL); 1662 } 1663 1664 static int 1665 ixl_match(struct device *parent, void *match, void *aux) 1666 { 1667 return (ixl_device_lookup(aux) != NULL); 1668 } 1669 1670 void 1671 ixl_attach(struct device *parent, struct device *self, void *aux) 1672 { 1673 struct ixl_softc *sc = (struct ixl_softc *)self; 1674 struct ifnet *ifp = &sc->sc_ac.ac_if; 1675 struct pci_attach_args *pa = aux; 1676 pcireg_t memtype; 1677 uint32_t port, ari, func; 1678 uint64_t phy_types = 0; 1679 unsigned int nqueues, i; 1680 int tries; 1681 1682 rw_init(&sc->sc_cfg_lock, "ixlcfg"); 1683 1684 sc->sc_chip = ixl_device_lookup(pa)->id_chip; 1685 sc->sc_pc = pa->pa_pc; 1686 sc->sc_tag = pa->pa_tag; 1687 sc->sc_dmat = pa->pa_dmat; 1688 sc->sc_aq_regs = &ixl_pf_aq_regs; 1689 1690 sc->sc_nqueues = 0; /* 1 << 0 is 1 queue */ 1691 sc->sc_tx_ring_ndescs = 1024; 1692 sc->sc_rx_ring_ndescs = 1024; 1693 1694 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, IXL_PCIREG); 1695 if (pci_mapreg_map(pa, IXL_PCIREG, memtype, 0, 1696 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems, 0)) { 1697 printf(": unable to map registers\n"); 1698 return; 1699 } 1700 1701 sc->sc_base_queue = (ixl_rd(sc, I40E_PFLAN_QALLOC) & 1702 I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1703 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1704 1705 ixl_clear_hw(sc); 1706 if (ixl_pf_reset(sc) == -1) { 1707 /* error printed by ixl_pf_reset */ 1708 goto unmap; 1709 } 1710 1711 port = ixl_rd(sc, I40E_PFGEN_PORTNUM); 1712 port &= I40E_PFGEN_PORTNUM_PORT_NUM_MASK; 1713 port >>= I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 1714 sc->sc_port = port; 1715 printf(": port %u", port); 1716 1717 ari = ixl_rd(sc, I40E_GLPCI_CAPSUP); 1718 ari &= I40E_GLPCI_CAPSUP_ARI_EN_MASK; 1719 ari >>= I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 1720 1721 func = ixl_rd(sc, I40E_PF_FUNC_RID); 1722 sc->sc_pf_id = func & (ari ? 0xff : 0x7); 1723 1724 /* initialise the adminq */ 1725 1726 if (ixl_dmamem_alloc(sc, &sc->sc_atq, 1727 sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) { 1728 printf("\n" "%s: unable to allocate atq\n", DEVNAME(sc)); 1729 goto unmap; 1730 } 1731 1732 SIMPLEQ_INIT(&sc->sc_arq_idle); 1733 SIMPLEQ_INIT(&sc->sc_arq_live); 1734 if_rxr_init(&sc->sc_arq_ring, 2, IXL_AQ_NUM - 1); 1735 task_set(&sc->sc_arq_task, ixl_arq, sc); 1736 sc->sc_arq_cons = 0; 1737 sc->sc_arq_prod = 0; 1738 1739 if (ixl_dmamem_alloc(sc, &sc->sc_arq, 1740 sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) { 1741 printf("\n" "%s: unable to allocate arq\n", DEVNAME(sc)); 1742 goto free_atq; 1743 } 1744 1745 if (!ixl_arq_fill(sc)) { 1746 printf("\n" "%s: unable to fill arq descriptors\n", 1747 DEVNAME(sc)); 1748 goto free_arq; 1749 } 1750 1751 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 1752 0, IXL_DMA_LEN(&sc->sc_atq), 1753 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1754 1755 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 1756 0, IXL_DMA_LEN(&sc->sc_arq), 1757 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1758 1759 for (tries = 0; tries < 10; tries++) { 1760 int rv; 1761 1762 sc->sc_atq_cons = 0; 1763 sc->sc_atq_prod = 0; 1764 1765 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 1766 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 1767 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 1768 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 1769 1770 ixl_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 1771 1772 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 1773 ixl_dmamem_lo(&sc->sc_atq)); 1774 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 1775 ixl_dmamem_hi(&sc->sc_atq)); 1776 ixl_wr(sc, sc->sc_aq_regs->atq_len, 1777 sc->sc_aq_regs->atq_len_enable | IXL_AQ_NUM); 1778 1779 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 1780 ixl_dmamem_lo(&sc->sc_arq)); 1781 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 1782 ixl_dmamem_hi(&sc->sc_arq)); 1783 ixl_wr(sc, sc->sc_aq_regs->arq_len, 1784 sc->sc_aq_regs->arq_len_enable | IXL_AQ_NUM); 1785 1786 rv = ixl_get_version(sc); 1787 if (rv == 0) 1788 break; 1789 if (rv != ETIMEDOUT) { 1790 printf(", unable to get firmware version\n"); 1791 goto shutdown; 1792 } 1793 1794 delaymsec(100); 1795 } 1796 1797 ixl_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 1798 1799 if (ixl_pxe_clear(sc) != 0) { 1800 /* error printed by ixl_pxe_clear */ 1801 goto shutdown; 1802 } 1803 1804 if (ixl_get_mac(sc) != 0) { 1805 /* error printed by ixl_get_mac */ 1806 goto shutdown; 1807 } 1808 1809 if (pci_intr_map_msix(pa, 0, &sc->sc_ih) == 0) { 1810 int nmsix = pci_intr_msix_count(pa); 1811 if (nmsix > 1) { /* we used 1 (the 0th) for the adminq */ 1812 nmsix--; 1813 1814 sc->sc_intrmap = intrmap_create(&sc->sc_dev, 1815 nmsix, IXL_MAX_VECTORS, INTRMAP_POWEROF2); 1816 nqueues = intrmap_count(sc->sc_intrmap); 1817 KASSERT(nqueues > 0); 1818 KASSERT(powerof2(nqueues)); 1819 sc->sc_nqueues = fls(nqueues) - 1; 1820 } 1821 } else { 1822 if (pci_intr_map_msi(pa, &sc->sc_ih) != 0 && 1823 pci_intr_map(pa, &sc->sc_ih) != 0) { 1824 printf(", unable to map interrupt\n"); 1825 goto shutdown; 1826 } 1827 } 1828 1829 nqueues = ixl_nqueues(sc); 1830 1831 printf(", %s, %d queue%s, address %s\n", 1832 pci_intr_string(sc->sc_pc, sc->sc_ih), ixl_nqueues(sc), 1833 (nqueues > 1 ? "s" : ""), 1834 ether_sprintf(sc->sc_ac.ac_enaddr)); 1835 1836 if (ixl_hmc(sc) != 0) { 1837 /* error printed by ixl_hmc */ 1838 goto shutdown; 1839 } 1840 1841 if (ixl_lldp_shut(sc) != 0) { 1842 /* error printed by ixl_lldp_shut */ 1843 goto free_hmc; 1844 } 1845 1846 if (ixl_phy_mask_ints(sc) != 0) { 1847 /* error printed by ixl_phy_mask_ints */ 1848 goto free_hmc; 1849 } 1850 1851 if (ixl_restart_an(sc) != 0) { 1852 /* error printed by ixl_restart_an */ 1853 goto free_hmc; 1854 } 1855 1856 if (ixl_get_switch_config(sc) != 0) { 1857 /* error printed by ixl_get_switch_config */ 1858 goto free_hmc; 1859 } 1860 1861 if (ixl_get_phy_types(sc, &phy_types) != 0) { 1862 /* error printed by ixl_get_phy_abilities */ 1863 goto free_hmc; 1864 } 1865 1866 if (ixl_get_link_status(sc) != 0) { 1867 /* error printed by ixl_get_link_status */ 1868 goto free_hmc; 1869 } 1870 1871 if (ixl_dmamem_alloc(sc, &sc->sc_scratch, 1872 sizeof(struct ixl_aq_vsi_data), 8) != 0) { 1873 printf("%s: unable to allocate scratch buffer\n", DEVNAME(sc)); 1874 goto free_hmc; 1875 } 1876 1877 if (ixl_get_vsi(sc) != 0) { 1878 /* error printed by ixl_get_vsi */ 1879 goto free_hmc; 1880 } 1881 1882 if (ixl_set_vsi(sc) != 0) { 1883 /* error printed by ixl_set_vsi */ 1884 goto free_scratch; 1885 } 1886 1887 sc->sc_ihc = pci_intr_establish(sc->sc_pc, sc->sc_ih, 1888 IPL_NET | IPL_MPSAFE, ixl_intr0, sc, DEVNAME(sc)); 1889 if (sc->sc_ihc == NULL) { 1890 printf("%s: unable to establish interrupt handler\n", 1891 DEVNAME(sc)); 1892 goto free_scratch; 1893 } 1894 1895 sc->sc_vectors = mallocarray(sizeof(*sc->sc_vectors), nqueues, 1896 M_DEVBUF, M_WAITOK|M_CANFAIL|M_ZERO); 1897 if (sc->sc_vectors == NULL) { 1898 printf("%s: unable to allocate vectors\n", DEVNAME(sc)); 1899 goto free_scratch; 1900 } 1901 1902 for (i = 0; i < nqueues; i++) { 1903 struct ixl_vector *iv = &sc->sc_vectors[i]; 1904 iv->iv_sc = sc; 1905 iv->iv_qid = i; 1906 snprintf(iv->iv_name, sizeof(iv->iv_name), 1907 "%s:%u", DEVNAME(sc), i); /* truncated? */ 1908 } 1909 1910 if (sc->sc_intrmap) { 1911 for (i = 0; i < nqueues; i++) { 1912 struct ixl_vector *iv = &sc->sc_vectors[i]; 1913 pci_intr_handle_t ih; 1914 int v = i + 1; /* 0 is used for adminq */ 1915 1916 if (pci_intr_map_msix(pa, v, &ih)) { 1917 printf("%s: unable to map msi-x vector %d\n", 1918 DEVNAME(sc), v); 1919 goto free_vectors; 1920 } 1921 1922 iv->iv_ihc = pci_intr_establish_cpu(sc->sc_pc, ih, 1923 IPL_NET | IPL_MPSAFE, 1924 intrmap_cpu(sc->sc_intrmap, i), 1925 ixl_intr_vector, iv, iv->iv_name); 1926 if (iv->iv_ihc == NULL) { 1927 printf("%s: unable to establish interrupt %d\n", 1928 DEVNAME(sc), v); 1929 goto free_vectors; 1930 } 1931 1932 ixl_wr(sc, I40E_PFINT_DYN_CTLN(i), 1933 I40E_PFINT_DYN_CTLN_INTENA_MASK | 1934 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1935 (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)); 1936 } 1937 } 1938 1939 /* fixup the chip ops for older fw releases */ 1940 if (sc->sc_chip == &ixl_710 && 1941 sc->sc_api_major == 1 && sc->sc_api_minor < 5) 1942 sc->sc_chip = &ixl_710_decrepit; 1943 1944 ifp->if_softc = sc; 1945 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1946 ifp->if_xflags = IFXF_MPSAFE; 1947 ifp->if_ioctl = ixl_ioctl; 1948 ifp->if_qstart = ixl_start; 1949 ifp->if_watchdog = ixl_watchdog; 1950 ifp->if_hardmtu = IXL_HARDMTU; 1951 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 1952 ifq_set_maxlen(&ifp->if_snd, sc->sc_tx_ring_ndescs); 1953 1954 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING; 1955 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | 1956 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4 | 1957 IFCAP_CSUM_TCPv6 | IFCAP_CSUM_UDPv6; 1958 1959 ifmedia_init(&sc->sc_media, 0, ixl_media_change, ixl_media_status); 1960 1961 ixl_media_add(sc, phy_types); 1962 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 1963 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 1964 1965 if_attach(ifp); 1966 ether_ifattach(ifp); 1967 1968 if_attach_queues(ifp, nqueues); 1969 if_attach_iqueues(ifp, nqueues); 1970 1971 mtx_init(&sc->sc_link_state_mtx, IPL_NET); 1972 task_set(&sc->sc_link_state_task, ixl_link_state_update, sc); 1973 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 1974 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | 1975 I40E_PFINT_ICR0_ENA_ADMINQ_MASK); 1976 ixl_wr(sc, I40E_PFINT_STAT_CTL0, 1977 IXL_NOITR << I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT); 1978 1979 /* remove default mac filter and replace it so we can see vlans */ 1980 ixl_remove_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 0); 1981 ixl_remove_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 1982 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1983 ixl_add_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 1984 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 1985 ixl_add_macvlan(sc, etherbroadcastaddr, 0, 1986 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 1987 memcpy(sc->sc_enaddr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 1988 1989 ixl_intr_enable(sc); 1990 1991 #if NKSTAT > 0 1992 ixl_kstat_attach(sc); 1993 #endif 1994 1995 return; 1996 free_vectors: 1997 if (sc->sc_intrmap != NULL) { 1998 for (i = 0; i < nqueues; i++) { 1999 struct ixl_vector *iv = &sc->sc_vectors[i]; 2000 if (iv->iv_ihc == NULL) 2001 continue; 2002 pci_intr_disestablish(sc->sc_pc, iv->iv_ihc); 2003 } 2004 } 2005 free(sc->sc_vectors, M_DEVBUF, nqueues * sizeof(*sc->sc_vectors)); 2006 free_scratch: 2007 ixl_dmamem_free(sc, &sc->sc_scratch); 2008 free_hmc: 2009 ixl_hmc_free(sc); 2010 shutdown: 2011 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 2012 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 2013 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 2014 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 2015 2016 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 0); 2017 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 0); 2018 ixl_wr(sc, sc->sc_aq_regs->atq_len, 0); 2019 2020 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 0); 2021 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 0); 2022 ixl_wr(sc, sc->sc_aq_regs->arq_len, 0); 2023 2024 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 2025 0, IXL_DMA_LEN(&sc->sc_arq), 2026 BUS_DMASYNC_POSTREAD); 2027 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 2028 0, IXL_DMA_LEN(&sc->sc_atq), 2029 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2030 2031 ixl_arq_unfill(sc); 2032 2033 free_arq: 2034 ixl_dmamem_free(sc, &sc->sc_arq); 2035 free_atq: 2036 ixl_dmamem_free(sc, &sc->sc_atq); 2037 unmap: 2038 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 2039 sc->sc_mems = 0; 2040 2041 if (sc->sc_intrmap != NULL) 2042 intrmap_destroy(sc->sc_intrmap); 2043 } 2044 2045 static void 2046 ixl_media_add(struct ixl_softc *sc, uint64_t phy_types) 2047 { 2048 struct ifmedia *ifm = &sc->sc_media; 2049 const struct ixl_phy_type *itype; 2050 unsigned int i; 2051 2052 for (i = 0; i < nitems(ixl_phy_type_map); i++) { 2053 itype = &ixl_phy_type_map[i]; 2054 2055 if (ISSET(phy_types, itype->phy_type)) 2056 ifmedia_add(ifm, IFM_ETHER | itype->ifm_type, 0, NULL); 2057 } 2058 } 2059 2060 static int 2061 ixl_media_change(struct ifnet *ifp) 2062 { 2063 /* ignore? */ 2064 return (EOPNOTSUPP); 2065 } 2066 2067 static void 2068 ixl_media_status(struct ifnet *ifp, struct ifmediareq *ifm) 2069 { 2070 struct ixl_softc *sc = ifp->if_softc; 2071 2072 NET_ASSERT_LOCKED(); 2073 2074 ifm->ifm_status = sc->sc_media_status; 2075 ifm->ifm_active = sc->sc_media_active; 2076 } 2077 2078 static void 2079 ixl_watchdog(struct ifnet *ifp) 2080 { 2081 2082 } 2083 2084 int 2085 ixl_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2086 { 2087 struct ixl_softc *sc = (struct ixl_softc *)ifp->if_softc; 2088 struct ifreq *ifr = (struct ifreq *)data; 2089 uint8_t addrhi[ETHER_ADDR_LEN], addrlo[ETHER_ADDR_LEN]; 2090 int aqerror, error = 0; 2091 2092 switch (cmd) { 2093 case SIOCSIFADDR: 2094 ifp->if_flags |= IFF_UP; 2095 /* FALLTHROUGH */ 2096 2097 case SIOCSIFFLAGS: 2098 if (ISSET(ifp->if_flags, IFF_UP)) { 2099 if (ISSET(ifp->if_flags, IFF_RUNNING)) 2100 error = ENETRESET; 2101 else 2102 error = ixl_up(sc); 2103 } else { 2104 if (ISSET(ifp->if_flags, IFF_RUNNING)) 2105 error = ixl_down(sc); 2106 } 2107 break; 2108 2109 case SIOCGIFMEDIA: 2110 case SIOCSIFMEDIA: 2111 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 2112 break; 2113 2114 case SIOCGIFRXR: 2115 error = ixl_rxrinfo(sc, (struct if_rxrinfo *)ifr->ifr_data); 2116 break; 2117 2118 case SIOCADDMULTI: 2119 if (ether_addmulti(ifr, &sc->sc_ac) == ENETRESET) { 2120 error = ether_multiaddr(&ifr->ifr_addr, addrlo, addrhi); 2121 if (error != 0) 2122 return (error); 2123 2124 aqerror = ixl_add_macvlan(sc, addrlo, 0, 2125 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 2126 if (aqerror == IXL_AQ_RC_ENOSPC) { 2127 ether_delmulti(ifr, &sc->sc_ac); 2128 error = ENOSPC; 2129 } 2130 2131 if (sc->sc_ac.ac_multirangecnt > 0) { 2132 SET(ifp->if_flags, IFF_ALLMULTI); 2133 error = ENETRESET; 2134 } 2135 } 2136 break; 2137 2138 case SIOCDELMULTI: 2139 if (ether_delmulti(ifr, &sc->sc_ac) == ENETRESET) { 2140 error = ether_multiaddr(&ifr->ifr_addr, addrlo, addrhi); 2141 if (error != 0) 2142 return (error); 2143 2144 ixl_remove_macvlan(sc, addrlo, 0, 2145 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 2146 2147 if (ISSET(ifp->if_flags, IFF_ALLMULTI) && 2148 sc->sc_ac.ac_multirangecnt == 0) { 2149 CLR(ifp->if_flags, IFF_ALLMULTI); 2150 error = ENETRESET; 2151 } 2152 } 2153 break; 2154 2155 case SIOCGIFSFFPAGE: 2156 error = rw_enter(&ixl_sff_lock, RW_WRITE|RW_INTR); 2157 if (error != 0) 2158 break; 2159 2160 error = ixl_get_sffpage(sc, (struct if_sffpage *)data); 2161 rw_exit(&ixl_sff_lock); 2162 break; 2163 2164 default: 2165 error = ether_ioctl(ifp, &sc->sc_ac, cmd, data); 2166 break; 2167 } 2168 2169 if (error == ENETRESET) 2170 error = ixl_iff(sc); 2171 2172 return (error); 2173 } 2174 2175 static inline void * 2176 ixl_hmc_kva(struct ixl_softc *sc, unsigned int type, unsigned int i) 2177 { 2178 uint8_t *kva = IXL_DMA_KVA(&sc->sc_hmc_pd); 2179 struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type]; 2180 2181 if (i >= e->hmc_count) 2182 return (NULL); 2183 2184 kva += e->hmc_base; 2185 kva += i * e->hmc_size; 2186 2187 return (kva); 2188 } 2189 2190 static inline size_t 2191 ixl_hmc_len(struct ixl_softc *sc, unsigned int type) 2192 { 2193 struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type]; 2194 2195 return (e->hmc_size); 2196 } 2197 2198 static int 2199 ixl_configure_rss(struct ixl_softc *sc) 2200 { 2201 struct ixl_rss_key rsskey; 2202 struct ixl_rss_lut_128 lut; 2203 uint8_t *lute = (uint8_t *)&lut; 2204 uint64_t rss_hena; 2205 unsigned int i, nqueues; 2206 int error; 2207 2208 #if 0 2209 /* if we want to do a 512 entry LUT, do this. */ 2210 uint32_t v = ixl_rd_ctl(sc, I40E_PFQF_CTL_0); 2211 SET(v, I40E_PFQF_CTL_0_HASHLUTSIZE_MASK); 2212 ixl_wr_ctl(sc, I40E_PFQF_CTL_0, v); 2213 #endif 2214 2215 stoeplitz_to_key(&rsskey, sizeof(rsskey)); 2216 2217 nqueues = ixl_nqueues(sc); 2218 for (i = 0; i < sizeof(lut); i++) { 2219 /* 2220 * ixl must have a power of 2 rings, so using mod 2221 * to populate the table is fine. 2222 */ 2223 lute[i] = i % nqueues; 2224 } 2225 2226 error = ixl_set_rss_key(sc, &rsskey); 2227 if (error != 0) 2228 return (error); 2229 2230 rss_hena = (uint64_t)ixl_rd_ctl(sc, I40E_PFQF_HENA(0)); 2231 rss_hena |= (uint64_t)ixl_rd_ctl(sc, I40E_PFQF_HENA(1)) << 32; 2232 rss_hena |= ixl_rss_hena(sc); 2233 ixl_wr_ctl(sc, I40E_PFQF_HENA(0), rss_hena); 2234 ixl_wr_ctl(sc, I40E_PFQF_HENA(1), rss_hena >> 32); 2235 2236 error = ixl_set_rss_lut(sc, &lut); 2237 if (error != 0) 2238 return (error); 2239 2240 /* nothing to clena up :( */ 2241 2242 return (0); 2243 } 2244 2245 static int 2246 ixl_up(struct ixl_softc *sc) 2247 { 2248 struct ifnet *ifp = &sc->sc_ac.ac_if; 2249 struct ifqueue *ifq; 2250 struct ifiqueue *ifiq; 2251 struct ixl_vector *iv; 2252 struct ixl_rx_ring *rxr; 2253 struct ixl_tx_ring *txr; 2254 unsigned int nqueues, i; 2255 uint32_t reg; 2256 int rv = ENOMEM; 2257 2258 nqueues = ixl_nqueues(sc); 2259 2260 rw_enter_write(&sc->sc_cfg_lock); 2261 if (sc->sc_dead) { 2262 rw_exit_write(&sc->sc_cfg_lock); 2263 return (ENXIO); 2264 } 2265 2266 /* allocation is the only thing that can fail, so do it up front */ 2267 for (i = 0; i < nqueues; i++) { 2268 rxr = ixl_rxr_alloc(sc, i); 2269 if (rxr == NULL) 2270 goto free; 2271 2272 txr = ixl_txr_alloc(sc, i); 2273 if (txr == NULL) { 2274 ixl_rxr_free(sc, rxr); 2275 goto free; 2276 } 2277 2278 /* wire everything together */ 2279 iv = &sc->sc_vectors[i]; 2280 iv->iv_rxr = rxr; 2281 iv->iv_txr = txr; 2282 2283 ifq = ifp->if_ifqs[i]; 2284 ifq->ifq_softc = txr; 2285 txr->txr_ifq = ifq; 2286 2287 ifiq = ifp->if_iqs[i]; 2288 ifiq->ifiq_softc = rxr; 2289 rxr->rxr_ifiq = ifiq; 2290 } 2291 2292 /* XXX wait 50ms from completion of last RX queue disable */ 2293 2294 for (i = 0; i < nqueues; i++) { 2295 iv = &sc->sc_vectors[i]; 2296 rxr = iv->iv_rxr; 2297 txr = iv->iv_txr; 2298 2299 ixl_txr_qdis(sc, txr, 1); 2300 2301 ixl_rxr_config(sc, rxr); 2302 ixl_txr_config(sc, txr); 2303 2304 ixl_wr(sc, I40E_QTX_CTL(i), I40E_QTX_CTL_PF_QUEUE | 2305 (sc->sc_pf_id << I40E_QTX_CTL_PF_INDX_SHIFT)); 2306 2307 ixl_wr(sc, rxr->rxr_tail, 0); 2308 ixl_rxfill(sc, rxr); 2309 2310 reg = ixl_rd(sc, I40E_QRX_ENA(i)); 2311 SET(reg, I40E_QRX_ENA_QENA_REQ_MASK); 2312 ixl_wr(sc, I40E_QRX_ENA(i), reg); 2313 2314 reg = ixl_rd(sc, I40E_QTX_ENA(i)); 2315 SET(reg, I40E_QTX_ENA_QENA_REQ_MASK); 2316 ixl_wr(sc, I40E_QTX_ENA(i), reg); 2317 } 2318 2319 for (i = 0; i < nqueues; i++) { 2320 iv = &sc->sc_vectors[i]; 2321 rxr = iv->iv_rxr; 2322 txr = iv->iv_txr; 2323 2324 if (ixl_rxr_enabled(sc, rxr) != 0) 2325 goto down; 2326 2327 if (ixl_txr_enabled(sc, txr) != 0) 2328 goto down; 2329 } 2330 2331 ixl_configure_rss(sc); 2332 2333 SET(ifp->if_flags, IFF_RUNNING); 2334 2335 if (sc->sc_intrmap == NULL) { 2336 ixl_wr(sc, I40E_PFINT_LNKLST0, 2337 (I40E_INTR_NOTX_QUEUE << 2338 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 2339 (I40E_QUEUE_TYPE_RX << 2340 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 2341 2342 ixl_wr(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), 2343 (I40E_INTR_NOTX_INTR << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 2344 (I40E_ITR_INDEX_RX << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 2345 (I40E_INTR_NOTX_RX_QUEUE << 2346 I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) | 2347 (I40E_INTR_NOTX_QUEUE << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 2348 (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 2349 I40E_QINT_RQCTL_CAUSE_ENA_MASK); 2350 2351 ixl_wr(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), 2352 (I40E_INTR_NOTX_INTR << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 2353 (I40E_ITR_INDEX_TX << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 2354 (I40E_INTR_NOTX_TX_QUEUE << 2355 I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) | 2356 (I40E_QUEUE_TYPE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 2357 (I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) | 2358 I40E_QINT_TQCTL_CAUSE_ENA_MASK); 2359 } else { 2360 /* vector 0 has no queues */ 2361 ixl_wr(sc, I40E_PFINT_LNKLST0, 2362 I40E_QUEUE_TYPE_EOL << 2363 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT); 2364 2365 /* queue n is mapped to vector n+1 */ 2366 for (i = 0; i < nqueues; i++) { 2367 /* LNKLSTN(i) configures vector i+1 */ 2368 ixl_wr(sc, I40E_PFINT_LNKLSTN(i), 2369 (i << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) | 2370 (I40E_QUEUE_TYPE_RX << 2371 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 2372 ixl_wr(sc, I40E_QINT_RQCTL(i), 2373 ((i+1) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 2374 (I40E_ITR_INDEX_RX << 2375 I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 2376 (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 2377 (I40E_QUEUE_TYPE_TX << 2378 I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 2379 I40E_QINT_RQCTL_CAUSE_ENA_MASK); 2380 ixl_wr(sc, I40E_QINT_TQCTL(i), 2381 ((i+1) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 2382 (I40E_ITR_INDEX_TX << 2383 I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 2384 (I40E_QUEUE_TYPE_EOL << 2385 I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 2386 (I40E_QUEUE_TYPE_RX << 2387 I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) | 2388 I40E_QINT_TQCTL_CAUSE_ENA_MASK); 2389 2390 ixl_wr(sc, I40E_PFINT_ITRN(0, i), 0x7a); 2391 ixl_wr(sc, I40E_PFINT_ITRN(1, i), 0x7a); 2392 ixl_wr(sc, I40E_PFINT_ITRN(2, i), 0); 2393 } 2394 } 2395 2396 ixl_wr(sc, I40E_PFINT_ITR0(0), 0x7a); 2397 ixl_wr(sc, I40E_PFINT_ITR0(1), 0x7a); 2398 ixl_wr(sc, I40E_PFINT_ITR0(2), 0); 2399 2400 rw_exit_write(&sc->sc_cfg_lock); 2401 2402 return (ENETRESET); 2403 2404 free: 2405 for (i = 0; i < nqueues; i++) { 2406 iv = &sc->sc_vectors[i]; 2407 rxr = iv->iv_rxr; 2408 txr = iv->iv_txr; 2409 2410 if (rxr == NULL) { 2411 /* 2412 * tx and rx get set at the same time, so if one 2413 * is NULL, the other is too. 2414 */ 2415 continue; 2416 } 2417 2418 ixl_txr_free(sc, txr); 2419 ixl_rxr_free(sc, rxr); 2420 } 2421 rw_exit_write(&sc->sc_cfg_lock); 2422 return (rv); 2423 down: 2424 rw_exit_write(&sc->sc_cfg_lock); 2425 ixl_down(sc); 2426 return (ETIMEDOUT); 2427 } 2428 2429 static int 2430 ixl_iff(struct ixl_softc *sc) 2431 { 2432 struct ifnet *ifp = &sc->sc_ac.ac_if; 2433 struct ixl_atq iatq; 2434 struct ixl_aq_desc *iaq; 2435 struct ixl_aq_vsi_promisc_param *param; 2436 2437 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 2438 return (0); 2439 2440 memset(&iatq, 0, sizeof(iatq)); 2441 2442 iaq = &iatq.iatq_desc; 2443 iaq->iaq_opcode = htole16(IXL_AQ_OP_SET_VSI_PROMISC); 2444 2445 param = (struct ixl_aq_vsi_promisc_param *)&iaq->iaq_param; 2446 param->flags = htole16(IXL_AQ_VSI_PROMISC_FLAG_BCAST | 2447 IXL_AQ_VSI_PROMISC_FLAG_VLAN); 2448 if (ISSET(ifp->if_flags, IFF_PROMISC)) { 2449 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST | 2450 IXL_AQ_VSI_PROMISC_FLAG_MCAST); 2451 } else if (ISSET(ifp->if_flags, IFF_ALLMULTI)) { 2452 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_MCAST); 2453 } 2454 param->valid_flags = htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST | 2455 IXL_AQ_VSI_PROMISC_FLAG_MCAST | IXL_AQ_VSI_PROMISC_FLAG_BCAST | 2456 IXL_AQ_VSI_PROMISC_FLAG_VLAN); 2457 param->seid = sc->sc_seid; 2458 2459 ixl_atq_exec(sc, &iatq, "ixliff"); 2460 2461 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK)) 2462 return (EIO); 2463 2464 if (memcmp(sc->sc_enaddr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN) != 0) { 2465 ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 2466 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 2467 ixl_add_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 2468 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 2469 memcpy(sc->sc_enaddr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 2470 } 2471 return (0); 2472 } 2473 2474 static int 2475 ixl_down(struct ixl_softc *sc) 2476 { 2477 struct ifnet *ifp = &sc->sc_ac.ac_if; 2478 struct ixl_vector *iv; 2479 struct ixl_rx_ring *rxr; 2480 struct ixl_tx_ring *txr; 2481 unsigned int nqueues, i; 2482 uint32_t reg; 2483 int error = 0; 2484 2485 nqueues = ixl_nqueues(sc); 2486 2487 rw_enter_write(&sc->sc_cfg_lock); 2488 2489 CLR(ifp->if_flags, IFF_RUNNING); 2490 2491 NET_UNLOCK(); 2492 2493 /* mask interrupts */ 2494 reg = ixl_rd(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE)); 2495 CLR(reg, I40E_QINT_RQCTL_CAUSE_ENA_MASK); 2496 ixl_wr(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), reg); 2497 2498 reg = ixl_rd(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE)); 2499 CLR(reg, I40E_QINT_TQCTL_CAUSE_ENA_MASK); 2500 ixl_wr(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), reg); 2501 2502 ixl_wr(sc, I40E_PFINT_LNKLST0, I40E_QUEUE_TYPE_EOL); 2503 2504 /* make sure the no hw generated work is still in flight */ 2505 intr_barrier(sc->sc_ihc); 2506 if (sc->sc_intrmap != NULL) { 2507 for (i = 0; i < nqueues; i++) { 2508 iv = &sc->sc_vectors[i]; 2509 rxr = iv->iv_rxr; 2510 txr = iv->iv_txr; 2511 2512 ixl_txr_qdis(sc, txr, 0); 2513 2514 ifq_barrier(txr->txr_ifq); 2515 2516 timeout_del_barrier(&rxr->rxr_refill); 2517 2518 intr_barrier(iv->iv_ihc); 2519 } 2520 } 2521 2522 /* XXX wait at least 400 usec for all tx queues in one go */ 2523 delay(500); 2524 2525 for (i = 0; i < nqueues; i++) { 2526 reg = ixl_rd(sc, I40E_QTX_ENA(i)); 2527 CLR(reg, I40E_QTX_ENA_QENA_REQ_MASK); 2528 ixl_wr(sc, I40E_QTX_ENA(i), reg); 2529 2530 reg = ixl_rd(sc, I40E_QRX_ENA(i)); 2531 CLR(reg, I40E_QRX_ENA_QENA_REQ_MASK); 2532 ixl_wr(sc, I40E_QRX_ENA(i), reg); 2533 } 2534 2535 for (i = 0; i < nqueues; i++) { 2536 iv = &sc->sc_vectors[i]; 2537 rxr = iv->iv_rxr; 2538 txr = iv->iv_txr; 2539 2540 if (ixl_txr_disabled(sc, txr) != 0) 2541 goto die; 2542 2543 if (ixl_rxr_disabled(sc, rxr) != 0) 2544 goto die; 2545 } 2546 2547 for (i = 0; i < nqueues; i++) { 2548 iv = &sc->sc_vectors[i]; 2549 rxr = iv->iv_rxr; 2550 txr = iv->iv_txr; 2551 2552 ixl_txr_unconfig(sc, txr); 2553 ixl_rxr_unconfig(sc, rxr); 2554 2555 ixl_txr_clean(sc, txr); 2556 ixl_rxr_clean(sc, rxr); 2557 2558 ixl_txr_free(sc, txr); 2559 ixl_rxr_free(sc, rxr); 2560 2561 ifp->if_iqs[i]->ifiq_softc = NULL; 2562 ifp->if_ifqs[i]->ifq_softc = NULL; 2563 } 2564 2565 out: 2566 rw_exit_write(&sc->sc_cfg_lock); 2567 NET_LOCK(); 2568 return (error); 2569 die: 2570 sc->sc_dead = 1; 2571 log(LOG_CRIT, "%s: failed to shut down rings", DEVNAME(sc)); 2572 error = ETIMEDOUT; 2573 goto out; 2574 } 2575 2576 static struct ixl_tx_ring * 2577 ixl_txr_alloc(struct ixl_softc *sc, unsigned int qid) 2578 { 2579 struct ixl_tx_ring *txr; 2580 struct ixl_tx_map *maps, *txm; 2581 unsigned int i; 2582 2583 txr = malloc(sizeof(*txr), M_DEVBUF, M_WAITOK|M_CANFAIL); 2584 if (txr == NULL) 2585 return (NULL); 2586 2587 maps = mallocarray(sizeof(*maps), 2588 sc->sc_tx_ring_ndescs, M_DEVBUF, M_WAITOK|M_CANFAIL|M_ZERO); 2589 if (maps == NULL) 2590 goto free; 2591 2592 if (ixl_dmamem_alloc(sc, &txr->txr_mem, 2593 sizeof(struct ixl_tx_desc) * sc->sc_tx_ring_ndescs, 2594 IXL_TX_QUEUE_ALIGN) != 0) 2595 goto freemap; 2596 2597 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2598 txm = &maps[i]; 2599 2600 if (bus_dmamap_create(sc->sc_dmat, 2601 IXL_HARDMTU, IXL_TX_PKT_DESCS, IXL_HARDMTU, 0, 2602 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 2603 &txm->txm_map) != 0) 2604 goto uncreate; 2605 2606 txm->txm_eop = -1; 2607 txm->txm_m = NULL; 2608 } 2609 2610 txr->txr_cons = txr->txr_prod = 0; 2611 txr->txr_maps = maps; 2612 2613 txr->txr_tail = I40E_QTX_TAIL(qid); 2614 txr->txr_qid = qid; 2615 2616 return (txr); 2617 2618 uncreate: 2619 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2620 txm = &maps[i]; 2621 2622 if (txm->txm_map == NULL) 2623 continue; 2624 2625 bus_dmamap_destroy(sc->sc_dmat, txm->txm_map); 2626 } 2627 2628 ixl_dmamem_free(sc, &txr->txr_mem); 2629 freemap: 2630 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_tx_ring_ndescs); 2631 free: 2632 free(txr, M_DEVBUF, sizeof(*txr)); 2633 return (NULL); 2634 } 2635 2636 static void 2637 ixl_txr_qdis(struct ixl_softc *sc, struct ixl_tx_ring *txr, int enable) 2638 { 2639 unsigned int qid; 2640 bus_size_t reg; 2641 uint32_t r; 2642 2643 qid = txr->txr_qid + sc->sc_base_queue; 2644 reg = I40E_GLLAN_TXPRE_QDIS(qid / 128); 2645 qid %= 128; 2646 2647 r = ixl_rd(sc, reg); 2648 CLR(r, I40E_GLLAN_TXPRE_QDIS_QINDX_MASK); 2649 SET(r, qid << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 2650 SET(r, enable ? I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK : 2651 I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK); 2652 ixl_wr(sc, reg, r); 2653 } 2654 2655 static void 2656 ixl_txr_config(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2657 { 2658 struct ixl_hmc_txq txq; 2659 struct ixl_aq_vsi_data *data = IXL_DMA_KVA(&sc->sc_scratch); 2660 void *hmc; 2661 2662 memset(&txq, 0, sizeof(txq)); 2663 txq.head = htole16(0); 2664 txq.new_context = 1; 2665 htolem64(&txq.base, 2666 IXL_DMA_DVA(&txr->txr_mem) / IXL_HMC_TXQ_BASE_UNIT); 2667 txq.head_wb_ena = IXL_HMC_TXQ_DESC_WB; 2668 htolem16(&txq.qlen, sc->sc_tx_ring_ndescs); 2669 txq.tphrdesc_ena = 0; 2670 txq.tphrpacket_ena = 0; 2671 txq.tphwdesc_ena = 0; 2672 txq.rdylist = data->qs_handle[0]; 2673 2674 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid); 2675 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX)); 2676 ixl_hmc_pack(hmc, &txq, ixl_hmc_pack_txq, nitems(ixl_hmc_pack_txq)); 2677 } 2678 2679 static void 2680 ixl_txr_unconfig(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2681 { 2682 void *hmc; 2683 2684 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid); 2685 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX)); 2686 } 2687 2688 static void 2689 ixl_txr_clean(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2690 { 2691 struct ixl_tx_map *maps, *txm; 2692 bus_dmamap_t map; 2693 unsigned int i; 2694 2695 maps = txr->txr_maps; 2696 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2697 txm = &maps[i]; 2698 2699 if (txm->txm_m == NULL) 2700 continue; 2701 2702 map = txm->txm_map; 2703 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2704 BUS_DMASYNC_POSTWRITE); 2705 bus_dmamap_unload(sc->sc_dmat, map); 2706 2707 m_freem(txm->txm_m); 2708 txm->txm_m = NULL; 2709 } 2710 } 2711 2712 static int 2713 ixl_txr_enabled(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2714 { 2715 bus_size_t ena = I40E_QTX_ENA(txr->txr_qid); 2716 uint32_t reg; 2717 int i; 2718 2719 for (i = 0; i < 10; i++) { 2720 reg = ixl_rd(sc, ena); 2721 if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK)) 2722 return (0); 2723 2724 delaymsec(10); 2725 } 2726 2727 return (ETIMEDOUT); 2728 } 2729 2730 static int 2731 ixl_txr_disabled(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2732 { 2733 bus_size_t ena = I40E_QTX_ENA(txr->txr_qid); 2734 uint32_t reg; 2735 int i; 2736 2737 for (i = 0; i < 20; i++) { 2738 reg = ixl_rd(sc, ena); 2739 if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK) == 0) 2740 return (0); 2741 2742 delaymsec(10); 2743 } 2744 2745 return (ETIMEDOUT); 2746 } 2747 2748 static void 2749 ixl_txr_free(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2750 { 2751 struct ixl_tx_map *maps, *txm; 2752 unsigned int i; 2753 2754 maps = txr->txr_maps; 2755 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2756 txm = &maps[i]; 2757 2758 bus_dmamap_destroy(sc->sc_dmat, txm->txm_map); 2759 } 2760 2761 ixl_dmamem_free(sc, &txr->txr_mem); 2762 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_tx_ring_ndescs); 2763 free(txr, M_DEVBUF, sizeof(*txr)); 2764 } 2765 2766 static inline int 2767 ixl_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, struct mbuf *m) 2768 { 2769 int error; 2770 2771 error = bus_dmamap_load_mbuf(dmat, map, m, 2772 BUS_DMA_STREAMING | BUS_DMA_NOWAIT); 2773 if (error != EFBIG) 2774 return (error); 2775 2776 error = m_defrag(m, M_DONTWAIT); 2777 if (error != 0) 2778 return (error); 2779 2780 return (bus_dmamap_load_mbuf(dmat, map, m, 2781 BUS_DMA_STREAMING | BUS_DMA_NOWAIT)); 2782 } 2783 2784 static uint64_t 2785 ixl_tx_setup_offload(struct mbuf *m0) 2786 { 2787 struct mbuf *m; 2788 int hoff; 2789 uint64_t hlen; 2790 uint8_t ipproto; 2791 uint64_t offload = 0; 2792 2793 if (ISSET(m0->m_flags, M_VLANTAG)) { 2794 uint64_t vtag = m0->m_pkthdr.ether_vtag; 2795 offload |= IXL_TX_DESC_CMD_IL2TAG1; 2796 offload |= vtag << IXL_TX_DESC_L2TAG1_SHIFT; 2797 } 2798 2799 if (!ISSET(m0->m_pkthdr.csum_flags, 2800 M_IPV4_CSUM_OUT|M_TCP_CSUM_OUT|M_UDP_CSUM_OUT)) 2801 return (offload); 2802 2803 switch (ntohs(mtod(m0, struct ether_header *)->ether_type)) { 2804 case ETHERTYPE_IP: { 2805 struct ip *ip; 2806 2807 m = m_getptr(m0, ETHER_HDR_LEN, &hoff); 2808 KASSERT(m != NULL && m->m_len - hoff >= sizeof(*ip)); 2809 ip = (struct ip *)(mtod(m, caddr_t) + hoff); 2810 2811 offload |= ISSET(m0->m_pkthdr.csum_flags, M_IPV4_CSUM_OUT) ? 2812 IXL_TX_DESC_CMD_IIPT_IPV4_CSUM : 2813 IXL_TX_DESC_CMD_IIPT_IPV4; 2814 2815 hlen = ip->ip_hl << 2; 2816 ipproto = ip->ip_p; 2817 break; 2818 } 2819 2820 #ifdef INET6 2821 case ETHERTYPE_IPV6: { 2822 struct ip6_hdr *ip6; 2823 2824 m = m_getptr(m0, ETHER_HDR_LEN, &hoff); 2825 KASSERT(m != NULL && m->m_len - hoff >= sizeof(*ip6)); 2826 ip6 = (struct ip6_hdr *)(mtod(m, caddr_t) + hoff); 2827 2828 offload |= IXL_TX_DESC_CMD_IIPT_IPV6; 2829 2830 hlen = sizeof(*ip6); 2831 ipproto = ip6->ip6_nxt; 2832 break; 2833 } 2834 #endif 2835 default: 2836 panic("CSUM_OUT set for non-IP packet"); 2837 /* NOTREACHED */ 2838 } 2839 2840 offload |= (ETHER_HDR_LEN >> 1) << IXL_TX_DESC_MACLEN_SHIFT; 2841 offload |= (hlen >> 2) << IXL_TX_DESC_IPLEN_SHIFT; 2842 2843 switch (ipproto) { 2844 case IPPROTO_TCP: { 2845 struct tcphdr *th; 2846 2847 if (!ISSET(m0->m_pkthdr.csum_flags, M_TCP_CSUM_OUT)) 2848 break; 2849 2850 m = m_getptr(m, hoff + hlen, &hoff); 2851 KASSERT(m != NULL && m->m_len - hoff >= sizeof(*th)); 2852 th = (struct tcphdr *)(mtod(m, caddr_t) + hoff); 2853 2854 offload |= IXL_TX_DESC_CMD_L4T_EOFT_TCP; 2855 offload |= (uint64_t)th->th_off << IXL_TX_DESC_L4LEN_SHIFT; 2856 break; 2857 } 2858 2859 case IPPROTO_UDP: 2860 if (!ISSET(m0->m_pkthdr.csum_flags, M_UDP_CSUM_OUT)) 2861 break; 2862 2863 offload |= IXL_TX_DESC_CMD_L4T_EOFT_UDP; 2864 offload |= (sizeof(struct udphdr) >> 2) << 2865 IXL_TX_DESC_L4LEN_SHIFT; 2866 break; 2867 } 2868 2869 return (offload); 2870 } 2871 2872 static void 2873 ixl_start(struct ifqueue *ifq) 2874 { 2875 struct ifnet *ifp = ifq->ifq_if; 2876 struct ixl_softc *sc = ifp->if_softc; 2877 struct ixl_tx_ring *txr = ifq->ifq_softc; 2878 struct ixl_tx_desc *ring, *txd; 2879 struct ixl_tx_map *txm; 2880 bus_dmamap_t map; 2881 struct mbuf *m; 2882 uint64_t cmd; 2883 unsigned int prod, free, last, i; 2884 unsigned int mask; 2885 int post = 0; 2886 uint64_t offload; 2887 #if NBPFILTER > 0 2888 caddr_t if_bpf; 2889 #endif 2890 2891 if (!LINK_STATE_IS_UP(ifp->if_link_state)) { 2892 ifq_purge(ifq); 2893 return; 2894 } 2895 2896 prod = txr->txr_prod; 2897 free = txr->txr_cons; 2898 if (free <= prod) 2899 free += sc->sc_tx_ring_ndescs; 2900 free -= prod; 2901 2902 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2903 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTWRITE); 2904 2905 ring = IXL_DMA_KVA(&txr->txr_mem); 2906 mask = sc->sc_tx_ring_ndescs - 1; 2907 2908 for (;;) { 2909 if (free <= IXL_TX_PKT_DESCS) { 2910 ifq_set_oactive(ifq); 2911 break; 2912 } 2913 2914 m = ifq_dequeue(ifq); 2915 if (m == NULL) 2916 break; 2917 2918 offload = ixl_tx_setup_offload(m); 2919 2920 txm = &txr->txr_maps[prod]; 2921 map = txm->txm_map; 2922 2923 if (ixl_load_mbuf(sc->sc_dmat, map, m) != 0) { 2924 ifq->ifq_errors++; 2925 m_freem(m); 2926 continue; 2927 } 2928 2929 bus_dmamap_sync(sc->sc_dmat, map, 0, 2930 map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2931 2932 for (i = 0; i < map->dm_nsegs; i++) { 2933 txd = &ring[prod]; 2934 2935 cmd = (uint64_t)map->dm_segs[i].ds_len << 2936 IXL_TX_DESC_BSIZE_SHIFT; 2937 cmd |= IXL_TX_DESC_DTYPE_DATA | IXL_TX_DESC_CMD_ICRC; 2938 cmd |= offload; 2939 2940 htolem64(&txd->addr, map->dm_segs[i].ds_addr); 2941 htolem64(&txd->cmd, cmd); 2942 2943 last = prod; 2944 2945 prod++; 2946 prod &= mask; 2947 } 2948 cmd |= IXL_TX_DESC_CMD_EOP | IXL_TX_DESC_CMD_RS; 2949 htolem64(&txd->cmd, cmd); 2950 2951 txm->txm_m = m; 2952 txm->txm_eop = last; 2953 2954 #if NBPFILTER > 0 2955 if_bpf = ifp->if_bpf; 2956 if (if_bpf) 2957 bpf_mtap_ether(if_bpf, m, BPF_DIRECTION_OUT); 2958 #endif 2959 2960 free -= i; 2961 post = 1; 2962 } 2963 2964 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2965 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREWRITE); 2966 2967 if (post) { 2968 txr->txr_prod = prod; 2969 ixl_wr(sc, txr->txr_tail, prod); 2970 } 2971 } 2972 2973 static int 2974 ixl_txeof(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2975 { 2976 struct ifqueue *ifq = txr->txr_ifq; 2977 struct ixl_tx_desc *ring, *txd; 2978 struct ixl_tx_map *txm; 2979 bus_dmamap_t map; 2980 unsigned int cons, prod, last; 2981 unsigned int mask; 2982 uint64_t dtype; 2983 int done = 0; 2984 2985 prod = txr->txr_prod; 2986 cons = txr->txr_cons; 2987 2988 if (cons == prod) 2989 return (0); 2990 2991 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2992 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTREAD); 2993 2994 ring = IXL_DMA_KVA(&txr->txr_mem); 2995 mask = sc->sc_tx_ring_ndescs - 1; 2996 2997 do { 2998 txm = &txr->txr_maps[cons]; 2999 last = txm->txm_eop; 3000 txd = &ring[last]; 3001 3002 dtype = txd->cmd & htole64(IXL_TX_DESC_DTYPE_MASK); 3003 if (dtype != htole64(IXL_TX_DESC_DTYPE_DONE)) 3004 break; 3005 3006 map = txm->txm_map; 3007 3008 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3009 BUS_DMASYNC_POSTWRITE); 3010 bus_dmamap_unload(sc->sc_dmat, map); 3011 m_freem(txm->txm_m); 3012 3013 txm->txm_m = NULL; 3014 txm->txm_eop = -1; 3015 3016 cons = last + 1; 3017 cons &= mask; 3018 3019 done = 1; 3020 } while (cons != prod); 3021 3022 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 3023 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREREAD); 3024 3025 txr->txr_cons = cons; 3026 3027 //ixl_enable(sc, txr->txr_msix); 3028 3029 if (ifq_is_oactive(ifq)) 3030 ifq_restart(ifq); 3031 3032 return (done); 3033 } 3034 3035 static struct ixl_rx_ring * 3036 ixl_rxr_alloc(struct ixl_softc *sc, unsigned int qid) 3037 { 3038 struct ixl_rx_ring *rxr; 3039 struct ixl_rx_map *maps, *rxm; 3040 unsigned int i; 3041 3042 rxr = malloc(sizeof(*rxr), M_DEVBUF, M_WAITOK|M_CANFAIL); 3043 if (rxr == NULL) 3044 return (NULL); 3045 3046 maps = mallocarray(sizeof(*maps), 3047 sc->sc_rx_ring_ndescs, M_DEVBUF, M_WAITOK|M_CANFAIL|M_ZERO); 3048 if (maps == NULL) 3049 goto free; 3050 3051 if (ixl_dmamem_alloc(sc, &rxr->rxr_mem, 3052 sizeof(struct ixl_rx_rd_desc_16) * sc->sc_rx_ring_ndescs, 3053 IXL_RX_QUEUE_ALIGN) != 0) 3054 goto freemap; 3055 3056 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3057 rxm = &maps[i]; 3058 3059 if (bus_dmamap_create(sc->sc_dmat, 3060 IXL_HARDMTU, 1, IXL_HARDMTU, 0, 3061 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 3062 &rxm->rxm_map) != 0) 3063 goto uncreate; 3064 3065 rxm->rxm_m = NULL; 3066 } 3067 3068 rxr->rxr_sc = sc; 3069 if_rxr_init(&rxr->rxr_acct, 17, sc->sc_rx_ring_ndescs - 1); 3070 timeout_set(&rxr->rxr_refill, ixl_rxrefill, rxr); 3071 rxr->rxr_cons = rxr->rxr_prod = 0; 3072 rxr->rxr_m_head = NULL; 3073 rxr->rxr_m_tail = &rxr->rxr_m_head; 3074 rxr->rxr_maps = maps; 3075 3076 rxr->rxr_tail = I40E_QRX_TAIL(qid); 3077 rxr->rxr_qid = qid; 3078 3079 return (rxr); 3080 3081 uncreate: 3082 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3083 rxm = &maps[i]; 3084 3085 if (rxm->rxm_map == NULL) 3086 continue; 3087 3088 bus_dmamap_destroy(sc->sc_dmat, rxm->rxm_map); 3089 } 3090 3091 ixl_dmamem_free(sc, &rxr->rxr_mem); 3092 freemap: 3093 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_rx_ring_ndescs); 3094 free: 3095 free(rxr, M_DEVBUF, sizeof(*rxr)); 3096 return (NULL); 3097 } 3098 3099 static void 3100 ixl_rxr_clean(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3101 { 3102 struct ixl_rx_map *maps, *rxm; 3103 bus_dmamap_t map; 3104 unsigned int i; 3105 3106 timeout_del_barrier(&rxr->rxr_refill); 3107 3108 maps = rxr->rxr_maps; 3109 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3110 rxm = &maps[i]; 3111 3112 if (rxm->rxm_m == NULL) 3113 continue; 3114 3115 map = rxm->rxm_map; 3116 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3117 BUS_DMASYNC_POSTWRITE); 3118 bus_dmamap_unload(sc->sc_dmat, map); 3119 3120 m_freem(rxm->rxm_m); 3121 rxm->rxm_m = NULL; 3122 } 3123 3124 m_freem(rxr->rxr_m_head); 3125 rxr->rxr_m_head = NULL; 3126 rxr->rxr_m_tail = &rxr->rxr_m_head; 3127 3128 rxr->rxr_prod = rxr->rxr_cons = 0; 3129 } 3130 3131 static int 3132 ixl_rxr_enabled(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3133 { 3134 bus_size_t ena = I40E_QRX_ENA(rxr->rxr_qid); 3135 uint32_t reg; 3136 int i; 3137 3138 for (i = 0; i < 10; i++) { 3139 reg = ixl_rd(sc, ena); 3140 if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK)) 3141 return (0); 3142 3143 delaymsec(10); 3144 } 3145 3146 return (ETIMEDOUT); 3147 } 3148 3149 static int 3150 ixl_rxr_disabled(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3151 { 3152 bus_size_t ena = I40E_QRX_ENA(rxr->rxr_qid); 3153 uint32_t reg; 3154 int i; 3155 3156 for (i = 0; i < 20; i++) { 3157 reg = ixl_rd(sc, ena); 3158 if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK) == 0) 3159 return (0); 3160 3161 delaymsec(10); 3162 } 3163 3164 return (ETIMEDOUT); 3165 } 3166 3167 static void 3168 ixl_rxr_config(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3169 { 3170 struct ixl_hmc_rxq rxq; 3171 void *hmc; 3172 3173 memset(&rxq, 0, sizeof(rxq)); 3174 3175 rxq.head = htole16(0); 3176 htolem64(&rxq.base, 3177 IXL_DMA_DVA(&rxr->rxr_mem) / IXL_HMC_RXQ_BASE_UNIT); 3178 htolem16(&rxq.qlen, sc->sc_rx_ring_ndescs); 3179 rxq.dbuff = htole16(MCLBYTES / IXL_HMC_RXQ_DBUFF_UNIT); 3180 rxq.hbuff = 0; 3181 rxq.dtype = IXL_HMC_RXQ_DTYPE_NOSPLIT; 3182 rxq.dsize = IXL_HMC_RXQ_DSIZE_16; 3183 rxq.crcstrip = 1; 3184 rxq.l2tsel = IXL_HMC_RXQ_L2TSEL_1ST_TAG_TO_L2TAG1; 3185 rxq.showiv = 0; 3186 rxq.rxmax = htole16(IXL_HARDMTU); 3187 rxq.tphrdesc_ena = 0; 3188 rxq.tphwdesc_ena = 0; 3189 rxq.tphdata_ena = 0; 3190 rxq.tphhead_ena = 0; 3191 rxq.lrxqthresh = 0; 3192 rxq.prefena = 1; 3193 3194 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_RX, rxr->rxr_qid); 3195 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_RX)); 3196 ixl_hmc_pack(hmc, &rxq, ixl_hmc_pack_rxq, nitems(ixl_hmc_pack_rxq)); 3197 } 3198 3199 static void 3200 ixl_rxr_unconfig(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3201 { 3202 void *hmc; 3203 3204 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_RX, rxr->rxr_qid); 3205 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_RX)); 3206 } 3207 3208 static void 3209 ixl_rxr_free(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3210 { 3211 struct ixl_rx_map *maps, *rxm; 3212 unsigned int i; 3213 3214 maps = rxr->rxr_maps; 3215 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3216 rxm = &maps[i]; 3217 3218 bus_dmamap_destroy(sc->sc_dmat, rxm->rxm_map); 3219 } 3220 3221 ixl_dmamem_free(sc, &rxr->rxr_mem); 3222 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_rx_ring_ndescs); 3223 free(rxr, M_DEVBUF, sizeof(*rxr)); 3224 } 3225 3226 static int 3227 ixl_rxeof(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3228 { 3229 struct ifiqueue *ifiq = rxr->rxr_ifiq; 3230 struct ifnet *ifp = &sc->sc_ac.ac_if; 3231 struct ixl_rx_wb_desc_16 *ring, *rxd; 3232 struct ixl_rx_map *rxm; 3233 bus_dmamap_t map; 3234 unsigned int cons, prod; 3235 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 3236 struct mbuf *m; 3237 uint64_t word; 3238 unsigned int len; 3239 unsigned int mask; 3240 int done = 0; 3241 3242 prod = rxr->rxr_prod; 3243 cons = rxr->rxr_cons; 3244 3245 if (cons == prod) 3246 return (0); 3247 3248 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 3249 0, IXL_DMA_LEN(&rxr->rxr_mem), 3250 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3251 3252 ring = IXL_DMA_KVA(&rxr->rxr_mem); 3253 mask = sc->sc_rx_ring_ndescs - 1; 3254 3255 do { 3256 rxd = &ring[cons]; 3257 3258 word = lemtoh64(&rxd->qword1); 3259 if (!ISSET(word, IXL_RX_DESC_DD)) 3260 break; 3261 3262 if_rxr_put(&rxr->rxr_acct, 1); 3263 3264 rxm = &rxr->rxr_maps[cons]; 3265 3266 map = rxm->rxm_map; 3267 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3268 BUS_DMASYNC_POSTREAD); 3269 bus_dmamap_unload(sc->sc_dmat, map); 3270 3271 m = rxm->rxm_m; 3272 rxm->rxm_m = NULL; 3273 3274 len = (word & IXL_RX_DESC_PLEN_MASK) >> IXL_RX_DESC_PLEN_SHIFT; 3275 m->m_len = len; 3276 m->m_pkthdr.len = 0; 3277 3278 m->m_next = NULL; 3279 *rxr->rxr_m_tail = m; 3280 rxr->rxr_m_tail = &m->m_next; 3281 3282 m = rxr->rxr_m_head; 3283 m->m_pkthdr.len += len; 3284 3285 if (ISSET(word, IXL_RX_DESC_EOP)) { 3286 if (!ISSET(word, 3287 IXL_RX_DESC_RXE | IXL_RX_DESC_OVERSIZE)) { 3288 if ((word & IXL_RX_DESC_FLTSTAT_MASK) == 3289 IXL_RX_DESC_FLTSTAT_RSS) { 3290 m->m_pkthdr.ph_flowid = 3291 lemtoh32(&rxd->filter_status); 3292 m->m_pkthdr.csum_flags |= M_FLOWID; 3293 } 3294 3295 if (ISSET(word, IXL_RX_DESC_L2TAG1P)) { 3296 m->m_pkthdr.ether_vtag = 3297 lemtoh16(&rxd->l2tag1); 3298 SET(m->m_flags, M_VLANTAG); 3299 } 3300 3301 ixl_rx_checksum(m, word); 3302 ml_enqueue(&ml, m); 3303 } else { 3304 ifp->if_ierrors++; /* XXX */ 3305 m_freem(m); 3306 } 3307 3308 rxr->rxr_m_head = NULL; 3309 rxr->rxr_m_tail = &rxr->rxr_m_head; 3310 } 3311 3312 cons++; 3313 cons &= mask; 3314 3315 done = 1; 3316 } while (cons != prod); 3317 3318 if (done) { 3319 rxr->rxr_cons = cons; 3320 if (ifiq_input(ifiq, &ml)) 3321 if_rxr_livelocked(&rxr->rxr_acct); 3322 ixl_rxfill(sc, rxr); 3323 } 3324 3325 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 3326 0, IXL_DMA_LEN(&rxr->rxr_mem), 3327 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3328 3329 return (done); 3330 } 3331 3332 static void 3333 ixl_rxfill(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3334 { 3335 struct ixl_rx_rd_desc_16 *ring, *rxd; 3336 struct ixl_rx_map *rxm; 3337 bus_dmamap_t map; 3338 struct mbuf *m; 3339 unsigned int prod; 3340 unsigned int slots; 3341 unsigned int mask; 3342 int post = 0; 3343 3344 slots = if_rxr_get(&rxr->rxr_acct, sc->sc_rx_ring_ndescs); 3345 if (slots == 0) 3346 return; 3347 3348 prod = rxr->rxr_prod; 3349 3350 ring = IXL_DMA_KVA(&rxr->rxr_mem); 3351 mask = sc->sc_rx_ring_ndescs - 1; 3352 3353 do { 3354 rxm = &rxr->rxr_maps[prod]; 3355 3356 m = MCLGETL(NULL, M_DONTWAIT, MCLBYTES + ETHER_ALIGN); 3357 if (m == NULL) 3358 break; 3359 m->m_data += (m->m_ext.ext_size - (MCLBYTES + ETHER_ALIGN)); 3360 m->m_len = m->m_pkthdr.len = MCLBYTES + ETHER_ALIGN; 3361 3362 map = rxm->rxm_map; 3363 3364 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 3365 BUS_DMA_NOWAIT) != 0) { 3366 m_freem(m); 3367 break; 3368 } 3369 3370 rxm->rxm_m = m; 3371 3372 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3373 BUS_DMASYNC_PREREAD); 3374 3375 rxd = &ring[prod]; 3376 3377 htolem64(&rxd->paddr, map->dm_segs[0].ds_addr); 3378 rxd->haddr = htole64(0); 3379 3380 prod++; 3381 prod &= mask; 3382 3383 post = 1; 3384 } while (--slots); 3385 3386 if_rxr_put(&rxr->rxr_acct, slots); 3387 3388 if (if_rxr_inuse(&rxr->rxr_acct) == 0) 3389 timeout_add(&rxr->rxr_refill, 1); 3390 else if (post) { 3391 rxr->rxr_prod = prod; 3392 ixl_wr(sc, rxr->rxr_tail, prod); 3393 } 3394 } 3395 3396 void 3397 ixl_rxrefill(void *arg) 3398 { 3399 struct ixl_rx_ring *rxr = arg; 3400 struct ixl_softc *sc = rxr->rxr_sc; 3401 3402 ixl_rxfill(sc, rxr); 3403 } 3404 3405 static int 3406 ixl_rxrinfo(struct ixl_softc *sc, struct if_rxrinfo *ifri) 3407 { 3408 struct ifnet *ifp = &sc->sc_ac.ac_if; 3409 struct if_rxring_info *ifr; 3410 struct ixl_rx_ring *ring; 3411 int i, rv; 3412 3413 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 3414 return (ENOTTY); 3415 3416 ifr = mallocarray(sizeof(*ifr), ixl_nqueues(sc), M_TEMP, 3417 M_WAITOK|M_CANFAIL|M_ZERO); 3418 if (ifr == NULL) 3419 return (ENOMEM); 3420 3421 for (i = 0; i < ixl_nqueues(sc); i++) { 3422 ring = ifp->if_iqs[i]->ifiq_softc; 3423 ifr[i].ifr_size = MCLBYTES; 3424 snprintf(ifr[i].ifr_name, sizeof(ifr[i].ifr_name), "%d", i); 3425 ifr[i].ifr_info = ring->rxr_acct; 3426 } 3427 3428 rv = if_rxr_info_ioctl(ifri, ixl_nqueues(sc), ifr); 3429 free(ifr, M_TEMP, ixl_nqueues(sc) * sizeof(*ifr)); 3430 3431 return (rv); 3432 } 3433 3434 static void 3435 ixl_rx_checksum(struct mbuf *m, uint64_t word) 3436 { 3437 if (!ISSET(word, IXL_RX_DESC_L3L4P)) 3438 return; 3439 3440 if (ISSET(word, IXL_RX_DESC_IPE)) 3441 return; 3442 3443 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 3444 3445 if (ISSET(word, IXL_RX_DESC_L4E)) 3446 return; 3447 3448 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 3449 } 3450 3451 static int 3452 ixl_intr0(void *xsc) 3453 { 3454 struct ixl_softc *sc = xsc; 3455 struct ifnet *ifp = &sc->sc_ac.ac_if; 3456 uint32_t icr; 3457 int rv = 0; 3458 3459 ixl_intr_enable(sc); 3460 icr = ixl_rd(sc, I40E_PFINT_ICR0); 3461 3462 if (ISSET(icr, I40E_PFINT_ICR0_ADMINQ_MASK)) { 3463 ixl_atq_done(sc); 3464 task_add(systq, &sc->sc_arq_task); 3465 rv = 1; 3466 } 3467 3468 if (ISSET(icr, I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK)) { 3469 task_add(systq, &sc->sc_link_state_task); 3470 rv = 1; 3471 } 3472 3473 if (ISSET(ifp->if_flags, IFF_RUNNING)) { 3474 struct ixl_vector *iv = sc->sc_vectors; 3475 if (ISSET(icr, I40E_INTR_NOTX_RX_MASK)) 3476 rv |= ixl_rxeof(sc, iv->iv_rxr); 3477 if (ISSET(icr, I40E_INTR_NOTX_TX_MASK)) 3478 rv |= ixl_txeof(sc, iv->iv_txr); 3479 } 3480 3481 return (rv); 3482 } 3483 3484 static int 3485 ixl_intr_vector(void *v) 3486 { 3487 struct ixl_vector *iv = v; 3488 struct ixl_softc *sc = iv->iv_sc; 3489 struct ifnet *ifp = &sc->sc_ac.ac_if; 3490 int rv = 0; 3491 3492 if (ISSET(ifp->if_flags, IFF_RUNNING)) { 3493 rv |= ixl_rxeof(sc, iv->iv_rxr); 3494 rv |= ixl_txeof(sc, iv->iv_txr); 3495 } 3496 3497 ixl_wr(sc, I40E_PFINT_DYN_CTLN(iv->iv_qid), 3498 I40E_PFINT_DYN_CTLN_INTENA_MASK | 3499 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 3500 (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)); 3501 3502 return (rv); 3503 } 3504 3505 static void 3506 ixl_link_state_update_iaq(struct ixl_softc *sc, void *arg) 3507 { 3508 struct ifnet *ifp = &sc->sc_ac.ac_if; 3509 struct ixl_aq_desc *iaq = arg; 3510 uint16_t retval; 3511 int link_state; 3512 int change = 0; 3513 3514 retval = lemtoh16(&iaq->iaq_retval); 3515 if (retval != IXL_AQ_RC_OK) { 3516 printf("%s: LINK STATUS error %u\n", DEVNAME(sc), retval); 3517 return; 3518 } 3519 3520 link_state = ixl_set_link_status(sc, iaq); 3521 mtx_enter(&sc->sc_link_state_mtx); 3522 if (ifp->if_link_state != link_state) { 3523 ifp->if_link_state = link_state; 3524 change = 1; 3525 } 3526 mtx_leave(&sc->sc_link_state_mtx); 3527 3528 if (change) 3529 if_link_state_change(ifp); 3530 } 3531 3532 static void 3533 ixl_link_state_update(void *xsc) 3534 { 3535 struct ixl_softc *sc = xsc; 3536 struct ixl_aq_desc *iaq; 3537 struct ixl_aq_link_param *param; 3538 3539 memset(&sc->sc_link_state_atq, 0, sizeof(sc->sc_link_state_atq)); 3540 iaq = &sc->sc_link_state_atq.iatq_desc; 3541 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS); 3542 param = (struct ixl_aq_link_param *)iaq->iaq_param; 3543 param->notify = IXL_AQ_LINK_NOTIFY; 3544 3545 ixl_atq_set(&sc->sc_link_state_atq, ixl_link_state_update_iaq, iaq); 3546 ixl_atq_post(sc, &sc->sc_link_state_atq); 3547 } 3548 3549 #if 0 3550 static void 3551 ixl_aq_dump(const struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 3552 { 3553 printf("%s: flags %b opcode %04x\n", DEVNAME(sc), 3554 lemtoh16(&iaq->iaq_flags), IXL_AQ_FLAGS_FMT, 3555 lemtoh16(&iaq->iaq_opcode)); 3556 printf("%s: datalen %u retval %u\n", DEVNAME(sc), 3557 lemtoh16(&iaq->iaq_datalen), lemtoh16(&iaq->iaq_retval)); 3558 printf("%s: cookie %016llx\n", DEVNAME(sc), iaq->iaq_cookie); 3559 printf("%s: %08x %08x %08x %08x\n", DEVNAME(sc), 3560 lemtoh32(&iaq->iaq_param[0]), lemtoh32(&iaq->iaq_param[1]), 3561 lemtoh32(&iaq->iaq_param[2]), lemtoh32(&iaq->iaq_param[3])); 3562 } 3563 #endif 3564 3565 static void 3566 ixl_arq(void *xsc) 3567 { 3568 struct ixl_softc *sc = xsc; 3569 struct ixl_aq_desc *arq, *iaq; 3570 struct ixl_aq_buf *aqb; 3571 unsigned int cons = sc->sc_arq_cons; 3572 unsigned int prod; 3573 int done = 0; 3574 3575 prod = ixl_rd(sc, sc->sc_aq_regs->arq_head) & 3576 sc->sc_aq_regs->arq_head_mask; 3577 3578 if (cons == prod) 3579 goto done; 3580 3581 arq = IXL_DMA_KVA(&sc->sc_arq); 3582 3583 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3584 0, IXL_DMA_LEN(&sc->sc_arq), 3585 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3586 3587 do { 3588 iaq = &arq[cons]; 3589 3590 aqb = SIMPLEQ_FIRST(&sc->sc_arq_live); 3591 SIMPLEQ_REMOVE_HEAD(&sc->sc_arq_live, aqb_entry); 3592 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IXL_AQ_BUFLEN, 3593 BUS_DMASYNC_POSTREAD); 3594 3595 switch (iaq->iaq_opcode) { 3596 case HTOLE16(IXL_AQ_OP_PHY_LINK_STATUS): 3597 ixl_link_state_update_iaq(sc, iaq); 3598 break; 3599 } 3600 3601 memset(iaq, 0, sizeof(*iaq)); 3602 SIMPLEQ_INSERT_TAIL(&sc->sc_arq_idle, aqb, aqb_entry); 3603 if_rxr_put(&sc->sc_arq_ring, 1); 3604 3605 cons++; 3606 cons &= IXL_AQ_MASK; 3607 3608 done = 1; 3609 } while (cons != prod); 3610 3611 if (done && ixl_arq_fill(sc)) 3612 ixl_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 3613 3614 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3615 0, IXL_DMA_LEN(&sc->sc_arq), 3616 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3617 3618 sc->sc_arq_cons = cons; 3619 3620 done: 3621 ixl_intr_enable(sc); 3622 } 3623 3624 static void 3625 ixl_atq_set(struct ixl_atq *iatq, 3626 void (*fn)(struct ixl_softc *, void *), void *arg) 3627 { 3628 iatq->iatq_fn = fn; 3629 iatq->iatq_arg = arg; 3630 } 3631 3632 static void 3633 ixl_atq_post(struct ixl_softc *sc, struct ixl_atq *iatq) 3634 { 3635 struct ixl_aq_desc *atq, *slot; 3636 unsigned int prod; 3637 3638 /* assert locked */ 3639 3640 atq = IXL_DMA_KVA(&sc->sc_atq); 3641 prod = sc->sc_atq_prod; 3642 slot = atq + prod; 3643 3644 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3645 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 3646 3647 *slot = iatq->iatq_desc; 3648 slot->iaq_cookie = (uint64_t)iatq; 3649 3650 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3651 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 3652 3653 prod++; 3654 prod &= IXL_AQ_MASK; 3655 sc->sc_atq_prod = prod; 3656 ixl_wr(sc, sc->sc_aq_regs->atq_tail, prod); 3657 } 3658 3659 static void 3660 ixl_atq_done(struct ixl_softc *sc) 3661 { 3662 struct ixl_aq_desc *atq, *slot; 3663 struct ixl_atq *iatq; 3664 unsigned int cons; 3665 unsigned int prod; 3666 3667 prod = sc->sc_atq_prod; 3668 cons = sc->sc_atq_cons; 3669 3670 if (prod == cons) 3671 return; 3672 3673 atq = IXL_DMA_KVA(&sc->sc_atq); 3674 3675 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3676 0, IXL_DMA_LEN(&sc->sc_atq), 3677 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3678 3679 do { 3680 slot = &atq[cons]; 3681 if (!ISSET(slot->iaq_flags, htole16(IXL_AQ_DD))) 3682 break; 3683 3684 iatq = (struct ixl_atq *)slot->iaq_cookie; 3685 iatq->iatq_desc = *slot; 3686 3687 memset(slot, 0, sizeof(*slot)); 3688 3689 (*iatq->iatq_fn)(sc, iatq->iatq_arg); 3690 3691 cons++; 3692 cons &= IXL_AQ_MASK; 3693 } while (cons != prod); 3694 3695 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3696 0, IXL_DMA_LEN(&sc->sc_atq), 3697 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3698 3699 sc->sc_atq_cons = cons; 3700 } 3701 3702 static void 3703 ixl_wakeup(struct ixl_softc *sc, void *arg) 3704 { 3705 struct cond *c = arg; 3706 3707 cond_signal(c); 3708 } 3709 3710 static void 3711 ixl_atq_exec(struct ixl_softc *sc, struct ixl_atq *iatq, const char *wmesg) 3712 { 3713 struct cond c = COND_INITIALIZER(); 3714 3715 KASSERT(iatq->iatq_desc.iaq_cookie == 0); 3716 3717 ixl_atq_set(iatq, ixl_wakeup, &c); 3718 ixl_atq_post(sc, iatq); 3719 3720 cond_wait(&c, wmesg); 3721 } 3722 3723 static int 3724 ixl_atq_poll(struct ixl_softc *sc, struct ixl_aq_desc *iaq, unsigned int tm) 3725 { 3726 struct ixl_aq_desc *atq, *slot; 3727 unsigned int prod; 3728 unsigned int t = 0; 3729 3730 atq = IXL_DMA_KVA(&sc->sc_atq); 3731 prod = sc->sc_atq_prod; 3732 slot = atq + prod; 3733 3734 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3735 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 3736 3737 *slot = *iaq; 3738 slot->iaq_flags |= htole16(IXL_AQ_SI); 3739 3740 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3741 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 3742 3743 prod++; 3744 prod &= IXL_AQ_MASK; 3745 sc->sc_atq_prod = prod; 3746 ixl_wr(sc, sc->sc_aq_regs->atq_tail, prod); 3747 3748 while (ixl_rd(sc, sc->sc_aq_regs->atq_head) != prod) { 3749 delaymsec(1); 3750 3751 if (t++ > tm) 3752 return (ETIMEDOUT); 3753 } 3754 3755 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3756 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTREAD); 3757 *iaq = *slot; 3758 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3759 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREREAD); 3760 3761 sc->sc_atq_cons = prod; 3762 3763 return (0); 3764 } 3765 3766 static int 3767 ixl_get_version(struct ixl_softc *sc) 3768 { 3769 struct ixl_aq_desc iaq; 3770 uint32_t fwbuild, fwver, apiver; 3771 3772 memset(&iaq, 0, sizeof(iaq)); 3773 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VERSION); 3774 3775 if (ixl_atq_poll(sc, &iaq, 2000) != 0) 3776 return (ETIMEDOUT); 3777 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) 3778 return (EIO); 3779 3780 fwbuild = lemtoh32(&iaq.iaq_param[1]); 3781 fwver = lemtoh32(&iaq.iaq_param[2]); 3782 apiver = lemtoh32(&iaq.iaq_param[3]); 3783 3784 sc->sc_api_major = apiver & 0xffff; 3785 sc->sc_api_minor = (apiver >> 16) & 0xffff; 3786 3787 printf(", FW %hu.%hu.%05u API %hu.%hu", (uint16_t)fwver, 3788 (uint16_t)(fwver >> 16), fwbuild, 3789 sc->sc_api_major, sc->sc_api_minor); 3790 3791 return (0); 3792 } 3793 3794 static int 3795 ixl_pxe_clear(struct ixl_softc *sc) 3796 { 3797 struct ixl_aq_desc iaq; 3798 3799 memset(&iaq, 0, sizeof(iaq)); 3800 iaq.iaq_opcode = htole16(IXL_AQ_OP_CLEAR_PXE_MODE); 3801 iaq.iaq_param[0] = htole32(0x2); 3802 3803 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 3804 printf(", CLEAR PXE MODE timeout\n"); 3805 return (-1); 3806 } 3807 3808 switch (iaq.iaq_retval) { 3809 case HTOLE16(IXL_AQ_RC_OK): 3810 case HTOLE16(IXL_AQ_RC_EEXIST): 3811 break; 3812 default: 3813 printf(", CLEAR PXE MODE error\n"); 3814 return (-1); 3815 } 3816 3817 return (0); 3818 } 3819 3820 static int 3821 ixl_lldp_shut(struct ixl_softc *sc) 3822 { 3823 struct ixl_aq_desc iaq; 3824 3825 memset(&iaq, 0, sizeof(iaq)); 3826 iaq.iaq_opcode = htole16(IXL_AQ_OP_LLDP_STOP_AGENT); 3827 iaq.iaq_param[0] = htole32(IXL_LLDP_SHUTDOWN); 3828 3829 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 3830 printf(", STOP LLDP AGENT timeout\n"); 3831 return (-1); 3832 } 3833 3834 switch (iaq.iaq_retval) { 3835 case HTOLE16(IXL_AQ_RC_EMODE): 3836 case HTOLE16(IXL_AQ_RC_EPERM): 3837 /* ignore silently */ 3838 default: 3839 break; 3840 } 3841 3842 return (0); 3843 } 3844 3845 static int 3846 ixl_get_mac(struct ixl_softc *sc) 3847 { 3848 struct ixl_dmamem idm; 3849 struct ixl_aq_desc iaq; 3850 struct ixl_aq_mac_addresses *addrs; 3851 int rv; 3852 3853 #ifdef __sparc64__ 3854 if (OF_getprop(PCITAG_NODE(sc->sc_tag), "local-mac-address", 3855 sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN) == ETHER_ADDR_LEN) 3856 return (0); 3857 #endif 3858 3859 if (ixl_dmamem_alloc(sc, &idm, sizeof(*addrs), 0) != 0) { 3860 printf(", unable to allocate mac addresses\n"); 3861 return (-1); 3862 } 3863 3864 memset(&iaq, 0, sizeof(iaq)); 3865 iaq.iaq_flags = htole16(IXL_AQ_BUF); 3866 iaq.iaq_opcode = htole16(IXL_AQ_OP_MAC_ADDRESS_READ); 3867 iaq.iaq_datalen = htole16(sizeof(*addrs)); 3868 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 3869 3870 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3871 BUS_DMASYNC_PREREAD); 3872 3873 rv = ixl_atq_poll(sc, &iaq, 250); 3874 3875 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3876 BUS_DMASYNC_POSTREAD); 3877 3878 if (rv != 0) { 3879 printf(", MAC ADDRESS READ timeout\n"); 3880 rv = -1; 3881 goto done; 3882 } 3883 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 3884 printf(", MAC ADDRESS READ error\n"); 3885 rv = -1; 3886 goto done; 3887 } 3888 3889 addrs = IXL_DMA_KVA(&idm); 3890 if (!ISSET(iaq.iaq_param[0], htole32(IXL_AQ_MAC_PORT_VALID))) { 3891 printf(", port address is not valid\n"); 3892 goto done; 3893 } 3894 3895 memcpy(sc->sc_ac.ac_enaddr, addrs->port, ETHER_ADDR_LEN); 3896 rv = 0; 3897 3898 done: 3899 ixl_dmamem_free(sc, &idm); 3900 return (rv); 3901 } 3902 3903 static int 3904 ixl_get_switch_config(struct ixl_softc *sc) 3905 { 3906 struct ixl_dmamem idm; 3907 struct ixl_aq_desc iaq; 3908 struct ixl_aq_switch_config *hdr; 3909 struct ixl_aq_switch_config_element *elms, *elm; 3910 unsigned int nelm; 3911 int rv; 3912 3913 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) { 3914 printf("%s: unable to allocate switch config buffer\n", 3915 DEVNAME(sc)); 3916 return (-1); 3917 } 3918 3919 memset(&iaq, 0, sizeof(iaq)); 3920 iaq.iaq_flags = htole16(IXL_AQ_BUF | 3921 (IXL_AQ_BUFLEN > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 3922 iaq.iaq_opcode = htole16(IXL_AQ_OP_SWITCH_GET_CONFIG); 3923 iaq.iaq_datalen = htole16(IXL_AQ_BUFLEN); 3924 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 3925 3926 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3927 BUS_DMASYNC_PREREAD); 3928 3929 rv = ixl_atq_poll(sc, &iaq, 250); 3930 3931 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3932 BUS_DMASYNC_POSTREAD); 3933 3934 if (rv != 0) { 3935 printf("%s: GET SWITCH CONFIG timeout\n", DEVNAME(sc)); 3936 rv = -1; 3937 goto done; 3938 } 3939 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 3940 printf("%s: GET SWITCH CONFIG error\n", DEVNAME(sc)); 3941 rv = -1; 3942 goto done; 3943 } 3944 3945 hdr = IXL_DMA_KVA(&idm); 3946 elms = (struct ixl_aq_switch_config_element *)(hdr + 1); 3947 3948 nelm = lemtoh16(&hdr->num_reported); 3949 if (nelm < 1) { 3950 printf("%s: no switch config available\n", DEVNAME(sc)); 3951 rv = -1; 3952 goto done; 3953 } 3954 3955 #if 0 3956 for (i = 0; i < nelm; i++) { 3957 elm = &elms[i]; 3958 3959 printf("%s: type %x revision %u seid %04x\n", DEVNAME(sc), 3960 elm->type, elm->revision, lemtoh16(&elm->seid)); 3961 printf("%s: uplink %04x downlink %04x\n", DEVNAME(sc), 3962 lemtoh16(&elm->uplink_seid), 3963 lemtoh16(&elm->downlink_seid)); 3964 printf("%s: conntype %x scheduler %04x extra %04x\n", 3965 DEVNAME(sc), elm->connection_type, 3966 lemtoh16(&elm->scheduler_id), 3967 lemtoh16(&elm->element_info)); 3968 } 3969 #endif 3970 3971 elm = &elms[0]; 3972 3973 sc->sc_uplink_seid = elm->uplink_seid; 3974 sc->sc_downlink_seid = elm->downlink_seid; 3975 sc->sc_seid = elm->seid; 3976 3977 if ((sc->sc_uplink_seid == htole16(0)) != 3978 (sc->sc_downlink_seid == htole16(0))) { 3979 printf("%s: SEIDs are misconfigured\n", DEVNAME(sc)); 3980 rv = -1; 3981 goto done; 3982 } 3983 3984 done: 3985 ixl_dmamem_free(sc, &idm); 3986 return (rv); 3987 } 3988 3989 static int 3990 ixl_phy_mask_ints(struct ixl_softc *sc) 3991 { 3992 struct ixl_aq_desc iaq; 3993 3994 memset(&iaq, 0, sizeof(iaq)); 3995 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_EVENT_MASK); 3996 iaq.iaq_param[2] = htole32(IXL_AQ_PHY_EV_MASK & 3997 ~(IXL_AQ_PHY_EV_LINK_UPDOWN | IXL_AQ_PHY_EV_MODULE_QUAL_FAIL | 3998 IXL_AQ_PHY_EV_MEDIA_NA)); 3999 4000 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4001 printf("%s: SET PHY EVENT MASK timeout\n", DEVNAME(sc)); 4002 return (-1); 4003 } 4004 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4005 printf("%s: SET PHY EVENT MASK error\n", DEVNAME(sc)); 4006 return (-1); 4007 } 4008 4009 return (0); 4010 } 4011 4012 static int 4013 ixl_get_phy_abilities(struct ixl_softc *sc,struct ixl_dmamem *idm) 4014 { 4015 struct ixl_aq_desc iaq; 4016 int rv; 4017 4018 memset(&iaq, 0, sizeof(iaq)); 4019 iaq.iaq_flags = htole16(IXL_AQ_BUF | 4020 (IXL_DMA_LEN(idm) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4021 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_GET_ABILITIES); 4022 htolem16(&iaq.iaq_datalen, IXL_DMA_LEN(idm)); 4023 iaq.iaq_param[0] = htole32(IXL_AQ_PHY_REPORT_INIT); 4024 ixl_aq_dva(&iaq, IXL_DMA_DVA(idm)); 4025 4026 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 4027 BUS_DMASYNC_PREREAD); 4028 4029 rv = ixl_atq_poll(sc, &iaq, 250); 4030 4031 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 4032 BUS_DMASYNC_POSTREAD); 4033 4034 if (rv != 0) 4035 return (-1); 4036 4037 return (lemtoh16(&iaq.iaq_retval)); 4038 } 4039 4040 static int 4041 ixl_get_phy_types(struct ixl_softc *sc, uint64_t *phy_types_ptr) 4042 { 4043 struct ixl_dmamem idm; 4044 struct ixl_aq_phy_abilities *phy; 4045 uint64_t phy_types; 4046 int rv; 4047 4048 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) { 4049 printf("%s: unable to allocate phy abilities buffer\n", 4050 DEVNAME(sc)); 4051 return (-1); 4052 } 4053 4054 rv = ixl_get_phy_abilities(sc, &idm); 4055 switch (rv) { 4056 case -1: 4057 printf("%s: GET PHY ABILITIES timeout\n", DEVNAME(sc)); 4058 goto err; 4059 case IXL_AQ_RC_OK: 4060 break; 4061 case IXL_AQ_RC_EIO: 4062 /* API is too old to handle this command */ 4063 phy_types = 0; 4064 goto done; 4065 default: 4066 printf("%s: GET PHY ABILITIES error %u\n", DEVNAME(sc), rv); 4067 goto err; 4068 } 4069 4070 phy = IXL_DMA_KVA(&idm); 4071 4072 phy_types = lemtoh32(&phy->phy_type); 4073 phy_types |= (uint64_t)phy->phy_type_ext << 32; 4074 4075 done: 4076 *phy_types_ptr = phy_types; 4077 4078 rv = 0; 4079 4080 err: 4081 ixl_dmamem_free(sc, &idm); 4082 return (rv); 4083 } 4084 4085 /* 4086 * this returns -2 on software/driver failure, -1 for problems 4087 * talking to the hardware, or the sff module type. 4088 */ 4089 4090 static int 4091 ixl_get_module_type(struct ixl_softc *sc) 4092 { 4093 struct ixl_dmamem idm; 4094 struct ixl_aq_phy_abilities *phy; 4095 int rv; 4096 4097 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) 4098 return (-2); 4099 4100 rv = ixl_get_phy_abilities(sc, &idm); 4101 if (rv != IXL_AQ_RC_OK) { 4102 rv = -1; 4103 goto done; 4104 } 4105 4106 phy = IXL_DMA_KVA(&idm); 4107 4108 rv = phy->module_type[0]; 4109 4110 done: 4111 ixl_dmamem_free(sc, &idm); 4112 return (rv); 4113 } 4114 4115 static int 4116 ixl_get_link_status(struct ixl_softc *sc) 4117 { 4118 struct ixl_aq_desc iaq; 4119 struct ixl_aq_link_param *param; 4120 4121 memset(&iaq, 0, sizeof(iaq)); 4122 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS); 4123 param = (struct ixl_aq_link_param *)iaq.iaq_param; 4124 param->notify = IXL_AQ_LINK_NOTIFY; 4125 4126 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4127 printf("%s: GET LINK STATUS timeout\n", DEVNAME(sc)); 4128 return (-1); 4129 } 4130 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4131 printf("%s: GET LINK STATUS error\n", DEVNAME(sc)); 4132 return (0); 4133 } 4134 4135 sc->sc_ac.ac_if.if_link_state = ixl_set_link_status(sc, &iaq); 4136 4137 return (0); 4138 } 4139 4140 struct ixl_sff_ops { 4141 int (*open)(struct ixl_softc *sc, struct if_sffpage *, uint8_t *); 4142 int (*get)(struct ixl_softc *sc, struct if_sffpage *, size_t); 4143 int (*close)(struct ixl_softc *sc, struct if_sffpage *, uint8_t); 4144 }; 4145 4146 static int 4147 ixl_sfp_open(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t *page) 4148 { 4149 int error; 4150 4151 if (sff->sff_addr != IFSFF_ADDR_EEPROM) 4152 return (0); 4153 4154 error = ixl_sff_get_byte(sc, IFSFF_ADDR_EEPROM, 127, page); 4155 if (error != 0) 4156 return (error); 4157 if (*page == sff->sff_page) 4158 return (0); 4159 error = ixl_sff_set_byte(sc, IFSFF_ADDR_EEPROM, 127, sff->sff_page); 4160 if (error != 0) 4161 return (error); 4162 4163 return (0); 4164 } 4165 4166 static int 4167 ixl_sfp_get(struct ixl_softc *sc, struct if_sffpage *sff, size_t i) 4168 { 4169 return (ixl_sff_get_byte(sc, sff->sff_addr, i, &sff->sff_data[i])); 4170 } 4171 4172 static int 4173 ixl_sfp_close(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t page) 4174 { 4175 int error; 4176 4177 if (sff->sff_addr != IFSFF_ADDR_EEPROM) 4178 return (0); 4179 4180 if (page == sff->sff_page) 4181 return (0); 4182 4183 error = ixl_sff_set_byte(sc, IFSFF_ADDR_EEPROM, 127, page); 4184 if (error != 0) 4185 return (error); 4186 4187 return (0); 4188 } 4189 4190 static const struct ixl_sff_ops ixl_sfp_ops = { 4191 ixl_sfp_open, 4192 ixl_sfp_get, 4193 ixl_sfp_close, 4194 }; 4195 4196 static int 4197 ixl_qsfp_open(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t *page) 4198 { 4199 if (sff->sff_addr != IFSFF_ADDR_EEPROM) 4200 return (EIO); 4201 4202 return (0); 4203 } 4204 4205 static int 4206 ixl_qsfp_get(struct ixl_softc *sc, struct if_sffpage *sff, size_t i) 4207 { 4208 return (ixl_sff_get_byte(sc, sff->sff_page, i, &sff->sff_data[i])); 4209 } 4210 4211 static int 4212 ixl_qsfp_close(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t page) 4213 { 4214 return (0); 4215 } 4216 4217 static const struct ixl_sff_ops ixl_qsfp_ops = { 4218 ixl_qsfp_open, 4219 ixl_qsfp_get, 4220 ixl_qsfp_close, 4221 }; 4222 4223 static int 4224 ixl_get_sffpage(struct ixl_softc *sc, struct if_sffpage *sff) 4225 { 4226 const struct ixl_sff_ops *ops; 4227 uint8_t page; 4228 size_t i; 4229 int error; 4230 4231 switch (ixl_get_module_type(sc)) { 4232 case -2: 4233 return (ENOMEM); 4234 case -1: 4235 return (ENXIO); 4236 case IXL_SFF8024_ID_SFP: 4237 ops = &ixl_sfp_ops; 4238 break; 4239 case IXL_SFF8024_ID_QSFP: 4240 case IXL_SFF8024_ID_QSFP_PLUS: 4241 case IXL_SFF8024_ID_QSFP28: 4242 ops = &ixl_qsfp_ops; 4243 break; 4244 default: 4245 return (EOPNOTSUPP); 4246 } 4247 4248 error = (*ops->open)(sc, sff, &page); 4249 if (error != 0) 4250 return (error); 4251 4252 for (i = 0; i < sizeof(sff->sff_data); i++) { 4253 error = (*ops->get)(sc, sff, i); 4254 if (error != 0) 4255 return (error); 4256 } 4257 4258 error = (*ops->close)(sc, sff, page); 4259 4260 return (0); 4261 } 4262 4263 static int 4264 ixl_sff_get_byte(struct ixl_softc *sc, uint8_t dev, uint32_t reg, uint8_t *p) 4265 { 4266 struct ixl_atq iatq; 4267 struct ixl_aq_desc *iaq; 4268 struct ixl_aq_phy_reg_access *param; 4269 4270 memset(&iatq, 0, sizeof(iatq)); 4271 iaq = &iatq.iatq_desc; 4272 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_GET_REGISTER); 4273 param = (struct ixl_aq_phy_reg_access *)iaq->iaq_param; 4274 param->phy_iface = IXL_AQ_PHY_IF_MODULE; 4275 param->dev_addr = dev; 4276 htolem32(¶m->reg, reg); 4277 4278 ixl_atq_exec(sc, &iatq, "ixlsffget"); 4279 4280 if (ISSET(sc->sc_ac.ac_if.if_flags, IFF_DEBUG)) { 4281 printf("%s: %s(dev 0x%02x, reg 0x%02x) -> %04x\n", 4282 DEVNAME(sc), __func__, 4283 dev, reg, lemtoh16(&iaq->iaq_retval)); 4284 } 4285 4286 switch (iaq->iaq_retval) { 4287 case htole16(IXL_AQ_RC_OK): 4288 break; 4289 case htole16(IXL_AQ_RC_EBUSY): 4290 return (EBUSY); 4291 case htole16(IXL_AQ_RC_ESRCH): 4292 return (ENODEV); 4293 case htole16(IXL_AQ_RC_EIO): 4294 case htole16(IXL_AQ_RC_EINVAL): 4295 default: 4296 return (EIO); 4297 } 4298 4299 *p = lemtoh32(¶m->val); 4300 4301 return (0); 4302 } 4303 4304 static int 4305 ixl_sff_set_byte(struct ixl_softc *sc, uint8_t dev, uint32_t reg, uint8_t v) 4306 { 4307 struct ixl_atq iatq; 4308 struct ixl_aq_desc *iaq; 4309 struct ixl_aq_phy_reg_access *param; 4310 4311 memset(&iatq, 0, sizeof(iatq)); 4312 iaq = &iatq.iatq_desc; 4313 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_REGISTER); 4314 param = (struct ixl_aq_phy_reg_access *)iaq->iaq_param; 4315 param->phy_iface = IXL_AQ_PHY_IF_MODULE; 4316 param->dev_addr = dev; 4317 htolem32(¶m->reg, reg); 4318 htolem32(¶m->val, v); 4319 4320 ixl_atq_exec(sc, &iatq, "ixlsffset"); 4321 4322 if (ISSET(sc->sc_ac.ac_if.if_flags, IFF_DEBUG)) { 4323 printf("%s: %s(dev 0x%02x, reg 0x%02x, val 0x%02x) -> %04x\n", 4324 DEVNAME(sc), __func__, 4325 dev, reg, v, lemtoh16(&iaq->iaq_retval)); 4326 } 4327 4328 switch (iaq->iaq_retval) { 4329 case htole16(IXL_AQ_RC_OK): 4330 break; 4331 case htole16(IXL_AQ_RC_EBUSY): 4332 return (EBUSY); 4333 case htole16(IXL_AQ_RC_ESRCH): 4334 return (ENODEV); 4335 case htole16(IXL_AQ_RC_EIO): 4336 case htole16(IXL_AQ_RC_EINVAL): 4337 default: 4338 return (EIO); 4339 } 4340 4341 return (0); 4342 } 4343 4344 static int 4345 ixl_get_vsi(struct ixl_softc *sc) 4346 { 4347 struct ixl_dmamem *vsi = &sc->sc_scratch; 4348 struct ixl_aq_desc iaq; 4349 struct ixl_aq_vsi_param *param; 4350 struct ixl_aq_vsi_reply *reply; 4351 int rv; 4352 4353 /* grumble, vsi info isn't "known" at compile time */ 4354 4355 memset(&iaq, 0, sizeof(iaq)); 4356 htolem16(&iaq.iaq_flags, IXL_AQ_BUF | 4357 (IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4358 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VSI_PARAMS); 4359 htolem16(&iaq.iaq_datalen, IXL_DMA_LEN(vsi)); 4360 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi)); 4361 4362 param = (struct ixl_aq_vsi_param *)iaq.iaq_param; 4363 param->uplink_seid = sc->sc_seid; 4364 4365 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4366 BUS_DMASYNC_PREREAD); 4367 4368 rv = ixl_atq_poll(sc, &iaq, 250); 4369 4370 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4371 BUS_DMASYNC_POSTREAD); 4372 4373 if (rv != 0) { 4374 printf("%s: GET VSI timeout\n", DEVNAME(sc)); 4375 return (-1); 4376 } 4377 4378 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4379 printf("%s: GET VSI error %u\n", DEVNAME(sc), 4380 lemtoh16(&iaq.iaq_retval)); 4381 return (-1); 4382 } 4383 4384 reply = (struct ixl_aq_vsi_reply *)iaq.iaq_param; 4385 sc->sc_vsi_number = reply->vsi_number; 4386 4387 return (0); 4388 } 4389 4390 static int 4391 ixl_set_vsi(struct ixl_softc *sc) 4392 { 4393 struct ixl_dmamem *vsi = &sc->sc_scratch; 4394 struct ixl_aq_desc iaq; 4395 struct ixl_aq_vsi_param *param; 4396 struct ixl_aq_vsi_data *data = IXL_DMA_KVA(vsi); 4397 int rv; 4398 4399 data->valid_sections = htole16(IXL_AQ_VSI_VALID_QUEUE_MAP | 4400 IXL_AQ_VSI_VALID_VLAN); 4401 4402 CLR(data->mapping_flags, htole16(IXL_AQ_VSI_QUE_MAP_MASK)); 4403 SET(data->mapping_flags, htole16(IXL_AQ_VSI_QUE_MAP_CONTIG)); 4404 data->queue_mapping[0] = htole16(0); 4405 data->tc_mapping[0] = htole16((0 << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) | 4406 (sc->sc_nqueues << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT)); 4407 4408 CLR(data->port_vlan_flags, 4409 htole16(IXL_AQ_VSI_PVLAN_MODE_MASK | IXL_AQ_VSI_PVLAN_EMOD_MASK)); 4410 SET(data->port_vlan_flags, htole16(IXL_AQ_VSI_PVLAN_MODE_ALL | 4411 IXL_AQ_VSI_PVLAN_EMOD_STR_BOTH)); 4412 4413 /* grumble, vsi info isn't "known" at compile time */ 4414 4415 memset(&iaq, 0, sizeof(iaq)); 4416 htolem16(&iaq.iaq_flags, IXL_AQ_BUF | IXL_AQ_RD | 4417 (IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4418 iaq.iaq_opcode = htole16(IXL_AQ_OP_UPD_VSI_PARAMS); 4419 htolem16(&iaq.iaq_datalen, IXL_DMA_LEN(vsi)); 4420 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi)); 4421 4422 param = (struct ixl_aq_vsi_param *)iaq.iaq_param; 4423 param->uplink_seid = sc->sc_seid; 4424 4425 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4426 BUS_DMASYNC_PREWRITE); 4427 4428 rv = ixl_atq_poll(sc, &iaq, 250); 4429 4430 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4431 BUS_DMASYNC_POSTWRITE); 4432 4433 if (rv != 0) { 4434 printf("%s: UPDATE VSI timeout\n", DEVNAME(sc)); 4435 return (-1); 4436 } 4437 4438 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4439 printf("%s: UPDATE VSI error %u\n", DEVNAME(sc), 4440 lemtoh16(&iaq.iaq_retval)); 4441 return (-1); 4442 } 4443 4444 return (0); 4445 } 4446 4447 static const struct ixl_phy_type * 4448 ixl_search_phy_type(uint8_t phy_type) 4449 { 4450 const struct ixl_phy_type *itype; 4451 uint64_t mask; 4452 unsigned int i; 4453 4454 if (phy_type >= 64) 4455 return (NULL); 4456 4457 mask = 1ULL << phy_type; 4458 4459 for (i = 0; i < nitems(ixl_phy_type_map); i++) { 4460 itype = &ixl_phy_type_map[i]; 4461 4462 if (ISSET(itype->phy_type, mask)) 4463 return (itype); 4464 } 4465 4466 return (NULL); 4467 } 4468 4469 static uint64_t 4470 ixl_search_link_speed(uint8_t link_speed) 4471 { 4472 const struct ixl_speed_type *type; 4473 unsigned int i; 4474 4475 for (i = 0; i < nitems(ixl_speed_type_map); i++) { 4476 type = &ixl_speed_type_map[i]; 4477 4478 if (ISSET(type->dev_speed, link_speed)) 4479 return (type->net_speed); 4480 } 4481 4482 return (0); 4483 } 4484 4485 static int 4486 ixl_set_link_status(struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 4487 { 4488 const struct ixl_aq_link_status *status; 4489 const struct ixl_phy_type *itype; 4490 4491 uint64_t ifm_active = IFM_ETHER; 4492 uint64_t ifm_status = IFM_AVALID; 4493 int link_state = LINK_STATE_DOWN; 4494 uint64_t baudrate = 0; 4495 4496 status = (const struct ixl_aq_link_status *)iaq->iaq_param; 4497 if (!ISSET(status->link_info, IXL_AQ_LINK_UP_FUNCTION)) 4498 goto done; 4499 4500 ifm_active |= IFM_FDX; 4501 ifm_status |= IFM_ACTIVE; 4502 link_state = LINK_STATE_FULL_DUPLEX; 4503 4504 itype = ixl_search_phy_type(status->phy_type); 4505 if (itype != NULL) 4506 ifm_active |= itype->ifm_type; 4507 4508 if (ISSET(status->an_info, IXL_AQ_LINK_PAUSE_TX)) 4509 ifm_active |= IFM_ETH_TXPAUSE; 4510 if (ISSET(status->an_info, IXL_AQ_LINK_PAUSE_RX)) 4511 ifm_active |= IFM_ETH_RXPAUSE; 4512 4513 baudrate = ixl_search_link_speed(status->link_speed); 4514 4515 done: 4516 /* NET_ASSERT_LOCKED() except during attach */ 4517 sc->sc_media_active = ifm_active; 4518 sc->sc_media_status = ifm_status; 4519 sc->sc_ac.ac_if.if_baudrate = baudrate; 4520 4521 return (link_state); 4522 } 4523 4524 static int 4525 ixl_restart_an(struct ixl_softc *sc) 4526 { 4527 struct ixl_aq_desc iaq; 4528 4529 memset(&iaq, 0, sizeof(iaq)); 4530 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_RESTART_AN); 4531 iaq.iaq_param[0] = 4532 htole32(IXL_AQ_PHY_RESTART_AN | IXL_AQ_PHY_LINK_ENABLE); 4533 4534 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4535 printf("%s: RESTART AN timeout\n", DEVNAME(sc)); 4536 return (-1); 4537 } 4538 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4539 printf("%s: RESTART AN error\n", DEVNAME(sc)); 4540 return (-1); 4541 } 4542 4543 return (0); 4544 } 4545 4546 static int 4547 ixl_add_macvlan(struct ixl_softc *sc, uint8_t *macaddr, uint16_t vlan, uint16_t flags) 4548 { 4549 struct ixl_aq_desc iaq; 4550 struct ixl_aq_add_macvlan *param; 4551 struct ixl_aq_add_macvlan_elem *elem; 4552 4553 memset(&iaq, 0, sizeof(iaq)); 4554 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4555 iaq.iaq_opcode = htole16(IXL_AQ_OP_ADD_MACVLAN); 4556 iaq.iaq_datalen = htole16(sizeof(*elem)); 4557 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch)); 4558 4559 param = (struct ixl_aq_add_macvlan *)&iaq.iaq_param; 4560 param->num_addrs = htole16(1); 4561 param->seid0 = htole16(0x8000) | sc->sc_seid; 4562 param->seid1 = 0; 4563 param->seid2 = 0; 4564 4565 elem = IXL_DMA_KVA(&sc->sc_scratch); 4566 memset(elem, 0, sizeof(*elem)); 4567 memcpy(elem->macaddr, macaddr, ETHER_ADDR_LEN); 4568 elem->flags = htole16(IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH | flags); 4569 elem->vlan = htole16(vlan); 4570 4571 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4572 printf("%s: ADD_MACVLAN timeout\n", DEVNAME(sc)); 4573 return (IXL_AQ_RC_EINVAL); 4574 } 4575 4576 return letoh16(iaq.iaq_retval); 4577 } 4578 4579 static int 4580 ixl_remove_macvlan(struct ixl_softc *sc, uint8_t *macaddr, uint16_t vlan, uint16_t flags) 4581 { 4582 struct ixl_aq_desc iaq; 4583 struct ixl_aq_remove_macvlan *param; 4584 struct ixl_aq_remove_macvlan_elem *elem; 4585 4586 memset(&iaq, 0, sizeof(iaq)); 4587 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4588 iaq.iaq_opcode = htole16(IXL_AQ_OP_REMOVE_MACVLAN); 4589 iaq.iaq_datalen = htole16(sizeof(*elem)); 4590 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch)); 4591 4592 param = (struct ixl_aq_remove_macvlan *)&iaq.iaq_param; 4593 param->num_addrs = htole16(1); 4594 param->seid0 = htole16(0x8000) | sc->sc_seid; 4595 param->seid1 = 0; 4596 param->seid2 = 0; 4597 4598 elem = IXL_DMA_KVA(&sc->sc_scratch); 4599 memset(elem, 0, sizeof(*elem)); 4600 memcpy(elem->macaddr, macaddr, ETHER_ADDR_LEN); 4601 elem->flags = htole16(IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH | flags); 4602 elem->vlan = htole16(vlan); 4603 4604 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4605 printf("%s: REMOVE_MACVLAN timeout\n", DEVNAME(sc)); 4606 return (IXL_AQ_RC_EINVAL); 4607 } 4608 4609 return letoh16(iaq.iaq_retval); 4610 } 4611 4612 static int 4613 ixl_hmc(struct ixl_softc *sc) 4614 { 4615 struct { 4616 uint32_t count; 4617 uint32_t minsize; 4618 bus_size_t maxcnt; 4619 bus_size_t setoff; 4620 bus_size_t setcnt; 4621 } regs[] = { 4622 { 4623 0, 4624 IXL_HMC_TXQ_MINSIZE, 4625 I40E_GLHMC_LANTXOBJSZ, 4626 I40E_GLHMC_LANTXBASE(sc->sc_pf_id), 4627 I40E_GLHMC_LANTXCNT(sc->sc_pf_id), 4628 }, 4629 { 4630 0, 4631 IXL_HMC_RXQ_MINSIZE, 4632 I40E_GLHMC_LANRXOBJSZ, 4633 I40E_GLHMC_LANRXBASE(sc->sc_pf_id), 4634 I40E_GLHMC_LANRXCNT(sc->sc_pf_id), 4635 }, 4636 { 4637 0, 4638 0, 4639 I40E_GLHMC_FCOEMAX, 4640 I40E_GLHMC_FCOEDDPBASE(sc->sc_pf_id), 4641 I40E_GLHMC_FCOEDDPCNT(sc->sc_pf_id), 4642 }, 4643 { 4644 0, 4645 0, 4646 I40E_GLHMC_FCOEFMAX, 4647 I40E_GLHMC_FCOEFBASE(sc->sc_pf_id), 4648 I40E_GLHMC_FCOEFCNT(sc->sc_pf_id), 4649 }, 4650 }; 4651 struct ixl_hmc_entry *e; 4652 uint64_t size, dva; 4653 uint8_t *kva; 4654 uint64_t *sdpage; 4655 unsigned int i; 4656 int npages, tables; 4657 4658 CTASSERT(nitems(regs) <= nitems(sc->sc_hmc_entries)); 4659 4660 regs[IXL_HMC_LAN_TX].count = regs[IXL_HMC_LAN_RX].count = 4661 ixl_rd(sc, I40E_GLHMC_LANQMAX); 4662 4663 size = 0; 4664 for (i = 0; i < nitems(regs); i++) { 4665 e = &sc->sc_hmc_entries[i]; 4666 4667 e->hmc_count = regs[i].count; 4668 e->hmc_size = 1U << ixl_rd(sc, regs[i].maxcnt); 4669 e->hmc_base = size; 4670 4671 if ((e->hmc_size * 8) < regs[i].minsize) { 4672 printf("%s: kernel hmc entry is too big\n", 4673 DEVNAME(sc)); 4674 return (-1); 4675 } 4676 4677 size += roundup(e->hmc_size * e->hmc_count, IXL_HMC_ROUNDUP); 4678 } 4679 size = roundup(size, IXL_HMC_PGSIZE); 4680 npages = size / IXL_HMC_PGSIZE; 4681 4682 tables = roundup(size, IXL_HMC_L2SZ) / IXL_HMC_L2SZ; 4683 4684 if (ixl_dmamem_alloc(sc, &sc->sc_hmc_pd, size, IXL_HMC_PGSIZE) != 0) { 4685 printf("%s: unable to allocate hmc pd memory\n", DEVNAME(sc)); 4686 return (-1); 4687 } 4688 4689 if (ixl_dmamem_alloc(sc, &sc->sc_hmc_sd, tables * IXL_HMC_PGSIZE, 4690 IXL_HMC_PGSIZE) != 0) { 4691 printf("%s: unable to allocate hmc sd memory\n", DEVNAME(sc)); 4692 ixl_dmamem_free(sc, &sc->sc_hmc_pd); 4693 return (-1); 4694 } 4695 4696 kva = IXL_DMA_KVA(&sc->sc_hmc_pd); 4697 memset(kva, 0, IXL_DMA_LEN(&sc->sc_hmc_pd)); 4698 4699 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 4700 0, IXL_DMA_LEN(&sc->sc_hmc_pd), 4701 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4702 4703 dva = IXL_DMA_DVA(&sc->sc_hmc_pd); 4704 sdpage = IXL_DMA_KVA(&sc->sc_hmc_sd); 4705 for (i = 0; i < npages; i++) { 4706 htolem64(sdpage++, dva | IXL_HMC_PDVALID); 4707 4708 dva += IXL_HMC_PGSIZE; 4709 } 4710 4711 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_sd), 4712 0, IXL_DMA_LEN(&sc->sc_hmc_sd), 4713 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4714 4715 dva = IXL_DMA_DVA(&sc->sc_hmc_sd); 4716 for (i = 0; i < tables; i++) { 4717 uint32_t count; 4718 4719 KASSERT(npages >= 0); 4720 4721 count = (npages > IXL_HMC_PGS) ? IXL_HMC_PGS : npages; 4722 4723 ixl_wr(sc, I40E_PFHMC_SDDATAHIGH, dva >> 32); 4724 ixl_wr(sc, I40E_PFHMC_SDDATALOW, dva | 4725 (count << I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | 4726 (1U << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT)); 4727 ixl_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 4728 ixl_wr(sc, I40E_PFHMC_SDCMD, 4729 (1U << I40E_PFHMC_SDCMD_PMSDWR_SHIFT) | i); 4730 4731 npages -= IXL_HMC_PGS; 4732 dva += IXL_HMC_PGSIZE; 4733 } 4734 4735 for (i = 0; i < nitems(regs); i++) { 4736 e = &sc->sc_hmc_entries[i]; 4737 4738 ixl_wr(sc, regs[i].setoff, e->hmc_base / IXL_HMC_ROUNDUP); 4739 ixl_wr(sc, regs[i].setcnt, e->hmc_count); 4740 } 4741 4742 return (0); 4743 } 4744 4745 static void 4746 ixl_hmc_free(struct ixl_softc *sc) 4747 { 4748 ixl_dmamem_free(sc, &sc->sc_hmc_sd); 4749 ixl_dmamem_free(sc, &sc->sc_hmc_pd); 4750 } 4751 4752 static void 4753 ixl_hmc_pack(void *d, const void *s, const struct ixl_hmc_pack *packing, 4754 unsigned int npacking) 4755 { 4756 uint8_t *dst = d; 4757 const uint8_t *src = s; 4758 unsigned int i; 4759 4760 for (i = 0; i < npacking; i++) { 4761 const struct ixl_hmc_pack *pack = &packing[i]; 4762 unsigned int offset = pack->lsb / 8; 4763 unsigned int align = pack->lsb % 8; 4764 const uint8_t *in = src + pack->offset; 4765 uint8_t *out = dst + offset; 4766 int width = pack->width; 4767 unsigned int inbits = 0; 4768 4769 if (align) { 4770 inbits = (*in++) << align; 4771 *out++ |= (inbits & 0xff); 4772 inbits >>= 8; 4773 4774 width -= 8 - align; 4775 } 4776 4777 while (width >= 8) { 4778 inbits |= (*in++) << align; 4779 *out++ = (inbits & 0xff); 4780 inbits >>= 8; 4781 4782 width -= 8; 4783 } 4784 4785 if (width > 0) { 4786 inbits |= (*in) << align; 4787 *out |= (inbits & ((1 << width) - 1)); 4788 } 4789 } 4790 } 4791 4792 static struct ixl_aq_buf * 4793 ixl_aqb_alloc(struct ixl_softc *sc) 4794 { 4795 struct ixl_aq_buf *aqb; 4796 4797 aqb = malloc(sizeof(*aqb), M_DEVBUF, M_WAITOK); 4798 if (aqb == NULL) 4799 return (NULL); 4800 4801 aqb->aqb_data = dma_alloc(IXL_AQ_BUFLEN, PR_WAITOK); 4802 if (aqb->aqb_data == NULL) 4803 goto free; 4804 4805 if (bus_dmamap_create(sc->sc_dmat, IXL_AQ_BUFLEN, 1, 4806 IXL_AQ_BUFLEN, 0, 4807 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 4808 &aqb->aqb_map) != 0) 4809 goto dma_free; 4810 4811 if (bus_dmamap_load(sc->sc_dmat, aqb->aqb_map, aqb->aqb_data, 4812 IXL_AQ_BUFLEN, NULL, BUS_DMA_WAITOK) != 0) 4813 goto destroy; 4814 4815 return (aqb); 4816 4817 destroy: 4818 bus_dmamap_destroy(sc->sc_dmat, aqb->aqb_map); 4819 dma_free: 4820 dma_free(aqb->aqb_data, IXL_AQ_BUFLEN); 4821 free: 4822 free(aqb, M_DEVBUF, sizeof(*aqb)); 4823 4824 return (NULL); 4825 } 4826 4827 static void 4828 ixl_aqb_free(struct ixl_softc *sc, struct ixl_aq_buf *aqb) 4829 { 4830 bus_dmamap_unload(sc->sc_dmat, aqb->aqb_map); 4831 bus_dmamap_destroy(sc->sc_dmat, aqb->aqb_map); 4832 dma_free(aqb->aqb_data, IXL_AQ_BUFLEN); 4833 free(aqb, M_DEVBUF, sizeof(*aqb)); 4834 } 4835 4836 static int 4837 ixl_arq_fill(struct ixl_softc *sc) 4838 { 4839 struct ixl_aq_buf *aqb; 4840 struct ixl_aq_desc *arq, *iaq; 4841 unsigned int prod = sc->sc_arq_prod; 4842 unsigned int n; 4843 int post = 0; 4844 4845 n = if_rxr_get(&sc->sc_arq_ring, IXL_AQ_NUM); 4846 arq = IXL_DMA_KVA(&sc->sc_arq); 4847 4848 while (n > 0) { 4849 aqb = SIMPLEQ_FIRST(&sc->sc_arq_idle); 4850 if (aqb != NULL) 4851 SIMPLEQ_REMOVE_HEAD(&sc->sc_arq_idle, aqb_entry); 4852 else if ((aqb = ixl_aqb_alloc(sc)) == NULL) 4853 break; 4854 4855 memset(aqb->aqb_data, 0, IXL_AQ_BUFLEN); 4856 4857 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IXL_AQ_BUFLEN, 4858 BUS_DMASYNC_PREREAD); 4859 4860 iaq = &arq[prod]; 4861 iaq->iaq_flags = htole16(IXL_AQ_BUF | 4862 (IXL_AQ_BUFLEN > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4863 iaq->iaq_opcode = 0; 4864 iaq->iaq_datalen = htole16(IXL_AQ_BUFLEN); 4865 iaq->iaq_retval = 0; 4866 iaq->iaq_cookie = 0; 4867 iaq->iaq_param[0] = 0; 4868 iaq->iaq_param[1] = 0; 4869 ixl_aq_dva(iaq, aqb->aqb_map->dm_segs[0].ds_addr); 4870 4871 SIMPLEQ_INSERT_TAIL(&sc->sc_arq_live, aqb, aqb_entry); 4872 4873 prod++; 4874 prod &= IXL_AQ_MASK; 4875 4876 post = 1; 4877 4878 n--; 4879 } 4880 4881 if_rxr_put(&sc->sc_arq_ring, n); 4882 sc->sc_arq_prod = prod; 4883 4884 return (post); 4885 } 4886 4887 static void 4888 ixl_arq_unfill(struct ixl_softc *sc) 4889 { 4890 struct ixl_aq_buf *aqb; 4891 4892 while ((aqb = SIMPLEQ_FIRST(&sc->sc_arq_live)) != NULL) { 4893 SIMPLEQ_REMOVE_HEAD(&sc->sc_arq_live, aqb_entry); 4894 4895 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IXL_AQ_BUFLEN, 4896 BUS_DMASYNC_POSTREAD); 4897 ixl_aqb_free(sc, aqb); 4898 } 4899 } 4900 4901 static void 4902 ixl_clear_hw(struct ixl_softc *sc) 4903 { 4904 uint32_t num_queues, base_queue; 4905 uint32_t num_pf_int; 4906 uint32_t num_vf_int; 4907 uint32_t num_vfs; 4908 uint32_t i, j; 4909 uint32_t val; 4910 4911 /* get number of interrupts, queues, and vfs */ 4912 val = ixl_rd(sc, I40E_GLPCI_CNF2); 4913 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 4914 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 4915 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 4916 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 4917 4918 val = ixl_rd(sc, I40E_PFLAN_QALLOC); 4919 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 4920 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 4921 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 4922 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 4923 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 4924 num_queues = (j - base_queue) + 1; 4925 else 4926 num_queues = 0; 4927 4928 val = ixl_rd(sc, I40E_PF_VT_PFALLOC); 4929 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 4930 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 4931 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 4932 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 4933 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 4934 num_vfs = (j - i) + 1; 4935 else 4936 num_vfs = 0; 4937 4938 /* stop all the interrupts */ 4939 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 0); 4940 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 4941 for (i = 0; i < num_pf_int - 2; i++) 4942 ixl_wr(sc, I40E_PFINT_DYN_CTLN(i), val); 4943 4944 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 4945 val = I40E_QUEUE_TYPE_EOL << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 4946 ixl_wr(sc, I40E_PFINT_LNKLST0, val); 4947 for (i = 0; i < num_pf_int - 2; i++) 4948 ixl_wr(sc, I40E_PFINT_LNKLSTN(i), val); 4949 val = I40E_QUEUE_TYPE_EOL << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 4950 for (i = 0; i < num_vfs; i++) 4951 ixl_wr(sc, I40E_VPINT_LNKLST0(i), val); 4952 for (i = 0; i < num_vf_int - 2; i++) 4953 ixl_wr(sc, I40E_VPINT_LNKLSTN(i), val); 4954 4955 /* warn the HW of the coming Tx disables */ 4956 for (i = 0; i < num_queues; i++) { 4957 uint32_t abs_queue_idx = base_queue + i; 4958 uint32_t reg_block = 0; 4959 4960 if (abs_queue_idx >= 128) { 4961 reg_block = abs_queue_idx / 128; 4962 abs_queue_idx %= 128; 4963 } 4964 4965 val = ixl_rd(sc, I40E_GLLAN_TXPRE_QDIS(reg_block)); 4966 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 4967 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 4968 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 4969 4970 ixl_wr(sc, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 4971 } 4972 delaymsec(400); 4973 4974 /* stop all the queues */ 4975 for (i = 0; i < num_queues; i++) { 4976 ixl_wr(sc, I40E_QINT_TQCTL(i), 0); 4977 ixl_wr(sc, I40E_QTX_ENA(i), 0); 4978 ixl_wr(sc, I40E_QINT_RQCTL(i), 0); 4979 ixl_wr(sc, I40E_QRX_ENA(i), 0); 4980 } 4981 4982 /* short wait for all queue disables to settle */ 4983 delaymsec(50); 4984 } 4985 4986 static int 4987 ixl_pf_reset(struct ixl_softc *sc) 4988 { 4989 uint32_t cnt = 0; 4990 uint32_t cnt1 = 0; 4991 uint32_t reg = 0; 4992 uint32_t grst_del; 4993 4994 /* 4995 * Poll for Global Reset steady state in case of recent GRST. 4996 * The grst delay value is in 100ms units, and we'll wait a 4997 * couple counts longer to be sure we don't just miss the end. 4998 */ 4999 grst_del = ixl_rd(sc, I40E_GLGEN_RSTCTL); 5000 grst_del &= I40E_GLGEN_RSTCTL_GRSTDEL_MASK; 5001 grst_del >>= I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 5002 grst_del += 10; 5003 5004 for (cnt = 0; cnt < grst_del; cnt++) { 5005 reg = ixl_rd(sc, I40E_GLGEN_RSTAT); 5006 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 5007 break; 5008 delaymsec(100); 5009 } 5010 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 5011 printf(", Global reset polling failed to complete\n"); 5012 return (-1); 5013 } 5014 5015 /* Now Wait for the FW to be ready */ 5016 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 5017 reg = ixl_rd(sc, I40E_GLNVM_ULD); 5018 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 5019 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 5020 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 5021 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) 5022 break; 5023 5024 delaymsec(10); 5025 } 5026 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 5027 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 5028 printf(", wait for FW Reset complete timed out " 5029 "(I40E_GLNVM_ULD = 0x%x)\n", reg); 5030 return (-1); 5031 } 5032 5033 /* 5034 * If there was a Global Reset in progress when we got here, 5035 * we don't need to do the PF Reset 5036 */ 5037 if (cnt == 0) { 5038 reg = ixl_rd(sc, I40E_PFGEN_CTRL); 5039 ixl_wr(sc, I40E_PFGEN_CTRL, reg | I40E_PFGEN_CTRL_PFSWR_MASK); 5040 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 5041 reg = ixl_rd(sc, I40E_PFGEN_CTRL); 5042 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 5043 break; 5044 delaymsec(1); 5045 } 5046 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 5047 printf(", PF reset polling failed to complete" 5048 "(I40E_PFGEN_CTRL= 0x%x)\n", reg); 5049 return (-1); 5050 } 5051 } 5052 5053 return (0); 5054 } 5055 5056 static uint32_t 5057 ixl_710_rd_ctl(struct ixl_softc *sc, uint32_t r) 5058 { 5059 struct ixl_atq iatq; 5060 struct ixl_aq_desc *iaq; 5061 uint16_t retval; 5062 5063 memset(&iatq, 0, sizeof(iatq)); 5064 iaq = &iatq.iatq_desc; 5065 iaq->iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_READ); 5066 htolem32(&iaq->iaq_param[1], r); 5067 5068 ixl_atq_exec(sc, &iatq, "ixl710rd"); 5069 5070 retval = lemtoh16(&iaq->iaq_retval); 5071 if (retval != IXL_AQ_RC_OK) { 5072 printf("%s: %s failed (%u)\n", DEVNAME(sc), __func__, retval); 5073 return (~0U); 5074 } 5075 5076 return (lemtoh32(&iaq->iaq_param[3])); 5077 } 5078 5079 static void 5080 ixl_710_wr_ctl(struct ixl_softc *sc, uint32_t r, uint32_t v) 5081 { 5082 struct ixl_atq iatq; 5083 struct ixl_aq_desc *iaq; 5084 uint16_t retval; 5085 5086 memset(&iatq, 0, sizeof(iatq)); 5087 iaq = &iatq.iatq_desc; 5088 iaq->iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_WRITE); 5089 htolem32(&iaq->iaq_param[1], r); 5090 htolem32(&iaq->iaq_param[3], v); 5091 5092 ixl_atq_exec(sc, &iatq, "ixl710wr"); 5093 5094 retval = lemtoh16(&iaq->iaq_retval); 5095 if (retval != IXL_AQ_RC_OK) { 5096 printf("%s: %s %08x=%08x failed (%u)\n", 5097 DEVNAME(sc), __func__, r, v, retval); 5098 } 5099 } 5100 5101 static int 5102 ixl_710_set_rss_key(struct ixl_softc *sc, const struct ixl_rss_key *rsskey) 5103 { 5104 unsigned int i; 5105 5106 for (i = 0; i < nitems(rsskey->key); i++) 5107 ixl_wr_ctl(sc, I40E_PFQF_HKEY(i), rsskey->key[i]); 5108 5109 return (0); 5110 } 5111 5112 static int 5113 ixl_710_set_rss_lut(struct ixl_softc *sc, const struct ixl_rss_lut_128 *lut) 5114 { 5115 unsigned int i; 5116 5117 for (i = 0; i < nitems(lut->entries); i++) 5118 ixl_wr(sc, I40E_PFQF_HLUT(i), lut->entries[i]); 5119 5120 return (0); 5121 } 5122 5123 static uint32_t 5124 ixl_722_rd_ctl(struct ixl_softc *sc, uint32_t r) 5125 { 5126 return (ixl_rd(sc, r)); 5127 } 5128 5129 static void 5130 ixl_722_wr_ctl(struct ixl_softc *sc, uint32_t r, uint32_t v) 5131 { 5132 ixl_wr(sc, r, v); 5133 } 5134 5135 static int 5136 ixl_722_set_rss_key(struct ixl_softc *sc, const struct ixl_rss_key *rsskey) 5137 { 5138 /* XXX */ 5139 5140 return (0); 5141 } 5142 5143 static int 5144 ixl_722_set_rss_lut(struct ixl_softc *sc, const struct ixl_rss_lut_128 *lut) 5145 { 5146 /* XXX */ 5147 5148 return (0); 5149 } 5150 5151 static int 5152 ixl_dmamem_alloc(struct ixl_softc *sc, struct ixl_dmamem *ixm, 5153 bus_size_t size, u_int align) 5154 { 5155 ixm->ixm_size = size; 5156 5157 if (bus_dmamap_create(sc->sc_dmat, ixm->ixm_size, 1, 5158 ixm->ixm_size, 0, 5159 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 5160 &ixm->ixm_map) != 0) 5161 return (1); 5162 if (bus_dmamem_alloc(sc->sc_dmat, ixm->ixm_size, 5163 align, 0, &ixm->ixm_seg, 1, &ixm->ixm_nsegs, 5164 BUS_DMA_WAITOK | BUS_DMA_ZERO) != 0) 5165 goto destroy; 5166 if (bus_dmamem_map(sc->sc_dmat, &ixm->ixm_seg, ixm->ixm_nsegs, 5167 ixm->ixm_size, &ixm->ixm_kva, BUS_DMA_WAITOK) != 0) 5168 goto free; 5169 if (bus_dmamap_load(sc->sc_dmat, ixm->ixm_map, ixm->ixm_kva, 5170 ixm->ixm_size, NULL, BUS_DMA_WAITOK) != 0) 5171 goto unmap; 5172 5173 return (0); 5174 unmap: 5175 bus_dmamem_unmap(sc->sc_dmat, ixm->ixm_kva, ixm->ixm_size); 5176 free: 5177 bus_dmamem_free(sc->sc_dmat, &ixm->ixm_seg, 1); 5178 destroy: 5179 bus_dmamap_destroy(sc->sc_dmat, ixm->ixm_map); 5180 return (1); 5181 } 5182 5183 static void 5184 ixl_dmamem_free(struct ixl_softc *sc, struct ixl_dmamem *ixm) 5185 { 5186 bus_dmamap_unload(sc->sc_dmat, ixm->ixm_map); 5187 bus_dmamem_unmap(sc->sc_dmat, ixm->ixm_kva, ixm->ixm_size); 5188 bus_dmamem_free(sc->sc_dmat, &ixm->ixm_seg, 1); 5189 bus_dmamap_destroy(sc->sc_dmat, ixm->ixm_map); 5190 } 5191 5192 #if NKSTAT > 0 5193 5194 CTASSERT(KSTAT_KV_U_NONE <= 0xffU); 5195 CTASSERT(KSTAT_KV_U_PACKETS <= 0xffU); 5196 CTASSERT(KSTAT_KV_U_BYTES <= 0xffU); 5197 5198 struct ixl_counter { 5199 const char *c_name; 5200 uint32_t c_base; 5201 uint8_t c_width; 5202 uint8_t c_type; 5203 }; 5204 5205 const struct ixl_counter ixl_port_counters[] = { 5206 /* GORC */ 5207 { "rx bytes", 0x00300000, 48, KSTAT_KV_U_BYTES }, 5208 /* MLFC */ 5209 { "mac local errs", 0x00300020, 32, KSTAT_KV_U_NONE }, 5210 /* MRFC */ 5211 { "mac remote errs", 0x00300040, 32, KSTAT_KV_U_NONE }, 5212 /* MSPDC */ 5213 { "mac short", 0x00300060, 32, KSTAT_KV_U_PACKETS }, 5214 /* CRCERRS */ 5215 { "crc errs", 0x00300080, 32, KSTAT_KV_U_PACKETS }, 5216 /* RLEC */ 5217 { "rx len errs", 0x003000a0, 32, KSTAT_KV_U_PACKETS }, 5218 /* ERRBC */ 5219 { "byte errs", 0x003000c0, 32, KSTAT_KV_U_PACKETS }, 5220 /* ILLERRC */ 5221 { "illegal byte", 0x003000d0, 32, KSTAT_KV_U_PACKETS }, 5222 /* RUC */ 5223 { "rx undersize", 0x00300100, 32, KSTAT_KV_U_PACKETS }, 5224 /* ROC */ 5225 { "rx oversize", 0x00300120, 32, KSTAT_KV_U_PACKETS }, 5226 /* LXONRXCNT */ 5227 { "rx link xon", 0x00300140, 32, KSTAT_KV_U_PACKETS }, 5228 /* LXOFFRXCNT */ 5229 { "rx link xoff", 0x00300160, 32, KSTAT_KV_U_PACKETS }, 5230 5231 /* Priority XON Received Count */ 5232 /* Priority XOFF Received Count */ 5233 /* Priority XON to XOFF Count */ 5234 5235 /* PRC64 */ 5236 { "rx 64B", 0x00300480, 48, KSTAT_KV_U_PACKETS }, 5237 /* PRC127 */ 5238 { "rx 65-127B", 0x003004A0, 48, KSTAT_KV_U_PACKETS }, 5239 /* PRC255 */ 5240 { "rx 128-255B", 0x003004C0, 48, KSTAT_KV_U_PACKETS }, 5241 /* PRC511 */ 5242 { "rx 256-511B", 0x003004E0, 48, KSTAT_KV_U_PACKETS }, 5243 /* PRC1023 */ 5244 { "rx 512-1023B", 0x00300500, 48, KSTAT_KV_U_PACKETS }, 5245 /* PRC1522 */ 5246 { "rx 1024-1522B", 0x00300520, 48, KSTAT_KV_U_PACKETS }, 5247 /* PRC9522 */ 5248 { "rx 1523-9522B", 0x00300540, 48, KSTAT_KV_U_PACKETS }, 5249 /* ROC */ 5250 { "rx fragment", 0x00300560, 32, KSTAT_KV_U_PACKETS }, 5251 /* RJC */ 5252 { "rx jabber", 0x00300580, 32, KSTAT_KV_U_PACKETS }, 5253 /* UPRC */ 5254 { "rx ucasts", 0x003005a0, 48, KSTAT_KV_U_PACKETS }, 5255 /* MPRC */ 5256 { "rx mcasts", 0x003005c0, 48, KSTAT_KV_U_PACKETS }, 5257 /* BPRC */ 5258 { "rx bcasts", 0x003005e0, 48, KSTAT_KV_U_PACKETS }, 5259 /* RDPC */ 5260 { "rx discards", 0x00300600, 32, KSTAT_KV_U_PACKETS }, 5261 /* LDPC */ 5262 { "rx lo discards", 0x00300620, 32, KSTAT_KV_U_PACKETS }, 5263 /* RUPP */ 5264 { "rx no dest", 0x00300660, 32, KSTAT_KV_U_PACKETS }, 5265 5266 /* GOTC */ 5267 { "tx bytes", 0x00300680, 48, KSTAT_KV_U_BYTES }, 5268 /* PTC64 */ 5269 { "tx 64B", 0x003006A0, 48, KSTAT_KV_U_PACKETS }, 5270 /* PTC127 */ 5271 { "tx 65-127B", 0x003006C0, 48, KSTAT_KV_U_PACKETS }, 5272 /* PTC255 */ 5273 { "tx 128-255B", 0x003006E0, 48, KSTAT_KV_U_PACKETS }, 5274 /* PTC511 */ 5275 { "tx 256-511B", 0x00300700, 48, KSTAT_KV_U_PACKETS }, 5276 /* PTC1023 */ 5277 { "tx 512-1023B", 0x00300720, 48, KSTAT_KV_U_PACKETS }, 5278 /* PTC1522 */ 5279 { "tx 1024-1522B", 0x00300740, 48, KSTAT_KV_U_PACKETS }, 5280 /* PTC9522 */ 5281 { "tx 1523-9522B", 0x00300760, 48, KSTAT_KV_U_PACKETS }, 5282 5283 /* Priority XON Transmitted Count */ 5284 /* Priority XOFF Transmitted Count */ 5285 5286 /* LXONTXC */ 5287 { "tx link xon", 0x00300980, 48, KSTAT_KV_U_PACKETS }, 5288 /* LXOFFTXC */ 5289 { "tx link xoff", 0x003009a0, 48, KSTAT_KV_U_PACKETS }, 5290 /* UPTC */ 5291 { "tx ucasts", 0x003009c0, 48, KSTAT_KV_U_PACKETS }, 5292 /* MPTC */ 5293 { "tx mcasts", 0x003009e0, 48, KSTAT_KV_U_PACKETS }, 5294 /* BPTC */ 5295 { "tx bcasts", 0x00300a00, 48, KSTAT_KV_U_PACKETS }, 5296 /* TDOLD */ 5297 { "tx link down", 0x00300a20, 48, KSTAT_KV_U_PACKETS }, 5298 }; 5299 5300 const struct ixl_counter ixl_vsi_counters[] = { 5301 /* VSI RDPC */ 5302 { "rx discards", 0x00310000, 32, KSTAT_KV_U_PACKETS }, 5303 /* VSI GOTC */ 5304 { "tx bytes", 0x00328000, 48, KSTAT_KV_U_BYTES }, 5305 /* VSI UPTC */ 5306 { "tx ucasts", 0x0033c000, 48, KSTAT_KV_U_PACKETS }, 5307 /* VSI MPTC */ 5308 { "tx mcasts", 0x0033cc00, 48, KSTAT_KV_U_PACKETS }, 5309 /* VSI BPTC */ 5310 { "tx bcasts", 0x0033d800, 48, KSTAT_KV_U_PACKETS }, 5311 /* VSI TEPC */ 5312 { "tx errs", 0x00344000, 48, KSTAT_KV_U_PACKETS }, 5313 /* VSI TDPC */ 5314 { "tx discards", 0x00348000, 48, KSTAT_KV_U_PACKETS }, 5315 /* VSI GORC */ 5316 { "rx bytes", 0x00358000, 48, KSTAT_KV_U_BYTES }, 5317 /* VSI UPRC */ 5318 { "rx ucasts", 0x0036c000, 48, KSTAT_KV_U_PACKETS }, 5319 /* VSI MPRC */ 5320 { "rx mcasts", 0x0036cc00, 48, KSTAT_KV_U_PACKETS }, 5321 /* VSI BPRC */ 5322 { "rx bcasts", 0x0036d800, 48, KSTAT_KV_U_PACKETS }, 5323 /* VSI RUPP */ 5324 { "rx noproto", 0x0036e400, 32, KSTAT_KV_U_PACKETS }, 5325 }; 5326 5327 struct ixl_counter_state { 5328 const struct ixl_counter 5329 *counters; 5330 uint64_t *values; 5331 size_t n; 5332 uint32_t index; 5333 unsigned int gen; 5334 }; 5335 5336 static void 5337 ixl_rd_counters(struct ixl_softc *sc, const struct ixl_counter_state *state, 5338 uint64_t *vs) 5339 { 5340 const struct ixl_counter *c; 5341 bus_addr_t r; 5342 uint64_t v; 5343 size_t i; 5344 5345 for (i = 0; i < state->n; i++) { 5346 c = &state->counters[i]; 5347 5348 r = c->c_base + (state->index * 8); 5349 5350 if (c->c_width == 32) 5351 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, r); 5352 else 5353 v = bus_space_read_8(sc->sc_memt, sc->sc_memh, r); 5354 5355 vs[i] = v; 5356 } 5357 } 5358 5359 static int 5360 ixl_kstat_read(struct kstat *ks) 5361 { 5362 struct ixl_softc *sc = ks->ks_softc; 5363 struct kstat_kv *kvs = ks->ks_data; 5364 struct ixl_counter_state *state = ks->ks_ptr; 5365 unsigned int gen = (state->gen++) & 1; 5366 uint64_t *ovs = state->values + (gen * state->n); 5367 uint64_t *nvs = state->values + (!gen * state->n); 5368 size_t i; 5369 5370 ixl_rd_counters(sc, state, nvs); 5371 getnanouptime(&ks->ks_updated); 5372 5373 for (i = 0; i < state->n; i++) { 5374 const struct ixl_counter *c = &state->counters[i]; 5375 uint64_t n = nvs[i], o = ovs[i]; 5376 5377 if (c->c_width < 64) { 5378 if (n < o) 5379 n += (1ULL << c->c_width); 5380 } 5381 5382 kstat_kv_u64(&kvs[i]) += (n - o); 5383 } 5384 5385 return (0); 5386 } 5387 5388 static void 5389 ixl_kstat_tick(void *arg) 5390 { 5391 struct ixl_softc *sc = arg; 5392 5393 timeout_add_sec(&sc->sc_kstat_tmo, 4); 5394 5395 mtx_enter(&sc->sc_kstat_mtx); 5396 5397 ixl_kstat_read(sc->sc_port_kstat); 5398 ixl_kstat_read(sc->sc_vsi_kstat); 5399 5400 mtx_leave(&sc->sc_kstat_mtx); 5401 } 5402 5403 static struct kstat * 5404 ixl_kstat_create(struct ixl_softc *sc, const char *name, 5405 const struct ixl_counter *counters, size_t n, uint32_t index) 5406 { 5407 struct kstat *ks; 5408 struct kstat_kv *kvs; 5409 struct ixl_counter_state *state; 5410 const struct ixl_counter *c; 5411 unsigned int i; 5412 5413 ks = kstat_create(DEVNAME(sc), 0, name, 0, KSTAT_T_KV, 0); 5414 if (ks == NULL) { 5415 /* unable to create kstats */ 5416 return (NULL); 5417 } 5418 5419 kvs = mallocarray(n, sizeof(*kvs), M_DEVBUF, M_WAITOK|M_ZERO); 5420 for (i = 0; i < n; i++) { 5421 c = &counters[i]; 5422 5423 kstat_kv_unit_init(&kvs[i], c->c_name, 5424 KSTAT_KV_T_COUNTER64, c->c_type); 5425 } 5426 5427 ks->ks_data = kvs; 5428 ks->ks_datalen = n * sizeof(*kvs); 5429 ks->ks_read = ixl_kstat_read; 5430 5431 state = malloc(sizeof(*state), M_DEVBUF, M_WAITOK|M_ZERO); 5432 state->counters = counters; 5433 state->n = n; 5434 state->values = mallocarray(n * 2, sizeof(*state->values), 5435 M_DEVBUF, M_WAITOK|M_ZERO); 5436 state->index = index; 5437 ks->ks_ptr = state; 5438 5439 kstat_set_mutex(ks, &sc->sc_kstat_mtx); 5440 ks->ks_softc = sc; 5441 kstat_install(ks); 5442 5443 /* fetch a baseline */ 5444 ixl_rd_counters(sc, state, state->values); 5445 5446 return (ks); 5447 } 5448 5449 static void 5450 ixl_kstat_attach(struct ixl_softc *sc) 5451 { 5452 mtx_init(&sc->sc_kstat_mtx, IPL_SOFTCLOCK); 5453 timeout_set(&sc->sc_kstat_tmo, ixl_kstat_tick, sc); 5454 5455 sc->sc_port_kstat = ixl_kstat_create(sc, "ixl-port", 5456 ixl_port_counters, nitems(ixl_port_counters), sc->sc_port); 5457 sc->sc_vsi_kstat = ixl_kstat_create(sc, "ixl-vsi", 5458 ixl_vsi_counters, nitems(ixl_vsi_counters), 5459 lemtoh16(&sc->sc_vsi_number)); 5460 5461 /* ixl counters go up even when the interface is down */ 5462 timeout_add_sec(&sc->sc_kstat_tmo, 4); 5463 } 5464 5465 #endif /* NKSTAT > 0 */ 5466