1 /* $OpenBSD: if_ixl.c,v 1.68 2020/07/16 03:04:50 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 2013-2015, Intel Corporation 5 * All rights reserved. 6 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 2016,2017 David Gwynne <dlg@openbsd.org> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50 #include "bpfilter.h" 51 #include "kstat.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/proc.h> 56 #include <sys/sockio.h> 57 #include <sys/mbuf.h> 58 #include <sys/kernel.h> 59 #include <sys/socket.h> 60 #include <sys/device.h> 61 #include <sys/pool.h> 62 #include <sys/queue.h> 63 #include <sys/timeout.h> 64 #include <sys/task.h> 65 #include <sys/syslog.h> 66 #include <sys/intrmap.h> 67 68 #include <machine/bus.h> 69 #include <machine/intr.h> 70 71 #include <net/if.h> 72 #include <net/if_dl.h> 73 #include <net/if_media.h> 74 #include <net/toeplitz.h> 75 76 #if NBPFILTER > 0 77 #include <net/bpf.h> 78 #endif 79 80 #if NKSTAT > 0 81 #include <sys/kstat.h> 82 #endif 83 84 #include <netinet/in.h> 85 #include <netinet/if_ether.h> 86 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/pcidevs.h> 90 91 #ifdef __sparc64__ 92 #include <dev/ofw/openfirm.h> 93 #endif 94 95 #ifndef CACHE_LINE_SIZE 96 #define CACHE_LINE_SIZE 64 97 #endif 98 99 #define IXL_MAX_VECTORS 8 /* XXX this is pretty arbitrary */ 100 101 #define I40E_MASK(mask, shift) ((mask) << (shift)) 102 #define I40E_PF_RESET_WAIT_COUNT 200 103 #define I40E_AQ_LARGE_BUF 512 104 105 /* bitfields for Tx queue mapping in QTX_CTL */ 106 #define I40E_QTX_CTL_VF_QUEUE 0x0 107 #define I40E_QTX_CTL_VM_QUEUE 0x1 108 #define I40E_QTX_CTL_PF_QUEUE 0x2 109 110 #define I40E_QUEUE_TYPE_EOL 0x7ff 111 #define I40E_INTR_NOTX_QUEUE 0 112 113 #define I40E_QUEUE_TYPE_RX 0x0 114 #define I40E_QUEUE_TYPE_TX 0x1 115 #define I40E_QUEUE_TYPE_PE_CEQ 0x2 116 #define I40E_QUEUE_TYPE_UNKNOWN 0x3 117 118 #define I40E_ITR_INDEX_RX 0x0 119 #define I40E_ITR_INDEX_TX 0x1 120 #define I40E_ITR_INDEX_OTHER 0x2 121 #define I40E_ITR_INDEX_NONE 0x3 122 123 #include <dev/pci/if_ixlreg.h> 124 125 #define I40E_INTR_NOTX_QUEUE 0 126 #define I40E_INTR_NOTX_INTR 0 127 #define I40E_INTR_NOTX_RX_QUEUE 0 128 #define I40E_INTR_NOTX_TX_QUEUE 1 129 #define I40E_INTR_NOTX_RX_MASK I40E_PFINT_ICR0_QUEUE_0_MASK 130 #define I40E_INTR_NOTX_TX_MASK I40E_PFINT_ICR0_QUEUE_1_MASK 131 132 struct ixl_aq_desc { 133 uint16_t iaq_flags; 134 #define IXL_AQ_DD (1U << 0) 135 #define IXL_AQ_CMP (1U << 1) 136 #define IXL_AQ_ERR (1U << 2) 137 #define IXL_AQ_VFE (1U << 3) 138 #define IXL_AQ_LB (1U << 9) 139 #define IXL_AQ_RD (1U << 10) 140 #define IXL_AQ_VFC (1U << 11) 141 #define IXL_AQ_BUF (1U << 12) 142 #define IXL_AQ_SI (1U << 13) 143 #define IXL_AQ_EI (1U << 14) 144 #define IXL_AQ_FE (1U << 15) 145 146 #define IXL_AQ_FLAGS_FMT "\020" "\020FE" "\017EI" "\016SI" "\015BUF" \ 147 "\014VFC" "\013DB" "\012LB" "\004VFE" \ 148 "\003ERR" "\002CMP" "\001DD" 149 150 uint16_t iaq_opcode; 151 152 uint16_t iaq_datalen; 153 uint16_t iaq_retval; 154 155 uint64_t iaq_cookie; 156 157 uint32_t iaq_param[4]; 158 /* iaq_data_hi iaq_param[2] */ 159 /* iaq_data_lo iaq_param[3] */ 160 } __packed __aligned(8); 161 162 /* aq commands */ 163 #define IXL_AQ_OP_GET_VERSION 0x0001 164 #define IXL_AQ_OP_DRIVER_VERSION 0x0002 165 #define IXL_AQ_OP_QUEUE_SHUTDOWN 0x0003 166 #define IXL_AQ_OP_SET_PF_CONTEXT 0x0004 167 #define IXL_AQ_OP_GET_AQ_ERR_REASON 0x0005 168 #define IXL_AQ_OP_REQUEST_RESOURCE 0x0008 169 #define IXL_AQ_OP_RELEASE_RESOURCE 0x0009 170 #define IXL_AQ_OP_LIST_FUNC_CAP 0x000a 171 #define IXL_AQ_OP_LIST_DEV_CAP 0x000b 172 #define IXL_AQ_OP_MAC_ADDRESS_READ 0x0107 173 #define IXL_AQ_OP_CLEAR_PXE_MODE 0x0110 174 #define IXL_AQ_OP_SWITCH_GET_CONFIG 0x0200 175 #define IXL_AQ_OP_RX_CTL_READ 0x0206 176 #define IXL_AQ_OP_RX_CTL_WRITE 0x0207 177 #define IXL_AQ_OP_ADD_VSI 0x0210 178 #define IXL_AQ_OP_UPD_VSI_PARAMS 0x0211 179 #define IXL_AQ_OP_GET_VSI_PARAMS 0x0212 180 #define IXL_AQ_OP_ADD_VEB 0x0230 181 #define IXL_AQ_OP_UPD_VEB_PARAMS 0x0231 182 #define IXL_AQ_OP_GET_VEB_PARAMS 0x0232 183 #define IXL_AQ_OP_ADD_MACVLAN 0x0250 184 #define IXL_AQ_OP_REMOVE_MACVLAN 0x0251 185 #define IXL_AQ_OP_SET_VSI_PROMISC 0x0254 186 #define IXL_AQ_OP_PHY_GET_ABILITIES 0x0600 187 #define IXL_AQ_OP_PHY_SET_CONFIG 0x0601 188 #define IXL_AQ_OP_PHY_SET_MAC_CONFIG 0x0603 189 #define IXL_AQ_OP_PHY_RESTART_AN 0x0605 190 #define IXL_AQ_OP_PHY_LINK_STATUS 0x0607 191 #define IXL_AQ_OP_PHY_SET_EVENT_MASK 0x0613 192 #define IXL_AQ_OP_PHY_SET_REGISTER 0x0628 193 #define IXL_AQ_OP_PHY_GET_REGISTER 0x0629 194 #define IXL_AQ_OP_LLDP_GET_MIB 0x0a00 195 #define IXL_AQ_OP_LLDP_MIB_CHG_EV 0x0a01 196 #define IXL_AQ_OP_LLDP_ADD_TLV 0x0a02 197 #define IXL_AQ_OP_LLDP_UPD_TLV 0x0a03 198 #define IXL_AQ_OP_LLDP_DEL_TLV 0x0a04 199 #define IXL_AQ_OP_LLDP_STOP_AGENT 0x0a05 200 #define IXL_AQ_OP_LLDP_START_AGENT 0x0a06 201 #define IXL_AQ_OP_LLDP_GET_CEE_DCBX 0x0a07 202 #define IXL_AQ_OP_LLDP_SPECIFIC_AGENT 0x0a09 203 #define IXL_AQ_OP_SET_RSS_KEY 0x0b02 /* 722 only */ 204 #define IXL_AQ_OP_SET_RSS_LUT 0x0b03 /* 722 only */ 205 #define IXL_AQ_OP_GET_RSS_KEY 0x0b04 /* 722 only */ 206 #define IXL_AQ_OP_GET_RSS_LUT 0x0b05 /* 722 only */ 207 208 struct ixl_aq_mac_addresses { 209 uint8_t pf_lan[ETHER_ADDR_LEN]; 210 uint8_t pf_san[ETHER_ADDR_LEN]; 211 uint8_t port[ETHER_ADDR_LEN]; 212 uint8_t pf_wol[ETHER_ADDR_LEN]; 213 } __packed; 214 215 #define IXL_AQ_MAC_PF_LAN_VALID (1U << 4) 216 #define IXL_AQ_MAC_PF_SAN_VALID (1U << 5) 217 #define IXL_AQ_MAC_PORT_VALID (1U << 6) 218 #define IXL_AQ_MAC_PF_WOL_VALID (1U << 7) 219 220 struct ixl_aq_capability { 221 uint16_t cap_id; 222 #define IXL_AQ_CAP_SWITCH_MODE 0x0001 223 #define IXL_AQ_CAP_MNG_MODE 0x0002 224 #define IXL_AQ_CAP_NPAR_ACTIVE 0x0003 225 #define IXL_AQ_CAP_OS2BMC_CAP 0x0004 226 #define IXL_AQ_CAP_FUNCTIONS_VALID 0x0005 227 #define IXL_AQ_CAP_ALTERNATE_RAM 0x0006 228 #define IXL_AQ_CAP_WOL_AND_PROXY 0x0008 229 #define IXL_AQ_CAP_SRIOV 0x0012 230 #define IXL_AQ_CAP_VF 0x0013 231 #define IXL_AQ_CAP_VMDQ 0x0014 232 #define IXL_AQ_CAP_8021QBG 0x0015 233 #define IXL_AQ_CAP_8021QBR 0x0016 234 #define IXL_AQ_CAP_VSI 0x0017 235 #define IXL_AQ_CAP_DCB 0x0018 236 #define IXL_AQ_CAP_FCOE 0x0021 237 #define IXL_AQ_CAP_ISCSI 0x0022 238 #define IXL_AQ_CAP_RSS 0x0040 239 #define IXL_AQ_CAP_RXQ 0x0041 240 #define IXL_AQ_CAP_TXQ 0x0042 241 #define IXL_AQ_CAP_MSIX 0x0043 242 #define IXL_AQ_CAP_VF_MSIX 0x0044 243 #define IXL_AQ_CAP_FLOW_DIRECTOR 0x0045 244 #define IXL_AQ_CAP_1588 0x0046 245 #define IXL_AQ_CAP_IWARP 0x0051 246 #define IXL_AQ_CAP_LED 0x0061 247 #define IXL_AQ_CAP_SDP 0x0062 248 #define IXL_AQ_CAP_MDIO 0x0063 249 #define IXL_AQ_CAP_WSR_PROT 0x0064 250 #define IXL_AQ_CAP_NVM_MGMT 0x0080 251 #define IXL_AQ_CAP_FLEX10 0x00F1 252 #define IXL_AQ_CAP_CEM 0x00F2 253 uint8_t major_rev; 254 uint8_t minor_rev; 255 uint32_t number; 256 uint32_t logical_id; 257 uint32_t phys_id; 258 uint8_t _reserved[16]; 259 } __packed __aligned(4); 260 261 #define IXL_LLDP_SHUTDOWN 0x1 262 263 struct ixl_aq_switch_config { 264 uint16_t num_reported; 265 uint16_t num_total; 266 uint8_t _reserved[12]; 267 } __packed __aligned(4); 268 269 struct ixl_aq_switch_config_element { 270 uint8_t type; 271 #define IXL_AQ_SW_ELEM_TYPE_MAC 1 272 #define IXL_AQ_SW_ELEM_TYPE_PF 2 273 #define IXL_AQ_SW_ELEM_TYPE_VF 3 274 #define IXL_AQ_SW_ELEM_TYPE_EMP 4 275 #define IXL_AQ_SW_ELEM_TYPE_BMC 5 276 #define IXL_AQ_SW_ELEM_TYPE_PV 16 277 #define IXL_AQ_SW_ELEM_TYPE_VEB 17 278 #define IXL_AQ_SW_ELEM_TYPE_PA 18 279 #define IXL_AQ_SW_ELEM_TYPE_VSI 19 280 uint8_t revision; 281 #define IXL_AQ_SW_ELEM_REV_1 1 282 uint16_t seid; 283 284 uint16_t uplink_seid; 285 uint16_t downlink_seid; 286 287 uint8_t _reserved[3]; 288 uint8_t connection_type; 289 #define IXL_AQ_CONN_TYPE_REGULAR 0x1 290 #define IXL_AQ_CONN_TYPE_DEFAULT 0x2 291 #define IXL_AQ_CONN_TYPE_CASCADED 0x3 292 293 uint16_t scheduler_id; 294 uint16_t element_info; 295 } __packed __aligned(4); 296 297 #define IXL_PHY_TYPE_SGMII 0x00 298 #define IXL_PHY_TYPE_1000BASE_KX 0x01 299 #define IXL_PHY_TYPE_10GBASE_KX4 0x02 300 #define IXL_PHY_TYPE_10GBASE_KR 0x03 301 #define IXL_PHY_TYPE_40GBASE_KR4 0x04 302 #define IXL_PHY_TYPE_XAUI 0x05 303 #define IXL_PHY_TYPE_XFI 0x06 304 #define IXL_PHY_TYPE_SFI 0x07 305 #define IXL_PHY_TYPE_XLAUI 0x08 306 #define IXL_PHY_TYPE_XLPPI 0x09 307 #define IXL_PHY_TYPE_40GBASE_CR4_CU 0x0a 308 #define IXL_PHY_TYPE_10GBASE_CR1_CU 0x0b 309 #define IXL_PHY_TYPE_10GBASE_AOC 0x0c 310 #define IXL_PHY_TYPE_40GBASE_AOC 0x0d 311 #define IXL_PHY_TYPE_100BASE_TX 0x11 312 #define IXL_PHY_TYPE_1000BASE_T 0x12 313 #define IXL_PHY_TYPE_10GBASE_T 0x13 314 #define IXL_PHY_TYPE_10GBASE_SR 0x14 315 #define IXL_PHY_TYPE_10GBASE_LR 0x15 316 #define IXL_PHY_TYPE_10GBASE_SFPP_CU 0x16 317 #define IXL_PHY_TYPE_10GBASE_CR1 0x17 318 #define IXL_PHY_TYPE_40GBASE_CR4 0x18 319 #define IXL_PHY_TYPE_40GBASE_SR4 0x19 320 #define IXL_PHY_TYPE_40GBASE_LR4 0x1a 321 #define IXL_PHY_TYPE_1000BASE_SX 0x1b 322 #define IXL_PHY_TYPE_1000BASE_LX 0x1c 323 #define IXL_PHY_TYPE_1000BASE_T_OPTICAL 0x1d 324 #define IXL_PHY_TYPE_20GBASE_KR2 0x1e 325 326 #define IXL_PHY_TYPE_25GBASE_KR 0x1f 327 #define IXL_PHY_TYPE_25GBASE_CR 0x20 328 #define IXL_PHY_TYPE_25GBASE_SR 0x21 329 #define IXL_PHY_TYPE_25GBASE_LR 0x22 330 #define IXL_PHY_TYPE_25GBASE_AOC 0x23 331 #define IXL_PHY_TYPE_25GBASE_ACC 0x24 332 333 struct ixl_aq_module_desc { 334 uint8_t oui[3]; 335 uint8_t _reserved1; 336 uint8_t part_number[16]; 337 uint8_t revision[4]; 338 uint8_t _reserved2[8]; 339 } __packed __aligned(4); 340 341 struct ixl_aq_phy_abilities { 342 uint32_t phy_type; 343 344 uint8_t link_speed; 345 #define IXL_AQ_PHY_LINK_SPEED_100MB (1 << 1) 346 #define IXL_AQ_PHY_LINK_SPEED_1000MB (1 << 2) 347 #define IXL_AQ_PHY_LINK_SPEED_10GB (1 << 3) 348 #define IXL_AQ_PHY_LINK_SPEED_40GB (1 << 4) 349 #define IXL_AQ_PHY_LINK_SPEED_20GB (1 << 5) 350 #define IXL_AQ_PHY_LINK_SPEED_25GB (1 << 6) 351 uint8_t abilities; 352 uint16_t eee_capability; 353 354 uint32_t eeer_val; 355 356 uint8_t d3_lpan; 357 uint8_t phy_type_ext; 358 #define IXL_AQ_PHY_TYPE_EXT_25G_KR 0x01 359 #define IXL_AQ_PHY_TYPE_EXT_25G_CR 0x02 360 #define IXL_AQ_PHY_TYPE_EXT_25G_SR 0x04 361 #define IXL_AQ_PHY_TYPE_EXT_25G_LR 0x08 362 uint8_t fec_cfg_curr_mod_ext_info; 363 #define IXL_AQ_ENABLE_FEC_KR 0x01 364 #define IXL_AQ_ENABLE_FEC_RS 0x02 365 #define IXL_AQ_REQUEST_FEC_KR 0x04 366 #define IXL_AQ_REQUEST_FEC_RS 0x08 367 #define IXL_AQ_ENABLE_FEC_AUTO 0x10 368 #define IXL_AQ_MODULE_TYPE_EXT_MASK 0xe0 369 #define IXL_AQ_MODULE_TYPE_EXT_SHIFT 5 370 uint8_t ext_comp_code; 371 372 uint8_t phy_id[4]; 373 374 uint8_t module_type[3]; 375 #define IXL_SFF8024_ID_SFP 0x03 376 #define IXL_SFF8024_ID_QSFP 0x0c 377 #define IXL_SFF8024_ID_QSFP_PLUS 0x0d 378 #define IXL_SFF8024_ID_QSFP28 0x11 379 uint8_t qualified_module_count; 380 #define IXL_AQ_PHY_MAX_QMS 16 381 struct ixl_aq_module_desc 382 qualified_module[IXL_AQ_PHY_MAX_QMS]; 383 } __packed __aligned(4); 384 385 struct ixl_aq_link_param { 386 uint8_t notify; 387 #define IXL_AQ_LINK_NOTIFY 0x03 388 uint8_t _reserved1; 389 uint8_t phy; 390 uint8_t speed; 391 uint8_t status; 392 uint8_t _reserved2[11]; 393 } __packed __aligned(4); 394 395 struct ixl_aq_vsi_param { 396 uint16_t uplink_seid; 397 uint8_t connect_type; 398 #define IXL_AQ_VSI_CONN_TYPE_NORMAL (0x1) 399 #define IXL_AQ_VSI_CONN_TYPE_DEFAULT (0x2) 400 #define IXL_AQ_VSI_CONN_TYPE_CASCADED (0x3) 401 uint8_t _reserved1; 402 403 uint8_t vf_id; 404 uint8_t _reserved2; 405 uint16_t vsi_flags; 406 #define IXL_AQ_VSI_TYPE_SHIFT 0x0 407 #define IXL_AQ_VSI_TYPE_MASK (0x3 << IXL_AQ_VSI_TYPE_SHIFT) 408 #define IXL_AQ_VSI_TYPE_VF 0x0 409 #define IXL_AQ_VSI_TYPE_VMDQ2 0x1 410 #define IXL_AQ_VSI_TYPE_PF 0x2 411 #define IXL_AQ_VSI_TYPE_EMP_MNG 0x3 412 #define IXL_AQ_VSI_FLAG_CASCADED_PV 0x4 413 414 uint32_t addr_hi; 415 uint32_t addr_lo; 416 } __packed __aligned(16); 417 418 struct ixl_aq_add_macvlan { 419 uint16_t num_addrs; 420 uint16_t seid0; 421 uint16_t seid1; 422 uint16_t seid2; 423 uint32_t addr_hi; 424 uint32_t addr_lo; 425 } __packed __aligned(16); 426 427 struct ixl_aq_add_macvlan_elem { 428 uint8_t macaddr[6]; 429 uint16_t vlan; 430 uint16_t flags; 431 #define IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH 0x0001 432 #define IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN 0x0004 433 uint16_t queue; 434 uint32_t _reserved; 435 } __packed __aligned(16); 436 437 struct ixl_aq_remove_macvlan { 438 uint16_t num_addrs; 439 uint16_t seid0; 440 uint16_t seid1; 441 uint16_t seid2; 442 uint32_t addr_hi; 443 uint32_t addr_lo; 444 } __packed __aligned(16); 445 446 struct ixl_aq_remove_macvlan_elem { 447 uint8_t macaddr[6]; 448 uint16_t vlan; 449 uint8_t flags; 450 #define IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH 0x0001 451 #define IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN 0x0008 452 uint8_t _reserved[7]; 453 } __packed __aligned(16); 454 455 struct ixl_aq_vsi_reply { 456 uint16_t seid; 457 uint16_t vsi_number; 458 459 uint16_t vsis_used; 460 uint16_t vsis_free; 461 462 uint32_t addr_hi; 463 uint32_t addr_lo; 464 } __packed __aligned(16); 465 466 struct ixl_aq_vsi_data { 467 /* first 96 byte are written by SW */ 468 uint16_t valid_sections; 469 #define IXL_AQ_VSI_VALID_SWITCH (1 << 0) 470 #define IXL_AQ_VSI_VALID_SECURITY (1 << 1) 471 #define IXL_AQ_VSI_VALID_VLAN (1 << 2) 472 #define IXL_AQ_VSI_VALID_CAS_PV (1 << 3) 473 #define IXL_AQ_VSI_VALID_INGRESS_UP (1 << 4) 474 #define IXL_AQ_VSI_VALID_EGRESS_UP (1 << 5) 475 #define IXL_AQ_VSI_VALID_QUEUE_MAP (1 << 6) 476 #define IXL_AQ_VSI_VALID_QUEUE_OPT (1 << 7) 477 #define IXL_AQ_VSI_VALID_OUTER_UP (1 << 8) 478 #define IXL_AQ_VSI_VALID_SCHED (1 << 9) 479 /* switch section */ 480 uint16_t switch_id; 481 #define IXL_AQ_VSI_SWITCH_ID_SHIFT 0 482 #define IXL_AQ_VSI_SWITCH_ID_MASK (0xfff << IXL_AQ_VSI_SWITCH_ID_SHIFT) 483 #define IXL_AQ_VSI_SWITCH_NOT_STAG (1 << 12) 484 #define IXL_AQ_VSI_SWITCH_LOCAL_LB (1 << 14) 485 486 uint8_t _reserved1[2]; 487 /* security section */ 488 uint8_t sec_flags; 489 #define IXL_AQ_VSI_SEC_ALLOW_DEST_OVRD (1 << 0) 490 #define IXL_AQ_VSI_SEC_ENABLE_VLAN_CHK (1 << 1) 491 #define IXL_AQ_VSI_SEC_ENABLE_MAC_CHK (1 << 2) 492 uint8_t _reserved2; 493 494 /* vlan section */ 495 uint16_t pvid; 496 uint16_t fcoe_pvid; 497 498 uint8_t port_vlan_flags; 499 #define IXL_AQ_VSI_PVLAN_MODE_SHIFT 0 500 #define IXL_AQ_VSI_PVLAN_MODE_MASK (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 501 #define IXL_AQ_VSI_PVLAN_MODE_TAGGED (0x1 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 502 #define IXL_AQ_VSI_PVLAN_MODE_UNTAGGED (0x2 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 503 #define IXL_AQ_VSI_PVLAN_MODE_ALL (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 504 #define IXL_AQ_VSI_PVLAN_INSERT_PVID (0x4 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 505 #define IXL_AQ_VSI_PVLAN_EMOD_SHIFT 0x3 506 #define IXL_AQ_VSI_PVLAN_EMOD_MASK (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 507 #define IXL_AQ_VSI_PVLAN_EMOD_STR_BOTH (0x0 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 508 #define IXL_AQ_VSI_PVLAN_EMOD_STR_UP (0x1 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 509 #define IXL_AQ_VSI_PVLAN_EMOD_STR (0x2 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 510 #define IXL_AQ_VSI_PVLAN_EMOD_NOTHING (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 511 uint8_t _reserved3[3]; 512 513 /* ingress egress up section */ 514 uint32_t ingress_table; 515 #define IXL_AQ_VSI_UP_SHIFT(_up) ((_up) * 3) 516 #define IXL_AQ_VSI_UP_MASK(_up) (0x7 << (IXL_AQ_VSI_UP_SHIFT(_up)) 517 uint32_t egress_table; 518 519 /* cascaded pv section */ 520 uint16_t cas_pv_tag; 521 uint8_t cas_pv_flags; 522 #define IXL_AQ_VSI_CAS_PV_TAGX_SHIFT 0 523 #define IXL_AQ_VSI_CAS_PV_TAGX_MASK (0x3 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 524 #define IXL_AQ_VSI_CAS_PV_TAGX_LEAVE (0x0 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 525 #define IXL_AQ_VSI_CAS_PV_TAGX_REMOVE (0x1 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 526 #define IXL_AQ_VSI_CAS_PV_TAGX_COPY (0x2 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 527 #define IXL_AQ_VSI_CAS_PV_INSERT_TAG (1 << 4) 528 #define IXL_AQ_VSI_CAS_PV_ETAG_PRUNE (1 << 5) 529 #define IXL_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG \ 530 (1 << 6) 531 uint8_t _reserved4; 532 533 /* queue mapping section */ 534 uint16_t mapping_flags; 535 #define IXL_AQ_VSI_QUE_MAP_MASK 0x1 536 #define IXL_AQ_VSI_QUE_MAP_CONTIG 0x0 537 #define IXL_AQ_VSI_QUE_MAP_NONCONTIG 0x1 538 uint16_t queue_mapping[16]; 539 #define IXL_AQ_VSI_QUEUE_SHIFT 0x0 540 #define IXL_AQ_VSI_QUEUE_MASK (0x7ff << IXL_AQ_VSI_QUEUE_SHIFT) 541 uint16_t tc_mapping[8]; 542 #define IXL_AQ_VSI_TC_Q_OFFSET_SHIFT 0 543 #define IXL_AQ_VSI_TC_Q_OFFSET_MASK (0x1ff << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) 544 #define IXL_AQ_VSI_TC_Q_NUMBER_SHIFT 9 545 #define IXL_AQ_VSI_TC_Q_NUMBER_MASK (0x7 << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT) 546 547 /* queueing option section */ 548 uint8_t queueing_opt_flags; 549 #define IXL_AQ_VSI_QUE_OPT_MCAST_UDP_EN (1 << 2) 550 #define IXL_AQ_VSI_QUE_OPT_UCAST_UDP_EN (1 << 3) 551 #define IXL_AQ_VSI_QUE_OPT_TCP_EN (1 << 4) 552 #define IXL_AQ_VSI_QUE_OPT_FCOE_EN (1 << 5) 553 #define IXL_AQ_VSI_QUE_OPT_RSS_LUT_PF 0 554 #define IXL_AQ_VSI_QUE_OPT_RSS_LUT_VSI (1 << 6) 555 uint8_t _reserved5[3]; 556 557 /* scheduler section */ 558 uint8_t up_enable_bits; 559 uint8_t _reserved6; 560 561 /* outer up section */ 562 uint32_t outer_up_table; /* same as ingress/egress tables */ 563 uint8_t _reserved7[8]; 564 565 /* last 32 bytes are written by FW */ 566 uint16_t qs_handle[8]; 567 #define IXL_AQ_VSI_QS_HANDLE_INVALID 0xffff 568 uint16_t stat_counter_idx; 569 uint16_t sched_id; 570 571 uint8_t _reserved8[12]; 572 } __packed __aligned(8); 573 574 CTASSERT(sizeof(struct ixl_aq_vsi_data) == 128); 575 576 struct ixl_aq_vsi_promisc_param { 577 uint16_t flags; 578 uint16_t valid_flags; 579 #define IXL_AQ_VSI_PROMISC_FLAG_UCAST (1 << 0) 580 #define IXL_AQ_VSI_PROMISC_FLAG_MCAST (1 << 1) 581 #define IXL_AQ_VSI_PROMISC_FLAG_BCAST (1 << 2) 582 #define IXL_AQ_VSI_PROMISC_FLAG_DFLT (1 << 3) 583 #define IXL_AQ_VSI_PROMISC_FLAG_VLAN (1 << 4) 584 #define IXL_AQ_VSI_PROMISC_FLAG_RXONLY (1 << 15) 585 586 uint16_t seid; 587 #define IXL_AQ_VSI_PROMISC_SEID_VALID (1 << 15) 588 uint16_t vlan; 589 #define IXL_AQ_VSI_PROMISC_VLAN_VALID (1 << 15) 590 uint32_t reserved[2]; 591 } __packed __aligned(8); 592 593 struct ixl_aq_veb_param { 594 uint16_t uplink_seid; 595 uint16_t downlink_seid; 596 uint16_t veb_flags; 597 #define IXL_AQ_ADD_VEB_FLOATING (1 << 0) 598 #define IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT 1 599 #define IXL_AQ_ADD_VEB_PORT_TYPE_MASK (0x3 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 600 #define IXL_AQ_ADD_VEB_PORT_TYPE_DEFAULT \ 601 (0x2 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 602 #define IXL_AQ_ADD_VEB_PORT_TYPE_DATA (0x4 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 603 #define IXL_AQ_ADD_VEB_ENABLE_L2_FILTER (1 << 3) /* deprecated */ 604 #define IXL_AQ_ADD_VEB_DISABLE_STATS (1 << 4) 605 uint8_t enable_tcs; 606 uint8_t _reserved[9]; 607 } __packed __aligned(16); 608 609 struct ixl_aq_veb_reply { 610 uint16_t _reserved1; 611 uint16_t _reserved2; 612 uint16_t _reserved3; 613 uint16_t switch_seid; 614 uint16_t veb_seid; 615 #define IXL_AQ_VEB_ERR_FLAG_NO_VEB (1 << 0) 616 #define IXL_AQ_VEB_ERR_FLAG_NO_SCHED (1 << 1) 617 #define IXL_AQ_VEB_ERR_FLAG_NO_COUNTER (1 << 2) 618 #define IXL_AQ_VEB_ERR_FLAG_NO_ENTRY (1 << 3); 619 uint16_t statistic_index; 620 uint16_t vebs_used; 621 uint16_t vebs_free; 622 } __packed __aligned(16); 623 624 /* GET PHY ABILITIES param[0] */ 625 #define IXL_AQ_PHY_REPORT_QUAL (1 << 0) 626 #define IXL_AQ_PHY_REPORT_INIT (1 << 1) 627 628 struct ixl_aq_phy_reg_access { 629 uint8_t phy_iface; 630 #define IXL_AQ_PHY_IF_INTERNAL 0 631 #define IXL_AQ_PHY_IF_EXTERNAL 1 632 #define IXL_AQ_PHY_IF_MODULE 2 633 uint8_t dev_addr; 634 uint16_t recall; 635 #define IXL_AQ_PHY_QSFP_DEV_ADDR 0 636 #define IXL_AQ_PHY_QSFP_LAST 1 637 uint32_t reg; 638 uint32_t val; 639 uint32_t _reserved2; 640 } __packed __aligned(16); 641 642 /* RESTART_AN param[0] */ 643 #define IXL_AQ_PHY_RESTART_AN (1 << 1) 644 #define IXL_AQ_PHY_LINK_ENABLE (1 << 2) 645 646 struct ixl_aq_link_status { /* this occupies the iaq_param space */ 647 uint16_t command_flags; /* only field set on command */ 648 #define IXL_AQ_LSE_MASK 0x3 649 #define IXL_AQ_LSE_NOP 0x0 650 #define IXL_AQ_LSE_DISABLE 0x2 651 #define IXL_AQ_LSE_ENABLE 0x3 652 #define IXL_AQ_LSE_IS_ENABLED 0x1 /* only set in response */ 653 uint8_t phy_type; 654 uint8_t link_speed; 655 #define IXL_AQ_LINK_SPEED_1GB (1 << 2) 656 #define IXL_AQ_LINK_SPEED_10GB (1 << 3) 657 #define IXL_AQ_LINK_SPEED_40GB (1 << 4) 658 #define IXL_AQ_LINK_SPEED_25GB (1 << 6) 659 uint8_t link_info; 660 #define IXL_AQ_LINK_UP_FUNCTION 0x01 661 #define IXL_AQ_LINK_FAULT 0x02 662 #define IXL_AQ_LINK_FAULT_TX 0x04 663 #define IXL_AQ_LINK_FAULT_RX 0x08 664 #define IXL_AQ_LINK_FAULT_REMOTE 0x10 665 #define IXL_AQ_LINK_UP_PORT 0x20 666 #define IXL_AQ_MEDIA_AVAILABLE 0x40 667 #define IXL_AQ_SIGNAL_DETECT 0x80 668 uint8_t an_info; 669 #define IXL_AQ_AN_COMPLETED 0x01 670 #define IXL_AQ_LP_AN_ABILITY 0x02 671 #define IXL_AQ_PD_FAULT 0x04 672 #define IXL_AQ_FEC_EN 0x08 673 #define IXL_AQ_PHY_LOW_POWER 0x10 674 #define IXL_AQ_LINK_PAUSE_TX 0x20 675 #define IXL_AQ_LINK_PAUSE_RX 0x40 676 #define IXL_AQ_QUALIFIED_MODULE 0x80 677 678 uint8_t ext_info; 679 #define IXL_AQ_LINK_PHY_TEMP_ALARM 0x01 680 #define IXL_AQ_LINK_XCESSIVE_ERRORS 0x02 681 #define IXL_AQ_LINK_TX_SHIFT 0x02 682 #define IXL_AQ_LINK_TX_MASK (0x03 << IXL_AQ_LINK_TX_SHIFT) 683 #define IXL_AQ_LINK_TX_ACTIVE 0x00 684 #define IXL_AQ_LINK_TX_DRAINED 0x01 685 #define IXL_AQ_LINK_TX_FLUSHED 0x03 686 #define IXL_AQ_LINK_FORCED_40G 0x10 687 /* 25G Error Codes */ 688 #define IXL_AQ_25G_NO_ERR 0X00 689 #define IXL_AQ_25G_NOT_PRESENT 0X01 690 #define IXL_AQ_25G_NVM_CRC_ERR 0X02 691 #define IXL_AQ_25G_SBUS_UCODE_ERR 0X03 692 #define IXL_AQ_25G_SERDES_UCODE_ERR 0X04 693 #define IXL_AQ_25G_NIMB_UCODE_ERR 0X05 694 uint8_t loopback; 695 uint16_t max_frame_size; 696 697 uint8_t config; 698 #define IXL_AQ_CONFIG_FEC_KR_ENA 0x01 699 #define IXL_AQ_CONFIG_FEC_RS_ENA 0x02 700 #define IXL_AQ_CONFIG_CRC_ENA 0x04 701 #define IXL_AQ_CONFIG_PACING_MASK 0x78 702 uint8_t power_desc; 703 #define IXL_AQ_LINK_POWER_CLASS_1 0x00 704 #define IXL_AQ_LINK_POWER_CLASS_2 0x01 705 #define IXL_AQ_LINK_POWER_CLASS_3 0x02 706 #define IXL_AQ_LINK_POWER_CLASS_4 0x03 707 #define IXL_AQ_PWR_CLASS_MASK 0x03 708 709 uint8_t reserved[4]; 710 } __packed __aligned(4); 711 /* event mask command flags for param[2] */ 712 #define IXL_AQ_PHY_EV_MASK 0x3ff 713 #define IXL_AQ_PHY_EV_LINK_UPDOWN (1 << 1) 714 #define IXL_AQ_PHY_EV_MEDIA_NA (1 << 2) 715 #define IXL_AQ_PHY_EV_LINK_FAULT (1 << 3) 716 #define IXL_AQ_PHY_EV_PHY_TEMP_ALARM (1 << 4) 717 #define IXL_AQ_PHY_EV_EXCESS_ERRORS (1 << 5) 718 #define IXL_AQ_PHY_EV_SIGNAL_DETECT (1 << 6) 719 #define IXL_AQ_PHY_EV_AN_COMPLETED (1 << 7) 720 #define IXL_AQ_PHY_EV_MODULE_QUAL_FAIL (1 << 8) 721 #define IXL_AQ_PHY_EV_PORT_TX_SUSPENDED (1 << 9) 722 723 struct ixl_aq_rss_lut { /* 722 */ 724 #define IXL_AQ_SET_RSS_LUT_VSI_VALID (1 << 15) 725 #define IXL_AQ_SET_RSS_LUT_VSI_ID_SHIFT 0 726 #define IXL_AQ_SET_RSS_LUT_VSI_ID_MASK \ 727 (0x3FF << IXL_AQ_SET_RSS_LUT_VSI_ID_SHIFT) 728 729 uint16_t vsi_number; 730 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 731 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_MASK \ 732 (0x1 << IXL_AQ_SET_RSS_LUT_TABLE_TYPE_SHIFT) 733 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_VSI 0 734 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_PF 1 735 uint16_t flags; 736 uint8_t _reserved[4]; 737 uint32_t addr_hi; 738 uint32_t addr_lo; 739 } __packed __aligned(16); 740 741 struct ixl_aq_get_set_rss_key { /* 722 */ 742 #define IXL_AQ_SET_RSS_KEY_VSI_VALID (1 << 15) 743 #define IXL_AQ_SET_RSS_KEY_VSI_ID_SHIFT 0 744 #define IXL_AQ_SET_RSS_KEY_VSI_ID_MASK \ 745 (0x3FF << IXL_AQ_SET_RSS_KEY_VSI_ID_SHIFT) 746 uint16_t vsi_number; 747 uint8_t _reserved[6]; 748 uint32_t addr_hi; 749 uint32_t addr_lo; 750 } __packed __aligned(16); 751 752 /* aq response codes */ 753 #define IXL_AQ_RC_OK 0 /* success */ 754 #define IXL_AQ_RC_EPERM 1 /* Operation not permitted */ 755 #define IXL_AQ_RC_ENOENT 2 /* No such element */ 756 #define IXL_AQ_RC_ESRCH 3 /* Bad opcode */ 757 #define IXL_AQ_RC_EINTR 4 /* operation interrupted */ 758 #define IXL_AQ_RC_EIO 5 /* I/O error */ 759 #define IXL_AQ_RC_ENXIO 6 /* No such resource */ 760 #define IXL_AQ_RC_E2BIG 7 /* Arg too long */ 761 #define IXL_AQ_RC_EAGAIN 8 /* Try again */ 762 #define IXL_AQ_RC_ENOMEM 9 /* Out of memory */ 763 #define IXL_AQ_RC_EACCES 10 /* Permission denied */ 764 #define IXL_AQ_RC_EFAULT 11 /* Bad address */ 765 #define IXL_AQ_RC_EBUSY 12 /* Device or resource busy */ 766 #define IXL_AQ_RC_EEXIST 13 /* object already exists */ 767 #define IXL_AQ_RC_EINVAL 14 /* invalid argument */ 768 #define IXL_AQ_RC_ENOTTY 15 /* not a typewriter */ 769 #define IXL_AQ_RC_ENOSPC 16 /* No space or alloc failure */ 770 #define IXL_AQ_RC_ENOSYS 17 /* function not implemented */ 771 #define IXL_AQ_RC_ERANGE 18 /* parameter out of range */ 772 #define IXL_AQ_RC_EFLUSHED 19 /* cmd flushed due to prev error */ 773 #define IXL_AQ_RC_BAD_ADDR 20 /* contains a bad pointer */ 774 #define IXL_AQ_RC_EMODE 21 /* not allowed in current mode */ 775 #define IXL_AQ_RC_EFBIG 22 /* file too large */ 776 777 struct ixl_tx_desc { 778 uint64_t addr; 779 uint64_t cmd; 780 #define IXL_TX_DESC_DTYPE_SHIFT 0 781 #define IXL_TX_DESC_DTYPE_MASK (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 782 #define IXL_TX_DESC_DTYPE_DATA (0x0ULL << IXL_TX_DESC_DTYPE_SHIFT) 783 #define IXL_TX_DESC_DTYPE_NOP (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 784 #define IXL_TX_DESC_DTYPE_CONTEXT (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 785 #define IXL_TX_DESC_DTYPE_FCOE_CTX (0x2ULL << IXL_TX_DESC_DTYPE_SHIFT) 786 #define IXL_TX_DESC_DTYPE_FD (0x8ULL << IXL_TX_DESC_DTYPE_SHIFT) 787 #define IXL_TX_DESC_DTYPE_DDP_CTX (0x9ULL << IXL_TX_DESC_DTYPE_SHIFT) 788 #define IXL_TX_DESC_DTYPE_FLEX_DATA (0xbULL << IXL_TX_DESC_DTYPE_SHIFT) 789 #define IXL_TX_DESC_DTYPE_FLEX_CTX_1 (0xcULL << IXL_TX_DESC_DTYPE_SHIFT) 790 #define IXL_TX_DESC_DTYPE_FLEX_CTX_2 (0xdULL << IXL_TX_DESC_DTYPE_SHIFT) 791 #define IXL_TX_DESC_DTYPE_DONE (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 792 793 #define IXL_TX_DESC_CMD_SHIFT 4 794 #define IXL_TX_DESC_CMD_MASK (0x3ffULL << IXL_TX_DESC_CMD_SHIFT) 795 #define IXL_TX_DESC_CMD_EOP (0x001 << IXL_TX_DESC_CMD_SHIFT) 796 #define IXL_TX_DESC_CMD_RS (0x002 << IXL_TX_DESC_CMD_SHIFT) 797 #define IXL_TX_DESC_CMD_ICRC (0x004 << IXL_TX_DESC_CMD_SHIFT) 798 #define IXL_TX_DESC_CMD_IL2TAG1 (0x008 << IXL_TX_DESC_CMD_SHIFT) 799 #define IXL_TX_DESC_CMD_DUMMY (0x010 << IXL_TX_DESC_CMD_SHIFT) 800 #define IXL_TX_DESC_CMD_IIPT_MASK (0x060 << IXL_TX_DESC_CMD_SHIFT) 801 #define IXL_TX_DESC_CMD_IIPT_NONIP (0x000 << IXL_TX_DESC_CMD_SHIFT) 802 #define IXL_TX_DESC_CMD_IIPT_IPV6 (0x020 << IXL_TX_DESC_CMD_SHIFT) 803 #define IXL_TX_DESC_CMD_IIPT_IPV4 (0x040 << IXL_TX_DESC_CMD_SHIFT) 804 #define IXL_TX_DESC_CMD_IIPT_IPV4_CSUM (0x060 << IXL_TX_DESC_CMD_SHIFT) 805 #define IXL_TX_DESC_CMD_FCOET (0x080 << IXL_TX_DESC_CMD_SHIFT) 806 #define IXL_TX_DESC_CMD_L4T_EOFT_MASK (0x300 << IXL_TX_DESC_CMD_SHIFT) 807 #define IXL_TX_DESC_CMD_L4T_EOFT_UNK (0x000 << IXL_TX_DESC_CMD_SHIFT) 808 #define IXL_TX_DESC_CMD_L4T_EOFT_TCP (0x100 << IXL_TX_DESC_CMD_SHIFT) 809 #define IXL_TX_DESC_CMD_L4T_EOFT_SCTP (0x200 << IXL_TX_DESC_CMD_SHIFT) 810 #define IXL_TX_DESC_CMD_L4T_EOFT_UDP (0x300 << IXL_TX_DESC_CMD_SHIFT) 811 812 #define IXL_TX_DESC_MACLEN_SHIFT 16 813 #define IXL_TX_DESC_MACLEN_MASK (0x7fULL << IXL_TX_DESC_MACLEN_SHIFT) 814 #define IXL_TX_DESC_IPLEN_SHIFT 23 815 #define IXL_TX_DESC_IPLEN_MASK (0x7fULL << IXL_TX_DESC_IPLEN_SHIFT) 816 #define IXL_TX_DESC_L4LEN_SHIFT 30 817 #define IXL_TX_DESC_L4LEN_MASK (0xfULL << IXL_TX_DESC_L4LEN_SHIFT) 818 #define IXL_TX_DESC_FCLEN_SHIFT 30 819 #define IXL_TX_DESC_FCLEN_MASK (0xfULL << IXL_TX_DESC_FCLEN_SHIFT) 820 821 #define IXL_TX_DESC_BSIZE_SHIFT 34 822 #define IXL_TX_DESC_BSIZE_MAX 0x3fffULL 823 #define IXL_TX_DESC_BSIZE_MASK \ 824 (IXL_TX_DESC_BSIZE_MAX << IXL_TX_DESC_BSIZE_SHIFT) 825 } __packed __aligned(16); 826 827 struct ixl_rx_rd_desc_16 { 828 uint64_t paddr; /* packet addr */ 829 uint64_t haddr; /* header addr */ 830 } __packed __aligned(16); 831 832 struct ixl_rx_rd_desc_32 { 833 uint64_t paddr; /* packet addr */ 834 uint64_t haddr; /* header addr */ 835 uint64_t _reserved1; 836 uint64_t _reserved2; 837 } __packed __aligned(16); 838 839 struct ixl_rx_wb_desc_16 { 840 uint64_t qword0; 841 uint64_t qword1; 842 #define IXL_RX_DESC_DD (1 << 0) 843 #define IXL_RX_DESC_EOP (1 << 1) 844 #define IXL_RX_DESC_L2TAG1P (1 << 2) 845 #define IXL_RX_DESC_L3L4P (1 << 3) 846 #define IXL_RX_DESC_CRCP (1 << 4) 847 #define IXL_RX_DESC_TSYNINDX_SHIFT 5 /* TSYNINDX */ 848 #define IXL_RX_DESC_TSYNINDX_MASK (7 << IXL_RX_DESC_TSYNINDX_SHIFT) 849 #define IXL_RX_DESC_UMB_SHIFT 9 850 #define IXL_RX_DESC_UMB_MASK (0x3 << IXL_RX_DESC_UMB_SHIFT) 851 #define IXL_RX_DESC_UMB_UCAST (0x0 << IXL_RX_DESC_UMB_SHIFT) 852 #define IXL_RX_DESC_UMB_MCAST (0x1 << IXL_RX_DESC_UMB_SHIFT) 853 #define IXL_RX_DESC_UMB_BCAST (0x2 << IXL_RX_DESC_UMB_SHIFT) 854 #define IXL_RX_DESC_UMB_MIRROR (0x3 << IXL_RX_DESC_UMB_SHIFT) 855 #define IXL_RX_DESC_FLM (1 << 11) 856 #define IXL_RX_DESC_FLTSTAT_SHIFT 12 857 #define IXL_RX_DESC_FLTSTAT_MASK (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 858 #define IXL_RX_DESC_FLTSTAT_NODATA (0x0 << IXL_RX_DESC_FLTSTAT_SHIFT) 859 #define IXL_RX_DESC_FLTSTAT_FDFILTID (0x1 << IXL_RX_DESC_FLTSTAT_SHIFT) 860 #define IXL_RX_DESC_FLTSTAT_RSS (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 861 #define IXL_RX_DESC_LPBK (1 << 14) 862 #define IXL_RX_DESC_IPV6EXTADD (1 << 15) 863 #define IXL_RX_DESC_INT_UDP_0 (1 << 18) 864 865 #define IXL_RX_DESC_RXE (1 << 19) 866 #define IXL_RX_DESC_HBO (1 << 21) 867 #define IXL_RX_DESC_IPE (1 << 22) 868 #define IXL_RX_DESC_L4E (1 << 23) 869 #define IXL_RX_DESC_EIPE (1 << 24) 870 #define IXL_RX_DESC_OVERSIZE (1 << 25) 871 872 #define IXL_RX_DESC_PTYPE_SHIFT 30 873 #define IXL_RX_DESC_PTYPE_MASK (0xffULL << IXL_RX_DESC_PTYPE_SHIFT) 874 875 #define IXL_RX_DESC_PLEN_SHIFT 38 876 #define IXL_RX_DESC_PLEN_MASK (0x3fffULL << IXL_RX_DESC_PLEN_SHIFT) 877 #define IXL_RX_DESC_HLEN_SHIFT 42 878 #define IXL_RX_DESC_HLEN_MASK (0x7ffULL << IXL_RX_DESC_HLEN_SHIFT) 879 } __packed __aligned(16); 880 881 struct ixl_rx_wb_desc_32 { 882 uint64_t qword0; 883 uint64_t qword1; 884 uint64_t qword2; 885 uint64_t qword3; 886 } __packed __aligned(16); 887 888 #define IXL_TX_PKT_DESCS 8 889 #define IXL_TX_QUEUE_ALIGN 128 890 #define IXL_RX_QUEUE_ALIGN 128 891 892 #define IXL_HARDMTU 9712 /* 9726 - ETHER_HDR_LEN */ 893 894 #define IXL_PCIREG PCI_MAPREG_START 895 896 #define IXL_ITR0 0x0 897 #define IXL_ITR1 0x1 898 #define IXL_ITR2 0x2 899 #define IXL_NOITR 0x2 900 901 #define IXL_AQ_NUM 256 902 #define IXL_AQ_MASK (IXL_AQ_NUM - 1) 903 #define IXL_AQ_ALIGN 64 /* lol */ 904 #define IXL_AQ_BUFLEN 4096 905 906 /* Packet Classifier Types for filters */ 907 /* bits 0-28 are reserved for future use */ 908 #define IXL_PCT_NONF_IPV4_UDP_UCAST (1ULL << 29) /* 722 */ 909 #define IXL_PCT_NONF_IPV4_UDP_MCAST (1ULL << 30) /* 722 */ 910 #define IXL_PCT_NONF_IPV4_UDP (1ULL << 31) 911 #define IXL_PCT_NONF_IPV4_TCP_SYN_NOACK (1ULL << 32) /* 722 */ 912 #define IXL_PCT_NONF_IPV4_TCP (1ULL << 33) 913 #define IXL_PCT_NONF_IPV4_SCTP (1ULL << 34) 914 #define IXL_PCT_NONF_IPV4_OTHER (1ULL << 35) 915 #define IXL_PCT_FRAG_IPV4 (1ULL << 36) 916 /* bits 37-38 are reserved for future use */ 917 #define IXL_PCT_NONF_IPV6_UDP_UCAST (1ULL << 39) /* 722 */ 918 #define IXL_PCT_NONF_IPV6_UDP_MCAST (1ULL << 40) /* 722 */ 919 #define IXL_PCT_NONF_IPV6_UDP (1ULL << 41) 920 #define IXL_PCT_NONF_IPV6_TCP_SYN_NOACK (1ULL << 42) /* 722 */ 921 #define IXL_PCT_NONF_IPV6_TCP (1ULL << 43) 922 #define IXL_PCT_NONF_IPV6_SCTP (1ULL << 44) 923 #define IXL_PCT_NONF_IPV6_OTHER (1ULL << 45) 924 #define IXL_PCT_FRAG_IPV6 (1ULL << 46) 925 /* bit 47 is reserved for future use */ 926 #define IXL_PCT_FCOE_OX (1ULL << 48) 927 #define IXL_PCT_FCOE_RX (1ULL << 49) 928 #define IXL_PCT_FCOE_OTHER (1ULL << 50) 929 /* bits 51-62 are reserved for future use */ 930 #define IXL_PCT_L2_PAYLOAD (1ULL << 63) 931 932 #define IXL_RSS_HENA_BASE_DEFAULT \ 933 IXL_PCT_NONF_IPV4_UDP | \ 934 IXL_PCT_NONF_IPV4_TCP | \ 935 IXL_PCT_NONF_IPV4_SCTP | \ 936 IXL_PCT_NONF_IPV4_OTHER | \ 937 IXL_PCT_FRAG_IPV4 | \ 938 IXL_PCT_NONF_IPV6_UDP | \ 939 IXL_PCT_NONF_IPV6_TCP | \ 940 IXL_PCT_NONF_IPV6_SCTP | \ 941 IXL_PCT_NONF_IPV6_OTHER | \ 942 IXL_PCT_FRAG_IPV6 | \ 943 IXL_PCT_L2_PAYLOAD 944 945 #define IXL_RSS_HENA_BASE_710 IXL_RSS_HENA_BASE_DEFAULT 946 #define IXL_RSS_HENA_BASE_722 IXL_RSS_HENA_BASE_DEFAULT | \ 947 IXL_PCT_NONF_IPV4_UDP_UCAST | \ 948 IXL_PCT_NONF_IPV4_UDP_MCAST | \ 949 IXL_PCT_NONF_IPV6_UDP_UCAST | \ 950 IXL_PCT_NONF_IPV6_UDP_MCAST | \ 951 IXL_PCT_NONF_IPV4_TCP_SYN_NOACK | \ 952 IXL_PCT_NONF_IPV6_TCP_SYN_NOACK 953 954 #define IXL_HMC_ROUNDUP 512 955 #define IXL_HMC_PGSIZE 4096 956 #define IXL_HMC_DVASZ sizeof(uint64_t) 957 #define IXL_HMC_PGS (IXL_HMC_PGSIZE / IXL_HMC_DVASZ) 958 #define IXL_HMC_L2SZ (IXL_HMC_PGSIZE * IXL_HMC_PGS) 959 #define IXL_HMC_PDVALID 1ULL 960 961 struct ixl_aq_regs { 962 bus_size_t atq_tail; 963 bus_size_t atq_head; 964 bus_size_t atq_len; 965 bus_size_t atq_bal; 966 bus_size_t atq_bah; 967 968 bus_size_t arq_tail; 969 bus_size_t arq_head; 970 bus_size_t arq_len; 971 bus_size_t arq_bal; 972 bus_size_t arq_bah; 973 974 uint32_t atq_len_enable; 975 uint32_t atq_tail_mask; 976 uint32_t atq_head_mask; 977 978 uint32_t arq_len_enable; 979 uint32_t arq_tail_mask; 980 uint32_t arq_head_mask; 981 }; 982 983 struct ixl_phy_type { 984 uint64_t phy_type; 985 uint64_t ifm_type; 986 }; 987 988 struct ixl_speed_type { 989 uint8_t dev_speed; 990 uint64_t net_speed; 991 }; 992 993 struct ixl_aq_buf { 994 SIMPLEQ_ENTRY(ixl_aq_buf) 995 aqb_entry; 996 void *aqb_data; 997 bus_dmamap_t aqb_map; 998 }; 999 SIMPLEQ_HEAD(ixl_aq_bufs, ixl_aq_buf); 1000 1001 struct ixl_dmamem { 1002 bus_dmamap_t ixm_map; 1003 bus_dma_segment_t ixm_seg; 1004 int ixm_nsegs; 1005 size_t ixm_size; 1006 caddr_t ixm_kva; 1007 }; 1008 #define IXL_DMA_MAP(_ixm) ((_ixm)->ixm_map) 1009 #define IXL_DMA_DVA(_ixm) ((_ixm)->ixm_map->dm_segs[0].ds_addr) 1010 #define IXL_DMA_KVA(_ixm) ((void *)(_ixm)->ixm_kva) 1011 #define IXL_DMA_LEN(_ixm) ((_ixm)->ixm_size) 1012 1013 struct ixl_hmc_entry { 1014 uint64_t hmc_base; 1015 uint32_t hmc_count; 1016 uint32_t hmc_size; 1017 }; 1018 1019 #define IXL_HMC_LAN_TX 0 1020 #define IXL_HMC_LAN_RX 1 1021 #define IXL_HMC_FCOE_CTX 2 1022 #define IXL_HMC_FCOE_FILTER 3 1023 #define IXL_HMC_COUNT 4 1024 1025 struct ixl_hmc_pack { 1026 uint16_t offset; 1027 uint16_t width; 1028 uint16_t lsb; 1029 }; 1030 1031 /* 1032 * these hmc objects have weird sizes and alignments, so these are abstract 1033 * representations of them that are nice for c to populate. 1034 * 1035 * the packing code relies on little-endian values being stored in the fields, 1036 * no high bits in the fields being set, and the fields must be packed in the 1037 * same order as they are in the ctx structure. 1038 */ 1039 1040 struct ixl_hmc_rxq { 1041 uint16_t head; 1042 uint8_t cpuid; 1043 uint64_t base; 1044 #define IXL_HMC_RXQ_BASE_UNIT 128 1045 uint16_t qlen; 1046 uint16_t dbuff; 1047 #define IXL_HMC_RXQ_DBUFF_UNIT 128 1048 uint8_t hbuff; 1049 #define IXL_HMC_RXQ_HBUFF_UNIT 64 1050 uint8_t dtype; 1051 #define IXL_HMC_RXQ_DTYPE_NOSPLIT 0x0 1052 #define IXL_HMC_RXQ_DTYPE_HSPLIT 0x1 1053 #define IXL_HMC_RXQ_DTYPE_SPLIT_ALWAYS 0x2 1054 uint8_t dsize; 1055 #define IXL_HMC_RXQ_DSIZE_16 0 1056 #define IXL_HMC_RXQ_DSIZE_32 1 1057 uint8_t crcstrip; 1058 uint8_t fc_ena; 1059 uint8_t l2sel; 1060 uint8_t hsplit_0; 1061 uint8_t hsplit_1; 1062 uint8_t showiv; 1063 uint16_t rxmax; 1064 uint8_t tphrdesc_ena; 1065 uint8_t tphwdesc_ena; 1066 uint8_t tphdata_ena; 1067 uint8_t tphhead_ena; 1068 uint8_t lrxqthresh; 1069 uint8_t prefena; 1070 }; 1071 1072 static const struct ixl_hmc_pack ixl_hmc_pack_rxq[] = { 1073 { offsetof(struct ixl_hmc_rxq, head), 13, 0 }, 1074 { offsetof(struct ixl_hmc_rxq, cpuid), 8, 13 }, 1075 { offsetof(struct ixl_hmc_rxq, base), 57, 32 }, 1076 { offsetof(struct ixl_hmc_rxq, qlen), 13, 89 }, 1077 { offsetof(struct ixl_hmc_rxq, dbuff), 7, 102 }, 1078 { offsetof(struct ixl_hmc_rxq, hbuff), 5, 109 }, 1079 { offsetof(struct ixl_hmc_rxq, dtype), 2, 114 }, 1080 { offsetof(struct ixl_hmc_rxq, dsize), 1, 116 }, 1081 { offsetof(struct ixl_hmc_rxq, crcstrip), 1, 117 }, 1082 { offsetof(struct ixl_hmc_rxq, fc_ena), 1, 118 }, 1083 { offsetof(struct ixl_hmc_rxq, l2sel), 1, 119 }, 1084 { offsetof(struct ixl_hmc_rxq, hsplit_0), 4, 120 }, 1085 { offsetof(struct ixl_hmc_rxq, hsplit_1), 2, 124 }, 1086 { offsetof(struct ixl_hmc_rxq, showiv), 1, 127 }, 1087 { offsetof(struct ixl_hmc_rxq, rxmax), 14, 174 }, 1088 { offsetof(struct ixl_hmc_rxq, tphrdesc_ena), 1, 193 }, 1089 { offsetof(struct ixl_hmc_rxq, tphwdesc_ena), 1, 194 }, 1090 { offsetof(struct ixl_hmc_rxq, tphdata_ena), 1, 195 }, 1091 { offsetof(struct ixl_hmc_rxq, tphhead_ena), 1, 196 }, 1092 { offsetof(struct ixl_hmc_rxq, lrxqthresh), 3, 198 }, 1093 { offsetof(struct ixl_hmc_rxq, prefena), 1, 201 }, 1094 }; 1095 1096 #define IXL_HMC_RXQ_MINSIZE (201 + 1) 1097 1098 struct ixl_hmc_txq { 1099 uint16_t head; 1100 uint8_t new_context; 1101 uint64_t base; 1102 #define IXL_HMC_TXQ_BASE_UNIT 128 1103 uint8_t fc_ena; 1104 uint8_t timesync_ena; 1105 uint8_t fd_ena; 1106 uint8_t alt_vlan_ena; 1107 uint16_t thead_wb; 1108 uint8_t cpuid; 1109 uint8_t head_wb_ena; 1110 #define IXL_HMC_TXQ_DESC_WB 0 1111 #define IXL_HMC_TXQ_HEAD_WB 1 1112 uint16_t qlen; 1113 uint8_t tphrdesc_ena; 1114 uint8_t tphrpacket_ena; 1115 uint8_t tphwdesc_ena; 1116 uint64_t head_wb_addr; 1117 uint32_t crc; 1118 uint16_t rdylist; 1119 uint8_t rdylist_act; 1120 }; 1121 1122 static const struct ixl_hmc_pack ixl_hmc_pack_txq[] = { 1123 { offsetof(struct ixl_hmc_txq, head), 13, 0 }, 1124 { offsetof(struct ixl_hmc_txq, new_context), 1, 30 }, 1125 { offsetof(struct ixl_hmc_txq, base), 57, 32 }, 1126 { offsetof(struct ixl_hmc_txq, fc_ena), 1, 89 }, 1127 { offsetof(struct ixl_hmc_txq, timesync_ena), 1, 90 }, 1128 { offsetof(struct ixl_hmc_txq, fd_ena), 1, 91 }, 1129 { offsetof(struct ixl_hmc_txq, alt_vlan_ena), 1, 92 }, 1130 { offsetof(struct ixl_hmc_txq, cpuid), 8, 96 }, 1131 /* line 1 */ 1132 { offsetof(struct ixl_hmc_txq, thead_wb), 13, 0 + 128 }, 1133 { offsetof(struct ixl_hmc_txq, head_wb_ena), 1, 32 + 128 }, 1134 { offsetof(struct ixl_hmc_txq, qlen), 13, 33 + 128 }, 1135 { offsetof(struct ixl_hmc_txq, tphrdesc_ena), 1, 46 + 128 }, 1136 { offsetof(struct ixl_hmc_txq, tphrpacket_ena), 1, 47 + 128 }, 1137 { offsetof(struct ixl_hmc_txq, tphwdesc_ena), 1, 48 + 128 }, 1138 { offsetof(struct ixl_hmc_txq, head_wb_addr), 64, 64 + 128 }, 1139 /* line 7 */ 1140 { offsetof(struct ixl_hmc_txq, crc), 32, 0 + (7*128) }, 1141 { offsetof(struct ixl_hmc_txq, rdylist), 10, 84 + (7*128) }, 1142 { offsetof(struct ixl_hmc_txq, rdylist_act), 1, 94 + (7*128) }, 1143 }; 1144 1145 #define IXL_HMC_TXQ_MINSIZE (94 + (7*128) + 1) 1146 1147 struct ixl_rss_key { 1148 uint32_t key[13]; 1149 }; 1150 1151 struct ixl_rss_lut_128 { 1152 uint32_t entries[128 / sizeof(uint32_t)]; 1153 }; 1154 1155 struct ixl_rss_lut_512 { 1156 uint32_t entries[512 / sizeof(uint32_t)]; 1157 }; 1158 1159 /* driver structures */ 1160 1161 struct ixl_vector; 1162 struct ixl_chip; 1163 1164 struct ixl_tx_map { 1165 struct mbuf *txm_m; 1166 bus_dmamap_t txm_map; 1167 unsigned int txm_eop; 1168 }; 1169 1170 struct ixl_tx_ring { 1171 struct ixl_softc *txr_sc; 1172 struct ixl_vector *txr_vector; 1173 struct ifqueue *txr_ifq; 1174 1175 unsigned int txr_prod; 1176 unsigned int txr_cons; 1177 1178 struct ixl_tx_map *txr_maps; 1179 struct ixl_dmamem txr_mem; 1180 1181 bus_size_t txr_tail; 1182 unsigned int txr_qid; 1183 } __aligned(CACHE_LINE_SIZE); 1184 1185 struct ixl_rx_map { 1186 struct mbuf *rxm_m; 1187 bus_dmamap_t rxm_map; 1188 }; 1189 1190 struct ixl_rx_ring { 1191 struct ixl_softc *rxr_sc; 1192 struct ixl_vector *rxr_vector; 1193 struct ifiqueue *rxr_ifiq; 1194 1195 struct if_rxring rxr_acct; 1196 struct timeout rxr_refill; 1197 1198 unsigned int rxr_prod; 1199 unsigned int rxr_cons; 1200 1201 struct ixl_rx_map *rxr_maps; 1202 struct ixl_dmamem rxr_mem; 1203 1204 struct mbuf *rxr_m_head; 1205 struct mbuf **rxr_m_tail; 1206 1207 bus_size_t rxr_tail; 1208 unsigned int rxr_qid; 1209 } __aligned(CACHE_LINE_SIZE); 1210 1211 struct ixl_atq { 1212 struct ixl_aq_desc iatq_desc; 1213 void *iatq_arg; 1214 void (*iatq_fn)(struct ixl_softc *, void *); 1215 }; 1216 SIMPLEQ_HEAD(ixl_atq_list, ixl_atq); 1217 1218 struct ixl_vector { 1219 struct ixl_softc *iv_sc; 1220 struct ixl_rx_ring *iv_rxr; 1221 struct ixl_tx_ring *iv_txr; 1222 int iv_qid; 1223 void *iv_ihc; 1224 char iv_name[16]; 1225 } __aligned(CACHE_LINE_SIZE); 1226 1227 struct ixl_softc { 1228 struct device sc_dev; 1229 const struct ixl_chip *sc_chip; 1230 struct arpcom sc_ac; 1231 struct ifmedia sc_media; 1232 uint64_t sc_media_status; 1233 uint64_t sc_media_active; 1234 1235 pci_chipset_tag_t sc_pc; 1236 pci_intr_handle_t sc_ih; 1237 void *sc_ihc; 1238 pcitag_t sc_tag; 1239 1240 bus_dma_tag_t sc_dmat; 1241 bus_space_tag_t sc_memt; 1242 bus_space_handle_t sc_memh; 1243 bus_size_t sc_mems; 1244 1245 uint8_t sc_pf_id; 1246 uint16_t sc_uplink_seid; /* le */ 1247 uint16_t sc_downlink_seid; /* le */ 1248 uint16_t sc_veb_seid; /* le */ 1249 uint16_t sc_vsi_number; /* le */ 1250 uint16_t sc_seid; 1251 unsigned int sc_base_queue; 1252 unsigned int sc_port; 1253 1254 struct ixl_dmamem sc_scratch; 1255 1256 const struct ixl_aq_regs * 1257 sc_aq_regs; 1258 1259 struct ixl_dmamem sc_atq; 1260 unsigned int sc_atq_prod; 1261 unsigned int sc_atq_cons; 1262 1263 struct ixl_dmamem sc_arq; 1264 struct task sc_arq_task; 1265 struct ixl_aq_bufs sc_arq_idle; 1266 struct ixl_aq_bufs sc_arq_live; 1267 struct if_rxring sc_arq_ring; 1268 unsigned int sc_arq_prod; 1269 unsigned int sc_arq_cons; 1270 1271 struct mutex sc_link_state_mtx; 1272 struct task sc_link_state_task; 1273 struct ixl_atq sc_link_state_atq; 1274 1275 struct ixl_dmamem sc_hmc_sd; 1276 struct ixl_dmamem sc_hmc_pd; 1277 struct ixl_hmc_entry sc_hmc_entries[IXL_HMC_COUNT]; 1278 1279 unsigned int sc_tx_ring_ndescs; 1280 unsigned int sc_rx_ring_ndescs; 1281 unsigned int sc_nqueues; /* 1 << sc_nqueues */ 1282 1283 struct intrmap *sc_intrmap; 1284 struct ixl_vector *sc_vectors; 1285 1286 struct rwlock sc_cfg_lock; 1287 unsigned int sc_dead; 1288 1289 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 1290 1291 #if NKSTAT > 0 1292 struct mutex sc_kstat_mtx; 1293 struct timeout sc_kstat_tmo; 1294 struct kstat *sc_port_kstat; 1295 struct kstat *sc_vsi_kstat; 1296 #endif 1297 }; 1298 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) 1299 1300 #define delaymsec(_ms) delay(1000 * (_ms)) 1301 1302 static void ixl_clear_hw(struct ixl_softc *); 1303 static int ixl_pf_reset(struct ixl_softc *); 1304 1305 static int ixl_dmamem_alloc(struct ixl_softc *, struct ixl_dmamem *, 1306 bus_size_t, u_int); 1307 static void ixl_dmamem_free(struct ixl_softc *, struct ixl_dmamem *); 1308 1309 static int ixl_arq_fill(struct ixl_softc *); 1310 static void ixl_arq_unfill(struct ixl_softc *); 1311 1312 static int ixl_atq_poll(struct ixl_softc *, struct ixl_aq_desc *, 1313 unsigned int); 1314 static void ixl_atq_set(struct ixl_atq *, 1315 void (*)(struct ixl_softc *, void *), void *); 1316 static void ixl_atq_post(struct ixl_softc *, struct ixl_atq *); 1317 static void ixl_atq_done(struct ixl_softc *); 1318 static void ixl_atq_exec(struct ixl_softc *, struct ixl_atq *, 1319 const char *); 1320 static int ixl_get_version(struct ixl_softc *); 1321 static int ixl_pxe_clear(struct ixl_softc *); 1322 static int ixl_lldp_shut(struct ixl_softc *); 1323 static int ixl_get_mac(struct ixl_softc *); 1324 static int ixl_get_switch_config(struct ixl_softc *); 1325 static int ixl_phy_mask_ints(struct ixl_softc *); 1326 static int ixl_get_phy_types(struct ixl_softc *, uint64_t *); 1327 static int ixl_restart_an(struct ixl_softc *); 1328 static int ixl_hmc(struct ixl_softc *); 1329 static void ixl_hmc_free(struct ixl_softc *); 1330 static int ixl_get_vsi(struct ixl_softc *); 1331 static int ixl_set_vsi(struct ixl_softc *); 1332 static int ixl_get_link_status(struct ixl_softc *); 1333 static int ixl_set_link_status(struct ixl_softc *, 1334 const struct ixl_aq_desc *); 1335 static int ixl_add_macvlan(struct ixl_softc *, uint8_t *, uint16_t, 1336 uint16_t); 1337 static int ixl_remove_macvlan(struct ixl_softc *, uint8_t *, uint16_t, 1338 uint16_t); 1339 static void ixl_link_state_update(void *); 1340 static void ixl_arq(void *); 1341 static void ixl_hmc_pack(void *, const void *, 1342 const struct ixl_hmc_pack *, unsigned int); 1343 1344 static int ixl_get_sffpage(struct ixl_softc *, struct if_sffpage *); 1345 static int ixl_sff_get_byte(struct ixl_softc *, uint8_t, uint32_t, 1346 uint8_t *); 1347 static int ixl_sff_set_byte(struct ixl_softc *, uint8_t, uint32_t, 1348 uint8_t); 1349 1350 static int ixl_match(struct device *, void *, void *); 1351 static void ixl_attach(struct device *, struct device *, void *); 1352 1353 static void ixl_media_add(struct ixl_softc *, uint64_t); 1354 static int ixl_media_change(struct ifnet *); 1355 static void ixl_media_status(struct ifnet *, struct ifmediareq *); 1356 static void ixl_watchdog(struct ifnet *); 1357 static int ixl_ioctl(struct ifnet *, u_long, caddr_t); 1358 static void ixl_start(struct ifqueue *); 1359 static int ixl_intr0(void *); 1360 static int ixl_intr_vector(void *); 1361 static int ixl_up(struct ixl_softc *); 1362 static int ixl_down(struct ixl_softc *); 1363 static int ixl_iff(struct ixl_softc *); 1364 1365 static struct ixl_tx_ring * 1366 ixl_txr_alloc(struct ixl_softc *, unsigned int); 1367 static void ixl_txr_qdis(struct ixl_softc *, struct ixl_tx_ring *, int); 1368 static void ixl_txr_config(struct ixl_softc *, struct ixl_tx_ring *); 1369 static int ixl_txr_enabled(struct ixl_softc *, struct ixl_tx_ring *); 1370 static int ixl_txr_disabled(struct ixl_softc *, struct ixl_tx_ring *); 1371 static void ixl_txr_unconfig(struct ixl_softc *, struct ixl_tx_ring *); 1372 static void ixl_txr_clean(struct ixl_softc *, struct ixl_tx_ring *); 1373 static void ixl_txr_free(struct ixl_softc *, struct ixl_tx_ring *); 1374 static int ixl_txeof(struct ixl_softc *, struct ixl_tx_ring *); 1375 1376 static struct ixl_rx_ring * 1377 ixl_rxr_alloc(struct ixl_softc *, unsigned int); 1378 static void ixl_rxr_config(struct ixl_softc *, struct ixl_rx_ring *); 1379 static int ixl_rxr_enabled(struct ixl_softc *, struct ixl_rx_ring *); 1380 static int ixl_rxr_disabled(struct ixl_softc *, struct ixl_rx_ring *); 1381 static void ixl_rxr_unconfig(struct ixl_softc *, struct ixl_rx_ring *); 1382 static void ixl_rxr_clean(struct ixl_softc *, struct ixl_rx_ring *); 1383 static void ixl_rxr_free(struct ixl_softc *, struct ixl_rx_ring *); 1384 static int ixl_rxeof(struct ixl_softc *, struct ixl_rx_ring *); 1385 static void ixl_rxfill(struct ixl_softc *, struct ixl_rx_ring *); 1386 static void ixl_rxrefill(void *); 1387 static int ixl_rxrinfo(struct ixl_softc *, struct if_rxrinfo *); 1388 1389 #if NKSTAT > 0 1390 static void ixl_kstat_attach(struct ixl_softc *); 1391 #endif 1392 1393 struct cfdriver ixl_cd = { 1394 NULL, 1395 "ixl", 1396 DV_IFNET, 1397 }; 1398 1399 struct cfattach ixl_ca = { 1400 sizeof(struct ixl_softc), 1401 ixl_match, 1402 ixl_attach, 1403 }; 1404 1405 static const struct ixl_phy_type ixl_phy_type_map[] = { 1406 { 1ULL << IXL_PHY_TYPE_SGMII, IFM_1000_SGMII }, 1407 { 1ULL << IXL_PHY_TYPE_1000BASE_KX, IFM_1000_KX }, 1408 { 1ULL << IXL_PHY_TYPE_10GBASE_KX4, IFM_10G_KX4 }, 1409 { 1ULL << IXL_PHY_TYPE_10GBASE_KR, IFM_10G_KR }, 1410 { 1ULL << IXL_PHY_TYPE_40GBASE_KR4, IFM_40G_KR4 }, 1411 { 1ULL << IXL_PHY_TYPE_XAUI | 1412 1ULL << IXL_PHY_TYPE_XFI, IFM_10G_CX4 }, 1413 { 1ULL << IXL_PHY_TYPE_SFI, IFM_10G_SFI }, 1414 { 1ULL << IXL_PHY_TYPE_XLAUI | 1415 1ULL << IXL_PHY_TYPE_XLPPI, IFM_40G_XLPPI }, 1416 { 1ULL << IXL_PHY_TYPE_40GBASE_CR4_CU | 1417 1ULL << IXL_PHY_TYPE_40GBASE_CR4, IFM_40G_CR4 }, 1418 { 1ULL << IXL_PHY_TYPE_10GBASE_CR1_CU | 1419 1ULL << IXL_PHY_TYPE_10GBASE_CR1, IFM_10G_CR1 }, 1420 { 1ULL << IXL_PHY_TYPE_10GBASE_AOC, IFM_10G_AOC }, 1421 { 1ULL << IXL_PHY_TYPE_40GBASE_AOC, IFM_40G_AOC }, 1422 { 1ULL << IXL_PHY_TYPE_100BASE_TX, IFM_100_TX }, 1423 { 1ULL << IXL_PHY_TYPE_1000BASE_T_OPTICAL | 1424 1ULL << IXL_PHY_TYPE_1000BASE_T, IFM_1000_T }, 1425 { 1ULL << IXL_PHY_TYPE_10GBASE_T, IFM_10G_T }, 1426 { 1ULL << IXL_PHY_TYPE_10GBASE_SR, IFM_10G_SR }, 1427 { 1ULL << IXL_PHY_TYPE_10GBASE_LR, IFM_10G_LR }, 1428 { 1ULL << IXL_PHY_TYPE_10GBASE_SFPP_CU, IFM_10G_SFP_CU }, 1429 { 1ULL << IXL_PHY_TYPE_40GBASE_SR4, IFM_40G_SR4 }, 1430 { 1ULL << IXL_PHY_TYPE_40GBASE_LR4, IFM_40G_LR4 }, 1431 { 1ULL << IXL_PHY_TYPE_1000BASE_SX, IFM_1000_SX }, 1432 { 1ULL << IXL_PHY_TYPE_1000BASE_LX, IFM_1000_LX }, 1433 { 1ULL << IXL_PHY_TYPE_20GBASE_KR2, IFM_20G_KR2 }, 1434 { 1ULL << IXL_PHY_TYPE_25GBASE_KR, IFM_25G_KR }, 1435 { 1ULL << IXL_PHY_TYPE_25GBASE_CR, IFM_25G_CR }, 1436 { 1ULL << IXL_PHY_TYPE_25GBASE_SR, IFM_25G_SR }, 1437 { 1ULL << IXL_PHY_TYPE_25GBASE_LR, IFM_25G_LR }, 1438 { 1ULL << IXL_PHY_TYPE_25GBASE_AOC, IFM_25G_AOC }, 1439 { 1ULL << IXL_PHY_TYPE_25GBASE_ACC, IFM_25G_CR }, 1440 }; 1441 1442 static const struct ixl_speed_type ixl_speed_type_map[] = { 1443 { IXL_AQ_LINK_SPEED_40GB, IF_Gbps(40) }, 1444 { IXL_AQ_LINK_SPEED_25GB, IF_Gbps(25) }, 1445 { IXL_AQ_LINK_SPEED_10GB, IF_Gbps(10) }, 1446 { IXL_AQ_LINK_SPEED_1GB, IF_Gbps(1) }, 1447 }; 1448 1449 static const struct ixl_aq_regs ixl_pf_aq_regs = { 1450 .atq_tail = I40E_PF_ATQT, 1451 .atq_tail_mask = I40E_PF_ATQT_ATQT_MASK, 1452 .atq_head = I40E_PF_ATQH, 1453 .atq_head_mask = I40E_PF_ATQH_ATQH_MASK, 1454 .atq_len = I40E_PF_ATQLEN, 1455 .atq_bal = I40E_PF_ATQBAL, 1456 .atq_bah = I40E_PF_ATQBAH, 1457 .atq_len_enable = I40E_PF_ATQLEN_ATQENABLE_MASK, 1458 1459 .arq_tail = I40E_PF_ARQT, 1460 .arq_tail_mask = I40E_PF_ARQT_ARQT_MASK, 1461 .arq_head = I40E_PF_ARQH, 1462 .arq_head_mask = I40E_PF_ARQH_ARQH_MASK, 1463 .arq_len = I40E_PF_ARQLEN, 1464 .arq_bal = I40E_PF_ARQBAL, 1465 .arq_bah = I40E_PF_ARQBAH, 1466 .arq_len_enable = I40E_PF_ARQLEN_ARQENABLE_MASK, 1467 }; 1468 1469 #define ixl_rd(_s, _r) \ 1470 bus_space_read_4((_s)->sc_memt, (_s)->sc_memh, (_r)) 1471 #define ixl_wr(_s, _r, _v) \ 1472 bus_space_write_4((_s)->sc_memt, (_s)->sc_memh, (_r), (_v)) 1473 #define ixl_barrier(_s, _r, _l, _o) \ 1474 bus_space_barrier((_s)->sc_memt, (_s)->sc_memh, (_r), (_l), (_o)) 1475 #define ixl_intr_enable(_s) \ 1476 ixl_wr((_s), I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_INTENA_MASK | \ 1477 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | \ 1478 (IXL_NOITR << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)) 1479 1480 #define ixl_nqueues(_sc) (1 << (_sc)->sc_nqueues) 1481 1482 #ifdef __LP64__ 1483 #define ixl_dmamem_hi(_ixm) (uint32_t)(IXL_DMA_DVA(_ixm) >> 32) 1484 #else 1485 #define ixl_dmamem_hi(_ixm) 0 1486 #endif 1487 1488 #define ixl_dmamem_lo(_ixm) (uint32_t)IXL_DMA_DVA(_ixm) 1489 1490 static inline void 1491 ixl_aq_dva(struct ixl_aq_desc *iaq, bus_addr_t addr) 1492 { 1493 #ifdef __LP64__ 1494 htolem32(&iaq->iaq_param[2], addr >> 32); 1495 #else 1496 iaq->iaq_param[2] = htole32(0); 1497 #endif 1498 htolem32(&iaq->iaq_param[3], addr); 1499 } 1500 1501 #if _BYTE_ORDER == _BIG_ENDIAN 1502 #define HTOLE16(_x) (uint16_t)(((_x) & 0xff) << 8 | ((_x) & 0xff00) >> 8) 1503 #else 1504 #define HTOLE16(_x) (_x) 1505 #endif 1506 1507 static struct rwlock ixl_sff_lock = RWLOCK_INITIALIZER("ixlsff"); 1508 1509 /* deal with differences between chips */ 1510 1511 struct ixl_chip { 1512 uint64_t ic_rss_hena; 1513 uint32_t (*ic_rd_ctl)(struct ixl_softc *, uint32_t); 1514 void (*ic_wr_ctl)(struct ixl_softc *, uint32_t, 1515 uint32_t); 1516 1517 int (*ic_set_rss_key)(struct ixl_softc *, 1518 const struct ixl_rss_key *); 1519 int (*ic_set_rss_lut)(struct ixl_softc *, 1520 const struct ixl_rss_lut_128 *); 1521 }; 1522 1523 static inline uint64_t 1524 ixl_rss_hena(struct ixl_softc *sc) 1525 { 1526 return (sc->sc_chip->ic_rss_hena); 1527 } 1528 1529 static inline uint32_t 1530 ixl_rd_ctl(struct ixl_softc *sc, uint32_t r) 1531 { 1532 return ((*sc->sc_chip->ic_rd_ctl)(sc, r)); 1533 } 1534 1535 static inline void 1536 ixl_wr_ctl(struct ixl_softc *sc, uint32_t r, uint32_t v) 1537 { 1538 (*sc->sc_chip->ic_wr_ctl)(sc, r, v); 1539 } 1540 1541 static inline int 1542 ixl_set_rss_key(struct ixl_softc *sc, const struct ixl_rss_key *rsskey) 1543 { 1544 return ((*sc->sc_chip->ic_set_rss_key)(sc, rsskey)); 1545 } 1546 1547 static inline int 1548 ixl_set_rss_lut(struct ixl_softc *sc, const struct ixl_rss_lut_128 *lut) 1549 { 1550 return ((*sc->sc_chip->ic_set_rss_lut)(sc, lut)); 1551 } 1552 1553 /* 710 chip specifics */ 1554 1555 static uint32_t ixl_710_rd_ctl(struct ixl_softc *, uint32_t); 1556 static void ixl_710_wr_ctl(struct ixl_softc *, uint32_t, uint32_t); 1557 static int ixl_710_set_rss_key(struct ixl_softc *, 1558 const struct ixl_rss_key *); 1559 static int ixl_710_set_rss_lut(struct ixl_softc *, 1560 const struct ixl_rss_lut_128 *); 1561 1562 static const struct ixl_chip ixl_710 = { 1563 .ic_rss_hena = IXL_RSS_HENA_BASE_710, 1564 .ic_rd_ctl = ixl_710_rd_ctl, 1565 .ic_wr_ctl = ixl_710_wr_ctl, 1566 .ic_set_rss_key = ixl_710_set_rss_key, 1567 .ic_set_rss_lut = ixl_710_set_rss_lut, 1568 }; 1569 1570 /* 722 chip specifics */ 1571 1572 static uint32_t ixl_722_rd_ctl(struct ixl_softc *, uint32_t); 1573 static void ixl_722_wr_ctl(struct ixl_softc *, uint32_t, uint32_t); 1574 static int ixl_722_set_rss_key(struct ixl_softc *, 1575 const struct ixl_rss_key *); 1576 static int ixl_722_set_rss_lut(struct ixl_softc *, 1577 const struct ixl_rss_lut_128 *); 1578 1579 static const struct ixl_chip ixl_722 = { 1580 .ic_rss_hena = IXL_RSS_HENA_BASE_722, 1581 .ic_rd_ctl = ixl_722_rd_ctl, 1582 .ic_wr_ctl = ixl_722_wr_ctl, 1583 .ic_set_rss_key = ixl_722_set_rss_key, 1584 .ic_set_rss_lut = ixl_722_set_rss_lut, 1585 }; 1586 1587 /* driver code */ 1588 1589 struct ixl_device { 1590 const struct ixl_chip *id_chip; 1591 pci_vendor_id_t id_vid; 1592 pci_product_id_t id_pid; 1593 }; 1594 1595 static const struct ixl_device ixl_devices[] = { 1596 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_SFP }, 1597 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_40G_BP }, 1598 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_BP, }, 1599 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_1 }, 1600 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_2 }, 1601 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_QSFP }, 1602 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_BASET }, 1603 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_1 }, 1604 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_2 }, 1605 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_T4_10G }, 1606 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XXV710_25G_BP }, 1607 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XXV710_25G_SFP28, }, 1608 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_KX }, 1609 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_QSFP }, 1610 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_SFP_1 }, 1611 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_1G }, 1612 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_T }, 1613 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_SFP_2 }, 1614 }; 1615 1616 static const struct ixl_device * 1617 ixl_device_lookup(struct pci_attach_args *pa) 1618 { 1619 pci_vendor_id_t vid = PCI_VENDOR(pa->pa_id); 1620 pci_product_id_t pid = PCI_PRODUCT(pa->pa_id); 1621 const struct ixl_device *id; 1622 unsigned int i; 1623 1624 for (i = 0; i < nitems(ixl_devices); i++) { 1625 id = &ixl_devices[i]; 1626 if (id->id_vid == vid && id->id_pid == pid) 1627 return (id); 1628 } 1629 1630 return (NULL); 1631 } 1632 1633 static int 1634 ixl_match(struct device *parent, void *match, void *aux) 1635 { 1636 return (ixl_device_lookup(aux) != NULL); 1637 } 1638 1639 void 1640 ixl_attach(struct device *parent, struct device *self, void *aux) 1641 { 1642 struct ixl_softc *sc = (struct ixl_softc *)self; 1643 struct ifnet *ifp = &sc->sc_ac.ac_if; 1644 struct pci_attach_args *pa = aux; 1645 pcireg_t memtype; 1646 uint32_t port, ari, func; 1647 uint64_t phy_types = 0; 1648 unsigned int nqueues, i; 1649 int tries; 1650 1651 rw_init(&sc->sc_cfg_lock, "ixlcfg"); 1652 1653 sc->sc_chip = ixl_device_lookup(pa)->id_chip; 1654 sc->sc_pc = pa->pa_pc; 1655 sc->sc_tag = pa->pa_tag; 1656 sc->sc_dmat = pa->pa_dmat; 1657 sc->sc_aq_regs = &ixl_pf_aq_regs; 1658 1659 sc->sc_nqueues = 0; /* 1 << 0 is 1 queue */ 1660 sc->sc_tx_ring_ndescs = 1024; 1661 sc->sc_rx_ring_ndescs = 1024; 1662 1663 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, IXL_PCIREG); 1664 if (pci_mapreg_map(pa, IXL_PCIREG, memtype, 0, 1665 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems, 0)) { 1666 printf(": unable to map registers\n"); 1667 return; 1668 } 1669 1670 sc->sc_base_queue = (ixl_rd(sc, I40E_PFLAN_QALLOC) & 1671 I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1672 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1673 1674 ixl_clear_hw(sc); 1675 if (ixl_pf_reset(sc) == -1) { 1676 /* error printed by ixl_pf_reset */ 1677 goto unmap; 1678 } 1679 1680 port = ixl_rd(sc, I40E_PFGEN_PORTNUM); 1681 port &= I40E_PFGEN_PORTNUM_PORT_NUM_MASK; 1682 port >>= I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 1683 sc->sc_port = port; 1684 printf(": port %u", port); 1685 1686 ari = ixl_rd(sc, I40E_GLPCI_CAPSUP); 1687 ari &= I40E_GLPCI_CAPSUP_ARI_EN_MASK; 1688 ari >>= I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 1689 1690 func = ixl_rd(sc, I40E_PF_FUNC_RID); 1691 sc->sc_pf_id = func & (ari ? 0xff : 0x7); 1692 1693 /* initialise the adminq */ 1694 1695 if (ixl_dmamem_alloc(sc, &sc->sc_atq, 1696 sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) { 1697 printf("\n" "%s: unable to allocate atq\n", DEVNAME(sc)); 1698 goto unmap; 1699 } 1700 1701 SIMPLEQ_INIT(&sc->sc_arq_idle); 1702 SIMPLEQ_INIT(&sc->sc_arq_live); 1703 if_rxr_init(&sc->sc_arq_ring, 2, IXL_AQ_NUM - 1); 1704 task_set(&sc->sc_arq_task, ixl_arq, sc); 1705 sc->sc_arq_cons = 0; 1706 sc->sc_arq_prod = 0; 1707 1708 if (ixl_dmamem_alloc(sc, &sc->sc_arq, 1709 sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) { 1710 printf("\n" "%s: unable to allocate arq\n", DEVNAME(sc)); 1711 goto free_atq; 1712 } 1713 1714 if (!ixl_arq_fill(sc)) { 1715 printf("\n" "%s: unable to fill arq descriptors\n", 1716 DEVNAME(sc)); 1717 goto free_arq; 1718 } 1719 1720 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 1721 0, IXL_DMA_LEN(&sc->sc_atq), 1722 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1723 1724 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 1725 0, IXL_DMA_LEN(&sc->sc_arq), 1726 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1727 1728 for (tries = 0; tries < 10; tries++) { 1729 int rv; 1730 1731 sc->sc_atq_cons = 0; 1732 sc->sc_atq_prod = 0; 1733 1734 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 1735 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 1736 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 1737 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 1738 1739 ixl_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 1740 1741 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 1742 ixl_dmamem_lo(&sc->sc_atq)); 1743 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 1744 ixl_dmamem_hi(&sc->sc_atq)); 1745 ixl_wr(sc, sc->sc_aq_regs->atq_len, 1746 sc->sc_aq_regs->atq_len_enable | IXL_AQ_NUM); 1747 1748 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 1749 ixl_dmamem_lo(&sc->sc_arq)); 1750 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 1751 ixl_dmamem_hi(&sc->sc_arq)); 1752 ixl_wr(sc, sc->sc_aq_regs->arq_len, 1753 sc->sc_aq_regs->arq_len_enable | IXL_AQ_NUM); 1754 1755 rv = ixl_get_version(sc); 1756 if (rv == 0) 1757 break; 1758 if (rv != ETIMEDOUT) { 1759 printf(", unable to get firmware version\n"); 1760 goto shutdown; 1761 } 1762 1763 delaymsec(100); 1764 } 1765 1766 ixl_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 1767 1768 if (ixl_pxe_clear(sc) != 0) { 1769 /* error printed by ixl_pxe_clear */ 1770 goto shutdown; 1771 } 1772 1773 if (ixl_get_mac(sc) != 0) { 1774 /* error printed by ixl_get_mac */ 1775 goto shutdown; 1776 } 1777 1778 if (pci_intr_map_msix(pa, 0, &sc->sc_ih) == 0) { 1779 int nmsix = pci_intr_msix_count(pa->pa_pc, pa->pa_tag); 1780 if (nmsix > 1) { /* we used 1 (the 0th) for the adminq */ 1781 nmsix--; 1782 1783 sc->sc_intrmap = intrmap_create(&sc->sc_dev, 1784 nmsix, IXL_MAX_VECTORS, INTRMAP_POWEROF2); 1785 nqueues = intrmap_count(sc->sc_intrmap); 1786 KASSERT(nqueues > 0); 1787 KASSERT(powerof2(nqueues)); 1788 sc->sc_nqueues = fls(nqueues) - 1; 1789 } 1790 } else { 1791 if (pci_intr_map_msi(pa, &sc->sc_ih) != 0 && 1792 pci_intr_map(pa, &sc->sc_ih) != 0) { 1793 printf(", unable to map interrupt\n"); 1794 goto shutdown; 1795 } 1796 } 1797 1798 nqueues = ixl_nqueues(sc); 1799 1800 printf(", %s, %d queue%s, address %s\n", 1801 pci_intr_string(sc->sc_pc, sc->sc_ih), ixl_nqueues(sc), 1802 (nqueues > 1 ? "s" : ""), 1803 ether_sprintf(sc->sc_ac.ac_enaddr)); 1804 1805 if (ixl_hmc(sc) != 0) { 1806 /* error printed by ixl_hmc */ 1807 goto shutdown; 1808 } 1809 1810 if (ixl_lldp_shut(sc) != 0) { 1811 /* error printed by ixl_lldp_shut */ 1812 goto free_hmc; 1813 } 1814 1815 if (ixl_phy_mask_ints(sc) != 0) { 1816 /* error printed by ixl_phy_mask_ints */ 1817 goto free_hmc; 1818 } 1819 1820 if (ixl_restart_an(sc) != 0) { 1821 /* error printed by ixl_restart_an */ 1822 goto free_hmc; 1823 } 1824 1825 if (ixl_get_switch_config(sc) != 0) { 1826 /* error printed by ixl_get_switch_config */ 1827 goto free_hmc; 1828 } 1829 1830 if (ixl_get_phy_types(sc, &phy_types) != 0) { 1831 /* error printed by ixl_get_phy_abilities */ 1832 goto free_hmc; 1833 } 1834 1835 if (ixl_get_link_status(sc) != 0) { 1836 /* error printed by ixl_get_link_status */ 1837 goto free_hmc; 1838 } 1839 1840 if (ixl_dmamem_alloc(sc, &sc->sc_scratch, 1841 sizeof(struct ixl_aq_vsi_data), 8) != 0) { 1842 printf("%s: unable to allocate scratch buffer\n", DEVNAME(sc)); 1843 goto free_hmc; 1844 } 1845 1846 if (ixl_get_vsi(sc) != 0) { 1847 /* error printed by ixl_get_vsi */ 1848 goto free_hmc; 1849 } 1850 1851 if (ixl_set_vsi(sc) != 0) { 1852 /* error printed by ixl_set_vsi */ 1853 goto free_scratch; 1854 } 1855 1856 sc->sc_ihc = pci_intr_establish(sc->sc_pc, sc->sc_ih, 1857 IPL_NET | IPL_MPSAFE, ixl_intr0, sc, DEVNAME(sc)); 1858 if (sc->sc_ihc == NULL) { 1859 printf("%s: unable to establish interrupt handler\n", 1860 DEVNAME(sc)); 1861 goto free_scratch; 1862 } 1863 1864 sc->sc_vectors = mallocarray(sizeof(*sc->sc_vectors), nqueues, 1865 M_DEVBUF, M_WAITOK|M_CANFAIL|M_ZERO); 1866 if (sc->sc_vectors == NULL) { 1867 printf("%s: unable to allocate vectors\n", DEVNAME(sc)); 1868 goto free_scratch; 1869 } 1870 1871 for (i = 0; i < nqueues; i++) { 1872 struct ixl_vector *iv = &sc->sc_vectors[i]; 1873 iv->iv_sc = sc; 1874 iv->iv_qid = i; 1875 snprintf(iv->iv_name, sizeof(iv->iv_name), 1876 "%s:%u", DEVNAME(sc), i); /* truncated? */ 1877 } 1878 1879 if (sc->sc_intrmap) { 1880 for (i = 0; i < nqueues; i++) { 1881 struct ixl_vector *iv = &sc->sc_vectors[i]; 1882 pci_intr_handle_t ih; 1883 int v = i + 1; /* 0 is used for adminq */ 1884 1885 if (pci_intr_map_msix(pa, v, &ih)) { 1886 printf("%s: unable to map msi-x vector %d\n", 1887 DEVNAME(sc), v); 1888 goto free_vectors; 1889 } 1890 1891 iv->iv_ihc = pci_intr_establish_cpu(sc->sc_pc, ih, 1892 IPL_NET | IPL_MPSAFE, 1893 intrmap_cpu(sc->sc_intrmap, i), 1894 ixl_intr_vector, iv, iv->iv_name); 1895 if (iv->iv_ihc == NULL) { 1896 printf("%s: unable to establish interrupt %d\n", 1897 DEVNAME(sc), v); 1898 goto free_vectors; 1899 } 1900 1901 ixl_wr(sc, I40E_PFINT_DYN_CTLN(i), 1902 I40E_PFINT_DYN_CTLN_INTENA_MASK | 1903 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1904 (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)); 1905 } 1906 } 1907 1908 ifp->if_softc = sc; 1909 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1910 ifp->if_xflags = IFXF_MPSAFE; 1911 ifp->if_ioctl = ixl_ioctl; 1912 ifp->if_qstart = ixl_start; 1913 ifp->if_watchdog = ixl_watchdog; 1914 ifp->if_hardmtu = IXL_HARDMTU; 1915 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 1916 ifq_set_maxlen(&ifp->if_snd, sc->sc_tx_ring_ndescs); 1917 1918 ifp->if_capabilities = IFCAP_VLAN_MTU; 1919 #if 0 1920 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1921 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1922 IFCAP_CSUM_UDPv4; 1923 #endif 1924 1925 ifmedia_init(&sc->sc_media, 0, ixl_media_change, ixl_media_status); 1926 1927 ixl_media_add(sc, phy_types); 1928 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 1929 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 1930 1931 if_attach(ifp); 1932 ether_ifattach(ifp); 1933 1934 if_attach_queues(ifp, nqueues); 1935 if_attach_iqueues(ifp, nqueues); 1936 1937 mtx_init(&sc->sc_link_state_mtx, IPL_NET); 1938 task_set(&sc->sc_link_state_task, ixl_link_state_update, sc); 1939 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 1940 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | 1941 I40E_PFINT_ICR0_ENA_ADMINQ_MASK); 1942 ixl_wr(sc, I40E_PFINT_STAT_CTL0, 1943 IXL_NOITR << I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT); 1944 1945 /* remove default mac filter and replace it so we can see vlans */ 1946 ixl_remove_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 0); 1947 ixl_remove_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 1948 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1949 ixl_add_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 1950 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 1951 ixl_add_macvlan(sc, etherbroadcastaddr, 0, 1952 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 1953 memcpy(sc->sc_enaddr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 1954 1955 ixl_intr_enable(sc); 1956 1957 #if NKSTAT > 0 1958 ixl_kstat_attach(sc); 1959 #endif 1960 1961 return; 1962 free_vectors: 1963 if (sc->sc_intrmap != NULL) { 1964 for (i = 0; i < nqueues; i++) { 1965 struct ixl_vector *iv = &sc->sc_vectors[i]; 1966 if (iv->iv_ihc == NULL) 1967 continue; 1968 pci_intr_disestablish(sc->sc_pc, iv->iv_ihc); 1969 } 1970 } 1971 free(sc->sc_vectors, M_DEVBUF, nqueues * sizeof(*sc->sc_vectors)); 1972 free_scratch: 1973 ixl_dmamem_free(sc, &sc->sc_scratch); 1974 free_hmc: 1975 ixl_hmc_free(sc); 1976 shutdown: 1977 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 1978 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 1979 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 1980 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 1981 1982 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 0); 1983 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 0); 1984 ixl_wr(sc, sc->sc_aq_regs->atq_len, 0); 1985 1986 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 0); 1987 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 0); 1988 ixl_wr(sc, sc->sc_aq_regs->arq_len, 0); 1989 1990 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 1991 0, IXL_DMA_LEN(&sc->sc_arq), 1992 BUS_DMASYNC_POSTREAD); 1993 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 1994 0, IXL_DMA_LEN(&sc->sc_atq), 1995 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1996 1997 ixl_arq_unfill(sc); 1998 1999 free_arq: 2000 ixl_dmamem_free(sc, &sc->sc_arq); 2001 free_atq: 2002 ixl_dmamem_free(sc, &sc->sc_atq); 2003 unmap: 2004 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 2005 sc->sc_mems = 0; 2006 2007 if (sc->sc_intrmap != NULL) 2008 intrmap_destroy(sc->sc_intrmap); 2009 } 2010 2011 static void 2012 ixl_media_add(struct ixl_softc *sc, uint64_t phy_types) 2013 { 2014 struct ifmedia *ifm = &sc->sc_media; 2015 const struct ixl_phy_type *itype; 2016 unsigned int i; 2017 2018 for (i = 0; i < nitems(ixl_phy_type_map); i++) { 2019 itype = &ixl_phy_type_map[i]; 2020 2021 if (ISSET(phy_types, itype->phy_type)) 2022 ifmedia_add(ifm, IFM_ETHER | itype->ifm_type, 0, NULL); 2023 } 2024 } 2025 2026 static int 2027 ixl_media_change(struct ifnet *ifp) 2028 { 2029 /* ignore? */ 2030 return (EOPNOTSUPP); 2031 } 2032 2033 static void 2034 ixl_media_status(struct ifnet *ifp, struct ifmediareq *ifm) 2035 { 2036 struct ixl_softc *sc = ifp->if_softc; 2037 2038 NET_ASSERT_LOCKED(); 2039 2040 ifm->ifm_status = sc->sc_media_status; 2041 ifm->ifm_active = sc->sc_media_active; 2042 } 2043 2044 static void 2045 ixl_watchdog(struct ifnet *ifp) 2046 { 2047 2048 } 2049 2050 int 2051 ixl_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2052 { 2053 struct ixl_softc *sc = (struct ixl_softc *)ifp->if_softc; 2054 struct ifreq *ifr = (struct ifreq *)data; 2055 uint8_t addrhi[ETHER_ADDR_LEN], addrlo[ETHER_ADDR_LEN]; 2056 int aqerror, error = 0; 2057 2058 switch (cmd) { 2059 case SIOCSIFADDR: 2060 ifp->if_flags |= IFF_UP; 2061 /* FALLTHROUGH */ 2062 2063 case SIOCSIFFLAGS: 2064 if (ISSET(ifp->if_flags, IFF_UP)) { 2065 if (ISSET(ifp->if_flags, IFF_RUNNING)) 2066 error = ENETRESET; 2067 else 2068 error = ixl_up(sc); 2069 } else { 2070 if (ISSET(ifp->if_flags, IFF_RUNNING)) 2071 error = ixl_down(sc); 2072 } 2073 break; 2074 2075 case SIOCGIFMEDIA: 2076 case SIOCSIFMEDIA: 2077 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 2078 break; 2079 2080 case SIOCGIFRXR: 2081 error = ixl_rxrinfo(sc, (struct if_rxrinfo *)ifr->ifr_data); 2082 break; 2083 2084 case SIOCADDMULTI: 2085 if (ether_addmulti(ifr, &sc->sc_ac) == ENETRESET) { 2086 error = ether_multiaddr(&ifr->ifr_addr, addrlo, addrhi); 2087 if (error != 0) 2088 return (error); 2089 2090 aqerror = ixl_add_macvlan(sc, addrlo, 0, 2091 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 2092 if (aqerror == IXL_AQ_RC_ENOSPC) { 2093 ether_delmulti(ifr, &sc->sc_ac); 2094 error = ENOSPC; 2095 } 2096 2097 if (sc->sc_ac.ac_multirangecnt > 0) { 2098 SET(ifp->if_flags, IFF_ALLMULTI); 2099 error = ENETRESET; 2100 } 2101 } 2102 break; 2103 2104 case SIOCDELMULTI: 2105 if (ether_delmulti(ifr, &sc->sc_ac) == ENETRESET) { 2106 error = ether_multiaddr(&ifr->ifr_addr, addrlo, addrhi); 2107 if (error != 0) 2108 return (error); 2109 2110 ixl_remove_macvlan(sc, addrlo, 0, 2111 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 2112 2113 if (ISSET(ifp->if_flags, IFF_ALLMULTI) && 2114 sc->sc_ac.ac_multirangecnt == 0) { 2115 CLR(ifp->if_flags, IFF_ALLMULTI); 2116 error = ENETRESET; 2117 } 2118 } 2119 break; 2120 2121 case SIOCGIFSFFPAGE: 2122 error = rw_enter(&ixl_sff_lock, RW_WRITE|RW_INTR); 2123 if (error != 0) 2124 break; 2125 2126 error = ixl_get_sffpage(sc, (struct if_sffpage *)data); 2127 rw_exit(&ixl_sff_lock); 2128 break; 2129 2130 default: 2131 error = ether_ioctl(ifp, &sc->sc_ac, cmd, data); 2132 break; 2133 } 2134 2135 if (error == ENETRESET) 2136 error = ixl_iff(sc); 2137 2138 return (error); 2139 } 2140 2141 static inline void * 2142 ixl_hmc_kva(struct ixl_softc *sc, unsigned int type, unsigned int i) 2143 { 2144 uint8_t *kva = IXL_DMA_KVA(&sc->sc_hmc_pd); 2145 struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type]; 2146 2147 if (i >= e->hmc_count) 2148 return (NULL); 2149 2150 kva += e->hmc_base; 2151 kva += i * e->hmc_size; 2152 2153 return (kva); 2154 } 2155 2156 static inline size_t 2157 ixl_hmc_len(struct ixl_softc *sc, unsigned int type) 2158 { 2159 struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type]; 2160 2161 return (e->hmc_size); 2162 } 2163 2164 static int 2165 ixl_configure_rss(struct ixl_softc *sc) 2166 { 2167 struct ixl_rss_key rsskey; 2168 struct ixl_rss_lut_128 lut; 2169 uint8_t *lute = (uint8_t *)&lut; 2170 uint64_t rss_hena; 2171 unsigned int i, nqueues; 2172 int error; 2173 2174 #if 0 2175 /* if we want to do a 512 entry LUT, do this. */ 2176 uint32_t v = ixl_rd_ctl(sc, I40E_PFQF_CTL_0); 2177 SET(v, I40E_PFQF_CTL_0_HASHLUTSIZE_MASK); 2178 ixl_wr_ctl(sc, I40E_PFQF_CTL_0, v); 2179 #endif 2180 2181 stoeplitz_to_key(&rsskey, sizeof(rsskey)); 2182 2183 nqueues = ixl_nqueues(sc); 2184 for (i = 0; i < sizeof(lut); i++) { 2185 /* 2186 * ixl must have a power of 2 rings, so using mod 2187 * to populate the table is fine. 2188 */ 2189 lute[i] = i % nqueues; 2190 } 2191 2192 error = ixl_set_rss_key(sc, &rsskey); 2193 if (error != 0) 2194 return (error); 2195 2196 rss_hena = (uint64_t)ixl_rd_ctl(sc, I40E_PFQF_HENA(0)); 2197 rss_hena |= (uint64_t)ixl_rd_ctl(sc, I40E_PFQF_HENA(1)) << 32; 2198 rss_hena |= ixl_rss_hena(sc); 2199 ixl_wr_ctl(sc, I40E_PFQF_HENA(0), rss_hena); 2200 ixl_wr_ctl(sc, I40E_PFQF_HENA(1), rss_hena >> 32); 2201 2202 error = ixl_set_rss_lut(sc, &lut); 2203 if (error != 0) 2204 return (error); 2205 2206 /* nothing to clena up :( */ 2207 2208 return (0); 2209 } 2210 2211 static int 2212 ixl_up(struct ixl_softc *sc) 2213 { 2214 struct ifnet *ifp = &sc->sc_ac.ac_if; 2215 struct ifqueue *ifq; 2216 struct ifiqueue *ifiq; 2217 struct ixl_vector *iv; 2218 struct ixl_rx_ring *rxr; 2219 struct ixl_tx_ring *txr; 2220 unsigned int nqueues, i; 2221 uint32_t reg; 2222 int rv = ENOMEM; 2223 2224 nqueues = ixl_nqueues(sc); 2225 2226 rw_enter_write(&sc->sc_cfg_lock); 2227 if (sc->sc_dead) { 2228 rw_exit_write(&sc->sc_cfg_lock); 2229 return (ENXIO); 2230 } 2231 2232 /* allocation is the only thing that can fail, so do it up front */ 2233 for (i = 0; i < nqueues; i++) { 2234 rxr = ixl_rxr_alloc(sc, i); 2235 if (rxr == NULL) 2236 goto free; 2237 2238 txr = ixl_txr_alloc(sc, i); 2239 if (txr == NULL) { 2240 ixl_rxr_free(sc, rxr); 2241 goto free; 2242 } 2243 2244 /* wire everything together */ 2245 iv = &sc->sc_vectors[i]; 2246 iv->iv_rxr = rxr; 2247 iv->iv_txr = txr; 2248 2249 ifq = ifp->if_ifqs[i]; 2250 ifq->ifq_softc = txr; 2251 txr->txr_ifq = ifq; 2252 2253 ifiq = ifp->if_iqs[i]; 2254 ifiq->ifiq_softc = rxr; 2255 rxr->rxr_ifiq = ifiq; 2256 } 2257 2258 /* XXX wait 50ms from completion of last RX queue disable */ 2259 2260 for (i = 0; i < nqueues; i++) { 2261 iv = &sc->sc_vectors[i]; 2262 rxr = iv->iv_rxr; 2263 txr = iv->iv_txr; 2264 2265 ixl_txr_qdis(sc, txr, 1); 2266 2267 ixl_rxr_config(sc, rxr); 2268 ixl_txr_config(sc, txr); 2269 2270 ixl_wr(sc, I40E_QTX_CTL(i), I40E_QTX_CTL_PF_QUEUE | 2271 (sc->sc_pf_id << I40E_QTX_CTL_PF_INDX_SHIFT)); 2272 2273 ixl_wr(sc, rxr->rxr_tail, 0); 2274 ixl_rxfill(sc, rxr); 2275 2276 reg = ixl_rd(sc, I40E_QRX_ENA(i)); 2277 SET(reg, I40E_QRX_ENA_QENA_REQ_MASK); 2278 ixl_wr(sc, I40E_QRX_ENA(i), reg); 2279 2280 reg = ixl_rd(sc, I40E_QTX_ENA(i)); 2281 SET(reg, I40E_QTX_ENA_QENA_REQ_MASK); 2282 ixl_wr(sc, I40E_QTX_ENA(i), reg); 2283 } 2284 2285 for (i = 0; i < nqueues; i++) { 2286 iv = &sc->sc_vectors[i]; 2287 rxr = iv->iv_rxr; 2288 txr = iv->iv_txr; 2289 2290 if (ixl_rxr_enabled(sc, rxr) != 0) 2291 goto down; 2292 2293 if (ixl_txr_enabled(sc, txr) != 0) 2294 goto down; 2295 } 2296 2297 ixl_configure_rss(sc); 2298 2299 SET(ifp->if_flags, IFF_RUNNING); 2300 2301 if (sc->sc_intrmap == NULL) { 2302 ixl_wr(sc, I40E_PFINT_LNKLST0, 2303 (I40E_INTR_NOTX_QUEUE << 2304 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 2305 (I40E_QUEUE_TYPE_RX << 2306 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 2307 2308 ixl_wr(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), 2309 (I40E_INTR_NOTX_INTR << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 2310 (I40E_ITR_INDEX_RX << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 2311 (I40E_INTR_NOTX_RX_QUEUE << 2312 I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) | 2313 (I40E_INTR_NOTX_QUEUE << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 2314 (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 2315 I40E_QINT_RQCTL_CAUSE_ENA_MASK); 2316 2317 ixl_wr(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), 2318 (I40E_INTR_NOTX_INTR << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 2319 (I40E_ITR_INDEX_TX << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 2320 (I40E_INTR_NOTX_TX_QUEUE << 2321 I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) | 2322 (I40E_QUEUE_TYPE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 2323 (I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) | 2324 I40E_QINT_TQCTL_CAUSE_ENA_MASK); 2325 } else { 2326 /* vector 0 has no queues */ 2327 ixl_wr(sc, I40E_PFINT_LNKLST0, 2328 I40E_QUEUE_TYPE_EOL << 2329 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT); 2330 2331 /* queue n is mapped to vector n+1 */ 2332 for (i = 0; i < nqueues; i++) { 2333 /* LNKLSTN(i) configures vector i+1 */ 2334 ixl_wr(sc, I40E_PFINT_LNKLSTN(i), 2335 (i << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) | 2336 (I40E_QUEUE_TYPE_RX << 2337 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 2338 ixl_wr(sc, I40E_QINT_RQCTL(i), 2339 ((i+1) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 2340 (I40E_ITR_INDEX_RX << 2341 I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 2342 (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 2343 (I40E_QUEUE_TYPE_TX << 2344 I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 2345 I40E_QINT_RQCTL_CAUSE_ENA_MASK); 2346 ixl_wr(sc, I40E_QINT_TQCTL(i), 2347 ((i+1) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 2348 (I40E_ITR_INDEX_TX << 2349 I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 2350 (I40E_QUEUE_TYPE_EOL << 2351 I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 2352 (I40E_QUEUE_TYPE_RX << 2353 I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) | 2354 I40E_QINT_TQCTL_CAUSE_ENA_MASK); 2355 2356 ixl_wr(sc, I40E_PFINT_ITRN(0, i), 0x7a); 2357 ixl_wr(sc, I40E_PFINT_ITRN(1, i), 0x7a); 2358 ixl_wr(sc, I40E_PFINT_ITRN(2, i), 0); 2359 } 2360 } 2361 2362 ixl_wr(sc, I40E_PFINT_ITR0(0), 0x7a); 2363 ixl_wr(sc, I40E_PFINT_ITR0(1), 0x7a); 2364 ixl_wr(sc, I40E_PFINT_ITR0(2), 0); 2365 2366 rw_exit_write(&sc->sc_cfg_lock); 2367 2368 return (ENETRESET); 2369 2370 free: 2371 for (i = 0; i < nqueues; i++) { 2372 iv = &sc->sc_vectors[i]; 2373 rxr = iv->iv_rxr; 2374 txr = iv->iv_txr; 2375 2376 if (rxr == NULL) { 2377 /* 2378 * tx and rx get set at the same time, so if one 2379 * is NULL, the other is too. 2380 */ 2381 continue; 2382 } 2383 2384 ixl_txr_free(sc, txr); 2385 ixl_rxr_free(sc, rxr); 2386 } 2387 rw_exit_write(&sc->sc_cfg_lock); 2388 return (rv); 2389 down: 2390 rw_exit_write(&sc->sc_cfg_lock); 2391 ixl_down(sc); 2392 return (ETIMEDOUT); 2393 } 2394 2395 static int 2396 ixl_iff(struct ixl_softc *sc) 2397 { 2398 struct ifnet *ifp = &sc->sc_ac.ac_if; 2399 struct ixl_atq iatq; 2400 struct ixl_aq_desc *iaq; 2401 struct ixl_aq_vsi_promisc_param *param; 2402 2403 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 2404 return (0); 2405 2406 memset(&iatq, 0, sizeof(iatq)); 2407 2408 iaq = &iatq.iatq_desc; 2409 iaq->iaq_opcode = htole16(IXL_AQ_OP_SET_VSI_PROMISC); 2410 2411 param = (struct ixl_aq_vsi_promisc_param *)&iaq->iaq_param; 2412 param->flags = htole16(IXL_AQ_VSI_PROMISC_FLAG_BCAST | 2413 IXL_AQ_VSI_PROMISC_FLAG_VLAN); 2414 if (ISSET(ifp->if_flags, IFF_PROMISC)) { 2415 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST | 2416 IXL_AQ_VSI_PROMISC_FLAG_MCAST); 2417 } else if (ISSET(ifp->if_flags, IFF_ALLMULTI)) { 2418 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_MCAST); 2419 } 2420 param->valid_flags = htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST | 2421 IXL_AQ_VSI_PROMISC_FLAG_MCAST | IXL_AQ_VSI_PROMISC_FLAG_BCAST | 2422 IXL_AQ_VSI_PROMISC_FLAG_VLAN); 2423 param->seid = sc->sc_seid; 2424 2425 ixl_atq_exec(sc, &iatq, "ixliff"); 2426 2427 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK)) 2428 return (EIO); 2429 2430 if (memcmp(sc->sc_enaddr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN) != 0) { 2431 ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 2432 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 2433 ixl_add_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 2434 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 2435 memcpy(sc->sc_enaddr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 2436 } 2437 return (0); 2438 } 2439 2440 static int 2441 ixl_down(struct ixl_softc *sc) 2442 { 2443 struct ifnet *ifp = &sc->sc_ac.ac_if; 2444 struct ixl_vector *iv; 2445 struct ixl_rx_ring *rxr; 2446 struct ixl_tx_ring *txr; 2447 unsigned int nqueues, i; 2448 uint32_t reg; 2449 int error = 0; 2450 2451 nqueues = ixl_nqueues(sc); 2452 2453 rw_enter_write(&sc->sc_cfg_lock); 2454 2455 CLR(ifp->if_flags, IFF_RUNNING); 2456 2457 NET_UNLOCK(); 2458 2459 /* mask interrupts */ 2460 reg = ixl_rd(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE)); 2461 CLR(reg, I40E_QINT_RQCTL_CAUSE_ENA_MASK); 2462 ixl_wr(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), reg); 2463 2464 reg = ixl_rd(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE)); 2465 CLR(reg, I40E_QINT_TQCTL_CAUSE_ENA_MASK); 2466 ixl_wr(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), reg); 2467 2468 ixl_wr(sc, I40E_PFINT_LNKLST0, I40E_QUEUE_TYPE_EOL); 2469 2470 /* make sure the no hw generated work is still in flight */ 2471 intr_barrier(sc->sc_ihc); 2472 if (sc->sc_intrmap != NULL) { 2473 for (i = 0; i < nqueues; i++) { 2474 iv = &sc->sc_vectors[i]; 2475 rxr = iv->iv_rxr; 2476 txr = iv->iv_txr; 2477 2478 ixl_txr_qdis(sc, txr, 0); 2479 2480 ifq_barrier(txr->txr_ifq); 2481 2482 timeout_del_barrier(&rxr->rxr_refill); 2483 2484 intr_barrier(iv->iv_ihc); 2485 } 2486 } 2487 2488 /* XXX wait at least 400 usec for all tx queues in one go */ 2489 delay(500); 2490 2491 for (i = 0; i < nqueues; i++) { 2492 reg = ixl_rd(sc, I40E_QTX_ENA(i)); 2493 CLR(reg, I40E_QTX_ENA_QENA_REQ_MASK); 2494 ixl_wr(sc, I40E_QTX_ENA(i), reg); 2495 2496 reg = ixl_rd(sc, I40E_QRX_ENA(i)); 2497 CLR(reg, I40E_QRX_ENA_QENA_REQ_MASK); 2498 ixl_wr(sc, I40E_QRX_ENA(i), reg); 2499 } 2500 2501 for (i = 0; i < nqueues; i++) { 2502 iv = &sc->sc_vectors[i]; 2503 rxr = iv->iv_rxr; 2504 txr = iv->iv_txr; 2505 2506 if (ixl_txr_disabled(sc, txr) != 0) 2507 goto die; 2508 2509 if (ixl_rxr_disabled(sc, rxr) != 0) 2510 goto die; 2511 } 2512 2513 for (i = 0; i < nqueues; i++) { 2514 iv = &sc->sc_vectors[i]; 2515 rxr = iv->iv_rxr; 2516 txr = iv->iv_txr; 2517 2518 ixl_txr_unconfig(sc, txr); 2519 ixl_rxr_unconfig(sc, rxr); 2520 2521 ixl_txr_clean(sc, txr); 2522 ixl_rxr_clean(sc, rxr); 2523 2524 ixl_txr_free(sc, txr); 2525 ixl_rxr_free(sc, rxr); 2526 2527 ifp->if_iqs[i]->ifiq_softc = NULL; 2528 ifp->if_ifqs[i]->ifq_softc = NULL; 2529 } 2530 2531 out: 2532 rw_exit_write(&sc->sc_cfg_lock); 2533 NET_LOCK(); 2534 return (error); 2535 die: 2536 sc->sc_dead = 1; 2537 log(LOG_CRIT, "%s: failed to shut down rings", DEVNAME(sc)); 2538 error = ETIMEDOUT; 2539 goto out; 2540 } 2541 2542 static struct ixl_tx_ring * 2543 ixl_txr_alloc(struct ixl_softc *sc, unsigned int qid) 2544 { 2545 struct ixl_tx_ring *txr; 2546 struct ixl_tx_map *maps, *txm; 2547 unsigned int i; 2548 2549 txr = malloc(sizeof(*txr), M_DEVBUF, M_WAITOK|M_CANFAIL); 2550 if (txr == NULL) 2551 return (NULL); 2552 2553 maps = mallocarray(sizeof(*maps), 2554 sc->sc_tx_ring_ndescs, M_DEVBUF, M_WAITOK|M_CANFAIL|M_ZERO); 2555 if (maps == NULL) 2556 goto free; 2557 2558 if (ixl_dmamem_alloc(sc, &txr->txr_mem, 2559 sizeof(struct ixl_tx_desc) * sc->sc_tx_ring_ndescs, 2560 IXL_TX_QUEUE_ALIGN) != 0) 2561 goto freemap; 2562 2563 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2564 txm = &maps[i]; 2565 2566 if (bus_dmamap_create(sc->sc_dmat, 2567 IXL_HARDMTU, IXL_TX_PKT_DESCS, IXL_HARDMTU, 0, 2568 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 2569 &txm->txm_map) != 0) 2570 goto uncreate; 2571 2572 txm->txm_eop = -1; 2573 txm->txm_m = NULL; 2574 } 2575 2576 txr->txr_cons = txr->txr_prod = 0; 2577 txr->txr_maps = maps; 2578 2579 txr->txr_tail = I40E_QTX_TAIL(qid); 2580 txr->txr_qid = qid; 2581 2582 return (txr); 2583 2584 uncreate: 2585 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2586 txm = &maps[i]; 2587 2588 if (txm->txm_map == NULL) 2589 continue; 2590 2591 bus_dmamap_destroy(sc->sc_dmat, txm->txm_map); 2592 } 2593 2594 ixl_dmamem_free(sc, &txr->txr_mem); 2595 freemap: 2596 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_tx_ring_ndescs); 2597 free: 2598 free(txr, M_DEVBUF, sizeof(*txr)); 2599 return (NULL); 2600 } 2601 2602 static void 2603 ixl_txr_qdis(struct ixl_softc *sc, struct ixl_tx_ring *txr, int enable) 2604 { 2605 unsigned int qid; 2606 bus_size_t reg; 2607 uint32_t r; 2608 2609 qid = txr->txr_qid + sc->sc_base_queue; 2610 reg = I40E_GLLAN_TXPRE_QDIS(qid / 128); 2611 qid %= 128; 2612 2613 r = ixl_rd(sc, reg); 2614 CLR(r, I40E_GLLAN_TXPRE_QDIS_QINDX_MASK); 2615 SET(r, qid << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 2616 SET(r, enable ? I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK : 2617 I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK); 2618 ixl_wr(sc, reg, r); 2619 } 2620 2621 static void 2622 ixl_txr_config(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2623 { 2624 struct ixl_hmc_txq txq; 2625 struct ixl_aq_vsi_data *data = IXL_DMA_KVA(&sc->sc_scratch); 2626 void *hmc; 2627 2628 memset(&txq, 0, sizeof(txq)); 2629 txq.head = htole16(0); 2630 txq.new_context = 1; 2631 htolem64(&txq.base, 2632 IXL_DMA_DVA(&txr->txr_mem) / IXL_HMC_TXQ_BASE_UNIT); 2633 txq.head_wb_ena = IXL_HMC_TXQ_DESC_WB; 2634 htolem16(&txq.qlen, sc->sc_tx_ring_ndescs); 2635 txq.tphrdesc_ena = 0; 2636 txq.tphrpacket_ena = 0; 2637 txq.tphwdesc_ena = 0; 2638 txq.rdylist = data->qs_handle[0]; 2639 2640 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid); 2641 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX)); 2642 ixl_hmc_pack(hmc, &txq, ixl_hmc_pack_txq, nitems(ixl_hmc_pack_txq)); 2643 } 2644 2645 static void 2646 ixl_txr_unconfig(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2647 { 2648 void *hmc; 2649 2650 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid); 2651 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX)); 2652 } 2653 2654 static void 2655 ixl_txr_clean(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2656 { 2657 struct ixl_tx_map *maps, *txm; 2658 bus_dmamap_t map; 2659 unsigned int i; 2660 2661 maps = txr->txr_maps; 2662 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2663 txm = &maps[i]; 2664 2665 if (txm->txm_m == NULL) 2666 continue; 2667 2668 map = txm->txm_map; 2669 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2670 BUS_DMASYNC_POSTWRITE); 2671 bus_dmamap_unload(sc->sc_dmat, map); 2672 2673 m_freem(txm->txm_m); 2674 txm->txm_m = NULL; 2675 } 2676 } 2677 2678 static int 2679 ixl_txr_enabled(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2680 { 2681 bus_size_t ena = I40E_QTX_ENA(txr->txr_qid); 2682 uint32_t reg; 2683 int i; 2684 2685 for (i = 0; i < 10; i++) { 2686 reg = ixl_rd(sc, ena); 2687 if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK)) 2688 return (0); 2689 2690 delaymsec(10); 2691 } 2692 2693 return (ETIMEDOUT); 2694 } 2695 2696 static int 2697 ixl_txr_disabled(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2698 { 2699 bus_size_t ena = I40E_QTX_ENA(txr->txr_qid); 2700 uint32_t reg; 2701 int i; 2702 2703 for (i = 0; i < 20; i++) { 2704 reg = ixl_rd(sc, ena); 2705 if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK) == 0) 2706 return (0); 2707 2708 delaymsec(10); 2709 } 2710 2711 return (ETIMEDOUT); 2712 } 2713 2714 static void 2715 ixl_txr_free(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2716 { 2717 struct ixl_tx_map *maps, *txm; 2718 unsigned int i; 2719 2720 maps = txr->txr_maps; 2721 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2722 txm = &maps[i]; 2723 2724 bus_dmamap_destroy(sc->sc_dmat, txm->txm_map); 2725 } 2726 2727 ixl_dmamem_free(sc, &txr->txr_mem); 2728 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_tx_ring_ndescs); 2729 free(txr, M_DEVBUF, sizeof(*txr)); 2730 } 2731 2732 static inline int 2733 ixl_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, struct mbuf *m) 2734 { 2735 int error; 2736 2737 error = bus_dmamap_load_mbuf(dmat, map, m, 2738 BUS_DMA_STREAMING | BUS_DMA_NOWAIT); 2739 if (error != EFBIG) 2740 return (error); 2741 2742 error = m_defrag(m, M_DONTWAIT); 2743 if (error != 0) 2744 return (error); 2745 2746 return (bus_dmamap_load_mbuf(dmat, map, m, 2747 BUS_DMA_STREAMING | BUS_DMA_NOWAIT)); 2748 } 2749 2750 static void 2751 ixl_start(struct ifqueue *ifq) 2752 { 2753 struct ifnet *ifp = ifq->ifq_if; 2754 struct ixl_softc *sc = ifp->if_softc; 2755 struct ixl_tx_ring *txr = ifq->ifq_softc; 2756 struct ixl_tx_desc *ring, *txd; 2757 struct ixl_tx_map *txm; 2758 bus_dmamap_t map; 2759 struct mbuf *m; 2760 uint64_t cmd; 2761 unsigned int prod, free, last, i; 2762 unsigned int mask; 2763 int post = 0; 2764 #if NBPFILTER > 0 2765 caddr_t if_bpf; 2766 #endif 2767 2768 if (!LINK_STATE_IS_UP(ifp->if_link_state)) { 2769 ifq_purge(ifq); 2770 return; 2771 } 2772 2773 prod = txr->txr_prod; 2774 free = txr->txr_cons; 2775 if (free <= prod) 2776 free += sc->sc_tx_ring_ndescs; 2777 free -= prod; 2778 2779 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2780 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTWRITE); 2781 2782 ring = IXL_DMA_KVA(&txr->txr_mem); 2783 mask = sc->sc_tx_ring_ndescs - 1; 2784 2785 for (;;) { 2786 if (free <= IXL_TX_PKT_DESCS) { 2787 ifq_set_oactive(ifq); 2788 break; 2789 } 2790 2791 m = ifq_dequeue(ifq); 2792 if (m == NULL) 2793 break; 2794 2795 txm = &txr->txr_maps[prod]; 2796 map = txm->txm_map; 2797 2798 if (ixl_load_mbuf(sc->sc_dmat, map, m) != 0) { 2799 ifq->ifq_errors++; 2800 m_freem(m); 2801 continue; 2802 } 2803 2804 bus_dmamap_sync(sc->sc_dmat, map, 0, 2805 map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2806 2807 for (i = 0; i < map->dm_nsegs; i++) { 2808 txd = &ring[prod]; 2809 2810 cmd = (uint64_t)map->dm_segs[i].ds_len << 2811 IXL_TX_DESC_BSIZE_SHIFT; 2812 cmd |= IXL_TX_DESC_DTYPE_DATA | IXL_TX_DESC_CMD_ICRC; 2813 2814 htolem64(&txd->addr, map->dm_segs[i].ds_addr); 2815 htolem64(&txd->cmd, cmd); 2816 2817 last = prod; 2818 2819 prod++; 2820 prod &= mask; 2821 } 2822 cmd |= IXL_TX_DESC_CMD_EOP | IXL_TX_DESC_CMD_RS; 2823 htolem64(&txd->cmd, cmd); 2824 2825 txm->txm_m = m; 2826 txm->txm_eop = last; 2827 2828 #if NBPFILTER > 0 2829 if_bpf = ifp->if_bpf; 2830 if (if_bpf) 2831 bpf_mtap_ether(if_bpf, m, BPF_DIRECTION_OUT); 2832 #endif 2833 2834 free -= i; 2835 post = 1; 2836 } 2837 2838 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2839 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREWRITE); 2840 2841 if (post) { 2842 txr->txr_prod = prod; 2843 ixl_wr(sc, txr->txr_tail, prod); 2844 } 2845 } 2846 2847 static int 2848 ixl_txeof(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2849 { 2850 struct ifqueue *ifq = txr->txr_ifq; 2851 struct ixl_tx_desc *ring, *txd; 2852 struct ixl_tx_map *txm; 2853 bus_dmamap_t map; 2854 unsigned int cons, prod, last; 2855 unsigned int mask; 2856 uint64_t dtype; 2857 int done = 0; 2858 2859 prod = txr->txr_prod; 2860 cons = txr->txr_cons; 2861 2862 if (cons == prod) 2863 return (0); 2864 2865 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2866 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTREAD); 2867 2868 ring = IXL_DMA_KVA(&txr->txr_mem); 2869 mask = sc->sc_tx_ring_ndescs - 1; 2870 2871 do { 2872 txm = &txr->txr_maps[cons]; 2873 last = txm->txm_eop; 2874 txd = &ring[last]; 2875 2876 dtype = txd->cmd & htole64(IXL_TX_DESC_DTYPE_MASK); 2877 if (dtype != htole64(IXL_TX_DESC_DTYPE_DONE)) 2878 break; 2879 2880 map = txm->txm_map; 2881 2882 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2883 BUS_DMASYNC_POSTWRITE); 2884 bus_dmamap_unload(sc->sc_dmat, map); 2885 m_freem(txm->txm_m); 2886 2887 txm->txm_m = NULL; 2888 txm->txm_eop = -1; 2889 2890 cons = last + 1; 2891 cons &= mask; 2892 2893 done = 1; 2894 } while (cons != prod); 2895 2896 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2897 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREREAD); 2898 2899 txr->txr_cons = cons; 2900 2901 //ixl_enable(sc, txr->txr_msix); 2902 2903 if (ifq_is_oactive(ifq)) 2904 ifq_restart(ifq); 2905 2906 return (done); 2907 } 2908 2909 static struct ixl_rx_ring * 2910 ixl_rxr_alloc(struct ixl_softc *sc, unsigned int qid) 2911 { 2912 struct ixl_rx_ring *rxr; 2913 struct ixl_rx_map *maps, *rxm; 2914 unsigned int i; 2915 2916 rxr = malloc(sizeof(*rxr), M_DEVBUF, M_WAITOK|M_CANFAIL); 2917 if (rxr == NULL) 2918 return (NULL); 2919 2920 maps = mallocarray(sizeof(*maps), 2921 sc->sc_rx_ring_ndescs, M_DEVBUF, M_WAITOK|M_CANFAIL|M_ZERO); 2922 if (maps == NULL) 2923 goto free; 2924 2925 if (ixl_dmamem_alloc(sc, &rxr->rxr_mem, 2926 sizeof(struct ixl_rx_rd_desc_16) * sc->sc_rx_ring_ndescs, 2927 IXL_RX_QUEUE_ALIGN) != 0) 2928 goto freemap; 2929 2930 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2931 rxm = &maps[i]; 2932 2933 if (bus_dmamap_create(sc->sc_dmat, 2934 IXL_HARDMTU, 1, IXL_HARDMTU, 0, 2935 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 2936 &rxm->rxm_map) != 0) 2937 goto uncreate; 2938 2939 rxm->rxm_m = NULL; 2940 } 2941 2942 rxr->rxr_sc = sc; 2943 if_rxr_init(&rxr->rxr_acct, 17, sc->sc_rx_ring_ndescs - 1); 2944 timeout_set(&rxr->rxr_refill, ixl_rxrefill, rxr); 2945 rxr->rxr_cons = rxr->rxr_prod = 0; 2946 rxr->rxr_m_head = NULL; 2947 rxr->rxr_m_tail = &rxr->rxr_m_head; 2948 rxr->rxr_maps = maps; 2949 2950 rxr->rxr_tail = I40E_QRX_TAIL(qid); 2951 rxr->rxr_qid = qid; 2952 2953 return (rxr); 2954 2955 uncreate: 2956 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2957 rxm = &maps[i]; 2958 2959 if (rxm->rxm_map == NULL) 2960 continue; 2961 2962 bus_dmamap_destroy(sc->sc_dmat, rxm->rxm_map); 2963 } 2964 2965 ixl_dmamem_free(sc, &rxr->rxr_mem); 2966 freemap: 2967 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_rx_ring_ndescs); 2968 free: 2969 free(rxr, M_DEVBUF, sizeof(*rxr)); 2970 return (NULL); 2971 } 2972 2973 static void 2974 ixl_rxr_clean(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 2975 { 2976 struct ixl_rx_map *maps, *rxm; 2977 bus_dmamap_t map; 2978 unsigned int i; 2979 2980 timeout_del_barrier(&rxr->rxr_refill); 2981 2982 maps = rxr->rxr_maps; 2983 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2984 rxm = &maps[i]; 2985 2986 if (rxm->rxm_m == NULL) 2987 continue; 2988 2989 map = rxm->rxm_map; 2990 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2991 BUS_DMASYNC_POSTWRITE); 2992 bus_dmamap_unload(sc->sc_dmat, map); 2993 2994 m_freem(rxm->rxm_m); 2995 rxm->rxm_m = NULL; 2996 } 2997 2998 m_freem(rxr->rxr_m_head); 2999 rxr->rxr_m_head = NULL; 3000 rxr->rxr_m_tail = &rxr->rxr_m_head; 3001 3002 rxr->rxr_prod = rxr->rxr_cons = 0; 3003 } 3004 3005 static int 3006 ixl_rxr_enabled(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3007 { 3008 bus_size_t ena = I40E_QRX_ENA(rxr->rxr_qid); 3009 uint32_t reg; 3010 int i; 3011 3012 for (i = 0; i < 10; i++) { 3013 reg = ixl_rd(sc, ena); 3014 if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK)) 3015 return (0); 3016 3017 delaymsec(10); 3018 } 3019 3020 return (ETIMEDOUT); 3021 } 3022 3023 static int 3024 ixl_rxr_disabled(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3025 { 3026 bus_size_t ena = I40E_QRX_ENA(rxr->rxr_qid); 3027 uint32_t reg; 3028 int i; 3029 3030 for (i = 0; i < 20; i++) { 3031 reg = ixl_rd(sc, ena); 3032 if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK) == 0) 3033 return (0); 3034 3035 delaymsec(10); 3036 } 3037 3038 return (ETIMEDOUT); 3039 } 3040 3041 static void 3042 ixl_rxr_config(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3043 { 3044 struct ixl_hmc_rxq rxq; 3045 void *hmc; 3046 3047 memset(&rxq, 0, sizeof(rxq)); 3048 3049 rxq.head = htole16(0); 3050 htolem64(&rxq.base, 3051 IXL_DMA_DVA(&rxr->rxr_mem) / IXL_HMC_RXQ_BASE_UNIT); 3052 htolem16(&rxq.qlen, sc->sc_rx_ring_ndescs); 3053 rxq.dbuff = htole16(MCLBYTES / IXL_HMC_RXQ_DBUFF_UNIT); 3054 rxq.hbuff = 0; 3055 rxq.dtype = IXL_HMC_RXQ_DTYPE_NOSPLIT; 3056 rxq.dsize = IXL_HMC_RXQ_DSIZE_16; 3057 rxq.crcstrip = 1; 3058 rxq.l2sel = 0; 3059 rxq.showiv = 0; 3060 rxq.rxmax = htole16(IXL_HARDMTU); 3061 rxq.tphrdesc_ena = 0; 3062 rxq.tphwdesc_ena = 0; 3063 rxq.tphdata_ena = 0; 3064 rxq.tphhead_ena = 0; 3065 rxq.lrxqthresh = 0; 3066 rxq.prefena = 1; 3067 3068 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_RX, rxr->rxr_qid); 3069 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_RX)); 3070 ixl_hmc_pack(hmc, &rxq, ixl_hmc_pack_rxq, nitems(ixl_hmc_pack_rxq)); 3071 } 3072 3073 static void 3074 ixl_rxr_unconfig(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3075 { 3076 void *hmc; 3077 3078 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_RX, rxr->rxr_qid); 3079 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_RX)); 3080 } 3081 3082 static void 3083 ixl_rxr_free(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3084 { 3085 struct ixl_rx_map *maps, *rxm; 3086 unsigned int i; 3087 3088 maps = rxr->rxr_maps; 3089 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3090 rxm = &maps[i]; 3091 3092 bus_dmamap_destroy(sc->sc_dmat, rxm->rxm_map); 3093 } 3094 3095 ixl_dmamem_free(sc, &rxr->rxr_mem); 3096 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_rx_ring_ndescs); 3097 free(rxr, M_DEVBUF, sizeof(*rxr)); 3098 } 3099 3100 static int 3101 ixl_rxeof(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3102 { 3103 struct ifiqueue *ifiq = rxr->rxr_ifiq; 3104 struct ifnet *ifp = &sc->sc_ac.ac_if; 3105 struct ixl_rx_wb_desc_16 *ring, *rxd; 3106 struct ixl_rx_map *rxm; 3107 bus_dmamap_t map; 3108 unsigned int cons, prod; 3109 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 3110 struct mbuf *m; 3111 uint64_t word; 3112 unsigned int len; 3113 unsigned int mask; 3114 int done = 0; 3115 3116 prod = rxr->rxr_prod; 3117 cons = rxr->rxr_cons; 3118 3119 if (cons == prod) 3120 return (0); 3121 3122 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 3123 0, IXL_DMA_LEN(&rxr->rxr_mem), 3124 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3125 3126 ring = IXL_DMA_KVA(&rxr->rxr_mem); 3127 mask = sc->sc_rx_ring_ndescs - 1; 3128 3129 do { 3130 rxd = &ring[cons]; 3131 3132 word = lemtoh64(&rxd->qword1); 3133 if (!ISSET(word, IXL_RX_DESC_DD)) 3134 break; 3135 3136 if_rxr_put(&rxr->rxr_acct, 1); 3137 3138 rxm = &rxr->rxr_maps[cons]; 3139 3140 map = rxm->rxm_map; 3141 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3142 BUS_DMASYNC_POSTREAD); 3143 bus_dmamap_unload(sc->sc_dmat, map); 3144 3145 m = rxm->rxm_m; 3146 rxm->rxm_m = NULL; 3147 3148 len = (word & IXL_RX_DESC_PLEN_MASK) >> IXL_RX_DESC_PLEN_SHIFT; 3149 m->m_len = len; 3150 m->m_pkthdr.len = 0; 3151 3152 m->m_next = NULL; 3153 *rxr->rxr_m_tail = m; 3154 rxr->rxr_m_tail = &m->m_next; 3155 3156 m = rxr->rxr_m_head; 3157 m->m_pkthdr.len += len; 3158 3159 if (ISSET(word, IXL_RX_DESC_EOP)) { 3160 if (!ISSET(word, 3161 IXL_RX_DESC_RXE | IXL_RX_DESC_OVERSIZE)) { 3162 ml_enqueue(&ml, m); 3163 } else { 3164 ifp->if_ierrors++; /* XXX */ 3165 m_freem(m); 3166 } 3167 3168 rxr->rxr_m_head = NULL; 3169 rxr->rxr_m_tail = &rxr->rxr_m_head; 3170 } 3171 3172 cons++; 3173 cons &= mask; 3174 3175 done = 1; 3176 } while (cons != prod); 3177 3178 if (done) { 3179 rxr->rxr_cons = cons; 3180 if (ifiq_input(ifiq, &ml)) 3181 if_rxr_livelocked(&rxr->rxr_acct); 3182 ixl_rxfill(sc, rxr); 3183 } 3184 3185 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 3186 0, IXL_DMA_LEN(&rxr->rxr_mem), 3187 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3188 3189 return (done); 3190 } 3191 3192 static void 3193 ixl_rxfill(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3194 { 3195 struct ixl_rx_rd_desc_16 *ring, *rxd; 3196 struct ixl_rx_map *rxm; 3197 bus_dmamap_t map; 3198 struct mbuf *m; 3199 unsigned int prod; 3200 unsigned int slots; 3201 unsigned int mask; 3202 int post = 0; 3203 3204 slots = if_rxr_get(&rxr->rxr_acct, sc->sc_rx_ring_ndescs); 3205 if (slots == 0) 3206 return; 3207 3208 prod = rxr->rxr_prod; 3209 3210 ring = IXL_DMA_KVA(&rxr->rxr_mem); 3211 mask = sc->sc_rx_ring_ndescs - 1; 3212 3213 do { 3214 rxm = &rxr->rxr_maps[prod]; 3215 3216 m = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES + ETHER_ALIGN); 3217 if (m == NULL) 3218 break; 3219 m->m_data += (m->m_ext.ext_size - (MCLBYTES + ETHER_ALIGN)); 3220 m->m_len = m->m_pkthdr.len = MCLBYTES + ETHER_ALIGN; 3221 3222 map = rxm->rxm_map; 3223 3224 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 3225 BUS_DMA_NOWAIT) != 0) { 3226 m_freem(m); 3227 break; 3228 } 3229 3230 rxm->rxm_m = m; 3231 3232 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3233 BUS_DMASYNC_PREREAD); 3234 3235 rxd = &ring[prod]; 3236 3237 htolem64(&rxd->paddr, map->dm_segs[0].ds_addr); 3238 rxd->haddr = htole64(0); 3239 3240 prod++; 3241 prod &= mask; 3242 3243 post = 1; 3244 } while (--slots); 3245 3246 if_rxr_put(&rxr->rxr_acct, slots); 3247 3248 if (if_rxr_inuse(&rxr->rxr_acct) == 0) 3249 timeout_add(&rxr->rxr_refill, 1); 3250 else if (post) { 3251 rxr->rxr_prod = prod; 3252 ixl_wr(sc, rxr->rxr_tail, prod); 3253 } 3254 } 3255 3256 void 3257 ixl_rxrefill(void *arg) 3258 { 3259 struct ixl_rx_ring *rxr = arg; 3260 struct ixl_softc *sc = rxr->rxr_sc; 3261 3262 ixl_rxfill(sc, rxr); 3263 } 3264 3265 static int 3266 ixl_rxrinfo(struct ixl_softc *sc, struct if_rxrinfo *ifri) 3267 { 3268 struct ifnet *ifp = &sc->sc_ac.ac_if; 3269 struct if_rxring_info *ifr; 3270 struct ixl_rx_ring *ring; 3271 int i, rv; 3272 3273 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 3274 return (ENOTTY); 3275 3276 ifr = mallocarray(sizeof(*ifr), ixl_nqueues(sc), M_TEMP, 3277 M_WAITOK|M_CANFAIL|M_ZERO); 3278 if (ifr == NULL) 3279 return (ENOMEM); 3280 3281 for (i = 0; i < ixl_nqueues(sc); i++) { 3282 ring = ifp->if_iqs[i]->ifiq_softc; 3283 ifr[i].ifr_size = MCLBYTES; 3284 ifr[i].ifr_info = ring->rxr_acct; 3285 } 3286 3287 rv = if_rxr_info_ioctl(ifri, ixl_nqueues(sc), ifr); 3288 free(ifr, M_TEMP, ixl_nqueues(sc) * sizeof(*ifr)); 3289 3290 return (rv); 3291 } 3292 3293 static int 3294 ixl_intr0(void *xsc) 3295 { 3296 struct ixl_softc *sc = xsc; 3297 struct ifnet *ifp = &sc->sc_ac.ac_if; 3298 uint32_t icr; 3299 int rv = 0; 3300 3301 ixl_intr_enable(sc); 3302 icr = ixl_rd(sc, I40E_PFINT_ICR0); 3303 3304 if (ISSET(icr, I40E_PFINT_ICR0_ADMINQ_MASK)) { 3305 ixl_atq_done(sc); 3306 task_add(systq, &sc->sc_arq_task); 3307 rv = 1; 3308 } 3309 3310 if (ISSET(icr, I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK)) { 3311 task_add(systq, &sc->sc_link_state_task); 3312 rv = 1; 3313 } 3314 3315 if (ISSET(ifp->if_flags, IFF_RUNNING)) { 3316 struct ixl_vector *iv = sc->sc_vectors; 3317 if (ISSET(icr, I40E_INTR_NOTX_RX_MASK)) 3318 rv |= ixl_rxeof(sc, iv->iv_rxr); 3319 if (ISSET(icr, I40E_INTR_NOTX_TX_MASK)) 3320 rv |= ixl_txeof(sc, iv->iv_txr); 3321 } 3322 3323 return (rv); 3324 } 3325 3326 static int 3327 ixl_intr_vector(void *v) 3328 { 3329 struct ixl_vector *iv = v; 3330 struct ixl_softc *sc = iv->iv_sc; 3331 struct ifnet *ifp = &sc->sc_ac.ac_if; 3332 int rv = 0; 3333 3334 if (ISSET(ifp->if_flags, IFF_RUNNING)) { 3335 rv |= ixl_rxeof(sc, iv->iv_rxr); 3336 rv |= ixl_txeof(sc, iv->iv_txr); 3337 } 3338 3339 ixl_wr(sc, I40E_PFINT_DYN_CTLN(iv->iv_qid), 3340 I40E_PFINT_DYN_CTLN_INTENA_MASK | 3341 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 3342 (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)); 3343 3344 return (rv); 3345 } 3346 3347 static void 3348 ixl_link_state_update_iaq(struct ixl_softc *sc, void *arg) 3349 { 3350 struct ifnet *ifp = &sc->sc_ac.ac_if; 3351 struct ixl_aq_desc *iaq = arg; 3352 uint16_t retval; 3353 int link_state; 3354 int change = 0; 3355 3356 retval = lemtoh16(&iaq->iaq_retval); 3357 if (retval != IXL_AQ_RC_OK) { 3358 printf("%s: LINK STATUS error %u\n", DEVNAME(sc), retval); 3359 return; 3360 } 3361 3362 link_state = ixl_set_link_status(sc, iaq); 3363 mtx_enter(&sc->sc_link_state_mtx); 3364 if (ifp->if_link_state != link_state) { 3365 ifp->if_link_state = link_state; 3366 change = 1; 3367 } 3368 mtx_leave(&sc->sc_link_state_mtx); 3369 3370 if (change) 3371 if_link_state_change(ifp); 3372 } 3373 3374 static void 3375 ixl_link_state_update(void *xsc) 3376 { 3377 struct ixl_softc *sc = xsc; 3378 struct ixl_aq_desc *iaq; 3379 struct ixl_aq_link_param *param; 3380 3381 memset(&sc->sc_link_state_atq, 0, sizeof(sc->sc_link_state_atq)); 3382 iaq = &sc->sc_link_state_atq.iatq_desc; 3383 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS); 3384 param = (struct ixl_aq_link_param *)iaq->iaq_param; 3385 param->notify = IXL_AQ_LINK_NOTIFY; 3386 3387 ixl_atq_set(&sc->sc_link_state_atq, ixl_link_state_update_iaq, iaq); 3388 ixl_atq_post(sc, &sc->sc_link_state_atq); 3389 } 3390 3391 #if 0 3392 static void 3393 ixl_aq_dump(const struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 3394 { 3395 printf("%s: flags %b opcode %04x\n", DEVNAME(sc), 3396 lemtoh16(&iaq->iaq_flags), IXL_AQ_FLAGS_FMT, 3397 lemtoh16(&iaq->iaq_opcode)); 3398 printf("%s: datalen %u retval %u\n", DEVNAME(sc), 3399 lemtoh16(&iaq->iaq_datalen), lemtoh16(&iaq->iaq_retval)); 3400 printf("%s: cookie %016llx\n", DEVNAME(sc), iaq->iaq_cookie); 3401 printf("%s: %08x %08x %08x %08x\n", DEVNAME(sc), 3402 lemtoh32(&iaq->iaq_param[0]), lemtoh32(&iaq->iaq_param[1]), 3403 lemtoh32(&iaq->iaq_param[2]), lemtoh32(&iaq->iaq_param[3])); 3404 } 3405 #endif 3406 3407 static void 3408 ixl_arq(void *xsc) 3409 { 3410 struct ixl_softc *sc = xsc; 3411 struct ixl_aq_desc *arq, *iaq; 3412 struct ixl_aq_buf *aqb; 3413 unsigned int cons = sc->sc_arq_cons; 3414 unsigned int prod; 3415 int done = 0; 3416 3417 prod = ixl_rd(sc, sc->sc_aq_regs->arq_head) & 3418 sc->sc_aq_regs->arq_head_mask; 3419 3420 if (cons == prod) 3421 goto done; 3422 3423 arq = IXL_DMA_KVA(&sc->sc_arq); 3424 3425 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3426 0, IXL_DMA_LEN(&sc->sc_arq), 3427 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3428 3429 do { 3430 iaq = &arq[cons]; 3431 3432 aqb = SIMPLEQ_FIRST(&sc->sc_arq_live); 3433 SIMPLEQ_REMOVE_HEAD(&sc->sc_arq_live, aqb_entry); 3434 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IXL_AQ_BUFLEN, 3435 BUS_DMASYNC_POSTREAD); 3436 3437 switch (iaq->iaq_opcode) { 3438 case HTOLE16(IXL_AQ_OP_PHY_LINK_STATUS): 3439 ixl_link_state_update_iaq(sc, iaq); 3440 break; 3441 } 3442 3443 memset(iaq, 0, sizeof(*iaq)); 3444 SIMPLEQ_INSERT_TAIL(&sc->sc_arq_idle, aqb, aqb_entry); 3445 if_rxr_put(&sc->sc_arq_ring, 1); 3446 3447 cons++; 3448 cons &= IXL_AQ_MASK; 3449 3450 done = 1; 3451 } while (cons != prod); 3452 3453 if (done && ixl_arq_fill(sc)) 3454 ixl_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 3455 3456 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3457 0, IXL_DMA_LEN(&sc->sc_arq), 3458 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3459 3460 sc->sc_arq_cons = cons; 3461 3462 done: 3463 ixl_intr_enable(sc); 3464 } 3465 3466 static void 3467 ixl_atq_set(struct ixl_atq *iatq, 3468 void (*fn)(struct ixl_softc *, void *), void *arg) 3469 { 3470 iatq->iatq_fn = fn; 3471 iatq->iatq_arg = arg; 3472 } 3473 3474 static void 3475 ixl_atq_post(struct ixl_softc *sc, struct ixl_atq *iatq) 3476 { 3477 struct ixl_aq_desc *atq, *slot; 3478 unsigned int prod; 3479 3480 /* assert locked */ 3481 3482 atq = IXL_DMA_KVA(&sc->sc_atq); 3483 prod = sc->sc_atq_prod; 3484 slot = atq + prod; 3485 3486 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3487 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 3488 3489 *slot = iatq->iatq_desc; 3490 slot->iaq_cookie = (uint64_t)iatq; 3491 3492 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3493 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 3494 3495 prod++; 3496 prod &= IXL_AQ_MASK; 3497 sc->sc_atq_prod = prod; 3498 ixl_wr(sc, sc->sc_aq_regs->atq_tail, prod); 3499 } 3500 3501 static void 3502 ixl_atq_done(struct ixl_softc *sc) 3503 { 3504 struct ixl_aq_desc *atq, *slot; 3505 struct ixl_atq *iatq; 3506 unsigned int cons; 3507 unsigned int prod; 3508 3509 prod = sc->sc_atq_prod; 3510 cons = sc->sc_atq_cons; 3511 3512 if (prod == cons) 3513 return; 3514 3515 atq = IXL_DMA_KVA(&sc->sc_atq); 3516 3517 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3518 0, IXL_DMA_LEN(&sc->sc_atq), 3519 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3520 3521 do { 3522 slot = &atq[cons]; 3523 if (!ISSET(slot->iaq_flags, htole16(IXL_AQ_DD))) 3524 break; 3525 3526 iatq = (struct ixl_atq *)slot->iaq_cookie; 3527 iatq->iatq_desc = *slot; 3528 3529 memset(slot, 0, sizeof(*slot)); 3530 3531 (*iatq->iatq_fn)(sc, iatq->iatq_arg); 3532 3533 cons++; 3534 cons &= IXL_AQ_MASK; 3535 } while (cons != prod); 3536 3537 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3538 0, IXL_DMA_LEN(&sc->sc_atq), 3539 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3540 3541 sc->sc_atq_cons = cons; 3542 } 3543 3544 static void 3545 ixl_wakeup(struct ixl_softc *sc, void *arg) 3546 { 3547 struct cond *c = arg; 3548 3549 cond_signal(c); 3550 } 3551 3552 static void 3553 ixl_atq_exec(struct ixl_softc *sc, struct ixl_atq *iatq, const char *wmesg) 3554 { 3555 struct cond c = COND_INITIALIZER(); 3556 3557 KASSERT(iatq->iatq_desc.iaq_cookie == 0); 3558 3559 ixl_atq_set(iatq, ixl_wakeup, &c); 3560 ixl_atq_post(sc, iatq); 3561 3562 cond_wait(&c, wmesg); 3563 } 3564 3565 static int 3566 ixl_atq_poll(struct ixl_softc *sc, struct ixl_aq_desc *iaq, unsigned int tm) 3567 { 3568 struct ixl_aq_desc *atq, *slot; 3569 unsigned int prod; 3570 unsigned int t = 0; 3571 3572 atq = IXL_DMA_KVA(&sc->sc_atq); 3573 prod = sc->sc_atq_prod; 3574 slot = atq + prod; 3575 3576 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3577 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 3578 3579 *slot = *iaq; 3580 slot->iaq_flags |= htole16(IXL_AQ_SI); 3581 3582 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3583 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 3584 3585 prod++; 3586 prod &= IXL_AQ_MASK; 3587 sc->sc_atq_prod = prod; 3588 ixl_wr(sc, sc->sc_aq_regs->atq_tail, prod); 3589 3590 while (ixl_rd(sc, sc->sc_aq_regs->atq_head) != prod) { 3591 delaymsec(1); 3592 3593 if (t++ > tm) 3594 return (ETIMEDOUT); 3595 } 3596 3597 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3598 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTREAD); 3599 *iaq = *slot; 3600 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3601 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREREAD); 3602 3603 sc->sc_atq_cons = prod; 3604 3605 return (0); 3606 } 3607 3608 static int 3609 ixl_get_version(struct ixl_softc *sc) 3610 { 3611 struct ixl_aq_desc iaq; 3612 uint32_t fwbuild, fwver, apiver; 3613 3614 memset(&iaq, 0, sizeof(iaq)); 3615 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VERSION); 3616 3617 if (ixl_atq_poll(sc, &iaq, 2000) != 0) 3618 return (ETIMEDOUT); 3619 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) 3620 return (EIO); 3621 3622 fwbuild = lemtoh32(&iaq.iaq_param[1]); 3623 fwver = lemtoh32(&iaq.iaq_param[2]); 3624 apiver = lemtoh32(&iaq.iaq_param[3]); 3625 3626 printf(", FW %hu.%hu.%05u API %hu.%hu", (uint16_t)fwver, 3627 (uint16_t)(fwver >> 16), fwbuild, (uint16_t)apiver, 3628 (uint16_t)(apiver >> 16)); 3629 3630 return (0); 3631 } 3632 3633 static int 3634 ixl_pxe_clear(struct ixl_softc *sc) 3635 { 3636 struct ixl_aq_desc iaq; 3637 3638 memset(&iaq, 0, sizeof(iaq)); 3639 iaq.iaq_opcode = htole16(IXL_AQ_OP_CLEAR_PXE_MODE); 3640 iaq.iaq_param[0] = htole32(0x2); 3641 3642 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 3643 printf(", CLEAR PXE MODE timeout\n"); 3644 return (-1); 3645 } 3646 3647 switch (iaq.iaq_retval) { 3648 case HTOLE16(IXL_AQ_RC_OK): 3649 case HTOLE16(IXL_AQ_RC_EEXIST): 3650 break; 3651 default: 3652 printf(", CLEAR PXE MODE error\n"); 3653 return (-1); 3654 } 3655 3656 return (0); 3657 } 3658 3659 static int 3660 ixl_lldp_shut(struct ixl_softc *sc) 3661 { 3662 struct ixl_aq_desc iaq; 3663 3664 memset(&iaq, 0, sizeof(iaq)); 3665 iaq.iaq_opcode = htole16(IXL_AQ_OP_LLDP_STOP_AGENT); 3666 iaq.iaq_param[0] = htole32(IXL_LLDP_SHUTDOWN); 3667 3668 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 3669 printf(", STOP LLDP AGENT timeout\n"); 3670 return (-1); 3671 } 3672 3673 switch (iaq.iaq_retval) { 3674 case HTOLE16(IXL_AQ_RC_EMODE): 3675 case HTOLE16(IXL_AQ_RC_EPERM): 3676 /* ignore silently */ 3677 default: 3678 break; 3679 } 3680 3681 return (0); 3682 } 3683 3684 static int 3685 ixl_get_mac(struct ixl_softc *sc) 3686 { 3687 struct ixl_dmamem idm; 3688 struct ixl_aq_desc iaq; 3689 struct ixl_aq_mac_addresses *addrs; 3690 int rv; 3691 3692 #ifdef __sparc64__ 3693 if (OF_getprop(PCITAG_NODE(sc->sc_tag), "local-mac-address", 3694 sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN) == ETHER_ADDR_LEN) 3695 return (0); 3696 #endif 3697 3698 if (ixl_dmamem_alloc(sc, &idm, sizeof(*addrs), 0) != 0) { 3699 printf(", unable to allocate mac addresses\n"); 3700 return (-1); 3701 } 3702 3703 memset(&iaq, 0, sizeof(iaq)); 3704 iaq.iaq_flags = htole16(IXL_AQ_BUF); 3705 iaq.iaq_opcode = htole16(IXL_AQ_OP_MAC_ADDRESS_READ); 3706 iaq.iaq_datalen = htole16(sizeof(*addrs)); 3707 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 3708 3709 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3710 BUS_DMASYNC_PREREAD); 3711 3712 rv = ixl_atq_poll(sc, &iaq, 250); 3713 3714 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3715 BUS_DMASYNC_POSTREAD); 3716 3717 if (rv != 0) { 3718 printf(", MAC ADDRESS READ timeout\n"); 3719 rv = -1; 3720 goto done; 3721 } 3722 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 3723 printf(", MAC ADDRESS READ error\n"); 3724 rv = -1; 3725 goto done; 3726 } 3727 3728 addrs = IXL_DMA_KVA(&idm); 3729 if (!ISSET(iaq.iaq_param[0], htole32(IXL_AQ_MAC_PORT_VALID))) { 3730 printf(", port address is not valid\n"); 3731 goto done; 3732 } 3733 3734 memcpy(sc->sc_ac.ac_enaddr, addrs->port, ETHER_ADDR_LEN); 3735 rv = 0; 3736 3737 done: 3738 ixl_dmamem_free(sc, &idm); 3739 return (rv); 3740 } 3741 3742 static int 3743 ixl_get_switch_config(struct ixl_softc *sc) 3744 { 3745 struct ixl_dmamem idm; 3746 struct ixl_aq_desc iaq; 3747 struct ixl_aq_switch_config *hdr; 3748 struct ixl_aq_switch_config_element *elms, *elm; 3749 unsigned int nelm; 3750 int rv; 3751 3752 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) { 3753 printf("%s: unable to allocate switch config buffer\n", 3754 DEVNAME(sc)); 3755 return (-1); 3756 } 3757 3758 memset(&iaq, 0, sizeof(iaq)); 3759 iaq.iaq_flags = htole16(IXL_AQ_BUF | 3760 (IXL_AQ_BUFLEN > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 3761 iaq.iaq_opcode = htole16(IXL_AQ_OP_SWITCH_GET_CONFIG); 3762 iaq.iaq_datalen = htole16(IXL_AQ_BUFLEN); 3763 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 3764 3765 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3766 BUS_DMASYNC_PREREAD); 3767 3768 rv = ixl_atq_poll(sc, &iaq, 250); 3769 3770 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3771 BUS_DMASYNC_POSTREAD); 3772 3773 if (rv != 0) { 3774 printf("%s: GET SWITCH CONFIG timeout\n", DEVNAME(sc)); 3775 rv = -1; 3776 goto done; 3777 } 3778 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 3779 printf("%s: GET SWITCH CONFIG error\n", DEVNAME(sc)); 3780 rv = -1; 3781 goto done; 3782 } 3783 3784 hdr = IXL_DMA_KVA(&idm); 3785 elms = (struct ixl_aq_switch_config_element *)(hdr + 1); 3786 3787 nelm = lemtoh16(&hdr->num_reported); 3788 if (nelm < 1) { 3789 printf("%s: no switch config available\n", DEVNAME(sc)); 3790 rv = -1; 3791 goto done; 3792 } 3793 3794 #if 0 3795 for (i = 0; i < nelm; i++) { 3796 elm = &elms[i]; 3797 3798 printf("%s: type %x revision %u seid %04x\n", DEVNAME(sc), 3799 elm->type, elm->revision, lemtoh16(&elm->seid)); 3800 printf("%s: uplink %04x downlink %04x\n", DEVNAME(sc), 3801 lemtoh16(&elm->uplink_seid), 3802 lemtoh16(&elm->downlink_seid)); 3803 printf("%s: conntype %x scheduler %04x extra %04x\n", 3804 DEVNAME(sc), elm->connection_type, 3805 lemtoh16(&elm->scheduler_id), 3806 lemtoh16(&elm->element_info)); 3807 } 3808 #endif 3809 3810 elm = &elms[0]; 3811 3812 sc->sc_uplink_seid = elm->uplink_seid; 3813 sc->sc_downlink_seid = elm->downlink_seid; 3814 sc->sc_seid = elm->seid; 3815 3816 if ((sc->sc_uplink_seid == htole16(0)) != 3817 (sc->sc_downlink_seid == htole16(0))) { 3818 printf("%s: SEIDs are misconfigured\n", DEVNAME(sc)); 3819 rv = -1; 3820 goto done; 3821 } 3822 3823 done: 3824 ixl_dmamem_free(sc, &idm); 3825 return (rv); 3826 } 3827 3828 static int 3829 ixl_phy_mask_ints(struct ixl_softc *sc) 3830 { 3831 struct ixl_aq_desc iaq; 3832 3833 memset(&iaq, 0, sizeof(iaq)); 3834 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_EVENT_MASK); 3835 iaq.iaq_param[2] = htole32(IXL_AQ_PHY_EV_MASK & 3836 ~(IXL_AQ_PHY_EV_LINK_UPDOWN | IXL_AQ_PHY_EV_MODULE_QUAL_FAIL | 3837 IXL_AQ_PHY_EV_MEDIA_NA)); 3838 3839 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 3840 printf("%s: SET PHY EVENT MASK timeout\n", DEVNAME(sc)); 3841 return (-1); 3842 } 3843 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 3844 printf("%s: SET PHY EVENT MASK error\n", DEVNAME(sc)); 3845 return (-1); 3846 } 3847 3848 return (0); 3849 } 3850 3851 static int 3852 ixl_get_phy_abilities(struct ixl_softc *sc,struct ixl_dmamem *idm) 3853 { 3854 struct ixl_aq_desc iaq; 3855 int rv; 3856 3857 memset(&iaq, 0, sizeof(iaq)); 3858 iaq.iaq_flags = htole16(IXL_AQ_BUF | 3859 (IXL_DMA_LEN(idm) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 3860 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_GET_ABILITIES); 3861 htolem16(&iaq.iaq_datalen, IXL_DMA_LEN(idm)); 3862 iaq.iaq_param[0] = htole32(IXL_AQ_PHY_REPORT_INIT); 3863 ixl_aq_dva(&iaq, IXL_DMA_DVA(idm)); 3864 3865 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 3866 BUS_DMASYNC_PREREAD); 3867 3868 rv = ixl_atq_poll(sc, &iaq, 250); 3869 3870 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 3871 BUS_DMASYNC_POSTREAD); 3872 3873 if (rv != 0) 3874 return (-1); 3875 3876 return (lemtoh16(&iaq.iaq_retval)); 3877 } 3878 3879 static int 3880 ixl_get_phy_types(struct ixl_softc *sc, uint64_t *phy_types_ptr) 3881 { 3882 struct ixl_dmamem idm; 3883 struct ixl_aq_phy_abilities *phy; 3884 uint64_t phy_types; 3885 int rv; 3886 3887 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) { 3888 printf("%s: unable to allocate phy abilities buffer\n", 3889 DEVNAME(sc)); 3890 return (-1); 3891 } 3892 3893 rv = ixl_get_phy_abilities(sc, &idm); 3894 switch (rv) { 3895 case -1: 3896 printf("%s: GET PHY ABILITIES timeout\n", DEVNAME(sc)); 3897 goto err; 3898 case IXL_AQ_RC_OK: 3899 break; 3900 case IXL_AQ_RC_EIO: 3901 /* API is too old to handle this command */ 3902 phy_types = 0; 3903 goto done; 3904 default: 3905 printf("%s: GET PHY ABILITIIES error %u\n", DEVNAME(sc), rv); 3906 goto err; 3907 } 3908 3909 phy = IXL_DMA_KVA(&idm); 3910 3911 phy_types = lemtoh32(&phy->phy_type); 3912 phy_types |= (uint64_t)phy->phy_type_ext << 32; 3913 3914 done: 3915 *phy_types_ptr = phy_types; 3916 3917 rv = 0; 3918 3919 err: 3920 ixl_dmamem_free(sc, &idm); 3921 return (rv); 3922 } 3923 3924 /* 3925 * this returns -2 on software/driver failure, -1 for problems 3926 * talking to the hardware, or the sff module type. 3927 */ 3928 3929 static int 3930 ixl_get_module_type(struct ixl_softc *sc) 3931 { 3932 struct ixl_dmamem idm; 3933 struct ixl_aq_phy_abilities *phy; 3934 int rv; 3935 3936 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) 3937 return (-2); 3938 3939 rv = ixl_get_phy_abilities(sc, &idm); 3940 if (rv != IXL_AQ_RC_OK) { 3941 rv = -1; 3942 goto done; 3943 } 3944 3945 phy = IXL_DMA_KVA(&idm); 3946 3947 rv = phy->module_type[0]; 3948 3949 done: 3950 ixl_dmamem_free(sc, &idm); 3951 return (rv); 3952 } 3953 3954 static int 3955 ixl_get_link_status(struct ixl_softc *sc) 3956 { 3957 struct ixl_aq_desc iaq; 3958 struct ixl_aq_link_param *param; 3959 3960 memset(&iaq, 0, sizeof(iaq)); 3961 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS); 3962 param = (struct ixl_aq_link_param *)iaq.iaq_param; 3963 param->notify = IXL_AQ_LINK_NOTIFY; 3964 3965 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 3966 printf("%s: GET LINK STATUS timeout\n", DEVNAME(sc)); 3967 return (-1); 3968 } 3969 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 3970 printf("%s: GET LINK STATUS error\n", DEVNAME(sc)); 3971 return (0); 3972 } 3973 3974 sc->sc_ac.ac_if.if_link_state = ixl_set_link_status(sc, &iaq); 3975 3976 return (0); 3977 } 3978 3979 struct ixl_sff_ops { 3980 int (*open)(struct ixl_softc *sc, struct if_sffpage *, uint8_t *); 3981 int (*get)(struct ixl_softc *sc, struct if_sffpage *, size_t); 3982 int (*close)(struct ixl_softc *sc, struct if_sffpage *, uint8_t); 3983 }; 3984 3985 static int 3986 ixl_sfp_open(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t *page) 3987 { 3988 int error; 3989 3990 if (sff->sff_addr != IFSFF_ADDR_EEPROM) 3991 return (0); 3992 3993 error = ixl_sff_get_byte(sc, IFSFF_ADDR_EEPROM, 127, page); 3994 if (error != 0) 3995 return (error); 3996 if (*page == sff->sff_page) 3997 return (0); 3998 error = ixl_sff_set_byte(sc, IFSFF_ADDR_EEPROM, 127, sff->sff_page); 3999 if (error != 0) 4000 return (error); 4001 4002 return (0); 4003 } 4004 4005 static int 4006 ixl_sfp_get(struct ixl_softc *sc, struct if_sffpage *sff, size_t i) 4007 { 4008 return (ixl_sff_get_byte(sc, sff->sff_addr, i, &sff->sff_data[i])); 4009 } 4010 4011 static int 4012 ixl_sfp_close(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t page) 4013 { 4014 int error; 4015 4016 if (sff->sff_addr != IFSFF_ADDR_EEPROM) 4017 return (0); 4018 4019 if (page == sff->sff_page) 4020 return (0); 4021 4022 error = ixl_sff_set_byte(sc, IFSFF_ADDR_EEPROM, 127, page); 4023 if (error != 0) 4024 return (error); 4025 4026 return (0); 4027 } 4028 4029 static const struct ixl_sff_ops ixl_sfp_ops = { 4030 ixl_sfp_open, 4031 ixl_sfp_get, 4032 ixl_sfp_close, 4033 }; 4034 4035 static int 4036 ixl_qsfp_open(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t *page) 4037 { 4038 if (sff->sff_addr != IFSFF_ADDR_EEPROM) 4039 return (EIO); 4040 4041 return (0); 4042 } 4043 4044 static int 4045 ixl_qsfp_get(struct ixl_softc *sc, struct if_sffpage *sff, size_t i) 4046 { 4047 return (ixl_sff_get_byte(sc, sff->sff_page, i, &sff->sff_data[i])); 4048 } 4049 4050 static int 4051 ixl_qsfp_close(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t page) 4052 { 4053 return (0); 4054 } 4055 4056 static const struct ixl_sff_ops ixl_qsfp_ops = { 4057 ixl_qsfp_open, 4058 ixl_qsfp_get, 4059 ixl_qsfp_close, 4060 }; 4061 4062 static int 4063 ixl_get_sffpage(struct ixl_softc *sc, struct if_sffpage *sff) 4064 { 4065 const struct ixl_sff_ops *ops; 4066 uint8_t page; 4067 size_t i; 4068 int error; 4069 4070 switch (ixl_get_module_type(sc)) { 4071 case -2: 4072 return (ENOMEM); 4073 case -1: 4074 return (ENXIO); 4075 case IXL_SFF8024_ID_SFP: 4076 ops = &ixl_sfp_ops; 4077 break; 4078 case IXL_SFF8024_ID_QSFP: 4079 case IXL_SFF8024_ID_QSFP_PLUS: 4080 case IXL_SFF8024_ID_QSFP28: 4081 ops = &ixl_qsfp_ops; 4082 break; 4083 default: 4084 return (EOPNOTSUPP); 4085 } 4086 4087 error = (*ops->open)(sc, sff, &page); 4088 if (error != 0) 4089 return (error); 4090 4091 for (i = 0; i < sizeof(sff->sff_data); i++) { 4092 error = (*ops->get)(sc, sff, i); 4093 if (error != 0) 4094 return (error); 4095 } 4096 4097 error = (*ops->close)(sc, sff, page); 4098 4099 return (0); 4100 } 4101 4102 static int 4103 ixl_sff_get_byte(struct ixl_softc *sc, uint8_t dev, uint32_t reg, uint8_t *p) 4104 { 4105 struct ixl_atq iatq; 4106 struct ixl_aq_desc *iaq; 4107 struct ixl_aq_phy_reg_access *param; 4108 4109 memset(&iatq, 0, sizeof(iatq)); 4110 iaq = &iatq.iatq_desc; 4111 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_GET_REGISTER); 4112 param = (struct ixl_aq_phy_reg_access *)iaq->iaq_param; 4113 param->phy_iface = IXL_AQ_PHY_IF_MODULE; 4114 param->dev_addr = dev; 4115 htolem32(¶m->reg, reg); 4116 4117 ixl_atq_exec(sc, &iatq, "ixlsffget"); 4118 4119 if (ISSET(sc->sc_ac.ac_if.if_flags, IFF_DEBUG)) { 4120 printf("%s: %s(dev 0x%02x, reg 0x%02x) -> %04x\n", 4121 DEVNAME(sc), __func__, 4122 dev, reg, lemtoh16(&iaq->iaq_retval)); 4123 } 4124 4125 switch (iaq->iaq_retval) { 4126 case htole16(IXL_AQ_RC_OK): 4127 break; 4128 case htole16(IXL_AQ_RC_EBUSY): 4129 return (EBUSY); 4130 case htole16(IXL_AQ_RC_ESRCH): 4131 return (ENODEV); 4132 case htole16(IXL_AQ_RC_EIO): 4133 case htole16(IXL_AQ_RC_EINVAL): 4134 default: 4135 return (EIO); 4136 } 4137 4138 *p = lemtoh32(¶m->val); 4139 4140 return (0); 4141 } 4142 4143 static int 4144 ixl_sff_set_byte(struct ixl_softc *sc, uint8_t dev, uint32_t reg, uint8_t v) 4145 { 4146 struct ixl_atq iatq; 4147 struct ixl_aq_desc *iaq; 4148 struct ixl_aq_phy_reg_access *param; 4149 4150 memset(&iatq, 0, sizeof(iatq)); 4151 iaq = &iatq.iatq_desc; 4152 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_REGISTER); 4153 param = (struct ixl_aq_phy_reg_access *)iaq->iaq_param; 4154 param->phy_iface = IXL_AQ_PHY_IF_MODULE; 4155 param->dev_addr = dev; 4156 htolem32(¶m->reg, reg); 4157 htolem32(¶m->val, v); 4158 4159 ixl_atq_exec(sc, &iatq, "ixlsffset"); 4160 4161 if (ISSET(sc->sc_ac.ac_if.if_flags, IFF_DEBUG)) { 4162 printf("%s: %s(dev 0x%02x, reg 0x%02x, val 0x%02x) -> %04x\n", 4163 DEVNAME(sc), __func__, 4164 dev, reg, v, lemtoh16(&iaq->iaq_retval)); 4165 } 4166 4167 switch (iaq->iaq_retval) { 4168 case htole16(IXL_AQ_RC_OK): 4169 break; 4170 case htole16(IXL_AQ_RC_EBUSY): 4171 return (EBUSY); 4172 case htole16(IXL_AQ_RC_ESRCH): 4173 return (ENODEV); 4174 case htole16(IXL_AQ_RC_EIO): 4175 case htole16(IXL_AQ_RC_EINVAL): 4176 default: 4177 return (EIO); 4178 } 4179 4180 return (0); 4181 } 4182 4183 static int 4184 ixl_get_vsi(struct ixl_softc *sc) 4185 { 4186 struct ixl_dmamem *vsi = &sc->sc_scratch; 4187 struct ixl_aq_desc iaq; 4188 struct ixl_aq_vsi_param *param; 4189 struct ixl_aq_vsi_reply *reply; 4190 int rv; 4191 4192 /* grumble, vsi info isn't "known" at compile time */ 4193 4194 memset(&iaq, 0, sizeof(iaq)); 4195 htolem16(&iaq.iaq_flags, IXL_AQ_BUF | 4196 (IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4197 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VSI_PARAMS); 4198 htolem16(&iaq.iaq_datalen, IXL_DMA_LEN(vsi)); 4199 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi)); 4200 4201 param = (struct ixl_aq_vsi_param *)iaq.iaq_param; 4202 param->uplink_seid = sc->sc_seid; 4203 4204 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4205 BUS_DMASYNC_PREREAD); 4206 4207 rv = ixl_atq_poll(sc, &iaq, 250); 4208 4209 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4210 BUS_DMASYNC_POSTREAD); 4211 4212 if (rv != 0) { 4213 printf("%s: GET VSI timeout\n", DEVNAME(sc)); 4214 return (-1); 4215 } 4216 4217 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4218 printf("%s: GET VSI error %u\n", DEVNAME(sc), 4219 lemtoh16(&iaq.iaq_retval)); 4220 return (-1); 4221 } 4222 4223 reply = (struct ixl_aq_vsi_reply *)iaq.iaq_param; 4224 sc->sc_vsi_number = reply->vsi_number; 4225 4226 return (0); 4227 } 4228 4229 static int 4230 ixl_set_vsi(struct ixl_softc *sc) 4231 { 4232 struct ixl_dmamem *vsi = &sc->sc_scratch; 4233 struct ixl_aq_desc iaq; 4234 struct ixl_aq_vsi_param *param; 4235 struct ixl_aq_vsi_data *data = IXL_DMA_KVA(vsi); 4236 int rv; 4237 4238 data->valid_sections = htole16(IXL_AQ_VSI_VALID_QUEUE_MAP | 4239 IXL_AQ_VSI_VALID_VLAN); 4240 4241 CLR(data->mapping_flags, htole16(IXL_AQ_VSI_QUE_MAP_MASK)); 4242 SET(data->mapping_flags, htole16(IXL_AQ_VSI_QUE_MAP_CONTIG)); 4243 data->queue_mapping[0] = htole16(0); 4244 data->tc_mapping[0] = htole16((0 << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) | 4245 (sc->sc_nqueues << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT)); 4246 4247 CLR(data->port_vlan_flags, 4248 htole16(IXL_AQ_VSI_PVLAN_MODE_MASK | IXL_AQ_VSI_PVLAN_EMOD_MASK)); 4249 SET(data->port_vlan_flags, 4250 htole16(IXL_AQ_VSI_PVLAN_MODE_ALL | IXL_AQ_VSI_PVLAN_EMOD_NOTHING)); 4251 4252 /* grumble, vsi info isn't "known" at compile time */ 4253 4254 memset(&iaq, 0, sizeof(iaq)); 4255 htolem16(&iaq.iaq_flags, IXL_AQ_BUF | IXL_AQ_RD | 4256 (IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4257 iaq.iaq_opcode = htole16(IXL_AQ_OP_UPD_VSI_PARAMS); 4258 htolem16(&iaq.iaq_datalen, IXL_DMA_LEN(vsi)); 4259 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi)); 4260 4261 param = (struct ixl_aq_vsi_param *)iaq.iaq_param; 4262 param->uplink_seid = sc->sc_seid; 4263 4264 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4265 BUS_DMASYNC_PREWRITE); 4266 4267 rv = ixl_atq_poll(sc, &iaq, 250); 4268 4269 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4270 BUS_DMASYNC_POSTWRITE); 4271 4272 if (rv != 0) { 4273 printf("%s: UPDATE VSI timeout\n", DEVNAME(sc)); 4274 return (-1); 4275 } 4276 4277 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4278 printf("%s: UPDATE VSI error %u\n", DEVNAME(sc), 4279 lemtoh16(&iaq.iaq_retval)); 4280 return (-1); 4281 } 4282 4283 return (0); 4284 } 4285 4286 static const struct ixl_phy_type * 4287 ixl_search_phy_type(uint8_t phy_type) 4288 { 4289 const struct ixl_phy_type *itype; 4290 uint64_t mask; 4291 unsigned int i; 4292 4293 if (phy_type >= 64) 4294 return (NULL); 4295 4296 mask = 1ULL << phy_type; 4297 4298 for (i = 0; i < nitems(ixl_phy_type_map); i++) { 4299 itype = &ixl_phy_type_map[i]; 4300 4301 if (ISSET(itype->phy_type, mask)) 4302 return (itype); 4303 } 4304 4305 return (NULL); 4306 } 4307 4308 static uint64_t 4309 ixl_search_link_speed(uint8_t link_speed) 4310 { 4311 const struct ixl_speed_type *type; 4312 unsigned int i; 4313 4314 for (i = 0; i < nitems(ixl_speed_type_map); i++) { 4315 type = &ixl_speed_type_map[i]; 4316 4317 if (ISSET(type->dev_speed, link_speed)) 4318 return (type->net_speed); 4319 } 4320 4321 return (0); 4322 } 4323 4324 static int 4325 ixl_set_link_status(struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 4326 { 4327 const struct ixl_aq_link_status *status; 4328 const struct ixl_phy_type *itype; 4329 4330 uint64_t ifm_active = IFM_ETHER; 4331 uint64_t ifm_status = IFM_AVALID; 4332 int link_state = LINK_STATE_DOWN; 4333 uint64_t baudrate = 0; 4334 4335 status = (const struct ixl_aq_link_status *)iaq->iaq_param; 4336 if (!ISSET(status->link_info, IXL_AQ_LINK_UP_FUNCTION)) 4337 goto done; 4338 4339 ifm_active |= IFM_FDX; 4340 ifm_status |= IFM_ACTIVE; 4341 link_state = LINK_STATE_FULL_DUPLEX; 4342 4343 itype = ixl_search_phy_type(status->phy_type); 4344 if (itype != NULL) 4345 ifm_active |= itype->ifm_type; 4346 4347 if (ISSET(status->an_info, IXL_AQ_LINK_PAUSE_TX)) 4348 ifm_active |= IFM_ETH_TXPAUSE; 4349 if (ISSET(status->an_info, IXL_AQ_LINK_PAUSE_RX)) 4350 ifm_active |= IFM_ETH_RXPAUSE; 4351 4352 baudrate = ixl_search_link_speed(status->link_speed); 4353 4354 done: 4355 /* NET_ASSERT_LOCKED() except during attach */ 4356 sc->sc_media_active = ifm_active; 4357 sc->sc_media_status = ifm_status; 4358 sc->sc_ac.ac_if.if_baudrate = baudrate; 4359 4360 return (link_state); 4361 } 4362 4363 static int 4364 ixl_restart_an(struct ixl_softc *sc) 4365 { 4366 struct ixl_aq_desc iaq; 4367 4368 memset(&iaq, 0, sizeof(iaq)); 4369 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_RESTART_AN); 4370 iaq.iaq_param[0] = 4371 htole32(IXL_AQ_PHY_RESTART_AN | IXL_AQ_PHY_LINK_ENABLE); 4372 4373 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4374 printf("%s: RESTART AN timeout\n", DEVNAME(sc)); 4375 return (-1); 4376 } 4377 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4378 printf("%s: RESTART AN error\n", DEVNAME(sc)); 4379 return (-1); 4380 } 4381 4382 return (0); 4383 } 4384 4385 static int 4386 ixl_add_macvlan(struct ixl_softc *sc, uint8_t *macaddr, uint16_t vlan, uint16_t flags) 4387 { 4388 struct ixl_aq_desc iaq; 4389 struct ixl_aq_add_macvlan *param; 4390 struct ixl_aq_add_macvlan_elem *elem; 4391 4392 memset(&iaq, 0, sizeof(iaq)); 4393 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4394 iaq.iaq_opcode = htole16(IXL_AQ_OP_ADD_MACVLAN); 4395 iaq.iaq_datalen = htole16(sizeof(*elem)); 4396 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch)); 4397 4398 param = (struct ixl_aq_add_macvlan *)&iaq.iaq_param; 4399 param->num_addrs = htole16(1); 4400 param->seid0 = htole16(0x8000) | sc->sc_seid; 4401 param->seid1 = 0; 4402 param->seid2 = 0; 4403 4404 elem = IXL_DMA_KVA(&sc->sc_scratch); 4405 memset(elem, 0, sizeof(*elem)); 4406 memcpy(elem->macaddr, macaddr, ETHER_ADDR_LEN); 4407 elem->flags = htole16(IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH | flags); 4408 elem->vlan = htole16(vlan); 4409 4410 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4411 printf("%s: ADD_MACVLAN timeout\n", DEVNAME(sc)); 4412 return (IXL_AQ_RC_EINVAL); 4413 } 4414 4415 return letoh16(iaq.iaq_retval); 4416 } 4417 4418 static int 4419 ixl_remove_macvlan(struct ixl_softc *sc, uint8_t *macaddr, uint16_t vlan, uint16_t flags) 4420 { 4421 struct ixl_aq_desc iaq; 4422 struct ixl_aq_remove_macvlan *param; 4423 struct ixl_aq_remove_macvlan_elem *elem; 4424 4425 memset(&iaq, 0, sizeof(iaq)); 4426 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4427 iaq.iaq_opcode = htole16(IXL_AQ_OP_REMOVE_MACVLAN); 4428 iaq.iaq_datalen = htole16(sizeof(*elem)); 4429 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch)); 4430 4431 param = (struct ixl_aq_remove_macvlan *)&iaq.iaq_param; 4432 param->num_addrs = htole16(1); 4433 param->seid0 = htole16(0x8000) | sc->sc_seid; 4434 param->seid1 = 0; 4435 param->seid2 = 0; 4436 4437 elem = IXL_DMA_KVA(&sc->sc_scratch); 4438 memset(elem, 0, sizeof(*elem)); 4439 memcpy(elem->macaddr, macaddr, ETHER_ADDR_LEN); 4440 elem->flags = htole16(IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH | flags); 4441 elem->vlan = htole16(vlan); 4442 4443 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4444 printf("%s: REMOVE_MACVLAN timeout\n", DEVNAME(sc)); 4445 return (IXL_AQ_RC_EINVAL); 4446 } 4447 4448 return letoh16(iaq.iaq_retval); 4449 } 4450 4451 static int 4452 ixl_hmc(struct ixl_softc *sc) 4453 { 4454 struct { 4455 uint32_t count; 4456 uint32_t minsize; 4457 bus_size_t maxcnt; 4458 bus_size_t setoff; 4459 bus_size_t setcnt; 4460 } regs[] = { 4461 { 4462 0, 4463 IXL_HMC_TXQ_MINSIZE, 4464 I40E_GLHMC_LANTXOBJSZ, 4465 I40E_GLHMC_LANTXBASE(sc->sc_pf_id), 4466 I40E_GLHMC_LANTXCNT(sc->sc_pf_id), 4467 }, 4468 { 4469 0, 4470 IXL_HMC_RXQ_MINSIZE, 4471 I40E_GLHMC_LANRXOBJSZ, 4472 I40E_GLHMC_LANRXBASE(sc->sc_pf_id), 4473 I40E_GLHMC_LANRXCNT(sc->sc_pf_id), 4474 }, 4475 { 4476 0, 4477 0, 4478 I40E_GLHMC_FCOEMAX, 4479 I40E_GLHMC_FCOEDDPBASE(sc->sc_pf_id), 4480 I40E_GLHMC_FCOEDDPCNT(sc->sc_pf_id), 4481 }, 4482 { 4483 0, 4484 0, 4485 I40E_GLHMC_FCOEFMAX, 4486 I40E_GLHMC_FCOEFBASE(sc->sc_pf_id), 4487 I40E_GLHMC_FCOEFCNT(sc->sc_pf_id), 4488 }, 4489 }; 4490 struct ixl_hmc_entry *e; 4491 uint64_t size, dva; 4492 uint8_t *kva; 4493 uint64_t *sdpage; 4494 unsigned int i; 4495 int npages, tables; 4496 4497 CTASSERT(nitems(regs) <= nitems(sc->sc_hmc_entries)); 4498 4499 regs[IXL_HMC_LAN_TX].count = regs[IXL_HMC_LAN_RX].count = 4500 ixl_rd(sc, I40E_GLHMC_LANQMAX); 4501 4502 size = 0; 4503 for (i = 0; i < nitems(regs); i++) { 4504 e = &sc->sc_hmc_entries[i]; 4505 4506 e->hmc_count = regs[i].count; 4507 e->hmc_size = 1U << ixl_rd(sc, regs[i].maxcnt); 4508 e->hmc_base = size; 4509 4510 if ((e->hmc_size * 8) < regs[i].minsize) { 4511 printf("%s: kernel hmc entry is too big\n", 4512 DEVNAME(sc)); 4513 return (-1); 4514 } 4515 4516 size += roundup(e->hmc_size * e->hmc_count, IXL_HMC_ROUNDUP); 4517 } 4518 size = roundup(size, IXL_HMC_PGSIZE); 4519 npages = size / IXL_HMC_PGSIZE; 4520 4521 tables = roundup(size, IXL_HMC_L2SZ) / IXL_HMC_L2SZ; 4522 4523 if (ixl_dmamem_alloc(sc, &sc->sc_hmc_pd, size, IXL_HMC_PGSIZE) != 0) { 4524 printf("%s: unable to allocate hmc pd memory\n", DEVNAME(sc)); 4525 return (-1); 4526 } 4527 4528 if (ixl_dmamem_alloc(sc, &sc->sc_hmc_sd, tables * IXL_HMC_PGSIZE, 4529 IXL_HMC_PGSIZE) != 0) { 4530 printf("%s: unable to allocate hmc sd memory\n", DEVNAME(sc)); 4531 ixl_dmamem_free(sc, &sc->sc_hmc_pd); 4532 return (-1); 4533 } 4534 4535 kva = IXL_DMA_KVA(&sc->sc_hmc_pd); 4536 memset(kva, 0, IXL_DMA_LEN(&sc->sc_hmc_pd)); 4537 4538 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 4539 0, IXL_DMA_LEN(&sc->sc_hmc_pd), 4540 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4541 4542 dva = IXL_DMA_DVA(&sc->sc_hmc_pd); 4543 sdpage = IXL_DMA_KVA(&sc->sc_hmc_sd); 4544 for (i = 0; i < npages; i++) { 4545 htolem64(sdpage++, dva | IXL_HMC_PDVALID); 4546 4547 dva += IXL_HMC_PGSIZE; 4548 } 4549 4550 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_sd), 4551 0, IXL_DMA_LEN(&sc->sc_hmc_sd), 4552 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4553 4554 dva = IXL_DMA_DVA(&sc->sc_hmc_sd); 4555 for (i = 0; i < tables; i++) { 4556 uint32_t count; 4557 4558 KASSERT(npages >= 0); 4559 4560 count = (npages > IXL_HMC_PGS) ? IXL_HMC_PGS : npages; 4561 4562 ixl_wr(sc, I40E_PFHMC_SDDATAHIGH, dva >> 32); 4563 ixl_wr(sc, I40E_PFHMC_SDDATALOW, dva | 4564 (count << I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | 4565 (1U << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT)); 4566 ixl_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 4567 ixl_wr(sc, I40E_PFHMC_SDCMD, 4568 (1U << I40E_PFHMC_SDCMD_PMSDWR_SHIFT) | i); 4569 4570 npages -= IXL_HMC_PGS; 4571 dva += IXL_HMC_PGSIZE; 4572 } 4573 4574 for (i = 0; i < nitems(regs); i++) { 4575 e = &sc->sc_hmc_entries[i]; 4576 4577 ixl_wr(sc, regs[i].setoff, e->hmc_base / IXL_HMC_ROUNDUP); 4578 ixl_wr(sc, regs[i].setcnt, e->hmc_count); 4579 } 4580 4581 return (0); 4582 } 4583 4584 static void 4585 ixl_hmc_free(struct ixl_softc *sc) 4586 { 4587 ixl_dmamem_free(sc, &sc->sc_hmc_sd); 4588 ixl_dmamem_free(sc, &sc->sc_hmc_pd); 4589 } 4590 4591 static void 4592 ixl_hmc_pack(void *d, const void *s, const struct ixl_hmc_pack *packing, 4593 unsigned int npacking) 4594 { 4595 uint8_t *dst = d; 4596 const uint8_t *src = s; 4597 unsigned int i; 4598 4599 for (i = 0; i < npacking; i++) { 4600 const struct ixl_hmc_pack *pack = &packing[i]; 4601 unsigned int offset = pack->lsb / 8; 4602 unsigned int align = pack->lsb % 8; 4603 const uint8_t *in = src + pack->offset; 4604 uint8_t *out = dst + offset; 4605 int width = pack->width; 4606 unsigned int inbits = 0; 4607 4608 if (align) { 4609 inbits = (*in++) << align; 4610 *out++ |= (inbits & 0xff); 4611 inbits >>= 8; 4612 4613 width -= 8 - align; 4614 } 4615 4616 while (width >= 8) { 4617 inbits |= (*in++) << align; 4618 *out++ = (inbits & 0xff); 4619 inbits >>= 8; 4620 4621 width -= 8; 4622 } 4623 4624 if (width > 0) { 4625 inbits |= (*in) << align; 4626 *out |= (inbits & ((1 << width) - 1)); 4627 } 4628 } 4629 } 4630 4631 static struct ixl_aq_buf * 4632 ixl_aqb_alloc(struct ixl_softc *sc) 4633 { 4634 struct ixl_aq_buf *aqb; 4635 4636 aqb = malloc(sizeof(*aqb), M_DEVBUF, M_WAITOK); 4637 if (aqb == NULL) 4638 return (NULL); 4639 4640 aqb->aqb_data = dma_alloc(IXL_AQ_BUFLEN, PR_WAITOK); 4641 if (aqb->aqb_data == NULL) 4642 goto free; 4643 4644 if (bus_dmamap_create(sc->sc_dmat, IXL_AQ_BUFLEN, 1, 4645 IXL_AQ_BUFLEN, 0, 4646 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 4647 &aqb->aqb_map) != 0) 4648 goto dma_free; 4649 4650 if (bus_dmamap_load(sc->sc_dmat, aqb->aqb_map, aqb->aqb_data, 4651 IXL_AQ_BUFLEN, NULL, BUS_DMA_WAITOK) != 0) 4652 goto destroy; 4653 4654 return (aqb); 4655 4656 destroy: 4657 bus_dmamap_destroy(sc->sc_dmat, aqb->aqb_map); 4658 dma_free: 4659 dma_free(aqb->aqb_data, IXL_AQ_BUFLEN); 4660 free: 4661 free(aqb, M_DEVBUF, sizeof(*aqb)); 4662 4663 return (NULL); 4664 } 4665 4666 static void 4667 ixl_aqb_free(struct ixl_softc *sc, struct ixl_aq_buf *aqb) 4668 { 4669 bus_dmamap_unload(sc->sc_dmat, aqb->aqb_map); 4670 bus_dmamap_destroy(sc->sc_dmat, aqb->aqb_map); 4671 dma_free(aqb->aqb_data, IXL_AQ_BUFLEN); 4672 free(aqb, M_DEVBUF, sizeof(*aqb)); 4673 } 4674 4675 static int 4676 ixl_arq_fill(struct ixl_softc *sc) 4677 { 4678 struct ixl_aq_buf *aqb; 4679 struct ixl_aq_desc *arq, *iaq; 4680 unsigned int prod = sc->sc_arq_prod; 4681 unsigned int n; 4682 int post = 0; 4683 4684 n = if_rxr_get(&sc->sc_arq_ring, IXL_AQ_NUM); 4685 arq = IXL_DMA_KVA(&sc->sc_arq); 4686 4687 while (n > 0) { 4688 aqb = SIMPLEQ_FIRST(&sc->sc_arq_idle); 4689 if (aqb != NULL) 4690 SIMPLEQ_REMOVE_HEAD(&sc->sc_arq_idle, aqb_entry); 4691 else if ((aqb = ixl_aqb_alloc(sc)) == NULL) 4692 break; 4693 4694 memset(aqb->aqb_data, 0, IXL_AQ_BUFLEN); 4695 4696 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IXL_AQ_BUFLEN, 4697 BUS_DMASYNC_PREREAD); 4698 4699 iaq = &arq[prod]; 4700 iaq->iaq_flags = htole16(IXL_AQ_BUF | 4701 (IXL_AQ_BUFLEN > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4702 iaq->iaq_opcode = 0; 4703 iaq->iaq_datalen = htole16(IXL_AQ_BUFLEN); 4704 iaq->iaq_retval = 0; 4705 iaq->iaq_cookie = 0; 4706 iaq->iaq_param[0] = 0; 4707 iaq->iaq_param[1] = 0; 4708 ixl_aq_dva(iaq, aqb->aqb_map->dm_segs[0].ds_addr); 4709 4710 SIMPLEQ_INSERT_TAIL(&sc->sc_arq_live, aqb, aqb_entry); 4711 4712 prod++; 4713 prod &= IXL_AQ_MASK; 4714 4715 post = 1; 4716 4717 n--; 4718 } 4719 4720 if_rxr_put(&sc->sc_arq_ring, n); 4721 sc->sc_arq_prod = prod; 4722 4723 return (post); 4724 } 4725 4726 static void 4727 ixl_arq_unfill(struct ixl_softc *sc) 4728 { 4729 struct ixl_aq_buf *aqb; 4730 4731 while ((aqb = SIMPLEQ_FIRST(&sc->sc_arq_live)) != NULL) { 4732 SIMPLEQ_REMOVE_HEAD(&sc->sc_arq_live, aqb_entry); 4733 4734 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IXL_AQ_BUFLEN, 4735 BUS_DMASYNC_POSTREAD); 4736 ixl_aqb_free(sc, aqb); 4737 } 4738 } 4739 4740 static void 4741 ixl_clear_hw(struct ixl_softc *sc) 4742 { 4743 uint32_t num_queues, base_queue; 4744 uint32_t num_pf_int; 4745 uint32_t num_vf_int; 4746 uint32_t num_vfs; 4747 uint32_t i, j; 4748 uint32_t val; 4749 4750 /* get number of interrupts, queues, and vfs */ 4751 val = ixl_rd(sc, I40E_GLPCI_CNF2); 4752 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 4753 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 4754 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 4755 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 4756 4757 val = ixl_rd(sc, I40E_PFLAN_QALLOC); 4758 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 4759 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 4760 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 4761 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 4762 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 4763 num_queues = (j - base_queue) + 1; 4764 else 4765 num_queues = 0; 4766 4767 val = ixl_rd(sc, I40E_PF_VT_PFALLOC); 4768 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 4769 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 4770 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 4771 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 4772 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 4773 num_vfs = (j - i) + 1; 4774 else 4775 num_vfs = 0; 4776 4777 /* stop all the interrupts */ 4778 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 0); 4779 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 4780 for (i = 0; i < num_pf_int - 2; i++) 4781 ixl_wr(sc, I40E_PFINT_DYN_CTLN(i), val); 4782 4783 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 4784 val = I40E_QUEUE_TYPE_EOL << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 4785 ixl_wr(sc, I40E_PFINT_LNKLST0, val); 4786 for (i = 0; i < num_pf_int - 2; i++) 4787 ixl_wr(sc, I40E_PFINT_LNKLSTN(i), val); 4788 val = I40E_QUEUE_TYPE_EOL << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 4789 for (i = 0; i < num_vfs; i++) 4790 ixl_wr(sc, I40E_VPINT_LNKLST0(i), val); 4791 for (i = 0; i < num_vf_int - 2; i++) 4792 ixl_wr(sc, I40E_VPINT_LNKLSTN(i), val); 4793 4794 /* warn the HW of the coming Tx disables */ 4795 for (i = 0; i < num_queues; i++) { 4796 uint32_t abs_queue_idx = base_queue + i; 4797 uint32_t reg_block = 0; 4798 4799 if (abs_queue_idx >= 128) { 4800 reg_block = abs_queue_idx / 128; 4801 abs_queue_idx %= 128; 4802 } 4803 4804 val = ixl_rd(sc, I40E_GLLAN_TXPRE_QDIS(reg_block)); 4805 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 4806 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 4807 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 4808 4809 ixl_wr(sc, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 4810 } 4811 delaymsec(400); 4812 4813 /* stop all the queues */ 4814 for (i = 0; i < num_queues; i++) { 4815 ixl_wr(sc, I40E_QINT_TQCTL(i), 0); 4816 ixl_wr(sc, I40E_QTX_ENA(i), 0); 4817 ixl_wr(sc, I40E_QINT_RQCTL(i), 0); 4818 ixl_wr(sc, I40E_QRX_ENA(i), 0); 4819 } 4820 4821 /* short wait for all queue disables to settle */ 4822 delaymsec(50); 4823 } 4824 4825 static int 4826 ixl_pf_reset(struct ixl_softc *sc) 4827 { 4828 uint32_t cnt = 0; 4829 uint32_t cnt1 = 0; 4830 uint32_t reg = 0; 4831 uint32_t grst_del; 4832 4833 /* 4834 * Poll for Global Reset steady state in case of recent GRST. 4835 * The grst delay value is in 100ms units, and we'll wait a 4836 * couple counts longer to be sure we don't just miss the end. 4837 */ 4838 grst_del = ixl_rd(sc, I40E_GLGEN_RSTCTL); 4839 grst_del &= I40E_GLGEN_RSTCTL_GRSTDEL_MASK; 4840 grst_del >>= I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 4841 grst_del += 10; 4842 4843 for (cnt = 0; cnt < grst_del; cnt++) { 4844 reg = ixl_rd(sc, I40E_GLGEN_RSTAT); 4845 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 4846 break; 4847 delaymsec(100); 4848 } 4849 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 4850 printf(", Global reset polling failed to complete\n"); 4851 return (-1); 4852 } 4853 4854 /* Now Wait for the FW to be ready */ 4855 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 4856 reg = ixl_rd(sc, I40E_GLNVM_ULD); 4857 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 4858 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 4859 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 4860 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) 4861 break; 4862 4863 delaymsec(10); 4864 } 4865 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 4866 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 4867 printf(", wait for FW Reset complete timed out " 4868 "(I40E_GLNVM_ULD = 0x%x)\n", reg); 4869 return (-1); 4870 } 4871 4872 /* 4873 * If there was a Global Reset in progress when we got here, 4874 * we don't need to do the PF Reset 4875 */ 4876 if (cnt == 0) { 4877 reg = ixl_rd(sc, I40E_PFGEN_CTRL); 4878 ixl_wr(sc, I40E_PFGEN_CTRL, reg | I40E_PFGEN_CTRL_PFSWR_MASK); 4879 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 4880 reg = ixl_rd(sc, I40E_PFGEN_CTRL); 4881 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 4882 break; 4883 delaymsec(1); 4884 } 4885 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 4886 printf(", PF reset polling failed to complete" 4887 "(I40E_PFGEN_CTRL= 0x%x)\n", reg); 4888 return (-1); 4889 } 4890 } 4891 4892 return (0); 4893 } 4894 4895 static uint32_t 4896 ixl_710_rd_ctl(struct ixl_softc *sc, uint32_t r) 4897 { 4898 /* XXX this should fall back to registers for api < 1.5 */ 4899 struct ixl_atq iatq; 4900 struct ixl_aq_desc *iaq; 4901 uint16_t retval; 4902 4903 memset(&iatq, 0, sizeof(iatq)); 4904 iaq = &iatq.iatq_desc; 4905 iaq->iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_READ); 4906 htolem32(&iaq->iaq_param[1], r); 4907 4908 ixl_atq_exec(sc, &iatq, "ixl710rd"); 4909 4910 retval = lemtoh16(&iaq->iaq_retval); 4911 if (retval != IXL_AQ_RC_OK) { 4912 printf("%s: %s failed (%u)\n", DEVNAME(sc), __func__, retval); 4913 return (~0U); 4914 } 4915 4916 return (lemtoh32(&iaq->iaq_param[3])); 4917 } 4918 4919 static void 4920 ixl_710_wr_ctl(struct ixl_softc *sc, uint32_t r, uint32_t v) 4921 { 4922 /* XXX this should fall back to registers for api < 1.5 */ 4923 struct ixl_atq iatq; 4924 struct ixl_aq_desc *iaq; 4925 uint16_t retval; 4926 4927 memset(&iatq, 0, sizeof(iatq)); 4928 iaq = &iatq.iatq_desc; 4929 iaq->iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_WRITE); 4930 htolem32(&iaq->iaq_param[1], r); 4931 htolem32(&iaq->iaq_param[3], v); 4932 4933 ixl_atq_exec(sc, &iatq, "ixl710wr"); 4934 4935 retval = lemtoh16(&iaq->iaq_retval); 4936 if (retval != IXL_AQ_RC_OK) { 4937 printf("%s: %s %08x=%08x failed (%u)\n", 4938 DEVNAME(sc), __func__, r, v, retval); 4939 } 4940 } 4941 4942 static int 4943 ixl_710_set_rss_key(struct ixl_softc *sc, const struct ixl_rss_key *rsskey) 4944 { 4945 unsigned int i; 4946 4947 for (i = 0; i < nitems(rsskey->key); i++) 4948 ixl_710_wr_ctl(sc, I40E_PFQF_HKEY(i), rsskey->key[i]); 4949 4950 return (0); 4951 } 4952 4953 static int 4954 ixl_710_set_rss_lut(struct ixl_softc *sc, const struct ixl_rss_lut_128 *lut) 4955 { 4956 unsigned int i; 4957 4958 for (i = 0; i < nitems(lut->entries); i++) 4959 ixl_wr(sc, I40E_PFQF_HLUT(i), lut->entries[i]); 4960 4961 return (0); 4962 } 4963 4964 static uint32_t 4965 ixl_722_rd_ctl(struct ixl_softc *sc, uint32_t r) 4966 { 4967 return (ixl_rd(sc, r)); 4968 } 4969 4970 static void 4971 ixl_722_wr_ctl(struct ixl_softc *sc, uint32_t r, uint32_t v) 4972 { 4973 ixl_wr(sc, r, v); 4974 } 4975 4976 static int 4977 ixl_722_set_rss_key(struct ixl_softc *sc, const struct ixl_rss_key *rsskey) 4978 { 4979 /* XXX */ 4980 4981 return (0); 4982 } 4983 4984 static int 4985 ixl_722_set_rss_lut(struct ixl_softc *sc, const struct ixl_rss_lut_128 *lut) 4986 { 4987 /* XXX */ 4988 4989 return (0); 4990 } 4991 4992 static int 4993 ixl_dmamem_alloc(struct ixl_softc *sc, struct ixl_dmamem *ixm, 4994 bus_size_t size, u_int align) 4995 { 4996 ixm->ixm_size = size; 4997 4998 if (bus_dmamap_create(sc->sc_dmat, ixm->ixm_size, 1, 4999 ixm->ixm_size, 0, 5000 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 5001 &ixm->ixm_map) != 0) 5002 return (1); 5003 if (bus_dmamem_alloc(sc->sc_dmat, ixm->ixm_size, 5004 align, 0, &ixm->ixm_seg, 1, &ixm->ixm_nsegs, 5005 BUS_DMA_WAITOK | BUS_DMA_ZERO) != 0) 5006 goto destroy; 5007 if (bus_dmamem_map(sc->sc_dmat, &ixm->ixm_seg, ixm->ixm_nsegs, 5008 ixm->ixm_size, &ixm->ixm_kva, BUS_DMA_WAITOK) != 0) 5009 goto free; 5010 if (bus_dmamap_load(sc->sc_dmat, ixm->ixm_map, ixm->ixm_kva, 5011 ixm->ixm_size, NULL, BUS_DMA_WAITOK) != 0) 5012 goto unmap; 5013 5014 return (0); 5015 unmap: 5016 bus_dmamem_unmap(sc->sc_dmat, ixm->ixm_kva, ixm->ixm_size); 5017 free: 5018 bus_dmamem_free(sc->sc_dmat, &ixm->ixm_seg, 1); 5019 destroy: 5020 bus_dmamap_destroy(sc->sc_dmat, ixm->ixm_map); 5021 return (1); 5022 } 5023 5024 static void 5025 ixl_dmamem_free(struct ixl_softc *sc, struct ixl_dmamem *ixm) 5026 { 5027 bus_dmamap_unload(sc->sc_dmat, ixm->ixm_map); 5028 bus_dmamem_unmap(sc->sc_dmat, ixm->ixm_kva, ixm->ixm_size); 5029 bus_dmamem_free(sc->sc_dmat, &ixm->ixm_seg, 1); 5030 bus_dmamap_destroy(sc->sc_dmat, ixm->ixm_map); 5031 } 5032 5033 #if NKSTAT > 0 5034 5035 CTASSERT(KSTAT_KV_U_NONE <= 0xffU); 5036 CTASSERT(KSTAT_KV_U_PACKETS <= 0xffU); 5037 CTASSERT(KSTAT_KV_U_BYTES <= 0xffU); 5038 5039 struct ixl_counter { 5040 const char *c_name; 5041 uint32_t c_base; 5042 uint8_t c_width; 5043 uint8_t c_type; 5044 }; 5045 5046 const struct ixl_counter ixl_port_counters[] = { 5047 /* GORC */ 5048 { "rx bytes", 0x00300000, 48, KSTAT_KV_U_BYTES }, 5049 /* MLFC */ 5050 { "mac local errs", 0x00300020, 32, KSTAT_KV_U_NONE }, 5051 /* MRFC */ 5052 { "mac remote errs", 0x00300040, 32, KSTAT_KV_U_NONE }, 5053 /* MSPDC */ 5054 { "mac short", 0x00300060, 32, KSTAT_KV_U_PACKETS }, 5055 /* CRCERRS */ 5056 { "crc errs", 0x00300080, 32, KSTAT_KV_U_PACKETS }, 5057 /* RLEC */ 5058 { "rx len errs", 0x003000a0, 32, KSTAT_KV_U_PACKETS }, 5059 /* ERRBC */ 5060 { "byte errs", 0x003000c0, 32, KSTAT_KV_U_PACKETS }, 5061 /* ILLERRC */ 5062 { "illegal byte", 0x003000d0, 32, KSTAT_KV_U_PACKETS }, 5063 /* RUC */ 5064 { "rx undersize", 0x00300100, 32, KSTAT_KV_U_PACKETS }, 5065 /* ROC */ 5066 { "rx oversize", 0x00300120, 32, KSTAT_KV_U_PACKETS }, 5067 /* LXONRXCNT */ 5068 { "rx link xon", 0x00300140, 32, KSTAT_KV_U_PACKETS }, 5069 /* LXOFFRXCNT */ 5070 { "rx link xoff", 0x00300160, 32, KSTAT_KV_U_PACKETS }, 5071 5072 /* Priority XON Received Count */ 5073 /* Priority XOFF Received Count */ 5074 /* Priority XON to XOFF Count */ 5075 5076 /* PRC64 */ 5077 { "rx 64B", 0x00300480, 48, KSTAT_KV_U_PACKETS }, 5078 /* PRC127 */ 5079 { "rx 65-127B", 0x003004A0, 48, KSTAT_KV_U_PACKETS }, 5080 /* PRC255 */ 5081 { "rx 128-255B", 0x003004C0, 48, KSTAT_KV_U_PACKETS }, 5082 /* PRC511 */ 5083 { "rx 256-511B", 0x003004E0, 48, KSTAT_KV_U_PACKETS }, 5084 /* PRC1023 */ 5085 { "rx 512-1023B", 0x00300500, 48, KSTAT_KV_U_PACKETS }, 5086 /* PRC1522 */ 5087 { "rx 1024-1522B", 0x00300520, 48, KSTAT_KV_U_PACKETS }, 5088 /* PRC9522 */ 5089 { "rx 1523-9522B", 0x00300540, 48, KSTAT_KV_U_PACKETS }, 5090 /* ROC */ 5091 { "rx fragment", 0x00300560, 32, KSTAT_KV_U_PACKETS }, 5092 /* RJC */ 5093 { "rx jabber", 0x00300580, 32, KSTAT_KV_U_PACKETS }, 5094 /* UPRC */ 5095 { "rx ucasts", 0x003005a0, 48, KSTAT_KV_U_PACKETS }, 5096 /* MPRC */ 5097 { "rx mcasts", 0x003005c0, 48, KSTAT_KV_U_PACKETS }, 5098 /* BPRC */ 5099 { "rx bcasts", 0x003005e0, 48, KSTAT_KV_U_PACKETS }, 5100 /* RDPC */ 5101 { "rx discards", 0x00300600, 32, KSTAT_KV_U_PACKETS }, 5102 /* LDPC */ 5103 { "rx lo discards", 0x00300620, 32, KSTAT_KV_U_PACKETS }, 5104 /* RUPP */ 5105 { "rx no dest", 0x00300660, 32, KSTAT_KV_U_PACKETS }, 5106 5107 /* GOTC */ 5108 { "tx bytes", 0x00300680, 48, KSTAT_KV_U_BYTES }, 5109 /* PTC64 */ 5110 { "tx 64B", 0x003006A0, 48, KSTAT_KV_U_PACKETS }, 5111 /* PTC127 */ 5112 { "tx 65-127B", 0x003006C0, 48, KSTAT_KV_U_PACKETS }, 5113 /* PTC255 */ 5114 { "tx 128-255B", 0x003006E0, 48, KSTAT_KV_U_PACKETS }, 5115 /* PTC511 */ 5116 { "tx 256-511B", 0x00300700, 48, KSTAT_KV_U_PACKETS }, 5117 /* PTC1023 */ 5118 { "tx 512-1023B", 0x00300720, 48, KSTAT_KV_U_PACKETS }, 5119 /* PTC1522 */ 5120 { "tx 1024-1522B", 0x00300740, 48, KSTAT_KV_U_PACKETS }, 5121 /* PTC9522 */ 5122 { "tx 1523-9522B", 0x00300760, 48, KSTAT_KV_U_PACKETS }, 5123 5124 /* Priority XON Transmitted Count */ 5125 /* Priority XOFF Transmitted Count */ 5126 5127 /* LXONTXC */ 5128 { "tx link xon", 0x00300980, 48, KSTAT_KV_U_PACKETS }, 5129 /* LXOFFTXC */ 5130 { "tx link xoff", 0x003009a0, 48, KSTAT_KV_U_PACKETS }, 5131 /* UPTC */ 5132 { "tx ucasts", 0x003009c0, 48, KSTAT_KV_U_PACKETS }, 5133 /* MPTC */ 5134 { "tx mcasts", 0x003009e0, 48, KSTAT_KV_U_PACKETS }, 5135 /* BPTC */ 5136 { "tx bcasts", 0x00300a00, 48, KSTAT_KV_U_PACKETS }, 5137 /* TDOLD */ 5138 { "tx link down", 0x00300a20, 48, KSTAT_KV_U_PACKETS }, 5139 }; 5140 5141 const struct ixl_counter ixl_vsi_counters[] = { 5142 /* VSI RDPC */ 5143 { "rx discards", 0x00310000, 32, KSTAT_KV_U_PACKETS }, 5144 /* VSI GOTC */ 5145 { "tx bytes", 0x00328000, 48, KSTAT_KV_U_BYTES }, 5146 /* VSI UPTC */ 5147 { "tx ucasts", 0x0033c000, 48, KSTAT_KV_U_PACKETS }, 5148 /* VSI MPTC */ 5149 { "tx mcasts", 0x0033cc00, 48, KSTAT_KV_U_PACKETS }, 5150 /* VSI BPTC */ 5151 { "tx bcasts", 0x0033d800, 48, KSTAT_KV_U_PACKETS }, 5152 /* VSI TEPC */ 5153 { "tx errs", 0x00344000, 48, KSTAT_KV_U_PACKETS }, 5154 /* VSI TDPC */ 5155 { "tx discards", 0x00348000, 48, KSTAT_KV_U_PACKETS }, 5156 /* VSI GORC */ 5157 { "rx bytes", 0x00358000, 48, KSTAT_KV_U_BYTES }, 5158 /* VSI UPRC */ 5159 { "rx ucasts", 0x0036c000, 48, KSTAT_KV_U_PACKETS }, 5160 /* VSI MPRC */ 5161 { "rx mcasts", 0x0036cc00, 48, KSTAT_KV_U_PACKETS }, 5162 /* VSI BPRC */ 5163 { "rx bcasts", 0x0036d800, 48, KSTAT_KV_U_PACKETS }, 5164 /* VSI RUPP */ 5165 { "rx noproto", 0x0036e400, 32, KSTAT_KV_U_PACKETS }, 5166 }; 5167 5168 struct ixl_counter_state { 5169 const struct ixl_counter 5170 *counters; 5171 uint64_t *values; 5172 size_t n; 5173 uint32_t index; 5174 unsigned int gen; 5175 }; 5176 5177 static void 5178 ixl_rd_counters(struct ixl_softc *sc, const struct ixl_counter_state *state, 5179 uint64_t *vs) 5180 { 5181 const struct ixl_counter *c; 5182 bus_addr_t r; 5183 uint64_t v; 5184 size_t i; 5185 5186 for (i = 0; i < state->n; i++) { 5187 c = &state->counters[i]; 5188 5189 r = c->c_base + (state->index * 8); 5190 5191 if (c->c_width == 32) 5192 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, r); 5193 else 5194 v = bus_space_read_8(sc->sc_memt, sc->sc_memh, r); 5195 5196 vs[i] = v; 5197 } 5198 } 5199 5200 static int 5201 ixl_kstat_read(struct kstat *ks) 5202 { 5203 struct ixl_softc *sc = ks->ks_softc; 5204 struct kstat_kv *kvs = ks->ks_data; 5205 struct ixl_counter_state *state = ks->ks_ptr; 5206 unsigned int gen = (state->gen++) & 1; 5207 uint64_t *ovs = state->values + (gen * state->n); 5208 uint64_t *nvs = state->values + (!gen * state->n); 5209 size_t i; 5210 5211 ixl_rd_counters(sc, state, nvs); 5212 getnanouptime(&ks->ks_updated); 5213 5214 for (i = 0; i < state->n; i++) { 5215 const struct ixl_counter *c = &state->counters[i]; 5216 uint64_t n = nvs[i], o = ovs[i]; 5217 5218 if (c->c_width < 64) { 5219 if (n < o) 5220 n += (1ULL << c->c_width); 5221 } 5222 5223 kstat_kv_u64(&kvs[i]) += (n - o); 5224 } 5225 5226 return (0); 5227 } 5228 5229 static void 5230 ixl_kstat_tick(void *arg) 5231 { 5232 struct ixl_softc *sc = arg; 5233 5234 timeout_add_sec(&sc->sc_kstat_tmo, 4); 5235 5236 mtx_enter(&sc->sc_kstat_mtx); 5237 5238 ixl_kstat_read(sc->sc_port_kstat); 5239 ixl_kstat_read(sc->sc_vsi_kstat); 5240 5241 mtx_leave(&sc->sc_kstat_mtx); 5242 } 5243 5244 static struct kstat * 5245 ixl_kstat_create(struct ixl_softc *sc, const char *name, 5246 const struct ixl_counter *counters, size_t n, uint32_t index) 5247 { 5248 struct kstat *ks; 5249 struct kstat_kv *kvs; 5250 struct ixl_counter_state *state; 5251 const struct ixl_counter *c; 5252 unsigned int i; 5253 5254 ks = kstat_create(DEVNAME(sc), 0, name, 0, KSTAT_T_KV, 0); 5255 if (ks == NULL) { 5256 /* unable to create kstats */ 5257 return (NULL); 5258 } 5259 5260 kvs = mallocarray(n, sizeof(*kvs), M_DEVBUF, M_WAITOK|M_ZERO); 5261 for (i = 0; i < n; i++) { 5262 c = &counters[i]; 5263 5264 kstat_kv_unit_init(&kvs[i], c->c_name, 5265 KSTAT_KV_T_COUNTER64, c->c_type); 5266 } 5267 5268 ks->ks_data = kvs; 5269 ks->ks_datalen = n * sizeof(*kvs); 5270 ks->ks_read = ixl_kstat_read; 5271 5272 state = malloc(sizeof(*state), M_DEVBUF, M_WAITOK|M_ZERO); 5273 state->counters = counters; 5274 state->n = n; 5275 state->values = mallocarray(n * 2, sizeof(*state->values), 5276 M_DEVBUF, M_WAITOK|M_ZERO); 5277 state->index = index; 5278 ks->ks_ptr = state; 5279 5280 kstat_set_mutex(ks, &sc->sc_kstat_mtx); 5281 ks->ks_softc = sc; 5282 kstat_install(ks); 5283 5284 /* fetch a baseline */ 5285 ixl_rd_counters(sc, state, state->values); 5286 5287 return (ks); 5288 } 5289 5290 static void 5291 ixl_kstat_attach(struct ixl_softc *sc) 5292 { 5293 mtx_init(&sc->sc_kstat_mtx, IPL_SOFTCLOCK); 5294 timeout_set(&sc->sc_kstat_tmo, ixl_kstat_tick, sc); 5295 5296 sc->sc_port_kstat = ixl_kstat_create(sc, "ixl-port", 5297 ixl_port_counters, nitems(ixl_port_counters), sc->sc_port); 5298 sc->sc_vsi_kstat = ixl_kstat_create(sc, "ixl-vsi", 5299 ixl_vsi_counters, nitems(ixl_vsi_counters), 5300 lemtoh16(&sc->sc_vsi_number)); 5301 5302 /* ixl counters go up even when the interface is down */ 5303 timeout_add_sec(&sc->sc_kstat_tmo, 4); 5304 } 5305 5306 #endif /* NKSTAT > 0 */ 5307