1 /* $OpenBSD: if_iwnreg.h,v 1.53 2016/04/28 08:28:18 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2007, 2008 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define IWN_TX_RING_COUNT 256 21 #define IWN_TX_RING_LOMARK 192 22 #define IWN_TX_RING_HIMARK 224 23 #define IWN_RX_RING_COUNT_LOG 6 24 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 25 26 #define IWN4965_NTXQUEUES 16 27 #define IWN5000_NTXQUEUES 20 28 29 #define IWN4965_NDMACHNLS 7 30 #define IWN5000_NDMACHNLS 8 31 32 #define IWN_SRVC_DMACHNL 9 33 34 #define IWN_ICT_SIZE 4096 35 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 36 37 /* Maximum number of DMA segments for TX. */ 38 #define IWN_MAX_SCATTER 20 39 40 /* RX buffers must be large enough to hold a full 4K A-MPDU. */ 41 #define IWN_RBUF_SIZE (4 * 1024) 42 43 #if defined(__LP64__) 44 /* HW supports 36-bit DMA addresses. */ 45 #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 46 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 47 #else 48 #define IWN_LOADDR(paddr) (paddr) 49 #define IWN_HIADDR(paddr) (0) 50 #endif 51 52 /* Base Address Register. */ 53 #define IWN_PCI_BAR0 PCI_MAPREG_START 54 55 /* 56 * Control and status registers. 57 */ 58 #define IWN_HW_IF_CONFIG 0x000 59 #define IWN_INT_COALESCING 0x004 60 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 61 #define IWN_INT 0x008 62 #define IWN_INT_MASK 0x00c 63 #define IWN_FH_INT 0x010 64 #define IWN_RESET 0x020 65 #define IWN_GP_CNTRL 0x024 66 #define IWN_HW_REV 0x028 67 #define IWN_EEPROM 0x02c 68 #define IWN_EEPROM_GP 0x030 69 #define IWN_OTP_GP 0x034 70 #define IWN_GIO 0x03c 71 #define IWN_GP_DRIVER 0x050 72 #define IWN_UCODE_GP1_CLR 0x05c 73 #define IWN_LED 0x094 74 #define IWN_DRAM_INT_TBL 0x0a0 75 #define IWN_SHADOW_REG_CTRL 0x0a8 76 #define IWN_GIO_CHICKEN 0x100 77 #define IWN_ANA_PLL 0x20c 78 #define IWN_HW_REV_WA 0x22c 79 #define IWN_DBG_HPET_MEM 0x240 80 #define IWN_DBG_LINK_PWR_MGMT 0x250 81 #define IWN_MEM_RADDR 0x40c 82 #define IWN_MEM_WADDR 0x410 83 #define IWN_MEM_WDATA 0x418 84 #define IWN_MEM_RDATA 0x41c 85 #define IWN_PRPH_WADDR 0x444 86 #define IWN_PRPH_RADDR 0x448 87 #define IWN_PRPH_WDATA 0x44c 88 #define IWN_PRPH_RDATA 0x450 89 #define IWN_HBUS_TARG_WRPTR 0x460 90 91 /* 92 * Flow-Handler registers. 93 */ 94 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 95 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 96 #define IWN_FH_KW_ADDR 0x197c 97 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 98 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 99 #define IWN_FH_STATUS_WPTR 0x1bc0 100 #define IWN_FH_RX_BASE 0x1bc4 101 #define IWN_FH_RX_WPTR 0x1bc8 102 #define IWN_FH_RX_CONFIG 0x1c00 103 #define IWN_FH_RX_STATUS 0x1c44 104 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 105 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 106 #define IWN_FH_TX_CHICKEN 0x1e98 107 #define IWN_FH_TX_STATUS 0x1eb0 108 109 /* 110 * TX scheduler registers. 111 */ 112 #define IWN_SCHED_BASE 0xa02c00 113 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 114 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 115 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 116 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 117 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 118 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 119 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 120 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 121 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 122 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 123 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 124 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 125 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 126 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 127 128 /* 129 * Offsets in TX scheduler's SRAM. 130 */ 131 #define IWN4965_SCHED_CTX_OFF 0x380 132 #define IWN4965_SCHED_CTX_LEN 416 133 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 134 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 135 #define IWN5000_SCHED_CTX_OFF 0x600 136 #define IWN5000_SCHED_CTX_LEN 520 137 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 138 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 139 140 /* 141 * NIC internal memory offsets. 142 */ 143 #define IWN_APMG_CLK_CTRL 0x3000 144 #define IWN_APMG_CLK_EN 0x3004 145 #define IWN_APMG_CLK_DIS 0x3008 146 #define IWN_APMG_PS 0x300c 147 #define IWN_APMG_DIGITAL_SVR 0x3058 148 #define IWN_APMG_ANALOG_SVR 0x306c 149 #define IWN_APMG_PCI_STT 0x3010 150 #define IWN_BSM_WR_CTRL 0x3400 151 #define IWN_BSM_WR_MEM_SRC 0x3404 152 #define IWN_BSM_WR_MEM_DST 0x3408 153 #define IWN_BSM_WR_DWCOUNT 0x340c 154 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 155 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 156 #define IWN_BSM_DRAM_DATA_ADDR 0x3498 157 #define IWN_BSM_DRAM_DATA_SIZE 0x349c 158 #define IWN_BSM_SRAM_BASE 0x3800 159 160 /* Possible flags for register IWN_HW_IF_CONFIG. */ 161 #define IWN_HW_IF_CONFIG_4965_R (1 << 4) 162 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 163 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 164 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 165 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 166 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 167 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 168 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 169 170 /* Possible values for register IWN_INT_PERIODIC. */ 171 #define IWN_INT_PERIODIC_DIS 0x00 172 #define IWN_INT_PERIODIC_ENA 0xff 173 174 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 175 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 176 177 /* Possible values for IWN_BSM_WR_MEM_DST. */ 178 #define IWN_FW_TEXT_BASE 0x00000000 179 #define IWN_FW_DATA_BASE 0x00800000 180 181 /* Possible flags for register IWN_RESET. */ 182 #define IWN_RESET_NEVO (1U << 0) 183 #define IWN_RESET_SW (1U << 7) 184 #define IWN_RESET_MASTER_DISABLED (1U << 8) 185 #define IWN_RESET_STOP_MASTER (1U << 9) 186 #define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) 187 188 /* Possible flags for register IWN_GP_CNTRL. */ 189 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 190 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 191 #define IWN_GP_CNTRL_INIT_DONE (1 << 2) 192 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 193 #define IWN_GP_CNTRL_SLEEP (1 << 4) 194 #define IWN_GP_CNTRL_RFKILL (1 << 27) 195 196 /* Possible flags for register IWN_HW_REV. */ 197 #define IWN_HW_REV_TYPE_SHIFT 4 198 #define IWN_HW_REV_TYPE_MASK 0x000001f0 199 #define IWN_HW_REV_TYPE_4965 0 200 #define IWN_HW_REV_TYPE_5300 2 201 #define IWN_HW_REV_TYPE_5350 3 202 #define IWN_HW_REV_TYPE_5150 4 203 #define IWN_HW_REV_TYPE_5100 5 204 #define IWN_HW_REV_TYPE_1000 6 205 #define IWN_HW_REV_TYPE_6000 7 206 #define IWN_HW_REV_TYPE_6050 8 207 #define IWN_HW_REV_TYPE_6005 11 208 #define IWN_HW_REV_TYPE_2030 12 209 #define IWN_HW_REV_TYPE_2000 16 210 #define IWN_HW_REV_TYPE_105 17 211 #define IWN_HW_REV_TYPE_135 18 212 213 214 /* Possible flags for register IWN_GIO_CHICKEN. */ 215 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 216 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 217 218 /* Possible flags for register IWN_GIO. */ 219 #define IWN_GIO_L0S_ENA (1 << 1) 220 221 /* Possible flags for register IWN_GP_DRIVER. */ 222 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 223 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 224 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 225 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 226 #define IWN_GP_DRIVER_6050_1X2 (1 << 3) 227 #define IWN_GP_DRIVER_RADIO_IQ_INVERT (1 << 7) 228 229 /* Possible flags for register IWN_UCODE_GP1_CLR. */ 230 #define IWN_UCODE_GP1_RFKILL (1 << 1) 231 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 232 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 233 234 /* Possible flags/values for register IWN_LED. */ 235 #define IWN_LED_BSM_CTRL (1 << 5) 236 #define IWN_LED_OFF 0x00000038 237 #define IWN_LED_ON 0x00000078 238 239 /* Possible flags for register IWN_DRAM_INT_TBL. */ 240 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1U << 27) 241 #define IWN_DRAM_INT_TBL_ENABLE (1U << 31) 242 243 /* Possible values for register IWN_ANA_PLL. */ 244 #define IWN_ANA_PLL_INIT 0x00880300 245 246 /* Possible flags for register IWN_FH_RX_STATUS. */ 247 #define IWN_FH_RX_STATUS_IDLE (1 << 24) 248 249 /* Possible flags for register IWN_BSM_WR_CTRL. */ 250 #define IWN_BSM_WR_CTRL_START_EN (1U << 30) 251 #define IWN_BSM_WR_CTRL_START (1U << 31) 252 253 /* Possible flags for register IWN_INT. */ 254 #define IWN_INT_ALIVE (1U << 0) 255 #define IWN_INT_WAKEUP (1U << 1) 256 #define IWN_INT_SW_RX (1U << 3) 257 #define IWN_INT_CT_REACHED (1U << 6) 258 #define IWN_INT_RF_TOGGLED (1U << 7) 259 #define IWN_INT_SW_ERR (1U << 25) 260 #define IWN_INT_SCHED (1U << 26) 261 #define IWN_INT_FH_TX (1U << 27) 262 #define IWN_INT_RX_PERIODIC (1U << 28) 263 #define IWN_INT_HW_ERR (1U << 29) 264 #define IWN_INT_FH_RX (1U << 31) 265 266 /* Shortcut. */ 267 #define IWN_INT_MASK_DEF \ 268 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 269 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 270 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 271 272 /* Possible flags for register IWN_FH_INT. */ 273 #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 274 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 275 #define IWN_FH_INT_HI_PRIOR (1 << 30) 276 /* Shortcuts for the above. */ 277 #define IWN_FH_INT_TX \ 278 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 279 #define IWN_FH_INT_RX \ 280 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 281 282 /* Possible flags/values for register IWN_FH_TX_CONFIG. */ 283 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 284 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 285 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1U << 20) 286 287 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 288 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 289 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 290 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 291 292 /* Possible flags for register IWN_FH_TX_CHICKEN. */ 293 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 294 295 /* Possible flags for register IWN_FH_TX_STATUS. */ 296 #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 297 298 /* Possible flags for register IWN_FH_RX_CONFIG. */ 299 #define IWN_FH_RX_CONFIG_ENA (1U << 31) 300 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 301 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1U << 16) 302 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1U << 15) 303 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1U << 12) 304 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) /* units 32 usec */ 305 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1U << 2) 306 307 /* Possible flags for register IWN_FH_TX_CONFIG. */ 308 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 309 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1U << 3) 310 311 /* Possible flags for register IWN_EEPROM. */ 312 #define IWN_EEPROM_READ_VALID (1 << 0) 313 #define IWN_EEPROM_CMD (1 << 1) 314 315 /* Possible flags for register IWN_EEPROM_GP. */ 316 #define IWN_EEPROM_GP_IF_OWNER 0x00000180 317 318 /* Possible flags for register IWN_OTP_GP. */ 319 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 320 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 321 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 322 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 323 324 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 325 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 326 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 327 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 328 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 329 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 330 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 331 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 332 333 /* Possible flags for registers IWN_APMG_CLK_*. */ 334 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 335 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 336 337 /* Possible flags for register IWN_APMG_PS. */ 338 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 339 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 340 #define IWN_APMG_PS_PWR_SRC_VMAIN 0 341 #define IWN_APMG_PS_PWR_SRC_VAUX 2 342 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 343 #define IWN_APMG_PS_RESET_REQ (1 << 26) 344 345 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 346 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 347 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 348 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 349 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 350 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 351 352 /* Possible flags for IWN_APMG_PCI_STT. */ 353 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 354 355 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 356 #define IWN_FW_UPDATED (1U << 31) 357 358 #define IWN_SCHED_WINSZ 64 359 #define IWN_SCHED_LIMIT 64 360 #define IWN4965_SCHED_COUNT 512 361 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 362 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 363 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 364 365 struct iwn_tx_desc { 366 uint8_t reserved1[3]; 367 uint8_t nsegs; 368 struct { 369 uint32_t addr; 370 uint16_t len; 371 } __packed segs[IWN_MAX_SCATTER]; 372 /* Pad to 128 bytes. */ 373 uint32_t reserved2; 374 } __packed; 375 376 struct iwn_rx_status { 377 uint16_t closed_count; 378 uint16_t closed_rx_count; 379 uint16_t finished_count; 380 uint16_t finished_rx_count; 381 uint32_t reserved[2]; 382 } __packed; 383 384 struct iwn_rx_desc { 385 uint32_t len; 386 #define IWN_RX_DESC_LEN_MASK 0x00003fff 387 #define IWN_RX_DESC_LEN_SHIFT 0 388 #define IWN_RX_DESC_FLAG_FLUSH_RB_REQ 0x80000000 389 #define IWN_RX_DESC_FLAG_IGNORE_TC 0x40000000 390 #define IWN_RX_DESC_FLAG_FAST_IRQ 0x20000000 391 392 uint8_t type; 393 #define IWN_UC_READY 1 394 #define IWN_ADD_NODE_DONE 24 395 #define IWN_TX_DONE 28 396 #define IWN5000_CALIBRATION_RESULT 102 397 #define IWN5000_CALIBRATION_DONE 103 398 #define IWN_START_SCAN 130 399 #define IWN_STOP_SCAN 132 400 #define IWN_RX_STATISTICS 156 401 #define IWN_BEACON_STATISTICS 157 402 #define IWN_STATE_CHANGED 161 403 #define IWN_BEACON_MISSED 162 404 #define IWN_RX_PHY 192 405 #define IWN_MPDU_RX_DONE 193 406 #define IWN_RX_DONE 195 407 #define IWN_RX_COMPRESSED_BA 197 408 409 uint8_t flags; /* XXX iwlwifi calls this "group_id" */ 410 uint8_t idx; 411 uint8_t qid; 412 } __packed; 413 414 /* Possible RX status flags. */ 415 #define IWN_RX_NO_CRC_ERR (1 << 0) 416 #define IWN_RX_NO_OVFL_ERR (1 << 1) 417 /* Shortcut for the above. */ 418 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 419 #define IWN_RX_MPDU_MIC_OK (1 << 6) 420 #define IWN_RX_CIPHER_MASK (7 << 8) 421 #define IWN_RX_CIPHER_CCMP (2 << 8) 422 #define IWN_RX_MPDU_DEC (1 << 11) 423 #define IWN_RX_DECRYPT_MASK (3 << 11) 424 #define IWN_RX_DECRYPT_OK (3 << 11) 425 426 struct iwn_tx_cmd { 427 uint8_t code; 428 #define IWN_CMD_RXON 16 429 #define IWN_CMD_RXON_ASSOC 17 430 #define IWN_CMD_EDCA_PARAMS 19 431 #define IWN_CMD_TIMING 20 432 #define IWN_CMD_ADD_NODE 24 433 #define IWN_CMD_TX_DATA 28 434 #define IWN_CMD_LINK_QUALITY 78 435 #define IWN_CMD_SET_LED 72 436 #define IWN5000_CMD_WIMAX_COEX 90 437 #define IWN5000_CMD_CALIB_CONFIG 101 438 #define IWN_CMD_SET_POWER_MODE 119 439 #define IWN_CMD_SCAN 128 440 #define IWN_CMD_TXPOWER_DBM 149 441 #define IWN_CMD_TXPOWER 151 442 #define IWN5000_CMD_TX_ANT_CONFIG 152 443 #define IWN_CMD_BT_COEX 155 444 #define IWN_CMD_GET_STATISTICS 156 445 #define IWN_CMD_SET_CRITICAL_TEMP 164 446 #define IWN_CMD_SET_SENSITIVITY 168 447 #define IWN_CMD_PHY_CALIB 176 448 #define IWN_CMD_BT_COEX_PRIOTABLE 204 449 #define IWN_CMD_BT_COEX_PROT 205 450 451 uint8_t flags; 452 uint8_t idx; 453 uint8_t qid; 454 uint8_t data[136]; 455 } __packed; 456 457 /* Antenna flags, used in various commands. */ 458 #define IWN_ANT_A (1 << 0) 459 #define IWN_ANT_B (1 << 1) 460 #define IWN_ANT_C (1 << 2) 461 /* Shortcuts. */ 462 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 463 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 464 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 465 466 /* Structure for command IWN_CMD_RXON. */ 467 struct iwn_rxon { 468 uint8_t myaddr[IEEE80211_ADDR_LEN]; 469 uint16_t reserved1; 470 uint8_t bssid[IEEE80211_ADDR_LEN]; 471 uint16_t reserved2; 472 uint8_t wlap[IEEE80211_ADDR_LEN]; 473 uint16_t reserved3; 474 uint8_t mode; 475 #define IWN_MODE_HOSTAP 1 476 #define IWN_MODE_STA 3 477 #define IWN_MODE_IBSS 4 478 #define IWN_MODE_MONITOR 6 479 480 uint8_t air; 481 uint16_t rxchain; 482 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 483 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 484 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 485 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 486 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 487 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 488 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 489 490 uint8_t ofdm_mask; 491 uint8_t cck_mask; 492 uint16_t associd; 493 uint32_t flags; 494 #define IWN_RXON_24GHZ (1 << 0) 495 #define IWN_RXON_CCK (1 << 1) 496 #define IWN_RXON_AUTO (1 << 2) 497 #define IWN_RXON_TGG_PROT (1 << 3) 498 #define IWN_RXON_SHSLOT (1 << 4) 499 #define IWN_RXON_SHPREAMBLE (1 << 5) 500 #define IWN_RXON_NODIVERSITY (1 << 7) 501 #define IWN_RXON_ANTENNA_A (1 << 8) 502 #define IWN_RXON_ANTENNA_B (1 << 9) 503 #define IWN_RXON_TSF (1 << 15) 504 #define IWN_RXON_HT_HT40MINUS (1 << 22) 505 #define IWN_RXON_HT_PROTMODE(x) ((x) << 23) /* 2 bits */ 506 #define IWN_RXON_HT_CHANMODE_PURE40 (1 << 25) 507 #define IWN_RXON_HT_CHANMODE_MIXED2040 (2 << 25) 508 #define IWN_RXON_CTS_TO_SELF (1 << 30) 509 510 uint32_t filter; 511 #define IWN_FILTER_PROMISC (1 << 0) 512 #define IWN_FILTER_CTL (1 << 1) 513 #define IWN_FILTER_MULTICAST (1 << 2) 514 #define IWN_FILTER_NODECRYPT (1 << 3) 515 #define IWN_FILTER_BSS (1 << 5) 516 #define IWN_FILTER_BEACON (1 << 6) 517 518 uint8_t chan; 519 uint8_t reserved4; 520 uint8_t ht_single_mask; 521 uint8_t ht_dual_mask; 522 /* The following fields are for >=5000 Series only. */ 523 uint8_t ht_triple_mask; 524 uint8_t reserved5; 525 uint16_t acquisition; 526 uint16_t reserved6; 527 } __packed; 528 529 /* Structure for command IWN_CMD_RXON_ASSOC. */ 530 struct iwn_rxon_assoc { 531 uint32_t flags; 532 uint32_t filter; 533 uint8_t ofdm_mask; 534 uint8_t cck_mask; 535 uint16_t reserved1; 536 uint8_t ht_single_mask; 537 uint8_t ht_dual_mask; 538 uint8_t ht_triple_mask; 539 uint8_t reserved2; 540 uint16_t rxchain; 541 uint16_t acquisition; 542 uint32_t reserved3; 543 } __packed; 544 545 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 546 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 547 548 /* Structure for command IWN_CMD_ASSOCIATE. */ 549 struct iwn_assoc { 550 uint32_t flags; 551 uint32_t filter; 552 uint8_t ofdm_mask; 553 uint8_t cck_mask; 554 uint16_t reserved; 555 } __packed; 556 557 /* Structure for command IWN_CMD_EDCA_PARAMS. */ 558 struct iwn_edca_params { 559 uint32_t flags; 560 #define IWN_EDCA_UPDATE (1 << 0) 561 #define IWN_EDCA_TXOP (1 << 4) 562 563 struct { 564 uint16_t cwmin; 565 uint16_t cwmax; 566 uint8_t aifsn; 567 uint8_t reserved; 568 uint16_t txoplimit; 569 } __packed ac[EDCA_NUM_AC]; 570 } __packed; 571 572 /* Structure for command IWN_CMD_TIMING. */ 573 struct iwn_cmd_timing { 574 uint64_t tstamp; 575 uint16_t bintval; 576 uint16_t atim; 577 uint32_t binitval; 578 uint16_t lintval; 579 uint16_t reserved; 580 } __packed; 581 582 /* Structure for command IWN_CMD_ADD_NODE. */ 583 struct iwn_node_info { 584 uint8_t control; 585 #define IWN_NODE_UPDATE (1 << 0) 586 587 uint8_t reserved1[3]; 588 589 uint8_t macaddr[IEEE80211_ADDR_LEN]; 590 uint16_t reserved2; 591 uint8_t id; 592 #define IWN_ID_BSS 0 593 #define IWN5000_ID_BROADCAST 15 594 #define IWN4965_ID_BROADCAST 31 595 596 uint8_t flags; 597 #define IWN_FLAG_SET_KEY (1 << 0) 598 #define IWN_FLAG_SET_DISABLE_TID (1 << 1) 599 #define IWN_FLAG_SET_TXRATE (1 << 2) 600 #define IWN_FLAG_SET_ADDBA (1 << 3) 601 #define IWN_FLAG_SET_DELBA (1 << 4) 602 603 uint16_t reserved3; 604 uint16_t kflags; 605 #define IWN_KFLAG_CCMP (1 << 1) 606 #define IWN_KFLAG_MAP (1 << 3) 607 #define IWN_KFLAG_KID(kid) ((kid) << 8) 608 #define IWN_KFLAG_INVALID (1 << 11) 609 #define IWN_KFLAG_GROUP (1 << 14) 610 611 uint8_t tsc2; /* TKIP TSC2 */ 612 uint8_t reserved4; 613 uint16_t ttak[5]; 614 uint8_t kid; 615 uint8_t reserved5; 616 uint8_t key[16]; 617 /* The following 3 fields are for 5000 Series only. */ 618 uint64_t tsc; 619 uint8_t rxmic[IEEE80211_TKIP_MICLEN]; 620 uint8_t txmic[IEEE80211_TKIP_MICLEN]; 621 622 uint32_t htflags; 623 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 624 #define IWN_AMDPU_SIZE_FACTOR_MASK ((0x3) << 19) 625 #define IWN_AMDPU_DENSITY(x) ((x) << 23) 626 #define IWN_AMDPU_DENSITY_MASK ((0x7) << 23) 627 628 uint32_t htmask; 629 uint16_t disable_tid; 630 uint16_t reserved6; 631 uint8_t addba_tid; 632 uint8_t delba_tid; 633 uint16_t addba_ssn; 634 uint32_t reserved7; 635 } __packed; 636 637 struct iwn4965_node_info { 638 uint8_t control; 639 uint8_t reserved1[3]; 640 uint8_t macaddr[IEEE80211_ADDR_LEN]; 641 uint16_t reserved2; 642 uint8_t id; 643 uint8_t flags; 644 uint16_t reserved3; 645 uint16_t kflags; 646 uint8_t tsc2; /* TKIP TSC2 */ 647 uint8_t reserved4; 648 uint16_t ttak[5]; 649 uint8_t kid; 650 uint8_t reserved5; 651 uint8_t key[16]; 652 uint32_t htflags; 653 uint32_t htmask; 654 uint16_t disable_tid; 655 uint16_t reserved6; 656 uint8_t addba_tid; 657 uint8_t delba_tid; 658 uint16_t addba_ssn; 659 uint32_t reserved7; 660 } __packed; 661 662 #define IWN_RFLAG_MCS (1 << 0) 663 #define IWN_RFLAG_CCK (1 << 1) 664 #define IWN_RFLAG_GREENFIELD (1 << 2) 665 #define IWN_RFLAG_HT40 (1 << 3) 666 #define IWN_RFLAG_DUPLICATE (1 << 4) 667 #define IWN_RFLAG_SGI (1 << 5) 668 #define IWN_RFLAG_ANT(x) ((x) << 6) 669 670 /* Structure for command IWN_CMD_TX_DATA. */ 671 struct iwn_cmd_data { 672 uint16_t len; 673 uint16_t lnext; 674 uint32_t flags; 675 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 676 #define IWN_TX_NEED_RTS (1 << 1) 677 #define IWN_TX_NEED_CTS (1 << 2) 678 #define IWN_TX_NEED_ACK (1 << 3) 679 #define IWN_TX_LINKQ (1 << 4) 680 #define IWN_TX_IMM_BA (1 << 6) 681 #define IWN_TX_FULL_TXOP (1 << 7) 682 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 683 #define IWN_TX_AUTO_SEQ (1 << 13) 684 #define IWN_TX_MORE_FRAG (1 << 14) 685 #define IWN_TX_INSERT_TSTAMP (1 << 16) 686 #define IWN_TX_NEED_PADDING (1 << 20) 687 688 uint32_t scratch; 689 uint8_t plcp; 690 uint8_t rflags; 691 uint16_t xrflags; 692 693 uint8_t id; 694 uint8_t security; 695 #define IWN_CIPHER_WEP40 1 696 #define IWN_CIPHER_CCMP 2 697 #define IWN_CIPHER_TKIP 3 698 #define IWN_CIPHER_WEP104 9 699 700 uint8_t linkq; 701 uint8_t reserved2; 702 uint8_t key[16]; 703 uint16_t fnext; 704 uint16_t reserved3; 705 uint32_t lifetime; 706 #define IWN_LIFETIME_INFINITE 0xffffffff 707 708 uint32_t loaddr; 709 uint8_t hiaddr; 710 uint8_t rts_ntries; 711 uint8_t data_ntries; 712 uint8_t tid; 713 uint16_t timeout; 714 uint16_t txop; 715 } __packed; 716 717 /* Structure for command IWN_CMD_LINK_QUALITY. */ 718 #define IWN_MAX_TX_RETRIES 16 719 struct iwn_cmd_link_quality { 720 uint8_t id; 721 uint8_t reserved1; 722 uint16_t ctl; 723 uint8_t flags; 724 uint8_t mimo; 725 uint8_t antmsk_1stream; 726 uint8_t antmsk_2stream; 727 uint8_t ridx[EDCA_NUM_AC]; 728 uint16_t ampdu_limit; 729 uint8_t ampdu_threshold; 730 uint8_t ampdu_max; 731 #define IWN_AMPDU_MAX_UNLIMITED 0 732 #define IWN_AMPDU_MAX_NO_AGG 1 733 #define IWN_AMPDU_MAX 63 734 uint32_t reserved2; 735 struct { 736 uint8_t plcp; 737 uint8_t rflags; 738 uint16_t xrflags; 739 } __packed retry[IWN_MAX_TX_RETRIES]; 740 uint32_t reserved3; 741 } __packed; 742 743 /* Structure for command IWN_CMD_SET_LED. */ 744 struct iwn_cmd_led { 745 uint32_t unit; /* multiplier (in usecs) */ 746 uint8_t which; 747 #define IWN_LED_ACTIVITY 1 748 #define IWN_LED_LINK 2 749 750 uint8_t off; 751 uint8_t on; 752 uint8_t reserved; 753 } __packed; 754 755 /* Structure for command IWN5000_CMD_WIMAX_COEX. */ 756 struct iwn5000_wimax_coex { 757 uint32_t flags; 758 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 759 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 760 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 761 #define IWN_WIMAX_COEX_ENABLE (1 << 7) 762 763 struct iwn5000_wimax_event { 764 uint8_t request; 765 uint8_t window; 766 uint8_t reserved; 767 uint8_t flags; 768 } __packed events[16]; 769 } __packed; 770 771 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 772 struct iwn5000_calib_elem { 773 uint32_t enable; 774 uint32_t start; 775 #define IWN5000_CALIB_DC (1 << 1) 776 777 uint32_t send; 778 uint32_t apply; 779 uint32_t reserved; 780 } __packed; 781 782 struct iwn5000_calib_status { 783 struct iwn5000_calib_elem once; 784 struct iwn5000_calib_elem perd; 785 uint32_t flags; 786 } __packed; 787 788 struct iwn5000_calib_config { 789 struct iwn5000_calib_status ucode; 790 struct iwn5000_calib_status driver; 791 uint32_t reserved; 792 } __packed; 793 794 /* Structure for command IWN_CMD_SET_POWER_MODE. */ 795 struct iwn_pmgt_cmd { 796 uint16_t flags; 797 #define IWN_PS_ALLOW_SLEEP (1 << 0) 798 #define IWN_PS_NOTIFY (1 << 1) 799 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 800 #define IWN_PS_PCI_PMGT (1 << 3) 801 #define IWN_PS_FAST_PD (1 << 4) 802 803 uint8_t keepalive; 804 uint8_t debug; 805 uint32_t rxtimeout; 806 uint32_t txtimeout; 807 uint32_t intval[5]; 808 uint32_t beacons; 809 } __packed; 810 811 /* Structures for command IWN_CMD_SCAN. */ 812 struct iwn_scan_essid { 813 uint8_t id; 814 uint8_t len; 815 uint8_t data[IEEE80211_NWID_LEN]; 816 } __packed; 817 818 struct iwn_scan_hdr { 819 uint16_t len; 820 uint8_t reserved1; 821 uint8_t nchan; 822 uint16_t quiet_time; 823 uint16_t quiet_threshold; 824 uint16_t crc_threshold; 825 uint16_t rxchain; 826 uint32_t max_svc; /* background scans */ 827 uint32_t pause_svc; /* background scans */ 828 uint32_t flags; 829 uint32_t filter; 830 831 /* Followed by a struct iwn_cmd_data. */ 832 /* Followed by an array of 20 structs iwn_scan_essid. */ 833 /* Followed by probe request body. */ 834 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 835 } __packed; 836 837 struct iwn_scan_chan { 838 uint32_t flags; 839 #define IWN_CHAN_PASSIVE (0 << 0) 840 #define IWN_CHAN_ACTIVE (1 << 0) 841 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 842 843 uint16_t chan; 844 uint8_t rf_gain; 845 uint8_t dsp_gain; 846 uint16_t active; /* msecs */ 847 uint16_t passive; /* msecs */ 848 } __packed; 849 850 /* Maximum size of a scan command. */ 851 #define IWN_SCAN_MAXSZ (MCLBYTES - 4) 852 853 /* 854 * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after 855 * sending probe req. This should be set long enough to hear probe responses 856 * from more than one AP. 857 */ 858 #define IWN_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 859 #define IWN_ACTIVE_DWELL_TIME_5GHZ (20) 860 #define IWN_ACTIVE_DWELL_FACTOR_2GHZ (3) 861 #define IWN_ACTIVE_DWELL_FACTOR_5GHZ (2) 862 863 /* 864 * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. 865 * Must be set longer than active dwell time. 866 * For the most reliable scan, set > AP beacon interval (typically 100msec). 867 */ 868 #define IWN_PASSIVE_DWELL_TIME_2GHZ (20) /* all times in msec */ 869 #define IWN_PASSIVE_DWELL_TIME_5GHZ (10) 870 #define IWN_PASSIVE_DWELL_BASE (100) 871 #define IWN_CHANNEL_TUNE_TIME (5) 872 873 /* 874 * If active scanning is requested but a certain channel is 875 * marked passive, we can do active scanning if we detect 876 * transmissions. 877 * 878 * There is an issue with some firmware versions that triggers 879 * a sysassert on a "good CRC threshold" of zero (== disabled), 880 * on a radar channel even though this means that we should NOT 881 * send probes. 882 * 883 * The "good CRC threshold" is the number of frames that we 884 * need to receive during our dwell time on a channel before 885 * sending out probes -- setting this to a huge value will 886 * mean we never reach it, but at the same time work around 887 * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER 888 * here instead of IWN_GOOD_CRC_TH_DISABLED. 889 * 890 * This was fixed in later versions along with some other 891 * scan changes, and the threshold behaves as a flag in those 892 * versions. 893 */ 894 #define IWN_GOOD_CRC_TH_DISABLED 0 895 #define IWN_GOOD_CRC_TH_DEFAULT htole16(1) 896 #define IWN_GOOD_CRC_TH_NEVER htole16(0xffff) 897 898 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 899 #define IWN_RIDX_MAX 32 900 struct iwn4965_cmd_txpower { 901 uint8_t band; 902 uint8_t reserved1; 903 uint8_t chan; 904 uint8_t reserved2; 905 struct { 906 uint8_t rf_gain[2]; 907 uint8_t dsp_gain[2]; 908 } __packed power[IWN_RIDX_MAX + 1]; 909 } __packed; 910 911 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 912 struct iwn5000_cmd_txpower { 913 int8_t global_limit; /* in half-dBm */ 914 #define IWN5000_TXPOWER_AUTO 0x7f 915 #define IWN5000_TXPOWER_MAX_DBM 16 916 917 uint8_t flags; 918 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 919 920 int8_t srv_limit; /* in half-dBm */ 921 uint8_t reserved; 922 } __packed; 923 924 /* Structures for command IWN_CMD_BLUETOOTH. */ 925 struct iwn_bluetooth { 926 uint8_t flags; 927 #define IWN_BT_COEX_CHAN_ANN (1 << 0) 928 #define IWN_BT_COEX_BT_PRIO (1 << 1) 929 #define IWN_BT_COEX_2_WIRE (1 << 2) 930 931 uint8_t lead_time; 932 #define IWN_BT_LEAD_TIME_DEF 30 933 934 uint8_t max_kill; 935 #define IWN_BT_MAX_KILL_DEF 5 936 937 uint8_t reserved; 938 uint32_t kill_ack; 939 uint32_t kill_cts; 940 } __packed; 941 942 struct iwn6000_btcoex_config { 943 uint8_t flags; 944 #define IWN_BT_COEX6000_CHAN_INHIBITION 1 945 #define IWN_BT_COEX6000_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5)) 946 #define IWN_BT_COEX6000_MODE_SHIFT 3 947 #define IWN_BT_COEX6000_MODE_DISABLED 0 948 #define IWN_BT_COEX6000_MODE_LEGACY_2W 1 949 #define IWN_BT_COEX6000_MODE_3W 2 950 #define IWN_BT_COEX6000_MODE_4W 3 951 #define IWN_BT_UCODE_DEFAULT (1<<6) 952 #define IWN_BT_SYNC_2_BT_DISABLE (1<<7) 953 954 uint8_t lead_time; 955 uint8_t max_kill; 956 uint8_t bt3_t7_timer; 957 uint32_t kill_ack; 958 uint32_t kill_cts; 959 uint8_t sample_time; 960 uint8_t bt3_t2_timer; 961 uint16_t bt4_reaction; 962 uint32_t lookup_table[12]; 963 uint16_t bt4_decision; 964 uint16_t valid; 965 uint8_t prio_boost; 966 uint8_t tx_prio_boost; 967 uint16_t rx_prio_boost; 968 } __packed; 969 970 struct iwn2000_btcoex_config { 971 uint8_t flags; /* same as in iwn6000_btcoex_config */ 972 uint8_t lead_time; 973 uint8_t max_kill; 974 uint8_t bt3_t7_timer; 975 uint32_t kill_ack; 976 uint32_t kill_cts; 977 uint8_t sample_time; 978 uint8_t bt3_t2_timer; 979 uint16_t bt4_reaction; 980 uint32_t lookup_table[12]; 981 uint16_t bt4_decision; 982 uint16_t valid; 983 uint32_t prio_boost; 984 uint8_t reserved; 985 uint8_t tx_prio_boost; 986 uint16_t rx_prio_boost; 987 } __packed; 988 989 /* Structure for command IWN_CMD_BT_COEX_PRIOTABLE */ 990 struct iwn_btcoex_priotable { 991 uint8_t calib_init1; 992 uint8_t calib_init2; 993 uint8_t calib_periodic_low1; 994 uint8_t calib_periodic_low2; 995 uint8_t calib_periodic_high1; 996 uint8_t calib_periodic_high2; 997 uint8_t dtim; 998 uint8_t scan52; 999 uint8_t scan24; 1000 uint8_t reserved[7]; 1001 } __packed; 1002 1003 /* Structure for command IWN_CMD_BT_COEX_PROT */ 1004 struct iwn_btcoex_prot { 1005 uint8_t open; 1006 uint8_t type; 1007 uint8_t reserved[2]; 1008 } __packed; 1009 1010 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 1011 struct iwn_critical_temp { 1012 uint32_t reserved; 1013 uint32_t tempM; 1014 uint32_t tempR; 1015 /* degK <-> degC conversion macros. */ 1016 #define IWN_CTOK(c) ((c) + 273) 1017 #define IWN_KTOC(k) ((k) - 273) 1018 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 1019 } __packed; 1020 1021 /* Structures for command IWN_CMD_SET_SENSITIVITY. */ 1022 struct iwn_sensitivity_cmd { 1023 uint16_t which; 1024 #define IWN_SENSITIVITY_DEFAULTTBL 0 1025 #define IWN_SENSITIVITY_WORKTBL 1 1026 1027 uint16_t energy_cck; 1028 uint16_t energy_ofdm; 1029 uint16_t corr_ofdm_x1; 1030 uint16_t corr_ofdm_mrc_x1; 1031 uint16_t corr_cck_mrc_x4; 1032 uint16_t corr_ofdm_x4; 1033 uint16_t corr_ofdm_mrc_x4; 1034 uint16_t corr_barker; 1035 uint16_t corr_barker_mrc; 1036 uint16_t corr_cck_x4; 1037 uint16_t energy_ofdm_th; 1038 } __packed; 1039 1040 struct iwn_enhanced_sensitivity_cmd { 1041 uint16_t which; 1042 uint16_t energy_cck; 1043 uint16_t energy_ofdm; 1044 uint16_t corr_ofdm_x1; 1045 uint16_t corr_ofdm_mrc_x1; 1046 uint16_t corr_cck_mrc_x4; 1047 uint16_t corr_ofdm_x4; 1048 uint16_t corr_ofdm_mrc_x4; 1049 uint16_t corr_barker; 1050 uint16_t corr_barker_mrc; 1051 uint16_t corr_cck_x4; 1052 uint16_t energy_ofdm_th; 1053 /* "Enhanced" part. */ 1054 uint16_t ina_det_ofdm; 1055 uint16_t ina_det_cck; 1056 uint16_t corr_11_9_en; 1057 uint16_t ofdm_det_slope_mrc; 1058 uint16_t ofdm_det_icept_mrc; 1059 uint16_t ofdm_det_slope; 1060 uint16_t ofdm_det_icept; 1061 uint16_t cck_det_slope_mrc; 1062 uint16_t cck_det_icept_mrc; 1063 uint16_t cck_det_slope; 1064 uint16_t cck_det_icept; 1065 uint16_t reserved; 1066 } __packed; 1067 1068 /* Structures for command IWN_CMD_PHY_CALIB. */ 1069 struct iwn_phy_calib { 1070 uint8_t code; 1071 #define IWN4965_PHY_CALIB_DIFF_GAIN 7 1072 #define IWN5000_PHY_CALIB_DC 8 1073 #define IWN5000_PHY_CALIB_LO 9 1074 #define IWN5000_PHY_CALIB_TX_IQ 11 1075 #define IWN5000_PHY_CALIB_CRYSTAL 15 1076 #define IWN5000_PHY_CALIB_BASE_BAND 16 1077 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 1078 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 1079 #define IWN5000_PHY_CALIB_NOISE_GAIN 19 1080 1081 #define IWN6000_PHY_CALIB_TEMP_OFFSET 18 1082 #define IWN2000_PHY_CALIB_TEMP_OFFSET 18 1083 1084 #define IWN5000_PHY_CALIB_MAX 253 1085 1086 uint8_t group; 1087 uint8_t ngroups; 1088 uint8_t isvalid; 1089 } __packed; 1090 1091 struct iwn5000_phy_calib_crystal { 1092 uint8_t code; 1093 uint8_t group; 1094 uint8_t ngroups; 1095 uint8_t isvalid; 1096 1097 uint8_t cap_pin[2]; 1098 uint8_t reserved[2]; 1099 } __packed; 1100 1101 struct iwn6000_phy_calib_temp_offset { 1102 uint8_t code; 1103 uint8_t group; 1104 uint8_t ngroups; 1105 uint8_t isvalid; 1106 int16_t offset; 1107 #define IWN_DEFAULT_TEMP_OFFSET 2700 1108 1109 uint16_t reserved; 1110 } __packed; 1111 1112 struct iwn2000_phy_calib_temp_offset { 1113 uint8_t code; 1114 uint8_t group; 1115 uint8_t ngroups; 1116 uint8_t isvalid; 1117 int16_t offset_high; 1118 int16_t offset_low; 1119 int16_t burnt_voltage_ref; 1120 int16_t reserved; 1121 } __packed; 1122 1123 struct iwn_phy_calib_gain { 1124 uint8_t code; 1125 uint8_t group; 1126 uint8_t ngroups; 1127 uint8_t isvalid; 1128 1129 int8_t gain[3]; 1130 uint8_t reserved; 1131 } __packed; 1132 1133 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1134 struct iwn_spectrum_cmd { 1135 uint16_t len; 1136 uint8_t token; 1137 uint8_t id; 1138 uint8_t origin; 1139 uint8_t periodic; 1140 uint16_t timeout; 1141 uint32_t start; 1142 uint32_t reserved1; 1143 uint32_t flags; 1144 uint32_t filter; 1145 uint16_t nchan; 1146 uint16_t reserved2; 1147 struct { 1148 uint32_t duration; 1149 uint8_t chan; 1150 uint8_t type; 1151 #define IWN_MEASUREMENT_BASIC (1 << 0) 1152 #define IWN_MEASUREMENT_CCA (1 << 1) 1153 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1154 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1155 #define IWN_MEASUREMENT_FRAME (1 << 4) 1156 #define IWN_MEASUREMENT_IDLE (1 << 7) 1157 1158 uint16_t reserved; 1159 } __packed chan[10]; 1160 } __packed; 1161 1162 /* Structure for IWN_UC_READY notification. */ 1163 #define IWN_NATTEN_GROUPS 5 1164 struct iwn_ucode_info { 1165 uint8_t minor; 1166 uint8_t major; 1167 uint16_t reserved1; 1168 uint8_t revision[8]; 1169 uint8_t type; 1170 uint8_t subtype; 1171 #define IWN_UCODE_RUNTIME 0 1172 #define IWN_UCODE_INIT 9 1173 1174 uint16_t reserved2; 1175 uint32_t logptr; 1176 uint32_t errptr; 1177 uint32_t tstamp; 1178 uint32_t valid; 1179 1180 /* The following fields are for UCODE_INIT only. */ 1181 int32_t volt; 1182 struct { 1183 int32_t chan20MHz; 1184 int32_t chan40MHz; 1185 } __packed temp[4]; 1186 int32_t atten[IWN_NATTEN_GROUPS][2]; 1187 } __packed; 1188 1189 /* Structures for IWN_TX_DONE notification. */ 1190 struct iwn4965_tx_stat { 1191 uint8_t nframes; 1192 uint8_t btkillcnt; 1193 uint8_t rtsfailcnt; 1194 uint8_t ackfailcnt; 1195 uint8_t rate; 1196 uint8_t rflags; 1197 uint16_t xrflags; 1198 uint16_t duration; 1199 uint16_t reserved; 1200 uint32_t power[2]; 1201 uint32_t status; 1202 } __packed; 1203 1204 struct iwn5000_tx_stat { 1205 uint8_t nframes; 1206 uint8_t btkillcnt; 1207 uint8_t rtsfailcnt; 1208 uint8_t ackfailcnt; 1209 uint8_t rate; 1210 uint8_t rflags; 1211 uint16_t xrflags; 1212 uint16_t duration; 1213 uint16_t reserved; 1214 uint32_t power[2]; 1215 uint32_t info; 1216 uint16_t seq; 1217 uint16_t len; 1218 uint8_t tlc; 1219 uint8_t ratid; 1220 uint8_t fc[2]; 1221 uint16_t status; 1222 uint16_t sequence; 1223 } __packed; 1224 1225 /* Structure for IWN_BEACON_MISSED notification. */ 1226 struct iwn_beacon_missed { 1227 uint32_t consecutive; 1228 uint32_t total; 1229 uint32_t expected; 1230 uint32_t received; 1231 } __packed; 1232 1233 /* Structure for IWN_MPDU_RX_DONE notification. */ 1234 struct iwn_rx_mpdu { 1235 uint16_t len; 1236 uint16_t reserved; 1237 } __packed; 1238 1239 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1240 struct iwn4965_rx_phystat { 1241 uint16_t antenna; 1242 uint16_t agc; 1243 uint8_t rssi[6]; 1244 } __packed; 1245 1246 struct iwn5000_rx_phystat { 1247 uint32_t reserved1; 1248 uint32_t agc; 1249 uint16_t rssi[3]; 1250 } __packed; 1251 1252 struct iwn_rx_stat { 1253 uint8_t phy_len; 1254 uint8_t cfg_phy_len; 1255 #define IWN_STAT_MAXLEN 20 1256 1257 uint8_t id; 1258 uint8_t reserved1; 1259 uint64_t tstamp; 1260 uint32_t beacon; 1261 uint16_t flags; 1262 #define IWN_STAT_FLAG_24GHZ (1 << 0) 1263 #define IWN_STAT_FLAG_MOD_CCK (1 << 1) 1264 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1265 #define IWN_STAT_FLAG_NARROW_BAND (1 << 3) 1266 #define IWN_STAT_FLAG_ANT(x) ((x) << 4) /* 3 bits */ 1267 #define IWN_STAT_FLAG_AGG (1 << 7) 1268 1269 uint16_t chan; 1270 uint8_t phybuf[32]; 1271 uint8_t rate; 1272 uint8_t rflags; 1273 uint16_t xrflags; 1274 uint16_t len; 1275 uint16_t reserve3; 1276 } __packed; 1277 1278 #define IWN_RSSI_TO_DBM 44 1279 1280 /* Structure for IWN_RX_COMPRESSED_BA notification. */ 1281 struct iwn_compressed_ba { 1282 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1283 uint16_t reserved; 1284 uint8_t id; 1285 uint8_t tid; 1286 uint16_t seq; 1287 uint64_t bitmap; 1288 uint16_t qid; 1289 uint16_t ssn; 1290 } __packed; 1291 1292 /* Structure for IWN_START_SCAN notification. */ 1293 struct iwn_start_scan { 1294 uint64_t tstamp; 1295 uint32_t tbeacon; 1296 uint8_t chan; 1297 uint8_t band; 1298 uint16_t reserved; 1299 uint32_t status; 1300 } __packed; 1301 1302 /* Structure for IWN_STOP_SCAN notification. */ 1303 struct iwn_stop_scan { 1304 uint8_t nchan; 1305 uint8_t status; 1306 uint8_t reserved; 1307 uint8_t chan; 1308 uint64_t tsf; 1309 } __packed; 1310 1311 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1312 struct iwn_spectrum_notif { 1313 uint8_t id; 1314 uint8_t token; 1315 uint8_t idx; 1316 uint8_t state; 1317 #define IWN_MEASUREMENT_START 0 1318 #define IWN_MEASUREMENT_STOP 1 1319 1320 uint32_t start; 1321 uint8_t band; 1322 uint8_t chan; 1323 uint8_t type; 1324 uint8_t reserved1; 1325 uint32_t cca_ofdm; 1326 uint32_t cca_cck; 1327 uint32_t cca_time; 1328 uint8_t basic; 1329 uint8_t reserved2[3]; 1330 uint32_t ofdm[8]; 1331 uint32_t cck[8]; 1332 uint32_t stop; 1333 uint32_t status; 1334 #define IWN_MEASUREMENT_OK 0 1335 #define IWN_MEASUREMENT_CONCURRENT 1 1336 #define IWN_MEASUREMENT_CSA_CONFLICT 2 1337 #define IWN_MEASUREMENT_TGH_CONFLICT 3 1338 #define IWN_MEASUREMENT_STOPPED 6 1339 #define IWN_MEASUREMENT_TIMEOUT 7 1340 #define IWN_MEASUREMENT_FAILED 8 1341 } __packed; 1342 1343 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1344 struct iwn_rx_phy_stats { 1345 uint32_t ina; 1346 uint32_t fina; 1347 uint32_t bad_plcp; 1348 uint32_t bad_crc32; 1349 uint32_t overrun; 1350 uint32_t eoverrun; 1351 uint32_t good_crc32; 1352 uint32_t fa; 1353 uint32_t bad_fina_sync; 1354 uint32_t sfd_timeout; 1355 uint32_t fina_timeout; 1356 uint32_t no_rts_ack; 1357 uint32_t rxe_limit; 1358 uint32_t ack; 1359 uint32_t cts; 1360 uint32_t ba_resp; 1361 uint32_t dsp_kill; 1362 uint32_t bad_mh; 1363 uint32_t rssi_sum; 1364 uint32_t reserved; 1365 } __packed; 1366 1367 struct iwn_rx_general_stats { 1368 uint32_t bad_cts; 1369 uint32_t bad_ack; 1370 uint32_t not_bss; 1371 uint32_t filtered; 1372 uint32_t bad_chan; 1373 uint32_t beacons; 1374 uint32_t missed_beacons; 1375 uint32_t adc_saturated; /* time in 0.8us */ 1376 uint32_t ina_searched; /* time in 0.8us */ 1377 uint32_t noise[3]; 1378 uint32_t flags; 1379 uint32_t load; 1380 uint32_t fa; 1381 uint32_t rssi[3]; 1382 uint32_t energy[3]; 1383 } __packed; 1384 1385 struct iwn_rx_ht_phy_stats { 1386 uint32_t bad_plcp; 1387 uint32_t overrun; 1388 uint32_t eoverrun; 1389 uint32_t good_crc32; 1390 uint32_t bad_crc32; 1391 uint32_t bad_mh; 1392 uint32_t good_ampdu_crc32; 1393 uint32_t ampdu; 1394 uint32_t fragment; 1395 uint32_t reserved; 1396 } __packed; 1397 1398 struct iwn_rx_stats { 1399 struct iwn_rx_phy_stats ofdm; 1400 struct iwn_rx_phy_stats cck; 1401 struct iwn_rx_general_stats general; 1402 struct iwn_rx_ht_phy_stats ht; 1403 } __packed; 1404 1405 struct iwn_tx_stats { 1406 uint32_t preamble; 1407 uint32_t rx_detected; 1408 uint32_t bt_defer; 1409 uint32_t bt_kill; 1410 uint32_t short_len; 1411 uint32_t cts_timeout; 1412 uint32_t ack_timeout; 1413 uint32_t exp_ack; 1414 uint32_t ack; 1415 uint32_t msdu; 1416 uint32_t busrt_err1; 1417 uint32_t burst_err2; 1418 uint32_t cts_collision; 1419 uint32_t ack_collision; 1420 uint32_t ba_timeout; 1421 uint32_t ba_resched; 1422 uint32_t query_ampdu; 1423 uint32_t query; 1424 uint32_t query_ampdu_frag; 1425 uint32_t query_mismatch; 1426 uint32_t not_ready; 1427 uint32_t underrun; 1428 uint32_t bt_ht_kill; 1429 uint32_t rx_ba_resp; 1430 uint32_t reserved[2]; 1431 } __packed; 1432 1433 struct iwn_general_stats { 1434 uint32_t temp; 1435 uint32_t temp_m; 1436 uint32_t burst_check; 1437 uint32_t burst; 1438 uint32_t reserved1[4]; 1439 uint32_t sleep; 1440 uint32_t slot_out; 1441 uint32_t slot_idle; 1442 uint32_t ttl_tstamp; 1443 uint32_t tx_ant_a; 1444 uint32_t tx_ant_b; 1445 uint32_t exec; 1446 uint32_t probe; 1447 uint32_t reserved2[2]; 1448 uint32_t rx_enabled; 1449 uint32_t reserved3[3]; 1450 } __packed; 1451 1452 struct iwn_stats { 1453 uint32_t flags; 1454 struct iwn_rx_stats rx; 1455 struct iwn_tx_stats tx; 1456 struct iwn_general_stats general; 1457 } __packed; 1458 1459 1460 /* Firmware error dump. */ 1461 struct iwn_fw_dump { 1462 uint32_t valid; 1463 uint32_t id; 1464 uint32_t pc; 1465 uint32_t branch_link[2]; 1466 uint32_t interrupt_link[2]; 1467 uint32_t error_data[2]; 1468 uint32_t src_line; 1469 uint32_t tsf; 1470 uint32_t time[2]; 1471 } __packed; 1472 1473 /* TLV firmware header. */ 1474 struct iwn_fw_tlv_hdr { 1475 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1476 uint32_t signature; 1477 #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1478 1479 uint8_t descr[64]; 1480 uint32_t rev; 1481 #define IWN_FW_API(x) (((x) >> 8) & 0xff) 1482 1483 uint32_t build; 1484 uint64_t altmask; 1485 } __packed; 1486 1487 /* TLV header. */ 1488 struct iwn_fw_tlv { 1489 uint16_t type; 1490 #define IWN_FW_TLV_MAIN_TEXT 1 1491 #define IWN_FW_TLV_MAIN_DATA 2 1492 #define IWN_FW_TLV_INIT_TEXT 3 1493 #define IWN_FW_TLV_INIT_DATA 4 1494 #define IWN_FW_TLV_BOOT_TEXT 5 1495 #define IWN_FW_TLV_PBREQ_MAXLEN 6 1496 #define IWN_FW_TLV_ENH_SENS 14 1497 #define IWN_FW_TLV_PHY_CALIB 15 1498 #define IWN_FW_TLV_FLAGS 18 1499 1500 uint16_t alt; 1501 uint32_t len; 1502 } __packed; 1503 1504 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1505 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1506 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1507 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1508 #define IWN_FW_BOOT_TEXT_MAXSZ 1024 1509 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1510 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1511 1512 /* 1513 * Microcode flags TLV (18.) 1514 */ 1515 1516 /** 1517 * enum iwn_ucode_tlv_flag - ucode API flags 1518 * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 1519 * was a separate TLV but moved here to save space. 1520 * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 1521 * treats good CRC threshold as a boolean 1522 * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 1523 * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 1524 * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 1525 * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 1526 * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 1527 * offload profile config command. 1528 * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 1529 * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 1530 * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 1531 * (rather than two) IPv6 addresses 1532 * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 1533 * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 1534 * from the probe request template. 1535 * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 1536 * connection when going back to D0 1537 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 1538 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 1539 * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 1540 * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 1541 * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 1542 * containing CAM (Continuous Active Mode) indication. 1543 */ 1544 enum iwn_ucode_tlv_flag { 1545 IWN_UCODE_TLV_FLAGS_PAN = (1 << 0), 1546 IWN_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 1547 IWN_UCODE_TLV_FLAGS_MFP = (1 << 2), 1548 IWN_UCODE_TLV_FLAGS_P2P = (1 << 3), 1549 IWN_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 1550 IWN_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 1551 IWN_UCODE_TLV_FLAGS_UAPSD = (1 << 6), 1552 IWN_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 1553 IWN_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 1554 IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 1555 IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 1556 IWN_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 1557 IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 1558 IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 1559 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 1560 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 1561 IWN_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 1562 IWN_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 1563 IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 1564 }; 1565 1566 /* 1567 * Offsets into EEPROM. 1568 */ 1569 #define IWN_EEPROM_MAC 0x015 1570 #define IWN_EEPROM_SKU_CAP 0x045 1571 #define IWN_EEPROM_RFCFG 0x048 1572 #define IWN4965_EEPROM_DOMAIN 0x060 1573 #define IWN4965_EEPROM_BAND1 0x063 1574 #define IWN5000_EEPROM_REG 0x066 1575 #define IWN5000_EEPROM_CAL 0x067 1576 #define IWN4965_EEPROM_BAND2 0x072 1577 #define IWN4965_EEPROM_BAND3 0x080 1578 #define IWN4965_EEPROM_BAND4 0x08d 1579 #define IWN4965_EEPROM_BAND5 0x099 1580 #define IWN4965_EEPROM_BAND6 0x0a0 1581 #define IWN4965_EEPROM_BAND7 0x0a8 1582 #define IWN4965_EEPROM_MAXPOW 0x0e8 1583 #define IWN4965_EEPROM_VOLTAGE 0x0e9 1584 #define IWN4965_EEPROM_BANDS 0x0ea 1585 /* Indirect offsets. */ 1586 #define IWN5000_EEPROM_DOMAIN 0x001 1587 #define IWN5000_EEPROM_BAND1 0x004 1588 #define IWN5000_EEPROM_BAND2 0x013 1589 #define IWN5000_EEPROM_BAND3 0x021 1590 #define IWN5000_EEPROM_BAND4 0x02e 1591 #define IWN5000_EEPROM_BAND5 0x03a 1592 #define IWN5000_EEPROM_BAND6 0x041 1593 #define IWN5000_EEPROM_BAND7 0x049 1594 #define IWN6000_EEPROM_ENHINFO 0x054 1595 #define IWN5000_EEPROM_CRYSTAL 0x128 1596 #define IWN5000_EEPROM_TEMP 0x12a 1597 #define IWN5000_EEPROM_VOLT 0x12b 1598 #define IWN2000_EEPROM_RAWTEMP 0x12b 1599 1600 /* Possible flags for IWN_EEPROM_SKU_CAP. */ 1601 #define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1602 #define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1603 #define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1604 1605 /* Possible flags for IWN_EEPROM_RFCFG. */ 1606 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1607 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1608 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1609 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1610 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1611 1612 struct iwn_eeprom_chan { 1613 uint8_t flags; 1614 #define IWN_EEPROM_CHAN_VALID (1 << 0) 1615 #define IWN_EEPROM_CHAN_IBSS (1 << 1) 1616 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1617 #define IWN_EEPROM_CHAN_RADAR (1 << 4) 1618 1619 int8_t maxpwr; 1620 } __packed; 1621 1622 struct iwn_eeprom_enhinfo { 1623 uint16_t chan; 1624 int8_t chain[3]; /* max power in half-dBm */ 1625 uint8_t reserved; 1626 int8_t mimo2; /* max power in half-dBm */ 1627 int8_t mimo3; /* max power in half-dBm */ 1628 } __packed; 1629 1630 struct iwn5000_eeprom_calib_hdr { 1631 uint8_t version; 1632 uint8_t pa_type; 1633 uint16_t volt; 1634 } __packed; 1635 1636 #define IWN_NSAMPLES 3 1637 struct iwn4965_eeprom_chan_samples { 1638 uint8_t num; 1639 struct { 1640 uint8_t temp; 1641 uint8_t gain; 1642 uint8_t power; 1643 int8_t pa_det; 1644 } samples[2][IWN_NSAMPLES]; 1645 } __packed; 1646 1647 #define IWN_NBANDS 8 1648 struct iwn4965_eeprom_band { 1649 uint8_t lo; /* low channel number */ 1650 uint8_t hi; /* high channel number */ 1651 struct iwn4965_eeprom_chan_samples chans[2]; 1652 } __packed; 1653 1654 /* 1655 * Offsets of channels descriptions in EEPROM. 1656 */ 1657 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1658 IWN4965_EEPROM_BAND1, 1659 IWN4965_EEPROM_BAND2, 1660 IWN4965_EEPROM_BAND3, 1661 IWN4965_EEPROM_BAND4, 1662 IWN4965_EEPROM_BAND5, 1663 IWN4965_EEPROM_BAND6, 1664 IWN4965_EEPROM_BAND7 1665 }; 1666 1667 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1668 IWN5000_EEPROM_BAND1, 1669 IWN5000_EEPROM_BAND2, 1670 IWN5000_EEPROM_BAND3, 1671 IWN5000_EEPROM_BAND4, 1672 IWN5000_EEPROM_BAND5, 1673 IWN5000_EEPROM_BAND6, 1674 IWN5000_EEPROM_BAND7 1675 }; 1676 1677 #define IWN_CHAN_BANDS_COUNT 7 1678 #define IWN_MAX_CHAN_PER_BAND 14 1679 static const struct iwn_chan_band { 1680 uint8_t nchan; 1681 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1682 } iwn_bands[] = { 1683 /* 20MHz channels, 2GHz band. */ 1684 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1685 /* 20MHz channels, 5GHz band. */ 1686 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1687 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1688 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1689 { 6, { 145, 149, 153, 157, 161, 165 } }, 1690 /* 40MHz channels (primary channels), 2GHz band. */ 1691 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1692 /* 40MHz channels (primary channels), 5GHz band. */ 1693 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1694 }; 1695 1696 #define IWN1000_OTP_NBLOCKS 3 1697 #define IWN6000_OTP_NBLOCKS 4 1698 #define IWN6050_OTP_NBLOCKS 7 1699 1700 /* HW rate indices. */ 1701 #define IWN_RIDX_CCK1 0 1702 #define IWN_RIDX_OFDM6 4 1703 1704 #define IWN_PLCP_INVALID 0xff 1705 1706 static const struct iwn_rate { 1707 uint8_t rate; 1708 uint8_t plcp; 1709 uint8_t flags; 1710 uint8_t ht_plcp; 1711 uint8_t ht_flags; 1712 } iwn_rates[IWN_RIDX_MAX + 1] = { 1713 /* Legacy */ /* HT */ 1714 { 2, 10, IWN_RFLAG_CCK, IWN_PLCP_INVALID, 0 }, 1715 { 4, 20, IWN_RFLAG_CCK, IWN_PLCP_INVALID, 0 }, 1716 { 11, 55, IWN_RFLAG_CCK, IWN_PLCP_INVALID, 0 }, 1717 { 22, 110, IWN_RFLAG_CCK, IWN_PLCP_INVALID, 0 }, 1718 { 12, 0xd, 0, 0, IWN_RFLAG_MCS }, 1719 { 18, 0xf, 0, IWN_PLCP_INVALID, 0 }, 1720 { 24, 0x5, 0, 1, IWN_RFLAG_MCS }, 1721 { 36, 0x7, 0, 2, IWN_RFLAG_MCS, }, 1722 { 48, 0x9, 0, 3, IWN_RFLAG_MCS, }, 1723 { 72, 0xb, 0, 4, IWN_RFLAG_MCS, }, 1724 { 96, 0x1, 0, 5, IWN_RFLAG_MCS, }, 1725 { 108, 0x3, 0, 6, IWN_RFLAG_MCS, }, 1726 { 128, IWN_PLCP_INVALID, 0, 7, IWN_RFLAG_MCS, } 1727 }; 1728 1729 /* Convert an MCS index into an iwn_rates[] index. */ 1730 const int iwn_mcs2ridx[] = { 4, 6, 7, 8, 9, 10, 11, 12 }; 1731 1732 #define IWN4965_MAX_PWR_INDEX 107 1733 1734 /* 1735 * RF Tx gain values from highest to lowest power (values obtained from 1736 * the reference driver.) 1737 */ 1738 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1739 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1740 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1741 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1742 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1743 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1744 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1745 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1746 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1747 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1748 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1749 }; 1750 1751 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1752 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1753 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1754 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1755 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1756 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1757 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1758 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1759 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1760 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1761 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1762 }; 1763 1764 /* 1765 * DSP pre-DAC gain values from highest to lowest power (values obtained 1766 * from the reference driver.) 1767 */ 1768 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1769 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1770 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1771 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1772 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1773 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1774 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1775 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1776 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1777 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1778 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1779 }; 1780 1781 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1782 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1783 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1784 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1785 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1786 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1787 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1788 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1789 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1790 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1791 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1792 }; 1793 1794 /* 1795 * Power saving settings (values obtained from the reference driver.) 1796 */ 1797 #define IWN_NDTIMRANGES 3 1798 #define IWN_NPOWERLEVELS 6 1799 static const struct iwn_pmgt { 1800 uint32_t rxtimeout; 1801 uint32_t txtimeout; 1802 uint32_t intval[5]; 1803 int skip_dtim; 1804 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1805 /* DTIM <= 2 */ 1806 { 1807 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1808 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1809 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1810 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1811 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1812 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1813 }, 1814 /* 3 <= DTIM <= 10 */ 1815 { 1816 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1817 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1818 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1819 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1820 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1821 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1822 }, 1823 /* DTIM >= 11 */ 1824 { 1825 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1826 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1827 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1828 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1829 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1830 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1831 } 1832 }; 1833 1834 struct iwn_sensitivity_limits { 1835 uint32_t min_ofdm_x1; 1836 uint32_t max_ofdm_x1; 1837 uint32_t min_ofdm_mrc_x1; 1838 uint32_t max_ofdm_mrc_x1; 1839 uint32_t min_ofdm_x4; 1840 uint32_t max_ofdm_x4; 1841 uint32_t min_ofdm_mrc_x4; 1842 uint32_t max_ofdm_mrc_x4; 1843 uint32_t min_cck_x4; 1844 uint32_t max_cck_x4; 1845 uint32_t min_cck_mrc_x4; 1846 uint32_t max_cck_mrc_x4; 1847 uint32_t min_energy_cck; 1848 uint32_t energy_cck; 1849 uint32_t energy_ofdm; 1850 }; 1851 1852 /* 1853 * RX sensitivity limits (values obtained from the reference driver.) 1854 */ 1855 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1856 105, 140, 1857 220, 270, 1858 85, 120, 1859 170, 210, 1860 125, 200, 1861 200, 400, 1862 97, 1863 100, 1864 100 1865 }; 1866 1867 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1868 120, 120, /* min = max for performance bug in DSP. */ 1869 240, 240, /* min = max for performance bug in DSP. */ 1870 90, 120, 1871 170, 210, 1872 125, 200, 1873 170, 400, 1874 95, 1875 95, 1876 95 1877 }; 1878 1879 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1880 105, 105, /* min = max for performance bug in DSP. */ 1881 220, 220, /* min = max for performance bug in DSP. */ 1882 90, 120, 1883 170, 210, 1884 125, 200, 1885 170, 400, 1886 95, 1887 95, 1888 95 1889 }; 1890 1891 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1892 120, 155, 1893 240, 290, 1894 90, 120, 1895 170, 210, 1896 125, 200, 1897 170, 400, 1898 95, 1899 95, 1900 95 1901 }; 1902 1903 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1904 105, 110, 1905 192, 232, 1906 80, 145, 1907 128, 232, 1908 125, 175, 1909 160, 310, 1910 97, 1911 97, 1912 100 1913 }; 1914 1915 static const struct iwn_sensitivity_limits iwn2000_sensitivity_limits = { 1916 105, 110, 1917 192, 232, 1918 80, 145, 1919 128, 232, 1920 125, 175, 1921 160, 310, 1922 97, 1923 97, 1924 100 1925 }; 1926 1927 /* Map TID to TX scheduler's FIFO. */ 1928 static const uint8_t iwn_tid2fifo[] = { 1929 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1930 }; 1931 1932 /* WiFi/WiMAX coexist event priority table for 6050. */ 1933 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1934 { 0x04, 0x03, 0x00, 0x00 }, 1935 { 0x04, 0x03, 0x00, 0x03 }, 1936 { 0x04, 0x03, 0x00, 0x03 }, 1937 { 0x04, 0x03, 0x00, 0x03 }, 1938 { 0x04, 0x03, 0x00, 0x00 }, 1939 { 0x04, 0x03, 0x00, 0x07 }, 1940 { 0x04, 0x03, 0x00, 0x00 }, 1941 { 0x04, 0x03, 0x00, 0x03 }, 1942 { 0x04, 0x03, 0x00, 0x03 }, 1943 { 0x04, 0x03, 0x00, 0x00 }, 1944 { 0x06, 0x03, 0x00, 0x07 }, 1945 { 0x04, 0x03, 0x00, 0x00 }, 1946 { 0x06, 0x06, 0x00, 0x03 }, 1947 { 0x04, 0x03, 0x00, 0x07 }, 1948 { 0x04, 0x03, 0x00, 0x00 }, 1949 { 0x04, 0x03, 0x00, 0x00 } 1950 }; 1951 1952 /* Firmware errors. */ 1953 static const char * const iwn_fw_errmsg[] = { 1954 "OK", 1955 "FAIL", 1956 "BAD_PARAM", 1957 "BAD_CHECKSUM", 1958 "NMI_INTERRUPT_WDG", 1959 "SYSASSERT", 1960 "FATAL_ERROR", 1961 "BAD_COMMAND", 1962 "HW_ERROR_TUNE_LOCK", 1963 "HW_ERROR_TEMPERATURE", 1964 "ILLEGAL_CHAN_FREQ", 1965 "VCC_NOT_STABLE", 1966 "FH_ERROR", 1967 "NMI_INTERRUPT_HOST", 1968 "NMI_INTERRUPT_ACTION_PT", 1969 "NMI_INTERRUPT_UNKNOWN", 1970 "UCODE_VERSION_MISMATCH", 1971 "HW_ERROR_ABS_LOCK", 1972 "HW_ERROR_CAL_LOCK_FAIL", 1973 "NMI_INTERRUPT_INST_ACTION_PT", 1974 "NMI_INTERRUPT_DATA_ACTION_PT", 1975 "NMI_TRM_HW_ER", 1976 "NMI_INTERRUPT_TRM", 1977 "NMI_INTERRUPT_BREAKPOINT" 1978 "DEBUG_0", 1979 "DEBUG_1", 1980 "DEBUG_2", 1981 "DEBUG_3", 1982 "ADVANCED_SYSASSERT" 1983 }; 1984 1985 /* Find least significant bit that is set. */ 1986 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1987 1988 #define IWN_READ(sc, reg) \ 1989 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1990 1991 #define IWN_WRITE(sc, reg, val) \ 1992 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1993 1994 #define IWN_WRITE_1(sc, reg, val) \ 1995 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1996 1997 #define IWN_SETBITS(sc, reg, mask) \ 1998 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1999 2000 #define IWN_CLRBITS(sc, reg, mask) \ 2001 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 2002 2003 #define IWN_BARRIER_WRITE(sc) \ 2004 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2005 BUS_SPACE_BARRIER_WRITE) 2006 2007 #define IWN_BARRIER_READ_WRITE(sc) \ 2008 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2009 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 2010