1 /* $OpenBSD: if_iwn.c,v 1.221 2019/11/06 14:52:35 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 21 * adapters. 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/mbuf.h> 29 #include <sys/kernel.h> 30 #include <sys/rwlock.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/conf.h> 35 #include <sys/device.h> 36 #include <sys/task.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 46 #if NBPFILTER > 0 47 #include <net/bpf.h> 48 #endif 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 53 #include <netinet/in.h> 54 #include <netinet/if_ether.h> 55 56 #include <net80211/ieee80211_var.h> 57 #include <net80211/ieee80211_amrr.h> 58 #include <net80211/ieee80211_mira.h> 59 #include <net80211/ieee80211_radiotap.h> 60 #include <net80211/ieee80211_priv.h> /* for SEQ_LT */ 61 #undef DPRINTF /* defined in ieee80211_priv.h */ 62 63 #include <dev/pci/if_iwnreg.h> 64 #include <dev/pci/if_iwnvar.h> 65 66 static const struct pci_matchid iwn_devices[] = { 67 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_4965_1 }, 68 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_4965_2 }, 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5100_1 }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5100_2 }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5150_1 }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5150_2 }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5300_1 }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5300_2 }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5350_1 }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5350_2 }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1000_1 }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1000_2 }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6300_1 }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6300_2 }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6200_1 }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6200_2 }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6050_1 }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6050_2 }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6005_1 }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6005_2 }, 87 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6030_1 }, 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6030_2 }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1030_1 }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1030_2 }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_100_1 }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_100_2 }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_130_1 }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_130_2 }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6235_1 }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6235_2 }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2230_1 }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2230_2 }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2200_1 }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2200_2 }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_135_1 }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_135_2 }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_105_1 }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_105_2 }, 105 }; 106 107 int iwn_match(struct device *, void *, void *); 108 void iwn_attach(struct device *, struct device *, void *); 109 int iwn4965_attach(struct iwn_softc *, pci_product_id_t); 110 int iwn5000_attach(struct iwn_softc *, pci_product_id_t); 111 #if NBPFILTER > 0 112 void iwn_radiotap_attach(struct iwn_softc *); 113 #endif 114 int iwn_detach(struct device *, int); 115 int iwn_activate(struct device *, int); 116 void iwn_wakeup(struct iwn_softc *); 117 void iwn_init_task(void *); 118 int iwn_nic_lock(struct iwn_softc *); 119 int iwn_eeprom_lock(struct iwn_softc *); 120 int iwn_init_otprom(struct iwn_softc *); 121 int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 122 int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 123 void **, bus_size_t, bus_size_t); 124 void iwn_dma_contig_free(struct iwn_dma_info *); 125 int iwn_alloc_sched(struct iwn_softc *); 126 void iwn_free_sched(struct iwn_softc *); 127 int iwn_alloc_kw(struct iwn_softc *); 128 void iwn_free_kw(struct iwn_softc *); 129 int iwn_alloc_ict(struct iwn_softc *); 130 void iwn_free_ict(struct iwn_softc *); 131 int iwn_alloc_fwmem(struct iwn_softc *); 132 void iwn_free_fwmem(struct iwn_softc *); 133 int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 134 void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 135 void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 136 int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 137 int); 138 void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 139 void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 140 void iwn5000_ict_reset(struct iwn_softc *); 141 int iwn_read_eeprom(struct iwn_softc *); 142 void iwn4965_read_eeprom(struct iwn_softc *); 143 void iwn4965_print_power_group(struct iwn_softc *, int); 144 void iwn5000_read_eeprom(struct iwn_softc *); 145 void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 146 void iwn_read_eeprom_enhinfo(struct iwn_softc *); 147 struct ieee80211_node *iwn_node_alloc(struct ieee80211com *); 148 void iwn_newassoc(struct ieee80211com *, struct ieee80211_node *, 149 int); 150 int iwn_media_change(struct ifnet *); 151 int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 152 void iwn_iter_func(void *, struct ieee80211_node *); 153 void iwn_calib_timeout(void *); 154 int iwn_ccmp_decap(struct iwn_softc *, struct mbuf *, 155 struct ieee80211_node *); 156 void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 157 struct iwn_rx_data *); 158 void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 159 struct iwn_rx_data *, struct mbuf_list *); 160 void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 161 struct iwn_rx_data *); 162 void iwn5000_rx_calib_results(struct iwn_softc *, 163 struct iwn_rx_desc *, struct iwn_rx_data *); 164 void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 165 struct iwn_rx_data *); 166 void iwn_ampdu_txq_advance(struct iwn_softc *, struct iwn_tx_ring *, 167 int, int); 168 void iwn_ampdu_tx_done(struct iwn_softc *, struct iwn_tx_ring *, 169 struct iwn_rx_desc *, uint16_t, struct iwn_txagg_status *, 170 int, uint32_t); 171 void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 172 struct iwn_rx_data *); 173 void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 174 struct iwn_rx_data *); 175 void iwn_tx_done_free_txdata(struct iwn_softc *, 176 struct iwn_tx_data *); 177 void iwn_clear_oactive(struct iwn_softc *, struct iwn_tx_ring *); 178 void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 179 uint8_t, int, int, uint16_t); 180 void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 181 void iwn_notif_intr(struct iwn_softc *); 182 void iwn_wakeup_intr(struct iwn_softc *); 183 void iwn_fatal_intr(struct iwn_softc *); 184 int iwn_intr(void *); 185 void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 186 uint16_t); 187 void iwn4965_reset_sched(struct iwn_softc *, int, int); 188 void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 189 uint16_t); 190 void iwn5000_reset_sched(struct iwn_softc *, int, int); 191 int iwn_tx(struct iwn_softc *, struct mbuf *, 192 struct ieee80211_node *); 193 int iwn_rval2ridx(int); 194 void iwn_start(struct ifnet *); 195 void iwn_watchdog(struct ifnet *); 196 int iwn_ioctl(struct ifnet *, u_long, caddr_t); 197 int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 198 int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 199 int); 200 int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 201 int); 202 int iwn_set_link_quality(struct iwn_softc *, 203 struct ieee80211_node *); 204 int iwn_add_broadcast_node(struct iwn_softc *, int, int); 205 void iwn_updateedca(struct ieee80211com *); 206 void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 207 int iwn_set_critical_temp(struct iwn_softc *); 208 int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 209 void iwn4965_power_calibration(struct iwn_softc *, int); 210 int iwn4965_set_txpower(struct iwn_softc *, int); 211 int iwn5000_set_txpower(struct iwn_softc *, int); 212 int iwn4965_get_rssi(const struct iwn_rx_stat *); 213 int iwn5000_get_rssi(const struct iwn_rx_stat *); 214 int iwn_get_noise(const struct iwn_rx_general_stats *); 215 int iwn4965_get_temperature(struct iwn_softc *); 216 int iwn5000_get_temperature(struct iwn_softc *); 217 int iwn_init_sensitivity(struct iwn_softc *); 218 void iwn_collect_noise(struct iwn_softc *, 219 const struct iwn_rx_general_stats *); 220 int iwn4965_init_gains(struct iwn_softc *); 221 int iwn5000_init_gains(struct iwn_softc *); 222 int iwn4965_set_gains(struct iwn_softc *); 223 int iwn5000_set_gains(struct iwn_softc *); 224 void iwn_tune_sensitivity(struct iwn_softc *, 225 const struct iwn_rx_stats *); 226 int iwn_send_sensitivity(struct iwn_softc *); 227 int iwn_set_pslevel(struct iwn_softc *, int, int, int); 228 int iwn_send_temperature_offset(struct iwn_softc *); 229 int iwn_send_btcoex(struct iwn_softc *); 230 int iwn_send_advanced_btcoex(struct iwn_softc *); 231 int iwn5000_runtime_calib(struct iwn_softc *); 232 int iwn_config(struct iwn_softc *); 233 uint16_t iwn_get_active_dwell_time(struct iwn_softc *, uint16_t, uint8_t); 234 uint16_t iwn_limit_dwell(struct iwn_softc *, uint16_t); 235 uint16_t iwn_get_passive_dwell_time(struct iwn_softc *, uint16_t); 236 int iwn_scan(struct iwn_softc *, uint16_t, int); 237 void iwn_scan_abort(struct iwn_softc *); 238 int iwn_bgscan(struct ieee80211com *); 239 int iwn_auth(struct iwn_softc *, int); 240 int iwn_run(struct iwn_softc *); 241 int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 242 struct ieee80211_key *); 243 void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 244 struct ieee80211_key *); 245 void iwn_update_htprot(struct ieee80211com *, 246 struct ieee80211_node *); 247 int iwn_ampdu_rx_start(struct ieee80211com *, 248 struct ieee80211_node *, uint8_t); 249 void iwn_ampdu_rx_stop(struct ieee80211com *, 250 struct ieee80211_node *, uint8_t); 251 int iwn_ampdu_tx_start(struct ieee80211com *, 252 struct ieee80211_node *, uint8_t); 253 void iwn_ampdu_tx_stop(struct ieee80211com *, 254 struct ieee80211_node *, uint8_t); 255 void iwn4965_ampdu_tx_start(struct iwn_softc *, 256 struct ieee80211_node *, uint8_t, uint16_t); 257 void iwn4965_ampdu_tx_stop(struct iwn_softc *, 258 uint8_t, uint16_t); 259 void iwn5000_ampdu_tx_start(struct iwn_softc *, 260 struct ieee80211_node *, uint8_t, uint16_t); 261 void iwn5000_ampdu_tx_stop(struct iwn_softc *, 262 uint8_t, uint16_t); 263 int iwn5000_query_calibration(struct iwn_softc *); 264 int iwn5000_send_calibration(struct iwn_softc *); 265 int iwn5000_send_wimax_coex(struct iwn_softc *); 266 int iwn5000_crystal_calib(struct iwn_softc *); 267 int iwn6000_temp_offset_calib(struct iwn_softc *); 268 int iwn2000_temp_offset_calib(struct iwn_softc *); 269 int iwn4965_post_alive(struct iwn_softc *); 270 int iwn5000_post_alive(struct iwn_softc *); 271 int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 272 int); 273 int iwn4965_load_firmware(struct iwn_softc *); 274 int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 275 const uint8_t *, int); 276 int iwn5000_load_firmware(struct iwn_softc *); 277 int iwn_read_firmware_leg(struct iwn_softc *, 278 struct iwn_fw_info *); 279 int iwn_read_firmware_tlv(struct iwn_softc *, 280 struct iwn_fw_info *, uint16_t); 281 int iwn_read_firmware(struct iwn_softc *); 282 int iwn_clock_wait(struct iwn_softc *); 283 int iwn_apm_init(struct iwn_softc *); 284 void iwn_apm_stop_master(struct iwn_softc *); 285 void iwn_apm_stop(struct iwn_softc *); 286 int iwn4965_nic_config(struct iwn_softc *); 287 int iwn5000_nic_config(struct iwn_softc *); 288 int iwn_hw_prepare(struct iwn_softc *); 289 int iwn_hw_init(struct iwn_softc *); 290 void iwn_hw_stop(struct iwn_softc *); 291 int iwn_init(struct ifnet *); 292 void iwn_stop(struct ifnet *); 293 294 #ifdef IWN_DEBUG 295 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 296 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 297 int iwn_debug = 1; 298 #else 299 #define DPRINTF(x) 300 #define DPRINTFN(n, x) 301 #endif 302 303 struct cfdriver iwn_cd = { 304 NULL, "iwn", DV_IFNET 305 }; 306 307 struct cfattach iwn_ca = { 308 sizeof (struct iwn_softc), iwn_match, iwn_attach, iwn_detach, 309 iwn_activate 310 }; 311 312 int 313 iwn_match(struct device *parent, void *match, void *aux) 314 { 315 return pci_matchbyid((struct pci_attach_args *)aux, iwn_devices, 316 nitems(iwn_devices)); 317 } 318 319 void 320 iwn_attach(struct device *parent, struct device *self, void *aux) 321 { 322 struct iwn_softc *sc = (struct iwn_softc *)self; 323 struct ieee80211com *ic = &sc->sc_ic; 324 struct ifnet *ifp = &ic->ic_if; 325 struct pci_attach_args *pa = aux; 326 const char *intrstr; 327 pci_intr_handle_t ih; 328 pcireg_t memtype, reg; 329 int i, error; 330 331 sc->sc_pct = pa->pa_pc; 332 sc->sc_pcitag = pa->pa_tag; 333 sc->sc_dmat = pa->pa_dmat; 334 335 /* 336 * Get the offset of the PCI Express Capability Structure in PCI 337 * Configuration Space. 338 */ 339 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 340 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 341 if (error == 0) { 342 printf(": PCIe capability structure not found!\n"); 343 return; 344 } 345 346 /* Clear device-specific "PCI retry timeout" register (41h). */ 347 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 348 if (reg & 0xff00) 349 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 350 351 /* Hardware bug workaround. */ 352 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 353 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 354 DPRINTF(("PCIe INTx Disable set\n")); 355 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 356 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 357 PCI_COMMAND_STATUS_REG, reg); 358 } 359 360 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 361 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 362 &sc->sc_sh, NULL, &sc->sc_sz, 0); 363 if (error != 0) { 364 printf(": can't map mem space\n"); 365 return; 366 } 367 368 /* Install interrupt handler. */ 369 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 370 printf(": can't map interrupt\n"); 371 return; 372 } 373 intrstr = pci_intr_string(sc->sc_pct, ih); 374 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc, 375 sc->sc_dev.dv_xname); 376 if (sc->sc_ih == NULL) { 377 printf(": can't establish interrupt"); 378 if (intrstr != NULL) 379 printf(" at %s", intrstr); 380 printf("\n"); 381 return; 382 } 383 printf(": %s", intrstr); 384 385 /* Read hardware revision and attach. */ 386 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0x1f; 387 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 388 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id)); 389 else 390 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id)); 391 if (error != 0) { 392 printf(": could not attach device\n"); 393 return; 394 } 395 396 if ((error = iwn_hw_prepare(sc)) != 0) { 397 printf(": hardware not ready\n"); 398 return; 399 } 400 401 /* Read MAC address, channels, etc from EEPROM. */ 402 if ((error = iwn_read_eeprom(sc)) != 0) { 403 printf(": could not read EEPROM\n"); 404 return; 405 } 406 407 /* Allocate DMA memory for firmware transfers. */ 408 if ((error = iwn_alloc_fwmem(sc)) != 0) { 409 printf(": could not allocate memory for firmware\n"); 410 return; 411 } 412 413 /* Allocate "Keep Warm" page. */ 414 if ((error = iwn_alloc_kw(sc)) != 0) { 415 printf(": could not allocate keep warm page\n"); 416 goto fail1; 417 } 418 419 /* Allocate ICT table for 5000 Series. */ 420 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 421 (error = iwn_alloc_ict(sc)) != 0) { 422 printf(": could not allocate ICT table\n"); 423 goto fail2; 424 } 425 426 /* Allocate TX scheduler "rings". */ 427 if ((error = iwn_alloc_sched(sc)) != 0) { 428 printf(": could not allocate TX scheduler rings\n"); 429 goto fail3; 430 } 431 432 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 433 for (i = 0; i < sc->ntxqs; i++) { 434 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 435 printf(": could not allocate TX ring %d\n", i); 436 goto fail4; 437 } 438 } 439 440 /* Allocate RX ring. */ 441 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 442 printf(": could not allocate RX ring\n"); 443 goto fail4; 444 } 445 446 /* Clear pending interrupts. */ 447 IWN_WRITE(sc, IWN_INT, 0xffffffff); 448 449 /* Count the number of available chains. */ 450 sc->ntxchains = 451 ((sc->txchainmask >> 2) & 1) + 452 ((sc->txchainmask >> 1) & 1) + 453 ((sc->txchainmask >> 0) & 1); 454 sc->nrxchains = 455 ((sc->rxchainmask >> 2) & 1) + 456 ((sc->rxchainmask >> 1) & 1) + 457 ((sc->rxchainmask >> 0) & 1); 458 printf(", MIMO %dT%dR, %.4s, address %s\n", sc->ntxchains, 459 sc->nrxchains, sc->eeprom_domain, ether_sprintf(ic->ic_myaddr)); 460 461 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 462 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 463 ic->ic_state = IEEE80211_S_INIT; 464 465 /* Set device capabilities. */ 466 ic->ic_caps = 467 IEEE80211_C_WEP | /* WEP */ 468 IEEE80211_C_RSN | /* WPA/RSN */ 469 IEEE80211_C_SCANALL | /* device scans all channels at once */ 470 IEEE80211_C_SCANALLBAND | /* driver scans all bands at once */ 471 IEEE80211_C_MONITOR | /* monitor mode supported */ 472 IEEE80211_C_SHSLOT | /* short slot time supported */ 473 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 474 IEEE80211_C_PMGT; /* power saving supported */ 475 476 /* No optional HT features supported for now, */ 477 ic->ic_htcaps = 0; 478 ic->ic_htxcaps = 0; 479 ic->ic_txbfcaps = 0; 480 ic->ic_aselcaps = 0; 481 ic->ic_ampdu_params = (IEEE80211_AMPDU_PARAM_SS_4 | 0x3 /* 64k */); 482 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 483 ic->ic_caps |= (IEEE80211_C_QOS | IEEE80211_C_TX_AMPDU); 484 /* Set HT capabilities. */ 485 ic->ic_htcaps = IEEE80211_HTCAP_SGI20; 486 #ifdef notyet 487 ic->ic_htcaps |= 488 #if IWN_RBUF_SIZE == 8192 489 IEEE80211_HTCAP_AMSDU7935 | 490 #endif 491 IEEE80211_HTCAP_CBW20_40 | 492 IEEE80211_HTCAP_SGI40; 493 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 494 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 495 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 496 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 497 else 498 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 499 #endif /* notyet */ 500 } 501 502 /* Set supported legacy rates. */ 503 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 504 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 505 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 506 ic->ic_sup_rates[IEEE80211_MODE_11A] = 507 ieee80211_std_rateset_11a; 508 } 509 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 510 /* Set supported HT rates. */ 511 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */ 512 #ifdef notyet 513 if (sc->nrxchains > 1) 514 ic->ic_sup_mcs[1] = 0xff; /* MCS 8-15 */ 515 if (sc->nrxchains > 2) 516 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 517 #endif 518 } 519 520 /* IBSS channel undefined for now. */ 521 ic->ic_ibss_chan = &ic->ic_channels[0]; 522 523 ifp->if_softc = sc; 524 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 525 ifp->if_ioctl = iwn_ioctl; 526 ifp->if_start = iwn_start; 527 ifp->if_watchdog = iwn_watchdog; 528 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 529 530 if_attach(ifp); 531 ieee80211_ifattach(ifp); 532 ic->ic_node_alloc = iwn_node_alloc; 533 ic->ic_bgscan_start = iwn_bgscan; 534 ic->ic_newassoc = iwn_newassoc; 535 ic->ic_updateedca = iwn_updateedca; 536 ic->ic_set_key = iwn_set_key; 537 ic->ic_delete_key = iwn_delete_key; 538 ic->ic_update_htprot = iwn_update_htprot; 539 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 540 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 541 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 542 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 543 544 /* Override 802.11 state transition machine. */ 545 sc->sc_newstate = ic->ic_newstate; 546 ic->ic_newstate = iwn_newstate; 547 ieee80211_media_init(ifp, iwn_media_change, ieee80211_media_status); 548 549 sc->amrr.amrr_min_success_threshold = 1; 550 sc->amrr.amrr_max_success_threshold = 15; 551 552 #if NBPFILTER > 0 553 iwn_radiotap_attach(sc); 554 #endif 555 timeout_set(&sc->calib_to, iwn_calib_timeout, sc); 556 rw_init(&sc->sc_rwlock, "iwnlock"); 557 task_set(&sc->init_task, iwn_init_task, sc); 558 return; 559 560 /* Free allocated memory if something failed during attachment. */ 561 fail4: while (--i >= 0) 562 iwn_free_tx_ring(sc, &sc->txq[i]); 563 iwn_free_sched(sc); 564 fail3: if (sc->ict != NULL) 565 iwn_free_ict(sc); 566 fail2: iwn_free_kw(sc); 567 fail1: iwn_free_fwmem(sc); 568 } 569 570 int 571 iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid) 572 { 573 struct iwn_ops *ops = &sc->ops; 574 575 ops->load_firmware = iwn4965_load_firmware; 576 ops->read_eeprom = iwn4965_read_eeprom; 577 ops->post_alive = iwn4965_post_alive; 578 ops->nic_config = iwn4965_nic_config; 579 ops->reset_sched = iwn4965_reset_sched; 580 ops->update_sched = iwn4965_update_sched; 581 ops->get_temperature = iwn4965_get_temperature; 582 ops->get_rssi = iwn4965_get_rssi; 583 ops->set_txpower = iwn4965_set_txpower; 584 ops->init_gains = iwn4965_init_gains; 585 ops->set_gains = iwn4965_set_gains; 586 ops->add_node = iwn4965_add_node; 587 ops->tx_done = iwn4965_tx_done; 588 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 589 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 590 sc->ntxqs = IWN4965_NTXQUEUES; 591 sc->first_agg_txq = IWN4965_FIRST_AGG_TXQUEUE; 592 sc->ndmachnls = IWN4965_NDMACHNLS; 593 sc->broadcast_id = IWN4965_ID_BROADCAST; 594 sc->rxonsz = IWN4965_RXONSZ; 595 sc->schedsz = IWN4965_SCHEDSZ; 596 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 597 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 598 sc->fwsz = IWN4965_FWSZ; 599 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 600 sc->limits = &iwn4965_sensitivity_limits; 601 sc->fwname = "iwn-4965"; 602 /* Override chains masks, ROM is known to be broken. */ 603 sc->txchainmask = IWN_ANT_AB; 604 sc->rxchainmask = IWN_ANT_ABC; 605 606 return 0; 607 } 608 609 int 610 iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid) 611 { 612 struct iwn_ops *ops = &sc->ops; 613 614 ops->load_firmware = iwn5000_load_firmware; 615 ops->read_eeprom = iwn5000_read_eeprom; 616 ops->post_alive = iwn5000_post_alive; 617 ops->nic_config = iwn5000_nic_config; 618 ops->reset_sched = iwn5000_reset_sched; 619 ops->update_sched = iwn5000_update_sched; 620 ops->get_temperature = iwn5000_get_temperature; 621 ops->get_rssi = iwn5000_get_rssi; 622 ops->set_txpower = iwn5000_set_txpower; 623 ops->init_gains = iwn5000_init_gains; 624 ops->set_gains = iwn5000_set_gains; 625 ops->add_node = iwn5000_add_node; 626 ops->tx_done = iwn5000_tx_done; 627 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 628 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 629 sc->ntxqs = IWN5000_NTXQUEUES; 630 sc->first_agg_txq = IWN5000_FIRST_AGG_TXQUEUE; 631 sc->ndmachnls = IWN5000_NDMACHNLS; 632 sc->broadcast_id = IWN5000_ID_BROADCAST; 633 sc->rxonsz = IWN5000_RXONSZ; 634 sc->schedsz = IWN5000_SCHEDSZ; 635 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 636 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 637 sc->fwsz = IWN5000_FWSZ; 638 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 639 640 switch (sc->hw_type) { 641 case IWN_HW_REV_TYPE_5100: 642 sc->limits = &iwn5000_sensitivity_limits; 643 sc->fwname = "iwn-5000"; 644 /* Override chains masks, ROM is known to be broken. */ 645 sc->txchainmask = IWN_ANT_B; 646 sc->rxchainmask = IWN_ANT_AB; 647 break; 648 case IWN_HW_REV_TYPE_5150: 649 sc->limits = &iwn5150_sensitivity_limits; 650 sc->fwname = "iwn-5150"; 651 break; 652 case IWN_HW_REV_TYPE_5300: 653 case IWN_HW_REV_TYPE_5350: 654 sc->limits = &iwn5000_sensitivity_limits; 655 sc->fwname = "iwn-5000"; 656 break; 657 case IWN_HW_REV_TYPE_1000: 658 sc->limits = &iwn1000_sensitivity_limits; 659 sc->fwname = "iwn-1000"; 660 break; 661 case IWN_HW_REV_TYPE_6000: 662 sc->limits = &iwn6000_sensitivity_limits; 663 sc->fwname = "iwn-6000"; 664 if (pid == PCI_PRODUCT_INTEL_WL_6200_1 || 665 pid == PCI_PRODUCT_INTEL_WL_6200_2) { 666 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 667 /* Override chains masks, ROM is known to be broken. */ 668 sc->txchainmask = IWN_ANT_BC; 669 sc->rxchainmask = IWN_ANT_BC; 670 } 671 break; 672 case IWN_HW_REV_TYPE_6050: 673 sc->limits = &iwn6000_sensitivity_limits; 674 sc->fwname = "iwn-6050"; 675 break; 676 case IWN_HW_REV_TYPE_6005: 677 sc->limits = &iwn6000_sensitivity_limits; 678 if (pid != PCI_PRODUCT_INTEL_WL_6005_1 && 679 pid != PCI_PRODUCT_INTEL_WL_6005_2) { 680 sc->fwname = "iwn-6030"; 681 sc->sc_flags |= IWN_FLAG_ADV_BT_COEX; 682 } else 683 sc->fwname = "iwn-6005"; 684 break; 685 case IWN_HW_REV_TYPE_2030: 686 sc->limits = &iwn2000_sensitivity_limits; 687 sc->fwname = "iwn-2030"; 688 sc->sc_flags |= IWN_FLAG_ADV_BT_COEX; 689 break; 690 case IWN_HW_REV_TYPE_2000: 691 sc->limits = &iwn2000_sensitivity_limits; 692 sc->fwname = "iwn-2000"; 693 break; 694 case IWN_HW_REV_TYPE_135: 695 sc->limits = &iwn2000_sensitivity_limits; 696 sc->fwname = "iwn-135"; 697 sc->sc_flags |= IWN_FLAG_ADV_BT_COEX; 698 break; 699 case IWN_HW_REV_TYPE_105: 700 sc->limits = &iwn2000_sensitivity_limits; 701 sc->fwname = "iwn-105"; 702 break; 703 default: 704 printf(": adapter type %d not supported\n", sc->hw_type); 705 return ENOTSUP; 706 } 707 return 0; 708 } 709 710 #if NBPFILTER > 0 711 /* 712 * Attach the interface to 802.11 radiotap. 713 */ 714 void 715 iwn_radiotap_attach(struct iwn_softc *sc) 716 { 717 bpfattach(&sc->sc_drvbpf, &sc->sc_ic.ic_if, DLT_IEEE802_11_RADIO, 718 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 719 720 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 721 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 722 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 723 724 sc->sc_txtap_len = sizeof sc->sc_txtapu; 725 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 726 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 727 } 728 #endif 729 730 int 731 iwn_detach(struct device *self, int flags) 732 { 733 struct iwn_softc *sc = (struct iwn_softc *)self; 734 struct ifnet *ifp = &sc->sc_ic.ic_if; 735 int qid; 736 737 timeout_del(&sc->calib_to); 738 task_del(systq, &sc->init_task); 739 740 /* Uninstall interrupt handler. */ 741 if (sc->sc_ih != NULL) 742 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 743 744 /* Free DMA resources. */ 745 iwn_free_rx_ring(sc, &sc->rxq); 746 for (qid = 0; qid < sc->ntxqs; qid++) 747 iwn_free_tx_ring(sc, &sc->txq[qid]); 748 iwn_free_sched(sc); 749 iwn_free_kw(sc); 750 if (sc->ict != NULL) 751 iwn_free_ict(sc); 752 iwn_free_fwmem(sc); 753 754 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 755 756 ieee80211_ifdetach(ifp); 757 if_detach(ifp); 758 759 return 0; 760 } 761 762 int 763 iwn_activate(struct device *self, int act) 764 { 765 struct iwn_softc *sc = (struct iwn_softc *)self; 766 struct ifnet *ifp = &sc->sc_ic.ic_if; 767 768 switch (act) { 769 case DVACT_SUSPEND: 770 if (ifp->if_flags & IFF_RUNNING) 771 iwn_stop(ifp); 772 break; 773 case DVACT_WAKEUP: 774 iwn_wakeup(sc); 775 break; 776 } 777 778 return 0; 779 } 780 781 void 782 iwn_wakeup(struct iwn_softc *sc) 783 { 784 pcireg_t reg; 785 786 /* Clear device-specific "PCI retry timeout" register (41h). */ 787 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 788 if (reg & 0xff00) 789 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 790 iwn_init_task(sc); 791 } 792 793 void 794 iwn_init_task(void *arg1) 795 { 796 struct iwn_softc *sc = arg1; 797 struct ifnet *ifp = &sc->sc_ic.ic_if; 798 int s; 799 800 rw_enter_write(&sc->sc_rwlock); 801 s = splnet(); 802 803 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 804 iwn_init(ifp); 805 806 splx(s); 807 rw_exit_write(&sc->sc_rwlock); 808 } 809 810 int 811 iwn_nic_lock(struct iwn_softc *sc) 812 { 813 int ntries; 814 815 /* Request exclusive access to NIC. */ 816 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 817 818 /* Spin until we actually get the lock. */ 819 for (ntries = 0; ntries < 1000; ntries++) { 820 if ((IWN_READ(sc, IWN_GP_CNTRL) & 821 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 822 IWN_GP_CNTRL_MAC_ACCESS_ENA) 823 return 0; 824 DELAY(10); 825 } 826 return ETIMEDOUT; 827 } 828 829 static __inline void 830 iwn_nic_unlock(struct iwn_softc *sc) 831 { 832 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 833 } 834 835 static __inline uint32_t 836 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 837 { 838 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 839 IWN_BARRIER_READ_WRITE(sc); 840 return IWN_READ(sc, IWN_PRPH_RDATA); 841 } 842 843 static __inline void 844 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 845 { 846 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 847 IWN_BARRIER_WRITE(sc); 848 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 849 } 850 851 static __inline void 852 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 853 { 854 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 855 } 856 857 static __inline void 858 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 859 { 860 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 861 } 862 863 static __inline void 864 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 865 const uint32_t *data, int count) 866 { 867 for (; count > 0; count--, data++, addr += 4) 868 iwn_prph_write(sc, addr, *data); 869 } 870 871 static __inline uint32_t 872 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 873 { 874 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 875 IWN_BARRIER_READ_WRITE(sc); 876 return IWN_READ(sc, IWN_MEM_RDATA); 877 } 878 879 static __inline void 880 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 881 { 882 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 883 IWN_BARRIER_WRITE(sc); 884 IWN_WRITE(sc, IWN_MEM_WDATA, data); 885 } 886 887 static __inline void 888 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 889 { 890 uint32_t tmp; 891 892 tmp = iwn_mem_read(sc, addr & ~3); 893 if (addr & 3) 894 tmp = (tmp & 0x0000ffff) | data << 16; 895 else 896 tmp = (tmp & 0xffff0000) | data; 897 iwn_mem_write(sc, addr & ~3, tmp); 898 } 899 900 #ifdef IWN_DEBUG 901 902 static __inline void 903 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 904 int count) 905 { 906 for (; count > 0; count--, addr += 4) 907 *data++ = iwn_mem_read(sc, addr); 908 } 909 910 #endif 911 912 static __inline void 913 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 914 int count) 915 { 916 for (; count > 0; count--, addr += 4) 917 iwn_mem_write(sc, addr, val); 918 } 919 920 int 921 iwn_eeprom_lock(struct iwn_softc *sc) 922 { 923 int i, ntries; 924 925 for (i = 0; i < 100; i++) { 926 /* Request exclusive access to EEPROM. */ 927 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 928 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 929 930 /* Spin until we actually get the lock. */ 931 for (ntries = 0; ntries < 100; ntries++) { 932 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 933 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 934 return 0; 935 DELAY(10); 936 } 937 } 938 return ETIMEDOUT; 939 } 940 941 static __inline void 942 iwn_eeprom_unlock(struct iwn_softc *sc) 943 { 944 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 945 } 946 947 /* 948 * Initialize access by host to One Time Programmable ROM. 949 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 950 */ 951 int 952 iwn_init_otprom(struct iwn_softc *sc) 953 { 954 uint16_t prev, base, next; 955 int count, error; 956 957 /* Wait for clock stabilization before accessing prph. */ 958 if ((error = iwn_clock_wait(sc)) != 0) 959 return error; 960 961 if ((error = iwn_nic_lock(sc)) != 0) 962 return error; 963 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 964 DELAY(5); 965 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 966 iwn_nic_unlock(sc); 967 968 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 969 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 970 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 971 IWN_RESET_LINK_PWR_MGMT_DIS); 972 } 973 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 974 /* Clear ECC status. */ 975 IWN_SETBITS(sc, IWN_OTP_GP, 976 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 977 978 /* 979 * Find the block before last block (contains the EEPROM image) 980 * for HW without OTP shadow RAM. 981 */ 982 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 983 /* Switch to absolute addressing mode. */ 984 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 985 base = 0; 986 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 987 error = iwn_read_prom_data(sc, base, &next, 2); 988 if (error != 0) 989 return error; 990 if (next == 0) /* End of linked-list. */ 991 break; 992 prev = base; 993 base = letoh16(next); 994 } 995 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 996 return EIO; 997 /* Skip "next" word. */ 998 sc->prom_base = prev + 1; 999 } 1000 return 0; 1001 } 1002 1003 int 1004 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1005 { 1006 uint8_t *out = data; 1007 uint32_t val, tmp; 1008 int ntries; 1009 1010 addr += sc->prom_base; 1011 for (; count > 0; count -= 2, addr++) { 1012 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1013 for (ntries = 0; ntries < 10; ntries++) { 1014 val = IWN_READ(sc, IWN_EEPROM); 1015 if (val & IWN_EEPROM_READ_VALID) 1016 break; 1017 DELAY(5); 1018 } 1019 if (ntries == 10) { 1020 printf("%s: timeout reading ROM at 0x%x\n", 1021 sc->sc_dev.dv_xname, addr); 1022 return ETIMEDOUT; 1023 } 1024 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1025 /* OTPROM, check for ECC errors. */ 1026 tmp = IWN_READ(sc, IWN_OTP_GP); 1027 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1028 printf("%s: OTPROM ECC error at 0x%x\n", 1029 sc->sc_dev.dv_xname, addr); 1030 return EIO; 1031 } 1032 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1033 /* Correctable ECC error, clear bit. */ 1034 IWN_SETBITS(sc, IWN_OTP_GP, 1035 IWN_OTP_GP_ECC_CORR_STTS); 1036 } 1037 } 1038 *out++ = val >> 16; 1039 if (count > 1) 1040 *out++ = val >> 24; 1041 } 1042 return 0; 1043 } 1044 1045 int 1046 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1047 bus_size_t size, bus_size_t alignment) 1048 { 1049 int nsegs, error; 1050 1051 dma->tag = tag; 1052 dma->size = size; 1053 1054 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1055 &dma->map); 1056 if (error != 0) 1057 goto fail; 1058 1059 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1060 BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1061 if (error != 0) 1062 goto fail; 1063 1064 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1065 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 1066 if (error != 0) 1067 goto fail; 1068 1069 error = bus_dmamap_load_raw(tag, dma->map, &dma->seg, 1, size, 1070 BUS_DMA_NOWAIT); 1071 if (error != 0) 1072 goto fail; 1073 1074 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1075 1076 dma->paddr = dma->map->dm_segs[0].ds_addr; 1077 if (kvap != NULL) 1078 *kvap = dma->vaddr; 1079 1080 return 0; 1081 1082 fail: iwn_dma_contig_free(dma); 1083 return error; 1084 } 1085 1086 void 1087 iwn_dma_contig_free(struct iwn_dma_info *dma) 1088 { 1089 if (dma->map != NULL) { 1090 if (dma->vaddr != NULL) { 1091 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1092 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1093 bus_dmamap_unload(dma->tag, dma->map); 1094 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1095 bus_dmamem_free(dma->tag, &dma->seg, 1); 1096 dma->vaddr = NULL; 1097 } 1098 bus_dmamap_destroy(dma->tag, dma->map); 1099 dma->map = NULL; 1100 } 1101 } 1102 1103 int 1104 iwn_alloc_sched(struct iwn_softc *sc) 1105 { 1106 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1107 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1108 (void **)&sc->sched, sc->schedsz, 1024); 1109 } 1110 1111 void 1112 iwn_free_sched(struct iwn_softc *sc) 1113 { 1114 iwn_dma_contig_free(&sc->sched_dma); 1115 } 1116 1117 int 1118 iwn_alloc_kw(struct iwn_softc *sc) 1119 { 1120 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1121 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1122 4096); 1123 } 1124 1125 void 1126 iwn_free_kw(struct iwn_softc *sc) 1127 { 1128 iwn_dma_contig_free(&sc->kw_dma); 1129 } 1130 1131 int 1132 iwn_alloc_ict(struct iwn_softc *sc) 1133 { 1134 /* ICT table must be aligned on a 4KB boundary. */ 1135 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1136 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1137 } 1138 1139 void 1140 iwn_free_ict(struct iwn_softc *sc) 1141 { 1142 iwn_dma_contig_free(&sc->ict_dma); 1143 } 1144 1145 int 1146 iwn_alloc_fwmem(struct iwn_softc *sc) 1147 { 1148 /* Must be aligned on a 16-byte boundary. */ 1149 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1150 sc->fwsz, 16); 1151 } 1152 1153 void 1154 iwn_free_fwmem(struct iwn_softc *sc) 1155 { 1156 iwn_dma_contig_free(&sc->fw_dma); 1157 } 1158 1159 int 1160 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1161 { 1162 bus_size_t size; 1163 int i, error; 1164 1165 ring->cur = 0; 1166 1167 /* Allocate RX descriptors (256-byte aligned). */ 1168 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1169 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1170 (void **)&ring->desc, size, 256); 1171 if (error != 0) { 1172 printf("%s: could not allocate RX ring DMA memory\n", 1173 sc->sc_dev.dv_xname); 1174 goto fail; 1175 } 1176 1177 /* Allocate RX status area (16-byte aligned). */ 1178 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1179 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1180 if (error != 0) { 1181 printf("%s: could not allocate RX status DMA memory\n", 1182 sc->sc_dev.dv_xname); 1183 goto fail; 1184 } 1185 1186 /* 1187 * Allocate and map RX buffers. 1188 */ 1189 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1190 struct iwn_rx_data *data = &ring->data[i]; 1191 1192 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1193 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1194 &data->map); 1195 if (error != 0) { 1196 printf("%s: could not create RX buf DMA map\n", 1197 sc->sc_dev.dv_xname); 1198 goto fail; 1199 } 1200 1201 data->m = MCLGETI(NULL, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1202 if (data->m == NULL) { 1203 printf("%s: could not allocate RX mbuf\n", 1204 sc->sc_dev.dv_xname); 1205 error = ENOBUFS; 1206 goto fail; 1207 } 1208 1209 error = bus_dmamap_load(sc->sc_dmat, data->map, 1210 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1211 BUS_DMA_NOWAIT | BUS_DMA_READ); 1212 if (error != 0) { 1213 printf("%s: can't map mbuf (error %d)\n", 1214 sc->sc_dev.dv_xname, error); 1215 goto fail; 1216 } 1217 1218 /* Set physical address of RX buffer (256-byte aligned). */ 1219 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1220 } 1221 1222 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1223 BUS_DMASYNC_PREWRITE); 1224 1225 return 0; 1226 1227 fail: iwn_free_rx_ring(sc, ring); 1228 return error; 1229 } 1230 1231 void 1232 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1233 { 1234 int ntries; 1235 1236 if (iwn_nic_lock(sc) == 0) { 1237 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1238 for (ntries = 0; ntries < 1000; ntries++) { 1239 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1240 IWN_FH_RX_STATUS_IDLE) 1241 break; 1242 DELAY(10); 1243 } 1244 iwn_nic_unlock(sc); 1245 } 1246 ring->cur = 0; 1247 sc->last_rx_valid = 0; 1248 } 1249 1250 void 1251 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1252 { 1253 int i; 1254 1255 iwn_dma_contig_free(&ring->desc_dma); 1256 iwn_dma_contig_free(&ring->stat_dma); 1257 1258 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1259 struct iwn_rx_data *data = &ring->data[i]; 1260 1261 if (data->m != NULL) { 1262 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1263 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1264 bus_dmamap_unload(sc->sc_dmat, data->map); 1265 m_freem(data->m); 1266 } 1267 if (data->map != NULL) 1268 bus_dmamap_destroy(sc->sc_dmat, data->map); 1269 } 1270 } 1271 1272 int 1273 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1274 { 1275 bus_addr_t paddr; 1276 bus_size_t size; 1277 int i, error; 1278 1279 ring->qid = qid; 1280 ring->queued = 0; 1281 ring->cur = 0; 1282 1283 /* Allocate TX descriptors (256-byte aligned). */ 1284 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1285 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1286 (void **)&ring->desc, size, 256); 1287 if (error != 0) { 1288 printf("%s: could not allocate TX ring DMA memory\n", 1289 sc->sc_dev.dv_xname); 1290 goto fail; 1291 } 1292 1293 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1294 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1295 (void **)&ring->cmd, size, 4); 1296 if (error != 0) { 1297 printf("%s: could not allocate TX cmd DMA memory\n", 1298 sc->sc_dev.dv_xname); 1299 goto fail; 1300 } 1301 1302 paddr = ring->cmd_dma.paddr; 1303 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1304 struct iwn_tx_data *data = &ring->data[i]; 1305 1306 data->cmd_paddr = paddr; 1307 data->scratch_paddr = paddr + 12; 1308 paddr += sizeof (struct iwn_tx_cmd); 1309 1310 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1311 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1312 &data->map); 1313 if (error != 0) { 1314 printf("%s: could not create TX buf DMA map\n", 1315 sc->sc_dev.dv_xname); 1316 goto fail; 1317 } 1318 } 1319 return 0; 1320 1321 fail: iwn_free_tx_ring(sc, ring); 1322 return error; 1323 } 1324 1325 void 1326 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1327 { 1328 int i; 1329 1330 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1331 struct iwn_tx_data *data = &ring->data[i]; 1332 1333 if (data->m != NULL) { 1334 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1335 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1336 bus_dmamap_unload(sc->sc_dmat, data->map); 1337 m_freem(data->m); 1338 data->m = NULL; 1339 } 1340 } 1341 /* Clear TX descriptors. */ 1342 memset(ring->desc, 0, ring->desc_dma.size); 1343 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1344 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1345 sc->qfullmsk &= ~(1 << ring->qid); 1346 ring->queued = 0; 1347 ring->cur = 0; 1348 } 1349 1350 void 1351 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1352 { 1353 int i; 1354 1355 iwn_dma_contig_free(&ring->desc_dma); 1356 iwn_dma_contig_free(&ring->cmd_dma); 1357 1358 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1359 struct iwn_tx_data *data = &ring->data[i]; 1360 1361 if (data->m != NULL) { 1362 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1363 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1364 bus_dmamap_unload(sc->sc_dmat, data->map); 1365 m_freem(data->m); 1366 } 1367 if (data->map != NULL) 1368 bus_dmamap_destroy(sc->sc_dmat, data->map); 1369 } 1370 } 1371 1372 void 1373 iwn5000_ict_reset(struct iwn_softc *sc) 1374 { 1375 /* Disable interrupts. */ 1376 IWN_WRITE(sc, IWN_INT_MASK, 0); 1377 1378 /* Reset ICT table. */ 1379 memset(sc->ict, 0, IWN_ICT_SIZE); 1380 sc->ict_cur = 0; 1381 1382 /* Set physical address of ICT table (4KB aligned). */ 1383 DPRINTF(("enabling ICT\n")); 1384 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1385 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1386 1387 /* Enable periodic RX interrupt. */ 1388 sc->int_mask |= IWN_INT_RX_PERIODIC; 1389 /* Switch to ICT interrupt mode in driver. */ 1390 sc->sc_flags |= IWN_FLAG_USE_ICT; 1391 1392 /* Re-enable interrupts. */ 1393 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1394 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1395 } 1396 1397 int 1398 iwn_read_eeprom(struct iwn_softc *sc) 1399 { 1400 struct iwn_ops *ops = &sc->ops; 1401 struct ieee80211com *ic = &sc->sc_ic; 1402 uint16_t val; 1403 int error; 1404 1405 /* Check whether adapter has an EEPROM or an OTPROM. */ 1406 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1407 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1408 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1409 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1410 "OTPROM" : "EEPROM")); 1411 1412 /* Adapter has to be powered on for EEPROM access to work. */ 1413 if ((error = iwn_apm_init(sc)) != 0) { 1414 printf("%s: could not power ON adapter\n", 1415 sc->sc_dev.dv_xname); 1416 return error; 1417 } 1418 1419 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1420 printf("%s: bad ROM signature\n", sc->sc_dev.dv_xname); 1421 return EIO; 1422 } 1423 if ((error = iwn_eeprom_lock(sc)) != 0) { 1424 printf("%s: could not lock ROM (error=%d)\n", 1425 sc->sc_dev.dv_xname, error); 1426 return error; 1427 } 1428 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1429 if ((error = iwn_init_otprom(sc)) != 0) { 1430 printf("%s: could not initialize OTPROM\n", 1431 sc->sc_dev.dv_xname); 1432 return error; 1433 } 1434 } 1435 1436 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1437 DPRINTF(("SKU capabilities=0x%04x\n", letoh16(val))); 1438 /* Check if HT support is bonded out. */ 1439 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1440 sc->sc_flags |= IWN_FLAG_HAS_11N; 1441 1442 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1443 sc->rfcfg = letoh16(val); 1444 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1445 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1446 if (sc->txchainmask == 0) 1447 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1448 if (sc->rxchainmask == 0) 1449 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1450 1451 /* Read MAC address. */ 1452 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1453 1454 /* Read adapter-specific information from EEPROM. */ 1455 ops->read_eeprom(sc); 1456 1457 iwn_apm_stop(sc); /* Power OFF adapter. */ 1458 1459 iwn_eeprom_unlock(sc); 1460 return 0; 1461 } 1462 1463 void 1464 iwn4965_read_eeprom(struct iwn_softc *sc) 1465 { 1466 uint32_t addr; 1467 uint16_t val; 1468 int i; 1469 1470 /* Read regulatory domain (4 ASCII characters). */ 1471 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1472 1473 /* Read the list of authorized channels (20MHz ones only). */ 1474 for (i = 0; i < 5; i++) { 1475 addr = iwn4965_regulatory_bands[i]; 1476 iwn_read_eeprom_channels(sc, i, addr); 1477 } 1478 1479 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1480 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1481 sc->maxpwr2GHz = val & 0xff; 1482 sc->maxpwr5GHz = val >> 8; 1483 /* Check that EEPROM values are within valid range. */ 1484 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1485 sc->maxpwr5GHz = 38; 1486 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1487 sc->maxpwr2GHz = 38; 1488 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1489 1490 /* Read samples for each TX power group. */ 1491 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1492 sizeof sc->bands); 1493 1494 /* Read voltage at which samples were taken. */ 1495 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1496 sc->eeprom_voltage = (int16_t)letoh16(val); 1497 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1498 1499 #ifdef IWN_DEBUG 1500 /* Print samples. */ 1501 if (iwn_debug > 0) { 1502 for (i = 0; i < IWN_NBANDS; i++) 1503 iwn4965_print_power_group(sc, i); 1504 } 1505 #endif 1506 } 1507 1508 #ifdef IWN_DEBUG 1509 void 1510 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1511 { 1512 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1513 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1514 int j, c; 1515 1516 printf("===band %d===\n", i); 1517 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1518 printf("chan1 num=%d\n", chans[0].num); 1519 for (c = 0; c < 2; c++) { 1520 for (j = 0; j < IWN_NSAMPLES; j++) { 1521 printf("chain %d, sample %d: temp=%d gain=%d " 1522 "power=%d pa_det=%d\n", c, j, 1523 chans[0].samples[c][j].temp, 1524 chans[0].samples[c][j].gain, 1525 chans[0].samples[c][j].power, 1526 chans[0].samples[c][j].pa_det); 1527 } 1528 } 1529 printf("chan2 num=%d\n", chans[1].num); 1530 for (c = 0; c < 2; c++) { 1531 for (j = 0; j < IWN_NSAMPLES; j++) { 1532 printf("chain %d, sample %d: temp=%d gain=%d " 1533 "power=%d pa_det=%d\n", c, j, 1534 chans[1].samples[c][j].temp, 1535 chans[1].samples[c][j].gain, 1536 chans[1].samples[c][j].power, 1537 chans[1].samples[c][j].pa_det); 1538 } 1539 } 1540 } 1541 #endif 1542 1543 void 1544 iwn5000_read_eeprom(struct iwn_softc *sc) 1545 { 1546 struct iwn5000_eeprom_calib_hdr hdr; 1547 int32_t volt; 1548 uint32_t base, addr; 1549 uint16_t val; 1550 int i; 1551 1552 /* Read regulatory domain (4 ASCII characters). */ 1553 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1554 base = letoh16(val); 1555 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1556 sc->eeprom_domain, 4); 1557 1558 /* Read the list of authorized channels (20MHz ones only). */ 1559 for (i = 0; i < 5; i++) { 1560 addr = base + iwn5000_regulatory_bands[i]; 1561 iwn_read_eeprom_channels(sc, i, addr); 1562 } 1563 1564 /* Read enhanced TX power information for 6000 Series. */ 1565 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1566 iwn_read_eeprom_enhinfo(sc); 1567 1568 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1569 base = letoh16(val); 1570 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1571 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1572 hdr.version, hdr.pa_type, letoh16(hdr.volt))); 1573 sc->calib_ver = hdr.version; 1574 1575 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 1576 sc->hw_type == IWN_HW_REV_TYPE_2000 || 1577 sc->hw_type == IWN_HW_REV_TYPE_135 || 1578 sc->hw_type == IWN_HW_REV_TYPE_105) { 1579 sc->eeprom_voltage = letoh16(hdr.volt); 1580 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1581 sc->eeprom_temp = letoh16(val); 1582 iwn_read_prom_data(sc, base + IWN2000_EEPROM_RAWTEMP, &val, 2); 1583 sc->eeprom_rawtemp = letoh16(val); 1584 } 1585 1586 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1587 /* Compute temperature offset. */ 1588 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1589 sc->eeprom_temp = letoh16(val); 1590 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1591 volt = letoh16(val); 1592 sc->temp_off = sc->eeprom_temp - (volt / -5); 1593 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1594 sc->eeprom_temp, volt, sc->temp_off)); 1595 } else { 1596 /* Read crystal calibration. */ 1597 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1598 &sc->eeprom_crystal, sizeof (uint32_t)); 1599 DPRINTF(("crystal calibration 0x%08x\n", 1600 letoh32(sc->eeprom_crystal))); 1601 } 1602 } 1603 1604 void 1605 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1606 { 1607 struct ieee80211com *ic = &sc->sc_ic; 1608 const struct iwn_chan_band *band = &iwn_bands[n]; 1609 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1610 uint8_t chan; 1611 int i; 1612 1613 iwn_read_prom_data(sc, addr, channels, 1614 band->nchan * sizeof (struct iwn_eeprom_chan)); 1615 1616 for (i = 0; i < band->nchan; i++) { 1617 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1618 continue; 1619 1620 chan = band->chan[i]; 1621 1622 if (n == 0) { /* 2GHz band */ 1623 ic->ic_channels[chan].ic_freq = 1624 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1625 ic->ic_channels[chan].ic_flags = 1626 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1627 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1628 1629 } else { /* 5GHz band */ 1630 /* 1631 * Some adapters support channels 7, 8, 11 and 12 1632 * both in the 2GHz and 4.9GHz bands. 1633 * Because of limitations in our net80211 layer, 1634 * we don't support them in the 4.9GHz band. 1635 */ 1636 if (chan <= 14) 1637 continue; 1638 1639 ic->ic_channels[chan].ic_freq = 1640 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1641 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1642 /* We have at least one valid 5GHz channel. */ 1643 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1644 } 1645 1646 /* Is active scan allowed on this channel? */ 1647 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1648 ic->ic_channels[chan].ic_flags |= 1649 IEEE80211_CHAN_PASSIVE; 1650 } 1651 1652 /* Save maximum allowed TX power for this channel. */ 1653 sc->maxpwr[chan] = channels[i].maxpwr; 1654 1655 if (sc->sc_flags & IWN_FLAG_HAS_11N) 1656 ic->ic_channels[chan].ic_flags |= IEEE80211_CHAN_HT; 1657 1658 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1659 chan, channels[i].flags, sc->maxpwr[chan])); 1660 } 1661 } 1662 1663 void 1664 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1665 { 1666 struct iwn_eeprom_enhinfo enhinfo[35]; 1667 uint16_t val, base; 1668 int8_t maxpwr; 1669 int i; 1670 1671 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1672 base = letoh16(val); 1673 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1674 enhinfo, sizeof enhinfo); 1675 1676 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1677 for (i = 0; i < nitems(enhinfo); i++) { 1678 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1679 continue; /* Skip invalid entries. */ 1680 1681 maxpwr = 0; 1682 if (sc->txchainmask & IWN_ANT_A) 1683 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1684 if (sc->txchainmask & IWN_ANT_B) 1685 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1686 if (sc->txchainmask & IWN_ANT_C) 1687 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1688 if (sc->ntxchains == 2) 1689 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1690 else if (sc->ntxchains == 3) 1691 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1692 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1693 1694 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1695 sc->enh_maxpwr[i] = maxpwr; 1696 } 1697 } 1698 1699 struct ieee80211_node * 1700 iwn_node_alloc(struct ieee80211com *ic) 1701 { 1702 return malloc(sizeof (struct iwn_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1703 } 1704 1705 void 1706 iwn_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 1707 { 1708 struct iwn_softc *sc = ic->ic_if.if_softc; 1709 struct iwn_node *wn = (void *)ni; 1710 uint8_t rate; 1711 int ridx, i; 1712 1713 if ((ni->ni_flags & IEEE80211_NODE_HT) == 0) 1714 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1715 1716 /* Start at lowest available bit-rate, AMRR/MiRA will raise. */ 1717 ni->ni_txrate = 0; 1718 ni->ni_txmcs = 0; 1719 1720 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1721 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1722 /* Map 802.11 rate to HW rate index. */ 1723 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 1724 if (iwn_rates[ridx].plcp != IWN_PLCP_INVALID && 1725 iwn_rates[ridx].rate == rate) 1726 break; 1727 } 1728 wn->ridx[i] = ridx; 1729 } 1730 } 1731 1732 int 1733 iwn_media_change(struct ifnet *ifp) 1734 { 1735 struct iwn_softc *sc = ifp->if_softc; 1736 struct ieee80211com *ic = &sc->sc_ic; 1737 uint8_t rate, ridx; 1738 int error; 1739 1740 error = ieee80211_media_change(ifp); 1741 if (error != ENETRESET) 1742 return error; 1743 1744 if (ic->ic_fixed_mcs != -1) 1745 sc->fixed_ridx = iwn_mcs2ridx[ic->ic_fixed_mcs]; 1746 if (ic->ic_fixed_rate != -1) { 1747 rate = ic->ic_sup_rates[ic->ic_curmode]. 1748 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1749 /* Map 802.11 rate to HW rate index. */ 1750 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1751 if (iwn_rates[ridx].plcp != IWN_PLCP_INVALID && 1752 iwn_rates[ridx].rate == rate) 1753 break; 1754 sc->fixed_ridx = ridx; 1755 } 1756 1757 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1758 (IFF_UP | IFF_RUNNING)) { 1759 iwn_stop(ifp); 1760 error = iwn_init(ifp); 1761 } 1762 return error; 1763 } 1764 1765 int 1766 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1767 { 1768 struct ifnet *ifp = &ic->ic_if; 1769 struct iwn_softc *sc = ifp->if_softc; 1770 struct ieee80211_node *ni = ic->ic_bss; 1771 struct iwn_node *wn = (void *)ni; 1772 int error; 1773 1774 if (ic->ic_state == IEEE80211_S_RUN) { 1775 if (nstate == IEEE80211_S_SCAN) { 1776 /* 1777 * During RUN->SCAN we don't call sc_newstate() so 1778 * we must stop A-MPDU Tx ourselves in this case. 1779 */ 1780 ieee80211_stop_ampdu_tx(ic, ni, -1); 1781 ieee80211_ba_del(ni); 1782 } 1783 ieee80211_mira_cancel_timeouts(&wn->mn); 1784 timeout_del(&sc->calib_to); 1785 sc->calib.state = IWN_CALIB_STATE_INIT; 1786 if (sc->sc_flags & IWN_FLAG_BGSCAN) 1787 iwn_scan_abort(sc); 1788 } 1789 1790 if (ic->ic_state == IEEE80211_S_SCAN) { 1791 if (nstate == IEEE80211_S_SCAN) { 1792 if (sc->sc_flags & IWN_FLAG_SCANNING) 1793 return 0; 1794 } else 1795 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1796 /* Turn LED off when leaving scan state. */ 1797 iwn_set_led(sc, IWN_LED_LINK, 1, 0); 1798 } 1799 1800 if (ic->ic_state >= IEEE80211_S_ASSOC && 1801 nstate <= IEEE80211_S_ASSOC) { 1802 /* Reset state to handle re- and disassociations. */ 1803 sc->rxon.associd = 0; 1804 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1805 sc->calib.state = IWN_CALIB_STATE_INIT; 1806 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 1807 if (error != 0) 1808 printf("%s: RXON command failed\n", 1809 sc->sc_dev.dv_xname); 1810 } 1811 1812 switch (nstate) { 1813 case IEEE80211_S_SCAN: 1814 /* Make the link LED blink while we're scanning. */ 1815 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1816 1817 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ, 0)) != 0) { 1818 printf("%s: could not initiate scan\n", 1819 sc->sc_dev.dv_xname); 1820 return error; 1821 } 1822 if (ifp->if_flags & IFF_DEBUG) 1823 printf("%s: %s -> %s\n", ifp->if_xname, 1824 ieee80211_state_name[ic->ic_state], 1825 ieee80211_state_name[nstate]); 1826 if ((sc->sc_flags & IWN_FLAG_BGSCAN) == 0) { 1827 ieee80211_set_link_state(ic, LINK_STATE_DOWN); 1828 ieee80211_node_cleanup(ic, ic->ic_bss); 1829 } 1830 ic->ic_state = nstate; 1831 return 0; 1832 1833 case IEEE80211_S_ASSOC: 1834 if (ic->ic_state != IEEE80211_S_RUN) 1835 break; 1836 /* FALLTHROUGH */ 1837 case IEEE80211_S_AUTH: 1838 if ((error = iwn_auth(sc, arg)) != 0) { 1839 printf("%s: could not move to auth state\n", 1840 sc->sc_dev.dv_xname); 1841 return error; 1842 } 1843 break; 1844 1845 case IEEE80211_S_RUN: 1846 if ((error = iwn_run(sc)) != 0) { 1847 printf("%s: could not move to run state\n", 1848 sc->sc_dev.dv_xname); 1849 return error; 1850 } 1851 break; 1852 1853 case IEEE80211_S_INIT: 1854 sc->calib.state = IWN_CALIB_STATE_INIT; 1855 break; 1856 } 1857 1858 return sc->sc_newstate(ic, nstate, arg); 1859 } 1860 1861 void 1862 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1863 { 1864 struct iwn_softc *sc = arg; 1865 struct iwn_node *wn = (void *)ni; 1866 1867 if ((ni->ni_flags & IEEE80211_NODE_HT) == 0) 1868 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1869 } 1870 1871 void 1872 iwn_calib_timeout(void *arg) 1873 { 1874 struct iwn_softc *sc = arg; 1875 struct ieee80211com *ic = &sc->sc_ic; 1876 int s; 1877 1878 s = splnet(); 1879 if (ic->ic_fixed_rate == -1) { 1880 if (ic->ic_opmode == IEEE80211_M_STA) 1881 iwn_iter_func(sc, ic->ic_bss); 1882 else 1883 ieee80211_iterate_nodes(ic, iwn_iter_func, sc); 1884 } 1885 /* Force automatic TX power calibration every 60 secs. */ 1886 if (++sc->calib_cnt >= 120) { 1887 uint32_t flags = 0; 1888 1889 DPRINTFN(2, ("sending request for statistics\n")); 1890 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1891 sizeof flags, 1); 1892 sc->calib_cnt = 0; 1893 } 1894 splx(s); 1895 1896 /* Automatic rate control triggered every 500ms. */ 1897 timeout_add_msec(&sc->calib_to, 500); 1898 } 1899 1900 int 1901 iwn_ccmp_decap(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1902 { 1903 struct ieee80211com *ic = &sc->sc_ic; 1904 struct ieee80211_key *k = &ni->ni_pairwise_key; 1905 struct ieee80211_frame *wh; 1906 struct ieee80211_rx_ba *ba; 1907 uint64_t pn, *prsc; 1908 uint8_t *ivp; 1909 uint8_t tid; 1910 int hdrlen, hasqos; 1911 1912 wh = mtod(m, struct ieee80211_frame *); 1913 hdrlen = ieee80211_get_hdrlen(wh); 1914 ivp = (uint8_t *)wh + hdrlen; 1915 1916 /* Check that ExtIV bit is be set. */ 1917 if (!(ivp[3] & IEEE80211_WEP_EXTIV)) { 1918 DPRINTF(("CCMP decap ExtIV not set\n")); 1919 return 1; 1920 } 1921 hasqos = ieee80211_has_qos(wh); 1922 tid = hasqos ? ieee80211_get_qos(wh) & IEEE80211_QOS_TID : 0; 1923 ba = hasqos ? &ni->ni_rx_ba[tid] : NULL; 1924 prsc = &k->k_rsc[tid]; 1925 1926 /* Extract the 48-bit PN from the CCMP header. */ 1927 pn = (uint64_t)ivp[0] | 1928 (uint64_t)ivp[1] << 8 | 1929 (uint64_t)ivp[4] << 16 | 1930 (uint64_t)ivp[5] << 24 | 1931 (uint64_t)ivp[6] << 32 | 1932 (uint64_t)ivp[7] << 40; 1933 if (pn <= *prsc) { 1934 if (hasqos && ba->ba_state == IEEE80211_BA_AGREED) { 1935 /* 1936 * This is an A-MPDU subframe. 1937 * Such frames may be received out of order due to 1938 * legitimate retransmissions of failed subframes 1939 * in previous A-MPDUs. Duplicates will be handled 1940 * in ieee80211_inputm() as part of A-MPDU reordering. 1941 */ 1942 } else if (ieee80211_has_seq(wh)) { 1943 /* 1944 * Not necessarily a replayed frame since we did not 1945 * check the sequence number of the 802.11 header yet. 1946 */ 1947 int nrxseq, orxseq; 1948 1949 nrxseq = letoh16(*(u_int16_t *)wh->i_seq) >> 1950 IEEE80211_SEQ_SEQ_SHIFT; 1951 if (hasqos) 1952 orxseq = ni->ni_qos_rxseqs[tid]; 1953 else 1954 orxseq = ni->ni_rxseq; 1955 if (nrxseq < orxseq) { 1956 DPRINTF(("CCMP replayed (n=%d < o=%d)\n", 1957 nrxseq, orxseq)); 1958 ic->ic_stats.is_ccmp_replays++; 1959 return 1; 1960 } 1961 } else { 1962 DPRINTF(("CCMP replayed\n")); 1963 ic->ic_stats.is_ccmp_replays++; 1964 return 1; 1965 } 1966 } 1967 /* Update last seen packet number. */ 1968 *prsc = pn; 1969 1970 /* Clear Protected bit and strip IV. */ 1971 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1972 memmove(mtod(m, caddr_t) + IEEE80211_CCMP_HDRLEN, wh, hdrlen); 1973 m_adj(m, IEEE80211_CCMP_HDRLEN); 1974 /* Strip MIC. */ 1975 m_adj(m, -IEEE80211_CCMP_MICLEN); 1976 return 0; 1977 } 1978 1979 /* 1980 * Process an RX_PHY firmware notification. This is usually immediately 1981 * followed by an MPDU_RX_DONE notification. 1982 */ 1983 void 1984 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1985 struct iwn_rx_data *data) 1986 { 1987 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1988 1989 DPRINTFN(2, ("received PHY stats\n")); 1990 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1991 sizeof (*stat), BUS_DMASYNC_POSTREAD); 1992 1993 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1994 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1995 sc->last_rx_valid = IWN_LAST_RX_VALID; 1996 /* 1997 * The firmware does not send separate RX_PHY 1998 * notifications for A-MPDU subframes. 1999 */ 2000 if (stat->flags & htole16(IWN_STAT_FLAG_AGG)) 2001 sc->last_rx_valid |= IWN_LAST_RX_AMPDU; 2002 } 2003 2004 /* 2005 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 2006 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 2007 */ 2008 void 2009 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2010 struct iwn_rx_data *data, struct mbuf_list *ml) 2011 { 2012 struct iwn_ops *ops = &sc->ops; 2013 struct ieee80211com *ic = &sc->sc_ic; 2014 struct ifnet *ifp = &ic->ic_if; 2015 struct iwn_rx_ring *ring = &sc->rxq; 2016 struct ieee80211_frame *wh; 2017 struct ieee80211_rxinfo rxi; 2018 struct ieee80211_node *ni; 2019 struct ieee80211_channel *bss_chan = NULL; 2020 uint8_t saved_bssid[IEEE80211_ADDR_LEN] = { 0 }; 2021 struct mbuf *m, *m1; 2022 struct iwn_rx_stat *stat; 2023 caddr_t head; 2024 uint32_t flags; 2025 int error, len, rssi; 2026 uint16_t chan; 2027 2028 if (desc->type == IWN_MPDU_RX_DONE) { 2029 /* Check for prior RX_PHY notification. */ 2030 if (!sc->last_rx_valid) { 2031 DPRINTF(("missing RX_PHY\n")); 2032 return; 2033 } 2034 sc->last_rx_valid &= ~IWN_LAST_RX_VALID; 2035 stat = &sc->last_rx_stat; 2036 if ((sc->last_rx_valid & IWN_LAST_RX_AMPDU) && 2037 (stat->flags & htole16(IWN_STAT_FLAG_AGG)) == 0) { 2038 DPRINTF(("missing RX_PHY (expecting A-MPDU)\n")); 2039 return; 2040 } 2041 if ((sc->last_rx_valid & IWN_LAST_RX_AMPDU) == 0 && 2042 (stat->flags & htole16(IWN_STAT_FLAG_AGG))) { 2043 DPRINTF(("missing RX_PHY (unexpected A-MPDU)\n")); 2044 return; 2045 } 2046 } else 2047 stat = (struct iwn_rx_stat *)(desc + 1); 2048 2049 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 2050 BUS_DMASYNC_POSTREAD); 2051 2052 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2053 printf("%s: invalid RX statistic header\n", 2054 sc->sc_dev.dv_xname); 2055 return; 2056 } 2057 if (desc->type == IWN_MPDU_RX_DONE) { 2058 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2059 head = (caddr_t)(mpdu + 1); 2060 len = letoh16(mpdu->len); 2061 } else { 2062 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2063 len = letoh16(stat->len); 2064 } 2065 2066 flags = letoh32(*(uint32_t *)(head + len)); 2067 2068 /* Discard frames with a bad FCS early. */ 2069 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2070 DPRINTFN(2, ("RX flags error %x\n", flags)); 2071 ifp->if_ierrors++; 2072 return; 2073 } 2074 /* Discard frames that are too short. */ 2075 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2076 /* Allow control frames in monitor mode. */ 2077 if (len < sizeof (struct ieee80211_frame_cts)) { 2078 DPRINTF(("frame too short: %d\n", len)); 2079 ic->ic_stats.is_rx_tooshort++; 2080 ifp->if_ierrors++; 2081 return; 2082 } 2083 } else if (len < sizeof (*wh)) { 2084 DPRINTF(("frame too short: %d\n", len)); 2085 ic->ic_stats.is_rx_tooshort++; 2086 ifp->if_ierrors++; 2087 return; 2088 } 2089 2090 m1 = MCLGETI(NULL, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 2091 if (m1 == NULL) { 2092 ic->ic_stats.is_rx_nombuf++; 2093 ifp->if_ierrors++; 2094 return; 2095 } 2096 bus_dmamap_unload(sc->sc_dmat, data->map); 2097 2098 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 2099 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 2100 if (error != 0) { 2101 m_freem(m1); 2102 2103 /* Try to reload the old mbuf. */ 2104 error = bus_dmamap_load(sc->sc_dmat, data->map, 2105 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 2106 BUS_DMA_NOWAIT | BUS_DMA_READ); 2107 if (error != 0) { 2108 panic("%s: could not load old RX mbuf", 2109 sc->sc_dev.dv_xname); 2110 } 2111 /* Physical address may have changed. */ 2112 ring->desc[ring->cur] = 2113 htole32(data->map->dm_segs[0].ds_addr >> 8); 2114 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2115 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2116 BUS_DMASYNC_PREWRITE); 2117 ifp->if_ierrors++; 2118 return; 2119 } 2120 2121 m = data->m; 2122 data->m = m1; 2123 /* Update RX descriptor. */ 2124 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 2125 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2126 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2127 BUS_DMASYNC_PREWRITE); 2128 2129 /* Finalize mbuf. */ 2130 m->m_data = head; 2131 m->m_pkthdr.len = m->m_len = len; 2132 2133 /* 2134 * Grab a reference to the source node. Note that control frames are 2135 * shorter than struct ieee80211_frame but ieee80211_find_rxnode() 2136 * is being careful about control frames. 2137 */ 2138 wh = mtod(m, struct ieee80211_frame *); 2139 if (len < sizeof (*wh) && 2140 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 2141 ic->ic_stats.is_rx_tooshort++; 2142 ifp->if_ierrors++; 2143 m_freem(m); 2144 return; 2145 } 2146 ni = ieee80211_find_rxnode(ic, wh); 2147 2148 rxi.rxi_flags = 0; 2149 if (((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) 2150 && (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 2151 !IEEE80211_IS_MULTICAST(wh->i_addr1) && 2152 (ni->ni_flags & IEEE80211_NODE_RXPROT) && 2153 ni->ni_pairwise_key.k_cipher == IEEE80211_CIPHER_CCMP) { 2154 if ((flags & IWN_RX_CIPHER_MASK) != IWN_RX_CIPHER_CCMP) { 2155 ic->ic_stats.is_ccmp_dec_errs++; 2156 ifp->if_ierrors++; 2157 m_freem(m); 2158 return; 2159 } 2160 /* Check whether decryption was successful or not. */ 2161 if ((desc->type == IWN_MPDU_RX_DONE && 2162 (flags & (IWN_RX_MPDU_DEC | IWN_RX_MPDU_MIC_OK)) != 2163 (IWN_RX_MPDU_DEC | IWN_RX_MPDU_MIC_OK)) || 2164 (desc->type != IWN_MPDU_RX_DONE && 2165 (flags & IWN_RX_DECRYPT_MASK) != IWN_RX_DECRYPT_OK)) { 2166 DPRINTF(("CCMP decryption failed 0x%x\n", flags)); 2167 ic->ic_stats.is_ccmp_dec_errs++; 2168 ifp->if_ierrors++; 2169 m_freem(m); 2170 return; 2171 } 2172 if (iwn_ccmp_decap(sc, m, ni) != 0) { 2173 ifp->if_ierrors++; 2174 m_freem(m); 2175 return; 2176 } 2177 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 2178 } 2179 2180 rssi = ops->get_rssi(stat); 2181 2182 chan = stat->chan; 2183 if (chan > IEEE80211_CHAN_MAX) 2184 chan = IEEE80211_CHAN_MAX; 2185 2186 /* Fix current channel. */ 2187 if (ni == ic->ic_bss) { 2188 /* 2189 * We may switch ic_bss's channel during scans. 2190 * Record the current channel so we can restore it later. 2191 */ 2192 bss_chan = ni->ni_chan; 2193 IEEE80211_ADDR_COPY(&saved_bssid, ni->ni_macaddr); 2194 } 2195 ni->ni_chan = &ic->ic_channels[chan]; 2196 2197 #if NBPFILTER > 0 2198 if (sc->sc_drvbpf != NULL) { 2199 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2200 uint16_t chan_flags; 2201 2202 tap->wr_flags = 0; 2203 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2204 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2205 tap->wr_chan_freq = htole16(ic->ic_channels[chan].ic_freq); 2206 chan_flags = ic->ic_channels[chan].ic_flags; 2207 if (ic->ic_curmode != IEEE80211_MODE_11N) 2208 chan_flags &= ~IEEE80211_CHAN_HT; 2209 tap->wr_chan_flags = htole16(chan_flags); 2210 tap->wr_dbm_antsignal = (int8_t)rssi; 2211 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2212 tap->wr_tsft = stat->tstamp; 2213 if (stat->rflags & IWN_RFLAG_MCS) { 2214 tap->wr_rate = (0x80 | stat->rate); /* HT MCS index */ 2215 } else { 2216 switch (stat->rate) { 2217 /* CCK rates. */ 2218 case 10: tap->wr_rate = 2; break; 2219 case 20: tap->wr_rate = 4; break; 2220 case 55: tap->wr_rate = 11; break; 2221 case 110: tap->wr_rate = 22; break; 2222 /* OFDM rates. */ 2223 case 0xd: tap->wr_rate = 12; break; 2224 case 0xf: tap->wr_rate = 18; break; 2225 case 0x5: tap->wr_rate = 24; break; 2226 case 0x7: tap->wr_rate = 36; break; 2227 case 0x9: tap->wr_rate = 48; break; 2228 case 0xb: tap->wr_rate = 72; break; 2229 case 0x1: tap->wr_rate = 96; break; 2230 case 0x3: tap->wr_rate = 108; break; 2231 /* Unknown rate: should not happen. */ 2232 default: tap->wr_rate = 0; 2233 } 2234 } 2235 2236 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_rxtap_len, 2237 m, BPF_DIRECTION_IN); 2238 } 2239 #endif 2240 2241 /* Send the frame to the 802.11 layer. */ 2242 rxi.rxi_rssi = rssi; 2243 rxi.rxi_tstamp = 0; /* unused */ 2244 ieee80211_inputm(ifp, m, ni, &rxi, ml); 2245 2246 /* 2247 * ieee80211_inputm() might have changed our BSS. 2248 * Restore ic_bss's channel if we are still in the same BSS. 2249 */ 2250 if (ni == ic->ic_bss && IEEE80211_ADDR_EQ(saved_bssid, ni->ni_macaddr)) 2251 ni->ni_chan = bss_chan; 2252 2253 /* Node is no longer needed. */ 2254 ieee80211_release_node(ic, ni); 2255 } 2256 2257 /* Process an incoming Compressed BlockAck. */ 2258 void 2259 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2260 struct iwn_rx_data *data) 2261 { 2262 struct iwn_compressed_ba *cba = (struct iwn_compressed_ba *)(desc + 1); 2263 struct ieee80211com *ic = &sc->sc_ic; 2264 struct ieee80211_node *ni; 2265 struct ieee80211_tx_ba *ba; 2266 struct iwn_node *wn; 2267 struct iwn_tx_ring *txq; 2268 uint16_t ssn, idx; 2269 int qid; 2270 2271 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*cba), 2272 BUS_DMASYNC_POSTREAD); 2273 2274 if (!IEEE80211_ADDR_EQ(ic->ic_bss->ni_macaddr, cba->macaddr)) 2275 return; 2276 2277 ni = ic->ic_bss; 2278 wn = (void *)ni; 2279 2280 qid = le16toh(cba->qid); 2281 if (qid < sc->first_agg_txq || qid >= sc->ntxqs) 2282 return; 2283 2284 txq = &sc->txq[qid]; 2285 ssn = le16toh(cba->ssn); /* BA window starting sequence number */ 2286 idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 2287 2288 /* Protect against a firmware bug where the queue/TID are off. */ 2289 if (qid != sc->first_agg_txq + cba->tid) 2290 return; 2291 /* 2292 * Update Tx rate statistics. 2293 */ 2294 if (ic->ic_state == IEEE80211_S_RUN && cba->nframes_sent > 0) { 2295 uint8_t nframes = cba->nframes_sent; 2296 int read = txq->read; 2297 wn->mn.agglen = 0; 2298 wn->mn.ampdu_size = 0; 2299 /* Add up the lengths of all frames before the window. */ 2300 while (nframes && read != idx) { 2301 struct iwn_tx_data *txdata = &txq->data[read]; 2302 wn->mn.agglen++; 2303 wn->mn.ampdu_size += txdata->totlen + IEEE80211_CRC_LEN; 2304 read = (read + 1) % IWN_TX_RING_COUNT; 2305 nframes--; 2306 } 2307 wn->mn.frames += cba->nframes_sent; 2308 /* If firmware reports a bogus ACK counter, fix it up. */ 2309 if (cba->nframes_acked > cba->nframes_sent) 2310 cba->nframes_acked = cba->nframes_sent; 2311 wn->mn.retries += cba->nframes_sent - cba->nframes_acked; 2312 if (wn->mn.txfail > wn->mn.frames) 2313 wn->mn.txfail = wn->mn.frames; 2314 if (wn->mn.ampdu_size > 0) 2315 ieee80211_mira_choose(&wn->mn, ic, ni); 2316 } 2317 2318 ba = &ni->ni_tx_ba[cba->tid]; 2319 2320 if (!SEQ_LT(ssn, ba->ba_winstart)) { 2321 ieee80211_output_ba_move_window(ic, ni, cba->tid, ssn); 2322 iwn_ampdu_txq_advance(sc, txq, qid, 2323 IWN_AGG_SSN_TO_TXQ_IDX(ssn)); 2324 iwn_clear_oactive(sc, txq); 2325 } 2326 } 2327 2328 /* 2329 * Process a CALIBRATION_RESULT notification sent by the initialization 2330 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2331 */ 2332 void 2333 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2334 struct iwn_rx_data *data) 2335 { 2336 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2337 int len, idx = -1; 2338 2339 /* Runtime firmware should not send such a notification. */ 2340 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2341 return; 2342 2343 len = (letoh32(desc->len) & IWN_RX_DESC_LEN_MASK) - 4; 2344 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2345 BUS_DMASYNC_POSTREAD); 2346 2347 switch (calib->code) { 2348 case IWN5000_PHY_CALIB_DC: 2349 if (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2350 sc->hw_type == IWN_HW_REV_TYPE_2030 || 2351 sc->hw_type == IWN_HW_REV_TYPE_2000 || 2352 sc->hw_type == IWN_HW_REV_TYPE_135 || 2353 sc->hw_type == IWN_HW_REV_TYPE_105) 2354 idx = 0; 2355 break; 2356 case IWN5000_PHY_CALIB_LO: 2357 idx = 1; 2358 break; 2359 case IWN5000_PHY_CALIB_TX_IQ: 2360 idx = 2; 2361 break; 2362 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2363 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2364 sc->hw_type != IWN_HW_REV_TYPE_5150) 2365 idx = 3; 2366 break; 2367 case IWN5000_PHY_CALIB_BASE_BAND: 2368 idx = 4; 2369 break; 2370 } 2371 if (idx == -1) /* Ignore other results. */ 2372 return; 2373 2374 /* Save calibration result. */ 2375 if (sc->calibcmd[idx].buf != NULL) 2376 free(sc->calibcmd[idx].buf, M_DEVBUF, 0); 2377 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2378 if (sc->calibcmd[idx].buf == NULL) { 2379 DPRINTF(("not enough memory for calibration result %d\n", 2380 calib->code)); 2381 return; 2382 } 2383 DPRINTF(("saving calibration result code=%d len=%d\n", 2384 calib->code, len)); 2385 sc->calibcmd[idx].len = len; 2386 memcpy(sc->calibcmd[idx].buf, calib, len); 2387 } 2388 2389 /* 2390 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2391 * The latter is sent by the firmware after each received beacon. 2392 */ 2393 void 2394 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2395 struct iwn_rx_data *data) 2396 { 2397 struct iwn_ops *ops = &sc->ops; 2398 struct ieee80211com *ic = &sc->sc_ic; 2399 struct iwn_calib_state *calib = &sc->calib; 2400 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2401 int temp; 2402 2403 /* Ignore statistics received during a scan. */ 2404 if (ic->ic_state != IEEE80211_S_RUN) 2405 return; 2406 2407 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2408 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2409 2410 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2411 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2412 2413 /* Test if temperature has changed. */ 2414 if (stats->general.temp != sc->rawtemp) { 2415 /* Convert "raw" temperature to degC. */ 2416 sc->rawtemp = stats->general.temp; 2417 temp = ops->get_temperature(sc); 2418 DPRINTFN(2, ("temperature=%dC\n", temp)); 2419 2420 /* Update TX power if need be (4965AGN only). */ 2421 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2422 iwn4965_power_calibration(sc, temp); 2423 } 2424 2425 if (desc->type != IWN_BEACON_STATISTICS) 2426 return; /* Reply to a statistics request. */ 2427 2428 sc->noise = iwn_get_noise(&stats->rx.general); 2429 2430 /* Test that RSSI and noise are present in stats report. */ 2431 if (letoh32(stats->rx.general.flags) != 1) { 2432 DPRINTF(("received statistics without RSSI\n")); 2433 return; 2434 } 2435 2436 /* 2437 * XXX Differential gain calibration makes the 6005 firmware 2438 * crap out, so skip it for now. This effectively disables 2439 * sensitivity tuning as well. 2440 */ 2441 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 2442 return; 2443 2444 if (calib->state == IWN_CALIB_STATE_ASSOC) 2445 iwn_collect_noise(sc, &stats->rx.general); 2446 else if (calib->state == IWN_CALIB_STATE_RUN) 2447 iwn_tune_sensitivity(sc, &stats->rx); 2448 } 2449 2450 void 2451 iwn_ampdu_txq_advance(struct iwn_softc *sc, struct iwn_tx_ring *txq, int qid, 2452 int idx) 2453 { 2454 struct iwn_ops *ops = &sc->ops; 2455 2456 DPRINTFN(3, ("%s: txq->cur=%d txq->read=%d txq->queued=%d qid=%d " 2457 "idx=%d\n", __func__, txq->cur, txq->read, txq->queued, qid, idx)); 2458 2459 while (txq->read != idx) { 2460 struct iwn_tx_data *txdata = &txq->data[txq->read]; 2461 if (txdata->m != NULL) { 2462 ops->reset_sched(sc, qid, txq->read); 2463 iwn_tx_done_free_txdata(sc, txdata); 2464 txq->queued--; 2465 } 2466 txq->read = (txq->read + 1) % IWN_TX_RING_COUNT; 2467 } 2468 } 2469 2470 /* 2471 * Handle A-MPDU Tx queue status report. 2472 * Tx failures come as single frames (perhaps out of order), and before failing 2473 * an A-MPDU subframe the firmware transmits it as a single frame at least once 2474 * and reports Tx success/failure here. Frames successfully transmitted in an 2475 * A-MPDU are completed when a compressed block ack notification is received. 2476 */ 2477 void 2478 iwn_ampdu_tx_done(struct iwn_softc *sc, struct iwn_tx_ring *txq, 2479 struct iwn_rx_desc *desc, uint16_t status, 2480 struct iwn_txagg_status *agg_status, int nframes, uint32_t ssn) 2481 { 2482 struct ieee80211com *ic = &sc->sc_ic; 2483 int tid = desc->qid - sc->first_agg_txq; 2484 struct iwn_tx_data *txdata = &txq->data[desc->idx]; 2485 struct ieee80211_node *ni = txdata->ni; 2486 struct iwn_node *wn = (void *)ni; 2487 int txfail = (status != IWN_TX_STATUS_SUCCESS && 2488 status != IWN_TX_STATUS_DIRECT_DONE); 2489 struct ieee80211_tx_ba *ba; 2490 2491 sc->sc_tx_timer = 0; 2492 2493 if (ic->ic_state != IEEE80211_S_RUN || nframes > 1 || ni == NULL) 2494 return; 2495 2496 ba = &ni->ni_tx_ba[tid]; 2497 2498 /* This is a final single-frame Tx attempt. */ 2499 DPRINTFN(3, ("%s: final tx status=0x%x qid=%d queued=%d idx=%d ssn=%u " 2500 "bitmap=0x%llx\n", __func__, status, desc->qid, txq->queued, 2501 desc->idx, ssn, ba->ba_bitmap)); 2502 2503 wn->mn.frames++; 2504 wn->mn.ampdu_size = txdata->totlen + IEEE80211_CRC_LEN; 2505 wn->mn.agglen = 1; 2506 if (txfail) 2507 wn->mn.txfail++; 2508 if (wn->mn.txfail > wn->mn.frames) 2509 wn->mn.txfail = wn->mn.frames; 2510 ieee80211_mira_choose(&wn->mn, ic, ni); 2511 2512 if (txfail) 2513 ieee80211_tx_compressed_bar(ic, ni, tid, ssn); 2514 else if (!SEQ_LT(ssn, ba->ba_winstart)) { 2515 /* 2516 * Move window forward if SSN lies beyond end of window, 2517 * otherwise we can't record the ACK for this frame. 2518 * Non-acked frames which left holes in the bitmap near 2519 * the beginning of the window must be discarded. 2520 */ 2521 uint16_t s = ssn; 2522 while (SEQ_LT(ba->ba_winend, s)) { 2523 ieee80211_output_ba_move_window(ic, ni, tid, s); 2524 iwn_ampdu_txq_advance(sc, txq, desc->qid, 2525 IWN_AGG_SSN_TO_TXQ_IDX(s)); 2526 s = (s + 1) % 0xfff; 2527 } 2528 /* SSN should now be within the window; set corresponding bit. */ 2529 ieee80211_output_ba_record_ack(ic, ni, tid, ssn); 2530 } 2531 2532 /* Move window forward up to the first hole in the bitmap. */ 2533 ieee80211_output_ba_move_window_to_first_unacked(ic, ni, tid, ssn); 2534 iwn_ampdu_txq_advance(sc, txq, desc->qid, 2535 IWN_AGG_SSN_TO_TXQ_IDX(ba->ba_winstart)); 2536 2537 iwn_clear_oactive(sc, txq); 2538 } 2539 2540 /* 2541 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2542 * and 5000 adapters have different incompatible TX status formats. 2543 */ 2544 void 2545 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2546 struct iwn_rx_data *data) 2547 { 2548 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2549 struct iwn_tx_ring *ring; 2550 size_t len = (letoh32(desc->len) & IWN_RX_DESC_LEN_MASK); 2551 uint16_t status = letoh32(stat->stat.status) & 0xff; 2552 uint32_t ssn; 2553 2554 if (desc->qid > IWN4965_NTXQUEUES) 2555 return; 2556 2557 ring = &sc->txq[desc->qid]; 2558 2559 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2560 len, BUS_DMASYNC_POSTREAD); 2561 2562 /* Sanity checks. */ 2563 if (sizeof(*stat) > len) 2564 return; 2565 if (stat->nframes < 1 || stat->nframes > IWN_AMPDU_MAX) 2566 return; 2567 if (desc->qid < sc->first_agg_txq && stat->nframes > 1) 2568 return; 2569 if (desc->qid >= sc->first_agg_txq && sizeof(*stat) + sizeof(ssn) + 2570 stat->nframes * sizeof(stat->stat) > len) 2571 return; 2572 2573 if (desc->qid < sc->first_agg_txq) { 2574 /* XXX 4965 does not report byte count */ 2575 struct iwn_tx_data *txdata = &ring->data[desc->idx]; 2576 uint16_t framelen = txdata->totlen + IEEE80211_CRC_LEN; 2577 int txfail = (status != IWN_TX_STATUS_SUCCESS && 2578 status != IWN_TX_STATUS_DIRECT_DONE); 2579 2580 iwn_tx_done(sc, desc, stat->ackfailcnt, txfail, desc->qid, 2581 framelen); 2582 } else { 2583 memcpy(&ssn, &stat->stat.status + stat->nframes, sizeof(ssn)); 2584 ssn = le32toh(ssn) & 0xfff; 2585 iwn_ampdu_tx_done(sc, ring, desc, status, stat->stat.agg_status, 2586 stat->nframes, ssn); 2587 } 2588 } 2589 2590 void 2591 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2592 struct iwn_rx_data *data) 2593 { 2594 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2595 struct iwn_tx_ring *ring; 2596 size_t len = (letoh32(desc->len) & IWN_RX_DESC_LEN_MASK); 2597 uint16_t status = letoh32(stat->stat.status) & 0xff; 2598 uint32_t ssn; 2599 2600 if (desc->qid > IWN5000_NTXQUEUES) 2601 return; 2602 2603 ring = &sc->txq[desc->qid]; 2604 2605 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2606 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2607 2608 /* Sanity checks. */ 2609 if (sizeof(*stat) > len) 2610 return; 2611 if (stat->nframes < 1 || stat->nframes > IWN_AMPDU_MAX) 2612 return; 2613 if (desc->qid < sc->first_agg_txq && stat->nframes > 1) 2614 return; 2615 if (desc->qid >= sc->first_agg_txq && sizeof(*stat) + sizeof(ssn) + 2616 stat->nframes * sizeof(stat->stat) > len) 2617 return; 2618 2619 /* If this was not an aggregated frame, complete it now. */ 2620 if (desc->qid < sc->first_agg_txq) { 2621 int txfail = (status != IWN_TX_STATUS_SUCCESS && 2622 status != IWN_TX_STATUS_DIRECT_DONE); 2623 2624 /* Reset TX scheduler slot. */ 2625 iwn5000_reset_sched(sc, desc->qid, desc->idx); 2626 2627 iwn_tx_done(sc, desc, stat->ackfailcnt, txfail, desc->qid, 2628 letoh16(stat->len)); 2629 } else { 2630 memcpy(&ssn, &stat->stat.status + stat->nframes, sizeof(ssn)); 2631 ssn = le32toh(ssn) & 0xfff; 2632 iwn_ampdu_tx_done(sc, ring, desc, status, stat->stat.agg_status, 2633 stat->nframes, ssn); 2634 } 2635 } 2636 2637 void 2638 iwn_tx_done_free_txdata(struct iwn_softc *sc, struct iwn_tx_data *data) 2639 { 2640 struct ieee80211com *ic = &sc->sc_ic; 2641 2642 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2643 BUS_DMASYNC_POSTWRITE); 2644 bus_dmamap_unload(sc->sc_dmat, data->map); 2645 m_freem(data->m); 2646 data->m = NULL; 2647 ieee80211_release_node(ic, data->ni); 2648 data->ni = NULL; 2649 data->totlen = 0; 2650 } 2651 2652 void 2653 iwn_clear_oactive(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2654 { 2655 struct ieee80211com *ic = &sc->sc_ic; 2656 struct ifnet *ifp = &ic->ic_if; 2657 2658 if (ring->queued < IWN_TX_RING_LOMARK) { 2659 sc->qfullmsk &= ~(1 << ring->qid); 2660 if (sc->qfullmsk == 0 && ifq_is_oactive(&ifp->if_snd)) { 2661 ifq_clr_oactive(&ifp->if_snd); 2662 (*ifp->if_start)(ifp); 2663 } 2664 } 2665 } 2666 2667 /* 2668 * Adapter-independent backend for TX_DONE firmware notifications. 2669 * This handles Tx status for non-aggregation queues. 2670 */ 2671 void 2672 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2673 uint8_t ackfailcnt, int txfail, int qid, uint16_t len) 2674 { 2675 struct ieee80211com *ic = &sc->sc_ic; 2676 struct ifnet *ifp = &ic->ic_if; 2677 struct iwn_tx_ring *ring = &sc->txq[qid]; 2678 struct iwn_tx_data *data = &ring->data[desc->idx]; 2679 struct iwn_node *wn = (void *)data->ni; 2680 2681 if (data->ni == NULL) 2682 return; 2683 2684 /* Update rate control statistics. */ 2685 if (data->ni->ni_flags & IEEE80211_NODE_HT) { 2686 wn->mn.frames++; 2687 wn->mn.ampdu_size = len; 2688 wn->mn.agglen = 1; 2689 if (ackfailcnt > 0) 2690 wn->mn.retries += ackfailcnt; 2691 if (txfail) 2692 wn->mn.txfail++; 2693 if (ic->ic_state == IEEE80211_S_RUN) { 2694 if (wn->mn.retries > wn->mn.frames) 2695 wn->mn.retries = wn->mn.frames; 2696 if (wn->mn.txfail > wn->mn.frames) 2697 wn->mn.txfail = wn->mn.frames; 2698 ieee80211_mira_choose(&wn->mn, ic, data->ni); 2699 } 2700 } else { 2701 wn->amn.amn_txcnt++; 2702 if (ackfailcnt > 0) 2703 wn->amn.amn_retrycnt++; 2704 } 2705 if (txfail) 2706 ifp->if_oerrors++; 2707 2708 iwn_tx_done_free_txdata(sc, data); 2709 2710 sc->sc_tx_timer = 0; 2711 ring->queued--; 2712 iwn_clear_oactive(sc, ring); 2713 } 2714 2715 /* 2716 * Process a "command done" firmware notification. This is where we wakeup 2717 * processes waiting for a synchronous command completion. 2718 */ 2719 void 2720 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2721 { 2722 struct iwn_tx_ring *ring = &sc->txq[4]; 2723 struct iwn_tx_data *data; 2724 2725 if ((desc->qid & 0xf) != 4) 2726 return; /* Not a command ack. */ 2727 2728 data = &ring->data[desc->idx]; 2729 2730 /* If the command was mapped in an mbuf, free it. */ 2731 if (data->m != NULL) { 2732 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2733 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2734 bus_dmamap_unload(sc->sc_dmat, data->map); 2735 m_freem(data->m); 2736 data->m = NULL; 2737 } 2738 wakeup(&ring->desc[desc->idx]); 2739 } 2740 2741 /* 2742 * Process an INT_FH_RX or INT_SW_RX interrupt. 2743 */ 2744 void 2745 iwn_notif_intr(struct iwn_softc *sc) 2746 { 2747 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2748 struct iwn_ops *ops = &sc->ops; 2749 struct ieee80211com *ic = &sc->sc_ic; 2750 struct ifnet *ifp = &ic->ic_if; 2751 uint16_t hw; 2752 2753 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2754 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2755 2756 hw = letoh16(sc->rxq.stat->closed_count) & 0xfff; 2757 while (sc->rxq.cur != hw) { 2758 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2759 struct iwn_rx_desc *desc; 2760 2761 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2762 BUS_DMASYNC_POSTREAD); 2763 desc = mtod(data->m, struct iwn_rx_desc *); 2764 2765 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2766 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2767 2768 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2769 iwn_cmd_done(sc, desc); 2770 2771 switch (desc->type) { 2772 case IWN_RX_PHY: 2773 iwn_rx_phy(sc, desc, data); 2774 break; 2775 2776 case IWN_RX_DONE: /* 4965AGN only. */ 2777 case IWN_MPDU_RX_DONE: 2778 /* An 802.11 frame has been received. */ 2779 iwn_rx_done(sc, desc, data, &ml); 2780 break; 2781 case IWN_RX_COMPRESSED_BA: 2782 /* A Compressed BlockAck has been received. */ 2783 iwn_rx_compressed_ba(sc, desc, data); 2784 break; 2785 case IWN_TX_DONE: 2786 /* An 802.11 frame has been transmitted. */ 2787 ops->tx_done(sc, desc, data); 2788 break; 2789 2790 case IWN_RX_STATISTICS: 2791 case IWN_BEACON_STATISTICS: 2792 iwn_rx_statistics(sc, desc, data); 2793 break; 2794 2795 case IWN_BEACON_MISSED: 2796 { 2797 struct iwn_beacon_missed *miss = 2798 (struct iwn_beacon_missed *)(desc + 1); 2799 uint32_t missed; 2800 2801 if ((ic->ic_opmode != IEEE80211_M_STA) || 2802 (ic->ic_state != IEEE80211_S_RUN)) 2803 break; 2804 2805 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2806 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2807 missed = letoh32(miss->consecutive); 2808 2809 /* 2810 * If more than 5 consecutive beacons are missed, 2811 * reinitialize the sensitivity state machine. 2812 */ 2813 if (missed > 5) 2814 (void)iwn_init_sensitivity(sc); 2815 2816 /* 2817 * Rather than go directly to scan state, try to send a 2818 * directed probe request first. If that fails then the 2819 * state machine will drop us into scanning after timing 2820 * out waiting for a probe response. 2821 */ 2822 if (missed > ic->ic_bmissthres && !ic->ic_mgt_timer) { 2823 if (ic->ic_if.if_flags & IFF_DEBUG) 2824 printf("%s: receiving no beacons from " 2825 "%s; checking if this AP is still " 2826 "responding to probe requests\n", 2827 sc->sc_dev.dv_xname, ether_sprintf( 2828 ic->ic_bss->ni_macaddr)); 2829 IEEE80211_SEND_MGMT(ic, ic->ic_bss, 2830 IEEE80211_FC0_SUBTYPE_PROBE_REQ, 0); 2831 } 2832 break; 2833 } 2834 case IWN_UC_READY: 2835 { 2836 struct iwn_ucode_info *uc = 2837 (struct iwn_ucode_info *)(desc + 1); 2838 2839 /* The microcontroller is ready. */ 2840 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2841 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2842 DPRINTF(("microcode alive notification version=%d.%d " 2843 "subtype=%x alive=%x\n", uc->major, uc->minor, 2844 uc->subtype, letoh32(uc->valid))); 2845 2846 if (letoh32(uc->valid) != 1) { 2847 printf("%s: microcontroller initialization " 2848 "failed\n", sc->sc_dev.dv_xname); 2849 break; 2850 } 2851 if (uc->subtype == IWN_UCODE_INIT) { 2852 /* Save microcontroller report. */ 2853 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2854 } 2855 /* Save the address of the error log in SRAM. */ 2856 sc->errptr = letoh32(uc->errptr); 2857 break; 2858 } 2859 case IWN_STATE_CHANGED: 2860 { 2861 uint32_t *status = (uint32_t *)(desc + 1); 2862 2863 /* Enabled/disabled notification. */ 2864 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2865 sizeof (*status), BUS_DMASYNC_POSTREAD); 2866 DPRINTF(("state changed to %x\n", letoh32(*status))); 2867 2868 if (letoh32(*status) & 1) { 2869 /* Radio transmitter is off, power down. */ 2870 iwn_stop(ifp); 2871 return; /* No further processing. */ 2872 } 2873 break; 2874 } 2875 case IWN_START_SCAN: 2876 { 2877 struct iwn_start_scan *scan = 2878 (struct iwn_start_scan *)(desc + 1); 2879 2880 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2881 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2882 DPRINTFN(2, ("scanning channel %d status %x\n", 2883 scan->chan, letoh32(scan->status))); 2884 2885 if (sc->sc_flags & IWN_FLAG_BGSCAN) 2886 break; 2887 2888 /* Fix current channel. */ 2889 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 2890 break; 2891 } 2892 case IWN_STOP_SCAN: 2893 { 2894 struct iwn_stop_scan *scan = 2895 (struct iwn_stop_scan *)(desc + 1); 2896 2897 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2898 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2899 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n", 2900 scan->nchan, scan->status, scan->chan)); 2901 2902 if (scan->status == 1 && scan->chan <= 14 && 2903 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 2904 int error; 2905 /* 2906 * We just finished scanning 2GHz channels, 2907 * start scanning 5GHz ones. 2908 */ 2909 error = iwn_scan(sc, IEEE80211_CHAN_5GHZ, 2910 (sc->sc_flags & IWN_FLAG_BGSCAN) ? 1 : 0); 2911 if (error == 0) 2912 break; 2913 } 2914 sc->sc_flags &= ~IWN_FLAG_SCANNING; 2915 sc->sc_flags &= ~IWN_FLAG_BGSCAN; 2916 ieee80211_end_scan(ifp); 2917 break; 2918 } 2919 case IWN5000_CALIBRATION_RESULT: 2920 iwn5000_rx_calib_results(sc, desc, data); 2921 break; 2922 2923 case IWN5000_CALIBRATION_DONE: 2924 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2925 wakeup(sc); 2926 break; 2927 } 2928 2929 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2930 } 2931 if_input(&sc->sc_ic.ic_if, &ml); 2932 2933 /* Tell the firmware what we have processed. */ 2934 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2935 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2936 } 2937 2938 /* 2939 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2940 * from power-down sleep mode. 2941 */ 2942 void 2943 iwn_wakeup_intr(struct iwn_softc *sc) 2944 { 2945 int qid; 2946 2947 DPRINTF(("ucode wakeup from power-down sleep\n")); 2948 2949 /* Wakeup RX and TX rings. */ 2950 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2951 for (qid = 0; qid < sc->ntxqs; qid++) { 2952 struct iwn_tx_ring *ring = &sc->txq[qid]; 2953 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2954 } 2955 } 2956 2957 #ifdef IWN_DEBUG 2958 /* 2959 * Dump the error log of the firmware when a firmware panic occurs. Although 2960 * we can't debug the firmware because it is neither open source nor free, it 2961 * can help us to identify certain classes of problems. 2962 */ 2963 void 2964 iwn_fatal_intr(struct iwn_softc *sc) 2965 { 2966 struct iwn_fw_dump dump; 2967 int i; 2968 2969 /* Check that the error log address is valid. */ 2970 if (sc->errptr < IWN_FW_DATA_BASE || 2971 sc->errptr + sizeof (dump) > 2972 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 2973 printf("%s: bad firmware error log address 0x%08x\n", 2974 sc->sc_dev.dv_xname, sc->errptr); 2975 return; 2976 } 2977 if (iwn_nic_lock(sc) != 0) { 2978 printf("%s: could not read firmware error log\n", 2979 sc->sc_dev.dv_xname); 2980 return; 2981 } 2982 /* Read firmware error log from SRAM. */ 2983 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2984 sizeof (dump) / sizeof (uint32_t)); 2985 iwn_nic_unlock(sc); 2986 2987 if (dump.valid == 0) { 2988 printf("%s: firmware error log is empty\n", 2989 sc->sc_dev.dv_xname); 2990 return; 2991 } 2992 printf("firmware error log:\n"); 2993 printf(" error type = \"%s\" (0x%08X)\n", 2994 (dump.id < nitems(iwn_fw_errmsg)) ? 2995 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2996 dump.id); 2997 printf(" program counter = 0x%08X\n", dump.pc); 2998 printf(" source line = 0x%08X\n", dump.src_line); 2999 printf(" error data = 0x%08X%08X\n", 3000 dump.error_data[0], dump.error_data[1]); 3001 printf(" branch link = 0x%08X%08X\n", 3002 dump.branch_link[0], dump.branch_link[1]); 3003 printf(" interrupt link = 0x%08X%08X\n", 3004 dump.interrupt_link[0], dump.interrupt_link[1]); 3005 printf(" time = %u\n", dump.time[0]); 3006 3007 /* Dump driver status (TX and RX rings) while we're here. */ 3008 printf("driver status:\n"); 3009 for (i = 0; i < sc->ntxqs; i++) { 3010 struct iwn_tx_ring *ring = &sc->txq[i]; 3011 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 3012 i, ring->qid, ring->cur, ring->queued); 3013 } 3014 printf(" rx ring: cur=%d\n", sc->rxq.cur); 3015 printf(" 802.11 state %d\n", sc->sc_ic.ic_state); 3016 } 3017 #endif 3018 3019 int 3020 iwn_intr(void *arg) 3021 { 3022 struct iwn_softc *sc = arg; 3023 struct ifnet *ifp = &sc->sc_ic.ic_if; 3024 uint32_t r1, r2, tmp; 3025 3026 /* Disable interrupts. */ 3027 IWN_WRITE(sc, IWN_INT_MASK, 0); 3028 3029 /* Read interrupts from ICT (fast) or from registers (slow). */ 3030 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3031 tmp = 0; 3032 while (sc->ict[sc->ict_cur] != 0) { 3033 tmp |= sc->ict[sc->ict_cur]; 3034 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 3035 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 3036 } 3037 tmp = letoh32(tmp); 3038 if (tmp == 0xffffffff) /* Shouldn't happen. */ 3039 tmp = 0; 3040 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 3041 tmp |= 0x8000; 3042 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 3043 r2 = 0; /* Unused. */ 3044 } else { 3045 r1 = IWN_READ(sc, IWN_INT); 3046 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 3047 return 0; /* Hardware gone! */ 3048 r2 = IWN_READ(sc, IWN_FH_INT); 3049 } 3050 if (r1 == 0 && r2 == 0) { 3051 if (ifp->if_flags & IFF_UP) 3052 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 3053 return 0; /* Interrupt not for us. */ 3054 } 3055 3056 /* Acknowledge interrupts. */ 3057 IWN_WRITE(sc, IWN_INT, r1); 3058 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 3059 IWN_WRITE(sc, IWN_FH_INT, r2); 3060 3061 if (r1 & IWN_INT_RF_TOGGLED) { 3062 tmp = IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL; 3063 printf("%s: RF switch: radio %s\n", sc->sc_dev.dv_xname, 3064 tmp ? "enabled" : "disabled"); 3065 if (tmp) 3066 task_add(systq, &sc->init_task); 3067 } 3068 if (r1 & IWN_INT_CT_REACHED) { 3069 printf("%s: critical temperature reached!\n", 3070 sc->sc_dev.dv_xname); 3071 } 3072 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 3073 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 3074 3075 /* Force a complete recalibration on next init. */ 3076 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 3077 3078 /* Dump firmware error log and stop. */ 3079 #ifdef IWN_DEBUG 3080 iwn_fatal_intr(sc); 3081 #endif 3082 iwn_stop(ifp); 3083 task_add(systq, &sc->init_task); 3084 return 1; 3085 } 3086 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 3087 (r2 & IWN_FH_INT_RX)) { 3088 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3089 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 3090 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 3091 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 3092 IWN_INT_PERIODIC_DIS); 3093 iwn_notif_intr(sc); 3094 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 3095 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 3096 IWN_INT_PERIODIC_ENA); 3097 } 3098 } else 3099 iwn_notif_intr(sc); 3100 } 3101 3102 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 3103 if (sc->sc_flags & IWN_FLAG_USE_ICT) 3104 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 3105 wakeup(sc); /* FH DMA transfer completed. */ 3106 } 3107 3108 if (r1 & IWN_INT_ALIVE) 3109 wakeup(sc); /* Firmware is alive. */ 3110 3111 if (r1 & IWN_INT_WAKEUP) 3112 iwn_wakeup_intr(sc); 3113 3114 /* Re-enable interrupts. */ 3115 if (ifp->if_flags & IFF_UP) 3116 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 3117 3118 return 1; 3119 } 3120 3121 /* 3122 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 3123 * 5000 adapters use a slightly different format). 3124 */ 3125 void 3126 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3127 uint16_t len) 3128 { 3129 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 3130 3131 *w = htole16(len + 8); 3132 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3133 (caddr_t)w - sc->sched_dma.vaddr, sizeof (uint16_t), 3134 BUS_DMASYNC_PREWRITE); 3135 if (idx < IWN_SCHED_WINSZ) { 3136 *(w + IWN_TX_RING_COUNT) = *w; 3137 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3138 (caddr_t)(w + IWN_TX_RING_COUNT) - sc->sched_dma.vaddr, 3139 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 3140 } 3141 } 3142 3143 void 3144 iwn4965_reset_sched(struct iwn_softc *sc, int qid, int idx) 3145 { 3146 /* TBD */ 3147 } 3148 3149 void 3150 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3151 uint16_t len) 3152 { 3153 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3154 3155 *w = htole16(id << 12 | (len + 8)); 3156 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3157 (caddr_t)w - sc->sched_dma.vaddr, sizeof (uint16_t), 3158 BUS_DMASYNC_PREWRITE); 3159 if (idx < IWN_SCHED_WINSZ) { 3160 *(w + IWN_TX_RING_COUNT) = *w; 3161 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3162 (caddr_t)(w + IWN_TX_RING_COUNT) - sc->sched_dma.vaddr, 3163 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 3164 } 3165 } 3166 3167 void 3168 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 3169 { 3170 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3171 3172 *w = (*w & htole16(0xf000)) | htole16(1); 3173 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3174 (caddr_t)w - sc->sched_dma.vaddr, sizeof (uint16_t), 3175 BUS_DMASYNC_PREWRITE); 3176 if (idx < IWN_SCHED_WINSZ) { 3177 *(w + IWN_TX_RING_COUNT) = *w; 3178 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3179 (caddr_t)(w + IWN_TX_RING_COUNT) - sc->sched_dma.vaddr, 3180 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 3181 } 3182 } 3183 3184 int 3185 iwn_rval2ridx(int rval) 3186 { 3187 int ridx; 3188 3189 for (ridx = 0; ridx < nitems(iwn_rates); ridx++) { 3190 if (rval == iwn_rates[ridx].rate) 3191 break; 3192 } 3193 3194 return ridx; 3195 } 3196 3197 int 3198 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 3199 { 3200 struct iwn_ops *ops = &sc->ops; 3201 struct ieee80211com *ic = &sc->sc_ic; 3202 struct iwn_node *wn = (void *)ni; 3203 struct iwn_tx_ring *ring; 3204 struct iwn_tx_desc *desc; 3205 struct iwn_tx_data *data; 3206 struct iwn_tx_cmd *cmd; 3207 struct iwn_cmd_data *tx; 3208 const struct iwn_rate *rinfo; 3209 struct ieee80211_frame *wh; 3210 struct ieee80211_key *k = NULL; 3211 enum ieee80211_edca_ac ac; 3212 int qid; 3213 uint32_t flags; 3214 uint16_t qos; 3215 u_int hdrlen; 3216 bus_dma_segment_t *seg; 3217 uint8_t *ivp, tid, ridx, txant, type, subtype; 3218 int i, totlen, hasqos, error, pad; 3219 3220 wh = mtod(m, struct ieee80211_frame *); 3221 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3222 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3223 if (type == IEEE80211_FC0_TYPE_CTL) 3224 hdrlen = sizeof(struct ieee80211_frame_min); 3225 else 3226 hdrlen = ieee80211_get_hdrlen(wh); 3227 3228 if ((hasqos = ieee80211_has_qos(wh))) { 3229 /* Select EDCA Access Category and TX ring for this frame. */ 3230 struct ieee80211_tx_ba *ba; 3231 qos = ieee80211_get_qos(wh); 3232 tid = qos & IEEE80211_QOS_TID; 3233 ac = ieee80211_up_to_ac(ic, tid); 3234 qid = ac; 3235 3236 /* If possible, put this frame on an aggregation queue. */ 3237 if (sc->sc_tx_ba[tid].wn == wn) { 3238 ba = &ni->ni_tx_ba[tid]; 3239 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 3240 ba->ba_state == IEEE80211_BA_AGREED) { 3241 qid = sc->first_agg_txq + tid; 3242 if (sc->qfullmsk & (1 << qid)) { 3243 m_freem(m); 3244 return ENOBUFS; 3245 } 3246 } 3247 } 3248 } else { 3249 qos = 0; 3250 tid = IWN_NONQOS_TID; 3251 ac = EDCA_AC_BE; 3252 qid = ac; 3253 } 3254 3255 ring = &sc->txq[qid]; 3256 desc = &ring->desc[ring->cur]; 3257 data = &ring->data[ring->cur]; 3258 3259 /* Choose a TX rate index. */ 3260 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3261 type != IEEE80211_FC0_TYPE_DATA) 3262 ridx = iwn_rval2ridx(ieee80211_min_basic_rate(ic)); 3263 else if (ic->ic_fixed_mcs != -1) 3264 ridx = sc->fixed_ridx; 3265 else if (ic->ic_fixed_rate != -1) 3266 ridx = sc->fixed_ridx; 3267 else { 3268 if (ni->ni_flags & IEEE80211_NODE_HT) 3269 ridx = iwn_mcs2ridx[ni->ni_txmcs]; 3270 else 3271 ridx = wn->ridx[ni->ni_txrate]; 3272 } 3273 rinfo = &iwn_rates[ridx]; 3274 #if NBPFILTER > 0 3275 if (sc->sc_drvbpf != NULL) { 3276 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3277 uint16_t chan_flags; 3278 3279 tap->wt_flags = 0; 3280 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 3281 chan_flags = ni->ni_chan->ic_flags; 3282 if (ic->ic_curmode != IEEE80211_MODE_11N) 3283 chan_flags &= ~IEEE80211_CHAN_HT; 3284 tap->wt_chan_flags = htole16(chan_flags); 3285 if ((ni->ni_flags & IEEE80211_NODE_HT) && 3286 !IEEE80211_IS_MULTICAST(wh->i_addr1) && 3287 type == IEEE80211_FC0_TYPE_DATA) { 3288 tap->wt_rate = (0x80 | ni->ni_txmcs); 3289 } else 3290 tap->wt_rate = rinfo->rate; 3291 tap->wt_hwqueue = ac; 3292 if ((ic->ic_flags & IEEE80211_F_WEPON) && 3293 (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)) 3294 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3295 3296 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_txtap_len, 3297 m, BPF_DIRECTION_OUT); 3298 } 3299 #endif 3300 3301 totlen = m->m_pkthdr.len; 3302 3303 /* Encrypt the frame if need be. */ 3304 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 3305 /* Retrieve key for TX. */ 3306 k = ieee80211_get_txkey(ic, wh, ni); 3307 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 3308 /* Do software encryption. */ 3309 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 3310 return ENOBUFS; 3311 /* 802.11 header may have moved. */ 3312 wh = mtod(m, struct ieee80211_frame *); 3313 totlen = m->m_pkthdr.len; 3314 3315 } else /* HW appends CCMP MIC. */ 3316 totlen += IEEE80211_CCMP_HDRLEN; 3317 } 3318 3319 data->totlen = totlen; 3320 3321 /* Prepare TX firmware command. */ 3322 cmd = &ring->cmd[ring->cur]; 3323 cmd->code = IWN_CMD_TX_DATA; 3324 cmd->flags = 0; 3325 cmd->qid = ring->qid; 3326 cmd->idx = ring->cur; 3327 3328 tx = (struct iwn_cmd_data *)cmd->data; 3329 /* NB: No need to clear tx, all fields are reinitialized here. */ 3330 tx->scratch = 0; /* clear "scratch" area */ 3331 3332 flags = 0; 3333 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3334 /* Unicast frame, check if an ACK is expected. */ 3335 if (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 3336 IEEE80211_QOS_ACK_POLICY_NOACK) 3337 flags |= IWN_TX_NEED_ACK; 3338 } 3339 if (type == IEEE80211_FC0_TYPE_CTL && 3340 subtype == IEEE80211_FC0_SUBTYPE_BAR) 3341 flags |= (IWN_TX_NEED_ACK | IWN_TX_IMM_BA); 3342 3343 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 3344 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 3345 3346 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 3347 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3348 int rtsthres = ic->ic_rtsthreshold; 3349 if (ni->ni_flags & IEEE80211_NODE_HT) 3350 rtsthres = ieee80211_mira_get_rts_threshold(&wn->mn, 3351 ic, ni, totlen + IEEE80211_CRC_LEN); 3352 3353 /* NB: Group frames are sent using CCK in 802.11b/g/n (2GHz). */ 3354 if (totlen + IEEE80211_CRC_LEN > rtsthres) { 3355 flags |= IWN_TX_NEED_RTS; 3356 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3357 ridx >= IWN_RIDX_OFDM6) { 3358 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3359 flags |= IWN_TX_NEED_CTS; 3360 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3361 flags |= IWN_TX_NEED_RTS; 3362 } 3363 3364 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 3365 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3366 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3367 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 3368 flags |= IWN_TX_NEED_PROTECTION; 3369 } else 3370 flags |= IWN_TX_FULL_TXOP; 3371 } 3372 } 3373 3374 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3375 type != IEEE80211_FC0_TYPE_DATA) 3376 tx->id = sc->broadcast_id; 3377 else 3378 tx->id = wn->id; 3379 3380 if (type == IEEE80211_FC0_TYPE_MGT) { 3381 #ifndef IEEE80211_STA_ONLY 3382 /* Tell HW to set timestamp in probe responses. */ 3383 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3384 flags |= IWN_TX_INSERT_TSTAMP; 3385 #endif 3386 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3387 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3388 tx->timeout = htole16(3); 3389 else 3390 tx->timeout = htole16(2); 3391 } else 3392 tx->timeout = htole16(0); 3393 3394 if (hdrlen & 3) { 3395 /* First segment length must be a multiple of 4. */ 3396 flags |= IWN_TX_NEED_PADDING; 3397 pad = 4 - (hdrlen & 3); 3398 } else 3399 pad = 0; 3400 3401 tx->len = htole16(totlen); 3402 tx->tid = tid; 3403 tx->rts_ntries = 60; 3404 tx->data_ntries = 15; 3405 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3406 3407 if ((ni->ni_flags & IEEE80211_NODE_HT) && 3408 tx->id != sc->broadcast_id) 3409 tx->plcp = rinfo->ht_plcp; 3410 else 3411 tx->plcp = rinfo->plcp; 3412 3413 if ((ni->ni_flags & IEEE80211_NODE_HT) && 3414 tx->id != sc->broadcast_id) { 3415 tx->rflags = rinfo->ht_flags; 3416 if (ni->ni_htcaps & IEEE80211_HTCAP_SGI20) 3417 tx->rflags |= IWN_RFLAG_SGI; 3418 } 3419 else 3420 tx->rflags = rinfo->flags; 3421 if (tx->id == sc->broadcast_id) { 3422 /* Group or management frame. */ 3423 tx->linkq = 0; 3424 /* XXX Alternate between antenna A and B? */ 3425 txant = IWN_LSB(sc->txchainmask); 3426 tx->rflags |= IWN_RFLAG_ANT(txant); 3427 } else { 3428 if (ni->ni_flags & IEEE80211_NODE_HT) 3429 tx->linkq = 7 - ni->ni_txmcs; /* XXX revisit for MIMO */ 3430 else 3431 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1; 3432 flags |= IWN_TX_LINKQ; /* enable MRR */ 3433 } 3434 /* Set physical address of "scratch area". */ 3435 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3436 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3437 3438 /* Copy 802.11 header in TX command. */ 3439 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3440 3441 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 3442 /* Trim 802.11 header and prepend CCMP IV. */ 3443 m_adj(m, hdrlen - IEEE80211_CCMP_HDRLEN); 3444 ivp = mtod(m, uint8_t *); 3445 k->k_tsc++; 3446 ivp[0] = k->k_tsc; 3447 ivp[1] = k->k_tsc >> 8; 3448 ivp[2] = 0; 3449 ivp[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3450 ivp[4] = k->k_tsc >> 16; 3451 ivp[5] = k->k_tsc >> 24; 3452 ivp[6] = k->k_tsc >> 32; 3453 ivp[7] = k->k_tsc >> 40; 3454 3455 tx->security = IWN_CIPHER_CCMP; 3456 if (qid >= sc->first_agg_txq) 3457 flags |= IWN_TX_AMPDU_CCMP; 3458 memcpy(tx->key, k->k_key, k->k_len); 3459 3460 /* TX scheduler includes CCMP MIC len w/5000 Series. */ 3461 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 3462 totlen += IEEE80211_CCMP_MICLEN; 3463 } else { 3464 /* Trim 802.11 header. */ 3465 m_adj(m, hdrlen); 3466 tx->security = 0; 3467 } 3468 tx->flags = htole32(flags); 3469 3470 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3471 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3472 if (error != 0 && error != EFBIG) { 3473 printf("%s: can't map mbuf (error %d)\n", 3474 sc->sc_dev.dv_xname, error); 3475 m_freem(m); 3476 return error; 3477 } 3478 if (error != 0) { 3479 /* Too many DMA segments, linearize mbuf. */ 3480 if (m_defrag(m, M_DONTWAIT)) { 3481 m_freem(m); 3482 return ENOBUFS; 3483 } 3484 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3485 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3486 if (error != 0) { 3487 printf("%s: can't map mbuf (error %d)\n", 3488 sc->sc_dev.dv_xname, error); 3489 m_freem(m); 3490 return error; 3491 } 3492 } 3493 3494 data->m = m; 3495 data->ni = ni; 3496 3497 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 3498 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 3499 3500 /* Fill TX descriptor. */ 3501 desc->nsegs = 1 + data->map->dm_nsegs; 3502 /* First DMA segment is used by the TX command. */ 3503 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3504 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3505 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3506 /* Other DMA segments are for data payload. */ 3507 seg = data->map->dm_segs; 3508 for (i = 1; i <= data->map->dm_nsegs; i++) { 3509 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3510 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3511 seg->ds_len << 4); 3512 seg++; 3513 } 3514 3515 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 3516 BUS_DMASYNC_PREWRITE); 3517 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3518 (caddr_t)cmd - ring->cmd_dma.vaddr, sizeof (*cmd), 3519 BUS_DMASYNC_PREWRITE); 3520 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3521 (caddr_t)desc - ring->desc_dma.vaddr, sizeof (*desc), 3522 BUS_DMASYNC_PREWRITE); 3523 3524 /* Update TX scheduler. */ 3525 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3526 3527 /* Kick TX ring. */ 3528 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3529 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3530 3531 /* Mark TX ring as full if we reach a certain threshold. */ 3532 if (++ring->queued > IWN_TX_RING_HIMARK) 3533 sc->qfullmsk |= 1 << ring->qid; 3534 3535 return 0; 3536 } 3537 3538 void 3539 iwn_start(struct ifnet *ifp) 3540 { 3541 struct iwn_softc *sc = ifp->if_softc; 3542 struct ieee80211com *ic = &sc->sc_ic; 3543 struct ieee80211_node *ni; 3544 struct mbuf *m; 3545 3546 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 3547 return; 3548 3549 for (;;) { 3550 if (sc->qfullmsk != 0) { 3551 ifq_set_oactive(&ifp->if_snd); 3552 break; 3553 } 3554 3555 /* Send pending management frames first. */ 3556 m = mq_dequeue(&ic->ic_mgtq); 3557 if (m != NULL) { 3558 ni = m->m_pkthdr.ph_cookie; 3559 goto sendit; 3560 } 3561 if (ic->ic_state != IEEE80211_S_RUN || 3562 (ic->ic_xflags & IEEE80211_F_TX_MGMT_ONLY)) 3563 break; 3564 3565 /* Encapsulate and send data frames. */ 3566 IFQ_DEQUEUE(&ifp->if_snd, m); 3567 if (m == NULL) 3568 break; 3569 #if NBPFILTER > 0 3570 if (ifp->if_bpf != NULL) 3571 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 3572 #endif 3573 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 3574 continue; 3575 sendit: 3576 #if NBPFILTER > 0 3577 if (ic->ic_rawbpf != NULL) 3578 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 3579 #endif 3580 if (iwn_tx(sc, m, ni) != 0) { 3581 ieee80211_release_node(ic, ni); 3582 ifp->if_oerrors++; 3583 continue; 3584 } 3585 3586 sc->sc_tx_timer = 5; 3587 ifp->if_timer = 1; 3588 } 3589 } 3590 3591 void 3592 iwn_watchdog(struct ifnet *ifp) 3593 { 3594 struct iwn_softc *sc = ifp->if_softc; 3595 3596 ifp->if_timer = 0; 3597 3598 if (sc->sc_tx_timer > 0) { 3599 if (--sc->sc_tx_timer == 0) { 3600 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 3601 iwn_stop(ifp); 3602 ifp->if_oerrors++; 3603 return; 3604 } 3605 ifp->if_timer = 1; 3606 } 3607 3608 ieee80211_watchdog(ifp); 3609 } 3610 3611 int 3612 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3613 { 3614 struct iwn_softc *sc = ifp->if_softc; 3615 struct ieee80211com *ic = &sc->sc_ic; 3616 int s, error = 0; 3617 3618 error = rw_enter(&sc->sc_rwlock, RW_WRITE | RW_INTR); 3619 if (error) 3620 return error; 3621 s = splnet(); 3622 3623 switch (cmd) { 3624 case SIOCSIFADDR: 3625 ifp->if_flags |= IFF_UP; 3626 /* FALLTHROUGH */ 3627 case SIOCSIFFLAGS: 3628 if (ifp->if_flags & IFF_UP) { 3629 if (!(ifp->if_flags & IFF_RUNNING)) 3630 error = iwn_init(ifp); 3631 } else { 3632 if (ifp->if_flags & IFF_RUNNING) 3633 iwn_stop(ifp); 3634 } 3635 break; 3636 3637 case SIOCS80211POWER: 3638 error = ieee80211_ioctl(ifp, cmd, data); 3639 if (error != ENETRESET) 3640 break; 3641 if (ic->ic_state == IEEE80211_S_RUN && 3642 sc->calib.state == IWN_CALIB_STATE_RUN) { 3643 if (ic->ic_flags & IEEE80211_F_PMGTON) 3644 error = iwn_set_pslevel(sc, 0, 3, 0); 3645 else /* back to CAM */ 3646 error = iwn_set_pslevel(sc, 0, 0, 0); 3647 } else { 3648 /* Defer until transition to IWN_CALIB_STATE_RUN. */ 3649 error = 0; 3650 } 3651 break; 3652 3653 default: 3654 error = ieee80211_ioctl(ifp, cmd, data); 3655 } 3656 3657 if (error == ENETRESET) { 3658 error = 0; 3659 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3660 (IFF_UP | IFF_RUNNING)) { 3661 iwn_stop(ifp); 3662 error = iwn_init(ifp); 3663 } 3664 } 3665 3666 splx(s); 3667 rw_exit_write(&sc->sc_rwlock); 3668 return error; 3669 } 3670 3671 /* 3672 * Send a command to the firmware. 3673 */ 3674 int 3675 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3676 { 3677 struct iwn_ops *ops = &sc->ops; 3678 struct iwn_tx_ring *ring = &sc->txq[4]; 3679 struct iwn_tx_desc *desc; 3680 struct iwn_tx_data *data; 3681 struct iwn_tx_cmd *cmd; 3682 struct mbuf *m; 3683 bus_addr_t paddr; 3684 int totlen, error; 3685 3686 desc = &ring->desc[ring->cur]; 3687 data = &ring->data[ring->cur]; 3688 totlen = 4 + size; 3689 3690 if (size > sizeof cmd->data) { 3691 /* Command is too large to fit in a descriptor. */ 3692 if (totlen > MCLBYTES) 3693 return EINVAL; 3694 MGETHDR(m, M_DONTWAIT, MT_DATA); 3695 if (m == NULL) 3696 return ENOMEM; 3697 if (totlen > MHLEN) { 3698 MCLGET(m, M_DONTWAIT); 3699 if (!(m->m_flags & M_EXT)) { 3700 m_freem(m); 3701 return ENOMEM; 3702 } 3703 } 3704 cmd = mtod(m, struct iwn_tx_cmd *); 3705 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3706 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3707 if (error != 0) { 3708 m_freem(m); 3709 return error; 3710 } 3711 data->m = m; 3712 paddr = data->map->dm_segs[0].ds_addr; 3713 } else { 3714 cmd = &ring->cmd[ring->cur]; 3715 paddr = data->cmd_paddr; 3716 } 3717 3718 cmd->code = code; 3719 cmd->flags = 0; 3720 cmd->qid = ring->qid; 3721 cmd->idx = ring->cur; 3722 memcpy(cmd->data, buf, size); 3723 3724 desc->nsegs = 1; 3725 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3726 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3727 3728 if (size > sizeof cmd->data) { 3729 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3730 BUS_DMASYNC_PREWRITE); 3731 } else { 3732 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3733 (caddr_t)cmd - ring->cmd_dma.vaddr, totlen, 3734 BUS_DMASYNC_PREWRITE); 3735 } 3736 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3737 (caddr_t)desc - ring->desc_dma.vaddr, sizeof (*desc), 3738 BUS_DMASYNC_PREWRITE); 3739 3740 /* Update TX scheduler. */ 3741 ops->update_sched(sc, ring->qid, ring->cur, 0, 0); 3742 3743 /* Kick command ring. */ 3744 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3745 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3746 3747 return async ? 0 : tsleep_nsec(desc, PCATCH, "iwncmd", SEC_TO_NSEC(1)); 3748 } 3749 3750 int 3751 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3752 { 3753 struct iwn4965_node_info hnode; 3754 caddr_t src, dst; 3755 3756 /* 3757 * We use the node structure for 5000 Series internally (it is 3758 * a superset of the one for 4965AGN). We thus copy the common 3759 * fields before sending the command. 3760 */ 3761 src = (caddr_t)node; 3762 dst = (caddr_t)&hnode; 3763 memcpy(dst, src, 48); 3764 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3765 memcpy(dst + 48, src + 72, 20); 3766 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3767 } 3768 3769 int 3770 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3771 { 3772 /* Direct mapping. */ 3773 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3774 } 3775 3776 int 3777 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3778 { 3779 struct ieee80211com *ic = &sc->sc_ic; 3780 struct iwn_node *wn = (void *)ni; 3781 struct ieee80211_rateset *rs = &ni->ni_rates; 3782 struct iwn_cmd_link_quality linkq; 3783 const struct iwn_rate *rinfo; 3784 uint8_t txant; 3785 int i, txrate; 3786 3787 /* Use the first valid TX antenna. */ 3788 txant = IWN_LSB(sc->txchainmask); 3789 3790 memset(&linkq, 0, sizeof linkq); 3791 linkq.id = wn->id; 3792 linkq.antmsk_1stream = txant; 3793 linkq.antmsk_2stream = IWN_ANT_AB; 3794 linkq.ampdu_max = IWN_AMPDU_MAX; 3795 linkq.ampdu_threshold = 3; 3796 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3797 3798 if (ni->ni_flags & IEEE80211_NODE_HT) { 3799 /* Fill LQ table with MCS 7 - 0 (XXX revisit for MIMO) */ 3800 i = 0; 3801 for (txrate = 7; txrate >= 0; txrate--) { 3802 rinfo = &iwn_rates[iwn_mcs2ridx[txrate]]; 3803 linkq.retry[i].plcp = rinfo->ht_plcp; 3804 linkq.retry[i].rflags = rinfo->ht_flags; 3805 3806 if (ni->ni_htcaps & IEEE80211_HTCAP_SGI20) 3807 linkq.retry[i].rflags |= IWN_RFLAG_SGI; 3808 3809 /* XXX set correct ant mask for MIMO rates here */ 3810 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3811 3812 if (++i >= IWN_MAX_TX_RETRIES) 3813 break; 3814 } 3815 3816 /* Fill the rest with the lowest basic rate. */ 3817 rinfo = &iwn_rates[iwn_rval2ridx(ieee80211_min_basic_rate(ic))]; 3818 while (i < IWN_MAX_TX_RETRIES) { 3819 linkq.retry[i].plcp = rinfo->plcp; 3820 linkq.retry[i].rflags = rinfo->flags; 3821 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3822 i++; 3823 } 3824 } else { 3825 /* Start at highest available bit-rate. */ 3826 txrate = rs->rs_nrates - 1; 3827 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3828 rinfo = &iwn_rates[wn->ridx[txrate]]; 3829 linkq.retry[i].plcp = rinfo->plcp; 3830 linkq.retry[i].rflags = rinfo->flags; 3831 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3832 /* Next retry at immediate lower bit-rate. */ 3833 if (txrate > 0) 3834 txrate--; 3835 } 3836 } 3837 3838 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3839 } 3840 3841 /* 3842 * Broadcast node is used to send group-addressed and management frames. 3843 */ 3844 int 3845 iwn_add_broadcast_node(struct iwn_softc *sc, int async, int ridx) 3846 { 3847 struct iwn_ops *ops = &sc->ops; 3848 struct iwn_node_info node; 3849 struct iwn_cmd_link_quality linkq; 3850 const struct iwn_rate *rinfo; 3851 uint8_t txant; 3852 int i, error; 3853 3854 memset(&node, 0, sizeof node); 3855 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3856 node.id = sc->broadcast_id; 3857 DPRINTF(("adding broadcast node\n")); 3858 if ((error = ops->add_node(sc, &node, async)) != 0) 3859 return error; 3860 3861 /* Use the first valid TX antenna. */ 3862 txant = IWN_LSB(sc->txchainmask); 3863 3864 memset(&linkq, 0, sizeof linkq); 3865 linkq.id = sc->broadcast_id; 3866 linkq.antmsk_1stream = txant; 3867 linkq.antmsk_2stream = IWN_ANT_AB; 3868 linkq.ampdu_max = IWN_AMPDU_MAX_NO_AGG; 3869 linkq.ampdu_threshold = 3; 3870 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3871 3872 /* Use lowest mandatory bit-rate. */ 3873 rinfo = &iwn_rates[ridx]; 3874 linkq.retry[0].plcp = rinfo->plcp; 3875 linkq.retry[0].rflags = rinfo->flags; 3876 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3877 /* Use same bit-rate for all TX retries. */ 3878 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3879 linkq.retry[i].plcp = linkq.retry[0].plcp; 3880 linkq.retry[i].rflags = linkq.retry[0].rflags; 3881 } 3882 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3883 } 3884 3885 void 3886 iwn_updateedca(struct ieee80211com *ic) 3887 { 3888 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 3889 struct iwn_softc *sc = ic->ic_softc; 3890 struct iwn_edca_params cmd; 3891 int aci; 3892 3893 memset(&cmd, 0, sizeof cmd); 3894 cmd.flags = htole32(IWN_EDCA_UPDATE); 3895 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 3896 const struct ieee80211_edca_ac_params *ac = 3897 &ic->ic_edca_ac[aci]; 3898 cmd.ac[aci].aifsn = ac->ac_aifsn; 3899 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->ac_ecwmin)); 3900 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->ac_ecwmax)); 3901 cmd.ac[aci].txoplimit = 3902 htole16(IEEE80211_TXOP_TO_US(ac->ac_txoplimit)); 3903 } 3904 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 3905 #undef IWN_EXP2 3906 } 3907 3908 void 3909 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3910 { 3911 struct iwn_cmd_led led; 3912 3913 /* Clear microcode LED ownership. */ 3914 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3915 3916 led.which = which; 3917 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3918 led.off = off; 3919 led.on = on; 3920 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3921 } 3922 3923 /* 3924 * Set the critical temperature at which the firmware will stop the radio 3925 * and notify us. 3926 */ 3927 int 3928 iwn_set_critical_temp(struct iwn_softc *sc) 3929 { 3930 struct iwn_critical_temp crit; 3931 int32_t temp; 3932 3933 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3934 3935 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3936 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3937 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3938 temp = IWN_CTOK(110); 3939 else 3940 temp = 110; 3941 memset(&crit, 0, sizeof crit); 3942 crit.tempR = htole32(temp); 3943 DPRINTF(("setting critical temperature to %d\n", temp)); 3944 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3945 } 3946 3947 int 3948 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3949 { 3950 struct iwn_cmd_timing cmd; 3951 uint64_t val, mod; 3952 3953 memset(&cmd, 0, sizeof cmd); 3954 memcpy(&cmd.tstamp, ni->ni_tstamp, sizeof (uint64_t)); 3955 cmd.bintval = htole16(ni->ni_intval); 3956 cmd.lintval = htole16(10); 3957 3958 /* Compute remaining time until next beacon. */ 3959 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 3960 mod = letoh64(cmd.tstamp) % val; 3961 cmd.binitval = htole32((uint32_t)(val - mod)); 3962 3963 DPRINTF(("timing bintval=%u, tstamp=%llu, init=%u\n", 3964 ni->ni_intval, letoh64(cmd.tstamp), (uint32_t)(val - mod))); 3965 3966 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3967 } 3968 3969 void 3970 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3971 { 3972 /* Adjust TX power if need be (delta >= 3 degC). */ 3973 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 3974 if (abs(temp - sc->temp) >= 3) { 3975 /* Record temperature of last calibration. */ 3976 sc->temp = temp; 3977 (void)iwn4965_set_txpower(sc, 1); 3978 } 3979 } 3980 3981 /* 3982 * Set TX power for current channel (each rate has its own power settings). 3983 * This function takes into account the regulatory information from EEPROM, 3984 * the current temperature and the current voltage. 3985 */ 3986 int 3987 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3988 { 3989 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3990 #define fdivround(a, b, n) \ 3991 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3992 /* Linear interpolation. */ 3993 #define interpolate(x, x1, y1, x2, y2, n) \ 3994 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3995 3996 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3997 struct ieee80211com *ic = &sc->sc_ic; 3998 struct iwn_ucode_info *uc = &sc->ucode_info; 3999 struct ieee80211_channel *ch; 4000 struct iwn4965_cmd_txpower cmd; 4001 struct iwn4965_eeprom_chan_samples *chans; 4002 const uint8_t *rf_gain, *dsp_gain; 4003 int32_t vdiff, tdiff; 4004 int i, c, grp, maxpwr; 4005 uint8_t chan; 4006 4007 /* Retrieve current channel from last RXON. */ 4008 chan = sc->rxon.chan; 4009 DPRINTF(("setting TX power for channel %d\n", chan)); 4010 ch = &ic->ic_channels[chan]; 4011 4012 memset(&cmd, 0, sizeof cmd); 4013 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 4014 cmd.chan = chan; 4015 4016 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 4017 maxpwr = sc->maxpwr5GHz; 4018 rf_gain = iwn4965_rf_gain_5ghz; 4019 dsp_gain = iwn4965_dsp_gain_5ghz; 4020 } else { 4021 maxpwr = sc->maxpwr2GHz; 4022 rf_gain = iwn4965_rf_gain_2ghz; 4023 dsp_gain = iwn4965_dsp_gain_2ghz; 4024 } 4025 4026 /* Compute voltage compensation. */ 4027 vdiff = ((int32_t)letoh32(uc->volt) - sc->eeprom_voltage) / 7; 4028 if (vdiff > 0) 4029 vdiff *= 2; 4030 if (abs(vdiff) > 2) 4031 vdiff = 0; 4032 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 4033 vdiff, letoh32(uc->volt), sc->eeprom_voltage)); 4034 4035 /* Get channel attenuation group. */ 4036 if (chan <= 20) /* 1-20 */ 4037 grp = 4; 4038 else if (chan <= 43) /* 34-43 */ 4039 grp = 0; 4040 else if (chan <= 70) /* 44-70 */ 4041 grp = 1; 4042 else if (chan <= 124) /* 71-124 */ 4043 grp = 2; 4044 else /* 125-200 */ 4045 grp = 3; 4046 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 4047 4048 /* Get channel sub-band. */ 4049 for (i = 0; i < IWN_NBANDS; i++) 4050 if (sc->bands[i].lo != 0 && 4051 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 4052 break; 4053 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 4054 return EINVAL; 4055 chans = sc->bands[i].chans; 4056 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 4057 4058 for (c = 0; c < 2; c++) { 4059 uint8_t power, gain, temp; 4060 int maxchpwr, pwr, ridx, idx; 4061 4062 power = interpolate(chan, 4063 chans[0].num, chans[0].samples[c][1].power, 4064 chans[1].num, chans[1].samples[c][1].power, 1); 4065 gain = interpolate(chan, 4066 chans[0].num, chans[0].samples[c][1].gain, 4067 chans[1].num, chans[1].samples[c][1].gain, 1); 4068 temp = interpolate(chan, 4069 chans[0].num, chans[0].samples[c][1].temp, 4070 chans[1].num, chans[1].samples[c][1].temp, 1); 4071 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 4072 c, power, gain, temp)); 4073 4074 /* Compute temperature compensation. */ 4075 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 4076 DPRINTF(("temperature compensation=%d (current=%d, " 4077 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 4078 4079 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 4080 /* Convert dBm to half-dBm. */ 4081 maxchpwr = sc->maxpwr[chan] * 2; 4082 #ifdef notyet 4083 if (ridx > iwn_mcs2ridx[7] && ridx < iwn_mcs2ridx[16]) 4084 maxchpwr -= 6; /* MIMO 2T: -3dB */ 4085 #endif 4086 4087 pwr = maxpwr; 4088 4089 /* Adjust TX power based on rate. */ 4090 if ((ridx % 8) == 5) 4091 pwr -= 15; /* OFDM48: -7.5dB */ 4092 else if ((ridx % 8) == 6) 4093 pwr -= 17; /* OFDM54: -8.5dB */ 4094 else if ((ridx % 8) == 7) 4095 pwr -= 20; /* OFDM60: -10dB */ 4096 else 4097 pwr -= 10; /* Others: -5dB */ 4098 4099 /* Do not exceed channel max TX power. */ 4100 if (pwr > maxchpwr) 4101 pwr = maxchpwr; 4102 4103 idx = gain - (pwr - power) - tdiff - vdiff; 4104 if (ridx > iwn_mcs2ridx[7]) /* MIMO */ 4105 idx += (int32_t)letoh32(uc->atten[grp][c]); 4106 4107 if (cmd.band == 0) 4108 idx += 9; /* 5GHz */ 4109 if (ridx == IWN_RIDX_MAX) 4110 idx += 5; /* CCK */ 4111 4112 /* Make sure idx stays in a valid range. */ 4113 if (idx < 0) 4114 idx = 0; 4115 else if (idx > IWN4965_MAX_PWR_INDEX) 4116 idx = IWN4965_MAX_PWR_INDEX; 4117 4118 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 4119 c, ridx, idx)); 4120 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 4121 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 4122 } 4123 } 4124 4125 DPRINTF(("setting TX power for chan %d\n", chan)); 4126 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 4127 4128 #undef interpolate 4129 #undef fdivround 4130 } 4131 4132 int 4133 iwn5000_set_txpower(struct iwn_softc *sc, int async) 4134 { 4135 struct iwn5000_cmd_txpower cmd; 4136 4137 /* 4138 * TX power calibration is handled automatically by the firmware 4139 * for 5000 Series. 4140 */ 4141 memset(&cmd, 0, sizeof cmd); 4142 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 4143 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 4144 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 4145 DPRINTF(("setting TX power\n")); 4146 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 4147 } 4148 4149 /* 4150 * Retrieve the maximum RSSI (in dBm) among receivers. 4151 */ 4152 int 4153 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 4154 { 4155 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 4156 uint8_t mask, agc; 4157 int rssi; 4158 4159 mask = (letoh16(phy->antenna) >> 4) & IWN_ANT_ABC; 4160 agc = (letoh16(phy->agc) >> 7) & 0x7f; 4161 4162 rssi = 0; 4163 if (mask & IWN_ANT_A) 4164 rssi = MAX(rssi, phy->rssi[0]); 4165 if (mask & IWN_ANT_B) 4166 rssi = MAX(rssi, phy->rssi[2]); 4167 if (mask & IWN_ANT_C) 4168 rssi = MAX(rssi, phy->rssi[4]); 4169 4170 return rssi - agc - IWN_RSSI_TO_DBM; 4171 } 4172 4173 int 4174 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 4175 { 4176 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 4177 uint8_t agc; 4178 int rssi; 4179 4180 agc = (letoh32(phy->agc) >> 9) & 0x7f; 4181 4182 rssi = MAX(letoh16(phy->rssi[0]) & 0xff, 4183 letoh16(phy->rssi[1]) & 0xff); 4184 rssi = MAX(letoh16(phy->rssi[2]) & 0xff, rssi); 4185 4186 return rssi - agc - IWN_RSSI_TO_DBM; 4187 } 4188 4189 /* 4190 * Retrieve the average noise (in dBm) among receivers. 4191 */ 4192 int 4193 iwn_get_noise(const struct iwn_rx_general_stats *stats) 4194 { 4195 int i, total, nbant, noise; 4196 4197 total = nbant = 0; 4198 for (i = 0; i < 3; i++) { 4199 if ((noise = letoh32(stats->noise[i]) & 0xff) == 0) 4200 continue; 4201 total += noise; 4202 nbant++; 4203 } 4204 /* There should be at least one antenna but check anyway. */ 4205 return (nbant == 0) ? -127 : (total / nbant) - 107; 4206 } 4207 4208 /* 4209 * Compute temperature (in degC) from last received statistics. 4210 */ 4211 int 4212 iwn4965_get_temperature(struct iwn_softc *sc) 4213 { 4214 struct iwn_ucode_info *uc = &sc->ucode_info; 4215 int32_t r1, r2, r3, r4, temp; 4216 4217 r1 = letoh32(uc->temp[0].chan20MHz); 4218 r2 = letoh32(uc->temp[1].chan20MHz); 4219 r3 = letoh32(uc->temp[2].chan20MHz); 4220 r4 = letoh32(sc->rawtemp); 4221 4222 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 4223 return 0; 4224 4225 /* Sign-extend 23-bit R4 value to 32-bit. */ 4226 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 4227 /* Compute temperature in Kelvin. */ 4228 temp = (259 * (r4 - r2)) / (r3 - r1); 4229 temp = (temp * 97) / 100 + 8; 4230 4231 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 4232 return IWN_KTOC(temp); 4233 } 4234 4235 int 4236 iwn5000_get_temperature(struct iwn_softc *sc) 4237 { 4238 int32_t temp; 4239 4240 /* 4241 * Temperature is not used by the driver for 5000 Series because 4242 * TX power calibration is handled by firmware. 4243 */ 4244 temp = letoh32(sc->rawtemp); 4245 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 4246 temp = (temp / -5) + sc->temp_off; 4247 temp = IWN_KTOC(temp); 4248 } 4249 return temp; 4250 } 4251 4252 /* 4253 * Initialize sensitivity calibration state machine. 4254 */ 4255 int 4256 iwn_init_sensitivity(struct iwn_softc *sc) 4257 { 4258 struct iwn_ops *ops = &sc->ops; 4259 struct iwn_calib_state *calib = &sc->calib; 4260 uint32_t flags; 4261 int error; 4262 4263 /* Reset calibration state machine. */ 4264 memset(calib, 0, sizeof (*calib)); 4265 calib->state = IWN_CALIB_STATE_INIT; 4266 calib->cck_state = IWN_CCK_STATE_HIFA; 4267 /* Set initial correlation values. */ 4268 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 4269 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 4270 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 4271 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 4272 calib->cck_x4 = 125; 4273 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 4274 calib->energy_cck = sc->limits->energy_cck; 4275 4276 /* Write initial sensitivity. */ 4277 if ((error = iwn_send_sensitivity(sc)) != 0) 4278 return error; 4279 4280 /* Write initial gains. */ 4281 if ((error = ops->init_gains(sc)) != 0) 4282 return error; 4283 4284 /* Request statistics at each beacon interval. */ 4285 flags = 0; 4286 DPRINTFN(2, ("sending request for statistics\n")); 4287 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 4288 } 4289 4290 /* 4291 * Collect noise and RSSI statistics for the first 20 beacons received 4292 * after association and use them to determine connected antennas and 4293 * to set differential gains. 4294 */ 4295 void 4296 iwn_collect_noise(struct iwn_softc *sc, 4297 const struct iwn_rx_general_stats *stats) 4298 { 4299 struct iwn_ops *ops = &sc->ops; 4300 struct iwn_calib_state *calib = &sc->calib; 4301 uint32_t val; 4302 int i; 4303 4304 /* Accumulate RSSI and noise for all 3 antennas. */ 4305 for (i = 0; i < 3; i++) { 4306 calib->rssi[i] += letoh32(stats->rssi[i]) & 0xff; 4307 calib->noise[i] += letoh32(stats->noise[i]) & 0xff; 4308 } 4309 /* NB: We update differential gains only once after 20 beacons. */ 4310 if (++calib->nbeacons < 20) 4311 return; 4312 4313 /* Determine highest average RSSI. */ 4314 val = MAX(calib->rssi[0], calib->rssi[1]); 4315 val = MAX(calib->rssi[2], val); 4316 4317 /* Determine which antennas are connected. */ 4318 sc->chainmask = sc->rxchainmask; 4319 for (i = 0; i < 3; i++) 4320 if (val - calib->rssi[i] > 15 * 20) 4321 sc->chainmask &= ~(1 << i); 4322 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 4323 sc->rxchainmask, sc->chainmask)); 4324 4325 /* If none of the TX antennas are connected, keep at least one. */ 4326 if ((sc->chainmask & sc->txchainmask) == 0) 4327 sc->chainmask |= IWN_LSB(sc->txchainmask); 4328 4329 (void)ops->set_gains(sc); 4330 calib->state = IWN_CALIB_STATE_RUN; 4331 4332 #ifdef notyet 4333 /* XXX Disable RX chains with no antennas connected. */ 4334 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 4335 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4336 #endif 4337 4338 /* Enable power-saving mode if requested by user. */ 4339 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 4340 (void)iwn_set_pslevel(sc, 0, 3, 1); 4341 } 4342 4343 int 4344 iwn4965_init_gains(struct iwn_softc *sc) 4345 { 4346 struct iwn_phy_calib_gain cmd; 4347 4348 memset(&cmd, 0, sizeof cmd); 4349 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4350 /* Differential gains initially set to 0 for all 3 antennas. */ 4351 DPRINTF(("setting initial differential gains\n")); 4352 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4353 } 4354 4355 int 4356 iwn5000_init_gains(struct iwn_softc *sc) 4357 { 4358 struct iwn_phy_calib cmd; 4359 4360 memset(&cmd, 0, sizeof cmd); 4361 cmd.code = sc->reset_noise_gain; 4362 cmd.ngroups = 1; 4363 cmd.isvalid = 1; 4364 DPRINTF(("setting initial differential gains\n")); 4365 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4366 } 4367 4368 int 4369 iwn4965_set_gains(struct iwn_softc *sc) 4370 { 4371 struct iwn_calib_state *calib = &sc->calib; 4372 struct iwn_phy_calib_gain cmd; 4373 int i, delta, noise; 4374 4375 /* Get minimal noise among connected antennas. */ 4376 noise = INT_MAX; /* NB: There's at least one antenna. */ 4377 for (i = 0; i < 3; i++) 4378 if (sc->chainmask & (1 << i)) 4379 noise = MIN(calib->noise[i], noise); 4380 4381 memset(&cmd, 0, sizeof cmd); 4382 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4383 /* Set differential gains for connected antennas. */ 4384 for (i = 0; i < 3; i++) { 4385 if (sc->chainmask & (1 << i)) { 4386 /* Compute attenuation (in unit of 1.5dB). */ 4387 delta = (noise - (int32_t)calib->noise[i]) / 30; 4388 /* NB: delta <= 0 */ 4389 /* Limit to [-4.5dB,0]. */ 4390 cmd.gain[i] = MIN(abs(delta), 3); 4391 if (delta < 0) 4392 cmd.gain[i] |= 1 << 2; /* sign bit */ 4393 } 4394 } 4395 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 4396 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 4397 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4398 } 4399 4400 int 4401 iwn5000_set_gains(struct iwn_softc *sc) 4402 { 4403 struct iwn_calib_state *calib = &sc->calib; 4404 struct iwn_phy_calib_gain cmd; 4405 int i, ant, div, delta; 4406 4407 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 4408 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 4409 4410 memset(&cmd, 0, sizeof cmd); 4411 cmd.code = sc->noise_gain; 4412 cmd.ngroups = 1; 4413 cmd.isvalid = 1; 4414 /* Get first available RX antenna as referential. */ 4415 ant = IWN_LSB(sc->rxchainmask); 4416 /* Set differential gains for other antennas. */ 4417 for (i = ant + 1; i < 3; i++) { 4418 if (sc->chainmask & (1 << i)) { 4419 /* The delta is relative to antenna "ant". */ 4420 delta = ((int32_t)calib->noise[ant] - 4421 (int32_t)calib->noise[i]) / div; 4422 /* Limit to [-4.5dB,+4.5dB]. */ 4423 cmd.gain[i - 1] = MIN(abs(delta), 3); 4424 if (delta < 0) 4425 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 4426 } 4427 } 4428 DPRINTF(("setting differential gains: %x/%x (%x)\n", 4429 cmd.gain[0], cmd.gain[1], sc->chainmask)); 4430 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4431 } 4432 4433 /* 4434 * Tune RF RX sensitivity based on the number of false alarms detected 4435 * during the last beacon period. 4436 */ 4437 void 4438 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4439 { 4440 #define inc(val, inc, max) \ 4441 if ((val) < (max)) { \ 4442 if ((val) < (max) - (inc)) \ 4443 (val) += (inc); \ 4444 else \ 4445 (val) = (max); \ 4446 needs_update = 1; \ 4447 } 4448 #define dec(val, dec, min) \ 4449 if ((val) > (min)) { \ 4450 if ((val) > (min) + (dec)) \ 4451 (val) -= (dec); \ 4452 else \ 4453 (val) = (min); \ 4454 needs_update = 1; \ 4455 } 4456 4457 const struct iwn_sensitivity_limits *limits = sc->limits; 4458 struct iwn_calib_state *calib = &sc->calib; 4459 uint32_t val, rxena, fa; 4460 uint32_t energy[3], energy_min; 4461 uint8_t noise[3], noise_ref; 4462 int i, needs_update = 0; 4463 4464 /* Check that we've been enabled long enough. */ 4465 if ((rxena = letoh32(stats->general.load)) == 0) 4466 return; 4467 4468 /* Compute number of false alarms since last call for OFDM. */ 4469 fa = letoh32(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4470 fa += letoh32(stats->ofdm.fa) - calib->fa_ofdm; 4471 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4472 4473 /* Save counters values for next call. */ 4474 calib->bad_plcp_ofdm = letoh32(stats->ofdm.bad_plcp); 4475 calib->fa_ofdm = letoh32(stats->ofdm.fa); 4476 4477 if (fa > 50 * rxena) { 4478 /* High false alarm count, decrease sensitivity. */ 4479 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 4480 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4481 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4482 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4483 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4484 4485 } else if (fa < 5 * rxena) { 4486 /* Low false alarm count, increase sensitivity. */ 4487 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 4488 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4489 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4490 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4491 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4492 } 4493 4494 /* Compute maximum noise among 3 receivers. */ 4495 for (i = 0; i < 3; i++) 4496 noise[i] = (letoh32(stats->general.noise[i]) >> 8) & 0xff; 4497 val = MAX(noise[0], noise[1]); 4498 val = MAX(noise[2], val); 4499 /* Insert it into our samples table. */ 4500 calib->noise_samples[calib->cur_noise_sample] = val; 4501 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4502 4503 /* Compute maximum noise among last 20 samples. */ 4504 noise_ref = calib->noise_samples[0]; 4505 for (i = 1; i < 20; i++) 4506 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4507 4508 /* Compute maximum energy among 3 receivers. */ 4509 for (i = 0; i < 3; i++) 4510 energy[i] = letoh32(stats->general.energy[i]); 4511 val = MIN(energy[0], energy[1]); 4512 val = MIN(energy[2], val); 4513 /* Insert it into our samples table. */ 4514 calib->energy_samples[calib->cur_energy_sample] = val; 4515 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4516 4517 /* Compute minimum energy among last 10 samples. */ 4518 energy_min = calib->energy_samples[0]; 4519 for (i = 1; i < 10; i++) 4520 energy_min = MAX(energy_min, calib->energy_samples[i]); 4521 energy_min += 6; 4522 4523 /* Compute number of false alarms since last call for CCK. */ 4524 fa = letoh32(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4525 fa += letoh32(stats->cck.fa) - calib->fa_cck; 4526 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4527 4528 /* Save counters values for next call. */ 4529 calib->bad_plcp_cck = letoh32(stats->cck.bad_plcp); 4530 calib->fa_cck = letoh32(stats->cck.fa); 4531 4532 if (fa > 50 * rxena) { 4533 /* High false alarm count, decrease sensitivity. */ 4534 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 4535 calib->cck_state = IWN_CCK_STATE_HIFA; 4536 calib->low_fa = 0; 4537 4538 if (calib->cck_x4 > 160) { 4539 calib->noise_ref = noise_ref; 4540 if (calib->energy_cck > 2) 4541 dec(calib->energy_cck, 2, energy_min); 4542 } 4543 if (calib->cck_x4 < 160) { 4544 calib->cck_x4 = 161; 4545 needs_update = 1; 4546 } else 4547 inc(calib->cck_x4, 3, limits->max_cck_x4); 4548 4549 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4550 4551 } else if (fa < 5 * rxena) { 4552 /* Low false alarm count, increase sensitivity. */ 4553 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 4554 calib->cck_state = IWN_CCK_STATE_LOFA; 4555 calib->low_fa++; 4556 4557 if (calib->cck_state != IWN_CCK_STATE_INIT && 4558 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4559 calib->low_fa > 100)) { 4560 inc(calib->energy_cck, 2, limits->min_energy_cck); 4561 dec(calib->cck_x4, 3, limits->min_cck_x4); 4562 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4563 } 4564 } else { 4565 /* Not worth to increase or decrease sensitivity. */ 4566 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 4567 calib->low_fa = 0; 4568 calib->noise_ref = noise_ref; 4569 4570 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4571 /* Previous interval had many false alarms. */ 4572 dec(calib->energy_cck, 8, energy_min); 4573 } 4574 calib->cck_state = IWN_CCK_STATE_INIT; 4575 } 4576 4577 if (needs_update) 4578 (void)iwn_send_sensitivity(sc); 4579 #undef dec 4580 #undef inc 4581 } 4582 4583 int 4584 iwn_send_sensitivity(struct iwn_softc *sc) 4585 { 4586 struct iwn_calib_state *calib = &sc->calib; 4587 struct iwn_enhanced_sensitivity_cmd cmd; 4588 int len; 4589 4590 memset(&cmd, 0, sizeof cmd); 4591 len = sizeof (struct iwn_sensitivity_cmd); 4592 cmd.which = IWN_SENSITIVITY_WORKTBL; 4593 /* OFDM modulation. */ 4594 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4595 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4596 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4597 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4598 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4599 cmd.energy_ofdm_th = htole16(62); 4600 /* CCK modulation. */ 4601 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4602 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4603 cmd.energy_cck = htole16(calib->energy_cck); 4604 /* Barker modulation: use default values. */ 4605 cmd.corr_barker = htole16(190); 4606 cmd.corr_barker_mrc = htole16(390); 4607 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 4608 goto send; 4609 /* Enhanced sensitivity settings. */ 4610 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 4611 cmd.ofdm_det_slope_mrc = htole16(668); 4612 cmd.ofdm_det_icept_mrc = htole16(4); 4613 cmd.ofdm_det_slope = htole16(486); 4614 cmd.ofdm_det_icept = htole16(37); 4615 cmd.cck_det_slope_mrc = htole16(853); 4616 cmd.cck_det_icept_mrc = htole16(4); 4617 cmd.cck_det_slope = htole16(476); 4618 cmd.cck_det_icept = htole16(99); 4619 send: 4620 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 4621 } 4622 4623 /* 4624 * Set STA mode power saving level (between 0 and 5). 4625 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4626 */ 4627 int 4628 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4629 { 4630 struct iwn_pmgt_cmd cmd; 4631 const struct iwn_pmgt *pmgt; 4632 uint32_t max, skip_dtim; 4633 pcireg_t reg; 4634 int i; 4635 4636 /* Select which PS parameters to use. */ 4637 if (dtim <= 2) 4638 pmgt = &iwn_pmgt[0][level]; 4639 else if (dtim <= 10) 4640 pmgt = &iwn_pmgt[1][level]; 4641 else 4642 pmgt = &iwn_pmgt[2][level]; 4643 4644 memset(&cmd, 0, sizeof cmd); 4645 if (level != 0) /* not CAM */ 4646 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4647 if (level == 5) 4648 cmd.flags |= htole16(IWN_PS_FAST_PD); 4649 /* Retrieve PCIe Active State Power Management (ASPM). */ 4650 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4651 sc->sc_cap_off + PCI_PCIE_LCSR); 4652 if (!(reg & PCI_PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4653 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4654 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4655 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4656 4657 if (dtim == 0) { 4658 dtim = 1; 4659 skip_dtim = 0; 4660 } else 4661 skip_dtim = pmgt->skip_dtim; 4662 if (skip_dtim != 0) { 4663 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4664 max = pmgt->intval[4]; 4665 if (max == (uint32_t)-1) 4666 max = dtim * (skip_dtim + 1); 4667 else if (max > dtim) 4668 max = (max / dtim) * dtim; 4669 } else 4670 max = dtim; 4671 for (i = 0; i < 5; i++) 4672 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 4673 4674 DPRINTF(("setting power saving level to %d\n", level)); 4675 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4676 } 4677 4678 int 4679 iwn_send_btcoex(struct iwn_softc *sc) 4680 { 4681 struct iwn_bluetooth cmd; 4682 4683 memset(&cmd, 0, sizeof cmd); 4684 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4685 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 4686 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 4687 DPRINTF(("configuring bluetooth coexistence\n")); 4688 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 4689 } 4690 4691 int 4692 iwn_send_advanced_btcoex(struct iwn_softc *sc) 4693 { 4694 static const uint32_t btcoex_3wire[12] = { 4695 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 4696 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 4697 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 4698 }; 4699 struct iwn_btcoex_priotable btprio; 4700 struct iwn_btcoex_prot btprot; 4701 int error, i; 4702 4703 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 4704 sc->hw_type == IWN_HW_REV_TYPE_135) { 4705 struct iwn2000_btcoex_config btconfig; 4706 4707 memset(&btconfig, 0, sizeof btconfig); 4708 btconfig.flags = IWN_BT_COEX6000_CHAN_INHIBITION | 4709 (IWN_BT_COEX6000_MODE_3W << IWN_BT_COEX6000_MODE_SHIFT) | 4710 IWN_BT_SYNC_2_BT_DISABLE; 4711 btconfig.max_kill = 5; 4712 btconfig.bt3_t7_timer = 1; 4713 btconfig.kill_ack = htole32(0xffff0000); 4714 btconfig.kill_cts = htole32(0xffff0000); 4715 btconfig.sample_time = 2; 4716 btconfig.bt3_t2_timer = 0xc; 4717 for (i = 0; i < 12; i++) 4718 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 4719 btconfig.valid = htole16(0xff); 4720 btconfig.prio_boost = htole32(0xf0); 4721 DPRINTF(("configuring advanced bluetooth coexistence\n")); 4722 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 4723 sizeof(btconfig), 1); 4724 if (error != 0) 4725 return (error); 4726 } else { 4727 struct iwn6000_btcoex_config btconfig; 4728 4729 memset(&btconfig, 0, sizeof btconfig); 4730 btconfig.flags = IWN_BT_COEX6000_CHAN_INHIBITION | 4731 (IWN_BT_COEX6000_MODE_3W << IWN_BT_COEX6000_MODE_SHIFT) | 4732 IWN_BT_SYNC_2_BT_DISABLE; 4733 btconfig.max_kill = 5; 4734 btconfig.bt3_t7_timer = 1; 4735 btconfig.kill_ack = htole32(0xffff0000); 4736 btconfig.kill_cts = htole32(0xffff0000); 4737 btconfig.sample_time = 2; 4738 btconfig.bt3_t2_timer = 0xc; 4739 for (i = 0; i < 12; i++) 4740 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 4741 btconfig.valid = htole16(0xff); 4742 btconfig.prio_boost = 0xf0; 4743 DPRINTF(("configuring advanced bluetooth coexistence\n")); 4744 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 4745 sizeof(btconfig), 1); 4746 if (error != 0) 4747 return (error); 4748 } 4749 4750 memset(&btprio, 0, sizeof btprio); 4751 btprio.calib_init1 = 0x6; 4752 btprio.calib_init2 = 0x7; 4753 btprio.calib_periodic_low1 = 0x2; 4754 btprio.calib_periodic_low2 = 0x3; 4755 btprio.calib_periodic_high1 = 0x4; 4756 btprio.calib_periodic_high2 = 0x5; 4757 btprio.dtim = 0x6; 4758 btprio.scan52 = 0x8; 4759 btprio.scan24 = 0xa; 4760 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 4761 1); 4762 if (error != 0) 4763 return (error); 4764 4765 /* Force BT state machine change */ 4766 memset(&btprot, 0, sizeof btprot); 4767 btprot.open = 1; 4768 btprot.type = 1; 4769 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 4770 if (error != 0) 4771 return (error); 4772 4773 btprot.open = 0; 4774 return (iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1)); 4775 } 4776 4777 int 4778 iwn5000_runtime_calib(struct iwn_softc *sc) 4779 { 4780 struct iwn5000_calib_config cmd; 4781 4782 memset(&cmd, 0, sizeof cmd); 4783 cmd.ucode.once.enable = 0xffffffff; 4784 cmd.ucode.once.start = IWN5000_CALIB_DC; 4785 DPRINTF(("configuring runtime calibration\n")); 4786 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 4787 } 4788 4789 int 4790 iwn_config(struct iwn_softc *sc) 4791 { 4792 struct iwn_ops *ops = &sc->ops; 4793 struct ieee80211com *ic = &sc->sc_ic; 4794 struct ifnet *ifp = &ic->ic_if; 4795 uint32_t txmask; 4796 uint16_t rxchain; 4797 int error, ridx; 4798 4799 /* Set radio temperature sensor offset. */ 4800 if (sc->hw_type == IWN_HW_REV_TYPE_6005) { 4801 error = iwn6000_temp_offset_calib(sc); 4802 if (error != 0) { 4803 printf("%s: could not set temperature offset\n", 4804 sc->sc_dev.dv_xname); 4805 return error; 4806 } 4807 } 4808 4809 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 4810 sc->hw_type == IWN_HW_REV_TYPE_2000 || 4811 sc->hw_type == IWN_HW_REV_TYPE_135 || 4812 sc->hw_type == IWN_HW_REV_TYPE_105) { 4813 error = iwn2000_temp_offset_calib(sc); 4814 if (error != 0) { 4815 printf("%s: could not set temperature offset\n", 4816 sc->sc_dev.dv_xname); 4817 return error; 4818 } 4819 } 4820 4821 if (sc->hw_type == IWN_HW_REV_TYPE_6050 || 4822 sc->hw_type == IWN_HW_REV_TYPE_6005) { 4823 /* Configure runtime DC calibration. */ 4824 error = iwn5000_runtime_calib(sc); 4825 if (error != 0) { 4826 printf("%s: could not configure runtime calibration\n", 4827 sc->sc_dev.dv_xname); 4828 return error; 4829 } 4830 } 4831 4832 /* Configure valid TX chains for >=5000 Series. */ 4833 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4834 txmask = htole32(sc->txchainmask); 4835 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 4836 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4837 sizeof txmask, 0); 4838 if (error != 0) { 4839 printf("%s: could not configure valid TX chains\n", 4840 sc->sc_dev.dv_xname); 4841 return error; 4842 } 4843 } 4844 4845 /* Configure bluetooth coexistence. */ 4846 if (sc->sc_flags & IWN_FLAG_ADV_BT_COEX) 4847 error = iwn_send_advanced_btcoex(sc); 4848 else 4849 error = iwn_send_btcoex(sc); 4850 if (error != 0) { 4851 printf("%s: could not configure bluetooth coexistence\n", 4852 sc->sc_dev.dv_xname); 4853 return error; 4854 } 4855 4856 /* Set mode, channel, RX filter and enable RX. */ 4857 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4858 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 4859 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 4860 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 4861 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 4862 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4863 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) { 4864 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4865 if (ic->ic_flags & IEEE80211_F_USEPROT) 4866 sc->rxon.flags |= htole32(IWN_RXON_TGG_PROT); 4867 DPRINTF(("%s: 2ghz prot 0x%x\n", __func__, 4868 le32toh(sc->rxon.flags))); 4869 } 4870 switch (ic->ic_opmode) { 4871 case IEEE80211_M_STA: 4872 sc->rxon.mode = IWN_MODE_STA; 4873 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4874 break; 4875 case IEEE80211_M_MONITOR: 4876 sc->rxon.mode = IWN_MODE_MONITOR; 4877 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4878 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4879 break; 4880 default: 4881 /* Should not get there. */ 4882 break; 4883 } 4884 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4885 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4886 sc->rxon.ht_single_mask = 0xff; 4887 sc->rxon.ht_dual_mask = 0xff; 4888 sc->rxon.ht_triple_mask = 0xff; 4889 rxchain = 4890 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4891 IWN_RXCHAIN_MIMO_COUNT(sc->nrxchains) | 4892 IWN_RXCHAIN_IDLE_COUNT(sc->nrxchains); 4893 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4894 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4895 rxchain |= IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask); 4896 rxchain |= (IWN_RXCHAIN_DRIVER_FORCE | IWN_RXCHAIN_MIMO_FORCE); 4897 } 4898 sc->rxon.rxchain = htole16(rxchain); 4899 DPRINTF(("setting configuration\n")); 4900 DPRINTF(("%s: rxon chan %d flags %x cck %x ofdm %x rxchain %x\n", 4901 __func__, sc->rxon.chan, le32toh(sc->rxon.flags), sc->rxon.cck_mask, 4902 sc->rxon.ofdm_mask, sc->rxon.rxchain)); 4903 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 4904 if (error != 0) { 4905 printf("%s: RXON command failed\n", sc->sc_dev.dv_xname); 4906 return error; 4907 } 4908 4909 ridx = (sc->sc_ic.ic_curmode == IEEE80211_MODE_11A) ? 4910 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 4911 if ((error = iwn_add_broadcast_node(sc, 0, ridx)) != 0) { 4912 printf("%s: could not add broadcast node\n", 4913 sc->sc_dev.dv_xname); 4914 return error; 4915 } 4916 4917 /* Configuration has changed, set TX power accordingly. */ 4918 if ((error = ops->set_txpower(sc, 0)) != 0) { 4919 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 4920 return error; 4921 } 4922 4923 if ((error = iwn_set_critical_temp(sc)) != 0) { 4924 printf("%s: could not set critical temperature\n", 4925 sc->sc_dev.dv_xname); 4926 return error; 4927 } 4928 4929 /* Set power saving level to CAM during initialization. */ 4930 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4931 printf("%s: could not set power saving level\n", 4932 sc->sc_dev.dv_xname); 4933 return error; 4934 } 4935 return 0; 4936 } 4937 4938 uint16_t 4939 iwn_get_active_dwell_time(struct iwn_softc *sc, 4940 uint16_t flags, uint8_t n_probes) 4941 { 4942 /* No channel? Default to 2GHz settings */ 4943 if (flags & IEEE80211_CHAN_2GHZ) { 4944 return (IWN_ACTIVE_DWELL_TIME_2GHZ + 4945 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1)); 4946 } 4947 4948 /* 5GHz dwell time */ 4949 return (IWN_ACTIVE_DWELL_TIME_5GHZ + 4950 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1)); 4951 } 4952 4953 /* 4954 * Limit the total dwell time to 85% of the beacon interval. 4955 * 4956 * Returns the dwell time in milliseconds. 4957 */ 4958 uint16_t 4959 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 4960 { 4961 struct ieee80211com *ic = &sc->sc_ic; 4962 struct ieee80211_node *ni = ic->ic_bss; 4963 int bintval = 0; 4964 4965 /* bintval is in TU (1.024mS) */ 4966 if (ni != NULL) 4967 bintval = ni->ni_intval; 4968 4969 /* 4970 * If it's non-zero, we should calculate the minimum of 4971 * it and the DWELL_BASE. 4972 * 4973 * XXX Yes, the math should take into account that bintval 4974 * is 1.024mS, not 1mS.. 4975 */ 4976 if (ic->ic_state == IEEE80211_S_RUN && bintval > 0) 4977 return (MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100))); 4978 4979 /* No association context? Default */ 4980 return dwell_time; 4981 } 4982 4983 uint16_t 4984 iwn_get_passive_dwell_time(struct iwn_softc *sc, uint16_t flags) 4985 { 4986 uint16_t passive; 4987 if (flags & IEEE80211_CHAN_2GHZ) { 4988 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 4989 } else { 4990 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 4991 } 4992 4993 /* Clamp to the beacon interval if we're associated */ 4994 return (iwn_limit_dwell(sc, passive)); 4995 } 4996 4997 int 4998 iwn_scan(struct iwn_softc *sc, uint16_t flags, int bgscan) 4999 { 5000 struct ieee80211com *ic = &sc->sc_ic; 5001 struct iwn_scan_hdr *hdr; 5002 struct iwn_cmd_data *tx; 5003 struct iwn_scan_essid *essid; 5004 struct iwn_scan_chan *chan; 5005 struct ieee80211_frame *wh; 5006 struct ieee80211_rateset *rs; 5007 struct ieee80211_channel *c; 5008 struct ifnet *ifp = &ic->ic_if; 5009 uint8_t *buf, *frm; 5010 uint16_t rxchain, dwell_active, dwell_passive; 5011 uint8_t txant; 5012 int buflen, error, is_active; 5013 5014 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 5015 if (buf == NULL) { 5016 printf("%s: could not allocate buffer for scan command\n", 5017 sc->sc_dev.dv_xname); 5018 return ENOMEM; 5019 } 5020 hdr = (struct iwn_scan_hdr *)buf; 5021 /* 5022 * Move to the next channel if no frames are received within 10ms 5023 * after sending the probe request. 5024 */ 5025 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 5026 hdr->quiet_threshold = htole16(1); /* min # of packets */ 5027 5028 if (bgscan) { 5029 int bintval; 5030 5031 /* Set maximum off-channel time. */ 5032 hdr->max_out = htole32(200 * 1024); 5033 5034 /* Configure scan pauses which service on-channel traffic. */ 5035 bintval = ic->ic_bss->ni_intval ? ic->ic_bss->ni_intval : 100; 5036 hdr->pause_scan = htole32(((100 / bintval) << 22) | 5037 ((100 % bintval) * 1024)); 5038 } 5039 5040 /* Select antennas for scanning. */ 5041 rxchain = 5042 IWN_RXCHAIN_VALID(sc->rxchainmask) | 5043 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 5044 IWN_RXCHAIN_DRIVER_FORCE; 5045 if ((flags & IEEE80211_CHAN_5GHZ) && 5046 sc->hw_type == IWN_HW_REV_TYPE_4965) { 5047 /* 5048 * On 4965 ant A and C must be avoided in 5GHz because of a 5049 * HW bug which causes very weak RSSI values being reported. 5050 */ 5051 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 5052 } else /* Use all available RX antennas. */ 5053 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 5054 hdr->rxchain = htole16(rxchain); 5055 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 5056 5057 tx = (struct iwn_cmd_data *)(hdr + 1); 5058 tx->flags = htole32(IWN_TX_AUTO_SEQ); 5059 tx->id = sc->broadcast_id; 5060 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 5061 5062 if (flags & IEEE80211_CHAN_5GHZ) { 5063 /* Send probe requests at 6Mbps. */ 5064 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 5065 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 5066 } else { 5067 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 5068 if (bgscan && sc->hw_type == IWN_HW_REV_TYPE_4965 && 5069 sc->rxon.chan > 14) { 5070 /* 5071 * 4965 firmware can crash when sending probe requests 5072 * with CCK rates while associated to a 5GHz AP. 5073 * Send probe requests at 6Mbps OFDM as a workaround. 5074 */ 5075 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 5076 } else { 5077 /* Send probe requests at 1Mbps. */ 5078 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 5079 tx->rflags = IWN_RFLAG_CCK; 5080 } 5081 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 5082 } 5083 /* Use the first valid TX antenna. */ 5084 txant = IWN_LSB(sc->txchainmask); 5085 tx->rflags |= IWN_RFLAG_ANT(txant); 5086 5087 /* 5088 * Only do active scanning if we're announcing a probe request 5089 * for a given SSID (or more, if we ever add it to the driver.) 5090 */ 5091 is_active = 0; 5092 5093 /* 5094 * If we're scanning for a specific SSID, add it to the command. 5095 */ 5096 essid = (struct iwn_scan_essid *)(tx + 1); 5097 if (ic->ic_des_esslen != 0) { 5098 essid[0].id = IEEE80211_ELEMID_SSID; 5099 essid[0].len = ic->ic_des_esslen; 5100 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 5101 5102 is_active = 1; 5103 } 5104 /* 5105 * Build a probe request frame. Most of the following code is a 5106 * copy & paste of what is done in net80211. 5107 */ 5108 wh = (struct ieee80211_frame *)(essid + 20); 5109 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 5110 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 5111 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 5112 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 5113 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 5114 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 5115 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 5116 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 5117 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 5118 5119 frm = (uint8_t *)(wh + 1); 5120 frm = ieee80211_add_ssid(frm, NULL, 0); 5121 frm = ieee80211_add_rates(frm, rs); 5122 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 5123 frm = ieee80211_add_xrates(frm, rs); 5124 if (ic->ic_flags & IEEE80211_F_HTON) 5125 frm = ieee80211_add_htcaps(frm, ic); 5126 5127 /* Set length of probe request. */ 5128 tx->len = htole16(frm - (uint8_t *)wh); 5129 5130 /* 5131 * If active scanning is requested but a certain channel is 5132 * marked passive, we can do active scanning if we detect 5133 * transmissions. 5134 * 5135 * There is an issue with some firmware versions that triggers 5136 * a sysassert on a "good CRC threshold" of zero (== disabled), 5137 * on a radar channel even though this means that we should NOT 5138 * send probes. 5139 * 5140 * The "good CRC threshold" is the number of frames that we 5141 * need to receive during our dwell time on a channel before 5142 * sending out probes -- setting this to a huge value will 5143 * mean we never reach it, but at the same time work around 5144 * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER 5145 * here instead of IWN_GOOD_CRC_TH_DISABLED. 5146 * 5147 * This was fixed in later versions along with some other 5148 * scan changes, and the threshold behaves as a flag in those 5149 * versions. 5150 */ 5151 5152 /* 5153 * If we're doing active scanning, set the crc_threshold 5154 * to a suitable value. This is different to active veruss 5155 * passive scanning depending upon the channel flags; the 5156 * firmware will obey that particular check for us. 5157 */ 5158 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 5159 hdr->crc_threshold = is_active ? 5160 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 5161 else 5162 hdr->crc_threshold = is_active ? 5163 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 5164 5165 chan = (struct iwn_scan_chan *)frm; 5166 for (c = &ic->ic_channels[1]; 5167 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 5168 if ((c->ic_flags & flags) != flags) 5169 continue; 5170 5171 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 5172 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 5173 chan->flags = 0; 5174 if (ic->ic_des_esslen != 0) 5175 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 5176 5177 if (c->ic_flags & IEEE80211_CHAN_PASSIVE) 5178 chan->flags |= htole32(IWN_CHAN_PASSIVE); 5179 else 5180 chan->flags |= htole32(IWN_CHAN_ACTIVE); 5181 5182 /* 5183 * Calculate the active/passive dwell times. 5184 */ 5185 5186 dwell_active = iwn_get_active_dwell_time(sc, flags, is_active); 5187 dwell_passive = iwn_get_passive_dwell_time(sc, flags); 5188 5189 /* Make sure they're valid */ 5190 if (dwell_passive <= dwell_active) 5191 dwell_passive = dwell_active + 1; 5192 5193 chan->active = htole16(dwell_active); 5194 chan->passive = htole16(dwell_passive); 5195 5196 chan->dsp_gain = 0x6e; 5197 if (IEEE80211_IS_CHAN_5GHZ(c)) { 5198 chan->rf_gain = 0x3b; 5199 } else { 5200 chan->rf_gain = 0x28; 5201 } 5202 hdr->nchan++; 5203 chan++; 5204 } 5205 5206 buflen = (uint8_t *)chan - buf; 5207 hdr->len = htole16(buflen); 5208 5209 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan)); 5210 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 5211 if (error == 0) { 5212 /* 5213 * The current mode might have been fixed during association. 5214 * Ensure all channels get scanned. 5215 */ 5216 if (IFM_MODE(ic->ic_media.ifm_cur->ifm_media) == IFM_AUTO) 5217 ieee80211_setmode(ic, IEEE80211_MODE_AUTO); 5218 5219 sc->sc_flags |= IWN_FLAG_SCANNING; 5220 if (bgscan) 5221 sc->sc_flags |= IWN_FLAG_BGSCAN; 5222 } 5223 free(buf, M_DEVBUF, IWN_SCAN_MAXSZ); 5224 return error; 5225 } 5226 5227 void 5228 iwn_scan_abort(struct iwn_softc *sc) 5229 { 5230 iwn_cmd(sc, IWN_CMD_SCAN_ABORT, NULL, 0, 1); 5231 5232 /* XXX Cannot wait for status response in interrupt context. */ 5233 DELAY(100); 5234 5235 sc->sc_flags &= ~IWN_FLAG_SCANNING; 5236 sc->sc_flags &= ~IWN_FLAG_BGSCAN; 5237 } 5238 5239 int 5240 iwn_bgscan(struct ieee80211com *ic) 5241 { 5242 struct iwn_softc *sc = ic->ic_softc; 5243 int error; 5244 5245 if (sc->sc_flags & IWN_FLAG_SCANNING) 5246 return 0; 5247 5248 error = iwn_scan(sc, IEEE80211_CHAN_2GHZ, 1); 5249 if (error) 5250 printf("%s: could not initiate background scan\n", 5251 sc->sc_dev.dv_xname); 5252 return error; 5253 } 5254 5255 int 5256 iwn_auth(struct iwn_softc *sc, int arg) 5257 { 5258 struct iwn_ops *ops = &sc->ops; 5259 struct ieee80211com *ic = &sc->sc_ic; 5260 struct ieee80211_node *ni = ic->ic_bss; 5261 int error, ridx; 5262 int bss_switch = 5263 (!IEEE80211_ADDR_EQ(sc->bss_node_addr, etheranyaddr) && 5264 !IEEE80211_ADDR_EQ(sc->bss_node_addr, ni->ni_macaddr)); 5265 5266 /* Update adapter configuration. */ 5267 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 5268 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5269 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5270 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) { 5271 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5272 if (ic->ic_flags & IEEE80211_F_USEPROT) 5273 sc->rxon.flags |= htole32(IWN_RXON_TGG_PROT); 5274 DPRINTF(("%s: 2ghz prot 0x%x\n", __func__, 5275 le32toh(sc->rxon.flags))); 5276 } 5277 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5278 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5279 else 5280 sc->rxon.flags &= ~htole32(IWN_RXON_SHSLOT); 5281 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5282 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5283 else 5284 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE); 5285 switch (ic->ic_curmode) { 5286 case IEEE80211_MODE_11A: 5287 sc->rxon.cck_mask = 0; 5288 sc->rxon.ofdm_mask = 0x15; 5289 break; 5290 case IEEE80211_MODE_11B: 5291 sc->rxon.cck_mask = 0x03; 5292 sc->rxon.ofdm_mask = 0; 5293 break; 5294 default: /* Assume 802.11b/g/n. */ 5295 sc->rxon.cck_mask = 0x0f; 5296 sc->rxon.ofdm_mask = 0x15; 5297 } 5298 DPRINTF(("%s: rxon chan %d flags %x cck %x ofdm %x\n", __func__, 5299 sc->rxon.chan, le32toh(sc->rxon.flags), sc->rxon.cck_mask, 5300 sc->rxon.ofdm_mask)); 5301 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5302 if (error != 0) { 5303 printf("%s: RXON command failed\n", sc->sc_dev.dv_xname); 5304 return error; 5305 } 5306 5307 /* Configuration has changed, set TX power accordingly. */ 5308 if ((error = ops->set_txpower(sc, 1)) != 0) { 5309 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 5310 return error; 5311 } 5312 /* 5313 * Reconfiguring RXON clears the firmware nodes table so we must 5314 * add the broadcast node again. 5315 */ 5316 ridx = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 5317 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 5318 if ((error = iwn_add_broadcast_node(sc, 1, ridx)) != 0) { 5319 printf("%s: could not add broadcast node\n", 5320 sc->sc_dev.dv_xname); 5321 return error; 5322 } 5323 5324 /* 5325 * Make sure the firmware gets to see a beacon before we send 5326 * the auth request. Otherwise the Tx attempt can fail due to 5327 * the firmware's built-in regulatory domain enforcement. 5328 * Delaying here for every incoming deauth frame can result in a DoS. 5329 * Don't delay if we're here because of an incoming frame (arg != -1) 5330 * or if we're already waiting for a response (ic_mgt_timer != 0). 5331 * If we are switching APs after a background scan then net80211 has 5332 * just faked the reception of a deauth frame from our old AP, so it 5333 * is safe to delay in that case. 5334 */ 5335 if ((arg == -1 || bss_switch) && ic->ic_mgt_timer == 0) 5336 DELAY(ni->ni_intval * 3 * IEEE80211_DUR_TU); 5337 5338 /* We can now clear the cached address of our previous AP. */ 5339 memset(sc->bss_node_addr, 0, sizeof(sc->bss_node_addr)); 5340 5341 return 0; 5342 } 5343 5344 int 5345 iwn_run(struct iwn_softc *sc) 5346 { 5347 struct iwn_ops *ops = &sc->ops; 5348 struct ieee80211com *ic = &sc->sc_ic; 5349 struct ieee80211_node *ni = ic->ic_bss; 5350 struct iwn_node *wn = (void *)ni; 5351 struct iwn_node_info node; 5352 int error; 5353 5354 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 5355 /* Link LED blinks while monitoring. */ 5356 iwn_set_led(sc, IWN_LED_LINK, 50, 50); 5357 return 0; 5358 } 5359 if ((error = iwn_set_timing(sc, ni)) != 0) { 5360 printf("%s: could not set timing\n", sc->sc_dev.dv_xname); 5361 return error; 5362 } 5363 5364 /* Update adapter configuration. */ 5365 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 5366 /* Short preamble and slot time are negotiated when associating. */ 5367 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 5368 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5369 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5370 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5371 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5372 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 5373 5374 /* HT is negotiated when associating. */ 5375 if (ni->ni_flags & IEEE80211_NODE_HT) { 5376 enum ieee80211_htprot htprot = 5377 (ni->ni_htop1 & IEEE80211_HTOP1_PROT_MASK); 5378 DPRINTF(("%s: htprot = %d\n", __func__, htprot)); 5379 sc->rxon.flags |= htole32(IWN_RXON_HT_PROTMODE(htprot)); 5380 } else 5381 sc->rxon.flags &= ~htole32(IWN_RXON_HT_PROTMODE(3)); 5382 5383 if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)) { 5384 /* 11a or 11n 5GHz */ 5385 sc->rxon.cck_mask = 0; 5386 sc->rxon.ofdm_mask = 0x15; 5387 } else if (ni->ni_flags & IEEE80211_NODE_HT) { 5388 /* 11n 2GHz */ 5389 sc->rxon.cck_mask = 0x0f; 5390 sc->rxon.ofdm_mask = 0x15; 5391 } else { 5392 if (ni->ni_rates.rs_nrates == 4) { 5393 /* 11b */ 5394 sc->rxon.cck_mask = 0x03; 5395 sc->rxon.ofdm_mask = 0; 5396 } else { 5397 /* assume 11g */ 5398 sc->rxon.cck_mask = 0x0f; 5399 sc->rxon.ofdm_mask = 0x15; 5400 } 5401 } 5402 DPRINTF(("%s: rxon chan %d flags %x cck %x ofdm %x\n", __func__, 5403 sc->rxon.chan, le32toh(sc->rxon.flags), sc->rxon.cck_mask, 5404 sc->rxon.ofdm_mask)); 5405 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5406 if (error != 0) { 5407 printf("%s: could not update configuration\n", 5408 sc->sc_dev.dv_xname); 5409 return error; 5410 } 5411 5412 /* Configuration has changed, set TX power accordingly. */ 5413 if ((error = ops->set_txpower(sc, 1)) != 0) { 5414 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 5415 return error; 5416 } 5417 5418 /* Fake a join to initialize the TX rate. */ 5419 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 5420 iwn_newassoc(ic, ni, 1); 5421 5422 /* Add BSS node. */ 5423 memset(&node, 0, sizeof node); 5424 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 5425 node.id = IWN_ID_BSS; 5426 if (ni->ni_flags & IEEE80211_NODE_HT) { 5427 node.htmask = (IWN_AMDPU_SIZE_FACTOR_MASK | 5428 IWN_AMDPU_DENSITY_MASK); 5429 node.htflags = htole32( 5430 IWN_AMDPU_SIZE_FACTOR( 5431 (ic->ic_ampdu_params & IEEE80211_AMPDU_PARAM_LE)) | 5432 IWN_AMDPU_DENSITY( 5433 (ic->ic_ampdu_params & IEEE80211_AMPDU_PARAM_SS) >> 2)); 5434 } 5435 DPRINTF(("adding BSS node\n")); 5436 error = ops->add_node(sc, &node, 1); 5437 if (error != 0) { 5438 printf("%s: could not add BSS node\n", sc->sc_dev.dv_xname); 5439 return error; 5440 } 5441 5442 /* Cache address of AP in case it changes after a background scan. */ 5443 IEEE80211_ADDR_COPY(sc->bss_node_addr, ni->ni_macaddr); 5444 5445 DPRINTF(("setting link quality for node %d\n", node.id)); 5446 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 5447 printf("%s: could not setup link quality for node %d\n", 5448 sc->sc_dev.dv_xname, node.id); 5449 return error; 5450 } 5451 5452 if ((error = iwn_init_sensitivity(sc)) != 0) { 5453 printf("%s: could not set sensitivity\n", 5454 sc->sc_dev.dv_xname); 5455 return error; 5456 } 5457 /* Start periodic calibration timer. */ 5458 sc->calib.state = IWN_CALIB_STATE_ASSOC; 5459 sc->calib_cnt = 0; 5460 timeout_add_msec(&sc->calib_to, 500); 5461 5462 ieee80211_mira_node_init(&wn->mn); 5463 5464 /* Link LED always on while associated. */ 5465 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 5466 return 0; 5467 } 5468 5469 /* 5470 * We support CCMP hardware encryption/decryption of unicast frames only. 5471 * HW support for TKIP really sucks. We should let TKIP die anyway. 5472 */ 5473 int 5474 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 5475 struct ieee80211_key *k) 5476 { 5477 struct iwn_softc *sc = ic->ic_softc; 5478 struct iwn_ops *ops = &sc->ops; 5479 struct iwn_node *wn = (void *)ni; 5480 struct iwn_node_info node; 5481 uint16_t kflags; 5482 5483 if ((k->k_flags & IEEE80211_KEY_GROUP) || 5484 k->k_cipher != IEEE80211_CIPHER_CCMP) 5485 return ieee80211_set_key(ic, ni, k); 5486 5487 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 5488 if (k->k_flags & IEEE80211_KEY_GROUP) 5489 kflags |= IWN_KFLAG_GROUP; 5490 5491 memset(&node, 0, sizeof node); 5492 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 5493 sc->broadcast_id : wn->id; 5494 node.control = IWN_NODE_UPDATE; 5495 node.flags = IWN_FLAG_SET_KEY; 5496 node.kflags = htole16(kflags); 5497 node.kid = k->k_id; 5498 memcpy(node.key, k->k_key, k->k_len); 5499 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 5500 return ops->add_node(sc, &node, 1); 5501 } 5502 5503 void 5504 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 5505 struct ieee80211_key *k) 5506 { 5507 struct iwn_softc *sc = ic->ic_softc; 5508 struct iwn_ops *ops = &sc->ops; 5509 struct iwn_node *wn = (void *)ni; 5510 struct iwn_node_info node; 5511 5512 if ((k->k_flags & IEEE80211_KEY_GROUP) || 5513 k->k_cipher != IEEE80211_CIPHER_CCMP) { 5514 /* See comment about other ciphers above. */ 5515 ieee80211_delete_key(ic, ni, k); 5516 return; 5517 } 5518 if (ic->ic_state != IEEE80211_S_RUN) 5519 return; /* Nothing to do. */ 5520 memset(&node, 0, sizeof node); 5521 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 5522 sc->broadcast_id : wn->id; 5523 node.control = IWN_NODE_UPDATE; 5524 node.flags = IWN_FLAG_SET_KEY; 5525 node.kflags = htole16(IWN_KFLAG_INVALID); 5526 node.kid = 0xff; 5527 DPRINTF(("delete keys for node %d\n", node.id)); 5528 (void)ops->add_node(sc, &node, 1); 5529 } 5530 5531 /* 5532 * This function is called by upper layer when HT protection settings in 5533 * beacons have changed. 5534 */ 5535 void 5536 iwn_update_htprot(struct ieee80211com *ic, struct ieee80211_node *ni) 5537 { 5538 struct iwn_softc *sc = ic->ic_softc; 5539 struct iwn_ops *ops = &sc->ops; 5540 enum ieee80211_htprot htprot; 5541 struct iwn_rxon_assoc rxon_assoc; 5542 int s, error; 5543 5544 /* Update HT protection mode setting. */ 5545 htprot = (ni->ni_htop1 & IEEE80211_HTOP1_PROT_MASK) >> 5546 IEEE80211_HTOP1_PROT_SHIFT; 5547 sc->rxon.flags &= ~htole32(IWN_RXON_HT_PROTMODE(3)); 5548 sc->rxon.flags |= htole32(IWN_RXON_HT_PROTMODE(htprot)); 5549 5550 /* Update RXON config. */ 5551 memset(&rxon_assoc, 0, sizeof(rxon_assoc)); 5552 rxon_assoc.flags = sc->rxon.flags; 5553 rxon_assoc.filter = sc->rxon.filter; 5554 rxon_assoc.ofdm_mask = sc->rxon.ofdm_mask; 5555 rxon_assoc.cck_mask = sc->rxon.cck_mask; 5556 rxon_assoc.ht_single_mask = sc->rxon.ht_single_mask; 5557 rxon_assoc.ht_dual_mask = sc->rxon.ht_dual_mask; 5558 rxon_assoc.ht_triple_mask = sc->rxon.ht_triple_mask; 5559 rxon_assoc.rxchain = sc->rxon.rxchain; 5560 rxon_assoc.acquisition = sc->rxon.acquisition; 5561 5562 s = splnet(); 5563 5564 error = iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &rxon_assoc, 5565 sizeof(rxon_assoc), 1); 5566 if (error != 0) 5567 printf("%s: RXON_ASSOC command failed\n", sc->sc_dev.dv_xname); 5568 5569 DELAY(100); 5570 5571 /* All RXONs wipe the firmware's txpower table. Restore it. */ 5572 error = ops->set_txpower(sc, 1); 5573 if (error != 0) 5574 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 5575 5576 DELAY(100); 5577 5578 /* Restore power saving level */ 5579 if (ic->ic_flags & IEEE80211_F_PMGTON) 5580 error = iwn_set_pslevel(sc, 0, 3, 1); 5581 else 5582 error = iwn_set_pslevel(sc, 0, 0, 1); 5583 if (error != 0) 5584 printf("%s: could not set PS level\n", sc->sc_dev.dv_xname); 5585 5586 splx(s); 5587 } 5588 5589 /* 5590 * This function is called by upper layer when an ADDBA request is received 5591 * from another STA and before the ADDBA response is sent. 5592 */ 5593 int 5594 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5595 uint8_t tid) 5596 { 5597 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 5598 struct iwn_softc *sc = ic->ic_softc; 5599 struct iwn_ops *ops = &sc->ops; 5600 struct iwn_node *wn = (void *)ni; 5601 struct iwn_node_info node; 5602 5603 memset(&node, 0, sizeof node); 5604 node.id = wn->id; 5605 node.control = IWN_NODE_UPDATE; 5606 node.flags = IWN_FLAG_SET_ADDBA; 5607 node.addba_tid = tid; 5608 node.addba_ssn = htole16(ba->ba_winstart); 5609 DPRINTF(("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 5610 ba->ba_winstart)); 5611 /* XXX async command, so firmware may still fail to add BA agreement */ 5612 return ops->add_node(sc, &node, 1); 5613 } 5614 5615 /* 5616 * This function is called by upper layer on teardown of an HT-immediate 5617 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 5618 */ 5619 void 5620 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5621 uint8_t tid) 5622 { 5623 struct iwn_softc *sc = ic->ic_softc; 5624 struct iwn_ops *ops = &sc->ops; 5625 struct iwn_node *wn = (void *)ni; 5626 struct iwn_node_info node; 5627 5628 memset(&node, 0, sizeof node); 5629 node.id = wn->id; 5630 node.control = IWN_NODE_UPDATE; 5631 node.flags = IWN_FLAG_SET_DELBA; 5632 node.delba_tid = tid; 5633 DPRINTF(("DELBA RA=%d TID=%d\n", wn->id, tid)); 5634 (void)ops->add_node(sc, &node, 1); 5635 } 5636 5637 /* 5638 * This function is called by upper layer when an ADDBA response is received 5639 * from another STA. 5640 */ 5641 int 5642 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5643 uint8_t tid) 5644 { 5645 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5646 struct iwn_softc *sc = ic->ic_softc; 5647 struct iwn_ops *ops = &sc->ops; 5648 struct iwn_node *wn = (void *)ni; 5649 struct iwn_node_info node; 5650 int qid = sc->first_agg_txq + tid; 5651 int error; 5652 5653 /* Ensure we can map this TID to an aggregation queue. */ 5654 if (tid >= IWN_NUM_AMPDU_TID || ba->ba_winsize > IWN_SCHED_WINSZ || 5655 qid > sc->ntxqs || (sc->agg_queue_mask & (1 << qid))) 5656 return ENOSPC; 5657 5658 /* Enable TX for the specified RA/TID. */ 5659 wn->disable_tid &= ~(1 << tid); 5660 memset(&node, 0, sizeof node); 5661 node.id = wn->id; 5662 node.control = IWN_NODE_UPDATE; 5663 node.flags = IWN_FLAG_SET_DISABLE_TID; 5664 node.disable_tid = htole16(wn->disable_tid); 5665 error = ops->add_node(sc, &node, 1); 5666 if (error != 0) 5667 return error; 5668 5669 if ((error = iwn_nic_lock(sc)) != 0) 5670 return error; 5671 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 5672 iwn_nic_unlock(sc); 5673 5674 sc->agg_queue_mask |= (1 << qid); 5675 sc->sc_tx_ba[tid].wn = wn; 5676 ba->ba_bitmap = 0; 5677 5678 return 0; 5679 } 5680 5681 void 5682 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5683 uint8_t tid) 5684 { 5685 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5686 struct iwn_softc *sc = ic->ic_softc; 5687 struct iwn_ops *ops = &sc->ops; 5688 int qid = sc->first_agg_txq + tid; 5689 struct iwn_node *wn = (void *)ni; 5690 struct iwn_node_info node; 5691 5692 /* Discard all frames in the current window. */ 5693 iwn_ampdu_txq_advance(sc, &sc->txq[qid], qid, 5694 IWN_AGG_SSN_TO_TXQ_IDX(ba->ba_winend)); 5695 5696 if (iwn_nic_lock(sc) != 0) 5697 return; 5698 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart); 5699 iwn_nic_unlock(sc); 5700 5701 sc->agg_queue_mask &= ~(1 << qid); 5702 sc->sc_tx_ba[tid].wn = NULL; 5703 ba->ba_bitmap = 0; 5704 5705 /* Disable TX for the specified RA/TID. */ 5706 wn->disable_tid |= (1 << tid); 5707 memset(&node, 0, sizeof node); 5708 node.id = wn->id; 5709 node.control = IWN_NODE_UPDATE; 5710 node.flags = IWN_FLAG_SET_DISABLE_TID; 5711 node.disable_tid = htole16(wn->disable_tid); 5712 ops->add_node(sc, &node, 1); 5713 } 5714 5715 void 5716 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5717 uint8_t tid, uint16_t ssn) 5718 { 5719 struct iwn_node *wn = (void *)ni; 5720 int qid = IWN4965_FIRST_AGG_TXQUEUE + tid; 5721 uint16_t idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 5722 5723 /* Stop TX scheduler while we're changing its configuration. */ 5724 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5725 IWN4965_TXQ_STATUS_CHGACT); 5726 5727 /* Assign RA/TID translation to the queue. */ 5728 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5729 wn->id << 4 | tid); 5730 5731 /* Enable chain-building mode for the queue. */ 5732 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5733 5734 /* Set starting sequence number from the ADDBA request. */ 5735 sc->txq[qid].cur = sc->txq[qid].read = idx; 5736 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 5737 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5738 5739 /* Set scheduler window size. */ 5740 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5741 IWN_SCHED_WINSZ); 5742 /* Set scheduler frame limit. */ 5743 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5744 IWN_SCHED_LIMIT << 16); 5745 5746 /* Enable interrupts for the queue. */ 5747 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5748 5749 /* Mark the queue as active. */ 5750 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5751 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5752 iwn_tid2fifo[tid] << 1); 5753 } 5754 5755 void 5756 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5757 { 5758 int qid = IWN4965_FIRST_AGG_TXQUEUE + tid; 5759 uint16_t idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 5760 5761 /* Stop TX scheduler while we're changing its configuration. */ 5762 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5763 IWN4965_TXQ_STATUS_CHGACT); 5764 5765 /* Set starting sequence number from the ADDBA request. */ 5766 sc->txq[qid].cur = sc->txq[qid].read = idx; 5767 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 5768 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5769 5770 /* Disable interrupts for the queue. */ 5771 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5772 5773 /* Mark the queue as inactive. */ 5774 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5775 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5776 } 5777 5778 void 5779 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5780 uint8_t tid, uint16_t ssn) 5781 { 5782 int qid = IWN5000_FIRST_AGG_TXQUEUE + tid; 5783 int idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 5784 struct iwn_node *wn = (void *)ni; 5785 5786 /* Stop TX scheduler while we're changing its configuration. */ 5787 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5788 IWN5000_TXQ_STATUS_CHGACT); 5789 5790 /* Assign RA/TID translation to the queue. */ 5791 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5792 wn->id << 4 | tid); 5793 5794 /* Enable chain-building mode for the queue. */ 5795 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5796 5797 /* Enable aggregation for the queue. */ 5798 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5799 5800 /* Set starting sequence number from the ADDBA request. */ 5801 sc->txq[qid].cur = sc->txq[qid].read = idx; 5802 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 5803 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5804 5805 /* Set scheduler window size and frame limit. */ 5806 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5807 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5808 5809 /* Enable interrupts for the queue. */ 5810 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5811 5812 /* Mark the queue as active. */ 5813 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5814 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5815 } 5816 5817 void 5818 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5819 { 5820 int qid = IWN5000_FIRST_AGG_TXQUEUE + tid; 5821 int idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 5822 5823 /* Stop TX scheduler while we're changing its configuration. */ 5824 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5825 IWN5000_TXQ_STATUS_CHGACT); 5826 5827 /* Disable aggregation for the queue. */ 5828 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5829 5830 /* Set starting sequence number from the ADDBA request. */ 5831 sc->txq[qid].cur = sc->txq[qid].read = idx; 5832 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 5833 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5834 5835 /* Disable interrupts for the queue. */ 5836 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5837 5838 /* Mark the queue as inactive. */ 5839 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5840 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5841 } 5842 5843 /* 5844 * Query calibration tables from the initialization firmware. We do this 5845 * only once at first boot. Called from a process context. 5846 */ 5847 int 5848 iwn5000_query_calibration(struct iwn_softc *sc) 5849 { 5850 struct iwn5000_calib_config cmd; 5851 int error; 5852 5853 memset(&cmd, 0, sizeof cmd); 5854 cmd.ucode.once.enable = 0xffffffff; 5855 cmd.ucode.once.start = 0xffffffff; 5856 cmd.ucode.once.send = 0xffffffff; 5857 cmd.ucode.flags = 0xffffffff; 5858 DPRINTF(("sending calibration query\n")); 5859 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 5860 if (error != 0) 5861 return error; 5862 5863 /* Wait at most two seconds for calibration to complete. */ 5864 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 5865 error = tsleep_nsec(sc, PCATCH, "iwncal", SEC_TO_NSEC(2)); 5866 return error; 5867 } 5868 5869 /* 5870 * Send calibration results to the runtime firmware. These results were 5871 * obtained on first boot from the initialization firmware. 5872 */ 5873 int 5874 iwn5000_send_calibration(struct iwn_softc *sc) 5875 { 5876 int idx, error; 5877 5878 for (idx = 0; idx < 5; idx++) { 5879 if (sc->calibcmd[idx].buf == NULL) 5880 continue; /* No results available. */ 5881 DPRINTF(("send calibration result idx=%d len=%d\n", 5882 idx, sc->calibcmd[idx].len)); 5883 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5884 sc->calibcmd[idx].len, 0); 5885 if (error != 0) { 5886 printf("%s: could not send calibration result\n", 5887 sc->sc_dev.dv_xname); 5888 return error; 5889 } 5890 } 5891 return 0; 5892 } 5893 5894 int 5895 iwn5000_send_wimax_coex(struct iwn_softc *sc) 5896 { 5897 struct iwn5000_wimax_coex wimax; 5898 5899 #ifdef notyet 5900 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5901 /* Enable WiMAX coexistence for combo adapters. */ 5902 wimax.flags = 5903 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 5904 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 5905 IWN_WIMAX_COEX_STA_TABLE_VALID | 5906 IWN_WIMAX_COEX_ENABLE; 5907 memcpy(wimax.events, iwn6050_wimax_events, 5908 sizeof iwn6050_wimax_events); 5909 } else 5910 #endif 5911 { 5912 /* Disable WiMAX coexistence. */ 5913 wimax.flags = 0; 5914 memset(wimax.events, 0, sizeof wimax.events); 5915 } 5916 DPRINTF(("Configuring WiMAX coexistence\n")); 5917 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5918 } 5919 5920 int 5921 iwn5000_crystal_calib(struct iwn_softc *sc) 5922 { 5923 struct iwn5000_phy_calib_crystal cmd; 5924 5925 memset(&cmd, 0, sizeof cmd); 5926 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5927 cmd.ngroups = 1; 5928 cmd.isvalid = 1; 5929 cmd.cap_pin[0] = letoh32(sc->eeprom_crystal) & 0xff; 5930 cmd.cap_pin[1] = (letoh32(sc->eeprom_crystal) >> 16) & 0xff; 5931 DPRINTF(("sending crystal calibration %d, %d\n", 5932 cmd.cap_pin[0], cmd.cap_pin[1])); 5933 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5934 } 5935 5936 int 5937 iwn6000_temp_offset_calib(struct iwn_softc *sc) 5938 { 5939 struct iwn6000_phy_calib_temp_offset cmd; 5940 5941 memset(&cmd, 0, sizeof cmd); 5942 cmd.code = IWN6000_PHY_CALIB_TEMP_OFFSET; 5943 cmd.ngroups = 1; 5944 cmd.isvalid = 1; 5945 if (sc->eeprom_temp != 0) 5946 cmd.offset = htole16(sc->eeprom_temp); 5947 else 5948 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 5949 DPRINTF(("setting radio sensor offset to %d\n", letoh16(cmd.offset))); 5950 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5951 } 5952 5953 int 5954 iwn2000_temp_offset_calib(struct iwn_softc *sc) 5955 { 5956 struct iwn2000_phy_calib_temp_offset cmd; 5957 5958 memset(&cmd, 0, sizeof cmd); 5959 cmd.code = IWN2000_PHY_CALIB_TEMP_OFFSET; 5960 cmd.ngroups = 1; 5961 cmd.isvalid = 1; 5962 if (sc->eeprom_rawtemp != 0) { 5963 cmd.offset_low = htole16(sc->eeprom_rawtemp); 5964 cmd.offset_high = htole16(sc->eeprom_temp); 5965 } else { 5966 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 5967 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 5968 } 5969 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 5970 DPRINTF(("setting radio sensor offset to %d:%d, voltage to %d\n", 5971 letoh16(cmd.offset_low), letoh16(cmd.offset_high), 5972 letoh16(cmd.burnt_voltage_ref))); 5973 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5974 } 5975 5976 /* 5977 * This function is called after the runtime firmware notifies us of its 5978 * readiness (called in a process context). 5979 */ 5980 int 5981 iwn4965_post_alive(struct iwn_softc *sc) 5982 { 5983 int error, qid; 5984 5985 if ((error = iwn_nic_lock(sc)) != 0) 5986 return error; 5987 5988 /* Clear TX scheduler state in SRAM. */ 5989 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5990 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5991 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5992 5993 /* Set physical address of TX scheduler rings (1KB aligned). */ 5994 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5995 5996 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5997 5998 /* Disable chain mode for all our 16 queues. */ 5999 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 6000 6001 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 6002 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 6003 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 6004 6005 /* Set scheduler window size. */ 6006 iwn_mem_write(sc, sc->sched_base + 6007 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 6008 /* Set scheduler frame limit. */ 6009 iwn_mem_write(sc, sc->sched_base + 6010 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 6011 IWN_SCHED_LIMIT << 16); 6012 } 6013 6014 /* Enable interrupts for all our 16 queues. */ 6015 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 6016 /* Identify TX FIFO rings (0-7). */ 6017 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 6018 6019 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 6020 for (qid = 0; qid < 7; qid++) { 6021 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 6022 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 6023 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 6024 } 6025 iwn_nic_unlock(sc); 6026 return 0; 6027 } 6028 6029 /* 6030 * This function is called after the initialization or runtime firmware 6031 * notifies us of its readiness (called in a process context). 6032 */ 6033 int 6034 iwn5000_post_alive(struct iwn_softc *sc) 6035 { 6036 int error, qid; 6037 6038 /* Switch to using ICT interrupt mode. */ 6039 iwn5000_ict_reset(sc); 6040 6041 if ((error = iwn_nic_lock(sc)) != 0) 6042 return error; 6043 6044 /* Clear TX scheduler state in SRAM. */ 6045 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 6046 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 6047 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 6048 6049 /* Set physical address of TX scheduler rings (1KB aligned). */ 6050 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 6051 6052 /* Disable scheduler chain extension (enabled by default in HW). */ 6053 iwn_prph_write(sc, IWN5000_SCHED_CHAINEXT_EN, 0); 6054 6055 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 6056 6057 /* Enable chain mode for all queues, except command queue. */ 6058 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 6059 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 6060 6061 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 6062 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 6063 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 6064 6065 iwn_mem_write(sc, sc->sched_base + 6066 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 6067 /* Set scheduler window size and frame limit. */ 6068 iwn_mem_write(sc, sc->sched_base + 6069 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 6070 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 6071 } 6072 6073 /* Enable interrupts for all our 20 queues. */ 6074 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 6075 /* Identify TX FIFO rings (0-7). */ 6076 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 6077 6078 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 6079 for (qid = 0; qid < 7; qid++) { 6080 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 6081 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 6082 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 6083 } 6084 iwn_nic_unlock(sc); 6085 6086 /* Configure WiMAX coexistence for combo adapters. */ 6087 error = iwn5000_send_wimax_coex(sc); 6088 if (error != 0) { 6089 printf("%s: could not configure WiMAX coexistence\n", 6090 sc->sc_dev.dv_xname); 6091 return error; 6092 } 6093 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 6094 /* Perform crystal calibration. */ 6095 error = iwn5000_crystal_calib(sc); 6096 if (error != 0) { 6097 printf("%s: crystal calibration failed\n", 6098 sc->sc_dev.dv_xname); 6099 return error; 6100 } 6101 } 6102 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 6103 /* Query calibration from the initialization firmware. */ 6104 if ((error = iwn5000_query_calibration(sc)) != 0) { 6105 printf("%s: could not query calibration\n", 6106 sc->sc_dev.dv_xname); 6107 return error; 6108 } 6109 /* 6110 * We have the calibration results now, reboot with the 6111 * runtime firmware (call ourselves recursively!) 6112 */ 6113 iwn_hw_stop(sc); 6114 error = iwn_hw_init(sc); 6115 } else { 6116 /* Send calibration results to runtime firmware. */ 6117 error = iwn5000_send_calibration(sc); 6118 } 6119 return error; 6120 } 6121 6122 /* 6123 * The firmware boot code is small and is intended to be copied directly into 6124 * the NIC internal memory (no DMA transfer). 6125 */ 6126 int 6127 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 6128 { 6129 int error, ntries; 6130 6131 size /= sizeof (uint32_t); 6132 6133 if ((error = iwn_nic_lock(sc)) != 0) 6134 return error; 6135 6136 /* Copy microcode image into NIC memory. */ 6137 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 6138 (const uint32_t *)ucode, size); 6139 6140 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 6141 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 6142 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 6143 6144 /* Start boot load now. */ 6145 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 6146 6147 /* Wait for transfer to complete. */ 6148 for (ntries = 0; ntries < 1000; ntries++) { 6149 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 6150 IWN_BSM_WR_CTRL_START)) 6151 break; 6152 DELAY(10); 6153 } 6154 if (ntries == 1000) { 6155 printf("%s: could not load boot firmware\n", 6156 sc->sc_dev.dv_xname); 6157 iwn_nic_unlock(sc); 6158 return ETIMEDOUT; 6159 } 6160 6161 /* Enable boot after power up. */ 6162 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 6163 6164 iwn_nic_unlock(sc); 6165 return 0; 6166 } 6167 6168 int 6169 iwn4965_load_firmware(struct iwn_softc *sc) 6170 { 6171 struct iwn_fw_info *fw = &sc->fw; 6172 struct iwn_dma_info *dma = &sc->fw_dma; 6173 int error; 6174 6175 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 6176 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 6177 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 6178 BUS_DMASYNC_PREWRITE); 6179 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 6180 fw->init.text, fw->init.textsz); 6181 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 6182 fw->init.textsz, BUS_DMASYNC_PREWRITE); 6183 6184 /* Tell adapter where to find initialization sections. */ 6185 if ((error = iwn_nic_lock(sc)) != 0) 6186 return error; 6187 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 6188 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 6189 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 6190 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 6191 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 6192 iwn_nic_unlock(sc); 6193 6194 /* Load firmware boot code. */ 6195 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 6196 if (error != 0) { 6197 printf("%s: could not load boot firmware\n", 6198 sc->sc_dev.dv_xname); 6199 return error; 6200 } 6201 /* Now press "execute". */ 6202 IWN_WRITE(sc, IWN_RESET, 0); 6203 6204 /* Wait at most one second for first alive notification. */ 6205 if ((error = tsleep_nsec(sc, PCATCH, "iwninit", SEC_TO_NSEC(1))) != 0) { 6206 printf("%s: timeout waiting for adapter to initialize\n", 6207 sc->sc_dev.dv_xname); 6208 return error; 6209 } 6210 6211 /* Retrieve current temperature for initial TX power calibration. */ 6212 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 6213 sc->temp = iwn4965_get_temperature(sc); 6214 6215 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 6216 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 6217 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 6218 BUS_DMASYNC_PREWRITE); 6219 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 6220 fw->main.text, fw->main.textsz); 6221 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 6222 fw->main.textsz, BUS_DMASYNC_PREWRITE); 6223 6224 /* Tell adapter where to find runtime sections. */ 6225 if ((error = iwn_nic_lock(sc)) != 0) 6226 return error; 6227 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 6228 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 6229 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 6230 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 6231 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 6232 IWN_FW_UPDATED | fw->main.textsz); 6233 iwn_nic_unlock(sc); 6234 6235 return 0; 6236 } 6237 6238 int 6239 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 6240 const uint8_t *section, int size) 6241 { 6242 struct iwn_dma_info *dma = &sc->fw_dma; 6243 int error; 6244 6245 /* Copy firmware section into pre-allocated DMA-safe memory. */ 6246 memcpy(dma->vaddr, section, size); 6247 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 6248 6249 if ((error = iwn_nic_lock(sc)) != 0) 6250 return error; 6251 6252 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 6253 IWN_FH_TX_CONFIG_DMA_PAUSE); 6254 6255 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 6256 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 6257 IWN_LOADDR(dma->paddr)); 6258 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 6259 IWN_HIADDR(dma->paddr) << 28 | size); 6260 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 6261 IWN_FH_TXBUF_STATUS_TBNUM(1) | 6262 IWN_FH_TXBUF_STATUS_TBIDX(1) | 6263 IWN_FH_TXBUF_STATUS_TFBD_VALID); 6264 6265 /* Kick Flow Handler to start DMA transfer. */ 6266 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 6267 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 6268 6269 iwn_nic_unlock(sc); 6270 6271 /* Wait at most five seconds for FH DMA transfer to complete. */ 6272 return tsleep_nsec(sc, PCATCH, "iwninit", SEC_TO_NSEC(5)); 6273 } 6274 6275 int 6276 iwn5000_load_firmware(struct iwn_softc *sc) 6277 { 6278 struct iwn_fw_part *fw; 6279 int error; 6280 6281 /* Load the initialization firmware on first boot only. */ 6282 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 6283 &sc->fw.main : &sc->fw.init; 6284 6285 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 6286 fw->text, fw->textsz); 6287 if (error != 0) { 6288 printf("%s: could not load firmware %s section\n", 6289 sc->sc_dev.dv_xname, ".text"); 6290 return error; 6291 } 6292 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 6293 fw->data, fw->datasz); 6294 if (error != 0) { 6295 printf("%s: could not load firmware %s section\n", 6296 sc->sc_dev.dv_xname, ".data"); 6297 return error; 6298 } 6299 6300 /* Now press "execute". */ 6301 IWN_WRITE(sc, IWN_RESET, 0); 6302 return 0; 6303 } 6304 6305 /* 6306 * Extract text and data sections from a legacy firmware image. 6307 */ 6308 int 6309 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 6310 { 6311 const uint32_t *ptr; 6312 size_t hdrlen = 24; 6313 uint32_t rev; 6314 6315 ptr = (const uint32_t *)fw->data; 6316 rev = letoh32(*ptr++); 6317 6318 /* Check firmware API version. */ 6319 if (IWN_FW_API(rev) <= 1) { 6320 printf("%s: bad firmware, need API version >=2\n", 6321 sc->sc_dev.dv_xname); 6322 return EINVAL; 6323 } 6324 if (IWN_FW_API(rev) >= 3) { 6325 /* Skip build number (version 2 header). */ 6326 hdrlen += 4; 6327 ptr++; 6328 } 6329 if (fw->size < hdrlen) { 6330 printf("%s: firmware too short: %zu bytes\n", 6331 sc->sc_dev.dv_xname, fw->size); 6332 return EINVAL; 6333 } 6334 fw->main.textsz = letoh32(*ptr++); 6335 fw->main.datasz = letoh32(*ptr++); 6336 fw->init.textsz = letoh32(*ptr++); 6337 fw->init.datasz = letoh32(*ptr++); 6338 fw->boot.textsz = letoh32(*ptr++); 6339 6340 /* Check that all firmware sections fit. */ 6341 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 6342 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 6343 printf("%s: firmware too short: %zu bytes\n", 6344 sc->sc_dev.dv_xname, fw->size); 6345 return EINVAL; 6346 } 6347 6348 /* Get pointers to firmware sections. */ 6349 fw->main.text = (const uint8_t *)ptr; 6350 fw->main.data = fw->main.text + fw->main.textsz; 6351 fw->init.text = fw->main.data + fw->main.datasz; 6352 fw->init.data = fw->init.text + fw->init.textsz; 6353 fw->boot.text = fw->init.data + fw->init.datasz; 6354 return 0; 6355 } 6356 6357 /* 6358 * Extract text and data sections from a TLV firmware image. 6359 */ 6360 int 6361 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 6362 uint16_t alt) 6363 { 6364 const struct iwn_fw_tlv_hdr *hdr; 6365 const struct iwn_fw_tlv *tlv; 6366 const uint8_t *ptr, *end; 6367 uint64_t altmask; 6368 uint32_t len; 6369 6370 if (fw->size < sizeof (*hdr)) { 6371 printf("%s: firmware too short: %zu bytes\n", 6372 sc->sc_dev.dv_xname, fw->size); 6373 return EINVAL; 6374 } 6375 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 6376 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 6377 printf("%s: bad firmware signature 0x%08x\n", 6378 sc->sc_dev.dv_xname, letoh32(hdr->signature)); 6379 return EINVAL; 6380 } 6381 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr, 6382 letoh32(hdr->build))); 6383 6384 /* 6385 * Select the closest supported alternative that is less than 6386 * or equal to the specified one. 6387 */ 6388 altmask = letoh64(hdr->altmask); 6389 while (alt > 0 && !(altmask & (1ULL << alt))) 6390 alt--; /* Downgrade. */ 6391 DPRINTF(("using alternative %d\n", alt)); 6392 6393 ptr = (const uint8_t *)(hdr + 1); 6394 end = (const uint8_t *)(fw->data + fw->size); 6395 6396 /* Parse type-length-value fields. */ 6397 while (ptr + sizeof (*tlv) <= end) { 6398 tlv = (const struct iwn_fw_tlv *)ptr; 6399 len = letoh32(tlv->len); 6400 6401 ptr += sizeof (*tlv); 6402 if (ptr + len > end) { 6403 printf("%s: firmware too short: %zu bytes\n", 6404 sc->sc_dev.dv_xname, fw->size); 6405 return EINVAL; 6406 } 6407 /* Skip other alternatives. */ 6408 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 6409 goto next; 6410 6411 switch (letoh16(tlv->type)) { 6412 case IWN_FW_TLV_MAIN_TEXT: 6413 fw->main.text = ptr; 6414 fw->main.textsz = len; 6415 break; 6416 case IWN_FW_TLV_MAIN_DATA: 6417 fw->main.data = ptr; 6418 fw->main.datasz = len; 6419 break; 6420 case IWN_FW_TLV_INIT_TEXT: 6421 fw->init.text = ptr; 6422 fw->init.textsz = len; 6423 break; 6424 case IWN_FW_TLV_INIT_DATA: 6425 fw->init.data = ptr; 6426 fw->init.datasz = len; 6427 break; 6428 case IWN_FW_TLV_BOOT_TEXT: 6429 fw->boot.text = ptr; 6430 fw->boot.textsz = len; 6431 break; 6432 case IWN_FW_TLV_ENH_SENS: 6433 if (len != 0) { 6434 printf("%s: TLV type %d has invalid size %u\n", 6435 sc->sc_dev.dv_xname, letoh16(tlv->type), 6436 len); 6437 goto next; 6438 } 6439 sc->sc_flags |= IWN_FLAG_ENH_SENS; 6440 break; 6441 case IWN_FW_TLV_PHY_CALIB: 6442 if (len != sizeof(uint32_t)) { 6443 printf("%s: TLV type %d has invalid size %u\n", 6444 sc->sc_dev.dv_xname, letoh16(tlv->type), 6445 len); 6446 goto next; 6447 } 6448 if (letoh32(*ptr) <= IWN5000_PHY_CALIB_MAX) { 6449 sc->reset_noise_gain = letoh32(*ptr); 6450 sc->noise_gain = letoh32(*ptr) + 1; 6451 } 6452 break; 6453 case IWN_FW_TLV_FLAGS: 6454 if (len < sizeof(uint32_t)) 6455 break; 6456 if (len % sizeof(uint32_t)) 6457 break; 6458 sc->tlv_feature_flags = letoh32(*ptr); 6459 DPRINTF(("feature: 0x%08x\n", sc->tlv_feature_flags)); 6460 break; 6461 default: 6462 DPRINTF(("TLV type %d not handled\n", 6463 letoh16(tlv->type))); 6464 break; 6465 } 6466 next: /* TLV fields are 32-bit aligned. */ 6467 ptr += (len + 3) & ~3; 6468 } 6469 return 0; 6470 } 6471 6472 int 6473 iwn_read_firmware(struct iwn_softc *sc) 6474 { 6475 struct iwn_fw_info *fw = &sc->fw; 6476 int error; 6477 6478 /* 6479 * Some PHY calibration commands are firmware-dependent; these 6480 * are the default values that will be overridden if 6481 * necessary. 6482 */ 6483 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 6484 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 6485 6486 memset(fw, 0, sizeof (*fw)); 6487 6488 /* Read firmware image from filesystem. */ 6489 if ((error = loadfirmware(sc->fwname, &fw->data, &fw->size)) != 0) { 6490 printf("%s: could not read firmware %s (error %d)\n", 6491 sc->sc_dev.dv_xname, sc->fwname, error); 6492 return error; 6493 } 6494 if (fw->size < sizeof (uint32_t)) { 6495 printf("%s: firmware too short: %zu bytes\n", 6496 sc->sc_dev.dv_xname, fw->size); 6497 free(fw->data, M_DEVBUF, fw->size); 6498 return EINVAL; 6499 } 6500 6501 /* Retrieve text and data sections. */ 6502 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 6503 error = iwn_read_firmware_leg(sc, fw); 6504 else 6505 error = iwn_read_firmware_tlv(sc, fw, 1); 6506 if (error != 0) { 6507 printf("%s: could not read firmware sections\n", 6508 sc->sc_dev.dv_xname); 6509 free(fw->data, M_DEVBUF, fw->size); 6510 return error; 6511 } 6512 6513 /* Make sure text and data sections fit in hardware memory. */ 6514 if (fw->main.textsz > sc->fw_text_maxsz || 6515 fw->main.datasz > sc->fw_data_maxsz || 6516 fw->init.textsz > sc->fw_text_maxsz || 6517 fw->init.datasz > sc->fw_data_maxsz || 6518 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 6519 (fw->boot.textsz & 3) != 0) { 6520 printf("%s: firmware sections too large\n", 6521 sc->sc_dev.dv_xname); 6522 free(fw->data, M_DEVBUF, fw->size); 6523 return EINVAL; 6524 } 6525 6526 /* We can proceed with loading the firmware. */ 6527 return 0; 6528 } 6529 6530 int 6531 iwn_clock_wait(struct iwn_softc *sc) 6532 { 6533 int ntries; 6534 6535 /* Set "initialization complete" bit. */ 6536 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6537 6538 /* Wait for clock stabilization. */ 6539 for (ntries = 0; ntries < 2500; ntries++) { 6540 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 6541 return 0; 6542 DELAY(10); 6543 } 6544 printf("%s: timeout waiting for clock stabilization\n", 6545 sc->sc_dev.dv_xname); 6546 return ETIMEDOUT; 6547 } 6548 6549 int 6550 iwn_apm_init(struct iwn_softc *sc) 6551 { 6552 pcireg_t reg; 6553 int error; 6554 6555 /* Disable L0s exit timer (NMI bug workaround). */ 6556 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 6557 /* Don't wait for ICH L0s (ICH bug workaround). */ 6558 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 6559 6560 /* Set FH wait threshold to max (HW bug under stress workaround). */ 6561 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 6562 6563 /* Enable HAP INTA to move adapter from L1a to L0s. */ 6564 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 6565 6566 /* Retrieve PCIe Active State Power Management (ASPM). */ 6567 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 6568 sc->sc_cap_off + PCI_PCIE_LCSR); 6569 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 6570 if (reg & PCI_PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 6571 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6572 else 6573 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6574 6575 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6576 sc->hw_type <= IWN_HW_REV_TYPE_1000) 6577 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 6578 6579 /* Wait for clock stabilization before accessing prph. */ 6580 if ((error = iwn_clock_wait(sc)) != 0) 6581 return error; 6582 6583 if ((error = iwn_nic_lock(sc)) != 0) 6584 return error; 6585 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 6586 /* Enable DMA and BSM (Bootstrap State Machine). */ 6587 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6588 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 6589 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 6590 } else { 6591 /* Enable DMA. */ 6592 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6593 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6594 } 6595 DELAY(20); 6596 /* Disable L1-Active. */ 6597 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 6598 iwn_nic_unlock(sc); 6599 6600 return 0; 6601 } 6602 6603 void 6604 iwn_apm_stop_master(struct iwn_softc *sc) 6605 { 6606 int ntries; 6607 6608 /* Stop busmaster DMA activity. */ 6609 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 6610 for (ntries = 0; ntries < 100; ntries++) { 6611 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 6612 return; 6613 DELAY(10); 6614 } 6615 printf("%s: timeout waiting for master\n", sc->sc_dev.dv_xname); 6616 } 6617 6618 void 6619 iwn_apm_stop(struct iwn_softc *sc) 6620 { 6621 iwn_apm_stop_master(sc); 6622 6623 /* Reset the entire device. */ 6624 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 6625 DELAY(10); 6626 /* Clear "initialization complete" bit. */ 6627 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6628 } 6629 6630 int 6631 iwn4965_nic_config(struct iwn_softc *sc) 6632 { 6633 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 6634 /* 6635 * I don't believe this to be correct but this is what the 6636 * vendor driver is doing. Probably the bits should not be 6637 * shifted in IWN_RFCFG_*. 6638 */ 6639 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6640 IWN_RFCFG_TYPE(sc->rfcfg) | 6641 IWN_RFCFG_STEP(sc->rfcfg) | 6642 IWN_RFCFG_DASH(sc->rfcfg)); 6643 } 6644 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6645 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6646 return 0; 6647 } 6648 6649 int 6650 iwn5000_nic_config(struct iwn_softc *sc) 6651 { 6652 uint32_t tmp; 6653 int error; 6654 6655 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 6656 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6657 IWN_RFCFG_TYPE(sc->rfcfg) | 6658 IWN_RFCFG_STEP(sc->rfcfg) | 6659 IWN_RFCFG_DASH(sc->rfcfg)); 6660 } 6661 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6662 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6663 6664 if ((error = iwn_nic_lock(sc)) != 0) 6665 return error; 6666 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 6667 6668 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 6669 /* 6670 * Select first Switching Voltage Regulator (1.32V) to 6671 * solve a stability issue related to noisy DC2DC line 6672 * in the silicon of 1000 Series. 6673 */ 6674 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 6675 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 6676 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 6677 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 6678 } 6679 iwn_nic_unlock(sc); 6680 6681 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 6682 /* Use internal power amplifier only. */ 6683 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 6684 } 6685 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 6686 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 6687 /* Indicate that ROM calibration version is >=6. */ 6688 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 6689 } 6690 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 6691 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 6692 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 6693 sc->hw_type == IWN_HW_REV_TYPE_2000 || 6694 sc->hw_type == IWN_HW_REV_TYPE_135 || 6695 sc->hw_type == IWN_HW_REV_TYPE_105) 6696 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_IQ_INVERT); 6697 return 0; 6698 } 6699 6700 /* 6701 * Take NIC ownership over Intel Active Management Technology (AMT). 6702 */ 6703 int 6704 iwn_hw_prepare(struct iwn_softc *sc) 6705 { 6706 int ntries; 6707 6708 /* Check if hardware is ready. */ 6709 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6710 for (ntries = 0; ntries < 5; ntries++) { 6711 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6712 IWN_HW_IF_CONFIG_NIC_READY) 6713 return 0; 6714 DELAY(10); 6715 } 6716 6717 /* Hardware not ready, force into ready state. */ 6718 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 6719 for (ntries = 0; ntries < 15000; ntries++) { 6720 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 6721 IWN_HW_IF_CONFIG_PREPARE_DONE)) 6722 break; 6723 DELAY(10); 6724 } 6725 if (ntries == 15000) 6726 return ETIMEDOUT; 6727 6728 /* Hardware should be ready now. */ 6729 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6730 for (ntries = 0; ntries < 5; ntries++) { 6731 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6732 IWN_HW_IF_CONFIG_NIC_READY) 6733 return 0; 6734 DELAY(10); 6735 } 6736 return ETIMEDOUT; 6737 } 6738 6739 int 6740 iwn_hw_init(struct iwn_softc *sc) 6741 { 6742 struct iwn_ops *ops = &sc->ops; 6743 int error, chnl, qid; 6744 6745 /* Clear pending interrupts. */ 6746 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6747 6748 if ((error = iwn_apm_init(sc)) != 0) { 6749 printf("%s: could not power on adapter\n", 6750 sc->sc_dev.dv_xname); 6751 return error; 6752 } 6753 6754 /* Select VMAIN power source. */ 6755 if ((error = iwn_nic_lock(sc)) != 0) 6756 return error; 6757 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 6758 iwn_nic_unlock(sc); 6759 6760 /* Perform adapter-specific initialization. */ 6761 if ((error = ops->nic_config(sc)) != 0) 6762 return error; 6763 6764 /* Initialize RX ring. */ 6765 if ((error = iwn_nic_lock(sc)) != 0) 6766 return error; 6767 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 6768 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 6769 /* Set physical address of RX ring (256-byte aligned). */ 6770 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 6771 /* Set physical address of RX status (16-byte aligned). */ 6772 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 6773 /* Enable RX. */ 6774 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 6775 IWN_FH_RX_CONFIG_ENA | 6776 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 6777 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 6778 IWN_FH_RX_CONFIG_SINGLE_FRAME | 6779 IWN_FH_RX_CONFIG_RB_TIMEOUT(0x11) | /* about 1/2 msec */ 6780 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 6781 iwn_nic_unlock(sc); 6782 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 6783 6784 if ((error = iwn_nic_lock(sc)) != 0) 6785 return error; 6786 6787 /* Initialize TX scheduler. */ 6788 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6789 6790 /* Set physical address of "keep warm" page (16-byte aligned). */ 6791 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6792 6793 /* Initialize TX rings. */ 6794 for (qid = 0; qid < sc->ntxqs; qid++) { 6795 struct iwn_tx_ring *txq = &sc->txq[qid]; 6796 6797 /* Set physical address of TX ring (256-byte aligned). */ 6798 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6799 txq->desc_dma.paddr >> 8); 6800 } 6801 iwn_nic_unlock(sc); 6802 6803 /* Enable DMA channels. */ 6804 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6805 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6806 IWN_FH_TX_CONFIG_DMA_ENA | 6807 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 6808 } 6809 6810 /* Clear "radio off" and "commands blocked" bits. */ 6811 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6812 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 6813 6814 /* Clear pending interrupts. */ 6815 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6816 /* Enable interrupt coalescing. */ 6817 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 6818 /* Enable interrupts. */ 6819 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6820 6821 /* _Really_ make sure "radio off" bit is cleared! */ 6822 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6823 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6824 6825 /* Enable shadow registers. */ 6826 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 6827 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 6828 6829 if ((error = ops->load_firmware(sc)) != 0) { 6830 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 6831 return error; 6832 } 6833 /* Wait at most one second for firmware alive notification. */ 6834 if ((error = tsleep_nsec(sc, PCATCH, "iwninit", SEC_TO_NSEC(1))) != 0) { 6835 printf("%s: timeout waiting for adapter to initialize\n", 6836 sc->sc_dev.dv_xname); 6837 return error; 6838 } 6839 /* Do post-firmware initialization. */ 6840 return ops->post_alive(sc); 6841 } 6842 6843 void 6844 iwn_hw_stop(struct iwn_softc *sc) 6845 { 6846 int chnl, qid, ntries; 6847 6848 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 6849 6850 /* Disable interrupts. */ 6851 IWN_WRITE(sc, IWN_INT_MASK, 0); 6852 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6853 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 6854 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6855 6856 /* Make sure we no longer hold the NIC lock. */ 6857 iwn_nic_unlock(sc); 6858 6859 /* Stop TX scheduler. */ 6860 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6861 6862 /* Stop all DMA channels. */ 6863 if (iwn_nic_lock(sc) == 0) { 6864 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6865 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 6866 for (ntries = 0; ntries < 200; ntries++) { 6867 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 6868 IWN_FH_TX_STATUS_IDLE(chnl)) 6869 break; 6870 DELAY(10); 6871 } 6872 } 6873 iwn_nic_unlock(sc); 6874 } 6875 6876 /* Stop RX ring. */ 6877 iwn_reset_rx_ring(sc, &sc->rxq); 6878 6879 /* Reset all TX rings. */ 6880 for (qid = 0; qid < sc->ntxqs; qid++) 6881 iwn_reset_tx_ring(sc, &sc->txq[qid]); 6882 6883 if (iwn_nic_lock(sc) == 0) { 6884 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 6885 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6886 iwn_nic_unlock(sc); 6887 } 6888 DELAY(5); 6889 /* Power OFF adapter. */ 6890 iwn_apm_stop(sc); 6891 } 6892 6893 int 6894 iwn_init(struct ifnet *ifp) 6895 { 6896 struct iwn_softc *sc = ifp->if_softc; 6897 struct ieee80211com *ic = &sc->sc_ic; 6898 int error; 6899 6900 memset(sc->bss_node_addr, 0, sizeof(sc->bss_node_addr)); 6901 sc->agg_queue_mask = 0; 6902 memset(sc->sc_tx_ba, 0, sizeof(sc->sc_tx_ba)); 6903 6904 if ((error = iwn_hw_prepare(sc)) != 0) { 6905 printf("%s: hardware not ready\n", sc->sc_dev.dv_xname); 6906 goto fail; 6907 } 6908 6909 /* Initialize interrupt mask to default value. */ 6910 sc->int_mask = IWN_INT_MASK_DEF; 6911 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6912 6913 /* Check that the radio is not disabled by hardware switch. */ 6914 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 6915 printf("%s: radio is disabled by hardware switch\n", 6916 sc->sc_dev.dv_xname); 6917 error = EPERM; /* :-) */ 6918 /* Re-enable interrupts. */ 6919 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6920 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6921 return error; 6922 } 6923 6924 /* Read firmware images from the filesystem. */ 6925 if ((error = iwn_read_firmware(sc)) != 0) { 6926 printf("%s: could not read firmware\n", sc->sc_dev.dv_xname); 6927 goto fail; 6928 } 6929 6930 /* Initialize hardware and upload firmware. */ 6931 error = iwn_hw_init(sc); 6932 free(sc->fw.data, M_DEVBUF, sc->fw.size); 6933 if (error != 0) { 6934 printf("%s: could not initialize hardware\n", 6935 sc->sc_dev.dv_xname); 6936 goto fail; 6937 } 6938 6939 /* Configure adapter now that it is ready. */ 6940 if ((error = iwn_config(sc)) != 0) { 6941 printf("%s: could not configure device\n", 6942 sc->sc_dev.dv_xname); 6943 goto fail; 6944 } 6945 6946 ifq_clr_oactive(&ifp->if_snd); 6947 ifp->if_flags |= IFF_RUNNING; 6948 6949 if (ic->ic_opmode != IEEE80211_M_MONITOR) 6950 ieee80211_begin_scan(ifp); 6951 else 6952 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 6953 6954 return 0; 6955 6956 fail: iwn_stop(ifp); 6957 return error; 6958 } 6959 6960 void 6961 iwn_stop(struct ifnet *ifp) 6962 { 6963 struct iwn_softc *sc = ifp->if_softc; 6964 struct ieee80211com *ic = &sc->sc_ic; 6965 6966 timeout_del(&sc->calib_to); 6967 ifp->if_timer = sc->sc_tx_timer = 0; 6968 ifp->if_flags &= ~IFF_RUNNING; 6969 ifq_clr_oactive(&ifp->if_snd); 6970 6971 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 6972 6973 /* Power OFF hardware. */ 6974 iwn_hw_stop(sc); 6975 } 6976