1 /* $OpenBSD: if_iwn.c,v 1.263 2024/05/24 06:02:53 jsg Exp $ */ 2 3 /*- 4 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 21 * adapters. 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/mbuf.h> 29 #include <sys/rwlock.h> 30 #include <sys/socket.h> 31 #include <sys/systm.h> 32 #include <sys/malloc.h> 33 #include <sys/device.h> 34 #include <sys/task.h> 35 #include <sys/endian.h> 36 37 #include <machine/bus.h> 38 #include <machine/intr.h> 39 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcidevs.h> 43 44 #if NBPFILTER > 0 45 #include <net/bpf.h> 46 #endif 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 51 #include <netinet/in.h> 52 #include <netinet/if_ether.h> 53 54 #include <net80211/ieee80211_var.h> 55 #include <net80211/ieee80211_amrr.h> 56 #include <net80211/ieee80211_ra.h> 57 #include <net80211/ieee80211_radiotap.h> 58 #include <net80211/ieee80211_priv.h> /* for SEQ_LT */ 59 #undef DPRINTF /* defined in ieee80211_priv.h */ 60 61 #include <dev/pci/if_iwnreg.h> 62 #include <dev/pci/if_iwnvar.h> 63 64 static const struct pci_matchid iwn_devices[] = { 65 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_4965_1 }, 66 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_4965_2 }, 67 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5100_1 }, 68 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5100_2 }, 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5150_1 }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5150_2 }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5300_1 }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5300_2 }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5350_1 }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5350_2 }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1000_1 }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1000_2 }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6300_1 }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6300_2 }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6200_1 }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6200_2 }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6050_1 }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6050_2 }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6005_1 }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6005_2 }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6030_1 }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6030_2 }, 87 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1030_1 }, 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1030_2 }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_100_1 }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_100_2 }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_130_1 }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_130_2 }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6235_1 }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6235_2 }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2230_1 }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2230_2 }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2200_1 }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2200_2 }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_135_1 }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_135_2 }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_105_1 }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_105_2 }, 103 }; 104 105 int iwn_match(struct device *, void *, void *); 106 void iwn_attach(struct device *, struct device *, void *); 107 int iwn4965_attach(struct iwn_softc *, pci_product_id_t); 108 int iwn5000_attach(struct iwn_softc *, pci_product_id_t); 109 #if NBPFILTER > 0 110 void iwn_radiotap_attach(struct iwn_softc *); 111 #endif 112 int iwn_detach(struct device *, int); 113 int iwn_activate(struct device *, int); 114 void iwn_wakeup(struct iwn_softc *); 115 void iwn_init_task(void *); 116 int iwn_nic_lock(struct iwn_softc *); 117 int iwn_eeprom_lock(struct iwn_softc *); 118 int iwn_init_otprom(struct iwn_softc *); 119 int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 120 int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 121 void **, bus_size_t, bus_size_t); 122 void iwn_dma_contig_free(struct iwn_dma_info *); 123 int iwn_alloc_sched(struct iwn_softc *); 124 void iwn_free_sched(struct iwn_softc *); 125 int iwn_alloc_kw(struct iwn_softc *); 126 void iwn_free_kw(struct iwn_softc *); 127 int iwn_alloc_ict(struct iwn_softc *); 128 void iwn_free_ict(struct iwn_softc *); 129 int iwn_alloc_fwmem(struct iwn_softc *); 130 void iwn_free_fwmem(struct iwn_softc *); 131 int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 132 void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 133 void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 134 int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 135 int); 136 void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 137 void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 138 void iwn5000_ict_reset(struct iwn_softc *); 139 int iwn_read_eeprom(struct iwn_softc *); 140 void iwn4965_read_eeprom(struct iwn_softc *); 141 void iwn4965_print_power_group(struct iwn_softc *, int); 142 void iwn5000_read_eeprom(struct iwn_softc *); 143 void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 144 void iwn_read_eeprom_enhinfo(struct iwn_softc *); 145 struct ieee80211_node *iwn_node_alloc(struct ieee80211com *); 146 void iwn_newassoc(struct ieee80211com *, struct ieee80211_node *, 147 int); 148 int iwn_media_change(struct ifnet *); 149 int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 150 void iwn_iter_func(void *, struct ieee80211_node *); 151 void iwn_calib_timeout(void *); 152 int iwn_ccmp_decap(struct iwn_softc *, struct mbuf *, 153 struct ieee80211_node *); 154 void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 155 struct iwn_rx_data *); 156 void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 157 struct iwn_rx_data *, struct mbuf_list *); 158 void iwn_ra_choose(struct iwn_softc *, struct ieee80211_node *); 159 void iwn_ampdu_rate_control(struct iwn_softc *, struct ieee80211_node *, 160 struct iwn_tx_ring *, uint16_t, uint16_t); 161 void iwn_ht_single_rate_control(struct iwn_softc *, 162 struct ieee80211_node *, uint8_t, uint8_t, uint8_t, int); 163 void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 164 struct iwn_rx_data *); 165 void iwn5000_rx_calib_results(struct iwn_softc *, 166 struct iwn_rx_desc *, struct iwn_rx_data *); 167 void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 168 struct iwn_rx_data *); 169 void iwn_ampdu_txq_advance(struct iwn_softc *, struct iwn_tx_ring *, 170 int, int); 171 void iwn_ampdu_tx_done(struct iwn_softc *, struct iwn_tx_ring *, 172 struct iwn_rx_desc *, uint16_t, uint8_t, uint8_t, uint8_t, 173 int, uint32_t, struct iwn_txagg_status *); 174 void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 175 struct iwn_rx_data *); 176 void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 177 struct iwn_rx_data *); 178 void iwn_tx_done_free_txdata(struct iwn_softc *, 179 struct iwn_tx_data *); 180 void iwn_clear_oactive(struct iwn_softc *, struct iwn_tx_ring *); 181 void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 182 uint8_t, uint8_t, uint8_t, int, int, uint16_t); 183 void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 184 void iwn_notif_intr(struct iwn_softc *); 185 void iwn_wakeup_intr(struct iwn_softc *); 186 void iwn_fatal_intr(struct iwn_softc *); 187 int iwn_intr(void *); 188 void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 189 uint16_t); 190 void iwn4965_reset_sched(struct iwn_softc *, int, int); 191 void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 192 uint16_t); 193 void iwn5000_reset_sched(struct iwn_softc *, int, int); 194 int iwn_tx(struct iwn_softc *, struct mbuf *, 195 struct ieee80211_node *); 196 int iwn_rval2ridx(int); 197 void iwn_start(struct ifnet *); 198 void iwn_watchdog(struct ifnet *); 199 int iwn_ioctl(struct ifnet *, u_long, caddr_t); 200 int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 201 int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 202 int); 203 int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 204 int); 205 int iwn_set_link_quality(struct iwn_softc *, 206 struct ieee80211_node *); 207 int iwn_add_broadcast_node(struct iwn_softc *, int, int); 208 void iwn_updateedca(struct ieee80211com *); 209 void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 210 int iwn_set_critical_temp(struct iwn_softc *); 211 int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 212 void iwn4965_power_calibration(struct iwn_softc *, int); 213 int iwn4965_set_txpower(struct iwn_softc *, int); 214 int iwn5000_set_txpower(struct iwn_softc *, int); 215 int iwn4965_get_rssi(const struct iwn_rx_stat *); 216 int iwn5000_get_rssi(const struct iwn_rx_stat *); 217 int iwn_get_noise(const struct iwn_rx_general_stats *); 218 int iwn4965_get_temperature(struct iwn_softc *); 219 int iwn5000_get_temperature(struct iwn_softc *); 220 int iwn_init_sensitivity(struct iwn_softc *); 221 void iwn_collect_noise(struct iwn_softc *, 222 const struct iwn_rx_general_stats *); 223 int iwn4965_init_gains(struct iwn_softc *); 224 int iwn5000_init_gains(struct iwn_softc *); 225 int iwn4965_set_gains(struct iwn_softc *); 226 int iwn5000_set_gains(struct iwn_softc *); 227 void iwn_tune_sensitivity(struct iwn_softc *, 228 const struct iwn_rx_stats *); 229 int iwn_send_sensitivity(struct iwn_softc *); 230 int iwn_set_pslevel(struct iwn_softc *, int, int, int); 231 int iwn_send_btcoex(struct iwn_softc *); 232 int iwn_send_advanced_btcoex(struct iwn_softc *); 233 int iwn5000_runtime_calib(struct iwn_softc *); 234 int iwn_config(struct iwn_softc *); 235 uint16_t iwn_get_active_dwell_time(struct iwn_softc *, uint16_t, uint8_t); 236 uint16_t iwn_limit_dwell(struct iwn_softc *, uint16_t); 237 uint16_t iwn_get_passive_dwell_time(struct iwn_softc *, uint16_t); 238 int iwn_scan(struct iwn_softc *, uint16_t, int); 239 void iwn_scan_abort(struct iwn_softc *); 240 int iwn_bgscan(struct ieee80211com *); 241 void iwn_rxon_configure_ht40(struct ieee80211com *, 242 struct ieee80211_node *); 243 int iwn_rxon_ht40_enabled(struct iwn_softc *); 244 int iwn_auth(struct iwn_softc *, int); 245 int iwn_run(struct iwn_softc *); 246 int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 247 struct ieee80211_key *); 248 void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 249 struct ieee80211_key *); 250 void iwn_updatechan(struct ieee80211com *); 251 void iwn_updateprot(struct ieee80211com *); 252 void iwn_updateslot(struct ieee80211com *); 253 void iwn_update_rxon_restore_power(struct iwn_softc *); 254 void iwn5000_update_rxon(struct iwn_softc *); 255 void iwn4965_update_rxon(struct iwn_softc *); 256 int iwn_ampdu_rx_start(struct ieee80211com *, 257 struct ieee80211_node *, uint8_t); 258 void iwn_ampdu_rx_stop(struct ieee80211com *, 259 struct ieee80211_node *, uint8_t); 260 int iwn_ampdu_tx_start(struct ieee80211com *, 261 struct ieee80211_node *, uint8_t); 262 void iwn_ampdu_tx_stop(struct ieee80211com *, 263 struct ieee80211_node *, uint8_t); 264 void iwn4965_ampdu_tx_start(struct iwn_softc *, 265 struct ieee80211_node *, uint8_t, uint16_t); 266 void iwn4965_ampdu_tx_stop(struct iwn_softc *, 267 uint8_t, uint16_t); 268 void iwn5000_ampdu_tx_start(struct iwn_softc *, 269 struct ieee80211_node *, uint8_t, uint16_t); 270 void iwn5000_ampdu_tx_stop(struct iwn_softc *, 271 uint8_t, uint16_t); 272 int iwn5000_query_calibration(struct iwn_softc *); 273 int iwn5000_send_calibration(struct iwn_softc *); 274 int iwn5000_send_wimax_coex(struct iwn_softc *); 275 int iwn5000_crystal_calib(struct iwn_softc *); 276 int iwn6000_temp_offset_calib(struct iwn_softc *); 277 int iwn2000_temp_offset_calib(struct iwn_softc *); 278 int iwn4965_post_alive(struct iwn_softc *); 279 int iwn5000_post_alive(struct iwn_softc *); 280 int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 281 int); 282 int iwn4965_load_firmware(struct iwn_softc *); 283 int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 284 const uint8_t *, int); 285 int iwn5000_load_firmware(struct iwn_softc *); 286 int iwn_read_firmware_leg(struct iwn_softc *, 287 struct iwn_fw_info *); 288 int iwn_read_firmware_tlv(struct iwn_softc *, 289 struct iwn_fw_info *, uint16_t); 290 int iwn_read_firmware(struct iwn_softc *); 291 int iwn_clock_wait(struct iwn_softc *); 292 int iwn_apm_init(struct iwn_softc *); 293 void iwn_apm_stop_master(struct iwn_softc *); 294 void iwn_apm_stop(struct iwn_softc *); 295 int iwn4965_nic_config(struct iwn_softc *); 296 int iwn5000_nic_config(struct iwn_softc *); 297 int iwn_hw_prepare(struct iwn_softc *); 298 int iwn_hw_init(struct iwn_softc *); 299 void iwn_hw_stop(struct iwn_softc *); 300 int iwn_init(struct ifnet *); 301 void iwn_stop(struct ifnet *); 302 303 #ifdef IWN_DEBUG 304 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 305 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 306 int iwn_debug = 1; 307 #else 308 #define DPRINTF(x) 309 #define DPRINTFN(n, x) 310 #endif 311 312 struct cfdriver iwn_cd = { 313 NULL, "iwn", DV_IFNET 314 }; 315 316 const struct cfattach iwn_ca = { 317 sizeof (struct iwn_softc), iwn_match, iwn_attach, iwn_detach, 318 iwn_activate 319 }; 320 321 int 322 iwn_match(struct device *parent, void *match, void *aux) 323 { 324 return pci_matchbyid((struct pci_attach_args *)aux, iwn_devices, 325 nitems(iwn_devices)); 326 } 327 328 void 329 iwn_attach(struct device *parent, struct device *self, void *aux) 330 { 331 struct iwn_softc *sc = (struct iwn_softc *)self; 332 struct ieee80211com *ic = &sc->sc_ic; 333 struct ifnet *ifp = &ic->ic_if; 334 struct pci_attach_args *pa = aux; 335 const char *intrstr; 336 pci_intr_handle_t ih; 337 pcireg_t memtype, reg; 338 int i, error; 339 340 sc->sc_pct = pa->pa_pc; 341 sc->sc_pcitag = pa->pa_tag; 342 sc->sc_dmat = pa->pa_dmat; 343 344 /* 345 * Get the offset of the PCI Express Capability Structure in PCI 346 * Configuration Space. 347 */ 348 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 349 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 350 if (error == 0) { 351 printf(": PCIe capability structure not found!\n"); 352 return; 353 } 354 355 /* Clear device-specific "PCI retry timeout" register (41h). */ 356 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 357 if (reg & 0xff00) 358 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 359 360 /* Hardware bug workaround. */ 361 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 362 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 363 DPRINTF(("PCIe INTx Disable set\n")); 364 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 365 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 366 PCI_COMMAND_STATUS_REG, reg); 367 } 368 369 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 370 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 371 &sc->sc_sh, NULL, &sc->sc_sz, 0); 372 if (error != 0) { 373 printf(": can't map mem space\n"); 374 return; 375 } 376 377 /* Install interrupt handler. */ 378 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 379 printf(": can't map interrupt\n"); 380 return; 381 } 382 intrstr = pci_intr_string(sc->sc_pct, ih); 383 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc, 384 sc->sc_dev.dv_xname); 385 if (sc->sc_ih == NULL) { 386 printf(": can't establish interrupt"); 387 if (intrstr != NULL) 388 printf(" at %s", intrstr); 389 printf("\n"); 390 return; 391 } 392 printf(": %s", intrstr); 393 394 /* Read hardware revision and attach. */ 395 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0x1f; 396 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 397 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id)); 398 else 399 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id)); 400 if (error != 0) { 401 printf(": could not attach device\n"); 402 return; 403 } 404 405 if ((error = iwn_hw_prepare(sc)) != 0) { 406 printf(": hardware not ready\n"); 407 return; 408 } 409 410 /* Read MAC address, channels, etc from EEPROM. */ 411 if ((error = iwn_read_eeprom(sc)) != 0) { 412 printf(": could not read EEPROM\n"); 413 return; 414 } 415 416 /* Allocate DMA memory for firmware transfers. */ 417 if ((error = iwn_alloc_fwmem(sc)) != 0) { 418 printf(": could not allocate memory for firmware\n"); 419 return; 420 } 421 422 /* Allocate "Keep Warm" page. */ 423 if ((error = iwn_alloc_kw(sc)) != 0) { 424 printf(": could not allocate keep warm page\n"); 425 goto fail1; 426 } 427 428 /* Allocate ICT table for 5000 Series. */ 429 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 430 (error = iwn_alloc_ict(sc)) != 0) { 431 printf(": could not allocate ICT table\n"); 432 goto fail2; 433 } 434 435 /* Allocate TX scheduler "rings". */ 436 if ((error = iwn_alloc_sched(sc)) != 0) { 437 printf(": could not allocate TX scheduler rings\n"); 438 goto fail3; 439 } 440 441 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 442 for (i = 0; i < sc->ntxqs; i++) { 443 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 444 printf(": could not allocate TX ring %d\n", i); 445 goto fail4; 446 } 447 } 448 449 /* Allocate RX ring. */ 450 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 451 printf(": could not allocate RX ring\n"); 452 goto fail4; 453 } 454 455 /* Clear pending interrupts. */ 456 IWN_WRITE(sc, IWN_INT, 0xffffffff); 457 458 /* Count the number of available chains. */ 459 sc->ntxchains = 460 ((sc->txchainmask >> 2) & 1) + 461 ((sc->txchainmask >> 1) & 1) + 462 ((sc->txchainmask >> 0) & 1); 463 sc->nrxchains = 464 ((sc->rxchainmask >> 2) & 1) + 465 ((sc->rxchainmask >> 1) & 1) + 466 ((sc->rxchainmask >> 0) & 1); 467 printf(", MIMO %dT%dR, %.4s, address %s\n", sc->ntxchains, 468 sc->nrxchains, sc->eeprom_domain, ether_sprintf(ic->ic_myaddr)); 469 470 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 471 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 472 ic->ic_state = IEEE80211_S_INIT; 473 474 /* Set device capabilities. */ 475 ic->ic_caps = 476 IEEE80211_C_WEP | /* WEP */ 477 IEEE80211_C_RSN | /* WPA/RSN */ 478 IEEE80211_C_SCANALL | /* device scans all channels at once */ 479 IEEE80211_C_SCANALLBAND | /* driver scans all bands at once */ 480 IEEE80211_C_MONITOR | /* monitor mode supported */ 481 IEEE80211_C_SHSLOT | /* short slot time supported */ 482 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 483 IEEE80211_C_PMGT; /* power saving supported */ 484 485 /* No optional HT features supported for now, */ 486 ic->ic_htcaps = 0; 487 ic->ic_htxcaps = 0; 488 ic->ic_txbfcaps = 0; 489 ic->ic_aselcaps = 0; 490 ic->ic_ampdu_params = (IEEE80211_AMPDU_PARAM_SS_4 | 0x3 /* 64k */); 491 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 492 ic->ic_caps |= (IEEE80211_C_QOS | IEEE80211_C_TX_AMPDU); 493 /* Set HT capabilities. */ 494 ic->ic_htcaps = IEEE80211_HTCAP_SGI20; 495 /* 6200 devices have issues with SGI40 for some reason. */ 496 if ((sc->sc_flags & IWN_FLAG_INTERNAL_PA) == 0) 497 ic->ic_htcaps |= IEEE80211_HTCAP_SGI40; 498 ic->ic_htcaps |= IEEE80211_HTCAP_CBW20_40; 499 #ifdef notyet 500 ic->ic_htcaps |= 501 #if IWN_RBUF_SIZE == 8192 502 IEEE80211_HTCAP_AMSDU7935 | 503 #endif 504 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 505 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 506 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 507 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 508 else 509 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 510 #endif /* notyet */ 511 } 512 513 /* Set supported legacy rates. */ 514 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 515 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 516 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 517 ic->ic_sup_rates[IEEE80211_MODE_11A] = 518 ieee80211_std_rateset_11a; 519 } 520 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 521 /* Set supported HT rates. */ 522 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */ 523 #ifdef notyet 524 if (sc->nrxchains > 1) 525 ic->ic_sup_mcs[1] = 0xff; /* MCS 8-15 */ 526 if (sc->nrxchains > 2) 527 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 528 #endif 529 } 530 531 /* IBSS channel undefined for now. */ 532 ic->ic_ibss_chan = &ic->ic_channels[0]; 533 534 ifp->if_softc = sc; 535 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 536 ifp->if_ioctl = iwn_ioctl; 537 ifp->if_start = iwn_start; 538 ifp->if_watchdog = iwn_watchdog; 539 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 540 541 if_attach(ifp); 542 ieee80211_ifattach(ifp); 543 ic->ic_node_alloc = iwn_node_alloc; 544 ic->ic_bgscan_start = iwn_bgscan; 545 ic->ic_newassoc = iwn_newassoc; 546 ic->ic_updateedca = iwn_updateedca; 547 ic->ic_set_key = iwn_set_key; 548 ic->ic_delete_key = iwn_delete_key; 549 ic->ic_updatechan = iwn_updatechan; 550 ic->ic_updateprot = iwn_updateprot; 551 ic->ic_updateslot = iwn_updateslot; 552 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 553 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 554 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 555 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 556 557 /* Override 802.11 state transition machine. */ 558 sc->sc_newstate = ic->ic_newstate; 559 ic->ic_newstate = iwn_newstate; 560 ieee80211_media_init(ifp, iwn_media_change, ieee80211_media_status); 561 562 sc->amrr.amrr_min_success_threshold = 1; 563 sc->amrr.amrr_max_success_threshold = 15; 564 565 #if NBPFILTER > 0 566 iwn_radiotap_attach(sc); 567 #endif 568 timeout_set(&sc->calib_to, iwn_calib_timeout, sc); 569 rw_init(&sc->sc_rwlock, "iwnlock"); 570 task_set(&sc->init_task, iwn_init_task, sc); 571 return; 572 573 /* Free allocated memory if something failed during attachment. */ 574 fail4: while (--i >= 0) 575 iwn_free_tx_ring(sc, &sc->txq[i]); 576 iwn_free_sched(sc); 577 fail3: if (sc->ict != NULL) 578 iwn_free_ict(sc); 579 fail2: iwn_free_kw(sc); 580 fail1: iwn_free_fwmem(sc); 581 } 582 583 int 584 iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid) 585 { 586 struct iwn_ops *ops = &sc->ops; 587 588 ops->load_firmware = iwn4965_load_firmware; 589 ops->read_eeprom = iwn4965_read_eeprom; 590 ops->post_alive = iwn4965_post_alive; 591 ops->nic_config = iwn4965_nic_config; 592 ops->reset_sched = iwn4965_reset_sched; 593 ops->update_sched = iwn4965_update_sched; 594 ops->update_rxon = iwn4965_update_rxon; 595 ops->get_temperature = iwn4965_get_temperature; 596 ops->get_rssi = iwn4965_get_rssi; 597 ops->set_txpower = iwn4965_set_txpower; 598 ops->init_gains = iwn4965_init_gains; 599 ops->set_gains = iwn4965_set_gains; 600 ops->add_node = iwn4965_add_node; 601 ops->tx_done = iwn4965_tx_done; 602 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 603 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 604 sc->ntxqs = IWN4965_NTXQUEUES; 605 sc->first_agg_txq = IWN4965_FIRST_AGG_TXQUEUE; 606 sc->ndmachnls = IWN4965_NDMACHNLS; 607 sc->broadcast_id = IWN4965_ID_BROADCAST; 608 sc->rxonsz = IWN4965_RXONSZ; 609 sc->schedsz = IWN4965_SCHEDSZ; 610 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 611 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 612 sc->fwsz = IWN4965_FWSZ; 613 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 614 sc->limits = &iwn4965_sensitivity_limits; 615 sc->fwname = "iwn-4965"; 616 /* Override chains masks, ROM is known to be broken. */ 617 sc->txchainmask = IWN_ANT_AB; 618 sc->rxchainmask = IWN_ANT_ABC; 619 620 return 0; 621 } 622 623 int 624 iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid) 625 { 626 struct iwn_ops *ops = &sc->ops; 627 628 ops->load_firmware = iwn5000_load_firmware; 629 ops->read_eeprom = iwn5000_read_eeprom; 630 ops->post_alive = iwn5000_post_alive; 631 ops->nic_config = iwn5000_nic_config; 632 ops->reset_sched = iwn5000_reset_sched; 633 ops->update_sched = iwn5000_update_sched; 634 ops->update_rxon = iwn5000_update_rxon; 635 ops->get_temperature = iwn5000_get_temperature; 636 ops->get_rssi = iwn5000_get_rssi; 637 ops->set_txpower = iwn5000_set_txpower; 638 ops->init_gains = iwn5000_init_gains; 639 ops->set_gains = iwn5000_set_gains; 640 ops->add_node = iwn5000_add_node; 641 ops->tx_done = iwn5000_tx_done; 642 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 643 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 644 sc->ntxqs = IWN5000_NTXQUEUES; 645 sc->first_agg_txq = IWN5000_FIRST_AGG_TXQUEUE; 646 sc->ndmachnls = IWN5000_NDMACHNLS; 647 sc->broadcast_id = IWN5000_ID_BROADCAST; 648 sc->rxonsz = IWN5000_RXONSZ; 649 sc->schedsz = IWN5000_SCHEDSZ; 650 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 651 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 652 sc->fwsz = IWN5000_FWSZ; 653 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 654 655 switch (sc->hw_type) { 656 case IWN_HW_REV_TYPE_5100: 657 sc->limits = &iwn5000_sensitivity_limits; 658 sc->fwname = "iwn-5000"; 659 /* Override chains masks, ROM is known to be broken. */ 660 sc->txchainmask = IWN_ANT_B; 661 sc->rxchainmask = IWN_ANT_AB; 662 break; 663 case IWN_HW_REV_TYPE_5150: 664 sc->limits = &iwn5150_sensitivity_limits; 665 sc->fwname = "iwn-5150"; 666 break; 667 case IWN_HW_REV_TYPE_5300: 668 case IWN_HW_REV_TYPE_5350: 669 sc->limits = &iwn5000_sensitivity_limits; 670 sc->fwname = "iwn-5000"; 671 break; 672 case IWN_HW_REV_TYPE_1000: 673 sc->limits = &iwn1000_sensitivity_limits; 674 sc->fwname = "iwn-1000"; 675 break; 676 case IWN_HW_REV_TYPE_6000: 677 sc->limits = &iwn6000_sensitivity_limits; 678 sc->fwname = "iwn-6000"; 679 if (pid == PCI_PRODUCT_INTEL_WL_6200_1 || 680 pid == PCI_PRODUCT_INTEL_WL_6200_2) { 681 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 682 /* Override chains masks, ROM is known to be broken. */ 683 sc->txchainmask = IWN_ANT_BC; 684 sc->rxchainmask = IWN_ANT_BC; 685 } 686 break; 687 case IWN_HW_REV_TYPE_6050: 688 sc->limits = &iwn6000_sensitivity_limits; 689 sc->fwname = "iwn-6050"; 690 break; 691 case IWN_HW_REV_TYPE_6005: 692 sc->limits = &iwn6000_sensitivity_limits; 693 if (pid != PCI_PRODUCT_INTEL_WL_6005_1 && 694 pid != PCI_PRODUCT_INTEL_WL_6005_2) { 695 sc->fwname = "iwn-6030"; 696 sc->sc_flags |= IWN_FLAG_ADV_BT_COEX; 697 } else 698 sc->fwname = "iwn-6005"; 699 break; 700 case IWN_HW_REV_TYPE_2030: 701 sc->limits = &iwn2000_sensitivity_limits; 702 sc->fwname = "iwn-2030"; 703 sc->sc_flags |= IWN_FLAG_ADV_BT_COEX; 704 break; 705 case IWN_HW_REV_TYPE_2000: 706 sc->limits = &iwn2000_sensitivity_limits; 707 sc->fwname = "iwn-2000"; 708 break; 709 case IWN_HW_REV_TYPE_135: 710 sc->limits = &iwn2000_sensitivity_limits; 711 sc->fwname = "iwn-135"; 712 sc->sc_flags |= IWN_FLAG_ADV_BT_COEX; 713 break; 714 case IWN_HW_REV_TYPE_105: 715 sc->limits = &iwn2000_sensitivity_limits; 716 sc->fwname = "iwn-105"; 717 break; 718 default: 719 printf(": adapter type %d not supported\n", sc->hw_type); 720 return ENOTSUP; 721 } 722 return 0; 723 } 724 725 #if NBPFILTER > 0 726 /* 727 * Attach the interface to 802.11 radiotap. 728 */ 729 void 730 iwn_radiotap_attach(struct iwn_softc *sc) 731 { 732 bpfattach(&sc->sc_drvbpf, &sc->sc_ic.ic_if, DLT_IEEE802_11_RADIO, 733 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 734 735 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 736 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 737 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 738 739 sc->sc_txtap_len = sizeof sc->sc_txtapu; 740 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 741 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 742 } 743 #endif 744 745 int 746 iwn_detach(struct device *self, int flags) 747 { 748 struct iwn_softc *sc = (struct iwn_softc *)self; 749 struct ifnet *ifp = &sc->sc_ic.ic_if; 750 int qid; 751 752 timeout_del(&sc->calib_to); 753 task_del(systq, &sc->init_task); 754 755 /* Uninstall interrupt handler. */ 756 if (sc->sc_ih != NULL) 757 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 758 759 /* Free DMA resources. */ 760 iwn_free_rx_ring(sc, &sc->rxq); 761 for (qid = 0; qid < sc->ntxqs; qid++) 762 iwn_free_tx_ring(sc, &sc->txq[qid]); 763 iwn_free_sched(sc); 764 iwn_free_kw(sc); 765 if (sc->ict != NULL) 766 iwn_free_ict(sc); 767 iwn_free_fwmem(sc); 768 769 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 770 771 ieee80211_ifdetach(ifp); 772 if_detach(ifp); 773 774 return 0; 775 } 776 777 int 778 iwn_activate(struct device *self, int act) 779 { 780 struct iwn_softc *sc = (struct iwn_softc *)self; 781 struct ifnet *ifp = &sc->sc_ic.ic_if; 782 783 switch (act) { 784 case DVACT_SUSPEND: 785 if (ifp->if_flags & IFF_RUNNING) 786 iwn_stop(ifp); 787 break; 788 case DVACT_WAKEUP: 789 iwn_wakeup(sc); 790 break; 791 } 792 793 return 0; 794 } 795 796 void 797 iwn_wakeup(struct iwn_softc *sc) 798 { 799 pcireg_t reg; 800 801 /* Clear device-specific "PCI retry timeout" register (41h). */ 802 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 803 if (reg & 0xff00) 804 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 805 iwn_init_task(sc); 806 } 807 808 void 809 iwn_init_task(void *arg1) 810 { 811 struct iwn_softc *sc = arg1; 812 struct ifnet *ifp = &sc->sc_ic.ic_if; 813 int s; 814 815 rw_enter_write(&sc->sc_rwlock); 816 s = splnet(); 817 818 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 819 iwn_init(ifp); 820 821 splx(s); 822 rw_exit_write(&sc->sc_rwlock); 823 } 824 825 int 826 iwn_nic_lock(struct iwn_softc *sc) 827 { 828 int ntries; 829 830 /* Request exclusive access to NIC. */ 831 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 832 833 /* Spin until we actually get the lock. */ 834 for (ntries = 0; ntries < 1000; ntries++) { 835 if ((IWN_READ(sc, IWN_GP_CNTRL) & 836 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 837 IWN_GP_CNTRL_MAC_ACCESS_ENA) 838 return 0; 839 DELAY(10); 840 } 841 return ETIMEDOUT; 842 } 843 844 static __inline void 845 iwn_nic_unlock(struct iwn_softc *sc) 846 { 847 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 848 } 849 850 static __inline uint32_t 851 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 852 { 853 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 854 IWN_BARRIER_READ_WRITE(sc); 855 return IWN_READ(sc, IWN_PRPH_RDATA); 856 } 857 858 static __inline void 859 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 860 { 861 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 862 IWN_BARRIER_WRITE(sc); 863 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 864 } 865 866 static __inline void 867 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 868 { 869 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 870 } 871 872 static __inline void 873 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 874 { 875 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 876 } 877 878 static __inline void 879 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 880 const uint32_t *data, int count) 881 { 882 for (; count > 0; count--, data++, addr += 4) 883 iwn_prph_write(sc, addr, *data); 884 } 885 886 static __inline uint32_t 887 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 888 { 889 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 890 IWN_BARRIER_READ_WRITE(sc); 891 return IWN_READ(sc, IWN_MEM_RDATA); 892 } 893 894 static __inline void 895 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 896 { 897 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 898 IWN_BARRIER_WRITE(sc); 899 IWN_WRITE(sc, IWN_MEM_WDATA, data); 900 } 901 902 static __inline void 903 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 904 { 905 uint32_t tmp; 906 907 tmp = iwn_mem_read(sc, addr & ~3); 908 if (addr & 3) 909 tmp = (tmp & 0x0000ffff) | data << 16; 910 else 911 tmp = (tmp & 0xffff0000) | data; 912 iwn_mem_write(sc, addr & ~3, tmp); 913 } 914 915 static __inline void 916 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 917 int count) 918 { 919 for (; count > 0; count--, addr += 4) 920 *data++ = iwn_mem_read(sc, addr); 921 } 922 923 static __inline void 924 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 925 int count) 926 { 927 for (; count > 0; count--, addr += 4) 928 iwn_mem_write(sc, addr, val); 929 } 930 931 int 932 iwn_eeprom_lock(struct iwn_softc *sc) 933 { 934 int i, ntries; 935 936 for (i = 0; i < 100; i++) { 937 /* Request exclusive access to EEPROM. */ 938 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 939 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 940 941 /* Spin until we actually get the lock. */ 942 for (ntries = 0; ntries < 100; ntries++) { 943 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 944 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 945 return 0; 946 DELAY(10); 947 } 948 } 949 return ETIMEDOUT; 950 } 951 952 static __inline void 953 iwn_eeprom_unlock(struct iwn_softc *sc) 954 { 955 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 956 } 957 958 /* 959 * Initialize access by host to One Time Programmable ROM. 960 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 961 */ 962 int 963 iwn_init_otprom(struct iwn_softc *sc) 964 { 965 uint16_t prev, base, next; 966 int count, error; 967 968 /* Wait for clock stabilization before accessing prph. */ 969 if ((error = iwn_clock_wait(sc)) != 0) 970 return error; 971 972 if ((error = iwn_nic_lock(sc)) != 0) 973 return error; 974 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 975 DELAY(5); 976 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 977 iwn_nic_unlock(sc); 978 979 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 980 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 981 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 982 IWN_RESET_LINK_PWR_MGMT_DIS); 983 } 984 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 985 /* Clear ECC status. */ 986 IWN_SETBITS(sc, IWN_OTP_GP, 987 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 988 989 /* 990 * Find the block before last block (contains the EEPROM image) 991 * for HW without OTP shadow RAM. 992 */ 993 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 994 /* Switch to absolute addressing mode. */ 995 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 996 base = 0; 997 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 998 error = iwn_read_prom_data(sc, base, &next, 2); 999 if (error != 0) 1000 return error; 1001 if (next == 0) /* End of linked-list. */ 1002 break; 1003 prev = base; 1004 base = letoh16(next); 1005 } 1006 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1007 return EIO; 1008 /* Skip "next" word. */ 1009 sc->prom_base = prev + 1; 1010 } 1011 return 0; 1012 } 1013 1014 int 1015 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1016 { 1017 uint8_t *out = data; 1018 uint32_t val, tmp; 1019 int ntries; 1020 1021 addr += sc->prom_base; 1022 for (; count > 0; count -= 2, addr++) { 1023 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1024 for (ntries = 0; ntries < 10; ntries++) { 1025 val = IWN_READ(sc, IWN_EEPROM); 1026 if (val & IWN_EEPROM_READ_VALID) 1027 break; 1028 DELAY(5); 1029 } 1030 if (ntries == 10) { 1031 printf("%s: timeout reading ROM at 0x%x\n", 1032 sc->sc_dev.dv_xname, addr); 1033 return ETIMEDOUT; 1034 } 1035 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1036 /* OTPROM, check for ECC errors. */ 1037 tmp = IWN_READ(sc, IWN_OTP_GP); 1038 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1039 printf("%s: OTPROM ECC error at 0x%x\n", 1040 sc->sc_dev.dv_xname, addr); 1041 return EIO; 1042 } 1043 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1044 /* Correctable ECC error, clear bit. */ 1045 IWN_SETBITS(sc, IWN_OTP_GP, 1046 IWN_OTP_GP_ECC_CORR_STTS); 1047 } 1048 } 1049 *out++ = val >> 16; 1050 if (count > 1) 1051 *out++ = val >> 24; 1052 } 1053 return 0; 1054 } 1055 1056 int 1057 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1058 bus_size_t size, bus_size_t alignment) 1059 { 1060 int nsegs, error; 1061 1062 dma->tag = tag; 1063 dma->size = size; 1064 1065 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1066 &dma->map); 1067 if (error != 0) 1068 goto fail; 1069 1070 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1071 BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1072 if (error != 0) 1073 goto fail; 1074 1075 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1076 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 1077 if (error != 0) 1078 goto fail; 1079 1080 error = bus_dmamap_load_raw(tag, dma->map, &dma->seg, 1, size, 1081 BUS_DMA_NOWAIT); 1082 if (error != 0) 1083 goto fail; 1084 1085 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1086 1087 dma->paddr = dma->map->dm_segs[0].ds_addr; 1088 if (kvap != NULL) 1089 *kvap = dma->vaddr; 1090 1091 return 0; 1092 1093 fail: iwn_dma_contig_free(dma); 1094 return error; 1095 } 1096 1097 void 1098 iwn_dma_contig_free(struct iwn_dma_info *dma) 1099 { 1100 if (dma->map != NULL) { 1101 if (dma->vaddr != NULL) { 1102 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1103 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1104 bus_dmamap_unload(dma->tag, dma->map); 1105 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1106 bus_dmamem_free(dma->tag, &dma->seg, 1); 1107 dma->vaddr = NULL; 1108 } 1109 bus_dmamap_destroy(dma->tag, dma->map); 1110 dma->map = NULL; 1111 } 1112 } 1113 1114 int 1115 iwn_alloc_sched(struct iwn_softc *sc) 1116 { 1117 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1118 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1119 (void **)&sc->sched, sc->schedsz, 1024); 1120 } 1121 1122 void 1123 iwn_free_sched(struct iwn_softc *sc) 1124 { 1125 iwn_dma_contig_free(&sc->sched_dma); 1126 } 1127 1128 int 1129 iwn_alloc_kw(struct iwn_softc *sc) 1130 { 1131 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1132 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1133 4096); 1134 } 1135 1136 void 1137 iwn_free_kw(struct iwn_softc *sc) 1138 { 1139 iwn_dma_contig_free(&sc->kw_dma); 1140 } 1141 1142 int 1143 iwn_alloc_ict(struct iwn_softc *sc) 1144 { 1145 /* ICT table must be aligned on a 4KB boundary. */ 1146 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1147 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1148 } 1149 1150 void 1151 iwn_free_ict(struct iwn_softc *sc) 1152 { 1153 iwn_dma_contig_free(&sc->ict_dma); 1154 } 1155 1156 int 1157 iwn_alloc_fwmem(struct iwn_softc *sc) 1158 { 1159 /* Must be aligned on a 16-byte boundary. */ 1160 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1161 sc->fwsz, 16); 1162 } 1163 1164 void 1165 iwn_free_fwmem(struct iwn_softc *sc) 1166 { 1167 iwn_dma_contig_free(&sc->fw_dma); 1168 } 1169 1170 int 1171 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1172 { 1173 bus_size_t size; 1174 int i, error; 1175 1176 ring->cur = 0; 1177 1178 /* Allocate RX descriptors (256-byte aligned). */ 1179 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1180 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1181 (void **)&ring->desc, size, 256); 1182 if (error != 0) { 1183 printf("%s: could not allocate RX ring DMA memory\n", 1184 sc->sc_dev.dv_xname); 1185 goto fail; 1186 } 1187 1188 /* Allocate RX status area (16-byte aligned). */ 1189 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1190 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1191 if (error != 0) { 1192 printf("%s: could not allocate RX status DMA memory\n", 1193 sc->sc_dev.dv_xname); 1194 goto fail; 1195 } 1196 1197 /* 1198 * Allocate and map RX buffers. 1199 */ 1200 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1201 struct iwn_rx_data *data = &ring->data[i]; 1202 1203 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1204 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1205 &data->map); 1206 if (error != 0) { 1207 printf("%s: could not create RX buf DMA map\n", 1208 sc->sc_dev.dv_xname); 1209 goto fail; 1210 } 1211 1212 data->m = MCLGETL(NULL, M_DONTWAIT, IWN_RBUF_SIZE); 1213 if (data->m == NULL) { 1214 printf("%s: could not allocate RX mbuf\n", 1215 sc->sc_dev.dv_xname); 1216 error = ENOBUFS; 1217 goto fail; 1218 } 1219 1220 error = bus_dmamap_load(sc->sc_dmat, data->map, 1221 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1222 BUS_DMA_NOWAIT | BUS_DMA_READ); 1223 if (error != 0) { 1224 printf("%s: can't map mbuf (error %d)\n", 1225 sc->sc_dev.dv_xname, error); 1226 goto fail; 1227 } 1228 1229 /* Set physical address of RX buffer (256-byte aligned). */ 1230 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1231 } 1232 1233 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1234 BUS_DMASYNC_PREWRITE); 1235 1236 return 0; 1237 1238 fail: iwn_free_rx_ring(sc, ring); 1239 return error; 1240 } 1241 1242 void 1243 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1244 { 1245 int ntries; 1246 1247 if (iwn_nic_lock(sc) == 0) { 1248 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1249 for (ntries = 0; ntries < 1000; ntries++) { 1250 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1251 IWN_FH_RX_STATUS_IDLE) 1252 break; 1253 DELAY(10); 1254 } 1255 iwn_nic_unlock(sc); 1256 } 1257 ring->cur = 0; 1258 sc->last_rx_valid = 0; 1259 } 1260 1261 void 1262 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1263 { 1264 int i; 1265 1266 iwn_dma_contig_free(&ring->desc_dma); 1267 iwn_dma_contig_free(&ring->stat_dma); 1268 1269 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1270 struct iwn_rx_data *data = &ring->data[i]; 1271 1272 if (data->m != NULL) { 1273 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1274 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1275 bus_dmamap_unload(sc->sc_dmat, data->map); 1276 m_freem(data->m); 1277 } 1278 if (data->map != NULL) 1279 bus_dmamap_destroy(sc->sc_dmat, data->map); 1280 } 1281 } 1282 1283 int 1284 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1285 { 1286 bus_addr_t paddr; 1287 bus_size_t size; 1288 int i, error; 1289 1290 ring->qid = qid; 1291 ring->queued = 0; 1292 ring->cur = 0; 1293 1294 /* Allocate TX descriptors (256-byte aligned). */ 1295 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1296 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1297 (void **)&ring->desc, size, 256); 1298 if (error != 0) { 1299 printf("%s: could not allocate TX ring DMA memory\n", 1300 sc->sc_dev.dv_xname); 1301 goto fail; 1302 } 1303 1304 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1305 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1306 (void **)&ring->cmd, size, 4); 1307 if (error != 0) { 1308 printf("%s: could not allocate TX cmd DMA memory\n", 1309 sc->sc_dev.dv_xname); 1310 goto fail; 1311 } 1312 1313 paddr = ring->cmd_dma.paddr; 1314 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1315 struct iwn_tx_data *data = &ring->data[i]; 1316 1317 data->cmd_paddr = paddr; 1318 data->scratch_paddr = paddr + 12; 1319 paddr += sizeof (struct iwn_tx_cmd); 1320 1321 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1322 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1323 &data->map); 1324 if (error != 0) { 1325 printf("%s: could not create TX buf DMA map\n", 1326 sc->sc_dev.dv_xname); 1327 goto fail; 1328 } 1329 } 1330 return 0; 1331 1332 fail: iwn_free_tx_ring(sc, ring); 1333 return error; 1334 } 1335 1336 void 1337 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1338 { 1339 int i; 1340 1341 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1342 struct iwn_tx_data *data = &ring->data[i]; 1343 1344 if (data->m != NULL) { 1345 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1346 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1347 bus_dmamap_unload(sc->sc_dmat, data->map); 1348 m_freem(data->m); 1349 data->m = NULL; 1350 } 1351 } 1352 /* Clear TX descriptors. */ 1353 memset(ring->desc, 0, ring->desc_dma.size); 1354 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1355 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1356 sc->qfullmsk &= ~(1 << ring->qid); 1357 ring->queued = 0; 1358 ring->cur = 0; 1359 } 1360 1361 void 1362 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1363 { 1364 int i; 1365 1366 iwn_dma_contig_free(&ring->desc_dma); 1367 iwn_dma_contig_free(&ring->cmd_dma); 1368 1369 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1370 struct iwn_tx_data *data = &ring->data[i]; 1371 1372 if (data->m != NULL) { 1373 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1374 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1375 bus_dmamap_unload(sc->sc_dmat, data->map); 1376 m_freem(data->m); 1377 } 1378 if (data->map != NULL) 1379 bus_dmamap_destroy(sc->sc_dmat, data->map); 1380 } 1381 } 1382 1383 void 1384 iwn5000_ict_reset(struct iwn_softc *sc) 1385 { 1386 /* Disable interrupts. */ 1387 IWN_WRITE(sc, IWN_INT_MASK, 0); 1388 1389 /* Reset ICT table. */ 1390 memset(sc->ict, 0, IWN_ICT_SIZE); 1391 sc->ict_cur = 0; 1392 1393 /* Set physical address of ICT table (4KB aligned). */ 1394 DPRINTF(("enabling ICT\n")); 1395 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1396 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1397 1398 /* Enable periodic RX interrupt. */ 1399 sc->int_mask |= IWN_INT_RX_PERIODIC; 1400 /* Switch to ICT interrupt mode in driver. */ 1401 sc->sc_flags |= IWN_FLAG_USE_ICT; 1402 1403 /* Re-enable interrupts. */ 1404 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1405 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1406 } 1407 1408 int 1409 iwn_read_eeprom(struct iwn_softc *sc) 1410 { 1411 struct iwn_ops *ops = &sc->ops; 1412 struct ieee80211com *ic = &sc->sc_ic; 1413 uint16_t val; 1414 int error; 1415 1416 /* Check whether adapter has an EEPROM or an OTPROM. */ 1417 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1418 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1419 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1420 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1421 "OTPROM" : "EEPROM")); 1422 1423 /* Adapter has to be powered on for EEPROM access to work. */ 1424 if ((error = iwn_apm_init(sc)) != 0) { 1425 printf("%s: could not power ON adapter\n", 1426 sc->sc_dev.dv_xname); 1427 return error; 1428 } 1429 1430 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1431 printf("%s: bad ROM signature\n", sc->sc_dev.dv_xname); 1432 return EIO; 1433 } 1434 if ((error = iwn_eeprom_lock(sc)) != 0) { 1435 printf("%s: could not lock ROM (error=%d)\n", 1436 sc->sc_dev.dv_xname, error); 1437 return error; 1438 } 1439 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1440 if ((error = iwn_init_otprom(sc)) != 0) { 1441 printf("%s: could not initialize OTPROM\n", 1442 sc->sc_dev.dv_xname); 1443 return error; 1444 } 1445 } 1446 1447 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1448 DPRINTF(("SKU capabilities=0x%04x\n", letoh16(val))); 1449 /* Check if HT support is bonded out. */ 1450 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1451 sc->sc_flags |= IWN_FLAG_HAS_11N; 1452 1453 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1454 sc->rfcfg = letoh16(val); 1455 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1456 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1457 if (sc->txchainmask == 0) 1458 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1459 if (sc->rxchainmask == 0) 1460 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1461 1462 /* Read MAC address. */ 1463 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1464 1465 /* Read adapter-specific information from EEPROM. */ 1466 ops->read_eeprom(sc); 1467 1468 iwn_apm_stop(sc); /* Power OFF adapter. */ 1469 1470 iwn_eeprom_unlock(sc); 1471 return 0; 1472 } 1473 1474 void 1475 iwn4965_read_eeprom(struct iwn_softc *sc) 1476 { 1477 uint32_t addr; 1478 uint16_t val; 1479 int i; 1480 1481 /* Read regulatory domain (4 ASCII characters). */ 1482 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1483 1484 /* Read the list of authorized channels. */ 1485 for (i = 0; i < 7; i++) { 1486 addr = iwn4965_regulatory_bands[i]; 1487 iwn_read_eeprom_channels(sc, i, addr); 1488 } 1489 1490 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1491 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1492 sc->maxpwr2GHz = val & 0xff; 1493 sc->maxpwr5GHz = val >> 8; 1494 /* Check that EEPROM values are within valid range. */ 1495 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1496 sc->maxpwr5GHz = 38; 1497 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1498 sc->maxpwr2GHz = 38; 1499 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1500 1501 /* Read samples for each TX power group. */ 1502 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1503 sizeof sc->bands); 1504 1505 /* Read voltage at which samples were taken. */ 1506 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1507 sc->eeprom_voltage = (int16_t)letoh16(val); 1508 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1509 1510 #ifdef IWN_DEBUG 1511 /* Print samples. */ 1512 if (iwn_debug > 0) { 1513 for (i = 0; i < IWN_NBANDS; i++) 1514 iwn4965_print_power_group(sc, i); 1515 } 1516 #endif 1517 } 1518 1519 #ifdef IWN_DEBUG 1520 void 1521 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1522 { 1523 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1524 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1525 int j, c; 1526 1527 printf("===band %d===\n", i); 1528 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1529 printf("chan1 num=%d\n", chans[0].num); 1530 for (c = 0; c < 2; c++) { 1531 for (j = 0; j < IWN_NSAMPLES; j++) { 1532 printf("chain %d, sample %d: temp=%d gain=%d " 1533 "power=%d pa_det=%d\n", c, j, 1534 chans[0].samples[c][j].temp, 1535 chans[0].samples[c][j].gain, 1536 chans[0].samples[c][j].power, 1537 chans[0].samples[c][j].pa_det); 1538 } 1539 } 1540 printf("chan2 num=%d\n", chans[1].num); 1541 for (c = 0; c < 2; c++) { 1542 for (j = 0; j < IWN_NSAMPLES; j++) { 1543 printf("chain %d, sample %d: temp=%d gain=%d " 1544 "power=%d pa_det=%d\n", c, j, 1545 chans[1].samples[c][j].temp, 1546 chans[1].samples[c][j].gain, 1547 chans[1].samples[c][j].power, 1548 chans[1].samples[c][j].pa_det); 1549 } 1550 } 1551 } 1552 #endif 1553 1554 void 1555 iwn5000_read_eeprom(struct iwn_softc *sc) 1556 { 1557 struct iwn5000_eeprom_calib_hdr hdr; 1558 int32_t volt; 1559 uint32_t base, addr; 1560 uint16_t val; 1561 int i; 1562 1563 /* Read regulatory domain (4 ASCII characters). */ 1564 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1565 base = letoh16(val); 1566 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1567 sc->eeprom_domain, 4); 1568 1569 /* Read the list of authorized channels. */ 1570 for (i = 0; i < 7; i++) { 1571 addr = base + iwn5000_regulatory_bands[i]; 1572 iwn_read_eeprom_channels(sc, i, addr); 1573 } 1574 1575 /* Read enhanced TX power information for 6000 Series. */ 1576 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1577 iwn_read_eeprom_enhinfo(sc); 1578 1579 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1580 base = letoh16(val); 1581 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1582 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1583 hdr.version, hdr.pa_type, letoh16(hdr.volt))); 1584 sc->calib_ver = hdr.version; 1585 1586 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 1587 sc->hw_type == IWN_HW_REV_TYPE_2000 || 1588 sc->hw_type == IWN_HW_REV_TYPE_135 || 1589 sc->hw_type == IWN_HW_REV_TYPE_105) { 1590 sc->eeprom_voltage = letoh16(hdr.volt); 1591 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1592 sc->eeprom_temp = letoh16(val); 1593 iwn_read_prom_data(sc, base + IWN2000_EEPROM_RAWTEMP, &val, 2); 1594 sc->eeprom_rawtemp = letoh16(val); 1595 } 1596 1597 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1598 /* Compute temperature offset. */ 1599 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1600 sc->eeprom_temp = letoh16(val); 1601 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1602 volt = letoh16(val); 1603 sc->temp_off = sc->eeprom_temp - (volt / -5); 1604 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1605 sc->eeprom_temp, volt, sc->temp_off)); 1606 } else { 1607 /* Read crystal calibration. */ 1608 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1609 &sc->eeprom_crystal, sizeof (uint32_t)); 1610 DPRINTF(("crystal calibration 0x%08x\n", 1611 letoh32(sc->eeprom_crystal))); 1612 } 1613 } 1614 1615 void 1616 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1617 { 1618 struct ieee80211com *ic = &sc->sc_ic; 1619 const struct iwn_chan_band *band = &iwn_bands[n]; 1620 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1621 uint8_t chan; 1622 int i; 1623 1624 iwn_read_prom_data(sc, addr, channels, 1625 band->nchan * sizeof (struct iwn_eeprom_chan)); 1626 1627 for (i = 0; i < band->nchan; i++) { 1628 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1629 continue; 1630 1631 chan = band->chan[i]; 1632 1633 if (n == 0) { /* 2GHz band */ 1634 ic->ic_channels[chan].ic_freq = 1635 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1636 ic->ic_channels[chan].ic_flags = 1637 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1638 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1639 1640 } else if (n < 5) { /* 5GHz band */ 1641 /* 1642 * Some adapters support channels 7, 8, 11 and 12 1643 * both in the 2GHz and 4.9GHz bands. 1644 * Because of limitations in our net80211 layer, 1645 * we don't support them in the 4.9GHz band. 1646 */ 1647 if (chan <= 14) 1648 continue; 1649 1650 ic->ic_channels[chan].ic_freq = 1651 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1652 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1653 /* We have at least one valid 5GHz channel. */ 1654 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1655 } else { /* 40 MHz */ 1656 sc->maxpwr40[chan] = channels[i].maxpwr; 1657 ic->ic_channels[chan].ic_flags |= IEEE80211_CHAN_40MHZ; 1658 } 1659 1660 if (n < 5) { 1661 /* Is active scan allowed on this channel? */ 1662 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1663 ic->ic_channels[chan].ic_flags |= 1664 IEEE80211_CHAN_PASSIVE; 1665 } 1666 1667 /* Save maximum allowed TX power for this channel. */ 1668 sc->maxpwr[chan] = channels[i].maxpwr; 1669 1670 if (sc->sc_flags & IWN_FLAG_HAS_11N) 1671 ic->ic_channels[chan].ic_flags |= 1672 IEEE80211_CHAN_HT; 1673 } 1674 1675 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d maxpwr40=%d\n", 1676 chan, channels[i].flags, sc->maxpwr[chan], 1677 sc->maxpwr40[chan])); 1678 } 1679 } 1680 1681 void 1682 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1683 { 1684 struct iwn_eeprom_enhinfo enhinfo[35]; 1685 uint16_t val, base; 1686 int8_t maxpwr; 1687 int i; 1688 1689 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1690 base = letoh16(val); 1691 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1692 enhinfo, sizeof enhinfo); 1693 1694 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1695 for (i = 0; i < nitems(enhinfo); i++) { 1696 if ((enhinfo[i].flags & IWN_TXP_VALID) == 0) 1697 continue; /* Skip invalid entries. */ 1698 1699 maxpwr = 0; 1700 if (sc->txchainmask & IWN_ANT_A) 1701 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1702 if (sc->txchainmask & IWN_ANT_B) 1703 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1704 if (sc->txchainmask & IWN_ANT_C) 1705 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1706 if (sc->ntxchains == 2) 1707 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1708 else if (sc->ntxchains == 3) 1709 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1710 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1711 1712 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1713 sc->enh_maxpwr[i] = maxpwr; 1714 } 1715 } 1716 1717 struct ieee80211_node * 1718 iwn_node_alloc(struct ieee80211com *ic) 1719 { 1720 return malloc(sizeof (struct iwn_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1721 } 1722 1723 void 1724 iwn_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 1725 { 1726 struct iwn_softc *sc = ic->ic_if.if_softc; 1727 struct iwn_node *wn = (void *)ni; 1728 uint8_t rate; 1729 int ridx, i; 1730 1731 if ((ni->ni_flags & IEEE80211_NODE_HT) == 0) 1732 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1733 1734 /* Start at lowest available bit-rate, AMRR/MiRA will raise. */ 1735 ni->ni_txrate = 0; 1736 ni->ni_txmcs = 0; 1737 1738 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1739 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1740 /* Map 802.11 rate to HW rate index. */ 1741 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 1742 if (iwn_rates[ridx].plcp != IWN_PLCP_INVALID && 1743 iwn_rates[ridx].rate == rate) 1744 break; 1745 } 1746 wn->ridx[i] = ridx; 1747 } 1748 } 1749 1750 int 1751 iwn_media_change(struct ifnet *ifp) 1752 { 1753 struct iwn_softc *sc = ifp->if_softc; 1754 struct ieee80211com *ic = &sc->sc_ic; 1755 uint8_t rate, ridx; 1756 int error; 1757 1758 error = ieee80211_media_change(ifp); 1759 if (error != ENETRESET) 1760 return error; 1761 1762 if (ic->ic_fixed_mcs != -1) 1763 sc->fixed_ridx = iwn_mcs2ridx[ic->ic_fixed_mcs]; 1764 if (ic->ic_fixed_rate != -1) { 1765 rate = ic->ic_sup_rates[ic->ic_curmode]. 1766 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1767 /* Map 802.11 rate to HW rate index. */ 1768 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1769 if (iwn_rates[ridx].plcp != IWN_PLCP_INVALID && 1770 iwn_rates[ridx].rate == rate) 1771 break; 1772 sc->fixed_ridx = ridx; 1773 } 1774 1775 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1776 (IFF_UP | IFF_RUNNING)) { 1777 iwn_stop(ifp); 1778 error = iwn_init(ifp); 1779 } 1780 return error; 1781 } 1782 1783 int 1784 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1785 { 1786 struct ifnet *ifp = &ic->ic_if; 1787 struct iwn_softc *sc = ifp->if_softc; 1788 struct ieee80211_node *ni = ic->ic_bss; 1789 int error; 1790 1791 if (ic->ic_state == IEEE80211_S_RUN) { 1792 if (nstate == IEEE80211_S_SCAN) { 1793 /* 1794 * During RUN->SCAN we don't call sc_newstate() so 1795 * we must stop A-MPDU Tx ourselves in this case. 1796 */ 1797 ieee80211_stop_ampdu_tx(ic, ni, -1); 1798 ieee80211_ba_del(ni); 1799 } 1800 timeout_del(&sc->calib_to); 1801 sc->calib.state = IWN_CALIB_STATE_INIT; 1802 if (sc->sc_flags & IWN_FLAG_BGSCAN) 1803 iwn_scan_abort(sc); 1804 } 1805 1806 if (ic->ic_state == IEEE80211_S_SCAN) { 1807 if (nstate == IEEE80211_S_SCAN) { 1808 if (sc->sc_flags & IWN_FLAG_SCANNING) 1809 return 0; 1810 } else 1811 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1812 /* Turn LED off when leaving scan state. */ 1813 iwn_set_led(sc, IWN_LED_LINK, 1, 0); 1814 } 1815 1816 if (ic->ic_state >= IEEE80211_S_ASSOC && 1817 nstate <= IEEE80211_S_ASSOC) { 1818 /* Reset state to handle re- and disassociations. */ 1819 sc->rxon.associd = 0; 1820 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1821 sc->rxon.flags &= ~htole32(IWN_RXON_HT_CHANMODE_MIXED2040 | 1822 IWN_RXON_HT_CHANMODE_PURE40 | IWN_RXON_HT_HT40MINUS); 1823 sc->calib.state = IWN_CALIB_STATE_INIT; 1824 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 1825 if (error != 0) 1826 printf("%s: RXON command failed\n", 1827 sc->sc_dev.dv_xname); 1828 } 1829 1830 switch (nstate) { 1831 case IEEE80211_S_SCAN: 1832 /* Make the link LED blink while we're scanning. */ 1833 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1834 1835 if ((sc->sc_flags & IWN_FLAG_BGSCAN) == 0) { 1836 ieee80211_set_link_state(ic, LINK_STATE_DOWN); 1837 ieee80211_node_cleanup(ic, ic->ic_bss); 1838 } 1839 if (ifp->if_flags & IFF_DEBUG) 1840 printf("%s: %s -> %s\n", ifp->if_xname, 1841 ieee80211_state_name[ic->ic_state], 1842 ieee80211_state_name[nstate]); 1843 ic->ic_state = nstate; 1844 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ, 0)) != 0) { 1845 printf("%s: could not initiate scan\n", 1846 sc->sc_dev.dv_xname); 1847 } 1848 return error; 1849 1850 case IEEE80211_S_ASSOC: 1851 if (ic->ic_state != IEEE80211_S_RUN) 1852 break; 1853 /* FALLTHROUGH */ 1854 case IEEE80211_S_AUTH: 1855 if ((error = iwn_auth(sc, arg)) != 0) { 1856 printf("%s: could not move to auth state\n", 1857 sc->sc_dev.dv_xname); 1858 return error; 1859 } 1860 break; 1861 1862 case IEEE80211_S_RUN: 1863 if ((error = iwn_run(sc)) != 0) { 1864 printf("%s: could not move to run state\n", 1865 sc->sc_dev.dv_xname); 1866 return error; 1867 } 1868 break; 1869 1870 case IEEE80211_S_INIT: 1871 sc->calib.state = IWN_CALIB_STATE_INIT; 1872 break; 1873 } 1874 1875 return sc->sc_newstate(ic, nstate, arg); 1876 } 1877 1878 void 1879 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1880 { 1881 struct iwn_softc *sc = arg; 1882 struct iwn_node *wn = (void *)ni; 1883 1884 if ((ni->ni_flags & IEEE80211_NODE_HT) == 0) { 1885 int old_txrate = ni->ni_txrate; 1886 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1887 if (old_txrate != ni->ni_txrate) 1888 iwn_set_link_quality(sc, ni); 1889 } 1890 } 1891 1892 void 1893 iwn_calib_timeout(void *arg) 1894 { 1895 struct iwn_softc *sc = arg; 1896 struct ieee80211com *ic = &sc->sc_ic; 1897 int s; 1898 1899 s = splnet(); 1900 if (ic->ic_fixed_rate == -1) { 1901 if (ic->ic_opmode == IEEE80211_M_STA) 1902 iwn_iter_func(sc, ic->ic_bss); 1903 else 1904 ieee80211_iterate_nodes(ic, iwn_iter_func, sc); 1905 } 1906 /* Force automatic TX power calibration every 60 secs. */ 1907 if (++sc->calib_cnt >= 120) { 1908 uint32_t flags = 0; 1909 1910 DPRINTFN(2, ("sending request for statistics\n")); 1911 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1912 sizeof flags, 1); 1913 sc->calib_cnt = 0; 1914 } 1915 splx(s); 1916 1917 /* Automatic rate control triggered every 500ms. */ 1918 timeout_add_msec(&sc->calib_to, 500); 1919 } 1920 1921 int 1922 iwn_ccmp_decap(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1923 { 1924 struct ieee80211com *ic = &sc->sc_ic; 1925 struct ieee80211_key *k = &ni->ni_pairwise_key; 1926 struct ieee80211_frame *wh; 1927 uint64_t pn, *prsc; 1928 uint8_t *ivp; 1929 uint8_t tid; 1930 int hdrlen, hasqos; 1931 1932 wh = mtod(m, struct ieee80211_frame *); 1933 hdrlen = ieee80211_get_hdrlen(wh); 1934 ivp = (uint8_t *)wh + hdrlen; 1935 1936 /* Check that ExtIV bit is set. */ 1937 if (!(ivp[3] & IEEE80211_WEP_EXTIV)) { 1938 DPRINTF(("CCMP decap ExtIV not set\n")); 1939 return 1; 1940 } 1941 hasqos = ieee80211_has_qos(wh); 1942 tid = hasqos ? ieee80211_get_qos(wh) & IEEE80211_QOS_TID : 0; 1943 prsc = &k->k_rsc[tid]; 1944 1945 /* Extract the 48-bit PN from the CCMP header. */ 1946 pn = (uint64_t)ivp[0] | 1947 (uint64_t)ivp[1] << 8 | 1948 (uint64_t)ivp[4] << 16 | 1949 (uint64_t)ivp[5] << 24 | 1950 (uint64_t)ivp[6] << 32 | 1951 (uint64_t)ivp[7] << 40; 1952 if (pn <= *prsc) { 1953 DPRINTF(("CCMP replayed\n")); 1954 ic->ic_stats.is_ccmp_replays++; 1955 return 1; 1956 } 1957 /* Last seen packet number is updated in ieee80211_inputm(). */ 1958 1959 /* Strip MIC. IV will be stripped by ieee80211_inputm(). */ 1960 m_adj(m, -IEEE80211_CCMP_MICLEN); 1961 return 0; 1962 } 1963 1964 /* 1965 * Process an RX_PHY firmware notification. This is usually immediately 1966 * followed by an MPDU_RX_DONE notification. 1967 */ 1968 void 1969 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1970 struct iwn_rx_data *data) 1971 { 1972 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1973 1974 DPRINTFN(2, ("received PHY stats\n")); 1975 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1976 sizeof (*stat), BUS_DMASYNC_POSTREAD); 1977 1978 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1979 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1980 sc->last_rx_valid = IWN_LAST_RX_VALID; 1981 /* 1982 * The firmware does not send separate RX_PHY 1983 * notifications for A-MPDU subframes. 1984 */ 1985 if (stat->flags & htole16(IWN_STAT_FLAG_AGG)) 1986 sc->last_rx_valid |= IWN_LAST_RX_AMPDU; 1987 } 1988 1989 /* 1990 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1991 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1992 */ 1993 void 1994 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1995 struct iwn_rx_data *data, struct mbuf_list *ml) 1996 { 1997 struct iwn_ops *ops = &sc->ops; 1998 struct ieee80211com *ic = &sc->sc_ic; 1999 struct ifnet *ifp = &ic->ic_if; 2000 struct iwn_rx_ring *ring = &sc->rxq; 2001 struct ieee80211_frame *wh; 2002 struct ieee80211_rxinfo rxi; 2003 struct ieee80211_node *ni; 2004 struct mbuf *m, *m1; 2005 struct iwn_rx_stat *stat; 2006 caddr_t head; 2007 uint32_t flags; 2008 int error, len, rssi; 2009 uint16_t chan; 2010 2011 if (desc->type == IWN_MPDU_RX_DONE) { 2012 /* Check for prior RX_PHY notification. */ 2013 if (!sc->last_rx_valid) { 2014 DPRINTF(("missing RX_PHY\n")); 2015 return; 2016 } 2017 sc->last_rx_valid &= ~IWN_LAST_RX_VALID; 2018 stat = &sc->last_rx_stat; 2019 if ((sc->last_rx_valid & IWN_LAST_RX_AMPDU) && 2020 (stat->flags & htole16(IWN_STAT_FLAG_AGG)) == 0) { 2021 DPRINTF(("missing RX_PHY (expecting A-MPDU)\n")); 2022 return; 2023 } 2024 if ((sc->last_rx_valid & IWN_LAST_RX_AMPDU) == 0 && 2025 (stat->flags & htole16(IWN_STAT_FLAG_AGG))) { 2026 DPRINTF(("missing RX_PHY (unexpected A-MPDU)\n")); 2027 return; 2028 } 2029 } else 2030 stat = (struct iwn_rx_stat *)(desc + 1); 2031 2032 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 2033 BUS_DMASYNC_POSTREAD); 2034 2035 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2036 printf("%s: invalid RX statistic header\n", 2037 sc->sc_dev.dv_xname); 2038 return; 2039 } 2040 if (desc->type == IWN_MPDU_RX_DONE) { 2041 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2042 head = (caddr_t)(mpdu + 1); 2043 len = letoh16(mpdu->len); 2044 } else { 2045 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2046 len = letoh16(stat->len); 2047 } 2048 2049 flags = letoh32(*(uint32_t *)(head + len)); 2050 2051 /* Discard frames with a bad FCS early. */ 2052 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2053 DPRINTFN(2, ("RX flags error %x\n", flags)); 2054 ifp->if_ierrors++; 2055 return; 2056 } 2057 /* Discard frames that are too short. */ 2058 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2059 /* Allow control frames in monitor mode. */ 2060 if (len < sizeof (struct ieee80211_frame_cts)) { 2061 DPRINTF(("frame too short: %d\n", len)); 2062 ic->ic_stats.is_rx_tooshort++; 2063 ifp->if_ierrors++; 2064 return; 2065 } 2066 } else if (len < sizeof (*wh)) { 2067 DPRINTF(("frame too short: %d\n", len)); 2068 ic->ic_stats.is_rx_tooshort++; 2069 ifp->if_ierrors++; 2070 return; 2071 } 2072 2073 m1 = MCLGETL(NULL, M_DONTWAIT, IWN_RBUF_SIZE); 2074 if (m1 == NULL) { 2075 ic->ic_stats.is_rx_nombuf++; 2076 ifp->if_ierrors++; 2077 return; 2078 } 2079 bus_dmamap_unload(sc->sc_dmat, data->map); 2080 2081 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 2082 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 2083 if (error != 0) { 2084 m_freem(m1); 2085 2086 /* Try to reload the old mbuf. */ 2087 error = bus_dmamap_load(sc->sc_dmat, data->map, 2088 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 2089 BUS_DMA_NOWAIT | BUS_DMA_READ); 2090 if (error != 0) { 2091 panic("%s: could not load old RX mbuf", 2092 sc->sc_dev.dv_xname); 2093 } 2094 /* Physical address may have changed. */ 2095 ring->desc[ring->cur] = 2096 htole32(data->map->dm_segs[0].ds_addr >> 8); 2097 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2098 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2099 BUS_DMASYNC_PREWRITE); 2100 ifp->if_ierrors++; 2101 return; 2102 } 2103 2104 m = data->m; 2105 data->m = m1; 2106 /* Update RX descriptor. */ 2107 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 2108 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2109 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2110 BUS_DMASYNC_PREWRITE); 2111 2112 /* Finalize mbuf. */ 2113 m->m_data = head; 2114 m->m_pkthdr.len = m->m_len = len; 2115 2116 /* 2117 * Grab a reference to the source node. Note that control frames are 2118 * shorter than struct ieee80211_frame but ieee80211_find_rxnode() 2119 * is being careful about control frames. 2120 */ 2121 wh = mtod(m, struct ieee80211_frame *); 2122 if (len < sizeof (*wh) && 2123 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 2124 ic->ic_stats.is_rx_tooshort++; 2125 ifp->if_ierrors++; 2126 m_freem(m); 2127 return; 2128 } 2129 ni = ieee80211_find_rxnode(ic, wh); 2130 2131 memset(&rxi, 0, sizeof(rxi)); 2132 if (((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) 2133 && (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 2134 !IEEE80211_IS_MULTICAST(wh->i_addr1) && 2135 (ni->ni_flags & IEEE80211_NODE_RXPROT) && 2136 ni->ni_pairwise_key.k_cipher == IEEE80211_CIPHER_CCMP) { 2137 if ((flags & IWN_RX_CIPHER_MASK) != IWN_RX_CIPHER_CCMP) { 2138 ic->ic_stats.is_ccmp_dec_errs++; 2139 ifp->if_ierrors++; 2140 m_freem(m); 2141 ieee80211_release_node(ic, ni); 2142 return; 2143 } 2144 /* Check whether decryption was successful or not. */ 2145 if ((desc->type == IWN_MPDU_RX_DONE && 2146 (flags & (IWN_RX_MPDU_DEC | IWN_RX_MPDU_MIC_OK)) != 2147 (IWN_RX_MPDU_DEC | IWN_RX_MPDU_MIC_OK)) || 2148 (desc->type != IWN_MPDU_RX_DONE && 2149 (flags & IWN_RX_DECRYPT_MASK) != IWN_RX_DECRYPT_OK)) { 2150 DPRINTF(("CCMP decryption failed 0x%x\n", flags)); 2151 ic->ic_stats.is_ccmp_dec_errs++; 2152 ifp->if_ierrors++; 2153 m_freem(m); 2154 ieee80211_release_node(ic, ni); 2155 return; 2156 } 2157 if (iwn_ccmp_decap(sc, m, ni) != 0) { 2158 ifp->if_ierrors++; 2159 m_freem(m); 2160 ieee80211_release_node(ic, ni); 2161 return; 2162 } 2163 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 2164 } 2165 2166 rssi = ops->get_rssi(stat); 2167 2168 chan = stat->chan; 2169 if (chan > IEEE80211_CHAN_MAX) 2170 chan = IEEE80211_CHAN_MAX; 2171 2172 #if NBPFILTER > 0 2173 if (sc->sc_drvbpf != NULL) { 2174 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2175 uint16_t chan_flags; 2176 2177 tap->wr_flags = 0; 2178 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2179 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2180 tap->wr_chan_freq = htole16(ic->ic_channels[chan].ic_freq); 2181 chan_flags = ic->ic_channels[chan].ic_flags; 2182 if (ic->ic_curmode != IEEE80211_MODE_11N) 2183 chan_flags &= ~IEEE80211_CHAN_HT; 2184 tap->wr_chan_flags = htole16(chan_flags); 2185 tap->wr_dbm_antsignal = (int8_t)rssi; 2186 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2187 tap->wr_tsft = stat->tstamp; 2188 if (stat->rflags & IWN_RFLAG_MCS) { 2189 tap->wr_rate = (0x80 | stat->rate); /* HT MCS index */ 2190 } else { 2191 switch (stat->rate) { 2192 /* CCK rates. */ 2193 case 10: tap->wr_rate = 2; break; 2194 case 20: tap->wr_rate = 4; break; 2195 case 55: tap->wr_rate = 11; break; 2196 case 110: tap->wr_rate = 22; break; 2197 /* OFDM rates. */ 2198 case 0xd: tap->wr_rate = 12; break; 2199 case 0xf: tap->wr_rate = 18; break; 2200 case 0x5: tap->wr_rate = 24; break; 2201 case 0x7: tap->wr_rate = 36; break; 2202 case 0x9: tap->wr_rate = 48; break; 2203 case 0xb: tap->wr_rate = 72; break; 2204 case 0x1: tap->wr_rate = 96; break; 2205 case 0x3: tap->wr_rate = 108; break; 2206 /* Unknown rate: should not happen. */ 2207 default: tap->wr_rate = 0; 2208 } 2209 } 2210 2211 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_rxtap_len, 2212 m, BPF_DIRECTION_IN); 2213 } 2214 #endif 2215 2216 /* Send the frame to the 802.11 layer. */ 2217 rxi.rxi_rssi = rssi; 2218 rxi.rxi_chan = chan; 2219 ieee80211_inputm(ifp, m, ni, &rxi, ml); 2220 2221 /* Node is no longer needed. */ 2222 ieee80211_release_node(ic, ni); 2223 } 2224 2225 void 2226 iwn_ra_choose(struct iwn_softc *sc, struct ieee80211_node *ni) 2227 { 2228 struct ieee80211com *ic = &sc->sc_ic; 2229 struct iwn_node *wn = (void *)ni; 2230 int old_txmcs = ni->ni_txmcs; 2231 2232 ieee80211_ra_choose(&wn->rn, ic, ni); 2233 2234 /* Update firmware's LQ retry table if RA has chosen a new MCS. */ 2235 if (ni->ni_txmcs != old_txmcs) 2236 iwn_set_link_quality(sc, ni); 2237 } 2238 2239 void 2240 iwn_ampdu_rate_control(struct iwn_softc *sc, struct ieee80211_node *ni, 2241 struct iwn_tx_ring *txq, uint16_t seq, uint16_t ssn) 2242 { 2243 struct ieee80211com *ic = &sc->sc_ic; 2244 struct iwn_node *wn = (void *)ni; 2245 int idx, end_idx; 2246 2247 /* 2248 * Update Tx rate statistics for A-MPDUs before firmware's BA window. 2249 */ 2250 idx = IWN_AGG_SSN_TO_TXQ_IDX(seq); 2251 end_idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 2252 while (idx != end_idx) { 2253 struct iwn_tx_data *txdata = &txq->data[idx]; 2254 if (txdata->m != NULL && txdata->ampdu_nframes > 1) { 2255 /* 2256 * We can assume that this subframe has been ACKed 2257 * because ACK failures come as single frames and 2258 * before failing an A-MPDU subframe the firmware 2259 * sends it as a single frame at least once. 2260 */ 2261 ieee80211_ra_add_stats_ht(&wn->rn, ic, ni, 2262 txdata->ampdu_txmcs, 1, 0); 2263 2264 /* Report this frame only once. */ 2265 txdata->ampdu_nframes = 0; 2266 } 2267 2268 idx = (idx + 1) % IWN_TX_RING_COUNT; 2269 } 2270 2271 iwn_ra_choose(sc, ni); 2272 } 2273 2274 void 2275 iwn_ht_single_rate_control(struct iwn_softc *sc, struct ieee80211_node *ni, 2276 uint8_t rate, uint8_t rflags, uint8_t ackfailcnt, int txfail) 2277 { 2278 struct ieee80211com *ic = &sc->sc_ic; 2279 struct iwn_node *wn = (void *)ni; 2280 int mcs = rate; 2281 const struct ieee80211_ht_rateset *rs = 2282 ieee80211_ra_get_ht_rateset(rate, 2283 ieee80211_node_supports_ht_chan40(ni), 2284 ieee80211_ra_use_ht_sgi(ni)); 2285 unsigned int retries = 0, i; 2286 2287 /* 2288 * Ignore Tx reports which don't match our last LQ command. 2289 */ 2290 if (rate != ni->ni_txmcs) { 2291 if (++wn->lq_rate_mismatch > 15) { 2292 /* Try to sync firmware with driver. */ 2293 iwn_set_link_quality(sc, ni); 2294 wn->lq_rate_mismatch = 0; 2295 } 2296 return; 2297 } 2298 2299 wn->lq_rate_mismatch = 0; 2300 2301 /* 2302 * Firmware has attempted rates in this rate set in sequence. 2303 * Retries at a basic rate are counted against the minimum MCS. 2304 */ 2305 for (i = 0; i < ackfailcnt; i++) { 2306 if (mcs > rs->min_mcs) { 2307 ieee80211_ra_add_stats_ht(&wn->rn, ic, ni, mcs, 1, 1); 2308 mcs--; 2309 } else 2310 retries++; 2311 } 2312 2313 if (txfail && ackfailcnt == 0) 2314 ieee80211_ra_add_stats_ht(&wn->rn, ic, ni, mcs, 1, 1); 2315 else 2316 ieee80211_ra_add_stats_ht(&wn->rn, ic, ni, mcs, retries + 1, retries); 2317 2318 iwn_ra_choose(sc, ni); 2319 } 2320 2321 /* 2322 * Process an incoming Compressed BlockAck. 2323 * Note that these block ack notifications are generated by firmware and do 2324 * not necessarily correspond to contents of block ack frames seen on the air. 2325 */ 2326 void 2327 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2328 struct iwn_rx_data *data) 2329 { 2330 struct iwn_compressed_ba *cba = (struct iwn_compressed_ba *)(desc + 1); 2331 struct ieee80211com *ic = &sc->sc_ic; 2332 struct ieee80211_node *ni; 2333 struct ieee80211_tx_ba *ba; 2334 struct iwn_tx_ring *txq; 2335 uint16_t seq, ssn; 2336 int qid; 2337 2338 if (ic->ic_state != IEEE80211_S_RUN) 2339 return; 2340 2341 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*cba), 2342 BUS_DMASYNC_POSTREAD); 2343 2344 if (!IEEE80211_ADDR_EQ(ic->ic_bss->ni_macaddr, cba->macaddr)) 2345 return; 2346 2347 ni = ic->ic_bss; 2348 2349 qid = le16toh(cba->qid); 2350 if (qid < sc->first_agg_txq || qid >= sc->ntxqs) 2351 return; 2352 2353 txq = &sc->txq[qid]; 2354 2355 /* Protect against a firmware bug where the queue/TID are off. */ 2356 if (qid != sc->first_agg_txq + cba->tid) 2357 return; 2358 2359 ba = &ni->ni_tx_ba[cba->tid]; 2360 if (ba->ba_state != IEEE80211_BA_AGREED) 2361 return; 2362 2363 /* 2364 * The first bit in cba->bitmap corresponds to the sequence number 2365 * stored in the sequence control field cba->seq. 2366 * Multiple BA notifications in a row may be using this number, with 2367 * additional bits being set in cba->bitmap. It is unclear how the 2368 * firmware decides to shift this window forward. 2369 * We rely on ba->ba_winstart instead. 2370 */ 2371 seq = le16toh(cba->seq) >> IEEE80211_SEQ_SEQ_SHIFT; 2372 2373 /* 2374 * The firmware's new BA window starting sequence number 2375 * corresponds to the first hole in cba->bitmap, implying 2376 * that all frames between 'seq' and 'ssn' (non-inclusive) 2377 * have been acked. 2378 */ 2379 ssn = le16toh(cba->ssn); 2380 2381 if (SEQ_LT(ssn, ba->ba_winstart)) 2382 return; 2383 2384 /* Skip rate control if our Tx rate is fixed. */ 2385 if (ic->ic_fixed_mcs == -1) 2386 iwn_ampdu_rate_control(sc, ni, txq, ba->ba_winstart, ssn); 2387 2388 /* 2389 * SSN corresponds to the first (perhaps not yet transmitted) frame 2390 * in firmware's BA window. Firmware is not going to retransmit any 2391 * frames before its BA window so mark them all as done. 2392 */ 2393 ieee80211_output_ba_move_window(ic, ni, cba->tid, ssn); 2394 iwn_ampdu_txq_advance(sc, txq, qid, 2395 IWN_AGG_SSN_TO_TXQ_IDX(ssn)); 2396 iwn_clear_oactive(sc, txq); 2397 } 2398 2399 /* 2400 * Process a CALIBRATION_RESULT notification sent by the initialization 2401 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2402 */ 2403 void 2404 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2405 struct iwn_rx_data *data) 2406 { 2407 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2408 int len, idx = -1; 2409 2410 /* Runtime firmware should not send such a notification. */ 2411 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2412 return; 2413 2414 len = (letoh32(desc->len) & IWN_RX_DESC_LEN_MASK) - 4; 2415 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2416 BUS_DMASYNC_POSTREAD); 2417 2418 switch (calib->code) { 2419 case IWN5000_PHY_CALIB_DC: 2420 if (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2421 sc->hw_type == IWN_HW_REV_TYPE_2030 || 2422 sc->hw_type == IWN_HW_REV_TYPE_2000 || 2423 sc->hw_type == IWN_HW_REV_TYPE_135 || 2424 sc->hw_type == IWN_HW_REV_TYPE_105) 2425 idx = 0; 2426 break; 2427 case IWN5000_PHY_CALIB_LO: 2428 idx = 1; 2429 break; 2430 case IWN5000_PHY_CALIB_TX_IQ: 2431 idx = 2; 2432 break; 2433 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2434 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2435 sc->hw_type != IWN_HW_REV_TYPE_5150) 2436 idx = 3; 2437 break; 2438 case IWN5000_PHY_CALIB_BASE_BAND: 2439 idx = 4; 2440 break; 2441 } 2442 if (idx == -1) /* Ignore other results. */ 2443 return; 2444 2445 /* Save calibration result. */ 2446 if (sc->calibcmd[idx].buf != NULL) 2447 free(sc->calibcmd[idx].buf, M_DEVBUF, 0); 2448 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2449 if (sc->calibcmd[idx].buf == NULL) { 2450 DPRINTF(("not enough memory for calibration result %d\n", 2451 calib->code)); 2452 return; 2453 } 2454 DPRINTF(("saving calibration result code=%d len=%d\n", 2455 calib->code, len)); 2456 sc->calibcmd[idx].len = len; 2457 memcpy(sc->calibcmd[idx].buf, calib, len); 2458 } 2459 2460 /* 2461 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2462 * The latter is sent by the firmware after each received beacon. 2463 */ 2464 void 2465 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2466 struct iwn_rx_data *data) 2467 { 2468 struct iwn_ops *ops = &sc->ops; 2469 struct ieee80211com *ic = &sc->sc_ic; 2470 struct iwn_calib_state *calib = &sc->calib; 2471 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2472 int temp; 2473 2474 /* Ignore statistics received during a scan. */ 2475 if (ic->ic_state != IEEE80211_S_RUN) 2476 return; 2477 2478 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2479 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2480 2481 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2482 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2483 2484 sc->rx_stats_flags = htole32(stats->flags); 2485 2486 /* Test if temperature has changed. */ 2487 if (stats->general.temp != sc->rawtemp) { 2488 /* Convert "raw" temperature to degC. */ 2489 sc->rawtemp = stats->general.temp; 2490 temp = ops->get_temperature(sc); 2491 DPRINTFN(2, ("temperature=%dC\n", temp)); 2492 2493 /* Update TX power if need be (4965AGN only). */ 2494 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2495 iwn4965_power_calibration(sc, temp); 2496 } 2497 2498 if (desc->type != IWN_BEACON_STATISTICS) 2499 return; /* Reply to a statistics request. */ 2500 2501 sc->noise = iwn_get_noise(&stats->rx.general); 2502 2503 /* Test that RSSI and noise are present in stats report. */ 2504 if (sc->noise == -127) 2505 return; 2506 2507 if (letoh32(stats->rx.general.flags) != 1) { 2508 DPRINTF(("received statistics without RSSI\n")); 2509 return; 2510 } 2511 2512 /* 2513 * XXX Differential gain calibration makes the 6005 firmware 2514 * crap out, so skip it for now. This effectively disables 2515 * sensitivity tuning as well. 2516 */ 2517 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 2518 return; 2519 2520 if (calib->state == IWN_CALIB_STATE_ASSOC) 2521 iwn_collect_noise(sc, &stats->rx.general); 2522 else if (calib->state == IWN_CALIB_STATE_RUN) 2523 iwn_tune_sensitivity(sc, &stats->rx); 2524 } 2525 2526 void 2527 iwn_ampdu_txq_advance(struct iwn_softc *sc, struct iwn_tx_ring *txq, int qid, 2528 int idx) 2529 { 2530 struct iwn_ops *ops = &sc->ops; 2531 2532 DPRINTFN(3, ("%s: txq->cur=%d txq->read=%d txq->queued=%d qid=%d " 2533 "idx=%d\n", __func__, txq->cur, txq->read, txq->queued, qid, idx)); 2534 2535 while (txq->read != idx) { 2536 struct iwn_tx_data *txdata = &txq->data[txq->read]; 2537 if (txdata->m != NULL) { 2538 ops->reset_sched(sc, qid, txq->read); 2539 iwn_tx_done_free_txdata(sc, txdata); 2540 txq->queued--; 2541 } 2542 txq->read = (txq->read + 1) % IWN_TX_RING_COUNT; 2543 } 2544 } 2545 2546 /* 2547 * Handle A-MPDU Tx queue status report. 2548 * Tx failures come as single frames (perhaps out of order), and before failing 2549 * an A-MPDU subframe the firmware transmits it as a single frame at least once. 2550 * Frames successfully transmitted in an A-MPDU are completed when a compressed 2551 * block ack notification is received. 2552 */ 2553 void 2554 iwn_ampdu_tx_done(struct iwn_softc *sc, struct iwn_tx_ring *txq, 2555 struct iwn_rx_desc *desc, uint16_t status, uint8_t ackfailcnt, 2556 uint8_t rate, uint8_t rflags, int nframes, uint32_t ssn, 2557 struct iwn_txagg_status *agg_status) 2558 { 2559 struct ieee80211com *ic = &sc->sc_ic; 2560 int tid = desc->qid - sc->first_agg_txq; 2561 struct iwn_tx_data *txdata = &txq->data[desc->idx]; 2562 struct ieee80211_node *ni = txdata->ni; 2563 int txfail = (status != IWN_TX_STATUS_SUCCESS && 2564 status != IWN_TX_STATUS_DIRECT_DONE); 2565 struct ieee80211_tx_ba *ba; 2566 uint16_t seq; 2567 2568 sc->sc_tx_timer = 0; 2569 2570 if (ic->ic_state != IEEE80211_S_RUN) 2571 return; 2572 2573 if (nframes > 1) { 2574 int i; 2575 2576 /* 2577 * Collect information about this A-MPDU. 2578 */ 2579 for (i = 0; i < nframes; i++) { 2580 uint8_t qid = agg_status[i].qid; 2581 uint8_t idx = agg_status[i].idx; 2582 uint16_t txstatus = (le16toh(agg_status[i].status) & 2583 IWN_AGG_TX_STATUS_MASK); 2584 2585 if (txstatus != IWN_AGG_TX_STATE_TRANSMITTED) 2586 continue; 2587 2588 if (qid != desc->qid) 2589 continue; 2590 2591 txdata = &txq->data[idx]; 2592 if (txdata->ni == NULL) 2593 continue; 2594 2595 /* The Tx rate was the same for all subframes. */ 2596 txdata->ampdu_txmcs = rate; 2597 txdata->ampdu_nframes = nframes; 2598 } 2599 return; 2600 } 2601 2602 if (ni == NULL) 2603 return; 2604 2605 ba = &ni->ni_tx_ba[tid]; 2606 if (ba->ba_state != IEEE80211_BA_AGREED) 2607 return; 2608 if (SEQ_LT(ssn, ba->ba_winstart)) 2609 return; 2610 2611 /* This was a final single-frame Tx attempt for frame SSN-1. */ 2612 seq = (ssn - 1) & 0xfff; 2613 2614 /* 2615 * Skip rate control if our Tx rate is fixed. 2616 */ 2617 if (ic->ic_fixed_mcs == -1) { 2618 if (txdata->ampdu_nframes > 1) { 2619 struct iwn_node *wn = (void *)ni; 2620 /* 2621 * This frame was once part of an A-MPDU. 2622 * Report one failed A-MPDU Tx attempt. 2623 * The firmware might have made several such 2624 * attempts but we don't keep track of this. 2625 */ 2626 ieee80211_ra_add_stats_ht(&wn->rn, ic, ni, 2627 txdata->ampdu_txmcs, 1, 1); 2628 } 2629 2630 /* Report the final single-frame Tx attempt. */ 2631 if (rflags & IWN_RFLAG_MCS) 2632 iwn_ht_single_rate_control(sc, ni, rate, rflags, 2633 ackfailcnt, txfail); 2634 } 2635 2636 if (txfail) 2637 ieee80211_tx_compressed_bar(ic, ni, tid, ssn); 2638 2639 /* 2640 * SSN corresponds to the first (perhaps not yet transmitted) frame 2641 * in firmware's BA window. Firmware is not going to retransmit any 2642 * frames before its BA window so mark them all as done. 2643 */ 2644 ieee80211_output_ba_move_window(ic, ni, tid, ssn); 2645 iwn_ampdu_txq_advance(sc, txq, desc->qid, IWN_AGG_SSN_TO_TXQ_IDX(ssn)); 2646 iwn_clear_oactive(sc, txq); 2647 } 2648 2649 /* 2650 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2651 * and 5000 adapters have different incompatible TX status formats. 2652 */ 2653 void 2654 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2655 struct iwn_rx_data *data) 2656 { 2657 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2658 struct iwn_tx_ring *ring; 2659 size_t len = (letoh32(desc->len) & IWN_RX_DESC_LEN_MASK); 2660 uint16_t status = letoh32(stat->stat.status) & 0xff; 2661 uint32_t ssn; 2662 2663 if (desc->qid > IWN4965_NTXQUEUES) 2664 return; 2665 2666 ring = &sc->txq[desc->qid]; 2667 2668 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2669 len, BUS_DMASYNC_POSTREAD); 2670 2671 /* Sanity checks. */ 2672 if (sizeof(*stat) > len) 2673 return; 2674 if (stat->nframes < 1 || stat->nframes > IWN_AMPDU_MAX) 2675 return; 2676 if (desc->qid < sc->first_agg_txq && stat->nframes > 1) 2677 return; 2678 if (desc->qid >= sc->first_agg_txq && sizeof(*stat) + sizeof(ssn) + 2679 stat->nframes * sizeof(stat->stat) > len) 2680 return; 2681 2682 if (desc->qid < sc->first_agg_txq) { 2683 /* XXX 4965 does not report byte count */ 2684 struct iwn_tx_data *txdata = &ring->data[desc->idx]; 2685 uint16_t framelen = txdata->totlen + IEEE80211_CRC_LEN; 2686 int txfail = (status != IWN_TX_STATUS_SUCCESS && 2687 status != IWN_TX_STATUS_DIRECT_DONE); 2688 2689 iwn_tx_done(sc, desc, stat->ackfailcnt, stat->rate, 2690 stat->rflags, txfail, desc->qid, framelen); 2691 } else { 2692 memcpy(&ssn, &stat->stat.status + stat->nframes, sizeof(ssn)); 2693 ssn = le32toh(ssn) & 0xfff; 2694 iwn_ampdu_tx_done(sc, ring, desc, status, stat->ackfailcnt, 2695 stat->rate, stat->rflags, stat->nframes, ssn, 2696 stat->stat.agg_status); 2697 } 2698 } 2699 2700 void 2701 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2702 struct iwn_rx_data *data) 2703 { 2704 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2705 struct iwn_tx_ring *ring; 2706 size_t len = (letoh32(desc->len) & IWN_RX_DESC_LEN_MASK); 2707 uint16_t status = letoh32(stat->stat.status) & 0xff; 2708 uint32_t ssn; 2709 2710 if (desc->qid > IWN5000_NTXQUEUES) 2711 return; 2712 2713 ring = &sc->txq[desc->qid]; 2714 2715 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2716 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2717 2718 /* Sanity checks. */ 2719 if (sizeof(*stat) > len) 2720 return; 2721 if (stat->nframes < 1 || stat->nframes > IWN_AMPDU_MAX) 2722 return; 2723 if (desc->qid < sc->first_agg_txq && stat->nframes > 1) 2724 return; 2725 if (desc->qid >= sc->first_agg_txq && sizeof(*stat) + sizeof(ssn) + 2726 stat->nframes * sizeof(stat->stat) > len) 2727 return; 2728 2729 /* If this was not an aggregated frame, complete it now. */ 2730 if (desc->qid < sc->first_agg_txq) { 2731 int txfail = (status != IWN_TX_STATUS_SUCCESS && 2732 status != IWN_TX_STATUS_DIRECT_DONE); 2733 2734 /* Reset TX scheduler slot. */ 2735 iwn5000_reset_sched(sc, desc->qid, desc->idx); 2736 2737 iwn_tx_done(sc, desc, stat->ackfailcnt, stat->rate, 2738 stat->rflags, txfail, desc->qid, letoh16(stat->len)); 2739 } else { 2740 memcpy(&ssn, &stat->stat.status + stat->nframes, sizeof(ssn)); 2741 ssn = le32toh(ssn) & 0xfff; 2742 iwn_ampdu_tx_done(sc, ring, desc, status, stat->ackfailcnt, 2743 stat->rate, stat->rflags, stat->nframes, ssn, 2744 stat->stat.agg_status); 2745 } 2746 } 2747 2748 void 2749 iwn_tx_done_free_txdata(struct iwn_softc *sc, struct iwn_tx_data *data) 2750 { 2751 struct ieee80211com *ic = &sc->sc_ic; 2752 2753 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2754 BUS_DMASYNC_POSTWRITE); 2755 bus_dmamap_unload(sc->sc_dmat, data->map); 2756 m_freem(data->m); 2757 data->m = NULL; 2758 ieee80211_release_node(ic, data->ni); 2759 data->ni = NULL; 2760 data->totlen = 0; 2761 data->ampdu_nframes = 0; 2762 data->ampdu_txmcs = 0; 2763 } 2764 2765 void 2766 iwn_clear_oactive(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2767 { 2768 struct ieee80211com *ic = &sc->sc_ic; 2769 struct ifnet *ifp = &ic->ic_if; 2770 2771 if (ring->queued < IWN_TX_RING_LOMARK) { 2772 sc->qfullmsk &= ~(1 << ring->qid); 2773 if (sc->qfullmsk == 0 && ifq_is_oactive(&ifp->if_snd)) { 2774 ifq_clr_oactive(&ifp->if_snd); 2775 (*ifp->if_start)(ifp); 2776 } 2777 } 2778 } 2779 2780 /* 2781 * Adapter-independent backend for TX_DONE firmware notifications. 2782 * This handles Tx status for non-aggregation queues. 2783 */ 2784 void 2785 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2786 uint8_t ackfailcnt, uint8_t rate, uint8_t rflags, int txfail, 2787 int qid, uint16_t len) 2788 { 2789 struct ieee80211com *ic = &sc->sc_ic; 2790 struct ifnet *ifp = &ic->ic_if; 2791 struct iwn_tx_ring *ring = &sc->txq[qid]; 2792 struct iwn_tx_data *data = &ring->data[desc->idx]; 2793 struct iwn_node *wn = (void *)data->ni; 2794 2795 if (data->ni == NULL) 2796 return; 2797 2798 if (data->ni->ni_flags & IEEE80211_NODE_HT) { 2799 if (ic->ic_state == IEEE80211_S_RUN && 2800 ic->ic_fixed_mcs == -1 && (rflags & IWN_RFLAG_MCS)) { 2801 iwn_ht_single_rate_control(sc, data->ni, rate, rflags, 2802 ackfailcnt, txfail); 2803 } 2804 } else { 2805 if (rate != data->ni->ni_txrate) { 2806 if (++wn->lq_rate_mismatch > 15) { 2807 /* Try to sync firmware with driver. */ 2808 iwn_set_link_quality(sc, data->ni); 2809 wn->lq_rate_mismatch = 0; 2810 } 2811 } else { 2812 wn->lq_rate_mismatch = 0; 2813 2814 wn->amn.amn_txcnt++; 2815 if (ackfailcnt > 0) 2816 wn->amn.amn_retrycnt++; 2817 if (txfail) 2818 wn->amn.amn_retrycnt++; 2819 } 2820 } 2821 if (txfail) 2822 ifp->if_oerrors++; 2823 2824 iwn_tx_done_free_txdata(sc, data); 2825 2826 sc->sc_tx_timer = 0; 2827 ring->queued--; 2828 iwn_clear_oactive(sc, ring); 2829 } 2830 2831 /* 2832 * Process a "command done" firmware notification. This is where we wakeup 2833 * processes waiting for a synchronous command completion. 2834 */ 2835 void 2836 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2837 { 2838 struct iwn_tx_ring *ring = &sc->txq[4]; 2839 struct iwn_tx_data *data; 2840 2841 if ((desc->qid & 0xf) != 4) 2842 return; /* Not a command ack. */ 2843 2844 data = &ring->data[desc->idx]; 2845 2846 /* If the command was mapped in an mbuf, free it. */ 2847 if (data->m != NULL) { 2848 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2849 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2850 bus_dmamap_unload(sc->sc_dmat, data->map); 2851 m_freem(data->m); 2852 data->m = NULL; 2853 } 2854 wakeup(&ring->desc[desc->idx]); 2855 } 2856 2857 /* 2858 * Process an INT_FH_RX or INT_SW_RX interrupt. 2859 */ 2860 void 2861 iwn_notif_intr(struct iwn_softc *sc) 2862 { 2863 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2864 struct iwn_ops *ops = &sc->ops; 2865 struct ieee80211com *ic = &sc->sc_ic; 2866 struct ifnet *ifp = &ic->ic_if; 2867 uint16_t hw; 2868 2869 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2870 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2871 2872 hw = letoh16(sc->rxq.stat->closed_count) & 0xfff; 2873 while (sc->rxq.cur != hw) { 2874 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2875 struct iwn_rx_desc *desc; 2876 2877 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2878 BUS_DMASYNC_POSTREAD); 2879 desc = mtod(data->m, struct iwn_rx_desc *); 2880 2881 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2882 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2883 2884 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2885 iwn_cmd_done(sc, desc); 2886 2887 switch (desc->type) { 2888 case IWN_RX_PHY: 2889 iwn_rx_phy(sc, desc, data); 2890 break; 2891 2892 case IWN_RX_DONE: /* 4965AGN only. */ 2893 case IWN_MPDU_RX_DONE: 2894 /* An 802.11 frame has been received. */ 2895 iwn_rx_done(sc, desc, data, &ml); 2896 break; 2897 case IWN_RX_COMPRESSED_BA: 2898 /* A Compressed BlockAck has been received. */ 2899 iwn_rx_compressed_ba(sc, desc, data); 2900 break; 2901 case IWN_TX_DONE: 2902 /* An 802.11 frame has been transmitted. */ 2903 ops->tx_done(sc, desc, data); 2904 break; 2905 2906 case IWN_RX_STATISTICS: 2907 case IWN_BEACON_STATISTICS: 2908 iwn_rx_statistics(sc, desc, data); 2909 break; 2910 2911 case IWN_BEACON_MISSED: 2912 { 2913 struct iwn_beacon_missed *miss = 2914 (struct iwn_beacon_missed *)(desc + 1); 2915 uint32_t missed; 2916 2917 if ((ic->ic_opmode != IEEE80211_M_STA) || 2918 (ic->ic_state != IEEE80211_S_RUN)) 2919 break; 2920 2921 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2922 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2923 missed = letoh32(miss->consecutive); 2924 2925 /* 2926 * If more than 5 consecutive beacons are missed, 2927 * reinitialize the sensitivity state machine. 2928 */ 2929 if (missed > 5) 2930 (void)iwn_init_sensitivity(sc); 2931 2932 /* 2933 * Rather than go directly to scan state, try to send a 2934 * directed probe request first. If that fails then the 2935 * state machine will drop us into scanning after timing 2936 * out waiting for a probe response. 2937 */ 2938 if (missed > ic->ic_bmissthres && !ic->ic_mgt_timer) { 2939 if (ic->ic_if.if_flags & IFF_DEBUG) 2940 printf("%s: receiving no beacons from " 2941 "%s; checking if this AP is still " 2942 "responding to probe requests\n", 2943 sc->sc_dev.dv_xname, ether_sprintf( 2944 ic->ic_bss->ni_macaddr)); 2945 IEEE80211_SEND_MGMT(ic, ic->ic_bss, 2946 IEEE80211_FC0_SUBTYPE_PROBE_REQ, 0); 2947 } 2948 break; 2949 } 2950 case IWN_UC_READY: 2951 { 2952 struct iwn_ucode_info *uc = 2953 (struct iwn_ucode_info *)(desc + 1); 2954 2955 /* The microcontroller is ready. */ 2956 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2957 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2958 DPRINTF(("microcode alive notification version=%d.%d " 2959 "subtype=%x alive=%x\n", uc->major, uc->minor, 2960 uc->subtype, letoh32(uc->valid))); 2961 2962 if (letoh32(uc->valid) != 1) { 2963 printf("%s: microcontroller initialization " 2964 "failed\n", sc->sc_dev.dv_xname); 2965 break; 2966 } 2967 if (uc->subtype == IWN_UCODE_INIT) { 2968 /* Save microcontroller report. */ 2969 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2970 } 2971 /* Save the address of the error log in SRAM. */ 2972 sc->errptr = letoh32(uc->errptr); 2973 break; 2974 } 2975 case IWN_STATE_CHANGED: 2976 { 2977 uint32_t *status = (uint32_t *)(desc + 1); 2978 2979 /* Enabled/disabled notification. */ 2980 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2981 sizeof (*status), BUS_DMASYNC_POSTREAD); 2982 DPRINTF(("state changed to %x\n", letoh32(*status))); 2983 2984 if (letoh32(*status) & 1) { 2985 /* Radio transmitter is off, power down. */ 2986 iwn_stop(ifp); 2987 return; /* No further processing. */ 2988 } 2989 break; 2990 } 2991 case IWN_START_SCAN: 2992 { 2993 struct iwn_start_scan *scan = 2994 (struct iwn_start_scan *)(desc + 1); 2995 2996 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2997 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2998 DPRINTFN(2, ("scan start: chan %d status %x\n", 2999 scan->chan, letoh32(scan->status))); 3000 3001 if (sc->sc_flags & IWN_FLAG_BGSCAN) 3002 break; 3003 3004 /* Fix current channel. */ 3005 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 3006 break; 3007 } 3008 case IWN_STOP_SCAN: 3009 { 3010 struct iwn_stop_scan *scan = 3011 (struct iwn_stop_scan *)(desc + 1); 3012 3013 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 3014 sizeof (*scan), BUS_DMASYNC_POSTREAD); 3015 DPRINTFN(2, ("scan stop: nchan=%d status=%d chan=%d\n", 3016 scan->nchan, scan->status, scan->chan)); 3017 3018 if (scan->status == 1 && scan->chan <= 14 && 3019 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 3020 int error; 3021 /* 3022 * We just finished scanning 2GHz channels, 3023 * start scanning 5GHz ones. 3024 */ 3025 error = iwn_scan(sc, IEEE80211_CHAN_5GHZ, 3026 (sc->sc_flags & IWN_FLAG_BGSCAN) ? 1 : 0); 3027 if (error == 0) 3028 break; 3029 } 3030 sc->sc_flags &= ~IWN_FLAG_SCANNING; 3031 sc->sc_flags &= ~IWN_FLAG_BGSCAN; 3032 ieee80211_end_scan(ifp); 3033 break; 3034 } 3035 case IWN5000_CALIBRATION_RESULT: 3036 iwn5000_rx_calib_results(sc, desc, data); 3037 break; 3038 3039 case IWN5000_CALIBRATION_DONE: 3040 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 3041 wakeup(sc); 3042 break; 3043 } 3044 3045 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 3046 } 3047 if_input(&sc->sc_ic.ic_if, &ml); 3048 3049 /* Tell the firmware what we have processed. */ 3050 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 3051 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 3052 } 3053 3054 /* 3055 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 3056 * from power-down sleep mode. 3057 */ 3058 void 3059 iwn_wakeup_intr(struct iwn_softc *sc) 3060 { 3061 int qid; 3062 3063 DPRINTF(("ucode wakeup from power-down sleep\n")); 3064 3065 /* Wakeup RX and TX rings. */ 3066 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 3067 for (qid = 0; qid < sc->ntxqs; qid++) { 3068 struct iwn_tx_ring *ring = &sc->txq[qid]; 3069 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 3070 } 3071 } 3072 3073 /* 3074 * Dump the error log of the firmware when a firmware panic occurs. Although 3075 * we can't debug the firmware because it is neither open source nor free, it 3076 * can help us to identify certain classes of problems. 3077 */ 3078 void 3079 iwn_fatal_intr(struct iwn_softc *sc) 3080 { 3081 struct iwn_fw_dump dump; 3082 int i; 3083 3084 /* Check that the error log address is valid. */ 3085 if (sc->errptr < IWN_FW_DATA_BASE || 3086 sc->errptr + sizeof (dump) > 3087 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 3088 printf("%s: bad firmware error log address 0x%08x\n", 3089 sc->sc_dev.dv_xname, sc->errptr); 3090 return; 3091 } 3092 if (iwn_nic_lock(sc) != 0) { 3093 printf("%s: could not read firmware error log\n", 3094 sc->sc_dev.dv_xname); 3095 return; 3096 } 3097 /* Read firmware error log from SRAM. */ 3098 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 3099 sizeof (dump) / sizeof (uint32_t)); 3100 iwn_nic_unlock(sc); 3101 3102 if (dump.valid == 0) { 3103 printf("%s: firmware error log is empty\n", 3104 sc->sc_dev.dv_xname); 3105 return; 3106 } 3107 printf("firmware error log:\n"); 3108 printf(" error type = \"%s\" (0x%08X)\n", 3109 (dump.id < nitems(iwn_fw_errmsg)) ? 3110 iwn_fw_errmsg[dump.id] : "UNKNOWN", 3111 dump.id); 3112 printf(" program counter = 0x%08X\n", dump.pc); 3113 printf(" source line = 0x%08X\n", dump.src_line); 3114 printf(" error data = 0x%08X%08X\n", 3115 dump.error_data[0], dump.error_data[1]); 3116 printf(" branch link = 0x%08X%08X\n", 3117 dump.branch_link[0], dump.branch_link[1]); 3118 printf(" interrupt link = 0x%08X%08X\n", 3119 dump.interrupt_link[0], dump.interrupt_link[1]); 3120 printf(" time = %u\n", dump.time[0]); 3121 3122 /* Dump driver status (TX and RX rings) while we're here. */ 3123 printf("driver status:\n"); 3124 for (i = 0; i < sc->ntxqs; i++) { 3125 struct iwn_tx_ring *ring = &sc->txq[i]; 3126 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 3127 i, ring->qid, ring->cur, ring->queued); 3128 } 3129 printf(" rx ring: cur=%d\n", sc->rxq.cur); 3130 printf(" 802.11 state %d\n", sc->sc_ic.ic_state); 3131 } 3132 3133 int 3134 iwn_intr(void *arg) 3135 { 3136 struct iwn_softc *sc = arg; 3137 struct ifnet *ifp = &sc->sc_ic.ic_if; 3138 uint32_t r1, r2, tmp; 3139 3140 /* Disable interrupts. */ 3141 IWN_WRITE(sc, IWN_INT_MASK, 0); 3142 3143 /* Read interrupts from ICT (fast) or from registers (slow). */ 3144 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3145 tmp = 0; 3146 while (sc->ict[sc->ict_cur] != 0) { 3147 tmp |= sc->ict[sc->ict_cur]; 3148 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 3149 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 3150 } 3151 tmp = letoh32(tmp); 3152 if (tmp == 0xffffffff) /* Shouldn't happen. */ 3153 tmp = 0; 3154 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 3155 tmp |= 0x8000; 3156 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 3157 r2 = 0; /* Unused. */ 3158 } else { 3159 r1 = IWN_READ(sc, IWN_INT); 3160 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 3161 return 0; /* Hardware gone! */ 3162 r2 = IWN_READ(sc, IWN_FH_INT); 3163 } 3164 if (r1 == 0 && r2 == 0) { 3165 if (ifp->if_flags & IFF_UP) 3166 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 3167 return 0; /* Interrupt not for us. */ 3168 } 3169 3170 /* Acknowledge interrupts. */ 3171 IWN_WRITE(sc, IWN_INT, r1); 3172 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 3173 IWN_WRITE(sc, IWN_FH_INT, r2); 3174 3175 if (r1 & IWN_INT_RF_TOGGLED) { 3176 tmp = IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL; 3177 printf("%s: RF switch: radio %s\n", sc->sc_dev.dv_xname, 3178 tmp ? "enabled" : "disabled"); 3179 if (tmp) 3180 task_add(systq, &sc->init_task); 3181 } 3182 if (r1 & IWN_INT_CT_REACHED) { 3183 printf("%s: critical temperature reached!\n", 3184 sc->sc_dev.dv_xname); 3185 } 3186 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 3187 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 3188 3189 /* Force a complete recalibration on next init. */ 3190 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 3191 3192 /* Dump firmware error log and stop. */ 3193 if (ifp->if_flags & IFF_DEBUG) 3194 iwn_fatal_intr(sc); 3195 iwn_stop(ifp); 3196 task_add(systq, &sc->init_task); 3197 return 1; 3198 } 3199 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 3200 (r2 & IWN_FH_INT_RX)) { 3201 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3202 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 3203 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 3204 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 3205 IWN_INT_PERIODIC_DIS); 3206 iwn_notif_intr(sc); 3207 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 3208 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 3209 IWN_INT_PERIODIC_ENA); 3210 } 3211 } else 3212 iwn_notif_intr(sc); 3213 } 3214 3215 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 3216 if (sc->sc_flags & IWN_FLAG_USE_ICT) 3217 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 3218 wakeup(sc); /* FH DMA transfer completed. */ 3219 } 3220 3221 if (r1 & IWN_INT_ALIVE) 3222 wakeup(sc); /* Firmware is alive. */ 3223 3224 if (r1 & IWN_INT_WAKEUP) 3225 iwn_wakeup_intr(sc); 3226 3227 /* Re-enable interrupts. */ 3228 if (ifp->if_flags & IFF_UP) 3229 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 3230 3231 return 1; 3232 } 3233 3234 /* 3235 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 3236 * 5000 adapters use a slightly different format). 3237 */ 3238 void 3239 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3240 uint16_t len) 3241 { 3242 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 3243 3244 *w = htole16(len + 8); 3245 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3246 (caddr_t)w - sc->sched_dma.vaddr, sizeof (uint16_t), 3247 BUS_DMASYNC_PREWRITE); 3248 if (idx < IWN_SCHED_WINSZ) { 3249 *(w + IWN_TX_RING_COUNT) = *w; 3250 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3251 (caddr_t)(w + IWN_TX_RING_COUNT) - sc->sched_dma.vaddr, 3252 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 3253 } 3254 } 3255 3256 void 3257 iwn4965_reset_sched(struct iwn_softc *sc, int qid, int idx) 3258 { 3259 /* TBD */ 3260 } 3261 3262 void 3263 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3264 uint16_t len) 3265 { 3266 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3267 3268 *w = htole16(id << 12 | (len + 8)); 3269 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3270 (caddr_t)w - sc->sched_dma.vaddr, sizeof (uint16_t), 3271 BUS_DMASYNC_PREWRITE); 3272 if (idx < IWN_SCHED_WINSZ) { 3273 *(w + IWN_TX_RING_COUNT) = *w; 3274 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3275 (caddr_t)(w + IWN_TX_RING_COUNT) - sc->sched_dma.vaddr, 3276 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 3277 } 3278 } 3279 3280 void 3281 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 3282 { 3283 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3284 3285 *w = (*w & htole16(0xf000)) | htole16(1); 3286 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3287 (caddr_t)w - sc->sched_dma.vaddr, sizeof (uint16_t), 3288 BUS_DMASYNC_PREWRITE); 3289 if (idx < IWN_SCHED_WINSZ) { 3290 *(w + IWN_TX_RING_COUNT) = *w; 3291 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3292 (caddr_t)(w + IWN_TX_RING_COUNT) - sc->sched_dma.vaddr, 3293 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 3294 } 3295 } 3296 3297 int 3298 iwn_rval2ridx(int rval) 3299 { 3300 int ridx; 3301 3302 for (ridx = 0; ridx < nitems(iwn_rates); ridx++) { 3303 if (rval == iwn_rates[ridx].rate) 3304 break; 3305 } 3306 3307 return ridx; 3308 } 3309 3310 int 3311 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 3312 { 3313 struct iwn_ops *ops = &sc->ops; 3314 struct ieee80211com *ic = &sc->sc_ic; 3315 struct iwn_node *wn = (void *)ni; 3316 struct iwn_tx_ring *ring; 3317 struct iwn_tx_desc *desc; 3318 struct iwn_tx_data *data; 3319 struct iwn_tx_cmd *cmd; 3320 struct iwn_cmd_data *tx; 3321 const struct iwn_rate *rinfo; 3322 struct ieee80211_frame *wh; 3323 struct ieee80211_key *k = NULL; 3324 enum ieee80211_edca_ac ac; 3325 int qid; 3326 uint32_t flags; 3327 uint16_t qos; 3328 u_int hdrlen; 3329 bus_dma_segment_t *seg; 3330 uint8_t *ivp, tid, ridx, txant, type, subtype; 3331 int i, totlen, hasqos, error, pad; 3332 3333 wh = mtod(m, struct ieee80211_frame *); 3334 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3335 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3336 if (type == IEEE80211_FC0_TYPE_CTL) 3337 hdrlen = sizeof(struct ieee80211_frame_min); 3338 else 3339 hdrlen = ieee80211_get_hdrlen(wh); 3340 3341 if ((hasqos = ieee80211_has_qos(wh))) { 3342 /* Select EDCA Access Category and TX ring for this frame. */ 3343 struct ieee80211_tx_ba *ba; 3344 qos = ieee80211_get_qos(wh); 3345 tid = qos & IEEE80211_QOS_TID; 3346 ac = ieee80211_up_to_ac(ic, tid); 3347 qid = ac; 3348 3349 /* If possible, put this frame on an aggregation queue. */ 3350 if (sc->sc_tx_ba[tid].wn == wn) { 3351 ba = &ni->ni_tx_ba[tid]; 3352 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 3353 ba->ba_state == IEEE80211_BA_AGREED) { 3354 qid = sc->first_agg_txq + tid; 3355 if (sc->qfullmsk & (1 << qid)) { 3356 m_freem(m); 3357 return ENOBUFS; 3358 } 3359 } 3360 } 3361 } else { 3362 qos = 0; 3363 tid = IWN_NONQOS_TID; 3364 ac = EDCA_AC_BE; 3365 qid = ac; 3366 } 3367 3368 ring = &sc->txq[qid]; 3369 desc = &ring->desc[ring->cur]; 3370 data = &ring->data[ring->cur]; 3371 3372 /* Choose a TX rate index. */ 3373 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3374 type != IEEE80211_FC0_TYPE_DATA) 3375 ridx = iwn_rval2ridx(ieee80211_min_basic_rate(ic)); 3376 else if (ic->ic_fixed_mcs != -1) 3377 ridx = sc->fixed_ridx; 3378 else if (ic->ic_fixed_rate != -1) 3379 ridx = sc->fixed_ridx; 3380 else { 3381 if (ni->ni_flags & IEEE80211_NODE_HT) 3382 ridx = iwn_mcs2ridx[ni->ni_txmcs]; 3383 else 3384 ridx = wn->ridx[ni->ni_txrate]; 3385 } 3386 rinfo = &iwn_rates[ridx]; 3387 #if NBPFILTER > 0 3388 if (sc->sc_drvbpf != NULL) { 3389 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3390 uint16_t chan_flags; 3391 3392 tap->wt_flags = 0; 3393 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 3394 chan_flags = ni->ni_chan->ic_flags; 3395 if (ic->ic_curmode != IEEE80211_MODE_11N) 3396 chan_flags &= ~IEEE80211_CHAN_HT; 3397 tap->wt_chan_flags = htole16(chan_flags); 3398 if ((ni->ni_flags & IEEE80211_NODE_HT) && 3399 !IEEE80211_IS_MULTICAST(wh->i_addr1) && 3400 type == IEEE80211_FC0_TYPE_DATA) { 3401 tap->wt_rate = (0x80 | ni->ni_txmcs); 3402 } else 3403 tap->wt_rate = rinfo->rate; 3404 if ((ic->ic_flags & IEEE80211_F_WEPON) && 3405 (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)) 3406 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3407 3408 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_txtap_len, 3409 m, BPF_DIRECTION_OUT); 3410 } 3411 #endif 3412 3413 totlen = m->m_pkthdr.len; 3414 3415 /* Encrypt the frame if need be. */ 3416 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 3417 /* Retrieve key for TX. */ 3418 k = ieee80211_get_txkey(ic, wh, ni); 3419 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 3420 /* Do software encryption. */ 3421 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 3422 return ENOBUFS; 3423 /* 802.11 header may have moved. */ 3424 wh = mtod(m, struct ieee80211_frame *); 3425 totlen = m->m_pkthdr.len; 3426 3427 } else /* HW appends CCMP MIC. */ 3428 totlen += IEEE80211_CCMP_HDRLEN; 3429 } 3430 3431 data->totlen = totlen; 3432 3433 /* Prepare TX firmware command. */ 3434 cmd = &ring->cmd[ring->cur]; 3435 cmd->code = IWN_CMD_TX_DATA; 3436 cmd->flags = 0; 3437 cmd->qid = ring->qid; 3438 cmd->idx = ring->cur; 3439 3440 tx = (struct iwn_cmd_data *)cmd->data; 3441 /* NB: No need to clear tx, all fields are reinitialized here. */ 3442 tx->scratch = 0; /* clear "scratch" area */ 3443 3444 flags = 0; 3445 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3446 /* Unicast frame, check if an ACK is expected. */ 3447 if (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 3448 IEEE80211_QOS_ACK_POLICY_NOACK) 3449 flags |= IWN_TX_NEED_ACK; 3450 } 3451 if (type == IEEE80211_FC0_TYPE_CTL && 3452 subtype == IEEE80211_FC0_SUBTYPE_BAR) { 3453 struct ieee80211_frame_min *mwh; 3454 uint8_t *barfrm; 3455 uint16_t ctl; 3456 mwh = mtod(m, struct ieee80211_frame_min *); 3457 barfrm = (uint8_t *)&mwh[1]; 3458 ctl = LE_READ_2(barfrm); 3459 tid = (ctl & IEEE80211_BA_TID_INFO_MASK) >> 3460 IEEE80211_BA_TID_INFO_SHIFT; 3461 flags |= (IWN_TX_NEED_ACK | IWN_TX_IMM_BA); 3462 } 3463 3464 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 3465 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 3466 3467 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 3468 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3469 /* NB: Group frames are sent using CCK in 802.11b/g/n (2GHz). */ 3470 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 3471 flags |= IWN_TX_NEED_RTS; 3472 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3473 ridx >= IWN_RIDX_OFDM6) { 3474 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3475 flags |= IWN_TX_NEED_CTS; 3476 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3477 flags |= IWN_TX_NEED_RTS; 3478 } 3479 3480 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 3481 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3482 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3483 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 3484 flags |= IWN_TX_NEED_PROTECTION; 3485 } else 3486 flags |= IWN_TX_FULL_TXOP; 3487 } 3488 } 3489 3490 if (type == IEEE80211_FC0_TYPE_CTL && 3491 subtype == IEEE80211_FC0_SUBTYPE_BAR) 3492 tx->id = wn->id; 3493 else if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3494 type != IEEE80211_FC0_TYPE_DATA) 3495 tx->id = sc->broadcast_id; 3496 else 3497 tx->id = wn->id; 3498 3499 if (type == IEEE80211_FC0_TYPE_MGT) { 3500 #ifndef IEEE80211_STA_ONLY 3501 /* Tell HW to set timestamp in probe responses. */ 3502 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3503 flags |= IWN_TX_INSERT_TSTAMP; 3504 #endif 3505 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3506 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3507 tx->timeout = htole16(3); 3508 else 3509 tx->timeout = htole16(2); 3510 } else 3511 tx->timeout = htole16(0); 3512 3513 if (hdrlen & 3) { 3514 /* First segment length must be a multiple of 4. */ 3515 flags |= IWN_TX_NEED_PADDING; 3516 pad = 4 - (hdrlen & 3); 3517 } else 3518 pad = 0; 3519 3520 tx->len = htole16(totlen); 3521 tx->tid = tid; 3522 tx->rts_ntries = 60; 3523 tx->data_ntries = 15; 3524 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3525 3526 if ((ni->ni_flags & IEEE80211_NODE_HT) && 3527 tx->id != sc->broadcast_id) 3528 tx->plcp = rinfo->ht_plcp; 3529 else 3530 tx->plcp = rinfo->plcp; 3531 3532 if ((ni->ni_flags & IEEE80211_NODE_HT) && 3533 tx->id != sc->broadcast_id) { 3534 tx->rflags = rinfo->ht_flags; 3535 if (iwn_rxon_ht40_enabled(sc)) 3536 tx->rflags |= IWN_RFLAG_HT40; 3537 if (ieee80211_ra_use_ht_sgi(ni)) 3538 tx->rflags |= IWN_RFLAG_SGI; 3539 } 3540 else 3541 tx->rflags = rinfo->flags; 3542 if (tx->id == sc->broadcast_id || ic->ic_fixed_mcs != -1 || 3543 ic->ic_fixed_rate != -1) { 3544 /* Group or management frame, or fixed Tx rate. */ 3545 tx->linkq = 0; 3546 /* XXX Alternate between antenna A and B? */ 3547 txant = IWN_LSB(sc->txchainmask); 3548 tx->rflags |= IWN_RFLAG_ANT(txant); 3549 } else { 3550 tx->linkq = 0; /* initial index into firmware LQ retry table */ 3551 flags |= IWN_TX_LINKQ; /* enable multi-rate retry */ 3552 } 3553 /* Set physical address of "scratch area". */ 3554 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3555 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3556 3557 /* Copy 802.11 header in TX command. */ 3558 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3559 3560 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 3561 /* Trim 802.11 header and prepend CCMP IV. */ 3562 m_adj(m, hdrlen - IEEE80211_CCMP_HDRLEN); 3563 ivp = mtod(m, uint8_t *); 3564 k->k_tsc++; 3565 ivp[0] = k->k_tsc; 3566 ivp[1] = k->k_tsc >> 8; 3567 ivp[2] = 0; 3568 ivp[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3569 ivp[4] = k->k_tsc >> 16; 3570 ivp[5] = k->k_tsc >> 24; 3571 ivp[6] = k->k_tsc >> 32; 3572 ivp[7] = k->k_tsc >> 40; 3573 3574 tx->security = IWN_CIPHER_CCMP; 3575 if (qid >= sc->first_agg_txq) 3576 flags |= IWN_TX_AMPDU_CCMP; 3577 memcpy(tx->key, k->k_key, k->k_len); 3578 3579 /* TX scheduler includes CCMP MIC len w/5000 Series. */ 3580 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 3581 totlen += IEEE80211_CCMP_MICLEN; 3582 } else { 3583 /* Trim 802.11 header. */ 3584 m_adj(m, hdrlen); 3585 tx->security = 0; 3586 } 3587 tx->flags = htole32(flags); 3588 3589 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3590 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3591 if (error != 0 && error != EFBIG) { 3592 printf("%s: can't map mbuf (error %d)\n", 3593 sc->sc_dev.dv_xname, error); 3594 m_freem(m); 3595 return error; 3596 } 3597 if (error != 0) { 3598 /* Too many DMA segments, linearize mbuf. */ 3599 if (m_defrag(m, M_DONTWAIT)) { 3600 m_freem(m); 3601 return ENOBUFS; 3602 } 3603 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3604 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3605 if (error != 0) { 3606 printf("%s: can't map mbuf (error %d)\n", 3607 sc->sc_dev.dv_xname, error); 3608 m_freem(m); 3609 return error; 3610 } 3611 } 3612 3613 data->m = m; 3614 data->ni = ni; 3615 data->ampdu_txmcs = ni->ni_txmcs; /* updated upon Tx interrupt */ 3616 3617 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 3618 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 3619 3620 /* Fill TX descriptor. */ 3621 desc->nsegs = 1 + data->map->dm_nsegs; 3622 /* First DMA segment is used by the TX command. */ 3623 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3624 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3625 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3626 /* Other DMA segments are for data payload. */ 3627 seg = data->map->dm_segs; 3628 for (i = 1; i <= data->map->dm_nsegs; i++) { 3629 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3630 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3631 seg->ds_len << 4); 3632 seg++; 3633 } 3634 3635 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 3636 BUS_DMASYNC_PREWRITE); 3637 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3638 (caddr_t)cmd - ring->cmd_dma.vaddr, sizeof (*cmd), 3639 BUS_DMASYNC_PREWRITE); 3640 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3641 (caddr_t)desc - ring->desc_dma.vaddr, sizeof (*desc), 3642 BUS_DMASYNC_PREWRITE); 3643 3644 /* Update TX scheduler. */ 3645 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3646 3647 /* Kick TX ring. */ 3648 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3649 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3650 3651 /* Mark TX ring as full if we reach a certain threshold. */ 3652 if (++ring->queued > IWN_TX_RING_HIMARK) 3653 sc->qfullmsk |= 1 << ring->qid; 3654 3655 return 0; 3656 } 3657 3658 void 3659 iwn_start(struct ifnet *ifp) 3660 { 3661 struct iwn_softc *sc = ifp->if_softc; 3662 struct ieee80211com *ic = &sc->sc_ic; 3663 struct ieee80211_node *ni; 3664 struct mbuf *m; 3665 3666 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 3667 return; 3668 3669 for (;;) { 3670 if (sc->qfullmsk != 0) { 3671 ifq_set_oactive(&ifp->if_snd); 3672 break; 3673 } 3674 3675 /* Send pending management frames first. */ 3676 m = mq_dequeue(&ic->ic_mgtq); 3677 if (m != NULL) { 3678 ni = m->m_pkthdr.ph_cookie; 3679 goto sendit; 3680 } 3681 if (ic->ic_state != IEEE80211_S_RUN || 3682 (ic->ic_xflags & IEEE80211_F_TX_MGMT_ONLY)) 3683 break; 3684 3685 /* Encapsulate and send data frames. */ 3686 m = ifq_dequeue(&ifp->if_snd); 3687 if (m == NULL) 3688 break; 3689 #if NBPFILTER > 0 3690 if (ifp->if_bpf != NULL) 3691 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 3692 #endif 3693 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 3694 continue; 3695 sendit: 3696 #if NBPFILTER > 0 3697 if (ic->ic_rawbpf != NULL) 3698 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 3699 #endif 3700 if (iwn_tx(sc, m, ni) != 0) { 3701 ieee80211_release_node(ic, ni); 3702 ifp->if_oerrors++; 3703 continue; 3704 } 3705 3706 sc->sc_tx_timer = 5; 3707 ifp->if_timer = 1; 3708 } 3709 } 3710 3711 void 3712 iwn_watchdog(struct ifnet *ifp) 3713 { 3714 struct iwn_softc *sc = ifp->if_softc; 3715 3716 ifp->if_timer = 0; 3717 3718 if (sc->sc_tx_timer > 0) { 3719 if (--sc->sc_tx_timer == 0) { 3720 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 3721 iwn_stop(ifp); 3722 ifp->if_oerrors++; 3723 return; 3724 } 3725 ifp->if_timer = 1; 3726 } 3727 3728 ieee80211_watchdog(ifp); 3729 } 3730 3731 int 3732 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3733 { 3734 struct iwn_softc *sc = ifp->if_softc; 3735 struct ieee80211com *ic = &sc->sc_ic; 3736 int s, error = 0; 3737 3738 error = rw_enter(&sc->sc_rwlock, RW_WRITE | RW_INTR); 3739 if (error) 3740 return error; 3741 s = splnet(); 3742 3743 switch (cmd) { 3744 case SIOCSIFADDR: 3745 ifp->if_flags |= IFF_UP; 3746 /* FALLTHROUGH */ 3747 case SIOCSIFFLAGS: 3748 if (ifp->if_flags & IFF_UP) { 3749 if (!(ifp->if_flags & IFF_RUNNING)) 3750 error = iwn_init(ifp); 3751 } else { 3752 if (ifp->if_flags & IFF_RUNNING) 3753 iwn_stop(ifp); 3754 } 3755 break; 3756 3757 case SIOCS80211POWER: 3758 error = ieee80211_ioctl(ifp, cmd, data); 3759 if (error != ENETRESET) 3760 break; 3761 if (ic->ic_state == IEEE80211_S_RUN && 3762 sc->calib.state == IWN_CALIB_STATE_RUN) { 3763 if (ic->ic_flags & IEEE80211_F_PMGTON) 3764 error = iwn_set_pslevel(sc, 0, 3, 0); 3765 else /* back to CAM */ 3766 error = iwn_set_pslevel(sc, 0, 0, 0); 3767 } else { 3768 /* Defer until transition to IWN_CALIB_STATE_RUN. */ 3769 error = 0; 3770 } 3771 break; 3772 3773 default: 3774 error = ieee80211_ioctl(ifp, cmd, data); 3775 } 3776 3777 if (error == ENETRESET) { 3778 error = 0; 3779 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3780 (IFF_UP | IFF_RUNNING)) { 3781 iwn_stop(ifp); 3782 error = iwn_init(ifp); 3783 } 3784 } 3785 3786 splx(s); 3787 rw_exit_write(&sc->sc_rwlock); 3788 return error; 3789 } 3790 3791 /* 3792 * Send a command to the firmware. 3793 */ 3794 int 3795 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3796 { 3797 struct iwn_ops *ops = &sc->ops; 3798 struct iwn_tx_ring *ring = &sc->txq[4]; 3799 struct iwn_tx_desc *desc; 3800 struct iwn_tx_data *data; 3801 struct iwn_tx_cmd *cmd; 3802 struct mbuf *m; 3803 bus_addr_t paddr; 3804 int totlen, error; 3805 3806 desc = &ring->desc[ring->cur]; 3807 data = &ring->data[ring->cur]; 3808 totlen = 4 + size; 3809 3810 if (size > sizeof cmd->data) { 3811 /* Command is too large to fit in a descriptor. */ 3812 if (totlen > MCLBYTES) 3813 return EINVAL; 3814 MGETHDR(m, M_DONTWAIT, MT_DATA); 3815 if (m == NULL) 3816 return ENOMEM; 3817 if (totlen > MHLEN) { 3818 MCLGET(m, M_DONTWAIT); 3819 if (!(m->m_flags & M_EXT)) { 3820 m_freem(m); 3821 return ENOMEM; 3822 } 3823 } 3824 cmd = mtod(m, struct iwn_tx_cmd *); 3825 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3826 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3827 if (error != 0) { 3828 m_freem(m); 3829 return error; 3830 } 3831 data->m = m; 3832 paddr = data->map->dm_segs[0].ds_addr; 3833 } else { 3834 cmd = &ring->cmd[ring->cur]; 3835 paddr = data->cmd_paddr; 3836 } 3837 3838 cmd->code = code; 3839 cmd->flags = 0; 3840 cmd->qid = ring->qid; 3841 cmd->idx = ring->cur; 3842 memcpy(cmd->data, buf, size); 3843 3844 desc->nsegs = 1; 3845 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3846 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3847 3848 if (size > sizeof cmd->data) { 3849 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3850 BUS_DMASYNC_PREWRITE); 3851 } else { 3852 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3853 (caddr_t)cmd - ring->cmd_dma.vaddr, totlen, 3854 BUS_DMASYNC_PREWRITE); 3855 } 3856 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3857 (caddr_t)desc - ring->desc_dma.vaddr, sizeof (*desc), 3858 BUS_DMASYNC_PREWRITE); 3859 3860 /* Update TX scheduler. */ 3861 ops->update_sched(sc, ring->qid, ring->cur, 0, 0); 3862 3863 /* Kick command ring. */ 3864 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3865 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3866 3867 return async ? 0 : tsleep_nsec(desc, PCATCH, "iwncmd", SEC_TO_NSEC(1)); 3868 } 3869 3870 int 3871 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3872 { 3873 struct iwn4965_node_info hnode; 3874 caddr_t src, dst; 3875 3876 /* 3877 * We use the node structure for 5000 Series internally (it is 3878 * a superset of the one for 4965AGN). We thus copy the common 3879 * fields before sending the command. 3880 */ 3881 src = (caddr_t)node; 3882 dst = (caddr_t)&hnode; 3883 memcpy(dst, src, 48); 3884 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3885 memcpy(dst + 48, src + 72, 20); 3886 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3887 } 3888 3889 int 3890 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3891 { 3892 /* Direct mapping. */ 3893 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3894 } 3895 3896 int 3897 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3898 { 3899 struct ieee80211com *ic = &sc->sc_ic; 3900 struct iwn_node *wn = (void *)ni; 3901 struct iwn_cmd_link_quality linkq; 3902 const struct iwn_rate *rinfo; 3903 uint8_t txant; 3904 int i; 3905 3906 /* Use the first valid TX antenna. */ 3907 txant = IWN_LSB(sc->txchainmask); 3908 3909 memset(&linkq, 0, sizeof linkq); 3910 linkq.id = wn->id; 3911 linkq.antmsk_1stream = txant; 3912 linkq.antmsk_2stream = IWN_ANT_AB; 3913 linkq.ampdu_max = IWN_AMPDU_MAX; 3914 linkq.ampdu_threshold = 3; 3915 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3916 3917 i = 0; 3918 if (ni->ni_flags & IEEE80211_NODE_HT) { 3919 int txmcs; 3920 for (txmcs = ni->ni_txmcs; txmcs >= 0; txmcs--) { 3921 rinfo = &iwn_rates[iwn_mcs2ridx[txmcs]]; 3922 linkq.retry[i].plcp = rinfo->ht_plcp; 3923 linkq.retry[i].rflags = rinfo->ht_flags; 3924 3925 /* XXX set correct ant mask for MIMO rates here */ 3926 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3927 3928 /* First two Tx attempts may use 40MHz/SGI. */ 3929 if (i < 2) { 3930 if (iwn_rxon_ht40_enabled(sc)) 3931 linkq.retry[i].rflags |= IWN_RFLAG_HT40; 3932 if (ieee80211_ra_use_ht_sgi(ni)) 3933 linkq.retry[i].rflags |= IWN_RFLAG_SGI; 3934 } 3935 3936 if (++i >= IWN_MAX_TX_RETRIES) 3937 break; 3938 } 3939 } else { 3940 int txrate; 3941 for (txrate = ni->ni_txrate; txrate >= 0; txrate--) { 3942 rinfo = &iwn_rates[wn->ridx[txrate]]; 3943 linkq.retry[i].plcp = rinfo->plcp; 3944 linkq.retry[i].rflags = rinfo->flags; 3945 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3946 if (++i >= IWN_MAX_TX_RETRIES) 3947 break; 3948 } 3949 } 3950 3951 /* Fill the rest with the lowest basic rate. */ 3952 rinfo = &iwn_rates[iwn_rval2ridx(ieee80211_min_basic_rate(ic))]; 3953 while (i < IWN_MAX_TX_RETRIES) { 3954 linkq.retry[i].plcp = rinfo->plcp; 3955 linkq.retry[i].rflags = rinfo->flags; 3956 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3957 i++; 3958 } 3959 3960 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3961 } 3962 3963 /* 3964 * Broadcast node is used to send group-addressed and management frames. 3965 */ 3966 int 3967 iwn_add_broadcast_node(struct iwn_softc *sc, int async, int ridx) 3968 { 3969 struct iwn_ops *ops = &sc->ops; 3970 struct iwn_node_info node; 3971 struct iwn_cmd_link_quality linkq; 3972 const struct iwn_rate *rinfo; 3973 uint8_t txant; 3974 int i, error; 3975 3976 memset(&node, 0, sizeof node); 3977 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3978 node.id = sc->broadcast_id; 3979 DPRINTF(("adding broadcast node\n")); 3980 if ((error = ops->add_node(sc, &node, async)) != 0) 3981 return error; 3982 3983 /* Use the first valid TX antenna. */ 3984 txant = IWN_LSB(sc->txchainmask); 3985 3986 memset(&linkq, 0, sizeof linkq); 3987 linkq.id = sc->broadcast_id; 3988 linkq.antmsk_1stream = txant; 3989 linkq.antmsk_2stream = IWN_ANT_AB; 3990 linkq.ampdu_max = IWN_AMPDU_MAX_NO_AGG; 3991 linkq.ampdu_threshold = 3; 3992 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3993 3994 /* Use lowest mandatory bit-rate. */ 3995 rinfo = &iwn_rates[ridx]; 3996 linkq.retry[0].plcp = rinfo->plcp; 3997 linkq.retry[0].rflags = rinfo->flags; 3998 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3999 /* Use same bit-rate for all TX retries. */ 4000 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 4001 linkq.retry[i].plcp = linkq.retry[0].plcp; 4002 linkq.retry[i].rflags = linkq.retry[0].rflags; 4003 } 4004 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 4005 } 4006 4007 void 4008 iwn_updateedca(struct ieee80211com *ic) 4009 { 4010 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 4011 struct iwn_softc *sc = ic->ic_softc; 4012 struct iwn_edca_params cmd; 4013 int aci; 4014 4015 memset(&cmd, 0, sizeof cmd); 4016 cmd.flags = htole32(IWN_EDCA_UPDATE); 4017 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 4018 const struct ieee80211_edca_ac_params *ac = 4019 &ic->ic_edca_ac[aci]; 4020 cmd.ac[aci].aifsn = ac->ac_aifsn; 4021 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->ac_ecwmin)); 4022 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->ac_ecwmax)); 4023 cmd.ac[aci].txoplimit = 4024 htole16(IEEE80211_TXOP_TO_US(ac->ac_txoplimit)); 4025 } 4026 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4027 #undef IWN_EXP2 4028 } 4029 4030 void 4031 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 4032 { 4033 struct iwn_cmd_led led; 4034 4035 /* Clear microcode LED ownership. */ 4036 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 4037 4038 led.which = which; 4039 led.unit = htole32(10000); /* on/off in unit of 100ms */ 4040 led.off = off; 4041 led.on = on; 4042 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 4043 } 4044 4045 /* 4046 * Set the critical temperature at which the firmware will stop the radio 4047 * and notify us. 4048 */ 4049 int 4050 iwn_set_critical_temp(struct iwn_softc *sc) 4051 { 4052 struct iwn_critical_temp crit; 4053 int32_t temp; 4054 4055 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 4056 4057 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 4058 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 4059 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 4060 temp = IWN_CTOK(110); 4061 else 4062 temp = 110; 4063 memset(&crit, 0, sizeof crit); 4064 crit.tempR = htole32(temp); 4065 DPRINTF(("setting critical temperature to %d\n", temp)); 4066 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 4067 } 4068 4069 int 4070 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 4071 { 4072 struct iwn_cmd_timing cmd; 4073 uint64_t val, mod; 4074 4075 memset(&cmd, 0, sizeof cmd); 4076 memcpy(&cmd.tstamp, ni->ni_tstamp, sizeof (uint64_t)); 4077 cmd.bintval = htole16(ni->ni_intval); 4078 cmd.lintval = htole16(10); 4079 4080 /* Compute remaining time until next beacon. */ 4081 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 4082 mod = letoh64(cmd.tstamp) % val; 4083 cmd.binitval = htole32((uint32_t)(val - mod)); 4084 4085 DPRINTF(("timing bintval=%u, tstamp=%llu, init=%u\n", 4086 ni->ni_intval, letoh64(cmd.tstamp), (uint32_t)(val - mod))); 4087 4088 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 4089 } 4090 4091 void 4092 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 4093 { 4094 /* Adjust TX power if need be (delta >= 3 degC). */ 4095 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 4096 if (abs(temp - sc->temp) >= 3) { 4097 /* Record temperature of last calibration. */ 4098 sc->temp = temp; 4099 (void)iwn4965_set_txpower(sc, 1); 4100 } 4101 } 4102 4103 /* 4104 * Set TX power for current channel (each rate has its own power settings). 4105 * This function takes into account the regulatory information from EEPROM, 4106 * the current temperature and the current voltage. 4107 */ 4108 int 4109 iwn4965_set_txpower(struct iwn_softc *sc, int async) 4110 { 4111 /* Fixed-point arithmetic division using a n-bit fractional part. */ 4112 #define fdivround(a, b, n) \ 4113 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 4114 /* Linear interpolation. */ 4115 #define interpolate(x, x1, y1, x2, y2, n) \ 4116 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 4117 4118 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 4119 struct ieee80211com *ic = &sc->sc_ic; 4120 struct iwn_ucode_info *uc = &sc->ucode_info; 4121 struct ieee80211_channel *ch; 4122 struct iwn4965_cmd_txpower cmd; 4123 struct iwn4965_eeprom_chan_samples *chans; 4124 const uint8_t *rf_gain, *dsp_gain; 4125 int32_t vdiff, tdiff; 4126 int i, c, grp, maxpwr, is_ht40 = 0; 4127 uint8_t chan, ext_chan; 4128 4129 /* Retrieve current channel from last RXON. */ 4130 chan = sc->rxon.chan; 4131 DPRINTF(("setting TX power for channel %d\n", chan)); 4132 ch = &ic->ic_channels[chan]; 4133 4134 memset(&cmd, 0, sizeof cmd); 4135 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 4136 cmd.chan = chan; 4137 4138 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 4139 maxpwr = sc->maxpwr5GHz; 4140 rf_gain = iwn4965_rf_gain_5ghz; 4141 dsp_gain = iwn4965_dsp_gain_5ghz; 4142 } else { 4143 maxpwr = sc->maxpwr2GHz; 4144 rf_gain = iwn4965_rf_gain_2ghz; 4145 dsp_gain = iwn4965_dsp_gain_2ghz; 4146 } 4147 4148 /* Compute voltage compensation. */ 4149 vdiff = ((int32_t)letoh32(uc->volt) - sc->eeprom_voltage) / 7; 4150 if (vdiff > 0) 4151 vdiff *= 2; 4152 if (abs(vdiff) > 2) 4153 vdiff = 0; 4154 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 4155 vdiff, letoh32(uc->volt), sc->eeprom_voltage)); 4156 4157 /* Get channel attenuation group. */ 4158 if (chan <= 20) /* 1-20 */ 4159 grp = 4; 4160 else if (chan <= 43) /* 34-43 */ 4161 grp = 0; 4162 else if (chan <= 70) /* 44-70 */ 4163 grp = 1; 4164 else if (chan <= 124) /* 71-124 */ 4165 grp = 2; 4166 else /* 125-200 */ 4167 grp = 3; 4168 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 4169 4170 /* Get channel sub-band. */ 4171 for (i = 0; i < IWN_NBANDS; i++) 4172 if (sc->bands[i].lo != 0 && 4173 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 4174 break; 4175 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 4176 return EINVAL; 4177 chans = sc->bands[i].chans; 4178 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 4179 4180 if (iwn_rxon_ht40_enabled(sc)) { 4181 is_ht40 = 1; 4182 if (le32toh(sc->rxon.flags) & IWN_RXON_HT_HT40MINUS) 4183 ext_chan = chan - 2; 4184 else 4185 ext_chan = chan + 2; 4186 } else 4187 ext_chan = chan; 4188 4189 for (c = 0; c < 2; c++) { 4190 uint8_t power, gain, temp; 4191 int maxchpwr, pwr, ridx, idx; 4192 4193 power = interpolate(ext_chan, 4194 chans[0].num, chans[0].samples[c][1].power, 4195 chans[1].num, chans[1].samples[c][1].power, 1); 4196 gain = interpolate(ext_chan, 4197 chans[0].num, chans[0].samples[c][1].gain, 4198 chans[1].num, chans[1].samples[c][1].gain, 1); 4199 temp = interpolate(ext_chan, 4200 chans[0].num, chans[0].samples[c][1].temp, 4201 chans[1].num, chans[1].samples[c][1].temp, 1); 4202 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 4203 c, power, gain, temp)); 4204 4205 /* Compute temperature compensation. */ 4206 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 4207 DPRINTF(("temperature compensation=%d (current=%d, " 4208 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 4209 4210 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 4211 /* Convert dBm to half-dBm. */ 4212 if (is_ht40) 4213 maxchpwr = sc->maxpwr40[chan] * 2; 4214 else 4215 maxchpwr = sc->maxpwr[chan] * 2; 4216 #ifdef notyet 4217 if (ridx > iwn_mcs2ridx[7] && ridx < iwn_mcs2ridx[16]) 4218 maxchpwr -= 6; /* MIMO 2T: -3dB */ 4219 #endif 4220 4221 pwr = maxpwr; 4222 4223 /* Adjust TX power based on rate. */ 4224 if ((ridx % 8) == 5) 4225 pwr -= 15; /* OFDM48: -7.5dB */ 4226 else if ((ridx % 8) == 6) 4227 pwr -= 17; /* OFDM54: -8.5dB */ 4228 else if ((ridx % 8) == 7) 4229 pwr -= 20; /* OFDM60: -10dB */ 4230 else 4231 pwr -= 10; /* Others: -5dB */ 4232 4233 /* Do not exceed channel max TX power. */ 4234 if (pwr > maxchpwr) 4235 pwr = maxchpwr; 4236 4237 idx = gain - (pwr - power) - tdiff - vdiff; 4238 if (ridx > iwn_mcs2ridx[7]) /* MIMO */ 4239 idx += (int32_t)letoh32(uc->atten[grp][c]); 4240 4241 if (cmd.band == 0) 4242 idx += 9; /* 5GHz */ 4243 if (ridx == IWN_RIDX_MAX) 4244 idx += 5; /* CCK */ 4245 4246 /* Make sure idx stays in a valid range. */ 4247 if (idx < 0) 4248 idx = 0; 4249 else if (idx > IWN4965_MAX_PWR_INDEX) 4250 idx = IWN4965_MAX_PWR_INDEX; 4251 4252 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 4253 c, ridx, idx)); 4254 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 4255 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 4256 } 4257 } 4258 4259 DPRINTF(("setting TX power for chan %d\n", chan)); 4260 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 4261 4262 #undef interpolate 4263 #undef fdivround 4264 } 4265 4266 int 4267 iwn5000_set_txpower(struct iwn_softc *sc, int async) 4268 { 4269 struct iwn5000_cmd_txpower cmd; 4270 4271 /* 4272 * TX power calibration is handled automatically by the firmware 4273 * for 5000 Series. 4274 */ 4275 memset(&cmd, 0, sizeof cmd); 4276 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 4277 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 4278 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 4279 DPRINTF(("setting TX power\n")); 4280 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 4281 } 4282 4283 /* 4284 * Retrieve the maximum RSSI (in dBm) among receivers. 4285 */ 4286 int 4287 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 4288 { 4289 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 4290 uint8_t mask, agc; 4291 int rssi; 4292 4293 mask = (letoh16(phy->antenna) >> 4) & IWN_ANT_ABC; 4294 agc = (letoh16(phy->agc) >> 7) & 0x7f; 4295 4296 rssi = 0; 4297 if (mask & IWN_ANT_A) 4298 rssi = MAX(rssi, phy->rssi[0]); 4299 if (mask & IWN_ANT_B) 4300 rssi = MAX(rssi, phy->rssi[2]); 4301 if (mask & IWN_ANT_C) 4302 rssi = MAX(rssi, phy->rssi[4]); 4303 4304 return rssi - agc - IWN_RSSI_TO_DBM; 4305 } 4306 4307 int 4308 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 4309 { 4310 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 4311 uint8_t agc; 4312 int rssi; 4313 4314 agc = (letoh32(phy->agc) >> 9) & 0x7f; 4315 4316 rssi = MAX(letoh16(phy->rssi[0]) & 0xff, 4317 letoh16(phy->rssi[1]) & 0xff); 4318 rssi = MAX(letoh16(phy->rssi[2]) & 0xff, rssi); 4319 4320 return rssi - agc - IWN_RSSI_TO_DBM; 4321 } 4322 4323 /* 4324 * Retrieve the average noise (in dBm) among receivers. 4325 */ 4326 int 4327 iwn_get_noise(const struct iwn_rx_general_stats *stats) 4328 { 4329 int i, total, nbant, noise; 4330 4331 total = nbant = 0; 4332 for (i = 0; i < 3; i++) { 4333 if ((noise = letoh32(stats->noise[i]) & 0xff) == 0) 4334 continue; 4335 total += noise; 4336 nbant++; 4337 } 4338 /* There should be at least one antenna but check anyway. */ 4339 return (nbant == 0) ? -127 : (total / nbant) - 107; 4340 } 4341 4342 /* 4343 * Compute temperature (in degC) from last received statistics. 4344 */ 4345 int 4346 iwn4965_get_temperature(struct iwn_softc *sc) 4347 { 4348 struct iwn_ucode_info *uc = &sc->ucode_info; 4349 int32_t r1, r2, r3, r4, temp; 4350 4351 if (sc->rx_stats_flags & IWN_STATS_FLAGS_BAND_HT40) { 4352 r1 = letoh32(uc->temp[0].chan40MHz); 4353 r2 = letoh32(uc->temp[1].chan40MHz); 4354 r3 = letoh32(uc->temp[2].chan40MHz); 4355 } else { 4356 r1 = letoh32(uc->temp[0].chan20MHz); 4357 r2 = letoh32(uc->temp[1].chan20MHz); 4358 r3 = letoh32(uc->temp[2].chan20MHz); 4359 } 4360 r4 = letoh32(sc->rawtemp); 4361 4362 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 4363 return 0; 4364 4365 /* Sign-extend 23-bit R4 value to 32-bit. */ 4366 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 4367 /* Compute temperature in Kelvin. */ 4368 temp = (259 * (r4 - r2)) / (r3 - r1); 4369 temp = (temp * 97) / 100 + 8; 4370 4371 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 4372 return IWN_KTOC(temp); 4373 } 4374 4375 int 4376 iwn5000_get_temperature(struct iwn_softc *sc) 4377 { 4378 int32_t temp; 4379 4380 /* 4381 * Temperature is not used by the driver for 5000 Series because 4382 * TX power calibration is handled by firmware. 4383 */ 4384 temp = letoh32(sc->rawtemp); 4385 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 4386 temp = (temp / -5) + sc->temp_off; 4387 temp = IWN_KTOC(temp); 4388 } 4389 return temp; 4390 } 4391 4392 /* 4393 * Initialize sensitivity calibration state machine. 4394 */ 4395 int 4396 iwn_init_sensitivity(struct iwn_softc *sc) 4397 { 4398 struct iwn_ops *ops = &sc->ops; 4399 struct iwn_calib_state *calib = &sc->calib; 4400 uint32_t flags; 4401 int error; 4402 4403 /* Reset calibration state machine. */ 4404 memset(calib, 0, sizeof (*calib)); 4405 calib->state = IWN_CALIB_STATE_INIT; 4406 calib->cck_state = IWN_CCK_STATE_HIFA; 4407 /* Set initial correlation values. */ 4408 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 4409 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 4410 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 4411 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 4412 calib->cck_x4 = 125; 4413 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 4414 calib->energy_cck = sc->limits->energy_cck; 4415 4416 /* Write initial sensitivity. */ 4417 if ((error = iwn_send_sensitivity(sc)) != 0) 4418 return error; 4419 4420 /* Write initial gains. */ 4421 if ((error = ops->init_gains(sc)) != 0) 4422 return error; 4423 4424 /* Request statistics at each beacon interval. */ 4425 flags = 0; 4426 DPRINTFN(2, ("sending request for statistics\n")); 4427 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 4428 } 4429 4430 /* 4431 * Collect noise and RSSI statistics for the first 20 beacons received 4432 * after association and use them to determine connected antennas and 4433 * to set differential gains. 4434 */ 4435 void 4436 iwn_collect_noise(struct iwn_softc *sc, 4437 const struct iwn_rx_general_stats *stats) 4438 { 4439 struct iwn_ops *ops = &sc->ops; 4440 struct iwn_calib_state *calib = &sc->calib; 4441 uint32_t val; 4442 int i; 4443 4444 /* Accumulate RSSI and noise for all 3 antennas. */ 4445 for (i = 0; i < 3; i++) { 4446 calib->rssi[i] += letoh32(stats->rssi[i]) & 0xff; 4447 calib->noise[i] += letoh32(stats->noise[i]) & 0xff; 4448 } 4449 /* NB: We update differential gains only once after 20 beacons. */ 4450 if (++calib->nbeacons < 20) 4451 return; 4452 4453 /* Determine highest average RSSI. */ 4454 val = MAX(calib->rssi[0], calib->rssi[1]); 4455 val = MAX(calib->rssi[2], val); 4456 4457 /* Determine which antennas are connected. */ 4458 sc->chainmask = sc->rxchainmask; 4459 for (i = 0; i < 3; i++) 4460 if (val - calib->rssi[i] > 15 * 20) 4461 sc->chainmask &= ~(1 << i); 4462 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 4463 sc->rxchainmask, sc->chainmask)); 4464 4465 /* If none of the TX antennas are connected, keep at least one. */ 4466 if ((sc->chainmask & sc->txchainmask) == 0) 4467 sc->chainmask |= IWN_LSB(sc->txchainmask); 4468 4469 (void)ops->set_gains(sc); 4470 calib->state = IWN_CALIB_STATE_RUN; 4471 4472 #ifdef notyet 4473 /* XXX Disable RX chains with no antennas connected. */ 4474 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 4475 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4476 #endif 4477 4478 /* Enable power-saving mode if requested by user. */ 4479 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 4480 (void)iwn_set_pslevel(sc, 0, 3, 1); 4481 } 4482 4483 int 4484 iwn4965_init_gains(struct iwn_softc *sc) 4485 { 4486 struct iwn_phy_calib_gain cmd; 4487 4488 memset(&cmd, 0, sizeof cmd); 4489 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4490 /* Differential gains initially set to 0 for all 3 antennas. */ 4491 DPRINTF(("setting initial differential gains\n")); 4492 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4493 } 4494 4495 int 4496 iwn5000_init_gains(struct iwn_softc *sc) 4497 { 4498 struct iwn_phy_calib cmd; 4499 4500 memset(&cmd, 0, sizeof cmd); 4501 cmd.code = sc->reset_noise_gain; 4502 cmd.ngroups = 1; 4503 cmd.isvalid = 1; 4504 DPRINTF(("setting initial differential gains\n")); 4505 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4506 } 4507 4508 int 4509 iwn4965_set_gains(struct iwn_softc *sc) 4510 { 4511 struct iwn_calib_state *calib = &sc->calib; 4512 struct iwn_phy_calib_gain cmd; 4513 int i, delta, noise; 4514 4515 /* Get minimal noise among connected antennas. */ 4516 noise = INT_MAX; /* NB: There's at least one antenna. */ 4517 for (i = 0; i < 3; i++) 4518 if (sc->chainmask & (1 << i)) 4519 noise = MIN(calib->noise[i], noise); 4520 4521 memset(&cmd, 0, sizeof cmd); 4522 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4523 /* Set differential gains for connected antennas. */ 4524 for (i = 0; i < 3; i++) { 4525 if (sc->chainmask & (1 << i)) { 4526 /* Compute attenuation (in unit of 1.5dB). */ 4527 delta = (noise - (int32_t)calib->noise[i]) / 30; 4528 /* NB: delta <= 0 */ 4529 /* Limit to [-4.5dB,0]. */ 4530 cmd.gain[i] = MIN(abs(delta), 3); 4531 if (delta < 0) 4532 cmd.gain[i] |= 1 << 2; /* sign bit */ 4533 } 4534 } 4535 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 4536 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 4537 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4538 } 4539 4540 int 4541 iwn5000_set_gains(struct iwn_softc *sc) 4542 { 4543 struct iwn_calib_state *calib = &sc->calib; 4544 struct iwn_phy_calib_gain cmd; 4545 int i, ant, div, delta; 4546 4547 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 4548 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 4549 4550 memset(&cmd, 0, sizeof cmd); 4551 cmd.code = sc->noise_gain; 4552 cmd.ngroups = 1; 4553 cmd.isvalid = 1; 4554 /* 4555 * Get first available RX antenna as referential. 4556 * IWN_LSB() return values start with 1, but antenna gain array 4557 * cmd.gain[] and noise array calib->noise[] start with 0. 4558 */ 4559 ant = IWN_LSB(sc->rxchainmask) - 1; 4560 4561 /* Set differential gains for other antennas. */ 4562 for (i = ant + 1; i < 3; i++) { 4563 if (sc->chainmask & (1 << i)) { 4564 /* The delta is relative to antenna "ant". */ 4565 delta = ((int32_t)calib->noise[ant] - 4566 (int32_t)calib->noise[i]) / div; 4567 DPRINTF(("Ant[%d] vs. Ant[%d]: delta %d\n", ant, i, delta)); 4568 /* Limit to [-4.5dB,+4.5dB]. */ 4569 cmd.gain[i] = MIN(abs(delta), 3); 4570 if (delta < 0) 4571 cmd.gain[i] |= 1 << 2; /* sign bit */ 4572 DPRINTF(("Setting differential gains for antenna %d: %x\n", 4573 i, cmd.gain[i])); 4574 } 4575 } 4576 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4577 } 4578 4579 /* 4580 * Tune RF RX sensitivity based on the number of false alarms detected 4581 * during the last beacon period. 4582 */ 4583 void 4584 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4585 { 4586 #define inc(val, inc, max) \ 4587 if ((val) < (max)) { \ 4588 if ((val) < (max) - (inc)) \ 4589 (val) += (inc); \ 4590 else \ 4591 (val) = (max); \ 4592 needs_update = 1; \ 4593 } 4594 #define dec(val, dec, min) \ 4595 if ((val) > (min)) { \ 4596 if ((val) > (min) + (dec)) \ 4597 (val) -= (dec); \ 4598 else \ 4599 (val) = (min); \ 4600 needs_update = 1; \ 4601 } 4602 4603 const struct iwn_sensitivity_limits *limits = sc->limits; 4604 struct iwn_calib_state *calib = &sc->calib; 4605 uint32_t val, rxena, fa; 4606 uint32_t energy[3], energy_min; 4607 uint8_t noise[3], noise_ref; 4608 int i, needs_update = 0; 4609 4610 /* Check that we've been enabled long enough. */ 4611 if ((rxena = letoh32(stats->general.load)) == 0) 4612 return; 4613 4614 /* Compute number of false alarms since last call for OFDM. */ 4615 fa = letoh32(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4616 fa += letoh32(stats->ofdm.fa) - calib->fa_ofdm; 4617 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4618 4619 /* Save counters values for next call. */ 4620 calib->bad_plcp_ofdm = letoh32(stats->ofdm.bad_plcp); 4621 calib->fa_ofdm = letoh32(stats->ofdm.fa); 4622 4623 if (fa > 50 * rxena) { 4624 /* High false alarm count, decrease sensitivity. */ 4625 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 4626 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4627 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4628 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4629 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4630 4631 } else if (fa < 5 * rxena) { 4632 /* Low false alarm count, increase sensitivity. */ 4633 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 4634 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4635 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4636 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4637 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4638 } 4639 4640 /* Compute maximum noise among 3 receivers. */ 4641 for (i = 0; i < 3; i++) 4642 noise[i] = (letoh32(stats->general.noise[i]) >> 8) & 0xff; 4643 val = MAX(noise[0], noise[1]); 4644 val = MAX(noise[2], val); 4645 /* Insert it into our samples table. */ 4646 calib->noise_samples[calib->cur_noise_sample] = val; 4647 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4648 4649 /* Compute maximum noise among last 20 samples. */ 4650 noise_ref = calib->noise_samples[0]; 4651 for (i = 1; i < 20; i++) 4652 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4653 4654 /* Compute maximum energy among 3 receivers. */ 4655 for (i = 0; i < 3; i++) 4656 energy[i] = letoh32(stats->general.energy[i]); 4657 val = MIN(energy[0], energy[1]); 4658 val = MIN(energy[2], val); 4659 /* Insert it into our samples table. */ 4660 calib->energy_samples[calib->cur_energy_sample] = val; 4661 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4662 4663 /* Compute minimum energy among last 10 samples. */ 4664 energy_min = calib->energy_samples[0]; 4665 for (i = 1; i < 10; i++) 4666 energy_min = MAX(energy_min, calib->energy_samples[i]); 4667 energy_min += 6; 4668 4669 /* Compute number of false alarms since last call for CCK. */ 4670 fa = letoh32(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4671 fa += letoh32(stats->cck.fa) - calib->fa_cck; 4672 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4673 4674 /* Save counters values for next call. */ 4675 calib->bad_plcp_cck = letoh32(stats->cck.bad_plcp); 4676 calib->fa_cck = letoh32(stats->cck.fa); 4677 4678 if (fa > 50 * rxena) { 4679 /* High false alarm count, decrease sensitivity. */ 4680 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 4681 calib->cck_state = IWN_CCK_STATE_HIFA; 4682 calib->low_fa = 0; 4683 4684 if (calib->cck_x4 > 160) { 4685 calib->noise_ref = noise_ref; 4686 if (calib->energy_cck > 2) 4687 dec(calib->energy_cck, 2, energy_min); 4688 } 4689 if (calib->cck_x4 < 160) { 4690 calib->cck_x4 = 161; 4691 needs_update = 1; 4692 } else 4693 inc(calib->cck_x4, 3, limits->max_cck_x4); 4694 4695 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4696 4697 } else if (fa < 5 * rxena) { 4698 /* Low false alarm count, increase sensitivity. */ 4699 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 4700 calib->cck_state = IWN_CCK_STATE_LOFA; 4701 calib->low_fa++; 4702 4703 if (calib->cck_state != IWN_CCK_STATE_INIT && 4704 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4705 calib->low_fa > 100)) { 4706 inc(calib->energy_cck, 2, limits->min_energy_cck); 4707 dec(calib->cck_x4, 3, limits->min_cck_x4); 4708 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4709 } 4710 } else { 4711 /* Not worth to increase or decrease sensitivity. */ 4712 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 4713 calib->low_fa = 0; 4714 calib->noise_ref = noise_ref; 4715 4716 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4717 /* Previous interval had many false alarms. */ 4718 dec(calib->energy_cck, 8, energy_min); 4719 } 4720 calib->cck_state = IWN_CCK_STATE_INIT; 4721 } 4722 4723 if (needs_update) 4724 (void)iwn_send_sensitivity(sc); 4725 #undef dec 4726 #undef inc 4727 } 4728 4729 int 4730 iwn_send_sensitivity(struct iwn_softc *sc) 4731 { 4732 struct iwn_calib_state *calib = &sc->calib; 4733 struct iwn_enhanced_sensitivity_cmd cmd; 4734 int len; 4735 4736 memset(&cmd, 0, sizeof cmd); 4737 len = sizeof (struct iwn_sensitivity_cmd); 4738 cmd.which = IWN_SENSITIVITY_WORKTBL; 4739 /* OFDM modulation. */ 4740 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4741 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4742 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4743 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4744 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4745 cmd.energy_ofdm_th = htole16(62); 4746 /* CCK modulation. */ 4747 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4748 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4749 cmd.energy_cck = htole16(calib->energy_cck); 4750 /* Barker modulation: use default values. */ 4751 cmd.corr_barker = htole16(190); 4752 cmd.corr_barker_mrc = htole16(390); 4753 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 4754 goto send; 4755 /* Enhanced sensitivity settings. */ 4756 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 4757 cmd.ofdm_det_slope_mrc = htole16(668); 4758 cmd.ofdm_det_icept_mrc = htole16(4); 4759 cmd.ofdm_det_slope = htole16(486); 4760 cmd.ofdm_det_icept = htole16(37); 4761 cmd.cck_det_slope_mrc = htole16(853); 4762 cmd.cck_det_icept_mrc = htole16(4); 4763 cmd.cck_det_slope = htole16(476); 4764 cmd.cck_det_icept = htole16(99); 4765 send: 4766 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 4767 } 4768 4769 /* 4770 * Set STA mode power saving level (between 0 and 5). 4771 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4772 */ 4773 int 4774 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4775 { 4776 struct iwn_pmgt_cmd cmd; 4777 const struct iwn_pmgt *pmgt; 4778 uint32_t max, skip_dtim; 4779 pcireg_t reg; 4780 int i; 4781 4782 /* Select which PS parameters to use. */ 4783 if (dtim <= 2) 4784 pmgt = &iwn_pmgt[0][level]; 4785 else if (dtim <= 10) 4786 pmgt = &iwn_pmgt[1][level]; 4787 else 4788 pmgt = &iwn_pmgt[2][level]; 4789 4790 memset(&cmd, 0, sizeof cmd); 4791 if (level != 0) /* not CAM */ 4792 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4793 if (level == 5) 4794 cmd.flags |= htole16(IWN_PS_FAST_PD); 4795 /* Retrieve PCIe Active State Power Management (ASPM). */ 4796 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4797 sc->sc_cap_off + PCI_PCIE_LCSR); 4798 if (!(reg & PCI_PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4799 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4800 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4801 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4802 4803 if (dtim == 0) { 4804 dtim = 1; 4805 skip_dtim = 0; 4806 } else 4807 skip_dtim = pmgt->skip_dtim; 4808 if (skip_dtim != 0) { 4809 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4810 max = pmgt->intval[4]; 4811 if (max == (uint32_t)-1) 4812 max = dtim * (skip_dtim + 1); 4813 else if (max > dtim) 4814 max = (max / dtim) * dtim; 4815 } else 4816 max = dtim; 4817 for (i = 0; i < 5; i++) 4818 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 4819 4820 DPRINTF(("setting power saving level to %d\n", level)); 4821 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4822 } 4823 4824 int 4825 iwn_send_btcoex(struct iwn_softc *sc) 4826 { 4827 struct iwn_bluetooth cmd; 4828 4829 memset(&cmd, 0, sizeof cmd); 4830 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4831 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 4832 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 4833 DPRINTF(("configuring bluetooth coexistence\n")); 4834 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 4835 } 4836 4837 int 4838 iwn_send_advanced_btcoex(struct iwn_softc *sc) 4839 { 4840 static const uint32_t btcoex_3wire[12] = { 4841 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 4842 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 4843 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 4844 }; 4845 struct iwn_btcoex_priotable btprio; 4846 struct iwn_btcoex_prot btprot; 4847 int error, i; 4848 4849 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 4850 sc->hw_type == IWN_HW_REV_TYPE_135) { 4851 struct iwn2000_btcoex_config btconfig; 4852 4853 memset(&btconfig, 0, sizeof btconfig); 4854 btconfig.flags = IWN_BT_COEX6000_CHAN_INHIBITION | 4855 (IWN_BT_COEX6000_MODE_3W << IWN_BT_COEX6000_MODE_SHIFT) | 4856 IWN_BT_SYNC_2_BT_DISABLE; 4857 btconfig.max_kill = 5; 4858 btconfig.bt3_t7_timer = 1; 4859 btconfig.kill_ack = htole32(0xffff0000); 4860 btconfig.kill_cts = htole32(0xffff0000); 4861 btconfig.sample_time = 2; 4862 btconfig.bt3_t2_timer = 0xc; 4863 for (i = 0; i < 12; i++) 4864 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 4865 btconfig.valid = htole16(0xff); 4866 btconfig.prio_boost = htole32(0xf0); 4867 DPRINTF(("configuring advanced bluetooth coexistence\n")); 4868 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 4869 sizeof(btconfig), 1); 4870 if (error != 0) 4871 return (error); 4872 } else { 4873 struct iwn6000_btcoex_config btconfig; 4874 4875 memset(&btconfig, 0, sizeof btconfig); 4876 btconfig.flags = IWN_BT_COEX6000_CHAN_INHIBITION | 4877 (IWN_BT_COEX6000_MODE_3W << IWN_BT_COEX6000_MODE_SHIFT) | 4878 IWN_BT_SYNC_2_BT_DISABLE; 4879 btconfig.max_kill = 5; 4880 btconfig.bt3_t7_timer = 1; 4881 btconfig.kill_ack = htole32(0xffff0000); 4882 btconfig.kill_cts = htole32(0xffff0000); 4883 btconfig.sample_time = 2; 4884 btconfig.bt3_t2_timer = 0xc; 4885 for (i = 0; i < 12; i++) 4886 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 4887 btconfig.valid = htole16(0xff); 4888 btconfig.prio_boost = 0xf0; 4889 DPRINTF(("configuring advanced bluetooth coexistence\n")); 4890 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 4891 sizeof(btconfig), 1); 4892 if (error != 0) 4893 return (error); 4894 } 4895 4896 memset(&btprio, 0, sizeof btprio); 4897 btprio.calib_init1 = 0x6; 4898 btprio.calib_init2 = 0x7; 4899 btprio.calib_periodic_low1 = 0x2; 4900 btprio.calib_periodic_low2 = 0x3; 4901 btprio.calib_periodic_high1 = 0x4; 4902 btprio.calib_periodic_high2 = 0x5; 4903 btprio.dtim = 0x6; 4904 btprio.scan52 = 0x8; 4905 btprio.scan24 = 0xa; 4906 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 4907 1); 4908 if (error != 0) 4909 return (error); 4910 4911 /* Force BT state machine change */ 4912 memset(&btprot, 0, sizeof btprot); 4913 btprot.open = 1; 4914 btprot.type = 1; 4915 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 4916 if (error != 0) 4917 return (error); 4918 4919 btprot.open = 0; 4920 return (iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1)); 4921 } 4922 4923 int 4924 iwn5000_runtime_calib(struct iwn_softc *sc) 4925 { 4926 struct iwn5000_calib_config cmd; 4927 4928 memset(&cmd, 0, sizeof cmd); 4929 cmd.ucode.once.enable = 0xffffffff; 4930 cmd.ucode.once.start = IWN5000_CALIB_DC; 4931 DPRINTF(("configuring runtime calibration\n")); 4932 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 4933 } 4934 4935 int 4936 iwn_config(struct iwn_softc *sc) 4937 { 4938 struct iwn_ops *ops = &sc->ops; 4939 struct ieee80211com *ic = &sc->sc_ic; 4940 struct ifnet *ifp = &ic->ic_if; 4941 uint32_t txmask; 4942 uint16_t rxchain; 4943 int error, ridx; 4944 4945 /* Set radio temperature sensor offset. */ 4946 if (sc->hw_type == IWN_HW_REV_TYPE_6005) { 4947 error = iwn6000_temp_offset_calib(sc); 4948 if (error != 0) { 4949 printf("%s: could not set temperature offset\n", 4950 sc->sc_dev.dv_xname); 4951 return error; 4952 } 4953 } 4954 4955 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 4956 sc->hw_type == IWN_HW_REV_TYPE_2000 || 4957 sc->hw_type == IWN_HW_REV_TYPE_135 || 4958 sc->hw_type == IWN_HW_REV_TYPE_105) { 4959 error = iwn2000_temp_offset_calib(sc); 4960 if (error != 0) { 4961 printf("%s: could not set temperature offset\n", 4962 sc->sc_dev.dv_xname); 4963 return error; 4964 } 4965 } 4966 4967 if (sc->hw_type == IWN_HW_REV_TYPE_6050 || 4968 sc->hw_type == IWN_HW_REV_TYPE_6005) { 4969 /* Configure runtime DC calibration. */ 4970 error = iwn5000_runtime_calib(sc); 4971 if (error != 0) { 4972 printf("%s: could not configure runtime calibration\n", 4973 sc->sc_dev.dv_xname); 4974 return error; 4975 } 4976 } 4977 4978 /* Configure valid TX chains for >=5000 Series. */ 4979 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4980 txmask = htole32(sc->txchainmask); 4981 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 4982 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4983 sizeof txmask, 0); 4984 if (error != 0) { 4985 printf("%s: could not configure valid TX chains\n", 4986 sc->sc_dev.dv_xname); 4987 return error; 4988 } 4989 } 4990 4991 /* Configure bluetooth coexistence. */ 4992 if (sc->sc_flags & IWN_FLAG_ADV_BT_COEX) 4993 error = iwn_send_advanced_btcoex(sc); 4994 else 4995 error = iwn_send_btcoex(sc); 4996 if (error != 0) { 4997 printf("%s: could not configure bluetooth coexistence\n", 4998 sc->sc_dev.dv_xname); 4999 return error; 5000 } 5001 5002 /* Set mode, channel, RX filter and enable RX. */ 5003 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 5004 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 5005 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 5006 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 5007 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 5008 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5009 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) { 5010 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5011 if (ic->ic_flags & IEEE80211_F_USEPROT) 5012 sc->rxon.flags |= htole32(IWN_RXON_TGG_PROT); 5013 DPRINTF(("%s: 2ghz prot 0x%x\n", __func__, 5014 le32toh(sc->rxon.flags))); 5015 } 5016 switch (ic->ic_opmode) { 5017 case IEEE80211_M_STA: 5018 sc->rxon.mode = IWN_MODE_STA; 5019 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 5020 break; 5021 case IEEE80211_M_MONITOR: 5022 sc->rxon.mode = IWN_MODE_MONITOR; 5023 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 5024 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 5025 break; 5026 default: 5027 /* Should not get there. */ 5028 break; 5029 } 5030 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 5031 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 5032 sc->rxon.ht_single_mask = 0xff; 5033 sc->rxon.ht_dual_mask = 0xff; 5034 sc->rxon.ht_triple_mask = 0xff; 5035 rxchain = 5036 IWN_RXCHAIN_VALID(sc->rxchainmask) | 5037 IWN_RXCHAIN_MIMO_COUNT(sc->nrxchains) | 5038 IWN_RXCHAIN_IDLE_COUNT(sc->nrxchains); 5039 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 5040 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 5041 rxchain |= IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask); 5042 rxchain |= (IWN_RXCHAIN_DRIVER_FORCE | IWN_RXCHAIN_MIMO_FORCE); 5043 } 5044 sc->rxon.rxchain = htole16(rxchain); 5045 DPRINTF(("setting configuration\n")); 5046 DPRINTF(("%s: rxon chan %d flags %x cck %x ofdm %x rxchain %x\n", 5047 __func__, sc->rxon.chan, le32toh(sc->rxon.flags), sc->rxon.cck_mask, 5048 sc->rxon.ofdm_mask, sc->rxon.rxchain)); 5049 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 5050 if (error != 0) { 5051 printf("%s: RXON command failed\n", sc->sc_dev.dv_xname); 5052 return error; 5053 } 5054 5055 ridx = (sc->sc_ic.ic_curmode == IEEE80211_MODE_11A) ? 5056 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 5057 if ((error = iwn_add_broadcast_node(sc, 0, ridx)) != 0) { 5058 printf("%s: could not add broadcast node\n", 5059 sc->sc_dev.dv_xname); 5060 return error; 5061 } 5062 5063 /* Configuration has changed, set TX power accordingly. */ 5064 if ((error = ops->set_txpower(sc, 0)) != 0) { 5065 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 5066 return error; 5067 } 5068 5069 if ((error = iwn_set_critical_temp(sc)) != 0) { 5070 printf("%s: could not set critical temperature\n", 5071 sc->sc_dev.dv_xname); 5072 return error; 5073 } 5074 5075 /* Set power saving level to CAM during initialization. */ 5076 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 5077 printf("%s: could not set power saving level\n", 5078 sc->sc_dev.dv_xname); 5079 return error; 5080 } 5081 return 0; 5082 } 5083 5084 uint16_t 5085 iwn_get_active_dwell_time(struct iwn_softc *sc, 5086 uint16_t flags, uint8_t n_probes) 5087 { 5088 /* No channel? Default to 2GHz settings */ 5089 if (flags & IEEE80211_CHAN_2GHZ) { 5090 return (IWN_ACTIVE_DWELL_TIME_2GHZ + 5091 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1)); 5092 } 5093 5094 /* 5GHz dwell time */ 5095 return (IWN_ACTIVE_DWELL_TIME_5GHZ + 5096 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1)); 5097 } 5098 5099 /* 5100 * Limit the total dwell time to 85% of the beacon interval. 5101 * 5102 * Returns the dwell time in milliseconds. 5103 */ 5104 uint16_t 5105 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 5106 { 5107 struct ieee80211com *ic = &sc->sc_ic; 5108 struct ieee80211_node *ni = ic->ic_bss; 5109 int bintval = 0; 5110 5111 /* bintval is in TU (1.024mS) */ 5112 if (ni != NULL) 5113 bintval = ni->ni_intval; 5114 5115 /* 5116 * If it's non-zero, we should calculate the minimum of 5117 * it and the DWELL_BASE. 5118 * 5119 * XXX Yes, the math should take into account that bintval 5120 * is 1.024mS, not 1mS.. 5121 */ 5122 if (ic->ic_state == IEEE80211_S_RUN && bintval > 0) 5123 return (MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100))); 5124 5125 /* No association context? Default */ 5126 return dwell_time; 5127 } 5128 5129 uint16_t 5130 iwn_get_passive_dwell_time(struct iwn_softc *sc, uint16_t flags) 5131 { 5132 uint16_t passive; 5133 if (flags & IEEE80211_CHAN_2GHZ) { 5134 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 5135 } else { 5136 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 5137 } 5138 5139 /* Clamp to the beacon interval if we're associated */ 5140 return (iwn_limit_dwell(sc, passive)); 5141 } 5142 5143 int 5144 iwn_scan(struct iwn_softc *sc, uint16_t flags, int bgscan) 5145 { 5146 struct ieee80211com *ic = &sc->sc_ic; 5147 struct iwn_scan_hdr *hdr; 5148 struct iwn_cmd_data *tx; 5149 struct iwn_scan_essid *essid; 5150 struct iwn_scan_chan *chan; 5151 struct ieee80211_frame *wh; 5152 struct ieee80211_rateset *rs; 5153 struct ieee80211_channel *c; 5154 uint8_t *buf, *frm; 5155 uint16_t rxchain, dwell_active, dwell_passive; 5156 uint8_t txant; 5157 int buflen, error, is_active; 5158 5159 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 5160 if (buf == NULL) { 5161 printf("%s: could not allocate buffer for scan command\n", 5162 sc->sc_dev.dv_xname); 5163 return ENOMEM; 5164 } 5165 hdr = (struct iwn_scan_hdr *)buf; 5166 /* 5167 * Move to the next channel if no frames are received within 10ms 5168 * after sending the probe request. 5169 */ 5170 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 5171 hdr->quiet_threshold = htole16(1); /* min # of packets */ 5172 5173 if (bgscan) { 5174 int bintval; 5175 5176 /* Set maximum off-channel time. */ 5177 hdr->max_out = htole32(200 * 1024); 5178 5179 /* Configure scan pauses which service on-channel traffic. */ 5180 bintval = ic->ic_bss->ni_intval ? ic->ic_bss->ni_intval : 100; 5181 hdr->pause_scan = htole32(((100 / bintval) << 22) | 5182 ((100 % bintval) * 1024)); 5183 } 5184 5185 /* Select antennas for scanning. */ 5186 rxchain = 5187 IWN_RXCHAIN_VALID(sc->rxchainmask) | 5188 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 5189 IWN_RXCHAIN_DRIVER_FORCE; 5190 if ((flags & IEEE80211_CHAN_5GHZ) && 5191 sc->hw_type == IWN_HW_REV_TYPE_4965) { 5192 /* 5193 * On 4965 ant A and C must be avoided in 5GHz because of a 5194 * HW bug which causes very weak RSSI values being reported. 5195 */ 5196 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 5197 } else /* Use all available RX antennas. */ 5198 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 5199 hdr->rxchain = htole16(rxchain); 5200 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 5201 5202 tx = (struct iwn_cmd_data *)(hdr + 1); 5203 tx->flags = htole32(IWN_TX_AUTO_SEQ); 5204 tx->id = sc->broadcast_id; 5205 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 5206 5207 if (flags & IEEE80211_CHAN_5GHZ) { 5208 /* Send probe requests at 6Mbps. */ 5209 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 5210 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 5211 } else { 5212 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 5213 if (bgscan && sc->hw_type == IWN_HW_REV_TYPE_4965 && 5214 sc->rxon.chan > 14) { 5215 /* 5216 * 4965 firmware can crash when sending probe requests 5217 * with CCK rates while associated to a 5GHz AP. 5218 * Send probe requests at 6Mbps OFDM as a workaround. 5219 */ 5220 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 5221 } else { 5222 /* Send probe requests at 1Mbps. */ 5223 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 5224 tx->rflags = IWN_RFLAG_CCK; 5225 } 5226 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 5227 } 5228 /* Use the first valid TX antenna. */ 5229 txant = IWN_LSB(sc->txchainmask); 5230 tx->rflags |= IWN_RFLAG_ANT(txant); 5231 5232 /* 5233 * Only do active scanning if we're announcing a probe request 5234 * for a given SSID (or more, if we ever add it to the driver.) 5235 */ 5236 is_active = 0; 5237 5238 /* 5239 * If we're scanning for a specific SSID, add it to the command. 5240 */ 5241 essid = (struct iwn_scan_essid *)(tx + 1); 5242 if (ic->ic_des_esslen != 0) { 5243 essid[0].id = IEEE80211_ELEMID_SSID; 5244 essid[0].len = ic->ic_des_esslen; 5245 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 5246 5247 is_active = 1; 5248 } 5249 /* 5250 * Build a probe request frame. Most of the following code is a 5251 * copy & paste of what is done in net80211. 5252 */ 5253 wh = (struct ieee80211_frame *)(essid + 20); 5254 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 5255 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 5256 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 5257 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 5258 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 5259 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 5260 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 5261 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 5262 5263 frm = (uint8_t *)(wh + 1); 5264 frm = ieee80211_add_ssid(frm, NULL, 0); 5265 frm = ieee80211_add_rates(frm, rs); 5266 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 5267 frm = ieee80211_add_xrates(frm, rs); 5268 if (ic->ic_flags & IEEE80211_F_HTON) 5269 frm = ieee80211_add_htcaps(frm, ic); 5270 5271 /* Set length of probe request. */ 5272 tx->len = htole16(frm - (uint8_t *)wh); 5273 5274 /* 5275 * If active scanning is requested but a certain channel is 5276 * marked passive, we can do active scanning if we detect 5277 * transmissions. 5278 * 5279 * There is an issue with some firmware versions that triggers 5280 * a sysassert on a "good CRC threshold" of zero (== disabled), 5281 * on a radar channel even though this means that we should NOT 5282 * send probes. 5283 * 5284 * The "good CRC threshold" is the number of frames that we 5285 * need to receive during our dwell time on a channel before 5286 * sending out probes -- setting this to a huge value will 5287 * mean we never reach it, but at the same time work around 5288 * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER 5289 * here instead of IWN_GOOD_CRC_TH_DISABLED. 5290 * 5291 * This was fixed in later versions along with some other 5292 * scan changes, and the threshold behaves as a flag in those 5293 * versions. 5294 */ 5295 5296 /* 5297 * If we're doing active scanning, set the crc_threshold 5298 * to a suitable value. This is different to active veruss 5299 * passive scanning depending upon the channel flags; the 5300 * firmware will obey that particular check for us. 5301 */ 5302 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 5303 hdr->crc_threshold = is_active ? 5304 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 5305 else 5306 hdr->crc_threshold = is_active ? 5307 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 5308 5309 chan = (struct iwn_scan_chan *)frm; 5310 for (c = &ic->ic_channels[1]; 5311 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 5312 if ((c->ic_flags & flags) != flags) 5313 continue; 5314 5315 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 5316 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 5317 chan->flags = 0; 5318 if (ic->ic_des_esslen != 0) 5319 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 5320 5321 if (c->ic_flags & IEEE80211_CHAN_PASSIVE) 5322 chan->flags |= htole32(IWN_CHAN_PASSIVE); 5323 else 5324 chan->flags |= htole32(IWN_CHAN_ACTIVE); 5325 5326 /* 5327 * Calculate the active/passive dwell times. 5328 */ 5329 5330 dwell_active = iwn_get_active_dwell_time(sc, flags, is_active); 5331 dwell_passive = iwn_get_passive_dwell_time(sc, flags); 5332 5333 /* Make sure they're valid */ 5334 if (dwell_passive <= dwell_active) 5335 dwell_passive = dwell_active + 1; 5336 5337 chan->active = htole16(dwell_active); 5338 chan->passive = htole16(dwell_passive); 5339 5340 chan->dsp_gain = 0x6e; 5341 if (IEEE80211_IS_CHAN_5GHZ(c)) { 5342 chan->rf_gain = 0x3b; 5343 } else { 5344 chan->rf_gain = 0x28; 5345 } 5346 hdr->nchan++; 5347 chan++; 5348 } 5349 5350 buflen = (uint8_t *)chan - buf; 5351 hdr->len = htole16(buflen); 5352 5353 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 5354 if (error == 0) { 5355 /* 5356 * The current mode might have been fixed during association. 5357 * Ensure all channels get scanned. 5358 */ 5359 if (IFM_SUBTYPE(ic->ic_media.ifm_cur->ifm_media) == IFM_AUTO) 5360 ieee80211_setmode(ic, IEEE80211_MODE_AUTO); 5361 5362 sc->sc_flags |= IWN_FLAG_SCANNING; 5363 if (bgscan) 5364 sc->sc_flags |= IWN_FLAG_BGSCAN; 5365 } 5366 free(buf, M_DEVBUF, IWN_SCAN_MAXSZ); 5367 return error; 5368 } 5369 5370 void 5371 iwn_scan_abort(struct iwn_softc *sc) 5372 { 5373 iwn_cmd(sc, IWN_CMD_SCAN_ABORT, NULL, 0, 1); 5374 5375 /* XXX Cannot wait for status response in interrupt context. */ 5376 DELAY(100); 5377 5378 sc->sc_flags &= ~IWN_FLAG_SCANNING; 5379 sc->sc_flags &= ~IWN_FLAG_BGSCAN; 5380 } 5381 5382 int 5383 iwn_bgscan(struct ieee80211com *ic) 5384 { 5385 struct iwn_softc *sc = ic->ic_softc; 5386 int error; 5387 5388 if (sc->sc_flags & IWN_FLAG_SCANNING) 5389 return 0; 5390 5391 error = iwn_scan(sc, IEEE80211_CHAN_2GHZ, 1); 5392 if (error) 5393 printf("%s: could not initiate background scan\n", 5394 sc->sc_dev.dv_xname); 5395 return error; 5396 } 5397 5398 void 5399 iwn_rxon_configure_ht40(struct ieee80211com *ic, struct ieee80211_node *ni) 5400 { 5401 struct iwn_softc *sc = ic->ic_softc; 5402 uint8_t sco = (ni->ni_htop0 & IEEE80211_HTOP0_SCO_MASK); 5403 enum ieee80211_htprot htprot = (ni->ni_htop1 & 5404 IEEE80211_HTOP1_PROT_MASK); 5405 5406 sc->rxon.flags &= ~htole32(IWN_RXON_HT_CHANMODE_MIXED2040 | 5407 IWN_RXON_HT_CHANMODE_PURE40 | IWN_RXON_HT_HT40MINUS); 5408 5409 if (ieee80211_node_supports_ht_chan40(ni) && 5410 (sco == IEEE80211_HTOP0_SCO_SCA || 5411 sco == IEEE80211_HTOP0_SCO_SCB)) { 5412 if (sco == IEEE80211_HTOP0_SCO_SCB) 5413 sc->rxon.flags |= htole32(IWN_RXON_HT_HT40MINUS); 5414 if (htprot == IEEE80211_HTPROT_20MHZ) 5415 sc->rxon.flags |= htole32(IWN_RXON_HT_CHANMODE_PURE40); 5416 else 5417 sc->rxon.flags |= htole32( 5418 IWN_RXON_HT_CHANMODE_MIXED2040); 5419 } 5420 } 5421 5422 int 5423 iwn_rxon_ht40_enabled(struct iwn_softc *sc) 5424 { 5425 return ((le32toh(sc->rxon.flags) & IWN_RXON_HT_CHANMODE_MIXED2040) || 5426 (le32toh(sc->rxon.flags) & IWN_RXON_HT_CHANMODE_PURE40)) ? 1 : 0; 5427 } 5428 5429 int 5430 iwn_auth(struct iwn_softc *sc, int arg) 5431 { 5432 struct iwn_ops *ops = &sc->ops; 5433 struct ieee80211com *ic = &sc->sc_ic; 5434 struct ieee80211_node *ni = ic->ic_bss; 5435 int error, ridx; 5436 int bss_switch = 5437 (!IEEE80211_ADDR_EQ(sc->bss_node_addr, etheranyaddr) && 5438 !IEEE80211_ADDR_EQ(sc->bss_node_addr, ni->ni_macaddr)); 5439 5440 /* Update adapter configuration. */ 5441 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 5442 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5443 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5444 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) { 5445 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5446 if (ic->ic_flags & IEEE80211_F_USEPROT) 5447 sc->rxon.flags |= htole32(IWN_RXON_TGG_PROT); 5448 DPRINTF(("%s: 2ghz prot 0x%x\n", __func__, 5449 le32toh(sc->rxon.flags))); 5450 } 5451 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5452 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5453 else 5454 sc->rxon.flags &= ~htole32(IWN_RXON_SHSLOT); 5455 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5456 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5457 else 5458 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE); 5459 switch (ic->ic_curmode) { 5460 case IEEE80211_MODE_11A: 5461 sc->rxon.cck_mask = 0; 5462 sc->rxon.ofdm_mask = 0x15; 5463 break; 5464 case IEEE80211_MODE_11B: 5465 sc->rxon.cck_mask = 0x03; 5466 sc->rxon.ofdm_mask = 0; 5467 break; 5468 default: /* Assume 802.11b/g/n. */ 5469 sc->rxon.cck_mask = 0x0f; 5470 sc->rxon.ofdm_mask = 0x15; 5471 } 5472 /* Configure 40MHz early to avoid problems on 6205 devices. */ 5473 iwn_rxon_configure_ht40(ic, ni); 5474 DPRINTF(("%s: rxon chan %d flags %x cck %x ofdm %x\n", __func__, 5475 sc->rxon.chan, le32toh(sc->rxon.flags), sc->rxon.cck_mask, 5476 sc->rxon.ofdm_mask)); 5477 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5478 if (error != 0) { 5479 printf("%s: RXON command failed\n", sc->sc_dev.dv_xname); 5480 return error; 5481 } 5482 5483 /* Configuration has changed, set TX power accordingly. */ 5484 if ((error = ops->set_txpower(sc, 1)) != 0) { 5485 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 5486 return error; 5487 } 5488 /* 5489 * Reconfiguring RXON clears the firmware nodes table so we must 5490 * add the broadcast node again. 5491 */ 5492 ridx = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 5493 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 5494 if ((error = iwn_add_broadcast_node(sc, 1, ridx)) != 0) { 5495 printf("%s: could not add broadcast node\n", 5496 sc->sc_dev.dv_xname); 5497 return error; 5498 } 5499 5500 /* 5501 * Make sure the firmware gets to see a beacon before we send 5502 * the auth request. Otherwise the Tx attempt can fail due to 5503 * the firmware's built-in regulatory domain enforcement. 5504 * Delaying here for every incoming deauth frame can result in a DoS. 5505 * Don't delay if we're here because of an incoming frame (arg != -1) 5506 * or if we're already waiting for a response (ic_mgt_timer != 0). 5507 * If we are switching APs after a background scan then net80211 has 5508 * just faked the reception of a deauth frame from our old AP, so it 5509 * is safe to delay in that case. 5510 */ 5511 if ((arg == -1 || bss_switch) && ic->ic_mgt_timer == 0) 5512 DELAY(ni->ni_intval * 3 * IEEE80211_DUR_TU); 5513 5514 /* We can now clear the cached address of our previous AP. */ 5515 memset(sc->bss_node_addr, 0, sizeof(sc->bss_node_addr)); 5516 5517 return 0; 5518 } 5519 5520 int 5521 iwn_run(struct iwn_softc *sc) 5522 { 5523 struct iwn_ops *ops = &sc->ops; 5524 struct ieee80211com *ic = &sc->sc_ic; 5525 struct ieee80211_node *ni = ic->ic_bss; 5526 struct iwn_node *wn = (void *)ni; 5527 struct iwn_node_info node; 5528 int error; 5529 5530 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 5531 /* Link LED blinks while monitoring. */ 5532 iwn_set_led(sc, IWN_LED_LINK, 50, 50); 5533 return 0; 5534 } 5535 if ((error = iwn_set_timing(sc, ni)) != 0) { 5536 printf("%s: could not set timing\n", sc->sc_dev.dv_xname); 5537 return error; 5538 } 5539 5540 /* Update adapter configuration. */ 5541 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 5542 /* Short preamble and slot time are negotiated when associating. */ 5543 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 5544 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5545 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5546 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5547 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5548 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 5549 5550 /* HT is negotiated when associating. */ 5551 if (ni->ni_flags & IEEE80211_NODE_HT) { 5552 enum ieee80211_htprot htprot = 5553 (ni->ni_htop1 & IEEE80211_HTOP1_PROT_MASK); 5554 DPRINTF(("%s: htprot = %d\n", __func__, htprot)); 5555 sc->rxon.flags |= htole32(IWN_RXON_HT_PROTMODE(htprot)); 5556 } else 5557 sc->rxon.flags &= ~htole32(IWN_RXON_HT_PROTMODE(3)); 5558 5559 iwn_rxon_configure_ht40(ic, ni); 5560 5561 if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)) { 5562 /* 11a or 11n 5GHz */ 5563 sc->rxon.cck_mask = 0; 5564 sc->rxon.ofdm_mask = 0x15; 5565 } else if (ni->ni_flags & IEEE80211_NODE_HT) { 5566 /* 11n 2GHz */ 5567 sc->rxon.cck_mask = 0x0f; 5568 sc->rxon.ofdm_mask = 0x15; 5569 } else { 5570 if (ni->ni_rates.rs_nrates == 4) { 5571 /* 11b */ 5572 sc->rxon.cck_mask = 0x03; 5573 sc->rxon.ofdm_mask = 0; 5574 } else { 5575 /* assume 11g */ 5576 sc->rxon.cck_mask = 0x0f; 5577 sc->rxon.ofdm_mask = 0x15; 5578 } 5579 } 5580 DPRINTF(("%s: rxon chan %d flags %x cck %x ofdm %x\n", __func__, 5581 sc->rxon.chan, le32toh(sc->rxon.flags), sc->rxon.cck_mask, 5582 sc->rxon.ofdm_mask)); 5583 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5584 if (error != 0) { 5585 printf("%s: could not update configuration\n", 5586 sc->sc_dev.dv_xname); 5587 return error; 5588 } 5589 5590 /* Configuration has changed, set TX power accordingly. */ 5591 if ((error = ops->set_txpower(sc, 1)) != 0) { 5592 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 5593 return error; 5594 } 5595 5596 /* Fake a join to initialize the TX rate. */ 5597 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 5598 iwn_newassoc(ic, ni, 1); 5599 5600 /* Add BSS node. */ 5601 memset(&node, 0, sizeof node); 5602 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 5603 node.id = IWN_ID_BSS; 5604 if (ni->ni_flags & IEEE80211_NODE_HT) { 5605 node.htmask = (IWN_AMDPU_SIZE_FACTOR_MASK | 5606 IWN_AMDPU_DENSITY_MASK); 5607 node.htflags = htole32( 5608 IWN_AMDPU_SIZE_FACTOR( 5609 (ic->ic_ampdu_params & IEEE80211_AMPDU_PARAM_LE)) | 5610 IWN_AMDPU_DENSITY( 5611 (ic->ic_ampdu_params & IEEE80211_AMPDU_PARAM_SS) >> 2)); 5612 if (iwn_rxon_ht40_enabled(sc)) 5613 node.htflags |= htole32(IWN_40MHZ_ENABLE); 5614 } 5615 DPRINTF(("adding BSS node\n")); 5616 error = ops->add_node(sc, &node, 1); 5617 if (error != 0) { 5618 printf("%s: could not add BSS node\n", sc->sc_dev.dv_xname); 5619 return error; 5620 } 5621 5622 /* Cache address of AP in case it changes after a background scan. */ 5623 IEEE80211_ADDR_COPY(sc->bss_node_addr, ni->ni_macaddr); 5624 5625 DPRINTF(("setting link quality for node %d\n", node.id)); 5626 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 5627 printf("%s: could not setup link quality for node %d\n", 5628 sc->sc_dev.dv_xname, node.id); 5629 return error; 5630 } 5631 5632 if ((error = iwn_init_sensitivity(sc)) != 0) { 5633 printf("%s: could not set sensitivity\n", 5634 sc->sc_dev.dv_xname); 5635 return error; 5636 } 5637 /* Start periodic calibration timer. */ 5638 sc->calib.state = IWN_CALIB_STATE_ASSOC; 5639 sc->calib_cnt = 0; 5640 timeout_add_msec(&sc->calib_to, 500); 5641 5642 ieee80211_ra_node_init(&wn->rn); 5643 5644 /* Link LED always on while associated. */ 5645 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 5646 return 0; 5647 } 5648 5649 /* 5650 * We support CCMP hardware encryption/decryption of unicast frames only. 5651 * HW support for TKIP really sucks. We should let TKIP die anyway. 5652 */ 5653 int 5654 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 5655 struct ieee80211_key *k) 5656 { 5657 struct iwn_softc *sc = ic->ic_softc; 5658 struct iwn_ops *ops = &sc->ops; 5659 struct iwn_node *wn = (void *)ni; 5660 struct iwn_node_info node; 5661 uint16_t kflags; 5662 5663 if ((k->k_flags & IEEE80211_KEY_GROUP) || 5664 k->k_cipher != IEEE80211_CIPHER_CCMP) 5665 return ieee80211_set_key(ic, ni, k); 5666 5667 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 5668 if (k->k_flags & IEEE80211_KEY_GROUP) 5669 kflags |= IWN_KFLAG_GROUP; 5670 5671 memset(&node, 0, sizeof node); 5672 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 5673 sc->broadcast_id : wn->id; 5674 node.control = IWN_NODE_UPDATE; 5675 node.flags = IWN_FLAG_SET_KEY; 5676 node.kflags = htole16(kflags); 5677 node.kid = k->k_id; 5678 memcpy(node.key, k->k_key, k->k_len); 5679 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 5680 return ops->add_node(sc, &node, 1); 5681 } 5682 5683 void 5684 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 5685 struct ieee80211_key *k) 5686 { 5687 struct iwn_softc *sc = ic->ic_softc; 5688 struct iwn_ops *ops = &sc->ops; 5689 struct iwn_node *wn = (void *)ni; 5690 struct iwn_node_info node; 5691 5692 if ((k->k_flags & IEEE80211_KEY_GROUP) || 5693 k->k_cipher != IEEE80211_CIPHER_CCMP) { 5694 /* See comment about other ciphers above. */ 5695 ieee80211_delete_key(ic, ni, k); 5696 return; 5697 } 5698 if (ic->ic_state != IEEE80211_S_RUN) 5699 return; /* Nothing to do. */ 5700 memset(&node, 0, sizeof node); 5701 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 5702 sc->broadcast_id : wn->id; 5703 node.control = IWN_NODE_UPDATE; 5704 node.flags = IWN_FLAG_SET_KEY; 5705 node.kflags = htole16(IWN_KFLAG_INVALID); 5706 node.kid = 0xff; 5707 DPRINTF(("delete keys for node %d\n", node.id)); 5708 (void)ops->add_node(sc, &node, 1); 5709 } 5710 5711 void 5712 iwn_updatechan(struct ieee80211com *ic) 5713 { 5714 struct iwn_softc *sc = ic->ic_softc; 5715 5716 if (ic->ic_state != IEEE80211_S_RUN) 5717 return; 5718 5719 iwn_rxon_configure_ht40(ic, ic->ic_bss); 5720 sc->ops.update_rxon(sc); 5721 iwn_set_link_quality(sc, ic->ic_bss); 5722 } 5723 5724 void 5725 iwn_updateprot(struct ieee80211com *ic) 5726 { 5727 struct iwn_softc *sc = ic->ic_softc; 5728 enum ieee80211_htprot htprot; 5729 5730 if (ic->ic_state != IEEE80211_S_RUN) 5731 return; 5732 5733 /* Update ERP protection setting. */ 5734 if (ic->ic_flags & IEEE80211_F_USEPROT) 5735 sc->rxon.flags |= htole32(IWN_RXON_TGG_PROT); 5736 else 5737 sc->rxon.flags &= ~htole32(IWN_RXON_TGG_PROT); 5738 5739 /* Update HT protection mode setting. */ 5740 htprot = (ic->ic_bss->ni_htop1 & IEEE80211_HTOP1_PROT_MASK) >> 5741 IEEE80211_HTOP1_PROT_SHIFT; 5742 sc->rxon.flags &= ~htole32(IWN_RXON_HT_PROTMODE(3)); 5743 sc->rxon.flags |= htole32(IWN_RXON_HT_PROTMODE(htprot)); 5744 5745 sc->ops.update_rxon(sc); 5746 } 5747 5748 void 5749 iwn_updateslot(struct ieee80211com *ic) 5750 { 5751 struct iwn_softc *sc = ic->ic_softc; 5752 5753 if (ic->ic_state != IEEE80211_S_RUN) 5754 return; 5755 5756 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5757 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5758 else 5759 sc->rxon.flags &= ~htole32(IWN_RXON_SHSLOT); 5760 5761 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5762 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5763 else 5764 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE); 5765 5766 sc->ops.update_rxon(sc); 5767 } 5768 5769 void 5770 iwn_update_rxon_restore_power(struct iwn_softc *sc) 5771 { 5772 struct ieee80211com *ic = &sc->sc_ic; 5773 struct iwn_ops *ops = &sc->ops; 5774 int error; 5775 5776 DELAY(100); 5777 5778 /* All RXONs wipe the firmware's txpower table. Restore it. */ 5779 error = ops->set_txpower(sc, 1); 5780 if (error != 0) 5781 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 5782 5783 DELAY(100); 5784 5785 /* Restore power saving level */ 5786 if (ic->ic_flags & IEEE80211_F_PMGTON) 5787 error = iwn_set_pslevel(sc, 0, 3, 1); 5788 else 5789 error = iwn_set_pslevel(sc, 0, 0, 1); 5790 if (error != 0) 5791 printf("%s: could not set PS level\n", sc->sc_dev.dv_xname); 5792 } 5793 5794 void 5795 iwn5000_update_rxon(struct iwn_softc *sc) 5796 { 5797 struct iwn_rxon_assoc rxon_assoc; 5798 int s, error; 5799 5800 /* Update RXON config. */ 5801 memset(&rxon_assoc, 0, sizeof(rxon_assoc)); 5802 rxon_assoc.flags = sc->rxon.flags; 5803 rxon_assoc.filter = sc->rxon.filter; 5804 rxon_assoc.ofdm_mask = sc->rxon.ofdm_mask; 5805 rxon_assoc.cck_mask = sc->rxon.cck_mask; 5806 rxon_assoc.ht_single_mask = sc->rxon.ht_single_mask; 5807 rxon_assoc.ht_dual_mask = sc->rxon.ht_dual_mask; 5808 rxon_assoc.ht_triple_mask = sc->rxon.ht_triple_mask; 5809 rxon_assoc.rxchain = sc->rxon.rxchain; 5810 rxon_assoc.acquisition = sc->rxon.acquisition; 5811 5812 s = splnet(); 5813 5814 error = iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &rxon_assoc, 5815 sizeof(rxon_assoc), 1); 5816 if (error != 0) 5817 printf("%s: RXON_ASSOC command failed\n", sc->sc_dev.dv_xname); 5818 5819 iwn_update_rxon_restore_power(sc); 5820 5821 splx(s); 5822 } 5823 5824 void 5825 iwn4965_update_rxon(struct iwn_softc *sc) 5826 { 5827 struct iwn4965_rxon_assoc rxon_assoc; 5828 int s, error; 5829 5830 /* Update RXON config. */ 5831 memset(&rxon_assoc, 0, sizeof(rxon_assoc)); 5832 rxon_assoc.flags = sc->rxon.flags; 5833 rxon_assoc.filter = sc->rxon.filter; 5834 rxon_assoc.ofdm_mask = sc->rxon.ofdm_mask; 5835 rxon_assoc.cck_mask = sc->rxon.cck_mask; 5836 rxon_assoc.ht_single_mask = sc->rxon.ht_single_mask; 5837 rxon_assoc.ht_dual_mask = sc->rxon.ht_dual_mask; 5838 rxon_assoc.rxchain = sc->rxon.rxchain; 5839 5840 s = splnet(); 5841 5842 error = iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &rxon_assoc, 5843 sizeof(rxon_assoc), 1); 5844 if (error != 0) 5845 printf("%s: RXON_ASSOC command failed\n", sc->sc_dev.dv_xname); 5846 5847 iwn_update_rxon_restore_power(sc); 5848 5849 splx(s); 5850 } 5851 5852 /* 5853 * This function is called by upper layer when an ADDBA request is received 5854 * from another STA and before the ADDBA response is sent. 5855 */ 5856 int 5857 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5858 uint8_t tid) 5859 { 5860 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 5861 struct iwn_softc *sc = ic->ic_softc; 5862 struct iwn_ops *ops = &sc->ops; 5863 struct iwn_node *wn = (void *)ni; 5864 struct iwn_node_info node; 5865 5866 memset(&node, 0, sizeof node); 5867 node.id = wn->id; 5868 node.control = IWN_NODE_UPDATE; 5869 node.flags = IWN_FLAG_SET_ADDBA; 5870 node.addba_tid = tid; 5871 node.addba_ssn = htole16(ba->ba_winstart); 5872 DPRINTF(("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 5873 ba->ba_winstart)); 5874 /* XXX async command, so firmware may still fail to add BA agreement */ 5875 return ops->add_node(sc, &node, 1); 5876 } 5877 5878 /* 5879 * This function is called by upper layer on teardown of an HT-immediate 5880 * Block Ack agreement (e.g., upon receipt of a DELBA frame). 5881 */ 5882 void 5883 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5884 uint8_t tid) 5885 { 5886 struct iwn_softc *sc = ic->ic_softc; 5887 struct iwn_ops *ops = &sc->ops; 5888 struct iwn_node *wn = (void *)ni; 5889 struct iwn_node_info node; 5890 5891 memset(&node, 0, sizeof node); 5892 node.id = wn->id; 5893 node.control = IWN_NODE_UPDATE; 5894 node.flags = IWN_FLAG_SET_DELBA; 5895 node.delba_tid = tid; 5896 DPRINTF(("DELBA RA=%d TID=%d\n", wn->id, tid)); 5897 (void)ops->add_node(sc, &node, 1); 5898 } 5899 5900 /* 5901 * This function is called by upper layer when an ADDBA response is received 5902 * from another STA. 5903 */ 5904 int 5905 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5906 uint8_t tid) 5907 { 5908 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5909 struct iwn_softc *sc = ic->ic_softc; 5910 struct iwn_ops *ops = &sc->ops; 5911 struct iwn_node *wn = (void *)ni; 5912 struct iwn_node_info node; 5913 int qid = sc->first_agg_txq + tid; 5914 int error; 5915 5916 /* Ensure we can map this TID to an aggregation queue. */ 5917 if (tid >= IWN_NUM_AMPDU_TID || ba->ba_winsize > IWN_SCHED_WINSZ || 5918 qid > sc->ntxqs || (sc->agg_queue_mask & (1 << qid))) 5919 return ENOSPC; 5920 5921 /* Enable TX for the specified RA/TID. */ 5922 wn->disable_tid &= ~(1 << tid); 5923 memset(&node, 0, sizeof node); 5924 node.id = wn->id; 5925 node.control = IWN_NODE_UPDATE; 5926 node.flags = IWN_FLAG_SET_DISABLE_TID; 5927 node.disable_tid = htole16(wn->disable_tid); 5928 error = ops->add_node(sc, &node, 1); 5929 if (error != 0) 5930 return error; 5931 5932 if ((error = iwn_nic_lock(sc)) != 0) 5933 return error; 5934 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 5935 iwn_nic_unlock(sc); 5936 5937 sc->agg_queue_mask |= (1 << qid); 5938 sc->sc_tx_ba[tid].wn = wn; 5939 ba->ba_bitmap = 0; 5940 5941 return 0; 5942 } 5943 5944 void 5945 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5946 uint8_t tid) 5947 { 5948 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5949 struct iwn_softc *sc = ic->ic_softc; 5950 struct iwn_ops *ops = &sc->ops; 5951 int qid = sc->first_agg_txq + tid; 5952 struct iwn_node *wn = (void *)ni; 5953 struct iwn_node_info node; 5954 5955 /* Discard all frames in the current window. */ 5956 iwn_ampdu_txq_advance(sc, &sc->txq[qid], qid, 5957 IWN_AGG_SSN_TO_TXQ_IDX(ba->ba_winend)); 5958 5959 if (iwn_nic_lock(sc) != 0) 5960 return; 5961 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart); 5962 iwn_nic_unlock(sc); 5963 5964 sc->agg_queue_mask &= ~(1 << qid); 5965 sc->sc_tx_ba[tid].wn = NULL; 5966 ba->ba_bitmap = 0; 5967 5968 /* Disable TX for the specified RA/TID. */ 5969 wn->disable_tid |= (1 << tid); 5970 memset(&node, 0, sizeof node); 5971 node.id = wn->id; 5972 node.control = IWN_NODE_UPDATE; 5973 node.flags = IWN_FLAG_SET_DISABLE_TID; 5974 node.disable_tid = htole16(wn->disable_tid); 5975 ops->add_node(sc, &node, 1); 5976 } 5977 5978 void 5979 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5980 uint8_t tid, uint16_t ssn) 5981 { 5982 struct iwn_node *wn = (void *)ni; 5983 int qid = IWN4965_FIRST_AGG_TXQUEUE + tid; 5984 uint16_t idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 5985 5986 /* Stop TX scheduler while we're changing its configuration. */ 5987 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5988 IWN4965_TXQ_STATUS_CHGACT); 5989 5990 /* Assign RA/TID translation to the queue. */ 5991 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5992 wn->id << 4 | tid); 5993 5994 /* Enable chain-building mode for the queue. */ 5995 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5996 5997 /* Set starting sequence number from the ADDBA request. */ 5998 sc->txq[qid].cur = sc->txq[qid].read = idx; 5999 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 6000 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 6001 6002 /* Set scheduler window size. */ 6003 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 6004 IWN_SCHED_WINSZ); 6005 /* Set scheduler frame limit. */ 6006 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 6007 IWN_SCHED_LIMIT << 16); 6008 6009 /* Enable interrupts for the queue. */ 6010 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 6011 6012 /* Mark the queue as active. */ 6013 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 6014 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 6015 iwn_tid2fifo[tid] << 1); 6016 } 6017 6018 void 6019 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 6020 { 6021 int qid = IWN4965_FIRST_AGG_TXQUEUE + tid; 6022 uint16_t idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 6023 6024 /* Stop TX scheduler while we're changing its configuration. */ 6025 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 6026 IWN4965_TXQ_STATUS_CHGACT); 6027 6028 /* Set starting sequence number from the ADDBA request. */ 6029 sc->txq[qid].cur = sc->txq[qid].read = idx; 6030 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 6031 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 6032 6033 /* Disable interrupts for the queue. */ 6034 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 6035 6036 /* Mark the queue as inactive. */ 6037 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 6038 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 6039 } 6040 6041 void 6042 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 6043 uint8_t tid, uint16_t ssn) 6044 { 6045 int qid = IWN5000_FIRST_AGG_TXQUEUE + tid; 6046 int idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 6047 struct iwn_node *wn = (void *)ni; 6048 6049 /* Stop TX scheduler while we're changing its configuration. */ 6050 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 6051 IWN5000_TXQ_STATUS_CHGACT); 6052 6053 /* Assign RA/TID translation to the queue. */ 6054 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 6055 wn->id << 4 | tid); 6056 6057 /* Enable chain-building mode for the queue. */ 6058 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 6059 6060 /* Enable aggregation for the queue. */ 6061 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 6062 6063 /* Set starting sequence number from the ADDBA request. */ 6064 sc->txq[qid].cur = sc->txq[qid].read = idx; 6065 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 6066 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 6067 6068 /* Set scheduler window size and frame limit. */ 6069 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 6070 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 6071 6072 /* Enable interrupts for the queue. */ 6073 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 6074 6075 /* Mark the queue as active. */ 6076 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 6077 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 6078 } 6079 6080 void 6081 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 6082 { 6083 int qid = IWN5000_FIRST_AGG_TXQUEUE + tid; 6084 int idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 6085 6086 /* Stop TX scheduler while we're changing its configuration. */ 6087 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 6088 IWN5000_TXQ_STATUS_CHGACT); 6089 6090 /* Disable aggregation for the queue. */ 6091 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 6092 6093 /* Set starting sequence number from the ADDBA request. */ 6094 sc->txq[qid].cur = sc->txq[qid].read = idx; 6095 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 6096 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 6097 6098 /* Disable interrupts for the queue. */ 6099 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 6100 6101 /* Mark the queue as inactive. */ 6102 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 6103 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 6104 } 6105 6106 /* 6107 * Query calibration tables from the initialization firmware. We do this 6108 * only once at first boot. Called from a process context. 6109 */ 6110 int 6111 iwn5000_query_calibration(struct iwn_softc *sc) 6112 { 6113 struct iwn5000_calib_config cmd; 6114 int error; 6115 6116 memset(&cmd, 0, sizeof cmd); 6117 cmd.ucode.once.enable = 0xffffffff; 6118 cmd.ucode.once.start = 0xffffffff; 6119 cmd.ucode.once.send = 0xffffffff; 6120 cmd.ucode.flags = 0xffffffff; 6121 DPRINTF(("sending calibration query\n")); 6122 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 6123 if (error != 0) 6124 return error; 6125 6126 /* Wait at most two seconds for calibration to complete. */ 6127 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 6128 error = tsleep_nsec(sc, PCATCH, "iwncal", SEC_TO_NSEC(2)); 6129 return error; 6130 } 6131 6132 /* 6133 * Send calibration results to the runtime firmware. These results were 6134 * obtained on first boot from the initialization firmware. 6135 */ 6136 int 6137 iwn5000_send_calibration(struct iwn_softc *sc) 6138 { 6139 int idx, error; 6140 6141 for (idx = 0; idx < 5; idx++) { 6142 if (sc->calibcmd[idx].buf == NULL) 6143 continue; /* No results available. */ 6144 DPRINTF(("send calibration result idx=%d len=%d\n", 6145 idx, sc->calibcmd[idx].len)); 6146 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 6147 sc->calibcmd[idx].len, 0); 6148 if (error != 0) { 6149 printf("%s: could not send calibration result\n", 6150 sc->sc_dev.dv_xname); 6151 return error; 6152 } 6153 } 6154 return 0; 6155 } 6156 6157 int 6158 iwn5000_send_wimax_coex(struct iwn_softc *sc) 6159 { 6160 struct iwn5000_wimax_coex wimax; 6161 6162 #ifdef notyet 6163 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 6164 /* Enable WiMAX coexistence for combo adapters. */ 6165 wimax.flags = 6166 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 6167 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 6168 IWN_WIMAX_COEX_STA_TABLE_VALID | 6169 IWN_WIMAX_COEX_ENABLE; 6170 memcpy(wimax.events, iwn6050_wimax_events, 6171 sizeof iwn6050_wimax_events); 6172 } else 6173 #endif 6174 { 6175 /* Disable WiMAX coexistence. */ 6176 wimax.flags = 0; 6177 memset(wimax.events, 0, sizeof wimax.events); 6178 } 6179 DPRINTF(("Configuring WiMAX coexistence\n")); 6180 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 6181 } 6182 6183 int 6184 iwn5000_crystal_calib(struct iwn_softc *sc) 6185 { 6186 struct iwn5000_phy_calib_crystal cmd; 6187 6188 memset(&cmd, 0, sizeof cmd); 6189 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 6190 cmd.ngroups = 1; 6191 cmd.isvalid = 1; 6192 cmd.cap_pin[0] = letoh32(sc->eeprom_crystal) & 0xff; 6193 cmd.cap_pin[1] = (letoh32(sc->eeprom_crystal) >> 16) & 0xff; 6194 DPRINTF(("sending crystal calibration %d, %d\n", 6195 cmd.cap_pin[0], cmd.cap_pin[1])); 6196 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 6197 } 6198 6199 int 6200 iwn6000_temp_offset_calib(struct iwn_softc *sc) 6201 { 6202 struct iwn6000_phy_calib_temp_offset cmd; 6203 6204 memset(&cmd, 0, sizeof cmd); 6205 cmd.code = IWN6000_PHY_CALIB_TEMP_OFFSET; 6206 cmd.ngroups = 1; 6207 cmd.isvalid = 1; 6208 if (sc->eeprom_temp != 0) 6209 cmd.offset = htole16(sc->eeprom_temp); 6210 else 6211 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 6212 DPRINTF(("setting radio sensor offset to %d\n", letoh16(cmd.offset))); 6213 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 6214 } 6215 6216 int 6217 iwn2000_temp_offset_calib(struct iwn_softc *sc) 6218 { 6219 struct iwn2000_phy_calib_temp_offset cmd; 6220 6221 memset(&cmd, 0, sizeof cmd); 6222 cmd.code = IWN2000_PHY_CALIB_TEMP_OFFSET; 6223 cmd.ngroups = 1; 6224 cmd.isvalid = 1; 6225 if (sc->eeprom_rawtemp != 0) { 6226 cmd.offset_low = htole16(sc->eeprom_rawtemp); 6227 cmd.offset_high = htole16(sc->eeprom_temp); 6228 } else { 6229 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 6230 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 6231 } 6232 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 6233 DPRINTF(("setting radio sensor offset to %d:%d, voltage to %d\n", 6234 letoh16(cmd.offset_low), letoh16(cmd.offset_high), 6235 letoh16(cmd.burnt_voltage_ref))); 6236 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 6237 } 6238 6239 /* 6240 * This function is called after the runtime firmware notifies us of its 6241 * readiness (called in a process context). 6242 */ 6243 int 6244 iwn4965_post_alive(struct iwn_softc *sc) 6245 { 6246 int error, qid; 6247 6248 if ((error = iwn_nic_lock(sc)) != 0) 6249 return error; 6250 6251 /* Clear TX scheduler state in SRAM. */ 6252 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 6253 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 6254 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 6255 6256 /* Set physical address of TX scheduler rings (1KB aligned). */ 6257 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 6258 6259 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 6260 6261 /* Disable chain mode for all our 16 queues. */ 6262 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 6263 6264 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 6265 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 6266 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 6267 6268 /* Set scheduler window size. */ 6269 iwn_mem_write(sc, sc->sched_base + 6270 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 6271 /* Set scheduler frame limit. */ 6272 iwn_mem_write(sc, sc->sched_base + 6273 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 6274 IWN_SCHED_LIMIT << 16); 6275 } 6276 6277 /* Enable interrupts for all our 16 queues. */ 6278 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 6279 /* Identify TX FIFO rings (0-7). */ 6280 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 6281 6282 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 6283 for (qid = 0; qid < 7; qid++) { 6284 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 6285 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 6286 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 6287 } 6288 iwn_nic_unlock(sc); 6289 return 0; 6290 } 6291 6292 /* 6293 * This function is called after the initialization or runtime firmware 6294 * notifies us of its readiness (called in a process context). 6295 */ 6296 int 6297 iwn5000_post_alive(struct iwn_softc *sc) 6298 { 6299 int error, qid; 6300 6301 /* Switch to using ICT interrupt mode. */ 6302 iwn5000_ict_reset(sc); 6303 6304 if ((error = iwn_nic_lock(sc)) != 0) 6305 return error; 6306 6307 /* Clear TX scheduler state in SRAM. */ 6308 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 6309 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 6310 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 6311 6312 /* Set physical address of TX scheduler rings (1KB aligned). */ 6313 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 6314 6315 /* Disable scheduler chain extension (enabled by default in HW). */ 6316 iwn_prph_write(sc, IWN5000_SCHED_CHAINEXT_EN, 0); 6317 6318 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 6319 6320 /* Enable chain mode for all queues, except command queue. */ 6321 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 6322 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 6323 6324 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 6325 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 6326 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 6327 6328 iwn_mem_write(sc, sc->sched_base + 6329 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 6330 /* Set scheduler window size and frame limit. */ 6331 iwn_mem_write(sc, sc->sched_base + 6332 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 6333 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 6334 } 6335 6336 /* Enable interrupts for all our 20 queues. */ 6337 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 6338 /* Identify TX FIFO rings (0-7). */ 6339 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 6340 6341 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 6342 for (qid = 0; qid < 7; qid++) { 6343 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 6344 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 6345 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 6346 } 6347 iwn_nic_unlock(sc); 6348 6349 /* Configure WiMAX coexistence for combo adapters. */ 6350 error = iwn5000_send_wimax_coex(sc); 6351 if (error != 0) { 6352 printf("%s: could not configure WiMAX coexistence\n", 6353 sc->sc_dev.dv_xname); 6354 return error; 6355 } 6356 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 6357 /* Perform crystal calibration. */ 6358 error = iwn5000_crystal_calib(sc); 6359 if (error != 0) { 6360 printf("%s: crystal calibration failed\n", 6361 sc->sc_dev.dv_xname); 6362 return error; 6363 } 6364 } 6365 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 6366 /* Query calibration from the initialization firmware. */ 6367 if ((error = iwn5000_query_calibration(sc)) != 0) { 6368 printf("%s: could not query calibration\n", 6369 sc->sc_dev.dv_xname); 6370 return error; 6371 } 6372 /* 6373 * We have the calibration results now, reboot with the 6374 * runtime firmware (call ourselves recursively!) 6375 */ 6376 iwn_hw_stop(sc); 6377 error = iwn_hw_init(sc); 6378 } else { 6379 /* Send calibration results to runtime firmware. */ 6380 error = iwn5000_send_calibration(sc); 6381 } 6382 return error; 6383 } 6384 6385 /* 6386 * The firmware boot code is small and is intended to be copied directly into 6387 * the NIC internal memory (no DMA transfer). 6388 */ 6389 int 6390 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 6391 { 6392 int error, ntries; 6393 6394 size /= sizeof (uint32_t); 6395 6396 if ((error = iwn_nic_lock(sc)) != 0) 6397 return error; 6398 6399 /* Copy microcode image into NIC memory. */ 6400 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 6401 (const uint32_t *)ucode, size); 6402 6403 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 6404 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 6405 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 6406 6407 /* Start boot load now. */ 6408 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 6409 6410 /* Wait for transfer to complete. */ 6411 for (ntries = 0; ntries < 1000; ntries++) { 6412 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 6413 IWN_BSM_WR_CTRL_START)) 6414 break; 6415 DELAY(10); 6416 } 6417 if (ntries == 1000) { 6418 printf("%s: could not load boot firmware\n", 6419 sc->sc_dev.dv_xname); 6420 iwn_nic_unlock(sc); 6421 return ETIMEDOUT; 6422 } 6423 6424 /* Enable boot after power up. */ 6425 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 6426 6427 iwn_nic_unlock(sc); 6428 return 0; 6429 } 6430 6431 int 6432 iwn4965_load_firmware(struct iwn_softc *sc) 6433 { 6434 struct iwn_fw_info *fw = &sc->fw; 6435 struct iwn_dma_info *dma = &sc->fw_dma; 6436 int error; 6437 6438 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 6439 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 6440 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 6441 BUS_DMASYNC_PREWRITE); 6442 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 6443 fw->init.text, fw->init.textsz); 6444 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 6445 fw->init.textsz, BUS_DMASYNC_PREWRITE); 6446 6447 /* Tell adapter where to find initialization sections. */ 6448 if ((error = iwn_nic_lock(sc)) != 0) 6449 return error; 6450 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 6451 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 6452 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 6453 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 6454 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 6455 iwn_nic_unlock(sc); 6456 6457 /* Load firmware boot code. */ 6458 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 6459 if (error != 0) { 6460 printf("%s: could not load boot firmware\n", 6461 sc->sc_dev.dv_xname); 6462 return error; 6463 } 6464 /* Now press "execute". */ 6465 IWN_WRITE(sc, IWN_RESET, 0); 6466 6467 /* Wait at most one second for first alive notification. */ 6468 if ((error = tsleep_nsec(sc, PCATCH, "iwninit", SEC_TO_NSEC(1))) != 0) { 6469 printf("%s: timeout waiting for adapter to initialize\n", 6470 sc->sc_dev.dv_xname); 6471 return error; 6472 } 6473 6474 /* Retrieve current temperature for initial TX power calibration. */ 6475 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 6476 sc->temp = iwn4965_get_temperature(sc); 6477 6478 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 6479 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 6480 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 6481 BUS_DMASYNC_PREWRITE); 6482 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 6483 fw->main.text, fw->main.textsz); 6484 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 6485 fw->main.textsz, BUS_DMASYNC_PREWRITE); 6486 6487 /* Tell adapter where to find runtime sections. */ 6488 if ((error = iwn_nic_lock(sc)) != 0) 6489 return error; 6490 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 6491 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 6492 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 6493 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 6494 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 6495 IWN_FW_UPDATED | fw->main.textsz); 6496 iwn_nic_unlock(sc); 6497 6498 return 0; 6499 } 6500 6501 int 6502 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 6503 const uint8_t *section, int size) 6504 { 6505 struct iwn_dma_info *dma = &sc->fw_dma; 6506 int error; 6507 6508 /* Copy firmware section into pre-allocated DMA-safe memory. */ 6509 memcpy(dma->vaddr, section, size); 6510 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 6511 6512 if ((error = iwn_nic_lock(sc)) != 0) 6513 return error; 6514 6515 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 6516 IWN_FH_TX_CONFIG_DMA_PAUSE); 6517 6518 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 6519 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 6520 IWN_LOADDR(dma->paddr)); 6521 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 6522 IWN_HIADDR(dma->paddr) << 28 | size); 6523 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 6524 IWN_FH_TXBUF_STATUS_TBNUM(1) | 6525 IWN_FH_TXBUF_STATUS_TBIDX(1) | 6526 IWN_FH_TXBUF_STATUS_TFBD_VALID); 6527 6528 /* Kick Flow Handler to start DMA transfer. */ 6529 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 6530 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 6531 6532 iwn_nic_unlock(sc); 6533 6534 /* Wait at most five seconds for FH DMA transfer to complete. */ 6535 return tsleep_nsec(sc, PCATCH, "iwninit", SEC_TO_NSEC(5)); 6536 } 6537 6538 int 6539 iwn5000_load_firmware(struct iwn_softc *sc) 6540 { 6541 struct iwn_fw_part *fw; 6542 int error; 6543 6544 /* Load the initialization firmware on first boot only. */ 6545 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 6546 &sc->fw.main : &sc->fw.init; 6547 6548 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 6549 fw->text, fw->textsz); 6550 if (error != 0) { 6551 printf("%s: could not load firmware %s section\n", 6552 sc->sc_dev.dv_xname, ".text"); 6553 return error; 6554 } 6555 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 6556 fw->data, fw->datasz); 6557 if (error != 0) { 6558 printf("%s: could not load firmware %s section\n", 6559 sc->sc_dev.dv_xname, ".data"); 6560 return error; 6561 } 6562 6563 /* Now press "execute". */ 6564 IWN_WRITE(sc, IWN_RESET, 0); 6565 return 0; 6566 } 6567 6568 /* 6569 * Extract text and data sections from a legacy firmware image. 6570 */ 6571 int 6572 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 6573 { 6574 const uint32_t *ptr; 6575 size_t hdrlen = 24; 6576 uint32_t rev; 6577 6578 ptr = (const uint32_t *)fw->data; 6579 rev = letoh32(*ptr++); 6580 6581 /* Check firmware API version. */ 6582 if (IWN_FW_API(rev) <= 1) { 6583 printf("%s: bad firmware, need API version >=2\n", 6584 sc->sc_dev.dv_xname); 6585 return EINVAL; 6586 } 6587 if (IWN_FW_API(rev) >= 3) { 6588 /* Skip build number (version 2 header). */ 6589 hdrlen += 4; 6590 ptr++; 6591 } 6592 if (fw->size < hdrlen) { 6593 printf("%s: firmware too short: %zu bytes\n", 6594 sc->sc_dev.dv_xname, fw->size); 6595 return EINVAL; 6596 } 6597 fw->main.textsz = letoh32(*ptr++); 6598 fw->main.datasz = letoh32(*ptr++); 6599 fw->init.textsz = letoh32(*ptr++); 6600 fw->init.datasz = letoh32(*ptr++); 6601 fw->boot.textsz = letoh32(*ptr++); 6602 6603 /* Check that all firmware sections fit. */ 6604 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 6605 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 6606 printf("%s: firmware too short: %zu bytes\n", 6607 sc->sc_dev.dv_xname, fw->size); 6608 return EINVAL; 6609 } 6610 6611 /* Get pointers to firmware sections. */ 6612 fw->main.text = (const uint8_t *)ptr; 6613 fw->main.data = fw->main.text + fw->main.textsz; 6614 fw->init.text = fw->main.data + fw->main.datasz; 6615 fw->init.data = fw->init.text + fw->init.textsz; 6616 fw->boot.text = fw->init.data + fw->init.datasz; 6617 return 0; 6618 } 6619 6620 /* 6621 * Extract text and data sections from a TLV firmware image. 6622 */ 6623 int 6624 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 6625 uint16_t alt) 6626 { 6627 const struct iwn_fw_tlv_hdr *hdr; 6628 const struct iwn_fw_tlv *tlv; 6629 const uint8_t *ptr, *end; 6630 uint64_t altmask; 6631 uint32_t len; 6632 6633 if (fw->size < sizeof (*hdr)) { 6634 printf("%s: firmware too short: %zu bytes\n", 6635 sc->sc_dev.dv_xname, fw->size); 6636 return EINVAL; 6637 } 6638 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 6639 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 6640 printf("%s: bad firmware signature 0x%08x\n", 6641 sc->sc_dev.dv_xname, letoh32(hdr->signature)); 6642 return EINVAL; 6643 } 6644 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr, 6645 letoh32(hdr->build))); 6646 6647 /* 6648 * Select the closest supported alternative that is less than 6649 * or equal to the specified one. 6650 */ 6651 altmask = letoh64(hdr->altmask); 6652 while (alt > 0 && !(altmask & (1ULL << alt))) 6653 alt--; /* Downgrade. */ 6654 DPRINTF(("using alternative %d\n", alt)); 6655 6656 ptr = (const uint8_t *)(hdr + 1); 6657 end = (const uint8_t *)(fw->data + fw->size); 6658 6659 /* Parse type-length-value fields. */ 6660 while (ptr + sizeof (*tlv) <= end) { 6661 tlv = (const struct iwn_fw_tlv *)ptr; 6662 len = letoh32(tlv->len); 6663 6664 ptr += sizeof (*tlv); 6665 if (ptr + len > end) { 6666 printf("%s: firmware too short: %zu bytes\n", 6667 sc->sc_dev.dv_xname, fw->size); 6668 return EINVAL; 6669 } 6670 /* Skip other alternatives. */ 6671 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 6672 goto next; 6673 6674 switch (letoh16(tlv->type)) { 6675 case IWN_FW_TLV_MAIN_TEXT: 6676 fw->main.text = ptr; 6677 fw->main.textsz = len; 6678 break; 6679 case IWN_FW_TLV_MAIN_DATA: 6680 fw->main.data = ptr; 6681 fw->main.datasz = len; 6682 break; 6683 case IWN_FW_TLV_INIT_TEXT: 6684 fw->init.text = ptr; 6685 fw->init.textsz = len; 6686 break; 6687 case IWN_FW_TLV_INIT_DATA: 6688 fw->init.data = ptr; 6689 fw->init.datasz = len; 6690 break; 6691 case IWN_FW_TLV_BOOT_TEXT: 6692 fw->boot.text = ptr; 6693 fw->boot.textsz = len; 6694 break; 6695 case IWN_FW_TLV_ENH_SENS: 6696 if (len != 0) { 6697 printf("%s: TLV type %d has invalid size %u\n", 6698 sc->sc_dev.dv_xname, letoh16(tlv->type), 6699 len); 6700 goto next; 6701 } 6702 sc->sc_flags |= IWN_FLAG_ENH_SENS; 6703 break; 6704 case IWN_FW_TLV_PHY_CALIB: 6705 if (len != sizeof(uint32_t)) { 6706 printf("%s: TLV type %d has invalid size %u\n", 6707 sc->sc_dev.dv_xname, letoh16(tlv->type), 6708 len); 6709 goto next; 6710 } 6711 if (letoh32(*ptr) <= IWN5000_PHY_CALIB_MAX) { 6712 sc->reset_noise_gain = letoh32(*ptr); 6713 sc->noise_gain = letoh32(*ptr) + 1; 6714 } 6715 break; 6716 case IWN_FW_TLV_FLAGS: 6717 if (len < sizeof(uint32_t)) 6718 break; 6719 if (len % sizeof(uint32_t)) 6720 break; 6721 sc->tlv_feature_flags = letoh32(*ptr); 6722 DPRINTF(("feature: 0x%08x\n", sc->tlv_feature_flags)); 6723 break; 6724 default: 6725 DPRINTF(("TLV type %d not handled\n", 6726 letoh16(tlv->type))); 6727 break; 6728 } 6729 next: /* TLV fields are 32-bit aligned. */ 6730 ptr += (len + 3) & ~3; 6731 } 6732 return 0; 6733 } 6734 6735 int 6736 iwn_read_firmware(struct iwn_softc *sc) 6737 { 6738 struct iwn_fw_info *fw = &sc->fw; 6739 int error; 6740 6741 /* 6742 * Some PHY calibration commands are firmware-dependent; these 6743 * are the default values that will be overridden if 6744 * necessary. 6745 */ 6746 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 6747 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 6748 6749 memset(fw, 0, sizeof (*fw)); 6750 6751 /* Read firmware image from filesystem. */ 6752 if ((error = loadfirmware(sc->fwname, &fw->data, &fw->size)) != 0) { 6753 printf("%s: could not read firmware %s (error %d)\n", 6754 sc->sc_dev.dv_xname, sc->fwname, error); 6755 return error; 6756 } 6757 if (fw->size < sizeof (uint32_t)) { 6758 printf("%s: firmware too short: %zu bytes\n", 6759 sc->sc_dev.dv_xname, fw->size); 6760 free(fw->data, M_DEVBUF, fw->size); 6761 return EINVAL; 6762 } 6763 6764 /* Retrieve text and data sections. */ 6765 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 6766 error = iwn_read_firmware_leg(sc, fw); 6767 else 6768 error = iwn_read_firmware_tlv(sc, fw, 1); 6769 if (error != 0) { 6770 printf("%s: could not read firmware sections\n", 6771 sc->sc_dev.dv_xname); 6772 free(fw->data, M_DEVBUF, fw->size); 6773 return error; 6774 } 6775 6776 /* Make sure text and data sections fit in hardware memory. */ 6777 if (fw->main.textsz > sc->fw_text_maxsz || 6778 fw->main.datasz > sc->fw_data_maxsz || 6779 fw->init.textsz > sc->fw_text_maxsz || 6780 fw->init.datasz > sc->fw_data_maxsz || 6781 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 6782 (fw->boot.textsz & 3) != 0) { 6783 printf("%s: firmware sections too large\n", 6784 sc->sc_dev.dv_xname); 6785 free(fw->data, M_DEVBUF, fw->size); 6786 return EINVAL; 6787 } 6788 6789 /* We can proceed with loading the firmware. */ 6790 return 0; 6791 } 6792 6793 int 6794 iwn_clock_wait(struct iwn_softc *sc) 6795 { 6796 int ntries; 6797 6798 /* Set "initialization complete" bit. */ 6799 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6800 6801 /* Wait for clock stabilization. */ 6802 for (ntries = 0; ntries < 2500; ntries++) { 6803 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 6804 return 0; 6805 DELAY(10); 6806 } 6807 printf("%s: timeout waiting for clock stabilization\n", 6808 sc->sc_dev.dv_xname); 6809 return ETIMEDOUT; 6810 } 6811 6812 int 6813 iwn_apm_init(struct iwn_softc *sc) 6814 { 6815 pcireg_t reg; 6816 int error; 6817 6818 /* Disable L0s exit timer (NMI bug workaround). */ 6819 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 6820 /* Don't wait for ICH L0s (ICH bug workaround). */ 6821 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 6822 6823 /* Set FH wait threshold to max (HW bug under stress workaround). */ 6824 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 6825 6826 /* Enable HAP INTA to move adapter from L1a to L0s. */ 6827 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 6828 6829 /* Retrieve PCIe Active State Power Management (ASPM). */ 6830 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 6831 sc->sc_cap_off + PCI_PCIE_LCSR); 6832 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 6833 if (reg & PCI_PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 6834 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6835 else 6836 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6837 6838 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6839 sc->hw_type <= IWN_HW_REV_TYPE_1000) 6840 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 6841 6842 /* Wait for clock stabilization before accessing prph. */ 6843 if ((error = iwn_clock_wait(sc)) != 0) 6844 return error; 6845 6846 if ((error = iwn_nic_lock(sc)) != 0) 6847 return error; 6848 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 6849 /* Enable DMA and BSM (Bootstrap State Machine). */ 6850 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6851 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 6852 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 6853 } else { 6854 /* Enable DMA. */ 6855 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6856 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6857 } 6858 DELAY(20); 6859 /* Disable L1-Active. */ 6860 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 6861 iwn_nic_unlock(sc); 6862 6863 return 0; 6864 } 6865 6866 void 6867 iwn_apm_stop_master(struct iwn_softc *sc) 6868 { 6869 int ntries; 6870 6871 /* Stop busmaster DMA activity. */ 6872 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 6873 for (ntries = 0; ntries < 100; ntries++) { 6874 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 6875 return; 6876 DELAY(10); 6877 } 6878 printf("%s: timeout waiting for master\n", sc->sc_dev.dv_xname); 6879 } 6880 6881 void 6882 iwn_apm_stop(struct iwn_softc *sc) 6883 { 6884 iwn_apm_stop_master(sc); 6885 6886 /* Reset the entire device. */ 6887 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 6888 DELAY(10); 6889 /* Clear "initialization complete" bit. */ 6890 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6891 } 6892 6893 int 6894 iwn4965_nic_config(struct iwn_softc *sc) 6895 { 6896 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 6897 /* 6898 * I don't believe this to be correct but this is what the 6899 * vendor driver is doing. Probably the bits should not be 6900 * shifted in IWN_RFCFG_*. 6901 */ 6902 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6903 IWN_RFCFG_TYPE(sc->rfcfg) | 6904 IWN_RFCFG_STEP(sc->rfcfg) | 6905 IWN_RFCFG_DASH(sc->rfcfg)); 6906 } 6907 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6908 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6909 return 0; 6910 } 6911 6912 int 6913 iwn5000_nic_config(struct iwn_softc *sc) 6914 { 6915 uint32_t tmp; 6916 int error; 6917 6918 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 6919 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6920 IWN_RFCFG_TYPE(sc->rfcfg) | 6921 IWN_RFCFG_STEP(sc->rfcfg) | 6922 IWN_RFCFG_DASH(sc->rfcfg)); 6923 } 6924 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6925 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6926 6927 if ((error = iwn_nic_lock(sc)) != 0) 6928 return error; 6929 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 6930 6931 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 6932 /* 6933 * Select first Switching Voltage Regulator (1.32V) to 6934 * solve a stability issue related to noisy DC2DC line 6935 * in the silicon of 1000 Series. 6936 */ 6937 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 6938 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 6939 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 6940 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 6941 } 6942 iwn_nic_unlock(sc); 6943 6944 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 6945 /* Use internal power amplifier only. */ 6946 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 6947 } 6948 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 6949 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 6950 /* Indicate that ROM calibration version is >=6. */ 6951 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 6952 } 6953 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 6954 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 6955 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 6956 sc->hw_type == IWN_HW_REV_TYPE_2000 || 6957 sc->hw_type == IWN_HW_REV_TYPE_135 || 6958 sc->hw_type == IWN_HW_REV_TYPE_105) 6959 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_IQ_INVERT); 6960 return 0; 6961 } 6962 6963 /* 6964 * Take NIC ownership over Intel Active Management Technology (AMT). 6965 */ 6966 int 6967 iwn_hw_prepare(struct iwn_softc *sc) 6968 { 6969 int ntries; 6970 6971 /* Check if hardware is ready. */ 6972 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6973 for (ntries = 0; ntries < 5; ntries++) { 6974 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6975 IWN_HW_IF_CONFIG_NIC_READY) 6976 return 0; 6977 DELAY(10); 6978 } 6979 6980 /* Hardware not ready, force into ready state. */ 6981 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 6982 for (ntries = 0; ntries < 15000; ntries++) { 6983 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 6984 IWN_HW_IF_CONFIG_PREPARE_DONE)) 6985 break; 6986 DELAY(10); 6987 } 6988 if (ntries == 15000) 6989 return ETIMEDOUT; 6990 6991 /* Hardware should be ready now. */ 6992 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6993 for (ntries = 0; ntries < 5; ntries++) { 6994 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6995 IWN_HW_IF_CONFIG_NIC_READY) 6996 return 0; 6997 DELAY(10); 6998 } 6999 return ETIMEDOUT; 7000 } 7001 7002 int 7003 iwn_hw_init(struct iwn_softc *sc) 7004 { 7005 struct iwn_ops *ops = &sc->ops; 7006 int error, chnl, qid; 7007 7008 /* Clear pending interrupts. */ 7009 IWN_WRITE(sc, IWN_INT, 0xffffffff); 7010 7011 if ((error = iwn_apm_init(sc)) != 0) { 7012 printf("%s: could not power on adapter\n", 7013 sc->sc_dev.dv_xname); 7014 return error; 7015 } 7016 7017 /* Select VMAIN power source. */ 7018 if ((error = iwn_nic_lock(sc)) != 0) 7019 return error; 7020 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 7021 iwn_nic_unlock(sc); 7022 7023 /* Perform adapter-specific initialization. */ 7024 if ((error = ops->nic_config(sc)) != 0) 7025 return error; 7026 7027 /* Initialize RX ring. */ 7028 if ((error = iwn_nic_lock(sc)) != 0) 7029 return error; 7030 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 7031 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 7032 /* Set physical address of RX ring (256-byte aligned). */ 7033 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 7034 /* Set physical address of RX status (16-byte aligned). */ 7035 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 7036 /* Enable RX. */ 7037 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 7038 IWN_FH_RX_CONFIG_ENA | 7039 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 7040 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 7041 IWN_FH_RX_CONFIG_SINGLE_FRAME | 7042 IWN_FH_RX_CONFIG_RB_TIMEOUT(0x11) | /* about 1/2 msec */ 7043 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 7044 iwn_nic_unlock(sc); 7045 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 7046 7047 if ((error = iwn_nic_lock(sc)) != 0) 7048 return error; 7049 7050 /* Initialize TX scheduler. */ 7051 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 7052 7053 /* Set physical address of "keep warm" page (16-byte aligned). */ 7054 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 7055 7056 /* Initialize TX rings. */ 7057 for (qid = 0; qid < sc->ntxqs; qid++) { 7058 struct iwn_tx_ring *txq = &sc->txq[qid]; 7059 7060 /* Set physical address of TX ring (256-byte aligned). */ 7061 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 7062 txq->desc_dma.paddr >> 8); 7063 } 7064 iwn_nic_unlock(sc); 7065 7066 /* Enable DMA channels. */ 7067 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 7068 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 7069 IWN_FH_TX_CONFIG_DMA_ENA | 7070 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 7071 } 7072 7073 /* Clear "radio off" and "commands blocked" bits. */ 7074 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 7075 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 7076 7077 /* Clear pending interrupts. */ 7078 IWN_WRITE(sc, IWN_INT, 0xffffffff); 7079 /* Enable interrupt coalescing. */ 7080 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 7081 /* Enable interrupts. */ 7082 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 7083 7084 /* _Really_ make sure "radio off" bit is cleared! */ 7085 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 7086 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 7087 7088 /* Enable shadow registers. */ 7089 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 7090 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 7091 7092 if ((error = ops->load_firmware(sc)) != 0) { 7093 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 7094 return error; 7095 } 7096 /* Wait at most one second for firmware alive notification. */ 7097 if ((error = tsleep_nsec(sc, PCATCH, "iwninit", SEC_TO_NSEC(1))) != 0) { 7098 printf("%s: timeout waiting for adapter to initialize\n", 7099 sc->sc_dev.dv_xname); 7100 return error; 7101 } 7102 /* Do post-firmware initialization. */ 7103 return ops->post_alive(sc); 7104 } 7105 7106 void 7107 iwn_hw_stop(struct iwn_softc *sc) 7108 { 7109 int chnl, qid, ntries; 7110 7111 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 7112 7113 /* Disable interrupts. */ 7114 IWN_WRITE(sc, IWN_INT_MASK, 0); 7115 IWN_WRITE(sc, IWN_INT, 0xffffffff); 7116 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 7117 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 7118 7119 /* Make sure we no longer hold the NIC lock. */ 7120 iwn_nic_unlock(sc); 7121 7122 /* Stop TX scheduler. */ 7123 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 7124 7125 /* Stop all DMA channels. */ 7126 if (iwn_nic_lock(sc) == 0) { 7127 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 7128 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 7129 for (ntries = 0; ntries < 200; ntries++) { 7130 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 7131 IWN_FH_TX_STATUS_IDLE(chnl)) 7132 break; 7133 DELAY(10); 7134 } 7135 } 7136 iwn_nic_unlock(sc); 7137 } 7138 7139 /* Stop RX ring. */ 7140 iwn_reset_rx_ring(sc, &sc->rxq); 7141 7142 /* Reset all TX rings. */ 7143 for (qid = 0; qid < sc->ntxqs; qid++) 7144 iwn_reset_tx_ring(sc, &sc->txq[qid]); 7145 7146 if (iwn_nic_lock(sc) == 0) { 7147 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 7148 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 7149 iwn_nic_unlock(sc); 7150 } 7151 DELAY(5); 7152 /* Power OFF adapter. */ 7153 iwn_apm_stop(sc); 7154 } 7155 7156 int 7157 iwn_init(struct ifnet *ifp) 7158 { 7159 struct iwn_softc *sc = ifp->if_softc; 7160 struct ieee80211com *ic = &sc->sc_ic; 7161 int error; 7162 7163 memset(sc->bss_node_addr, 0, sizeof(sc->bss_node_addr)); 7164 sc->agg_queue_mask = 0; 7165 memset(sc->sc_tx_ba, 0, sizeof(sc->sc_tx_ba)); 7166 7167 if ((error = iwn_hw_prepare(sc)) != 0) { 7168 printf("%s: hardware not ready\n", sc->sc_dev.dv_xname); 7169 goto fail; 7170 } 7171 7172 /* Initialize interrupt mask to default value. */ 7173 sc->int_mask = IWN_INT_MASK_DEF; 7174 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 7175 7176 /* Check that the radio is not disabled by hardware switch. */ 7177 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 7178 printf("%s: radio is disabled by hardware switch\n", 7179 sc->sc_dev.dv_xname); 7180 error = EPERM; /* :-) */ 7181 /* Re-enable interrupts. */ 7182 IWN_WRITE(sc, IWN_INT, 0xffffffff); 7183 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 7184 return error; 7185 } 7186 7187 /* Read firmware images from the filesystem. */ 7188 if ((error = iwn_read_firmware(sc)) != 0) { 7189 printf("%s: could not read firmware\n", sc->sc_dev.dv_xname); 7190 goto fail; 7191 } 7192 7193 /* Initialize hardware and upload firmware. */ 7194 error = iwn_hw_init(sc); 7195 free(sc->fw.data, M_DEVBUF, sc->fw.size); 7196 if (error != 0) { 7197 printf("%s: could not initialize hardware\n", 7198 sc->sc_dev.dv_xname); 7199 goto fail; 7200 } 7201 7202 /* Configure adapter now that it is ready. */ 7203 if ((error = iwn_config(sc)) != 0) { 7204 printf("%s: could not configure device\n", 7205 sc->sc_dev.dv_xname); 7206 goto fail; 7207 } 7208 7209 ifq_clr_oactive(&ifp->if_snd); 7210 ifp->if_flags |= IFF_RUNNING; 7211 7212 if (ic->ic_opmode != IEEE80211_M_MONITOR) 7213 ieee80211_begin_scan(ifp); 7214 else 7215 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 7216 7217 return 0; 7218 7219 fail: iwn_stop(ifp); 7220 return error; 7221 } 7222 7223 void 7224 iwn_stop(struct ifnet *ifp) 7225 { 7226 struct iwn_softc *sc = ifp->if_softc; 7227 struct ieee80211com *ic = &sc->sc_ic; 7228 7229 timeout_del(&sc->calib_to); 7230 ifp->if_timer = sc->sc_tx_timer = 0; 7231 ifp->if_flags &= ~IFF_RUNNING; 7232 ifq_clr_oactive(&ifp->if_snd); 7233 7234 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 7235 7236 /* Power OFF hardware. */ 7237 iwn_hw_stop(sc); 7238 } 7239