1 /* $OpenBSD: if_iwn.c,v 1.250 2021/10/11 09:01:05 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 21 * adapters. 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/mbuf.h> 29 #include <sys/kernel.h> 30 #include <sys/rwlock.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/conf.h> 35 #include <sys/device.h> 36 #include <sys/task.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 46 #if NBPFILTER > 0 47 #include <net/bpf.h> 48 #endif 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 53 #include <netinet/in.h> 54 #include <netinet/if_ether.h> 55 56 #include <net80211/ieee80211_var.h> 57 #include <net80211/ieee80211_amrr.h> 58 #include <net80211/ieee80211_ra.h> 59 #include <net80211/ieee80211_radiotap.h> 60 #include <net80211/ieee80211_priv.h> /* for SEQ_LT */ 61 #undef DPRINTF /* defined in ieee80211_priv.h */ 62 63 #include <dev/pci/if_iwnreg.h> 64 #include <dev/pci/if_iwnvar.h> 65 66 static const struct pci_matchid iwn_devices[] = { 67 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_4965_1 }, 68 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_4965_2 }, 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5100_1 }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5100_2 }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5150_1 }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5150_2 }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5300_1 }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5300_2 }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5350_1 }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5350_2 }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1000_1 }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1000_2 }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6300_1 }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6300_2 }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6200_1 }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6200_2 }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6050_1 }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6050_2 }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6005_1 }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6005_2 }, 87 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6030_1 }, 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6030_2 }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1030_1 }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1030_2 }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_100_1 }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_100_2 }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_130_1 }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_130_2 }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6235_1 }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6235_2 }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2230_1 }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2230_2 }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2200_1 }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2200_2 }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_135_1 }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_135_2 }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_105_1 }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_105_2 }, 105 }; 106 107 int iwn_match(struct device *, void *, void *); 108 void iwn_attach(struct device *, struct device *, void *); 109 int iwn4965_attach(struct iwn_softc *, pci_product_id_t); 110 int iwn5000_attach(struct iwn_softc *, pci_product_id_t); 111 #if NBPFILTER > 0 112 void iwn_radiotap_attach(struct iwn_softc *); 113 #endif 114 int iwn_detach(struct device *, int); 115 int iwn_activate(struct device *, int); 116 void iwn_wakeup(struct iwn_softc *); 117 void iwn_init_task(void *); 118 int iwn_nic_lock(struct iwn_softc *); 119 int iwn_eeprom_lock(struct iwn_softc *); 120 int iwn_init_otprom(struct iwn_softc *); 121 int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 122 int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 123 void **, bus_size_t, bus_size_t); 124 void iwn_dma_contig_free(struct iwn_dma_info *); 125 int iwn_alloc_sched(struct iwn_softc *); 126 void iwn_free_sched(struct iwn_softc *); 127 int iwn_alloc_kw(struct iwn_softc *); 128 void iwn_free_kw(struct iwn_softc *); 129 int iwn_alloc_ict(struct iwn_softc *); 130 void iwn_free_ict(struct iwn_softc *); 131 int iwn_alloc_fwmem(struct iwn_softc *); 132 void iwn_free_fwmem(struct iwn_softc *); 133 int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 134 void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 135 void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 136 int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 137 int); 138 void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 139 void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 140 void iwn5000_ict_reset(struct iwn_softc *); 141 int iwn_read_eeprom(struct iwn_softc *); 142 void iwn4965_read_eeprom(struct iwn_softc *); 143 void iwn4965_print_power_group(struct iwn_softc *, int); 144 void iwn5000_read_eeprom(struct iwn_softc *); 145 void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 146 void iwn_read_eeprom_enhinfo(struct iwn_softc *); 147 struct ieee80211_node *iwn_node_alloc(struct ieee80211com *); 148 void iwn_newassoc(struct ieee80211com *, struct ieee80211_node *, 149 int); 150 int iwn_media_change(struct ifnet *); 151 int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 152 void iwn_iter_func(void *, struct ieee80211_node *); 153 void iwn_calib_timeout(void *); 154 int iwn_ccmp_decap(struct iwn_softc *, struct mbuf *, 155 struct ieee80211_node *); 156 void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 157 struct iwn_rx_data *); 158 void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 159 struct iwn_rx_data *, struct mbuf_list *); 160 void iwn_ra_choose(struct iwn_softc *, struct ieee80211_node *); 161 void iwn_ampdu_rate_control(struct iwn_softc *, struct ieee80211_node *, 162 struct iwn_tx_ring *, uint16_t, uint16_t); 163 void iwn_ht_single_rate_control(struct iwn_softc *, 164 struct ieee80211_node *, uint8_t, uint8_t, uint8_t, int); 165 void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 166 struct iwn_rx_data *); 167 void iwn5000_rx_calib_results(struct iwn_softc *, 168 struct iwn_rx_desc *, struct iwn_rx_data *); 169 void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 170 struct iwn_rx_data *); 171 void iwn_ampdu_txq_advance(struct iwn_softc *, struct iwn_tx_ring *, 172 int, int); 173 void iwn_ampdu_tx_done(struct iwn_softc *, struct iwn_tx_ring *, 174 struct iwn_rx_desc *, uint16_t, uint8_t, uint8_t, uint8_t, 175 int, uint32_t, struct iwn_txagg_status *); 176 void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 177 struct iwn_rx_data *); 178 void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 179 struct iwn_rx_data *); 180 void iwn_tx_done_free_txdata(struct iwn_softc *, 181 struct iwn_tx_data *); 182 void iwn_clear_oactive(struct iwn_softc *, struct iwn_tx_ring *); 183 void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 184 uint8_t, uint8_t, uint8_t, int, int, uint16_t); 185 void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 186 void iwn_notif_intr(struct iwn_softc *); 187 void iwn_wakeup_intr(struct iwn_softc *); 188 void iwn_fatal_intr(struct iwn_softc *); 189 int iwn_intr(void *); 190 void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 191 uint16_t); 192 void iwn4965_reset_sched(struct iwn_softc *, int, int); 193 void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 194 uint16_t); 195 void iwn5000_reset_sched(struct iwn_softc *, int, int); 196 int iwn_tx(struct iwn_softc *, struct mbuf *, 197 struct ieee80211_node *); 198 int iwn_rval2ridx(int); 199 void iwn_start(struct ifnet *); 200 void iwn_watchdog(struct ifnet *); 201 int iwn_ioctl(struct ifnet *, u_long, caddr_t); 202 int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 203 int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 204 int); 205 int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 206 int); 207 int iwn_set_link_quality(struct iwn_softc *, 208 struct ieee80211_node *); 209 int iwn_add_broadcast_node(struct iwn_softc *, int, int); 210 void iwn_updateedca(struct ieee80211com *); 211 void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 212 int iwn_set_critical_temp(struct iwn_softc *); 213 int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 214 void iwn4965_power_calibration(struct iwn_softc *, int); 215 int iwn4965_set_txpower(struct iwn_softc *, int); 216 int iwn5000_set_txpower(struct iwn_softc *, int); 217 int iwn4965_get_rssi(const struct iwn_rx_stat *); 218 int iwn5000_get_rssi(const struct iwn_rx_stat *); 219 int iwn_get_noise(const struct iwn_rx_general_stats *); 220 int iwn4965_get_temperature(struct iwn_softc *); 221 int iwn5000_get_temperature(struct iwn_softc *); 222 int iwn_init_sensitivity(struct iwn_softc *); 223 void iwn_collect_noise(struct iwn_softc *, 224 const struct iwn_rx_general_stats *); 225 int iwn4965_init_gains(struct iwn_softc *); 226 int iwn5000_init_gains(struct iwn_softc *); 227 int iwn4965_set_gains(struct iwn_softc *); 228 int iwn5000_set_gains(struct iwn_softc *); 229 void iwn_tune_sensitivity(struct iwn_softc *, 230 const struct iwn_rx_stats *); 231 int iwn_send_sensitivity(struct iwn_softc *); 232 int iwn_set_pslevel(struct iwn_softc *, int, int, int); 233 int iwn_send_temperature_offset(struct iwn_softc *); 234 int iwn_send_btcoex(struct iwn_softc *); 235 int iwn_send_advanced_btcoex(struct iwn_softc *); 236 int iwn5000_runtime_calib(struct iwn_softc *); 237 int iwn_config(struct iwn_softc *); 238 uint16_t iwn_get_active_dwell_time(struct iwn_softc *, uint16_t, uint8_t); 239 uint16_t iwn_limit_dwell(struct iwn_softc *, uint16_t); 240 uint16_t iwn_get_passive_dwell_time(struct iwn_softc *, uint16_t); 241 int iwn_scan(struct iwn_softc *, uint16_t, int); 242 void iwn_scan_abort(struct iwn_softc *); 243 int iwn_bgscan(struct ieee80211com *); 244 int iwn_auth(struct iwn_softc *, int); 245 int iwn_run(struct iwn_softc *); 246 int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 247 struct ieee80211_key *); 248 void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 249 struct ieee80211_key *); 250 void iwn_updateprot(struct ieee80211com *); 251 void iwn_updateslot(struct ieee80211com *); 252 void iwn_update_rxon(struct iwn_softc *); 253 int iwn_ampdu_rx_start(struct ieee80211com *, 254 struct ieee80211_node *, uint8_t); 255 void iwn_ampdu_rx_stop(struct ieee80211com *, 256 struct ieee80211_node *, uint8_t); 257 int iwn_ampdu_tx_start(struct ieee80211com *, 258 struct ieee80211_node *, uint8_t); 259 void iwn_ampdu_tx_stop(struct ieee80211com *, 260 struct ieee80211_node *, uint8_t); 261 void iwn4965_ampdu_tx_start(struct iwn_softc *, 262 struct ieee80211_node *, uint8_t, uint16_t); 263 void iwn4965_ampdu_tx_stop(struct iwn_softc *, 264 uint8_t, uint16_t); 265 void iwn5000_ampdu_tx_start(struct iwn_softc *, 266 struct ieee80211_node *, uint8_t, uint16_t); 267 void iwn5000_ampdu_tx_stop(struct iwn_softc *, 268 uint8_t, uint16_t); 269 int iwn5000_query_calibration(struct iwn_softc *); 270 int iwn5000_send_calibration(struct iwn_softc *); 271 int iwn5000_send_wimax_coex(struct iwn_softc *); 272 int iwn5000_crystal_calib(struct iwn_softc *); 273 int iwn6000_temp_offset_calib(struct iwn_softc *); 274 int iwn2000_temp_offset_calib(struct iwn_softc *); 275 int iwn4965_post_alive(struct iwn_softc *); 276 int iwn5000_post_alive(struct iwn_softc *); 277 int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 278 int); 279 int iwn4965_load_firmware(struct iwn_softc *); 280 int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 281 const uint8_t *, int); 282 int iwn5000_load_firmware(struct iwn_softc *); 283 int iwn_read_firmware_leg(struct iwn_softc *, 284 struct iwn_fw_info *); 285 int iwn_read_firmware_tlv(struct iwn_softc *, 286 struct iwn_fw_info *, uint16_t); 287 int iwn_read_firmware(struct iwn_softc *); 288 int iwn_clock_wait(struct iwn_softc *); 289 int iwn_apm_init(struct iwn_softc *); 290 void iwn_apm_stop_master(struct iwn_softc *); 291 void iwn_apm_stop(struct iwn_softc *); 292 int iwn4965_nic_config(struct iwn_softc *); 293 int iwn5000_nic_config(struct iwn_softc *); 294 int iwn_hw_prepare(struct iwn_softc *); 295 int iwn_hw_init(struct iwn_softc *); 296 void iwn_hw_stop(struct iwn_softc *); 297 int iwn_init(struct ifnet *); 298 void iwn_stop(struct ifnet *); 299 300 #ifdef IWN_DEBUG 301 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 302 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 303 int iwn_debug = 1; 304 #else 305 #define DPRINTF(x) 306 #define DPRINTFN(n, x) 307 #endif 308 309 struct cfdriver iwn_cd = { 310 NULL, "iwn", DV_IFNET 311 }; 312 313 struct cfattach iwn_ca = { 314 sizeof (struct iwn_softc), iwn_match, iwn_attach, iwn_detach, 315 iwn_activate 316 }; 317 318 int 319 iwn_match(struct device *parent, void *match, void *aux) 320 { 321 return pci_matchbyid((struct pci_attach_args *)aux, iwn_devices, 322 nitems(iwn_devices)); 323 } 324 325 void 326 iwn_attach(struct device *parent, struct device *self, void *aux) 327 { 328 struct iwn_softc *sc = (struct iwn_softc *)self; 329 struct ieee80211com *ic = &sc->sc_ic; 330 struct ifnet *ifp = &ic->ic_if; 331 struct pci_attach_args *pa = aux; 332 const char *intrstr; 333 pci_intr_handle_t ih; 334 pcireg_t memtype, reg; 335 int i, error; 336 337 sc->sc_pct = pa->pa_pc; 338 sc->sc_pcitag = pa->pa_tag; 339 sc->sc_dmat = pa->pa_dmat; 340 341 /* 342 * Get the offset of the PCI Express Capability Structure in PCI 343 * Configuration Space. 344 */ 345 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 346 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 347 if (error == 0) { 348 printf(": PCIe capability structure not found!\n"); 349 return; 350 } 351 352 /* Clear device-specific "PCI retry timeout" register (41h). */ 353 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 354 if (reg & 0xff00) 355 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 356 357 /* Hardware bug workaround. */ 358 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 359 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 360 DPRINTF(("PCIe INTx Disable set\n")); 361 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 362 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 363 PCI_COMMAND_STATUS_REG, reg); 364 } 365 366 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 367 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 368 &sc->sc_sh, NULL, &sc->sc_sz, 0); 369 if (error != 0) { 370 printf(": can't map mem space\n"); 371 return; 372 } 373 374 /* Install interrupt handler. */ 375 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 376 printf(": can't map interrupt\n"); 377 return; 378 } 379 intrstr = pci_intr_string(sc->sc_pct, ih); 380 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc, 381 sc->sc_dev.dv_xname); 382 if (sc->sc_ih == NULL) { 383 printf(": can't establish interrupt"); 384 if (intrstr != NULL) 385 printf(" at %s", intrstr); 386 printf("\n"); 387 return; 388 } 389 printf(": %s", intrstr); 390 391 /* Read hardware revision and attach. */ 392 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0x1f; 393 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 394 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id)); 395 else 396 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id)); 397 if (error != 0) { 398 printf(": could not attach device\n"); 399 return; 400 } 401 402 if ((error = iwn_hw_prepare(sc)) != 0) { 403 printf(": hardware not ready\n"); 404 return; 405 } 406 407 /* Read MAC address, channels, etc from EEPROM. */ 408 if ((error = iwn_read_eeprom(sc)) != 0) { 409 printf(": could not read EEPROM\n"); 410 return; 411 } 412 413 /* Allocate DMA memory for firmware transfers. */ 414 if ((error = iwn_alloc_fwmem(sc)) != 0) { 415 printf(": could not allocate memory for firmware\n"); 416 return; 417 } 418 419 /* Allocate "Keep Warm" page. */ 420 if ((error = iwn_alloc_kw(sc)) != 0) { 421 printf(": could not allocate keep warm page\n"); 422 goto fail1; 423 } 424 425 /* Allocate ICT table for 5000 Series. */ 426 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 427 (error = iwn_alloc_ict(sc)) != 0) { 428 printf(": could not allocate ICT table\n"); 429 goto fail2; 430 } 431 432 /* Allocate TX scheduler "rings". */ 433 if ((error = iwn_alloc_sched(sc)) != 0) { 434 printf(": could not allocate TX scheduler rings\n"); 435 goto fail3; 436 } 437 438 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 439 for (i = 0; i < sc->ntxqs; i++) { 440 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 441 printf(": could not allocate TX ring %d\n", i); 442 goto fail4; 443 } 444 } 445 446 /* Allocate RX ring. */ 447 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 448 printf(": could not allocate RX ring\n"); 449 goto fail4; 450 } 451 452 /* Clear pending interrupts. */ 453 IWN_WRITE(sc, IWN_INT, 0xffffffff); 454 455 /* Count the number of available chains. */ 456 sc->ntxchains = 457 ((sc->txchainmask >> 2) & 1) + 458 ((sc->txchainmask >> 1) & 1) + 459 ((sc->txchainmask >> 0) & 1); 460 sc->nrxchains = 461 ((sc->rxchainmask >> 2) & 1) + 462 ((sc->rxchainmask >> 1) & 1) + 463 ((sc->rxchainmask >> 0) & 1); 464 printf(", MIMO %dT%dR, %.4s, address %s\n", sc->ntxchains, 465 sc->nrxchains, sc->eeprom_domain, ether_sprintf(ic->ic_myaddr)); 466 467 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 468 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 469 ic->ic_state = IEEE80211_S_INIT; 470 471 /* Set device capabilities. */ 472 ic->ic_caps = 473 IEEE80211_C_WEP | /* WEP */ 474 IEEE80211_C_RSN | /* WPA/RSN */ 475 IEEE80211_C_SCANALL | /* device scans all channels at once */ 476 IEEE80211_C_SCANALLBAND | /* driver scans all bands at once */ 477 IEEE80211_C_MONITOR | /* monitor mode supported */ 478 IEEE80211_C_SHSLOT | /* short slot time supported */ 479 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 480 IEEE80211_C_PMGT; /* power saving supported */ 481 482 /* No optional HT features supported for now, */ 483 ic->ic_htcaps = 0; 484 ic->ic_htxcaps = 0; 485 ic->ic_txbfcaps = 0; 486 ic->ic_aselcaps = 0; 487 ic->ic_ampdu_params = (IEEE80211_AMPDU_PARAM_SS_4 | 0x3 /* 64k */); 488 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 489 ic->ic_caps |= (IEEE80211_C_QOS | IEEE80211_C_TX_AMPDU); 490 /* Set HT capabilities. */ 491 ic->ic_htcaps = IEEE80211_HTCAP_SGI20; 492 #ifdef notyet 493 ic->ic_htcaps |= 494 #if IWN_RBUF_SIZE == 8192 495 IEEE80211_HTCAP_AMSDU7935 | 496 #endif 497 IEEE80211_HTCAP_CBW20_40 | 498 IEEE80211_HTCAP_SGI40; 499 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 500 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 501 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 502 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 503 else 504 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 505 #endif /* notyet */ 506 } 507 508 /* Set supported legacy rates. */ 509 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 510 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 511 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 512 ic->ic_sup_rates[IEEE80211_MODE_11A] = 513 ieee80211_std_rateset_11a; 514 } 515 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 516 /* Set supported HT rates. */ 517 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */ 518 #ifdef notyet 519 if (sc->nrxchains > 1) 520 ic->ic_sup_mcs[1] = 0xff; /* MCS 8-15 */ 521 if (sc->nrxchains > 2) 522 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 523 #endif 524 } 525 526 /* IBSS channel undefined for now. */ 527 ic->ic_ibss_chan = &ic->ic_channels[0]; 528 529 ifp->if_softc = sc; 530 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 531 ifp->if_ioctl = iwn_ioctl; 532 ifp->if_start = iwn_start; 533 ifp->if_watchdog = iwn_watchdog; 534 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 535 536 if_attach(ifp); 537 ieee80211_ifattach(ifp); 538 ic->ic_node_alloc = iwn_node_alloc; 539 ic->ic_bgscan_start = iwn_bgscan; 540 ic->ic_newassoc = iwn_newassoc; 541 ic->ic_updateedca = iwn_updateedca; 542 ic->ic_set_key = iwn_set_key; 543 ic->ic_delete_key = iwn_delete_key; 544 ic->ic_updateprot = iwn_updateprot; 545 ic->ic_updateslot = iwn_updateslot; 546 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 547 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 548 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 549 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 550 551 /* Override 802.11 state transition machine. */ 552 sc->sc_newstate = ic->ic_newstate; 553 ic->ic_newstate = iwn_newstate; 554 ieee80211_media_init(ifp, iwn_media_change, ieee80211_media_status); 555 556 sc->amrr.amrr_min_success_threshold = 1; 557 sc->amrr.amrr_max_success_threshold = 15; 558 559 #if NBPFILTER > 0 560 iwn_radiotap_attach(sc); 561 #endif 562 timeout_set(&sc->calib_to, iwn_calib_timeout, sc); 563 rw_init(&sc->sc_rwlock, "iwnlock"); 564 task_set(&sc->init_task, iwn_init_task, sc); 565 return; 566 567 /* Free allocated memory if something failed during attachment. */ 568 fail4: while (--i >= 0) 569 iwn_free_tx_ring(sc, &sc->txq[i]); 570 iwn_free_sched(sc); 571 fail3: if (sc->ict != NULL) 572 iwn_free_ict(sc); 573 fail2: iwn_free_kw(sc); 574 fail1: iwn_free_fwmem(sc); 575 } 576 577 int 578 iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid) 579 { 580 struct iwn_ops *ops = &sc->ops; 581 582 ops->load_firmware = iwn4965_load_firmware; 583 ops->read_eeprom = iwn4965_read_eeprom; 584 ops->post_alive = iwn4965_post_alive; 585 ops->nic_config = iwn4965_nic_config; 586 ops->reset_sched = iwn4965_reset_sched; 587 ops->update_sched = iwn4965_update_sched; 588 ops->get_temperature = iwn4965_get_temperature; 589 ops->get_rssi = iwn4965_get_rssi; 590 ops->set_txpower = iwn4965_set_txpower; 591 ops->init_gains = iwn4965_init_gains; 592 ops->set_gains = iwn4965_set_gains; 593 ops->add_node = iwn4965_add_node; 594 ops->tx_done = iwn4965_tx_done; 595 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 596 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 597 sc->ntxqs = IWN4965_NTXQUEUES; 598 sc->first_agg_txq = IWN4965_FIRST_AGG_TXQUEUE; 599 sc->ndmachnls = IWN4965_NDMACHNLS; 600 sc->broadcast_id = IWN4965_ID_BROADCAST; 601 sc->rxonsz = IWN4965_RXONSZ; 602 sc->schedsz = IWN4965_SCHEDSZ; 603 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 604 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 605 sc->fwsz = IWN4965_FWSZ; 606 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 607 sc->limits = &iwn4965_sensitivity_limits; 608 sc->fwname = "iwn-4965"; 609 /* Override chains masks, ROM is known to be broken. */ 610 sc->txchainmask = IWN_ANT_AB; 611 sc->rxchainmask = IWN_ANT_ABC; 612 613 return 0; 614 } 615 616 int 617 iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid) 618 { 619 struct iwn_ops *ops = &sc->ops; 620 621 ops->load_firmware = iwn5000_load_firmware; 622 ops->read_eeprom = iwn5000_read_eeprom; 623 ops->post_alive = iwn5000_post_alive; 624 ops->nic_config = iwn5000_nic_config; 625 ops->reset_sched = iwn5000_reset_sched; 626 ops->update_sched = iwn5000_update_sched; 627 ops->get_temperature = iwn5000_get_temperature; 628 ops->get_rssi = iwn5000_get_rssi; 629 ops->set_txpower = iwn5000_set_txpower; 630 ops->init_gains = iwn5000_init_gains; 631 ops->set_gains = iwn5000_set_gains; 632 ops->add_node = iwn5000_add_node; 633 ops->tx_done = iwn5000_tx_done; 634 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 635 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 636 sc->ntxqs = IWN5000_NTXQUEUES; 637 sc->first_agg_txq = IWN5000_FIRST_AGG_TXQUEUE; 638 sc->ndmachnls = IWN5000_NDMACHNLS; 639 sc->broadcast_id = IWN5000_ID_BROADCAST; 640 sc->rxonsz = IWN5000_RXONSZ; 641 sc->schedsz = IWN5000_SCHEDSZ; 642 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 643 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 644 sc->fwsz = IWN5000_FWSZ; 645 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 646 647 switch (sc->hw_type) { 648 case IWN_HW_REV_TYPE_5100: 649 sc->limits = &iwn5000_sensitivity_limits; 650 sc->fwname = "iwn-5000"; 651 /* Override chains masks, ROM is known to be broken. */ 652 sc->txchainmask = IWN_ANT_B; 653 sc->rxchainmask = IWN_ANT_AB; 654 break; 655 case IWN_HW_REV_TYPE_5150: 656 sc->limits = &iwn5150_sensitivity_limits; 657 sc->fwname = "iwn-5150"; 658 break; 659 case IWN_HW_REV_TYPE_5300: 660 case IWN_HW_REV_TYPE_5350: 661 sc->limits = &iwn5000_sensitivity_limits; 662 sc->fwname = "iwn-5000"; 663 break; 664 case IWN_HW_REV_TYPE_1000: 665 sc->limits = &iwn1000_sensitivity_limits; 666 sc->fwname = "iwn-1000"; 667 break; 668 case IWN_HW_REV_TYPE_6000: 669 sc->limits = &iwn6000_sensitivity_limits; 670 sc->fwname = "iwn-6000"; 671 if (pid == PCI_PRODUCT_INTEL_WL_6200_1 || 672 pid == PCI_PRODUCT_INTEL_WL_6200_2) { 673 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 674 /* Override chains masks, ROM is known to be broken. */ 675 sc->txchainmask = IWN_ANT_BC; 676 sc->rxchainmask = IWN_ANT_BC; 677 } 678 break; 679 case IWN_HW_REV_TYPE_6050: 680 sc->limits = &iwn6000_sensitivity_limits; 681 sc->fwname = "iwn-6050"; 682 break; 683 case IWN_HW_REV_TYPE_6005: 684 sc->limits = &iwn6000_sensitivity_limits; 685 if (pid != PCI_PRODUCT_INTEL_WL_6005_1 && 686 pid != PCI_PRODUCT_INTEL_WL_6005_2) { 687 sc->fwname = "iwn-6030"; 688 sc->sc_flags |= IWN_FLAG_ADV_BT_COEX; 689 } else 690 sc->fwname = "iwn-6005"; 691 break; 692 case IWN_HW_REV_TYPE_2030: 693 sc->limits = &iwn2000_sensitivity_limits; 694 sc->fwname = "iwn-2030"; 695 sc->sc_flags |= IWN_FLAG_ADV_BT_COEX; 696 break; 697 case IWN_HW_REV_TYPE_2000: 698 sc->limits = &iwn2000_sensitivity_limits; 699 sc->fwname = "iwn-2000"; 700 break; 701 case IWN_HW_REV_TYPE_135: 702 sc->limits = &iwn2000_sensitivity_limits; 703 sc->fwname = "iwn-135"; 704 sc->sc_flags |= IWN_FLAG_ADV_BT_COEX; 705 break; 706 case IWN_HW_REV_TYPE_105: 707 sc->limits = &iwn2000_sensitivity_limits; 708 sc->fwname = "iwn-105"; 709 break; 710 default: 711 printf(": adapter type %d not supported\n", sc->hw_type); 712 return ENOTSUP; 713 } 714 return 0; 715 } 716 717 #if NBPFILTER > 0 718 /* 719 * Attach the interface to 802.11 radiotap. 720 */ 721 void 722 iwn_radiotap_attach(struct iwn_softc *sc) 723 { 724 bpfattach(&sc->sc_drvbpf, &sc->sc_ic.ic_if, DLT_IEEE802_11_RADIO, 725 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 726 727 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 728 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 729 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 730 731 sc->sc_txtap_len = sizeof sc->sc_txtapu; 732 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 733 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 734 } 735 #endif 736 737 int 738 iwn_detach(struct device *self, int flags) 739 { 740 struct iwn_softc *sc = (struct iwn_softc *)self; 741 struct ifnet *ifp = &sc->sc_ic.ic_if; 742 int qid; 743 744 timeout_del(&sc->calib_to); 745 task_del(systq, &sc->init_task); 746 747 /* Uninstall interrupt handler. */ 748 if (sc->sc_ih != NULL) 749 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 750 751 /* Free DMA resources. */ 752 iwn_free_rx_ring(sc, &sc->rxq); 753 for (qid = 0; qid < sc->ntxqs; qid++) 754 iwn_free_tx_ring(sc, &sc->txq[qid]); 755 iwn_free_sched(sc); 756 iwn_free_kw(sc); 757 if (sc->ict != NULL) 758 iwn_free_ict(sc); 759 iwn_free_fwmem(sc); 760 761 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 762 763 ieee80211_ifdetach(ifp); 764 if_detach(ifp); 765 766 return 0; 767 } 768 769 int 770 iwn_activate(struct device *self, int act) 771 { 772 struct iwn_softc *sc = (struct iwn_softc *)self; 773 struct ifnet *ifp = &sc->sc_ic.ic_if; 774 775 switch (act) { 776 case DVACT_SUSPEND: 777 if (ifp->if_flags & IFF_RUNNING) 778 iwn_stop(ifp); 779 break; 780 case DVACT_WAKEUP: 781 iwn_wakeup(sc); 782 break; 783 } 784 785 return 0; 786 } 787 788 void 789 iwn_wakeup(struct iwn_softc *sc) 790 { 791 pcireg_t reg; 792 793 /* Clear device-specific "PCI retry timeout" register (41h). */ 794 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 795 if (reg & 0xff00) 796 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 797 iwn_init_task(sc); 798 } 799 800 void 801 iwn_init_task(void *arg1) 802 { 803 struct iwn_softc *sc = arg1; 804 struct ifnet *ifp = &sc->sc_ic.ic_if; 805 int s; 806 807 rw_enter_write(&sc->sc_rwlock); 808 s = splnet(); 809 810 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 811 iwn_init(ifp); 812 813 splx(s); 814 rw_exit_write(&sc->sc_rwlock); 815 } 816 817 int 818 iwn_nic_lock(struct iwn_softc *sc) 819 { 820 int ntries; 821 822 /* Request exclusive access to NIC. */ 823 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 824 825 /* Spin until we actually get the lock. */ 826 for (ntries = 0; ntries < 1000; ntries++) { 827 if ((IWN_READ(sc, IWN_GP_CNTRL) & 828 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 829 IWN_GP_CNTRL_MAC_ACCESS_ENA) 830 return 0; 831 DELAY(10); 832 } 833 return ETIMEDOUT; 834 } 835 836 static __inline void 837 iwn_nic_unlock(struct iwn_softc *sc) 838 { 839 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 840 } 841 842 static __inline uint32_t 843 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 844 { 845 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 846 IWN_BARRIER_READ_WRITE(sc); 847 return IWN_READ(sc, IWN_PRPH_RDATA); 848 } 849 850 static __inline void 851 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 852 { 853 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 854 IWN_BARRIER_WRITE(sc); 855 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 856 } 857 858 static __inline void 859 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 860 { 861 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 862 } 863 864 static __inline void 865 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 866 { 867 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 868 } 869 870 static __inline void 871 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 872 const uint32_t *data, int count) 873 { 874 for (; count > 0; count--, data++, addr += 4) 875 iwn_prph_write(sc, addr, *data); 876 } 877 878 static __inline uint32_t 879 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 880 { 881 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 882 IWN_BARRIER_READ_WRITE(sc); 883 return IWN_READ(sc, IWN_MEM_RDATA); 884 } 885 886 static __inline void 887 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 888 { 889 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 890 IWN_BARRIER_WRITE(sc); 891 IWN_WRITE(sc, IWN_MEM_WDATA, data); 892 } 893 894 static __inline void 895 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 896 { 897 uint32_t tmp; 898 899 tmp = iwn_mem_read(sc, addr & ~3); 900 if (addr & 3) 901 tmp = (tmp & 0x0000ffff) | data << 16; 902 else 903 tmp = (tmp & 0xffff0000) | data; 904 iwn_mem_write(sc, addr & ~3, tmp); 905 } 906 907 static __inline void 908 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 909 int count) 910 { 911 for (; count > 0; count--, addr += 4) 912 *data++ = iwn_mem_read(sc, addr); 913 } 914 915 static __inline void 916 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 917 int count) 918 { 919 for (; count > 0; count--, addr += 4) 920 iwn_mem_write(sc, addr, val); 921 } 922 923 int 924 iwn_eeprom_lock(struct iwn_softc *sc) 925 { 926 int i, ntries; 927 928 for (i = 0; i < 100; i++) { 929 /* Request exclusive access to EEPROM. */ 930 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 931 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 932 933 /* Spin until we actually get the lock. */ 934 for (ntries = 0; ntries < 100; ntries++) { 935 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 936 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 937 return 0; 938 DELAY(10); 939 } 940 } 941 return ETIMEDOUT; 942 } 943 944 static __inline void 945 iwn_eeprom_unlock(struct iwn_softc *sc) 946 { 947 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 948 } 949 950 /* 951 * Initialize access by host to One Time Programmable ROM. 952 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 953 */ 954 int 955 iwn_init_otprom(struct iwn_softc *sc) 956 { 957 uint16_t prev, base, next; 958 int count, error; 959 960 /* Wait for clock stabilization before accessing prph. */ 961 if ((error = iwn_clock_wait(sc)) != 0) 962 return error; 963 964 if ((error = iwn_nic_lock(sc)) != 0) 965 return error; 966 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 967 DELAY(5); 968 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 969 iwn_nic_unlock(sc); 970 971 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 972 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 973 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 974 IWN_RESET_LINK_PWR_MGMT_DIS); 975 } 976 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 977 /* Clear ECC status. */ 978 IWN_SETBITS(sc, IWN_OTP_GP, 979 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 980 981 /* 982 * Find the block before last block (contains the EEPROM image) 983 * for HW without OTP shadow RAM. 984 */ 985 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 986 /* Switch to absolute addressing mode. */ 987 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 988 base = 0; 989 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 990 error = iwn_read_prom_data(sc, base, &next, 2); 991 if (error != 0) 992 return error; 993 if (next == 0) /* End of linked-list. */ 994 break; 995 prev = base; 996 base = letoh16(next); 997 } 998 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 999 return EIO; 1000 /* Skip "next" word. */ 1001 sc->prom_base = prev + 1; 1002 } 1003 return 0; 1004 } 1005 1006 int 1007 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1008 { 1009 uint8_t *out = data; 1010 uint32_t val, tmp; 1011 int ntries; 1012 1013 addr += sc->prom_base; 1014 for (; count > 0; count -= 2, addr++) { 1015 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1016 for (ntries = 0; ntries < 10; ntries++) { 1017 val = IWN_READ(sc, IWN_EEPROM); 1018 if (val & IWN_EEPROM_READ_VALID) 1019 break; 1020 DELAY(5); 1021 } 1022 if (ntries == 10) { 1023 printf("%s: timeout reading ROM at 0x%x\n", 1024 sc->sc_dev.dv_xname, addr); 1025 return ETIMEDOUT; 1026 } 1027 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1028 /* OTPROM, check for ECC errors. */ 1029 tmp = IWN_READ(sc, IWN_OTP_GP); 1030 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1031 printf("%s: OTPROM ECC error at 0x%x\n", 1032 sc->sc_dev.dv_xname, addr); 1033 return EIO; 1034 } 1035 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1036 /* Correctable ECC error, clear bit. */ 1037 IWN_SETBITS(sc, IWN_OTP_GP, 1038 IWN_OTP_GP_ECC_CORR_STTS); 1039 } 1040 } 1041 *out++ = val >> 16; 1042 if (count > 1) 1043 *out++ = val >> 24; 1044 } 1045 return 0; 1046 } 1047 1048 int 1049 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1050 bus_size_t size, bus_size_t alignment) 1051 { 1052 int nsegs, error; 1053 1054 dma->tag = tag; 1055 dma->size = size; 1056 1057 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1058 &dma->map); 1059 if (error != 0) 1060 goto fail; 1061 1062 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1063 BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1064 if (error != 0) 1065 goto fail; 1066 1067 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1068 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 1069 if (error != 0) 1070 goto fail; 1071 1072 error = bus_dmamap_load_raw(tag, dma->map, &dma->seg, 1, size, 1073 BUS_DMA_NOWAIT); 1074 if (error != 0) 1075 goto fail; 1076 1077 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1078 1079 dma->paddr = dma->map->dm_segs[0].ds_addr; 1080 if (kvap != NULL) 1081 *kvap = dma->vaddr; 1082 1083 return 0; 1084 1085 fail: iwn_dma_contig_free(dma); 1086 return error; 1087 } 1088 1089 void 1090 iwn_dma_contig_free(struct iwn_dma_info *dma) 1091 { 1092 if (dma->map != NULL) { 1093 if (dma->vaddr != NULL) { 1094 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1095 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1096 bus_dmamap_unload(dma->tag, dma->map); 1097 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1098 bus_dmamem_free(dma->tag, &dma->seg, 1); 1099 dma->vaddr = NULL; 1100 } 1101 bus_dmamap_destroy(dma->tag, dma->map); 1102 dma->map = NULL; 1103 } 1104 } 1105 1106 int 1107 iwn_alloc_sched(struct iwn_softc *sc) 1108 { 1109 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1110 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1111 (void **)&sc->sched, sc->schedsz, 1024); 1112 } 1113 1114 void 1115 iwn_free_sched(struct iwn_softc *sc) 1116 { 1117 iwn_dma_contig_free(&sc->sched_dma); 1118 } 1119 1120 int 1121 iwn_alloc_kw(struct iwn_softc *sc) 1122 { 1123 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1124 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1125 4096); 1126 } 1127 1128 void 1129 iwn_free_kw(struct iwn_softc *sc) 1130 { 1131 iwn_dma_contig_free(&sc->kw_dma); 1132 } 1133 1134 int 1135 iwn_alloc_ict(struct iwn_softc *sc) 1136 { 1137 /* ICT table must be aligned on a 4KB boundary. */ 1138 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1139 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1140 } 1141 1142 void 1143 iwn_free_ict(struct iwn_softc *sc) 1144 { 1145 iwn_dma_contig_free(&sc->ict_dma); 1146 } 1147 1148 int 1149 iwn_alloc_fwmem(struct iwn_softc *sc) 1150 { 1151 /* Must be aligned on a 16-byte boundary. */ 1152 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1153 sc->fwsz, 16); 1154 } 1155 1156 void 1157 iwn_free_fwmem(struct iwn_softc *sc) 1158 { 1159 iwn_dma_contig_free(&sc->fw_dma); 1160 } 1161 1162 int 1163 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1164 { 1165 bus_size_t size; 1166 int i, error; 1167 1168 ring->cur = 0; 1169 1170 /* Allocate RX descriptors (256-byte aligned). */ 1171 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1172 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1173 (void **)&ring->desc, size, 256); 1174 if (error != 0) { 1175 printf("%s: could not allocate RX ring DMA memory\n", 1176 sc->sc_dev.dv_xname); 1177 goto fail; 1178 } 1179 1180 /* Allocate RX status area (16-byte aligned). */ 1181 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1182 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1183 if (error != 0) { 1184 printf("%s: could not allocate RX status DMA memory\n", 1185 sc->sc_dev.dv_xname); 1186 goto fail; 1187 } 1188 1189 /* 1190 * Allocate and map RX buffers. 1191 */ 1192 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1193 struct iwn_rx_data *data = &ring->data[i]; 1194 1195 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1196 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1197 &data->map); 1198 if (error != 0) { 1199 printf("%s: could not create RX buf DMA map\n", 1200 sc->sc_dev.dv_xname); 1201 goto fail; 1202 } 1203 1204 data->m = MCLGETL(NULL, M_DONTWAIT, IWN_RBUF_SIZE); 1205 if (data->m == NULL) { 1206 printf("%s: could not allocate RX mbuf\n", 1207 sc->sc_dev.dv_xname); 1208 error = ENOBUFS; 1209 goto fail; 1210 } 1211 1212 error = bus_dmamap_load(sc->sc_dmat, data->map, 1213 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1214 BUS_DMA_NOWAIT | BUS_DMA_READ); 1215 if (error != 0) { 1216 printf("%s: can't map mbuf (error %d)\n", 1217 sc->sc_dev.dv_xname, error); 1218 goto fail; 1219 } 1220 1221 /* Set physical address of RX buffer (256-byte aligned). */ 1222 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1223 } 1224 1225 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1226 BUS_DMASYNC_PREWRITE); 1227 1228 return 0; 1229 1230 fail: iwn_free_rx_ring(sc, ring); 1231 return error; 1232 } 1233 1234 void 1235 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1236 { 1237 int ntries; 1238 1239 if (iwn_nic_lock(sc) == 0) { 1240 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1241 for (ntries = 0; ntries < 1000; ntries++) { 1242 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1243 IWN_FH_RX_STATUS_IDLE) 1244 break; 1245 DELAY(10); 1246 } 1247 iwn_nic_unlock(sc); 1248 } 1249 ring->cur = 0; 1250 sc->last_rx_valid = 0; 1251 } 1252 1253 void 1254 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1255 { 1256 int i; 1257 1258 iwn_dma_contig_free(&ring->desc_dma); 1259 iwn_dma_contig_free(&ring->stat_dma); 1260 1261 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1262 struct iwn_rx_data *data = &ring->data[i]; 1263 1264 if (data->m != NULL) { 1265 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1266 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1267 bus_dmamap_unload(sc->sc_dmat, data->map); 1268 m_freem(data->m); 1269 } 1270 if (data->map != NULL) 1271 bus_dmamap_destroy(sc->sc_dmat, data->map); 1272 } 1273 } 1274 1275 int 1276 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1277 { 1278 bus_addr_t paddr; 1279 bus_size_t size; 1280 int i, error; 1281 1282 ring->qid = qid; 1283 ring->queued = 0; 1284 ring->cur = 0; 1285 1286 /* Allocate TX descriptors (256-byte aligned). */ 1287 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1288 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1289 (void **)&ring->desc, size, 256); 1290 if (error != 0) { 1291 printf("%s: could not allocate TX ring DMA memory\n", 1292 sc->sc_dev.dv_xname); 1293 goto fail; 1294 } 1295 1296 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1297 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1298 (void **)&ring->cmd, size, 4); 1299 if (error != 0) { 1300 printf("%s: could not allocate TX cmd DMA memory\n", 1301 sc->sc_dev.dv_xname); 1302 goto fail; 1303 } 1304 1305 paddr = ring->cmd_dma.paddr; 1306 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1307 struct iwn_tx_data *data = &ring->data[i]; 1308 1309 data->cmd_paddr = paddr; 1310 data->scratch_paddr = paddr + 12; 1311 paddr += sizeof (struct iwn_tx_cmd); 1312 1313 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1314 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1315 &data->map); 1316 if (error != 0) { 1317 printf("%s: could not create TX buf DMA map\n", 1318 sc->sc_dev.dv_xname); 1319 goto fail; 1320 } 1321 } 1322 return 0; 1323 1324 fail: iwn_free_tx_ring(sc, ring); 1325 return error; 1326 } 1327 1328 void 1329 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1330 { 1331 int i; 1332 1333 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1334 struct iwn_tx_data *data = &ring->data[i]; 1335 1336 if (data->m != NULL) { 1337 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1338 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1339 bus_dmamap_unload(sc->sc_dmat, data->map); 1340 m_freem(data->m); 1341 data->m = NULL; 1342 } 1343 } 1344 /* Clear TX descriptors. */ 1345 memset(ring->desc, 0, ring->desc_dma.size); 1346 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1347 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1348 sc->qfullmsk &= ~(1 << ring->qid); 1349 ring->queued = 0; 1350 ring->cur = 0; 1351 } 1352 1353 void 1354 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1355 { 1356 int i; 1357 1358 iwn_dma_contig_free(&ring->desc_dma); 1359 iwn_dma_contig_free(&ring->cmd_dma); 1360 1361 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1362 struct iwn_tx_data *data = &ring->data[i]; 1363 1364 if (data->m != NULL) { 1365 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1366 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1367 bus_dmamap_unload(sc->sc_dmat, data->map); 1368 m_freem(data->m); 1369 } 1370 if (data->map != NULL) 1371 bus_dmamap_destroy(sc->sc_dmat, data->map); 1372 } 1373 } 1374 1375 void 1376 iwn5000_ict_reset(struct iwn_softc *sc) 1377 { 1378 /* Disable interrupts. */ 1379 IWN_WRITE(sc, IWN_INT_MASK, 0); 1380 1381 /* Reset ICT table. */ 1382 memset(sc->ict, 0, IWN_ICT_SIZE); 1383 sc->ict_cur = 0; 1384 1385 /* Set physical address of ICT table (4KB aligned). */ 1386 DPRINTF(("enabling ICT\n")); 1387 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1388 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1389 1390 /* Enable periodic RX interrupt. */ 1391 sc->int_mask |= IWN_INT_RX_PERIODIC; 1392 /* Switch to ICT interrupt mode in driver. */ 1393 sc->sc_flags |= IWN_FLAG_USE_ICT; 1394 1395 /* Re-enable interrupts. */ 1396 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1397 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1398 } 1399 1400 int 1401 iwn_read_eeprom(struct iwn_softc *sc) 1402 { 1403 struct iwn_ops *ops = &sc->ops; 1404 struct ieee80211com *ic = &sc->sc_ic; 1405 uint16_t val; 1406 int error; 1407 1408 /* Check whether adapter has an EEPROM or an OTPROM. */ 1409 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1410 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1411 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1412 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1413 "OTPROM" : "EEPROM")); 1414 1415 /* Adapter has to be powered on for EEPROM access to work. */ 1416 if ((error = iwn_apm_init(sc)) != 0) { 1417 printf("%s: could not power ON adapter\n", 1418 sc->sc_dev.dv_xname); 1419 return error; 1420 } 1421 1422 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1423 printf("%s: bad ROM signature\n", sc->sc_dev.dv_xname); 1424 return EIO; 1425 } 1426 if ((error = iwn_eeprom_lock(sc)) != 0) { 1427 printf("%s: could not lock ROM (error=%d)\n", 1428 sc->sc_dev.dv_xname, error); 1429 return error; 1430 } 1431 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1432 if ((error = iwn_init_otprom(sc)) != 0) { 1433 printf("%s: could not initialize OTPROM\n", 1434 sc->sc_dev.dv_xname); 1435 return error; 1436 } 1437 } 1438 1439 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1440 DPRINTF(("SKU capabilities=0x%04x\n", letoh16(val))); 1441 /* Check if HT support is bonded out. */ 1442 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1443 sc->sc_flags |= IWN_FLAG_HAS_11N; 1444 1445 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1446 sc->rfcfg = letoh16(val); 1447 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1448 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1449 if (sc->txchainmask == 0) 1450 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1451 if (sc->rxchainmask == 0) 1452 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1453 1454 /* Read MAC address. */ 1455 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1456 1457 /* Read adapter-specific information from EEPROM. */ 1458 ops->read_eeprom(sc); 1459 1460 iwn_apm_stop(sc); /* Power OFF adapter. */ 1461 1462 iwn_eeprom_unlock(sc); 1463 return 0; 1464 } 1465 1466 void 1467 iwn4965_read_eeprom(struct iwn_softc *sc) 1468 { 1469 uint32_t addr; 1470 uint16_t val; 1471 int i; 1472 1473 /* Read regulatory domain (4 ASCII characters). */ 1474 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1475 1476 /* Read the list of authorized channels (20MHz ones only). */ 1477 for (i = 0; i < 5; i++) { 1478 addr = iwn4965_regulatory_bands[i]; 1479 iwn_read_eeprom_channels(sc, i, addr); 1480 } 1481 1482 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1483 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1484 sc->maxpwr2GHz = val & 0xff; 1485 sc->maxpwr5GHz = val >> 8; 1486 /* Check that EEPROM values are within valid range. */ 1487 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1488 sc->maxpwr5GHz = 38; 1489 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1490 sc->maxpwr2GHz = 38; 1491 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1492 1493 /* Read samples for each TX power group. */ 1494 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1495 sizeof sc->bands); 1496 1497 /* Read voltage at which samples were taken. */ 1498 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1499 sc->eeprom_voltage = (int16_t)letoh16(val); 1500 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1501 1502 #ifdef IWN_DEBUG 1503 /* Print samples. */ 1504 if (iwn_debug > 0) { 1505 for (i = 0; i < IWN_NBANDS; i++) 1506 iwn4965_print_power_group(sc, i); 1507 } 1508 #endif 1509 } 1510 1511 #ifdef IWN_DEBUG 1512 void 1513 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1514 { 1515 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1516 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1517 int j, c; 1518 1519 printf("===band %d===\n", i); 1520 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1521 printf("chan1 num=%d\n", chans[0].num); 1522 for (c = 0; c < 2; c++) { 1523 for (j = 0; j < IWN_NSAMPLES; j++) { 1524 printf("chain %d, sample %d: temp=%d gain=%d " 1525 "power=%d pa_det=%d\n", c, j, 1526 chans[0].samples[c][j].temp, 1527 chans[0].samples[c][j].gain, 1528 chans[0].samples[c][j].power, 1529 chans[0].samples[c][j].pa_det); 1530 } 1531 } 1532 printf("chan2 num=%d\n", chans[1].num); 1533 for (c = 0; c < 2; c++) { 1534 for (j = 0; j < IWN_NSAMPLES; j++) { 1535 printf("chain %d, sample %d: temp=%d gain=%d " 1536 "power=%d pa_det=%d\n", c, j, 1537 chans[1].samples[c][j].temp, 1538 chans[1].samples[c][j].gain, 1539 chans[1].samples[c][j].power, 1540 chans[1].samples[c][j].pa_det); 1541 } 1542 } 1543 } 1544 #endif 1545 1546 void 1547 iwn5000_read_eeprom(struct iwn_softc *sc) 1548 { 1549 struct iwn5000_eeprom_calib_hdr hdr; 1550 int32_t volt; 1551 uint32_t base, addr; 1552 uint16_t val; 1553 int i; 1554 1555 /* Read regulatory domain (4 ASCII characters). */ 1556 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1557 base = letoh16(val); 1558 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1559 sc->eeprom_domain, 4); 1560 1561 /* Read the list of authorized channels (20MHz ones only). */ 1562 for (i = 0; i < 5; i++) { 1563 addr = base + iwn5000_regulatory_bands[i]; 1564 iwn_read_eeprom_channels(sc, i, addr); 1565 } 1566 1567 /* Read enhanced TX power information for 6000 Series. */ 1568 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1569 iwn_read_eeprom_enhinfo(sc); 1570 1571 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1572 base = letoh16(val); 1573 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1574 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1575 hdr.version, hdr.pa_type, letoh16(hdr.volt))); 1576 sc->calib_ver = hdr.version; 1577 1578 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 1579 sc->hw_type == IWN_HW_REV_TYPE_2000 || 1580 sc->hw_type == IWN_HW_REV_TYPE_135 || 1581 sc->hw_type == IWN_HW_REV_TYPE_105) { 1582 sc->eeprom_voltage = letoh16(hdr.volt); 1583 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1584 sc->eeprom_temp = letoh16(val); 1585 iwn_read_prom_data(sc, base + IWN2000_EEPROM_RAWTEMP, &val, 2); 1586 sc->eeprom_rawtemp = letoh16(val); 1587 } 1588 1589 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1590 /* Compute temperature offset. */ 1591 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1592 sc->eeprom_temp = letoh16(val); 1593 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1594 volt = letoh16(val); 1595 sc->temp_off = sc->eeprom_temp - (volt / -5); 1596 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1597 sc->eeprom_temp, volt, sc->temp_off)); 1598 } else { 1599 /* Read crystal calibration. */ 1600 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1601 &sc->eeprom_crystal, sizeof (uint32_t)); 1602 DPRINTF(("crystal calibration 0x%08x\n", 1603 letoh32(sc->eeprom_crystal))); 1604 } 1605 } 1606 1607 void 1608 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1609 { 1610 struct ieee80211com *ic = &sc->sc_ic; 1611 const struct iwn_chan_band *band = &iwn_bands[n]; 1612 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1613 uint8_t chan; 1614 int i; 1615 1616 iwn_read_prom_data(sc, addr, channels, 1617 band->nchan * sizeof (struct iwn_eeprom_chan)); 1618 1619 for (i = 0; i < band->nchan; i++) { 1620 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1621 continue; 1622 1623 chan = band->chan[i]; 1624 1625 if (n == 0) { /* 2GHz band */ 1626 ic->ic_channels[chan].ic_freq = 1627 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1628 ic->ic_channels[chan].ic_flags = 1629 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1630 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1631 1632 } else { /* 5GHz band */ 1633 /* 1634 * Some adapters support channels 7, 8, 11 and 12 1635 * both in the 2GHz and 4.9GHz bands. 1636 * Because of limitations in our net80211 layer, 1637 * we don't support them in the 4.9GHz band. 1638 */ 1639 if (chan <= 14) 1640 continue; 1641 1642 ic->ic_channels[chan].ic_freq = 1643 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1644 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1645 /* We have at least one valid 5GHz channel. */ 1646 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1647 } 1648 1649 /* Is active scan allowed on this channel? */ 1650 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1651 ic->ic_channels[chan].ic_flags |= 1652 IEEE80211_CHAN_PASSIVE; 1653 } 1654 1655 /* Save maximum allowed TX power for this channel. */ 1656 sc->maxpwr[chan] = channels[i].maxpwr; 1657 1658 if (sc->sc_flags & IWN_FLAG_HAS_11N) 1659 ic->ic_channels[chan].ic_flags |= IEEE80211_CHAN_HT; 1660 1661 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1662 chan, channels[i].flags, sc->maxpwr[chan])); 1663 } 1664 } 1665 1666 void 1667 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1668 { 1669 struct iwn_eeprom_enhinfo enhinfo[35]; 1670 uint16_t val, base; 1671 int8_t maxpwr; 1672 int i; 1673 1674 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1675 base = letoh16(val); 1676 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1677 enhinfo, sizeof enhinfo); 1678 1679 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1680 for (i = 0; i < nitems(enhinfo); i++) { 1681 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1682 continue; /* Skip invalid entries. */ 1683 1684 maxpwr = 0; 1685 if (sc->txchainmask & IWN_ANT_A) 1686 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1687 if (sc->txchainmask & IWN_ANT_B) 1688 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1689 if (sc->txchainmask & IWN_ANT_C) 1690 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1691 if (sc->ntxchains == 2) 1692 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1693 else if (sc->ntxchains == 3) 1694 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1695 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1696 1697 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1698 sc->enh_maxpwr[i] = maxpwr; 1699 } 1700 } 1701 1702 struct ieee80211_node * 1703 iwn_node_alloc(struct ieee80211com *ic) 1704 { 1705 return malloc(sizeof (struct iwn_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1706 } 1707 1708 void 1709 iwn_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 1710 { 1711 struct iwn_softc *sc = ic->ic_if.if_softc; 1712 struct iwn_node *wn = (void *)ni; 1713 uint8_t rate; 1714 int ridx, i; 1715 1716 if ((ni->ni_flags & IEEE80211_NODE_HT) == 0) 1717 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1718 1719 /* Start at lowest available bit-rate, AMRR/MiRA will raise. */ 1720 ni->ni_txrate = 0; 1721 ni->ni_txmcs = 0; 1722 1723 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1724 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1725 /* Map 802.11 rate to HW rate index. */ 1726 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 1727 if (iwn_rates[ridx].plcp != IWN_PLCP_INVALID && 1728 iwn_rates[ridx].rate == rate) 1729 break; 1730 } 1731 wn->ridx[i] = ridx; 1732 } 1733 } 1734 1735 int 1736 iwn_media_change(struct ifnet *ifp) 1737 { 1738 struct iwn_softc *sc = ifp->if_softc; 1739 struct ieee80211com *ic = &sc->sc_ic; 1740 uint8_t rate, ridx; 1741 int error; 1742 1743 error = ieee80211_media_change(ifp); 1744 if (error != ENETRESET) 1745 return error; 1746 1747 if (ic->ic_fixed_mcs != -1) 1748 sc->fixed_ridx = iwn_mcs2ridx[ic->ic_fixed_mcs]; 1749 if (ic->ic_fixed_rate != -1) { 1750 rate = ic->ic_sup_rates[ic->ic_curmode]. 1751 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1752 /* Map 802.11 rate to HW rate index. */ 1753 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1754 if (iwn_rates[ridx].plcp != IWN_PLCP_INVALID && 1755 iwn_rates[ridx].rate == rate) 1756 break; 1757 sc->fixed_ridx = ridx; 1758 } 1759 1760 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1761 (IFF_UP | IFF_RUNNING)) { 1762 iwn_stop(ifp); 1763 error = iwn_init(ifp); 1764 } 1765 return error; 1766 } 1767 1768 int 1769 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1770 { 1771 struct ifnet *ifp = &ic->ic_if; 1772 struct iwn_softc *sc = ifp->if_softc; 1773 struct ieee80211_node *ni = ic->ic_bss; 1774 int error; 1775 1776 if (ic->ic_state == IEEE80211_S_RUN) { 1777 if (nstate == IEEE80211_S_SCAN) { 1778 /* 1779 * During RUN->SCAN we don't call sc_newstate() so 1780 * we must stop A-MPDU Tx ourselves in this case. 1781 */ 1782 ieee80211_stop_ampdu_tx(ic, ni, -1); 1783 ieee80211_ba_del(ni); 1784 } 1785 timeout_del(&sc->calib_to); 1786 sc->calib.state = IWN_CALIB_STATE_INIT; 1787 if (sc->sc_flags & IWN_FLAG_BGSCAN) 1788 iwn_scan_abort(sc); 1789 } 1790 1791 if (ic->ic_state == IEEE80211_S_SCAN) { 1792 if (nstate == IEEE80211_S_SCAN) { 1793 if (sc->sc_flags & IWN_FLAG_SCANNING) 1794 return 0; 1795 } else 1796 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1797 /* Turn LED off when leaving scan state. */ 1798 iwn_set_led(sc, IWN_LED_LINK, 1, 0); 1799 } 1800 1801 if (ic->ic_state >= IEEE80211_S_ASSOC && 1802 nstate <= IEEE80211_S_ASSOC) { 1803 /* Reset state to handle re- and disassociations. */ 1804 sc->rxon.associd = 0; 1805 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1806 sc->calib.state = IWN_CALIB_STATE_INIT; 1807 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 1808 if (error != 0) 1809 printf("%s: RXON command failed\n", 1810 sc->sc_dev.dv_xname); 1811 } 1812 1813 switch (nstate) { 1814 case IEEE80211_S_SCAN: 1815 /* Make the link LED blink while we're scanning. */ 1816 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1817 1818 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ, 0)) != 0) { 1819 printf("%s: could not initiate scan\n", 1820 sc->sc_dev.dv_xname); 1821 return error; 1822 } 1823 if (ifp->if_flags & IFF_DEBUG) 1824 printf("%s: %s -> %s\n", ifp->if_xname, 1825 ieee80211_state_name[ic->ic_state], 1826 ieee80211_state_name[nstate]); 1827 if ((sc->sc_flags & IWN_FLAG_BGSCAN) == 0) { 1828 ieee80211_set_link_state(ic, LINK_STATE_DOWN); 1829 ieee80211_node_cleanup(ic, ic->ic_bss); 1830 } 1831 ic->ic_state = nstate; 1832 return 0; 1833 1834 case IEEE80211_S_ASSOC: 1835 if (ic->ic_state != IEEE80211_S_RUN) 1836 break; 1837 /* FALLTHROUGH */ 1838 case IEEE80211_S_AUTH: 1839 if ((error = iwn_auth(sc, arg)) != 0) { 1840 printf("%s: could not move to auth state\n", 1841 sc->sc_dev.dv_xname); 1842 return error; 1843 } 1844 break; 1845 1846 case IEEE80211_S_RUN: 1847 if ((error = iwn_run(sc)) != 0) { 1848 printf("%s: could not move to run state\n", 1849 sc->sc_dev.dv_xname); 1850 return error; 1851 } 1852 break; 1853 1854 case IEEE80211_S_INIT: 1855 sc->calib.state = IWN_CALIB_STATE_INIT; 1856 break; 1857 } 1858 1859 return sc->sc_newstate(ic, nstate, arg); 1860 } 1861 1862 void 1863 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1864 { 1865 struct iwn_softc *sc = arg; 1866 struct iwn_node *wn = (void *)ni; 1867 1868 if ((ni->ni_flags & IEEE80211_NODE_HT) == 0) { 1869 int old_txrate = ni->ni_txrate; 1870 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1871 if (old_txrate != ni->ni_txrate) 1872 iwn_set_link_quality(sc, ni); 1873 } 1874 } 1875 1876 void 1877 iwn_calib_timeout(void *arg) 1878 { 1879 struct iwn_softc *sc = arg; 1880 struct ieee80211com *ic = &sc->sc_ic; 1881 int s; 1882 1883 s = splnet(); 1884 if (ic->ic_fixed_rate == -1) { 1885 if (ic->ic_opmode == IEEE80211_M_STA) 1886 iwn_iter_func(sc, ic->ic_bss); 1887 else 1888 ieee80211_iterate_nodes(ic, iwn_iter_func, sc); 1889 } 1890 /* Force automatic TX power calibration every 60 secs. */ 1891 if (++sc->calib_cnt >= 120) { 1892 uint32_t flags = 0; 1893 1894 DPRINTFN(2, ("sending request for statistics\n")); 1895 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1896 sizeof flags, 1); 1897 sc->calib_cnt = 0; 1898 } 1899 splx(s); 1900 1901 /* Automatic rate control triggered every 500ms. */ 1902 timeout_add_msec(&sc->calib_to, 500); 1903 } 1904 1905 int 1906 iwn_ccmp_decap(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1907 { 1908 struct ieee80211com *ic = &sc->sc_ic; 1909 struct ieee80211_key *k = &ni->ni_pairwise_key; 1910 struct ieee80211_frame *wh; 1911 uint64_t pn, *prsc; 1912 uint8_t *ivp; 1913 uint8_t tid; 1914 int hdrlen, hasqos; 1915 1916 wh = mtod(m, struct ieee80211_frame *); 1917 hdrlen = ieee80211_get_hdrlen(wh); 1918 ivp = (uint8_t *)wh + hdrlen; 1919 1920 /* Check that ExtIV bit is set. */ 1921 if (!(ivp[3] & IEEE80211_WEP_EXTIV)) { 1922 DPRINTF(("CCMP decap ExtIV not set\n")); 1923 return 1; 1924 } 1925 hasqos = ieee80211_has_qos(wh); 1926 tid = hasqos ? ieee80211_get_qos(wh) & IEEE80211_QOS_TID : 0; 1927 prsc = &k->k_rsc[tid]; 1928 1929 /* Extract the 48-bit PN from the CCMP header. */ 1930 pn = (uint64_t)ivp[0] | 1931 (uint64_t)ivp[1] << 8 | 1932 (uint64_t)ivp[4] << 16 | 1933 (uint64_t)ivp[5] << 24 | 1934 (uint64_t)ivp[6] << 32 | 1935 (uint64_t)ivp[7] << 40; 1936 if (pn <= *prsc) { 1937 DPRINTF(("CCMP replayed\n")); 1938 ic->ic_stats.is_ccmp_replays++; 1939 return 1; 1940 } 1941 /* Last seen packet number is updated in ieee80211_inputm(). */ 1942 1943 /* Strip MIC. IV will be stripped by ieee80211_inputm(). */ 1944 m_adj(m, -IEEE80211_CCMP_MICLEN); 1945 return 0; 1946 } 1947 1948 /* 1949 * Process an RX_PHY firmware notification. This is usually immediately 1950 * followed by an MPDU_RX_DONE notification. 1951 */ 1952 void 1953 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1954 struct iwn_rx_data *data) 1955 { 1956 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1957 1958 DPRINTFN(2, ("received PHY stats\n")); 1959 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1960 sizeof (*stat), BUS_DMASYNC_POSTREAD); 1961 1962 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1963 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1964 sc->last_rx_valid = IWN_LAST_RX_VALID; 1965 /* 1966 * The firmware does not send separate RX_PHY 1967 * notifications for A-MPDU subframes. 1968 */ 1969 if (stat->flags & htole16(IWN_STAT_FLAG_AGG)) 1970 sc->last_rx_valid |= IWN_LAST_RX_AMPDU; 1971 } 1972 1973 /* 1974 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1975 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1976 */ 1977 void 1978 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1979 struct iwn_rx_data *data, struct mbuf_list *ml) 1980 { 1981 struct iwn_ops *ops = &sc->ops; 1982 struct ieee80211com *ic = &sc->sc_ic; 1983 struct ifnet *ifp = &ic->ic_if; 1984 struct iwn_rx_ring *ring = &sc->rxq; 1985 struct ieee80211_frame *wh; 1986 struct ieee80211_rxinfo rxi; 1987 struct ieee80211_node *ni; 1988 struct ieee80211_channel *bss_chan = NULL; 1989 uint8_t saved_bssid[IEEE80211_ADDR_LEN] = { 0 }; 1990 struct mbuf *m, *m1; 1991 struct iwn_rx_stat *stat; 1992 caddr_t head; 1993 uint32_t flags; 1994 int error, len, rssi; 1995 uint16_t chan; 1996 1997 if (desc->type == IWN_MPDU_RX_DONE) { 1998 /* Check for prior RX_PHY notification. */ 1999 if (!sc->last_rx_valid) { 2000 DPRINTF(("missing RX_PHY\n")); 2001 return; 2002 } 2003 sc->last_rx_valid &= ~IWN_LAST_RX_VALID; 2004 stat = &sc->last_rx_stat; 2005 if ((sc->last_rx_valid & IWN_LAST_RX_AMPDU) && 2006 (stat->flags & htole16(IWN_STAT_FLAG_AGG)) == 0) { 2007 DPRINTF(("missing RX_PHY (expecting A-MPDU)\n")); 2008 return; 2009 } 2010 if ((sc->last_rx_valid & IWN_LAST_RX_AMPDU) == 0 && 2011 (stat->flags & htole16(IWN_STAT_FLAG_AGG))) { 2012 DPRINTF(("missing RX_PHY (unexpected A-MPDU)\n")); 2013 return; 2014 } 2015 } else 2016 stat = (struct iwn_rx_stat *)(desc + 1); 2017 2018 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 2019 BUS_DMASYNC_POSTREAD); 2020 2021 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2022 printf("%s: invalid RX statistic header\n", 2023 sc->sc_dev.dv_xname); 2024 return; 2025 } 2026 if (desc->type == IWN_MPDU_RX_DONE) { 2027 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2028 head = (caddr_t)(mpdu + 1); 2029 len = letoh16(mpdu->len); 2030 } else { 2031 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2032 len = letoh16(stat->len); 2033 } 2034 2035 flags = letoh32(*(uint32_t *)(head + len)); 2036 2037 /* Discard frames with a bad FCS early. */ 2038 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2039 DPRINTFN(2, ("RX flags error %x\n", flags)); 2040 ifp->if_ierrors++; 2041 return; 2042 } 2043 /* Discard frames that are too short. */ 2044 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2045 /* Allow control frames in monitor mode. */ 2046 if (len < sizeof (struct ieee80211_frame_cts)) { 2047 DPRINTF(("frame too short: %d\n", len)); 2048 ic->ic_stats.is_rx_tooshort++; 2049 ifp->if_ierrors++; 2050 return; 2051 } 2052 } else if (len < sizeof (*wh)) { 2053 DPRINTF(("frame too short: %d\n", len)); 2054 ic->ic_stats.is_rx_tooshort++; 2055 ifp->if_ierrors++; 2056 return; 2057 } 2058 2059 m1 = MCLGETL(NULL, M_DONTWAIT, IWN_RBUF_SIZE); 2060 if (m1 == NULL) { 2061 ic->ic_stats.is_rx_nombuf++; 2062 ifp->if_ierrors++; 2063 return; 2064 } 2065 bus_dmamap_unload(sc->sc_dmat, data->map); 2066 2067 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 2068 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 2069 if (error != 0) { 2070 m_freem(m1); 2071 2072 /* Try to reload the old mbuf. */ 2073 error = bus_dmamap_load(sc->sc_dmat, data->map, 2074 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 2075 BUS_DMA_NOWAIT | BUS_DMA_READ); 2076 if (error != 0) { 2077 panic("%s: could not load old RX mbuf", 2078 sc->sc_dev.dv_xname); 2079 } 2080 /* Physical address may have changed. */ 2081 ring->desc[ring->cur] = 2082 htole32(data->map->dm_segs[0].ds_addr >> 8); 2083 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2084 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2085 BUS_DMASYNC_PREWRITE); 2086 ifp->if_ierrors++; 2087 return; 2088 } 2089 2090 m = data->m; 2091 data->m = m1; 2092 /* Update RX descriptor. */ 2093 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 2094 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2095 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2096 BUS_DMASYNC_PREWRITE); 2097 2098 /* Finalize mbuf. */ 2099 m->m_data = head; 2100 m->m_pkthdr.len = m->m_len = len; 2101 2102 /* 2103 * Grab a reference to the source node. Note that control frames are 2104 * shorter than struct ieee80211_frame but ieee80211_find_rxnode() 2105 * is being careful about control frames. 2106 */ 2107 wh = mtod(m, struct ieee80211_frame *); 2108 if (len < sizeof (*wh) && 2109 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 2110 ic->ic_stats.is_rx_tooshort++; 2111 ifp->if_ierrors++; 2112 m_freem(m); 2113 return; 2114 } 2115 ni = ieee80211_find_rxnode(ic, wh); 2116 2117 rxi.rxi_flags = 0; 2118 if (((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) 2119 && (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 2120 !IEEE80211_IS_MULTICAST(wh->i_addr1) && 2121 (ni->ni_flags & IEEE80211_NODE_RXPROT) && 2122 ni->ni_pairwise_key.k_cipher == IEEE80211_CIPHER_CCMP) { 2123 if ((flags & IWN_RX_CIPHER_MASK) != IWN_RX_CIPHER_CCMP) { 2124 ic->ic_stats.is_ccmp_dec_errs++; 2125 ifp->if_ierrors++; 2126 m_freem(m); 2127 ieee80211_release_node(ic, ni); 2128 return; 2129 } 2130 /* Check whether decryption was successful or not. */ 2131 if ((desc->type == IWN_MPDU_RX_DONE && 2132 (flags & (IWN_RX_MPDU_DEC | IWN_RX_MPDU_MIC_OK)) != 2133 (IWN_RX_MPDU_DEC | IWN_RX_MPDU_MIC_OK)) || 2134 (desc->type != IWN_MPDU_RX_DONE && 2135 (flags & IWN_RX_DECRYPT_MASK) != IWN_RX_DECRYPT_OK)) { 2136 DPRINTF(("CCMP decryption failed 0x%x\n", flags)); 2137 ic->ic_stats.is_ccmp_dec_errs++; 2138 ifp->if_ierrors++; 2139 m_freem(m); 2140 ieee80211_release_node(ic, ni); 2141 return; 2142 } 2143 if (iwn_ccmp_decap(sc, m, ni) != 0) { 2144 ifp->if_ierrors++; 2145 m_freem(m); 2146 ieee80211_release_node(ic, ni); 2147 return; 2148 } 2149 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 2150 } 2151 2152 rssi = ops->get_rssi(stat); 2153 2154 chan = stat->chan; 2155 if (chan > IEEE80211_CHAN_MAX) 2156 chan = IEEE80211_CHAN_MAX; 2157 2158 /* Fix current channel. */ 2159 if (ni == ic->ic_bss) { 2160 /* 2161 * We may switch ic_bss's channel during scans. 2162 * Record the current channel so we can restore it later. 2163 */ 2164 bss_chan = ni->ni_chan; 2165 IEEE80211_ADDR_COPY(&saved_bssid, ni->ni_macaddr); 2166 } 2167 ni->ni_chan = &ic->ic_channels[chan]; 2168 2169 #if NBPFILTER > 0 2170 if (sc->sc_drvbpf != NULL) { 2171 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2172 uint16_t chan_flags; 2173 2174 tap->wr_flags = 0; 2175 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2176 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2177 tap->wr_chan_freq = htole16(ic->ic_channels[chan].ic_freq); 2178 chan_flags = ic->ic_channels[chan].ic_flags; 2179 if (ic->ic_curmode != IEEE80211_MODE_11N) 2180 chan_flags &= ~IEEE80211_CHAN_HT; 2181 tap->wr_chan_flags = htole16(chan_flags); 2182 tap->wr_dbm_antsignal = (int8_t)rssi; 2183 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2184 tap->wr_tsft = stat->tstamp; 2185 if (stat->rflags & IWN_RFLAG_MCS) { 2186 tap->wr_rate = (0x80 | stat->rate); /* HT MCS index */ 2187 } else { 2188 switch (stat->rate) { 2189 /* CCK rates. */ 2190 case 10: tap->wr_rate = 2; break; 2191 case 20: tap->wr_rate = 4; break; 2192 case 55: tap->wr_rate = 11; break; 2193 case 110: tap->wr_rate = 22; break; 2194 /* OFDM rates. */ 2195 case 0xd: tap->wr_rate = 12; break; 2196 case 0xf: tap->wr_rate = 18; break; 2197 case 0x5: tap->wr_rate = 24; break; 2198 case 0x7: tap->wr_rate = 36; break; 2199 case 0x9: tap->wr_rate = 48; break; 2200 case 0xb: tap->wr_rate = 72; break; 2201 case 0x1: tap->wr_rate = 96; break; 2202 case 0x3: tap->wr_rate = 108; break; 2203 /* Unknown rate: should not happen. */ 2204 default: tap->wr_rate = 0; 2205 } 2206 } 2207 2208 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_rxtap_len, 2209 m, BPF_DIRECTION_IN); 2210 } 2211 #endif 2212 2213 /* Send the frame to the 802.11 layer. */ 2214 rxi.rxi_rssi = rssi; 2215 rxi.rxi_tstamp = 0; /* unused */ 2216 ieee80211_inputm(ifp, m, ni, &rxi, ml); 2217 2218 /* 2219 * ieee80211_inputm() might have changed our BSS. 2220 * Restore ic_bss's channel if we are still in the same BSS. 2221 */ 2222 if (ni == ic->ic_bss && IEEE80211_ADDR_EQ(saved_bssid, ni->ni_macaddr)) 2223 ni->ni_chan = bss_chan; 2224 2225 /* Node is no longer needed. */ 2226 ieee80211_release_node(ic, ni); 2227 } 2228 2229 void 2230 iwn_ra_choose(struct iwn_softc *sc, struct ieee80211_node *ni) 2231 { 2232 struct ieee80211com *ic = &sc->sc_ic; 2233 struct iwn_node *wn = (void *)ni; 2234 int old_txmcs = ni->ni_txmcs; 2235 2236 ieee80211_ra_choose(&wn->rn, ic, ni); 2237 2238 /* Update firmware's LQ retry table if RA has chosen a new MCS. */ 2239 if (ni->ni_txmcs != old_txmcs) 2240 iwn_set_link_quality(sc, ni); 2241 } 2242 2243 void 2244 iwn_ampdu_rate_control(struct iwn_softc *sc, struct ieee80211_node *ni, 2245 struct iwn_tx_ring *txq, uint16_t seq, uint16_t ssn) 2246 { 2247 struct ieee80211com *ic = &sc->sc_ic; 2248 struct iwn_node *wn = (void *)ni; 2249 int idx, end_idx; 2250 2251 /* 2252 * Update Tx rate statistics for A-MPDUs before firmware's BA window. 2253 */ 2254 idx = IWN_AGG_SSN_TO_TXQ_IDX(seq); 2255 end_idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 2256 while (idx != end_idx) { 2257 struct iwn_tx_data *txdata = &txq->data[idx]; 2258 if (txdata->m != NULL && txdata->ampdu_nframes > 1) { 2259 /* 2260 * We can assume that this subframe has been ACKed 2261 * because ACK failures come as single frames and 2262 * before failing an A-MPDU subframe the firmware 2263 * sends it as a single frame at least once. 2264 */ 2265 ieee80211_ra_add_stats_ht(&wn->rn, ic, ni, 2266 txdata->ampdu_txmcs, 1, 0); 2267 2268 /* Report this frame only once. */ 2269 txdata->ampdu_nframes = 0; 2270 } 2271 2272 idx = (idx + 1) % IWN_TX_RING_COUNT; 2273 } 2274 2275 iwn_ra_choose(sc, ni); 2276 } 2277 2278 void 2279 iwn_ht_single_rate_control(struct iwn_softc *sc, struct ieee80211_node *ni, 2280 uint8_t rate, uint8_t rflags, uint8_t ackfailcnt, int txfail) 2281 { 2282 struct ieee80211com *ic = &sc->sc_ic; 2283 struct iwn_node *wn = (void *)ni; 2284 int mcs = rate; 2285 const struct ieee80211_ht_rateset *rs = 2286 ieee80211_ra_get_ht_rateset(rate, 0 /* chan40 */, 2287 ieee80211_ra_use_ht_sgi(ni)); 2288 unsigned int retries = 0, i; 2289 2290 /* 2291 * Ignore Tx reports which don't match our last LQ command. 2292 */ 2293 if (rate != ni->ni_txmcs) { 2294 if (++wn->lq_rate_mismatch > 15) { 2295 /* Try to sync firmware with driver. */ 2296 iwn_set_link_quality(sc, ni); 2297 wn->lq_rate_mismatch = 0; 2298 } 2299 return; 2300 } 2301 2302 wn->lq_rate_mismatch = 0; 2303 2304 /* 2305 * Firmware has attempted rates in this rate set in sequence. 2306 * Retries at a basic rate are counted against the minimum MCS. 2307 */ 2308 for (i = 0; i < ackfailcnt; i++) { 2309 if (mcs > rs->min_mcs) { 2310 ieee80211_ra_add_stats_ht(&wn->rn, ic, ni, mcs, 1, 1); 2311 mcs--; 2312 } else 2313 retries++; 2314 } 2315 2316 if (txfail && ackfailcnt == 0) 2317 ieee80211_ra_add_stats_ht(&wn->rn, ic, ni, mcs, 1, 1); 2318 else 2319 ieee80211_ra_add_stats_ht(&wn->rn, ic, ni, mcs, retries + 1, retries); 2320 2321 iwn_ra_choose(sc, ni); 2322 } 2323 2324 /* 2325 * Process an incoming Compressed BlockAck. 2326 * Note that these block ack notifications are generated by firmware and do 2327 * not necessarily correspond to contents of block ack frames seen on the air. 2328 */ 2329 void 2330 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2331 struct iwn_rx_data *data) 2332 { 2333 struct iwn_compressed_ba *cba = (struct iwn_compressed_ba *)(desc + 1); 2334 struct ieee80211com *ic = &sc->sc_ic; 2335 struct ieee80211_node *ni; 2336 struct ieee80211_tx_ba *ba; 2337 struct iwn_tx_ring *txq; 2338 uint16_t seq, ssn; 2339 int qid; 2340 2341 if (ic->ic_state != IEEE80211_S_RUN) 2342 return; 2343 2344 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*cba), 2345 BUS_DMASYNC_POSTREAD); 2346 2347 if (!IEEE80211_ADDR_EQ(ic->ic_bss->ni_macaddr, cba->macaddr)) 2348 return; 2349 2350 ni = ic->ic_bss; 2351 2352 qid = le16toh(cba->qid); 2353 if (qid < sc->first_agg_txq || qid >= sc->ntxqs) 2354 return; 2355 2356 txq = &sc->txq[qid]; 2357 2358 /* Protect against a firmware bug where the queue/TID are off. */ 2359 if (qid != sc->first_agg_txq + cba->tid) 2360 return; 2361 2362 ba = &ni->ni_tx_ba[cba->tid]; 2363 if (ba->ba_state != IEEE80211_BA_AGREED) 2364 return; 2365 2366 /* 2367 * The first bit in cba->bitmap corresponds to the sequence number 2368 * stored in the sequence control field cba->seq. 2369 * Multiple BA notifications in a row may be using this number, with 2370 * additional bits being set in cba->bitmap. It is unclear how the 2371 * firmware decides to shift this window forward. 2372 * We rely on ba->ba_winstart instead. 2373 */ 2374 seq = le16toh(cba->seq) >> IEEE80211_SEQ_SEQ_SHIFT; 2375 2376 /* 2377 * The firmware's new BA window starting sequence number 2378 * corresponds to the first hole in cba->bitmap, implying 2379 * that all frames between 'seq' and 'ssn' (non-inclusive) 2380 * have been acked. 2381 */ 2382 ssn = le16toh(cba->ssn); 2383 2384 if (SEQ_LT(ssn, ba->ba_winstart)) 2385 return; 2386 2387 /* Skip rate control if our Tx rate is fixed. */ 2388 if (ic->ic_fixed_mcs == -1) 2389 iwn_ampdu_rate_control(sc, ni, txq, ba->ba_winstart, ssn); 2390 2391 /* 2392 * SSN corresponds to the first (perhaps not yet transmitted) frame 2393 * in firmware's BA window. Firmware is not going to retransmit any 2394 * frames before its BA window so mark them all as done. 2395 */ 2396 ieee80211_output_ba_move_window(ic, ni, cba->tid, ssn); 2397 iwn_ampdu_txq_advance(sc, txq, qid, 2398 IWN_AGG_SSN_TO_TXQ_IDX(ssn)); 2399 iwn_clear_oactive(sc, txq); 2400 } 2401 2402 /* 2403 * Process a CALIBRATION_RESULT notification sent by the initialization 2404 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2405 */ 2406 void 2407 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2408 struct iwn_rx_data *data) 2409 { 2410 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2411 int len, idx = -1; 2412 2413 /* Runtime firmware should not send such a notification. */ 2414 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2415 return; 2416 2417 len = (letoh32(desc->len) & IWN_RX_DESC_LEN_MASK) - 4; 2418 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2419 BUS_DMASYNC_POSTREAD); 2420 2421 switch (calib->code) { 2422 case IWN5000_PHY_CALIB_DC: 2423 if (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2424 sc->hw_type == IWN_HW_REV_TYPE_2030 || 2425 sc->hw_type == IWN_HW_REV_TYPE_2000 || 2426 sc->hw_type == IWN_HW_REV_TYPE_135 || 2427 sc->hw_type == IWN_HW_REV_TYPE_105) 2428 idx = 0; 2429 break; 2430 case IWN5000_PHY_CALIB_LO: 2431 idx = 1; 2432 break; 2433 case IWN5000_PHY_CALIB_TX_IQ: 2434 idx = 2; 2435 break; 2436 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2437 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2438 sc->hw_type != IWN_HW_REV_TYPE_5150) 2439 idx = 3; 2440 break; 2441 case IWN5000_PHY_CALIB_BASE_BAND: 2442 idx = 4; 2443 break; 2444 } 2445 if (idx == -1) /* Ignore other results. */ 2446 return; 2447 2448 /* Save calibration result. */ 2449 if (sc->calibcmd[idx].buf != NULL) 2450 free(sc->calibcmd[idx].buf, M_DEVBUF, 0); 2451 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2452 if (sc->calibcmd[idx].buf == NULL) { 2453 DPRINTF(("not enough memory for calibration result %d\n", 2454 calib->code)); 2455 return; 2456 } 2457 DPRINTF(("saving calibration result code=%d len=%d\n", 2458 calib->code, len)); 2459 sc->calibcmd[idx].len = len; 2460 memcpy(sc->calibcmd[idx].buf, calib, len); 2461 } 2462 2463 /* 2464 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2465 * The latter is sent by the firmware after each received beacon. 2466 */ 2467 void 2468 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2469 struct iwn_rx_data *data) 2470 { 2471 struct iwn_ops *ops = &sc->ops; 2472 struct ieee80211com *ic = &sc->sc_ic; 2473 struct iwn_calib_state *calib = &sc->calib; 2474 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2475 int temp; 2476 2477 /* Ignore statistics received during a scan. */ 2478 if (ic->ic_state != IEEE80211_S_RUN) 2479 return; 2480 2481 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2482 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2483 2484 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2485 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2486 2487 /* Test if temperature has changed. */ 2488 if (stats->general.temp != sc->rawtemp) { 2489 /* Convert "raw" temperature to degC. */ 2490 sc->rawtemp = stats->general.temp; 2491 temp = ops->get_temperature(sc); 2492 DPRINTFN(2, ("temperature=%dC\n", temp)); 2493 2494 /* Update TX power if need be (4965AGN only). */ 2495 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2496 iwn4965_power_calibration(sc, temp); 2497 } 2498 2499 if (desc->type != IWN_BEACON_STATISTICS) 2500 return; /* Reply to a statistics request. */ 2501 2502 sc->noise = iwn_get_noise(&stats->rx.general); 2503 2504 /* Test that RSSI and noise are present in stats report. */ 2505 if (sc->noise == -127) 2506 return; 2507 2508 if (letoh32(stats->rx.general.flags) != 1) { 2509 DPRINTF(("received statistics without RSSI\n")); 2510 return; 2511 } 2512 2513 /* 2514 * XXX Differential gain calibration makes the 6005 firmware 2515 * crap out, so skip it for now. This effectively disables 2516 * sensitivity tuning as well. 2517 */ 2518 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 2519 return; 2520 2521 if (calib->state == IWN_CALIB_STATE_ASSOC) 2522 iwn_collect_noise(sc, &stats->rx.general); 2523 else if (calib->state == IWN_CALIB_STATE_RUN) 2524 iwn_tune_sensitivity(sc, &stats->rx); 2525 } 2526 2527 void 2528 iwn_ampdu_txq_advance(struct iwn_softc *sc, struct iwn_tx_ring *txq, int qid, 2529 int idx) 2530 { 2531 struct iwn_ops *ops = &sc->ops; 2532 2533 DPRINTFN(3, ("%s: txq->cur=%d txq->read=%d txq->queued=%d qid=%d " 2534 "idx=%d\n", __func__, txq->cur, txq->read, txq->queued, qid, idx)); 2535 2536 while (txq->read != idx) { 2537 struct iwn_tx_data *txdata = &txq->data[txq->read]; 2538 if (txdata->m != NULL) { 2539 ops->reset_sched(sc, qid, txq->read); 2540 iwn_tx_done_free_txdata(sc, txdata); 2541 txq->queued--; 2542 } 2543 txq->read = (txq->read + 1) % IWN_TX_RING_COUNT; 2544 } 2545 } 2546 2547 /* 2548 * Handle A-MPDU Tx queue status report. 2549 * Tx failures come as single frames (perhaps out of order), and before failing 2550 * an A-MPDU subframe the firmware transmits it as a single frame at least once. 2551 * Frames successfully transmitted in an A-MPDU are completed when a compressed 2552 * block ack notification is received. 2553 */ 2554 void 2555 iwn_ampdu_tx_done(struct iwn_softc *sc, struct iwn_tx_ring *txq, 2556 struct iwn_rx_desc *desc, uint16_t status, uint8_t ackfailcnt, 2557 uint8_t rate, uint8_t rflags, int nframes, uint32_t ssn, 2558 struct iwn_txagg_status *agg_status) 2559 { 2560 struct ieee80211com *ic = &sc->sc_ic; 2561 int tid = desc->qid - sc->first_agg_txq; 2562 struct iwn_tx_data *txdata = &txq->data[desc->idx]; 2563 struct ieee80211_node *ni = txdata->ni; 2564 int txfail = (status != IWN_TX_STATUS_SUCCESS && 2565 status != IWN_TX_STATUS_DIRECT_DONE); 2566 struct ieee80211_tx_ba *ba; 2567 uint16_t seq; 2568 2569 sc->sc_tx_timer = 0; 2570 2571 if (ic->ic_state != IEEE80211_S_RUN) 2572 return; 2573 2574 if (nframes > 1) { 2575 int i; 2576 2577 /* 2578 * Collect information about this A-MPDU. 2579 */ 2580 for (i = 0; i < nframes; i++) { 2581 uint8_t qid = agg_status[i].qid; 2582 uint8_t idx = agg_status[i].idx; 2583 uint16_t txstatus = (le16toh(agg_status[i].status) & 2584 IWN_AGG_TX_STATUS_MASK); 2585 2586 if (txstatus != IWN_AGG_TX_STATE_TRANSMITTED) 2587 continue; 2588 2589 if (qid != desc->qid) 2590 continue; 2591 2592 txdata = &txq->data[idx]; 2593 if (txdata->ni == NULL) 2594 continue; 2595 2596 /* The Tx rate was the same for all subframes. */ 2597 txdata->ampdu_txmcs = rate; 2598 txdata->ampdu_nframes = nframes; 2599 } 2600 return; 2601 } 2602 2603 if (ni == NULL) 2604 return; 2605 2606 ba = &ni->ni_tx_ba[tid]; 2607 if (ba->ba_state != IEEE80211_BA_AGREED) 2608 return; 2609 if (SEQ_LT(ssn, ba->ba_winstart)) 2610 return; 2611 2612 /* This was a final single-frame Tx attempt for frame SSN-1. */ 2613 seq = (ssn - 1) & 0xfff; 2614 2615 /* 2616 * Skip rate control if our Tx rate is fixed. 2617 */ 2618 if (ic->ic_fixed_mcs == -1) { 2619 if (txdata->ampdu_nframes > 1) { 2620 struct iwn_node *wn = (void *)ni; 2621 /* 2622 * This frame was once part of an A-MPDU. 2623 * Report one failed A-MPDU Tx attempt. 2624 * The firmware might have made several such 2625 * attempts but we don't keep track of this. 2626 */ 2627 ieee80211_ra_add_stats_ht(&wn->rn, ic, ni, 2628 txdata->ampdu_txmcs, 1, 1); 2629 } 2630 2631 /* Report the final single-frame Tx attempt. */ 2632 if (rflags & IWN_RFLAG_MCS) 2633 iwn_ht_single_rate_control(sc, ni, rate, rflags, 2634 ackfailcnt, txfail); 2635 } 2636 2637 if (txfail) 2638 ieee80211_tx_compressed_bar(ic, ni, tid, ssn); 2639 2640 /* 2641 * SSN corresponds to the first (perhaps not yet transmitted) frame 2642 * in firmware's BA window. Firmware is not going to retransmit any 2643 * frames before its BA window so mark them all as done. 2644 */ 2645 ieee80211_output_ba_move_window(ic, ni, tid, ssn); 2646 iwn_ampdu_txq_advance(sc, txq, desc->qid, IWN_AGG_SSN_TO_TXQ_IDX(ssn)); 2647 iwn_clear_oactive(sc, txq); 2648 } 2649 2650 /* 2651 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2652 * and 5000 adapters have different incompatible TX status formats. 2653 */ 2654 void 2655 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2656 struct iwn_rx_data *data) 2657 { 2658 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2659 struct iwn_tx_ring *ring; 2660 size_t len = (letoh32(desc->len) & IWN_RX_DESC_LEN_MASK); 2661 uint16_t status = letoh32(stat->stat.status) & 0xff; 2662 uint32_t ssn; 2663 2664 if (desc->qid > IWN4965_NTXQUEUES) 2665 return; 2666 2667 ring = &sc->txq[desc->qid]; 2668 2669 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2670 len, BUS_DMASYNC_POSTREAD); 2671 2672 /* Sanity checks. */ 2673 if (sizeof(*stat) > len) 2674 return; 2675 if (stat->nframes < 1 || stat->nframes > IWN_AMPDU_MAX) 2676 return; 2677 if (desc->qid < sc->first_agg_txq && stat->nframes > 1) 2678 return; 2679 if (desc->qid >= sc->first_agg_txq && sizeof(*stat) + sizeof(ssn) + 2680 stat->nframes * sizeof(stat->stat) > len) 2681 return; 2682 2683 if (desc->qid < sc->first_agg_txq) { 2684 /* XXX 4965 does not report byte count */ 2685 struct iwn_tx_data *txdata = &ring->data[desc->idx]; 2686 uint16_t framelen = txdata->totlen + IEEE80211_CRC_LEN; 2687 int txfail = (status != IWN_TX_STATUS_SUCCESS && 2688 status != IWN_TX_STATUS_DIRECT_DONE); 2689 2690 iwn_tx_done(sc, desc, stat->ackfailcnt, stat->rate, 2691 stat->rflags, txfail, desc->qid, framelen); 2692 } else { 2693 memcpy(&ssn, &stat->stat.status + stat->nframes, sizeof(ssn)); 2694 ssn = le32toh(ssn) & 0xfff; 2695 iwn_ampdu_tx_done(sc, ring, desc, status, stat->ackfailcnt, 2696 stat->rate, stat->rflags, stat->nframes, ssn, 2697 stat->stat.agg_status); 2698 } 2699 } 2700 2701 void 2702 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2703 struct iwn_rx_data *data) 2704 { 2705 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2706 struct iwn_tx_ring *ring; 2707 size_t len = (letoh32(desc->len) & IWN_RX_DESC_LEN_MASK); 2708 uint16_t status = letoh32(stat->stat.status) & 0xff; 2709 uint32_t ssn; 2710 2711 if (desc->qid > IWN5000_NTXQUEUES) 2712 return; 2713 2714 ring = &sc->txq[desc->qid]; 2715 2716 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2717 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2718 2719 /* Sanity checks. */ 2720 if (sizeof(*stat) > len) 2721 return; 2722 if (stat->nframes < 1 || stat->nframes > IWN_AMPDU_MAX) 2723 return; 2724 if (desc->qid < sc->first_agg_txq && stat->nframes > 1) 2725 return; 2726 if (desc->qid >= sc->first_agg_txq && sizeof(*stat) + sizeof(ssn) + 2727 stat->nframes * sizeof(stat->stat) > len) 2728 return; 2729 2730 /* If this was not an aggregated frame, complete it now. */ 2731 if (desc->qid < sc->first_agg_txq) { 2732 int txfail = (status != IWN_TX_STATUS_SUCCESS && 2733 status != IWN_TX_STATUS_DIRECT_DONE); 2734 2735 /* Reset TX scheduler slot. */ 2736 iwn5000_reset_sched(sc, desc->qid, desc->idx); 2737 2738 iwn_tx_done(sc, desc, stat->ackfailcnt, stat->rate, 2739 stat->rflags, txfail, desc->qid, letoh16(stat->len)); 2740 } else { 2741 memcpy(&ssn, &stat->stat.status + stat->nframes, sizeof(ssn)); 2742 ssn = le32toh(ssn) & 0xfff; 2743 iwn_ampdu_tx_done(sc, ring, desc, status, stat->ackfailcnt, 2744 stat->rate, stat->rflags, stat->nframes, ssn, 2745 stat->stat.agg_status); 2746 } 2747 } 2748 2749 void 2750 iwn_tx_done_free_txdata(struct iwn_softc *sc, struct iwn_tx_data *data) 2751 { 2752 struct ieee80211com *ic = &sc->sc_ic; 2753 2754 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2755 BUS_DMASYNC_POSTWRITE); 2756 bus_dmamap_unload(sc->sc_dmat, data->map); 2757 m_freem(data->m); 2758 data->m = NULL; 2759 ieee80211_release_node(ic, data->ni); 2760 data->ni = NULL; 2761 data->totlen = 0; 2762 data->ampdu_nframes = 0; 2763 data->ampdu_txmcs = 0; 2764 } 2765 2766 void 2767 iwn_clear_oactive(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2768 { 2769 struct ieee80211com *ic = &sc->sc_ic; 2770 struct ifnet *ifp = &ic->ic_if; 2771 2772 if (ring->queued < IWN_TX_RING_LOMARK) { 2773 sc->qfullmsk &= ~(1 << ring->qid); 2774 if (sc->qfullmsk == 0 && ifq_is_oactive(&ifp->if_snd)) { 2775 ifq_clr_oactive(&ifp->if_snd); 2776 (*ifp->if_start)(ifp); 2777 } 2778 } 2779 } 2780 2781 /* 2782 * Adapter-independent backend for TX_DONE firmware notifications. 2783 * This handles Tx status for non-aggregation queues. 2784 */ 2785 void 2786 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2787 uint8_t ackfailcnt, uint8_t rate, uint8_t rflags, int txfail, 2788 int qid, uint16_t len) 2789 { 2790 struct ieee80211com *ic = &sc->sc_ic; 2791 struct ifnet *ifp = &ic->ic_if; 2792 struct iwn_tx_ring *ring = &sc->txq[qid]; 2793 struct iwn_tx_data *data = &ring->data[desc->idx]; 2794 struct iwn_node *wn = (void *)data->ni; 2795 2796 if (data->ni == NULL) 2797 return; 2798 2799 if (data->ni->ni_flags & IEEE80211_NODE_HT) { 2800 if (ic->ic_state == IEEE80211_S_RUN && 2801 ic->ic_fixed_mcs == -1 && (rflags & IWN_RFLAG_MCS)) { 2802 iwn_ht_single_rate_control(sc, data->ni, rate, rflags, 2803 ackfailcnt, txfail); 2804 } 2805 } else { 2806 if (rate != data->ni->ni_txrate) { 2807 if (++wn->lq_rate_mismatch > 15) { 2808 /* Try to sync firmware with driver. */ 2809 iwn_set_link_quality(sc, data->ni); 2810 wn->lq_rate_mismatch = 0; 2811 } 2812 } else { 2813 wn->lq_rate_mismatch = 0; 2814 2815 wn->amn.amn_txcnt++; 2816 if (ackfailcnt > 0) 2817 wn->amn.amn_retrycnt++; 2818 if (txfail) 2819 wn->amn.amn_retrycnt++; 2820 } 2821 } 2822 if (txfail) 2823 ifp->if_oerrors++; 2824 2825 iwn_tx_done_free_txdata(sc, data); 2826 2827 sc->sc_tx_timer = 0; 2828 ring->queued--; 2829 iwn_clear_oactive(sc, ring); 2830 } 2831 2832 /* 2833 * Process a "command done" firmware notification. This is where we wakeup 2834 * processes waiting for a synchronous command completion. 2835 */ 2836 void 2837 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2838 { 2839 struct iwn_tx_ring *ring = &sc->txq[4]; 2840 struct iwn_tx_data *data; 2841 2842 if ((desc->qid & 0xf) != 4) 2843 return; /* Not a command ack. */ 2844 2845 data = &ring->data[desc->idx]; 2846 2847 /* If the command was mapped in an mbuf, free it. */ 2848 if (data->m != NULL) { 2849 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2850 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2851 bus_dmamap_unload(sc->sc_dmat, data->map); 2852 m_freem(data->m); 2853 data->m = NULL; 2854 } 2855 wakeup(&ring->desc[desc->idx]); 2856 } 2857 2858 /* 2859 * Process an INT_FH_RX or INT_SW_RX interrupt. 2860 */ 2861 void 2862 iwn_notif_intr(struct iwn_softc *sc) 2863 { 2864 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2865 struct iwn_ops *ops = &sc->ops; 2866 struct ieee80211com *ic = &sc->sc_ic; 2867 struct ifnet *ifp = &ic->ic_if; 2868 uint16_t hw; 2869 2870 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2871 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2872 2873 hw = letoh16(sc->rxq.stat->closed_count) & 0xfff; 2874 while (sc->rxq.cur != hw) { 2875 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2876 struct iwn_rx_desc *desc; 2877 2878 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2879 BUS_DMASYNC_POSTREAD); 2880 desc = mtod(data->m, struct iwn_rx_desc *); 2881 2882 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2883 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2884 2885 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2886 iwn_cmd_done(sc, desc); 2887 2888 switch (desc->type) { 2889 case IWN_RX_PHY: 2890 iwn_rx_phy(sc, desc, data); 2891 break; 2892 2893 case IWN_RX_DONE: /* 4965AGN only. */ 2894 case IWN_MPDU_RX_DONE: 2895 /* An 802.11 frame has been received. */ 2896 iwn_rx_done(sc, desc, data, &ml); 2897 break; 2898 case IWN_RX_COMPRESSED_BA: 2899 /* A Compressed BlockAck has been received. */ 2900 iwn_rx_compressed_ba(sc, desc, data); 2901 break; 2902 case IWN_TX_DONE: 2903 /* An 802.11 frame has been transmitted. */ 2904 ops->tx_done(sc, desc, data); 2905 break; 2906 2907 case IWN_RX_STATISTICS: 2908 case IWN_BEACON_STATISTICS: 2909 iwn_rx_statistics(sc, desc, data); 2910 break; 2911 2912 case IWN_BEACON_MISSED: 2913 { 2914 struct iwn_beacon_missed *miss = 2915 (struct iwn_beacon_missed *)(desc + 1); 2916 uint32_t missed; 2917 2918 if ((ic->ic_opmode != IEEE80211_M_STA) || 2919 (ic->ic_state != IEEE80211_S_RUN)) 2920 break; 2921 2922 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2923 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2924 missed = letoh32(miss->consecutive); 2925 2926 /* 2927 * If more than 5 consecutive beacons are missed, 2928 * reinitialize the sensitivity state machine. 2929 */ 2930 if (missed > 5) 2931 (void)iwn_init_sensitivity(sc); 2932 2933 /* 2934 * Rather than go directly to scan state, try to send a 2935 * directed probe request first. If that fails then the 2936 * state machine will drop us into scanning after timing 2937 * out waiting for a probe response. 2938 */ 2939 if (missed > ic->ic_bmissthres && !ic->ic_mgt_timer) { 2940 if (ic->ic_if.if_flags & IFF_DEBUG) 2941 printf("%s: receiving no beacons from " 2942 "%s; checking if this AP is still " 2943 "responding to probe requests\n", 2944 sc->sc_dev.dv_xname, ether_sprintf( 2945 ic->ic_bss->ni_macaddr)); 2946 IEEE80211_SEND_MGMT(ic, ic->ic_bss, 2947 IEEE80211_FC0_SUBTYPE_PROBE_REQ, 0); 2948 } 2949 break; 2950 } 2951 case IWN_UC_READY: 2952 { 2953 struct iwn_ucode_info *uc = 2954 (struct iwn_ucode_info *)(desc + 1); 2955 2956 /* The microcontroller is ready. */ 2957 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2958 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2959 DPRINTF(("microcode alive notification version=%d.%d " 2960 "subtype=%x alive=%x\n", uc->major, uc->minor, 2961 uc->subtype, letoh32(uc->valid))); 2962 2963 if (letoh32(uc->valid) != 1) { 2964 printf("%s: microcontroller initialization " 2965 "failed\n", sc->sc_dev.dv_xname); 2966 break; 2967 } 2968 if (uc->subtype == IWN_UCODE_INIT) { 2969 /* Save microcontroller report. */ 2970 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2971 } 2972 /* Save the address of the error log in SRAM. */ 2973 sc->errptr = letoh32(uc->errptr); 2974 break; 2975 } 2976 case IWN_STATE_CHANGED: 2977 { 2978 uint32_t *status = (uint32_t *)(desc + 1); 2979 2980 /* Enabled/disabled notification. */ 2981 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2982 sizeof (*status), BUS_DMASYNC_POSTREAD); 2983 DPRINTF(("state changed to %x\n", letoh32(*status))); 2984 2985 if (letoh32(*status) & 1) { 2986 /* Radio transmitter is off, power down. */ 2987 iwn_stop(ifp); 2988 return; /* No further processing. */ 2989 } 2990 break; 2991 } 2992 case IWN_START_SCAN: 2993 { 2994 struct iwn_start_scan *scan = 2995 (struct iwn_start_scan *)(desc + 1); 2996 2997 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2998 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2999 DPRINTFN(2, ("scan start: chan %d status %x\n", 3000 scan->chan, letoh32(scan->status))); 3001 3002 if (sc->sc_flags & IWN_FLAG_BGSCAN) 3003 break; 3004 3005 /* Fix current channel. */ 3006 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 3007 break; 3008 } 3009 case IWN_STOP_SCAN: 3010 { 3011 struct iwn_stop_scan *scan = 3012 (struct iwn_stop_scan *)(desc + 1); 3013 3014 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 3015 sizeof (*scan), BUS_DMASYNC_POSTREAD); 3016 DPRINTFN(2, ("scan stop: nchan=%d status=%d chan=%d\n", 3017 scan->nchan, scan->status, scan->chan)); 3018 3019 if (scan->status == 1 && scan->chan <= 14 && 3020 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 3021 int error; 3022 /* 3023 * We just finished scanning 2GHz channels, 3024 * start scanning 5GHz ones. 3025 */ 3026 error = iwn_scan(sc, IEEE80211_CHAN_5GHZ, 3027 (sc->sc_flags & IWN_FLAG_BGSCAN) ? 1 : 0); 3028 if (error == 0) 3029 break; 3030 } 3031 sc->sc_flags &= ~IWN_FLAG_SCANNING; 3032 sc->sc_flags &= ~IWN_FLAG_BGSCAN; 3033 ieee80211_end_scan(ifp); 3034 break; 3035 } 3036 case IWN5000_CALIBRATION_RESULT: 3037 iwn5000_rx_calib_results(sc, desc, data); 3038 break; 3039 3040 case IWN5000_CALIBRATION_DONE: 3041 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 3042 wakeup(sc); 3043 break; 3044 } 3045 3046 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 3047 } 3048 if_input(&sc->sc_ic.ic_if, &ml); 3049 3050 /* Tell the firmware what we have processed. */ 3051 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 3052 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 3053 } 3054 3055 /* 3056 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 3057 * from power-down sleep mode. 3058 */ 3059 void 3060 iwn_wakeup_intr(struct iwn_softc *sc) 3061 { 3062 int qid; 3063 3064 DPRINTF(("ucode wakeup from power-down sleep\n")); 3065 3066 /* Wakeup RX and TX rings. */ 3067 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 3068 for (qid = 0; qid < sc->ntxqs; qid++) { 3069 struct iwn_tx_ring *ring = &sc->txq[qid]; 3070 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 3071 } 3072 } 3073 3074 /* 3075 * Dump the error log of the firmware when a firmware panic occurs. Although 3076 * we can't debug the firmware because it is neither open source nor free, it 3077 * can help us to identify certain classes of problems. 3078 */ 3079 void 3080 iwn_fatal_intr(struct iwn_softc *sc) 3081 { 3082 struct iwn_fw_dump dump; 3083 int i; 3084 3085 /* Check that the error log address is valid. */ 3086 if (sc->errptr < IWN_FW_DATA_BASE || 3087 sc->errptr + sizeof (dump) > 3088 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 3089 printf("%s: bad firmware error log address 0x%08x\n", 3090 sc->sc_dev.dv_xname, sc->errptr); 3091 return; 3092 } 3093 if (iwn_nic_lock(sc) != 0) { 3094 printf("%s: could not read firmware error log\n", 3095 sc->sc_dev.dv_xname); 3096 return; 3097 } 3098 /* Read firmware error log from SRAM. */ 3099 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 3100 sizeof (dump) / sizeof (uint32_t)); 3101 iwn_nic_unlock(sc); 3102 3103 if (dump.valid == 0) { 3104 printf("%s: firmware error log is empty\n", 3105 sc->sc_dev.dv_xname); 3106 return; 3107 } 3108 printf("firmware error log:\n"); 3109 printf(" error type = \"%s\" (0x%08X)\n", 3110 (dump.id < nitems(iwn_fw_errmsg)) ? 3111 iwn_fw_errmsg[dump.id] : "UNKNOWN", 3112 dump.id); 3113 printf(" program counter = 0x%08X\n", dump.pc); 3114 printf(" source line = 0x%08X\n", dump.src_line); 3115 printf(" error data = 0x%08X%08X\n", 3116 dump.error_data[0], dump.error_data[1]); 3117 printf(" branch link = 0x%08X%08X\n", 3118 dump.branch_link[0], dump.branch_link[1]); 3119 printf(" interrupt link = 0x%08X%08X\n", 3120 dump.interrupt_link[0], dump.interrupt_link[1]); 3121 printf(" time = %u\n", dump.time[0]); 3122 3123 /* Dump driver status (TX and RX rings) while we're here. */ 3124 printf("driver status:\n"); 3125 for (i = 0; i < sc->ntxqs; i++) { 3126 struct iwn_tx_ring *ring = &sc->txq[i]; 3127 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 3128 i, ring->qid, ring->cur, ring->queued); 3129 } 3130 printf(" rx ring: cur=%d\n", sc->rxq.cur); 3131 printf(" 802.11 state %d\n", sc->sc_ic.ic_state); 3132 } 3133 3134 int 3135 iwn_intr(void *arg) 3136 { 3137 struct iwn_softc *sc = arg; 3138 struct ifnet *ifp = &sc->sc_ic.ic_if; 3139 uint32_t r1, r2, tmp; 3140 3141 /* Disable interrupts. */ 3142 IWN_WRITE(sc, IWN_INT_MASK, 0); 3143 3144 /* Read interrupts from ICT (fast) or from registers (slow). */ 3145 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3146 tmp = 0; 3147 while (sc->ict[sc->ict_cur] != 0) { 3148 tmp |= sc->ict[sc->ict_cur]; 3149 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 3150 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 3151 } 3152 tmp = letoh32(tmp); 3153 if (tmp == 0xffffffff) /* Shouldn't happen. */ 3154 tmp = 0; 3155 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 3156 tmp |= 0x8000; 3157 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 3158 r2 = 0; /* Unused. */ 3159 } else { 3160 r1 = IWN_READ(sc, IWN_INT); 3161 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 3162 return 0; /* Hardware gone! */ 3163 r2 = IWN_READ(sc, IWN_FH_INT); 3164 } 3165 if (r1 == 0 && r2 == 0) { 3166 if (ifp->if_flags & IFF_UP) 3167 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 3168 return 0; /* Interrupt not for us. */ 3169 } 3170 3171 /* Acknowledge interrupts. */ 3172 IWN_WRITE(sc, IWN_INT, r1); 3173 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 3174 IWN_WRITE(sc, IWN_FH_INT, r2); 3175 3176 if (r1 & IWN_INT_RF_TOGGLED) { 3177 tmp = IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL; 3178 printf("%s: RF switch: radio %s\n", sc->sc_dev.dv_xname, 3179 tmp ? "enabled" : "disabled"); 3180 if (tmp) 3181 task_add(systq, &sc->init_task); 3182 } 3183 if (r1 & IWN_INT_CT_REACHED) { 3184 printf("%s: critical temperature reached!\n", 3185 sc->sc_dev.dv_xname); 3186 } 3187 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 3188 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 3189 3190 /* Force a complete recalibration on next init. */ 3191 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 3192 3193 /* Dump firmware error log and stop. */ 3194 if (ifp->if_flags & IFF_DEBUG) 3195 iwn_fatal_intr(sc); 3196 iwn_stop(ifp); 3197 task_add(systq, &sc->init_task); 3198 return 1; 3199 } 3200 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 3201 (r2 & IWN_FH_INT_RX)) { 3202 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3203 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 3204 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 3205 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 3206 IWN_INT_PERIODIC_DIS); 3207 iwn_notif_intr(sc); 3208 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 3209 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 3210 IWN_INT_PERIODIC_ENA); 3211 } 3212 } else 3213 iwn_notif_intr(sc); 3214 } 3215 3216 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 3217 if (sc->sc_flags & IWN_FLAG_USE_ICT) 3218 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 3219 wakeup(sc); /* FH DMA transfer completed. */ 3220 } 3221 3222 if (r1 & IWN_INT_ALIVE) 3223 wakeup(sc); /* Firmware is alive. */ 3224 3225 if (r1 & IWN_INT_WAKEUP) 3226 iwn_wakeup_intr(sc); 3227 3228 /* Re-enable interrupts. */ 3229 if (ifp->if_flags & IFF_UP) 3230 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 3231 3232 return 1; 3233 } 3234 3235 /* 3236 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 3237 * 5000 adapters use a slightly different format). 3238 */ 3239 void 3240 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3241 uint16_t len) 3242 { 3243 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 3244 3245 *w = htole16(len + 8); 3246 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3247 (caddr_t)w - sc->sched_dma.vaddr, sizeof (uint16_t), 3248 BUS_DMASYNC_PREWRITE); 3249 if (idx < IWN_SCHED_WINSZ) { 3250 *(w + IWN_TX_RING_COUNT) = *w; 3251 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3252 (caddr_t)(w + IWN_TX_RING_COUNT) - sc->sched_dma.vaddr, 3253 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 3254 } 3255 } 3256 3257 void 3258 iwn4965_reset_sched(struct iwn_softc *sc, int qid, int idx) 3259 { 3260 /* TBD */ 3261 } 3262 3263 void 3264 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3265 uint16_t len) 3266 { 3267 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3268 3269 *w = htole16(id << 12 | (len + 8)); 3270 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3271 (caddr_t)w - sc->sched_dma.vaddr, sizeof (uint16_t), 3272 BUS_DMASYNC_PREWRITE); 3273 if (idx < IWN_SCHED_WINSZ) { 3274 *(w + IWN_TX_RING_COUNT) = *w; 3275 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3276 (caddr_t)(w + IWN_TX_RING_COUNT) - sc->sched_dma.vaddr, 3277 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 3278 } 3279 } 3280 3281 void 3282 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 3283 { 3284 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3285 3286 *w = (*w & htole16(0xf000)) | htole16(1); 3287 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3288 (caddr_t)w - sc->sched_dma.vaddr, sizeof (uint16_t), 3289 BUS_DMASYNC_PREWRITE); 3290 if (idx < IWN_SCHED_WINSZ) { 3291 *(w + IWN_TX_RING_COUNT) = *w; 3292 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3293 (caddr_t)(w + IWN_TX_RING_COUNT) - sc->sched_dma.vaddr, 3294 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 3295 } 3296 } 3297 3298 int 3299 iwn_rval2ridx(int rval) 3300 { 3301 int ridx; 3302 3303 for (ridx = 0; ridx < nitems(iwn_rates); ridx++) { 3304 if (rval == iwn_rates[ridx].rate) 3305 break; 3306 } 3307 3308 return ridx; 3309 } 3310 3311 int 3312 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 3313 { 3314 struct iwn_ops *ops = &sc->ops; 3315 struct ieee80211com *ic = &sc->sc_ic; 3316 struct iwn_node *wn = (void *)ni; 3317 struct iwn_tx_ring *ring; 3318 struct iwn_tx_desc *desc; 3319 struct iwn_tx_data *data; 3320 struct iwn_tx_cmd *cmd; 3321 struct iwn_cmd_data *tx; 3322 const struct iwn_rate *rinfo; 3323 struct ieee80211_frame *wh; 3324 struct ieee80211_key *k = NULL; 3325 enum ieee80211_edca_ac ac; 3326 int qid; 3327 uint32_t flags; 3328 uint16_t qos; 3329 u_int hdrlen; 3330 bus_dma_segment_t *seg; 3331 uint8_t *ivp, tid, ridx, txant, type, subtype; 3332 int i, totlen, hasqos, error, pad; 3333 3334 wh = mtod(m, struct ieee80211_frame *); 3335 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3336 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3337 if (type == IEEE80211_FC0_TYPE_CTL) 3338 hdrlen = sizeof(struct ieee80211_frame_min); 3339 else 3340 hdrlen = ieee80211_get_hdrlen(wh); 3341 3342 if ((hasqos = ieee80211_has_qos(wh))) { 3343 /* Select EDCA Access Category and TX ring for this frame. */ 3344 struct ieee80211_tx_ba *ba; 3345 qos = ieee80211_get_qos(wh); 3346 tid = qos & IEEE80211_QOS_TID; 3347 ac = ieee80211_up_to_ac(ic, tid); 3348 qid = ac; 3349 3350 /* If possible, put this frame on an aggregation queue. */ 3351 if (sc->sc_tx_ba[tid].wn == wn) { 3352 ba = &ni->ni_tx_ba[tid]; 3353 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 3354 ba->ba_state == IEEE80211_BA_AGREED) { 3355 qid = sc->first_agg_txq + tid; 3356 if (sc->qfullmsk & (1 << qid)) { 3357 m_freem(m); 3358 return ENOBUFS; 3359 } 3360 } 3361 } 3362 } else { 3363 qos = 0; 3364 tid = IWN_NONQOS_TID; 3365 ac = EDCA_AC_BE; 3366 qid = ac; 3367 } 3368 3369 ring = &sc->txq[qid]; 3370 desc = &ring->desc[ring->cur]; 3371 data = &ring->data[ring->cur]; 3372 3373 /* Choose a TX rate index. */ 3374 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3375 type != IEEE80211_FC0_TYPE_DATA) 3376 ridx = iwn_rval2ridx(ieee80211_min_basic_rate(ic)); 3377 else if (ic->ic_fixed_mcs != -1) 3378 ridx = sc->fixed_ridx; 3379 else if (ic->ic_fixed_rate != -1) 3380 ridx = sc->fixed_ridx; 3381 else { 3382 if (ni->ni_flags & IEEE80211_NODE_HT) 3383 ridx = iwn_mcs2ridx[ni->ni_txmcs]; 3384 else 3385 ridx = wn->ridx[ni->ni_txrate]; 3386 } 3387 rinfo = &iwn_rates[ridx]; 3388 #if NBPFILTER > 0 3389 if (sc->sc_drvbpf != NULL) { 3390 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3391 uint16_t chan_flags; 3392 3393 tap->wt_flags = 0; 3394 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 3395 chan_flags = ni->ni_chan->ic_flags; 3396 if (ic->ic_curmode != IEEE80211_MODE_11N) 3397 chan_flags &= ~IEEE80211_CHAN_HT; 3398 tap->wt_chan_flags = htole16(chan_flags); 3399 if ((ni->ni_flags & IEEE80211_NODE_HT) && 3400 !IEEE80211_IS_MULTICAST(wh->i_addr1) && 3401 type == IEEE80211_FC0_TYPE_DATA) { 3402 tap->wt_rate = (0x80 | ni->ni_txmcs); 3403 } else 3404 tap->wt_rate = rinfo->rate; 3405 if ((ic->ic_flags & IEEE80211_F_WEPON) && 3406 (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)) 3407 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3408 3409 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_txtap_len, 3410 m, BPF_DIRECTION_OUT); 3411 } 3412 #endif 3413 3414 totlen = m->m_pkthdr.len; 3415 3416 /* Encrypt the frame if need be. */ 3417 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 3418 /* Retrieve key for TX. */ 3419 k = ieee80211_get_txkey(ic, wh, ni); 3420 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 3421 /* Do software encryption. */ 3422 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 3423 return ENOBUFS; 3424 /* 802.11 header may have moved. */ 3425 wh = mtod(m, struct ieee80211_frame *); 3426 totlen = m->m_pkthdr.len; 3427 3428 } else /* HW appends CCMP MIC. */ 3429 totlen += IEEE80211_CCMP_HDRLEN; 3430 } 3431 3432 data->totlen = totlen; 3433 3434 /* Prepare TX firmware command. */ 3435 cmd = &ring->cmd[ring->cur]; 3436 cmd->code = IWN_CMD_TX_DATA; 3437 cmd->flags = 0; 3438 cmd->qid = ring->qid; 3439 cmd->idx = ring->cur; 3440 3441 tx = (struct iwn_cmd_data *)cmd->data; 3442 /* NB: No need to clear tx, all fields are reinitialized here. */ 3443 tx->scratch = 0; /* clear "scratch" area */ 3444 3445 flags = 0; 3446 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3447 /* Unicast frame, check if an ACK is expected. */ 3448 if (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 3449 IEEE80211_QOS_ACK_POLICY_NOACK) 3450 flags |= IWN_TX_NEED_ACK; 3451 } 3452 if (type == IEEE80211_FC0_TYPE_CTL && 3453 subtype == IEEE80211_FC0_SUBTYPE_BAR) { 3454 struct ieee80211_frame_min *mwh; 3455 uint8_t *barfrm; 3456 uint16_t ctl; 3457 mwh = mtod(m, struct ieee80211_frame_min *); 3458 barfrm = (uint8_t *)&mwh[1]; 3459 ctl = LE_READ_2(barfrm); 3460 tid = (ctl & IEEE80211_BA_TID_INFO_MASK) >> 3461 IEEE80211_BA_TID_INFO_SHIFT; 3462 flags |= (IWN_TX_NEED_ACK | IWN_TX_IMM_BA); 3463 } 3464 3465 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 3466 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 3467 3468 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 3469 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3470 /* NB: Group frames are sent using CCK in 802.11b/g/n (2GHz). */ 3471 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 3472 flags |= IWN_TX_NEED_RTS; 3473 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3474 ridx >= IWN_RIDX_OFDM6) { 3475 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3476 flags |= IWN_TX_NEED_CTS; 3477 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3478 flags |= IWN_TX_NEED_RTS; 3479 } 3480 3481 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 3482 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3483 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3484 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 3485 flags |= IWN_TX_NEED_PROTECTION; 3486 } else 3487 flags |= IWN_TX_FULL_TXOP; 3488 } 3489 } 3490 3491 if (type == IEEE80211_FC0_TYPE_CTL && 3492 subtype == IEEE80211_FC0_SUBTYPE_BAR) 3493 tx->id = wn->id; 3494 else if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3495 type != IEEE80211_FC0_TYPE_DATA) 3496 tx->id = sc->broadcast_id; 3497 else 3498 tx->id = wn->id; 3499 3500 if (type == IEEE80211_FC0_TYPE_MGT) { 3501 #ifndef IEEE80211_STA_ONLY 3502 /* Tell HW to set timestamp in probe responses. */ 3503 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3504 flags |= IWN_TX_INSERT_TSTAMP; 3505 #endif 3506 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3507 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3508 tx->timeout = htole16(3); 3509 else 3510 tx->timeout = htole16(2); 3511 } else 3512 tx->timeout = htole16(0); 3513 3514 if (hdrlen & 3) { 3515 /* First segment length must be a multiple of 4. */ 3516 flags |= IWN_TX_NEED_PADDING; 3517 pad = 4 - (hdrlen & 3); 3518 } else 3519 pad = 0; 3520 3521 tx->len = htole16(totlen); 3522 tx->tid = tid; 3523 tx->rts_ntries = 60; 3524 tx->data_ntries = 15; 3525 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3526 3527 if ((ni->ni_flags & IEEE80211_NODE_HT) && 3528 tx->id != sc->broadcast_id) 3529 tx->plcp = rinfo->ht_plcp; 3530 else 3531 tx->plcp = rinfo->plcp; 3532 3533 if ((ni->ni_flags & IEEE80211_NODE_HT) && 3534 tx->id != sc->broadcast_id) { 3535 tx->rflags = rinfo->ht_flags; 3536 if (ni->ni_htcaps & IEEE80211_HTCAP_SGI20) 3537 tx->rflags |= IWN_RFLAG_SGI; 3538 } 3539 else 3540 tx->rflags = rinfo->flags; 3541 if (tx->id == sc->broadcast_id || ic->ic_fixed_mcs != -1 || 3542 ic->ic_fixed_rate != -1) { 3543 /* Group or management frame, or fixed Tx rate. */ 3544 tx->linkq = 0; 3545 /* XXX Alternate between antenna A and B? */ 3546 txant = IWN_LSB(sc->txchainmask); 3547 tx->rflags |= IWN_RFLAG_ANT(txant); 3548 } else { 3549 tx->linkq = 0; /* initial index into firmware LQ retry table */ 3550 flags |= IWN_TX_LINKQ; /* enable multi-rate retry */ 3551 } 3552 /* Set physical address of "scratch area". */ 3553 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3554 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3555 3556 /* Copy 802.11 header in TX command. */ 3557 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3558 3559 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 3560 /* Trim 802.11 header and prepend CCMP IV. */ 3561 m_adj(m, hdrlen - IEEE80211_CCMP_HDRLEN); 3562 ivp = mtod(m, uint8_t *); 3563 k->k_tsc++; 3564 ivp[0] = k->k_tsc; 3565 ivp[1] = k->k_tsc >> 8; 3566 ivp[2] = 0; 3567 ivp[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3568 ivp[4] = k->k_tsc >> 16; 3569 ivp[5] = k->k_tsc >> 24; 3570 ivp[6] = k->k_tsc >> 32; 3571 ivp[7] = k->k_tsc >> 40; 3572 3573 tx->security = IWN_CIPHER_CCMP; 3574 if (qid >= sc->first_agg_txq) 3575 flags |= IWN_TX_AMPDU_CCMP; 3576 memcpy(tx->key, k->k_key, k->k_len); 3577 3578 /* TX scheduler includes CCMP MIC len w/5000 Series. */ 3579 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 3580 totlen += IEEE80211_CCMP_MICLEN; 3581 } else { 3582 /* Trim 802.11 header. */ 3583 m_adj(m, hdrlen); 3584 tx->security = 0; 3585 } 3586 tx->flags = htole32(flags); 3587 3588 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3589 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3590 if (error != 0 && error != EFBIG) { 3591 printf("%s: can't map mbuf (error %d)\n", 3592 sc->sc_dev.dv_xname, error); 3593 m_freem(m); 3594 return error; 3595 } 3596 if (error != 0) { 3597 /* Too many DMA segments, linearize mbuf. */ 3598 if (m_defrag(m, M_DONTWAIT)) { 3599 m_freem(m); 3600 return ENOBUFS; 3601 } 3602 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3603 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3604 if (error != 0) { 3605 printf("%s: can't map mbuf (error %d)\n", 3606 sc->sc_dev.dv_xname, error); 3607 m_freem(m); 3608 return error; 3609 } 3610 } 3611 3612 data->m = m; 3613 data->ni = ni; 3614 data->ampdu_txmcs = ni->ni_txmcs; /* updated upon Tx interrupt */ 3615 3616 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 3617 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 3618 3619 /* Fill TX descriptor. */ 3620 desc->nsegs = 1 + data->map->dm_nsegs; 3621 /* First DMA segment is used by the TX command. */ 3622 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3623 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3624 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3625 /* Other DMA segments are for data payload. */ 3626 seg = data->map->dm_segs; 3627 for (i = 1; i <= data->map->dm_nsegs; i++) { 3628 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3629 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3630 seg->ds_len << 4); 3631 seg++; 3632 } 3633 3634 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 3635 BUS_DMASYNC_PREWRITE); 3636 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3637 (caddr_t)cmd - ring->cmd_dma.vaddr, sizeof (*cmd), 3638 BUS_DMASYNC_PREWRITE); 3639 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3640 (caddr_t)desc - ring->desc_dma.vaddr, sizeof (*desc), 3641 BUS_DMASYNC_PREWRITE); 3642 3643 /* Update TX scheduler. */ 3644 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3645 3646 /* Kick TX ring. */ 3647 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3648 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3649 3650 /* Mark TX ring as full if we reach a certain threshold. */ 3651 if (++ring->queued > IWN_TX_RING_HIMARK) 3652 sc->qfullmsk |= 1 << ring->qid; 3653 3654 return 0; 3655 } 3656 3657 void 3658 iwn_start(struct ifnet *ifp) 3659 { 3660 struct iwn_softc *sc = ifp->if_softc; 3661 struct ieee80211com *ic = &sc->sc_ic; 3662 struct ieee80211_node *ni; 3663 struct mbuf *m; 3664 3665 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 3666 return; 3667 3668 for (;;) { 3669 if (sc->qfullmsk != 0) { 3670 ifq_set_oactive(&ifp->if_snd); 3671 break; 3672 } 3673 3674 /* Send pending management frames first. */ 3675 m = mq_dequeue(&ic->ic_mgtq); 3676 if (m != NULL) { 3677 ni = m->m_pkthdr.ph_cookie; 3678 goto sendit; 3679 } 3680 if (ic->ic_state != IEEE80211_S_RUN || 3681 (ic->ic_xflags & IEEE80211_F_TX_MGMT_ONLY)) 3682 break; 3683 3684 /* Encapsulate and send data frames. */ 3685 m = ifq_dequeue(&ifp->if_snd); 3686 if (m == NULL) 3687 break; 3688 #if NBPFILTER > 0 3689 if (ifp->if_bpf != NULL) 3690 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 3691 #endif 3692 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 3693 continue; 3694 sendit: 3695 #if NBPFILTER > 0 3696 if (ic->ic_rawbpf != NULL) 3697 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 3698 #endif 3699 if (iwn_tx(sc, m, ni) != 0) { 3700 ieee80211_release_node(ic, ni); 3701 ifp->if_oerrors++; 3702 continue; 3703 } 3704 3705 sc->sc_tx_timer = 5; 3706 ifp->if_timer = 1; 3707 } 3708 } 3709 3710 void 3711 iwn_watchdog(struct ifnet *ifp) 3712 { 3713 struct iwn_softc *sc = ifp->if_softc; 3714 3715 ifp->if_timer = 0; 3716 3717 if (sc->sc_tx_timer > 0) { 3718 if (--sc->sc_tx_timer == 0) { 3719 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 3720 iwn_stop(ifp); 3721 ifp->if_oerrors++; 3722 return; 3723 } 3724 ifp->if_timer = 1; 3725 } 3726 3727 ieee80211_watchdog(ifp); 3728 } 3729 3730 int 3731 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3732 { 3733 struct iwn_softc *sc = ifp->if_softc; 3734 struct ieee80211com *ic = &sc->sc_ic; 3735 int s, error = 0; 3736 3737 error = rw_enter(&sc->sc_rwlock, RW_WRITE | RW_INTR); 3738 if (error) 3739 return error; 3740 s = splnet(); 3741 3742 switch (cmd) { 3743 case SIOCSIFADDR: 3744 ifp->if_flags |= IFF_UP; 3745 /* FALLTHROUGH */ 3746 case SIOCSIFFLAGS: 3747 if (ifp->if_flags & IFF_UP) { 3748 if (!(ifp->if_flags & IFF_RUNNING)) 3749 error = iwn_init(ifp); 3750 } else { 3751 if (ifp->if_flags & IFF_RUNNING) 3752 iwn_stop(ifp); 3753 } 3754 break; 3755 3756 case SIOCS80211POWER: 3757 error = ieee80211_ioctl(ifp, cmd, data); 3758 if (error != ENETRESET) 3759 break; 3760 if (ic->ic_state == IEEE80211_S_RUN && 3761 sc->calib.state == IWN_CALIB_STATE_RUN) { 3762 if (ic->ic_flags & IEEE80211_F_PMGTON) 3763 error = iwn_set_pslevel(sc, 0, 3, 0); 3764 else /* back to CAM */ 3765 error = iwn_set_pslevel(sc, 0, 0, 0); 3766 } else { 3767 /* Defer until transition to IWN_CALIB_STATE_RUN. */ 3768 error = 0; 3769 } 3770 break; 3771 3772 default: 3773 error = ieee80211_ioctl(ifp, cmd, data); 3774 } 3775 3776 if (error == ENETRESET) { 3777 error = 0; 3778 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3779 (IFF_UP | IFF_RUNNING)) { 3780 iwn_stop(ifp); 3781 error = iwn_init(ifp); 3782 } 3783 } 3784 3785 splx(s); 3786 rw_exit_write(&sc->sc_rwlock); 3787 return error; 3788 } 3789 3790 /* 3791 * Send a command to the firmware. 3792 */ 3793 int 3794 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3795 { 3796 struct iwn_ops *ops = &sc->ops; 3797 struct iwn_tx_ring *ring = &sc->txq[4]; 3798 struct iwn_tx_desc *desc; 3799 struct iwn_tx_data *data; 3800 struct iwn_tx_cmd *cmd; 3801 struct mbuf *m; 3802 bus_addr_t paddr; 3803 int totlen, error; 3804 3805 desc = &ring->desc[ring->cur]; 3806 data = &ring->data[ring->cur]; 3807 totlen = 4 + size; 3808 3809 if (size > sizeof cmd->data) { 3810 /* Command is too large to fit in a descriptor. */ 3811 if (totlen > MCLBYTES) 3812 return EINVAL; 3813 MGETHDR(m, M_DONTWAIT, MT_DATA); 3814 if (m == NULL) 3815 return ENOMEM; 3816 if (totlen > MHLEN) { 3817 MCLGET(m, M_DONTWAIT); 3818 if (!(m->m_flags & M_EXT)) { 3819 m_freem(m); 3820 return ENOMEM; 3821 } 3822 } 3823 cmd = mtod(m, struct iwn_tx_cmd *); 3824 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3825 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3826 if (error != 0) { 3827 m_freem(m); 3828 return error; 3829 } 3830 data->m = m; 3831 paddr = data->map->dm_segs[0].ds_addr; 3832 } else { 3833 cmd = &ring->cmd[ring->cur]; 3834 paddr = data->cmd_paddr; 3835 } 3836 3837 cmd->code = code; 3838 cmd->flags = 0; 3839 cmd->qid = ring->qid; 3840 cmd->idx = ring->cur; 3841 memcpy(cmd->data, buf, size); 3842 3843 desc->nsegs = 1; 3844 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3845 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3846 3847 if (size > sizeof cmd->data) { 3848 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3849 BUS_DMASYNC_PREWRITE); 3850 } else { 3851 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3852 (caddr_t)cmd - ring->cmd_dma.vaddr, totlen, 3853 BUS_DMASYNC_PREWRITE); 3854 } 3855 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3856 (caddr_t)desc - ring->desc_dma.vaddr, sizeof (*desc), 3857 BUS_DMASYNC_PREWRITE); 3858 3859 /* Update TX scheduler. */ 3860 ops->update_sched(sc, ring->qid, ring->cur, 0, 0); 3861 3862 /* Kick command ring. */ 3863 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3864 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3865 3866 return async ? 0 : tsleep_nsec(desc, PCATCH, "iwncmd", SEC_TO_NSEC(1)); 3867 } 3868 3869 int 3870 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3871 { 3872 struct iwn4965_node_info hnode; 3873 caddr_t src, dst; 3874 3875 /* 3876 * We use the node structure for 5000 Series internally (it is 3877 * a superset of the one for 4965AGN). We thus copy the common 3878 * fields before sending the command. 3879 */ 3880 src = (caddr_t)node; 3881 dst = (caddr_t)&hnode; 3882 memcpy(dst, src, 48); 3883 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3884 memcpy(dst + 48, src + 72, 20); 3885 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3886 } 3887 3888 int 3889 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3890 { 3891 /* Direct mapping. */ 3892 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3893 } 3894 3895 int 3896 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3897 { 3898 struct ieee80211com *ic = &sc->sc_ic; 3899 struct iwn_node *wn = (void *)ni; 3900 struct iwn_cmd_link_quality linkq; 3901 const struct iwn_rate *rinfo; 3902 uint8_t txant; 3903 int i; 3904 3905 /* Use the first valid TX antenna. */ 3906 txant = IWN_LSB(sc->txchainmask); 3907 3908 memset(&linkq, 0, sizeof linkq); 3909 linkq.id = wn->id; 3910 linkq.antmsk_1stream = txant; 3911 linkq.antmsk_2stream = IWN_ANT_AB; 3912 linkq.ampdu_max = IWN_AMPDU_MAX; 3913 linkq.ampdu_threshold = 3; 3914 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3915 3916 i = 0; 3917 if (ni->ni_flags & IEEE80211_NODE_HT) { 3918 int txmcs; 3919 for (txmcs = ni->ni_txmcs; txmcs >= 0; txmcs--) { 3920 rinfo = &iwn_rates[iwn_mcs2ridx[txmcs]]; 3921 linkq.retry[i].plcp = rinfo->ht_plcp; 3922 linkq.retry[i].rflags = rinfo->ht_flags; 3923 3924 if (ni->ni_htcaps & IEEE80211_HTCAP_SGI20) 3925 linkq.retry[i].rflags |= IWN_RFLAG_SGI; 3926 3927 /* XXX set correct ant mask for MIMO rates here */ 3928 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3929 3930 if (++i >= IWN_MAX_TX_RETRIES) 3931 break; 3932 } 3933 } else { 3934 int txrate; 3935 for (txrate = ni->ni_txrate; txrate >= 0; txrate--) { 3936 rinfo = &iwn_rates[wn->ridx[txrate]]; 3937 linkq.retry[i].plcp = rinfo->plcp; 3938 linkq.retry[i].rflags = rinfo->flags; 3939 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3940 if (++i >= IWN_MAX_TX_RETRIES) 3941 break; 3942 } 3943 } 3944 3945 /* Fill the rest with the lowest basic rate. */ 3946 rinfo = &iwn_rates[iwn_rval2ridx(ieee80211_min_basic_rate(ic))]; 3947 while (i < IWN_MAX_TX_RETRIES) { 3948 linkq.retry[i].plcp = rinfo->plcp; 3949 linkq.retry[i].rflags = rinfo->flags; 3950 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3951 i++; 3952 } 3953 3954 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3955 } 3956 3957 /* 3958 * Broadcast node is used to send group-addressed and management frames. 3959 */ 3960 int 3961 iwn_add_broadcast_node(struct iwn_softc *sc, int async, int ridx) 3962 { 3963 struct iwn_ops *ops = &sc->ops; 3964 struct iwn_node_info node; 3965 struct iwn_cmd_link_quality linkq; 3966 const struct iwn_rate *rinfo; 3967 uint8_t txant; 3968 int i, error; 3969 3970 memset(&node, 0, sizeof node); 3971 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3972 node.id = sc->broadcast_id; 3973 DPRINTF(("adding broadcast node\n")); 3974 if ((error = ops->add_node(sc, &node, async)) != 0) 3975 return error; 3976 3977 /* Use the first valid TX antenna. */ 3978 txant = IWN_LSB(sc->txchainmask); 3979 3980 memset(&linkq, 0, sizeof linkq); 3981 linkq.id = sc->broadcast_id; 3982 linkq.antmsk_1stream = txant; 3983 linkq.antmsk_2stream = IWN_ANT_AB; 3984 linkq.ampdu_max = IWN_AMPDU_MAX_NO_AGG; 3985 linkq.ampdu_threshold = 3; 3986 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3987 3988 /* Use lowest mandatory bit-rate. */ 3989 rinfo = &iwn_rates[ridx]; 3990 linkq.retry[0].plcp = rinfo->plcp; 3991 linkq.retry[0].rflags = rinfo->flags; 3992 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3993 /* Use same bit-rate for all TX retries. */ 3994 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3995 linkq.retry[i].plcp = linkq.retry[0].plcp; 3996 linkq.retry[i].rflags = linkq.retry[0].rflags; 3997 } 3998 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3999 } 4000 4001 void 4002 iwn_updateedca(struct ieee80211com *ic) 4003 { 4004 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 4005 struct iwn_softc *sc = ic->ic_softc; 4006 struct iwn_edca_params cmd; 4007 int aci; 4008 4009 memset(&cmd, 0, sizeof cmd); 4010 cmd.flags = htole32(IWN_EDCA_UPDATE); 4011 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 4012 const struct ieee80211_edca_ac_params *ac = 4013 &ic->ic_edca_ac[aci]; 4014 cmd.ac[aci].aifsn = ac->ac_aifsn; 4015 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->ac_ecwmin)); 4016 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->ac_ecwmax)); 4017 cmd.ac[aci].txoplimit = 4018 htole16(IEEE80211_TXOP_TO_US(ac->ac_txoplimit)); 4019 } 4020 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4021 #undef IWN_EXP2 4022 } 4023 4024 void 4025 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 4026 { 4027 struct iwn_cmd_led led; 4028 4029 /* Clear microcode LED ownership. */ 4030 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 4031 4032 led.which = which; 4033 led.unit = htole32(10000); /* on/off in unit of 100ms */ 4034 led.off = off; 4035 led.on = on; 4036 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 4037 } 4038 4039 /* 4040 * Set the critical temperature at which the firmware will stop the radio 4041 * and notify us. 4042 */ 4043 int 4044 iwn_set_critical_temp(struct iwn_softc *sc) 4045 { 4046 struct iwn_critical_temp crit; 4047 int32_t temp; 4048 4049 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 4050 4051 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 4052 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 4053 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 4054 temp = IWN_CTOK(110); 4055 else 4056 temp = 110; 4057 memset(&crit, 0, sizeof crit); 4058 crit.tempR = htole32(temp); 4059 DPRINTF(("setting critical temperature to %d\n", temp)); 4060 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 4061 } 4062 4063 int 4064 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 4065 { 4066 struct iwn_cmd_timing cmd; 4067 uint64_t val, mod; 4068 4069 memset(&cmd, 0, sizeof cmd); 4070 memcpy(&cmd.tstamp, ni->ni_tstamp, sizeof (uint64_t)); 4071 cmd.bintval = htole16(ni->ni_intval); 4072 cmd.lintval = htole16(10); 4073 4074 /* Compute remaining time until next beacon. */ 4075 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 4076 mod = letoh64(cmd.tstamp) % val; 4077 cmd.binitval = htole32((uint32_t)(val - mod)); 4078 4079 DPRINTF(("timing bintval=%u, tstamp=%llu, init=%u\n", 4080 ni->ni_intval, letoh64(cmd.tstamp), (uint32_t)(val - mod))); 4081 4082 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 4083 } 4084 4085 void 4086 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 4087 { 4088 /* Adjust TX power if need be (delta >= 3 degC). */ 4089 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 4090 if (abs(temp - sc->temp) >= 3) { 4091 /* Record temperature of last calibration. */ 4092 sc->temp = temp; 4093 (void)iwn4965_set_txpower(sc, 1); 4094 } 4095 } 4096 4097 /* 4098 * Set TX power for current channel (each rate has its own power settings). 4099 * This function takes into account the regulatory information from EEPROM, 4100 * the current temperature and the current voltage. 4101 */ 4102 int 4103 iwn4965_set_txpower(struct iwn_softc *sc, int async) 4104 { 4105 /* Fixed-point arithmetic division using a n-bit fractional part. */ 4106 #define fdivround(a, b, n) \ 4107 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 4108 /* Linear interpolation. */ 4109 #define interpolate(x, x1, y1, x2, y2, n) \ 4110 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 4111 4112 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 4113 struct ieee80211com *ic = &sc->sc_ic; 4114 struct iwn_ucode_info *uc = &sc->ucode_info; 4115 struct ieee80211_channel *ch; 4116 struct iwn4965_cmd_txpower cmd; 4117 struct iwn4965_eeprom_chan_samples *chans; 4118 const uint8_t *rf_gain, *dsp_gain; 4119 int32_t vdiff, tdiff; 4120 int i, c, grp, maxpwr; 4121 uint8_t chan; 4122 4123 /* Retrieve current channel from last RXON. */ 4124 chan = sc->rxon.chan; 4125 DPRINTF(("setting TX power for channel %d\n", chan)); 4126 ch = &ic->ic_channels[chan]; 4127 4128 memset(&cmd, 0, sizeof cmd); 4129 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 4130 cmd.chan = chan; 4131 4132 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 4133 maxpwr = sc->maxpwr5GHz; 4134 rf_gain = iwn4965_rf_gain_5ghz; 4135 dsp_gain = iwn4965_dsp_gain_5ghz; 4136 } else { 4137 maxpwr = sc->maxpwr2GHz; 4138 rf_gain = iwn4965_rf_gain_2ghz; 4139 dsp_gain = iwn4965_dsp_gain_2ghz; 4140 } 4141 4142 /* Compute voltage compensation. */ 4143 vdiff = ((int32_t)letoh32(uc->volt) - sc->eeprom_voltage) / 7; 4144 if (vdiff > 0) 4145 vdiff *= 2; 4146 if (abs(vdiff) > 2) 4147 vdiff = 0; 4148 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 4149 vdiff, letoh32(uc->volt), sc->eeprom_voltage)); 4150 4151 /* Get channel attenuation group. */ 4152 if (chan <= 20) /* 1-20 */ 4153 grp = 4; 4154 else if (chan <= 43) /* 34-43 */ 4155 grp = 0; 4156 else if (chan <= 70) /* 44-70 */ 4157 grp = 1; 4158 else if (chan <= 124) /* 71-124 */ 4159 grp = 2; 4160 else /* 125-200 */ 4161 grp = 3; 4162 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 4163 4164 /* Get channel sub-band. */ 4165 for (i = 0; i < IWN_NBANDS; i++) 4166 if (sc->bands[i].lo != 0 && 4167 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 4168 break; 4169 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 4170 return EINVAL; 4171 chans = sc->bands[i].chans; 4172 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 4173 4174 for (c = 0; c < 2; c++) { 4175 uint8_t power, gain, temp; 4176 int maxchpwr, pwr, ridx, idx; 4177 4178 power = interpolate(chan, 4179 chans[0].num, chans[0].samples[c][1].power, 4180 chans[1].num, chans[1].samples[c][1].power, 1); 4181 gain = interpolate(chan, 4182 chans[0].num, chans[0].samples[c][1].gain, 4183 chans[1].num, chans[1].samples[c][1].gain, 1); 4184 temp = interpolate(chan, 4185 chans[0].num, chans[0].samples[c][1].temp, 4186 chans[1].num, chans[1].samples[c][1].temp, 1); 4187 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 4188 c, power, gain, temp)); 4189 4190 /* Compute temperature compensation. */ 4191 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 4192 DPRINTF(("temperature compensation=%d (current=%d, " 4193 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 4194 4195 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 4196 /* Convert dBm to half-dBm. */ 4197 maxchpwr = sc->maxpwr[chan] * 2; 4198 #ifdef notyet 4199 if (ridx > iwn_mcs2ridx[7] && ridx < iwn_mcs2ridx[16]) 4200 maxchpwr -= 6; /* MIMO 2T: -3dB */ 4201 #endif 4202 4203 pwr = maxpwr; 4204 4205 /* Adjust TX power based on rate. */ 4206 if ((ridx % 8) == 5) 4207 pwr -= 15; /* OFDM48: -7.5dB */ 4208 else if ((ridx % 8) == 6) 4209 pwr -= 17; /* OFDM54: -8.5dB */ 4210 else if ((ridx % 8) == 7) 4211 pwr -= 20; /* OFDM60: -10dB */ 4212 else 4213 pwr -= 10; /* Others: -5dB */ 4214 4215 /* Do not exceed channel max TX power. */ 4216 if (pwr > maxchpwr) 4217 pwr = maxchpwr; 4218 4219 idx = gain - (pwr - power) - tdiff - vdiff; 4220 if (ridx > iwn_mcs2ridx[7]) /* MIMO */ 4221 idx += (int32_t)letoh32(uc->atten[grp][c]); 4222 4223 if (cmd.band == 0) 4224 idx += 9; /* 5GHz */ 4225 if (ridx == IWN_RIDX_MAX) 4226 idx += 5; /* CCK */ 4227 4228 /* Make sure idx stays in a valid range. */ 4229 if (idx < 0) 4230 idx = 0; 4231 else if (idx > IWN4965_MAX_PWR_INDEX) 4232 idx = IWN4965_MAX_PWR_INDEX; 4233 4234 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 4235 c, ridx, idx)); 4236 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 4237 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 4238 } 4239 } 4240 4241 DPRINTF(("setting TX power for chan %d\n", chan)); 4242 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 4243 4244 #undef interpolate 4245 #undef fdivround 4246 } 4247 4248 int 4249 iwn5000_set_txpower(struct iwn_softc *sc, int async) 4250 { 4251 struct iwn5000_cmd_txpower cmd; 4252 4253 /* 4254 * TX power calibration is handled automatically by the firmware 4255 * for 5000 Series. 4256 */ 4257 memset(&cmd, 0, sizeof cmd); 4258 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 4259 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 4260 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 4261 DPRINTF(("setting TX power\n")); 4262 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 4263 } 4264 4265 /* 4266 * Retrieve the maximum RSSI (in dBm) among receivers. 4267 */ 4268 int 4269 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 4270 { 4271 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 4272 uint8_t mask, agc; 4273 int rssi; 4274 4275 mask = (letoh16(phy->antenna) >> 4) & IWN_ANT_ABC; 4276 agc = (letoh16(phy->agc) >> 7) & 0x7f; 4277 4278 rssi = 0; 4279 if (mask & IWN_ANT_A) 4280 rssi = MAX(rssi, phy->rssi[0]); 4281 if (mask & IWN_ANT_B) 4282 rssi = MAX(rssi, phy->rssi[2]); 4283 if (mask & IWN_ANT_C) 4284 rssi = MAX(rssi, phy->rssi[4]); 4285 4286 return rssi - agc - IWN_RSSI_TO_DBM; 4287 } 4288 4289 int 4290 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 4291 { 4292 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 4293 uint8_t agc; 4294 int rssi; 4295 4296 agc = (letoh32(phy->agc) >> 9) & 0x7f; 4297 4298 rssi = MAX(letoh16(phy->rssi[0]) & 0xff, 4299 letoh16(phy->rssi[1]) & 0xff); 4300 rssi = MAX(letoh16(phy->rssi[2]) & 0xff, rssi); 4301 4302 return rssi - agc - IWN_RSSI_TO_DBM; 4303 } 4304 4305 /* 4306 * Retrieve the average noise (in dBm) among receivers. 4307 */ 4308 int 4309 iwn_get_noise(const struct iwn_rx_general_stats *stats) 4310 { 4311 int i, total, nbant, noise; 4312 4313 total = nbant = 0; 4314 for (i = 0; i < 3; i++) { 4315 if ((noise = letoh32(stats->noise[i]) & 0xff) == 0) 4316 continue; 4317 total += noise; 4318 nbant++; 4319 } 4320 /* There should be at least one antenna but check anyway. */ 4321 return (nbant == 0) ? -127 : (total / nbant) - 107; 4322 } 4323 4324 /* 4325 * Compute temperature (in degC) from last received statistics. 4326 */ 4327 int 4328 iwn4965_get_temperature(struct iwn_softc *sc) 4329 { 4330 struct iwn_ucode_info *uc = &sc->ucode_info; 4331 int32_t r1, r2, r3, r4, temp; 4332 4333 r1 = letoh32(uc->temp[0].chan20MHz); 4334 r2 = letoh32(uc->temp[1].chan20MHz); 4335 r3 = letoh32(uc->temp[2].chan20MHz); 4336 r4 = letoh32(sc->rawtemp); 4337 4338 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 4339 return 0; 4340 4341 /* Sign-extend 23-bit R4 value to 32-bit. */ 4342 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 4343 /* Compute temperature in Kelvin. */ 4344 temp = (259 * (r4 - r2)) / (r3 - r1); 4345 temp = (temp * 97) / 100 + 8; 4346 4347 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 4348 return IWN_KTOC(temp); 4349 } 4350 4351 int 4352 iwn5000_get_temperature(struct iwn_softc *sc) 4353 { 4354 int32_t temp; 4355 4356 /* 4357 * Temperature is not used by the driver for 5000 Series because 4358 * TX power calibration is handled by firmware. 4359 */ 4360 temp = letoh32(sc->rawtemp); 4361 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 4362 temp = (temp / -5) + sc->temp_off; 4363 temp = IWN_KTOC(temp); 4364 } 4365 return temp; 4366 } 4367 4368 /* 4369 * Initialize sensitivity calibration state machine. 4370 */ 4371 int 4372 iwn_init_sensitivity(struct iwn_softc *sc) 4373 { 4374 struct iwn_ops *ops = &sc->ops; 4375 struct iwn_calib_state *calib = &sc->calib; 4376 uint32_t flags; 4377 int error; 4378 4379 /* Reset calibration state machine. */ 4380 memset(calib, 0, sizeof (*calib)); 4381 calib->state = IWN_CALIB_STATE_INIT; 4382 calib->cck_state = IWN_CCK_STATE_HIFA; 4383 /* Set initial correlation values. */ 4384 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 4385 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 4386 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 4387 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 4388 calib->cck_x4 = 125; 4389 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 4390 calib->energy_cck = sc->limits->energy_cck; 4391 4392 /* Write initial sensitivity. */ 4393 if ((error = iwn_send_sensitivity(sc)) != 0) 4394 return error; 4395 4396 /* Write initial gains. */ 4397 if ((error = ops->init_gains(sc)) != 0) 4398 return error; 4399 4400 /* Request statistics at each beacon interval. */ 4401 flags = 0; 4402 DPRINTFN(2, ("sending request for statistics\n")); 4403 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 4404 } 4405 4406 /* 4407 * Collect noise and RSSI statistics for the first 20 beacons received 4408 * after association and use them to determine connected antennas and 4409 * to set differential gains. 4410 */ 4411 void 4412 iwn_collect_noise(struct iwn_softc *sc, 4413 const struct iwn_rx_general_stats *stats) 4414 { 4415 struct iwn_ops *ops = &sc->ops; 4416 struct iwn_calib_state *calib = &sc->calib; 4417 uint32_t val; 4418 int i; 4419 4420 /* Accumulate RSSI and noise for all 3 antennas. */ 4421 for (i = 0; i < 3; i++) { 4422 calib->rssi[i] += letoh32(stats->rssi[i]) & 0xff; 4423 calib->noise[i] += letoh32(stats->noise[i]) & 0xff; 4424 } 4425 /* NB: We update differential gains only once after 20 beacons. */ 4426 if (++calib->nbeacons < 20) 4427 return; 4428 4429 /* Determine highest average RSSI. */ 4430 val = MAX(calib->rssi[0], calib->rssi[1]); 4431 val = MAX(calib->rssi[2], val); 4432 4433 /* Determine which antennas are connected. */ 4434 sc->chainmask = sc->rxchainmask; 4435 for (i = 0; i < 3; i++) 4436 if (val - calib->rssi[i] > 15 * 20) 4437 sc->chainmask &= ~(1 << i); 4438 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 4439 sc->rxchainmask, sc->chainmask)); 4440 4441 /* If none of the TX antennas are connected, keep at least one. */ 4442 if ((sc->chainmask & sc->txchainmask) == 0) 4443 sc->chainmask |= IWN_LSB(sc->txchainmask); 4444 4445 (void)ops->set_gains(sc); 4446 calib->state = IWN_CALIB_STATE_RUN; 4447 4448 #ifdef notyet 4449 /* XXX Disable RX chains with no antennas connected. */ 4450 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 4451 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4452 #endif 4453 4454 /* Enable power-saving mode if requested by user. */ 4455 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 4456 (void)iwn_set_pslevel(sc, 0, 3, 1); 4457 } 4458 4459 int 4460 iwn4965_init_gains(struct iwn_softc *sc) 4461 { 4462 struct iwn_phy_calib_gain cmd; 4463 4464 memset(&cmd, 0, sizeof cmd); 4465 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4466 /* Differential gains initially set to 0 for all 3 antennas. */ 4467 DPRINTF(("setting initial differential gains\n")); 4468 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4469 } 4470 4471 int 4472 iwn5000_init_gains(struct iwn_softc *sc) 4473 { 4474 struct iwn_phy_calib cmd; 4475 4476 memset(&cmd, 0, sizeof cmd); 4477 cmd.code = sc->reset_noise_gain; 4478 cmd.ngroups = 1; 4479 cmd.isvalid = 1; 4480 DPRINTF(("setting initial differential gains\n")); 4481 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4482 } 4483 4484 int 4485 iwn4965_set_gains(struct iwn_softc *sc) 4486 { 4487 struct iwn_calib_state *calib = &sc->calib; 4488 struct iwn_phy_calib_gain cmd; 4489 int i, delta, noise; 4490 4491 /* Get minimal noise among connected antennas. */ 4492 noise = INT_MAX; /* NB: There's at least one antenna. */ 4493 for (i = 0; i < 3; i++) 4494 if (sc->chainmask & (1 << i)) 4495 noise = MIN(calib->noise[i], noise); 4496 4497 memset(&cmd, 0, sizeof cmd); 4498 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4499 /* Set differential gains for connected antennas. */ 4500 for (i = 0; i < 3; i++) { 4501 if (sc->chainmask & (1 << i)) { 4502 /* Compute attenuation (in unit of 1.5dB). */ 4503 delta = (noise - (int32_t)calib->noise[i]) / 30; 4504 /* NB: delta <= 0 */ 4505 /* Limit to [-4.5dB,0]. */ 4506 cmd.gain[i] = MIN(abs(delta), 3); 4507 if (delta < 0) 4508 cmd.gain[i] |= 1 << 2; /* sign bit */ 4509 } 4510 } 4511 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 4512 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 4513 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4514 } 4515 4516 int 4517 iwn5000_set_gains(struct iwn_softc *sc) 4518 { 4519 struct iwn_calib_state *calib = &sc->calib; 4520 struct iwn_phy_calib_gain cmd; 4521 int i, ant, div, delta; 4522 4523 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 4524 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 4525 4526 memset(&cmd, 0, sizeof cmd); 4527 cmd.code = sc->noise_gain; 4528 cmd.ngroups = 1; 4529 cmd.isvalid = 1; 4530 /* 4531 * Get first available RX antenna as referential. 4532 * IWN_LSB() return values start with 1, but antenna gain array 4533 * cmd.gain[] and noise array calib->noise[] start with 0. 4534 */ 4535 ant = IWN_LSB(sc->rxchainmask) - 1; 4536 4537 /* Set differential gains for other antennas. */ 4538 for (i = ant + 1; i < 3; i++) { 4539 if (sc->chainmask & (1 << i)) { 4540 /* The delta is relative to antenna "ant". */ 4541 delta = ((int32_t)calib->noise[ant] - 4542 (int32_t)calib->noise[i]) / div; 4543 DPRINTF(("Ant[%d] vs. Ant[%d]: delta %d\n", ant, i, delta)); 4544 /* Limit to [-4.5dB,+4.5dB]. */ 4545 cmd.gain[i] = MIN(abs(delta), 3); 4546 if (delta < 0) 4547 cmd.gain[i] |= 1 << 2; /* sign bit */ 4548 DPRINTF(("Setting differential gains for antenna %d: %x\n", 4549 i, cmd.gain[i])); 4550 } 4551 } 4552 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4553 } 4554 4555 /* 4556 * Tune RF RX sensitivity based on the number of false alarms detected 4557 * during the last beacon period. 4558 */ 4559 void 4560 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4561 { 4562 #define inc(val, inc, max) \ 4563 if ((val) < (max)) { \ 4564 if ((val) < (max) - (inc)) \ 4565 (val) += (inc); \ 4566 else \ 4567 (val) = (max); \ 4568 needs_update = 1; \ 4569 } 4570 #define dec(val, dec, min) \ 4571 if ((val) > (min)) { \ 4572 if ((val) > (min) + (dec)) \ 4573 (val) -= (dec); \ 4574 else \ 4575 (val) = (min); \ 4576 needs_update = 1; \ 4577 } 4578 4579 const struct iwn_sensitivity_limits *limits = sc->limits; 4580 struct iwn_calib_state *calib = &sc->calib; 4581 uint32_t val, rxena, fa; 4582 uint32_t energy[3], energy_min; 4583 uint8_t noise[3], noise_ref; 4584 int i, needs_update = 0; 4585 4586 /* Check that we've been enabled long enough. */ 4587 if ((rxena = letoh32(stats->general.load)) == 0) 4588 return; 4589 4590 /* Compute number of false alarms since last call for OFDM. */ 4591 fa = letoh32(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4592 fa += letoh32(stats->ofdm.fa) - calib->fa_ofdm; 4593 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4594 4595 /* Save counters values for next call. */ 4596 calib->bad_plcp_ofdm = letoh32(stats->ofdm.bad_plcp); 4597 calib->fa_ofdm = letoh32(stats->ofdm.fa); 4598 4599 if (fa > 50 * rxena) { 4600 /* High false alarm count, decrease sensitivity. */ 4601 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 4602 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4603 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4604 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4605 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4606 4607 } else if (fa < 5 * rxena) { 4608 /* Low false alarm count, increase sensitivity. */ 4609 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 4610 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4611 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4612 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4613 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4614 } 4615 4616 /* Compute maximum noise among 3 receivers. */ 4617 for (i = 0; i < 3; i++) 4618 noise[i] = (letoh32(stats->general.noise[i]) >> 8) & 0xff; 4619 val = MAX(noise[0], noise[1]); 4620 val = MAX(noise[2], val); 4621 /* Insert it into our samples table. */ 4622 calib->noise_samples[calib->cur_noise_sample] = val; 4623 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4624 4625 /* Compute maximum noise among last 20 samples. */ 4626 noise_ref = calib->noise_samples[0]; 4627 for (i = 1; i < 20; i++) 4628 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4629 4630 /* Compute maximum energy among 3 receivers. */ 4631 for (i = 0; i < 3; i++) 4632 energy[i] = letoh32(stats->general.energy[i]); 4633 val = MIN(energy[0], energy[1]); 4634 val = MIN(energy[2], val); 4635 /* Insert it into our samples table. */ 4636 calib->energy_samples[calib->cur_energy_sample] = val; 4637 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4638 4639 /* Compute minimum energy among last 10 samples. */ 4640 energy_min = calib->energy_samples[0]; 4641 for (i = 1; i < 10; i++) 4642 energy_min = MAX(energy_min, calib->energy_samples[i]); 4643 energy_min += 6; 4644 4645 /* Compute number of false alarms since last call for CCK. */ 4646 fa = letoh32(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4647 fa += letoh32(stats->cck.fa) - calib->fa_cck; 4648 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4649 4650 /* Save counters values for next call. */ 4651 calib->bad_plcp_cck = letoh32(stats->cck.bad_plcp); 4652 calib->fa_cck = letoh32(stats->cck.fa); 4653 4654 if (fa > 50 * rxena) { 4655 /* High false alarm count, decrease sensitivity. */ 4656 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 4657 calib->cck_state = IWN_CCK_STATE_HIFA; 4658 calib->low_fa = 0; 4659 4660 if (calib->cck_x4 > 160) { 4661 calib->noise_ref = noise_ref; 4662 if (calib->energy_cck > 2) 4663 dec(calib->energy_cck, 2, energy_min); 4664 } 4665 if (calib->cck_x4 < 160) { 4666 calib->cck_x4 = 161; 4667 needs_update = 1; 4668 } else 4669 inc(calib->cck_x4, 3, limits->max_cck_x4); 4670 4671 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4672 4673 } else if (fa < 5 * rxena) { 4674 /* Low false alarm count, increase sensitivity. */ 4675 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 4676 calib->cck_state = IWN_CCK_STATE_LOFA; 4677 calib->low_fa++; 4678 4679 if (calib->cck_state != IWN_CCK_STATE_INIT && 4680 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4681 calib->low_fa > 100)) { 4682 inc(calib->energy_cck, 2, limits->min_energy_cck); 4683 dec(calib->cck_x4, 3, limits->min_cck_x4); 4684 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4685 } 4686 } else { 4687 /* Not worth to increase or decrease sensitivity. */ 4688 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 4689 calib->low_fa = 0; 4690 calib->noise_ref = noise_ref; 4691 4692 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4693 /* Previous interval had many false alarms. */ 4694 dec(calib->energy_cck, 8, energy_min); 4695 } 4696 calib->cck_state = IWN_CCK_STATE_INIT; 4697 } 4698 4699 if (needs_update) 4700 (void)iwn_send_sensitivity(sc); 4701 #undef dec 4702 #undef inc 4703 } 4704 4705 int 4706 iwn_send_sensitivity(struct iwn_softc *sc) 4707 { 4708 struct iwn_calib_state *calib = &sc->calib; 4709 struct iwn_enhanced_sensitivity_cmd cmd; 4710 int len; 4711 4712 memset(&cmd, 0, sizeof cmd); 4713 len = sizeof (struct iwn_sensitivity_cmd); 4714 cmd.which = IWN_SENSITIVITY_WORKTBL; 4715 /* OFDM modulation. */ 4716 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4717 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4718 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4719 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4720 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4721 cmd.energy_ofdm_th = htole16(62); 4722 /* CCK modulation. */ 4723 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4724 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4725 cmd.energy_cck = htole16(calib->energy_cck); 4726 /* Barker modulation: use default values. */ 4727 cmd.corr_barker = htole16(190); 4728 cmd.corr_barker_mrc = htole16(390); 4729 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 4730 goto send; 4731 /* Enhanced sensitivity settings. */ 4732 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 4733 cmd.ofdm_det_slope_mrc = htole16(668); 4734 cmd.ofdm_det_icept_mrc = htole16(4); 4735 cmd.ofdm_det_slope = htole16(486); 4736 cmd.ofdm_det_icept = htole16(37); 4737 cmd.cck_det_slope_mrc = htole16(853); 4738 cmd.cck_det_icept_mrc = htole16(4); 4739 cmd.cck_det_slope = htole16(476); 4740 cmd.cck_det_icept = htole16(99); 4741 send: 4742 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 4743 } 4744 4745 /* 4746 * Set STA mode power saving level (between 0 and 5). 4747 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4748 */ 4749 int 4750 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4751 { 4752 struct iwn_pmgt_cmd cmd; 4753 const struct iwn_pmgt *pmgt; 4754 uint32_t max, skip_dtim; 4755 pcireg_t reg; 4756 int i; 4757 4758 /* Select which PS parameters to use. */ 4759 if (dtim <= 2) 4760 pmgt = &iwn_pmgt[0][level]; 4761 else if (dtim <= 10) 4762 pmgt = &iwn_pmgt[1][level]; 4763 else 4764 pmgt = &iwn_pmgt[2][level]; 4765 4766 memset(&cmd, 0, sizeof cmd); 4767 if (level != 0) /* not CAM */ 4768 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4769 if (level == 5) 4770 cmd.flags |= htole16(IWN_PS_FAST_PD); 4771 /* Retrieve PCIe Active State Power Management (ASPM). */ 4772 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4773 sc->sc_cap_off + PCI_PCIE_LCSR); 4774 if (!(reg & PCI_PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4775 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4776 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4777 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4778 4779 if (dtim == 0) { 4780 dtim = 1; 4781 skip_dtim = 0; 4782 } else 4783 skip_dtim = pmgt->skip_dtim; 4784 if (skip_dtim != 0) { 4785 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4786 max = pmgt->intval[4]; 4787 if (max == (uint32_t)-1) 4788 max = dtim * (skip_dtim + 1); 4789 else if (max > dtim) 4790 max = (max / dtim) * dtim; 4791 } else 4792 max = dtim; 4793 for (i = 0; i < 5; i++) 4794 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 4795 4796 DPRINTF(("setting power saving level to %d\n", level)); 4797 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4798 } 4799 4800 int 4801 iwn_send_btcoex(struct iwn_softc *sc) 4802 { 4803 struct iwn_bluetooth cmd; 4804 4805 memset(&cmd, 0, sizeof cmd); 4806 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4807 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 4808 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 4809 DPRINTF(("configuring bluetooth coexistence\n")); 4810 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 4811 } 4812 4813 int 4814 iwn_send_advanced_btcoex(struct iwn_softc *sc) 4815 { 4816 static const uint32_t btcoex_3wire[12] = { 4817 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 4818 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 4819 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 4820 }; 4821 struct iwn_btcoex_priotable btprio; 4822 struct iwn_btcoex_prot btprot; 4823 int error, i; 4824 4825 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 4826 sc->hw_type == IWN_HW_REV_TYPE_135) { 4827 struct iwn2000_btcoex_config btconfig; 4828 4829 memset(&btconfig, 0, sizeof btconfig); 4830 btconfig.flags = IWN_BT_COEX6000_CHAN_INHIBITION | 4831 (IWN_BT_COEX6000_MODE_3W << IWN_BT_COEX6000_MODE_SHIFT) | 4832 IWN_BT_SYNC_2_BT_DISABLE; 4833 btconfig.max_kill = 5; 4834 btconfig.bt3_t7_timer = 1; 4835 btconfig.kill_ack = htole32(0xffff0000); 4836 btconfig.kill_cts = htole32(0xffff0000); 4837 btconfig.sample_time = 2; 4838 btconfig.bt3_t2_timer = 0xc; 4839 for (i = 0; i < 12; i++) 4840 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 4841 btconfig.valid = htole16(0xff); 4842 btconfig.prio_boost = htole32(0xf0); 4843 DPRINTF(("configuring advanced bluetooth coexistence\n")); 4844 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 4845 sizeof(btconfig), 1); 4846 if (error != 0) 4847 return (error); 4848 } else { 4849 struct iwn6000_btcoex_config btconfig; 4850 4851 memset(&btconfig, 0, sizeof btconfig); 4852 btconfig.flags = IWN_BT_COEX6000_CHAN_INHIBITION | 4853 (IWN_BT_COEX6000_MODE_3W << IWN_BT_COEX6000_MODE_SHIFT) | 4854 IWN_BT_SYNC_2_BT_DISABLE; 4855 btconfig.max_kill = 5; 4856 btconfig.bt3_t7_timer = 1; 4857 btconfig.kill_ack = htole32(0xffff0000); 4858 btconfig.kill_cts = htole32(0xffff0000); 4859 btconfig.sample_time = 2; 4860 btconfig.bt3_t2_timer = 0xc; 4861 for (i = 0; i < 12; i++) 4862 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 4863 btconfig.valid = htole16(0xff); 4864 btconfig.prio_boost = 0xf0; 4865 DPRINTF(("configuring advanced bluetooth coexistence\n")); 4866 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 4867 sizeof(btconfig), 1); 4868 if (error != 0) 4869 return (error); 4870 } 4871 4872 memset(&btprio, 0, sizeof btprio); 4873 btprio.calib_init1 = 0x6; 4874 btprio.calib_init2 = 0x7; 4875 btprio.calib_periodic_low1 = 0x2; 4876 btprio.calib_periodic_low2 = 0x3; 4877 btprio.calib_periodic_high1 = 0x4; 4878 btprio.calib_periodic_high2 = 0x5; 4879 btprio.dtim = 0x6; 4880 btprio.scan52 = 0x8; 4881 btprio.scan24 = 0xa; 4882 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 4883 1); 4884 if (error != 0) 4885 return (error); 4886 4887 /* Force BT state machine change */ 4888 memset(&btprot, 0, sizeof btprot); 4889 btprot.open = 1; 4890 btprot.type = 1; 4891 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 4892 if (error != 0) 4893 return (error); 4894 4895 btprot.open = 0; 4896 return (iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1)); 4897 } 4898 4899 int 4900 iwn5000_runtime_calib(struct iwn_softc *sc) 4901 { 4902 struct iwn5000_calib_config cmd; 4903 4904 memset(&cmd, 0, sizeof cmd); 4905 cmd.ucode.once.enable = 0xffffffff; 4906 cmd.ucode.once.start = IWN5000_CALIB_DC; 4907 DPRINTF(("configuring runtime calibration\n")); 4908 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 4909 } 4910 4911 int 4912 iwn_config(struct iwn_softc *sc) 4913 { 4914 struct iwn_ops *ops = &sc->ops; 4915 struct ieee80211com *ic = &sc->sc_ic; 4916 struct ifnet *ifp = &ic->ic_if; 4917 uint32_t txmask; 4918 uint16_t rxchain; 4919 int error, ridx; 4920 4921 /* Set radio temperature sensor offset. */ 4922 if (sc->hw_type == IWN_HW_REV_TYPE_6005) { 4923 error = iwn6000_temp_offset_calib(sc); 4924 if (error != 0) { 4925 printf("%s: could not set temperature offset\n", 4926 sc->sc_dev.dv_xname); 4927 return error; 4928 } 4929 } 4930 4931 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 4932 sc->hw_type == IWN_HW_REV_TYPE_2000 || 4933 sc->hw_type == IWN_HW_REV_TYPE_135 || 4934 sc->hw_type == IWN_HW_REV_TYPE_105) { 4935 error = iwn2000_temp_offset_calib(sc); 4936 if (error != 0) { 4937 printf("%s: could not set temperature offset\n", 4938 sc->sc_dev.dv_xname); 4939 return error; 4940 } 4941 } 4942 4943 if (sc->hw_type == IWN_HW_REV_TYPE_6050 || 4944 sc->hw_type == IWN_HW_REV_TYPE_6005) { 4945 /* Configure runtime DC calibration. */ 4946 error = iwn5000_runtime_calib(sc); 4947 if (error != 0) { 4948 printf("%s: could not configure runtime calibration\n", 4949 sc->sc_dev.dv_xname); 4950 return error; 4951 } 4952 } 4953 4954 /* Configure valid TX chains for >=5000 Series. */ 4955 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4956 txmask = htole32(sc->txchainmask); 4957 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 4958 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4959 sizeof txmask, 0); 4960 if (error != 0) { 4961 printf("%s: could not configure valid TX chains\n", 4962 sc->sc_dev.dv_xname); 4963 return error; 4964 } 4965 } 4966 4967 /* Configure bluetooth coexistence. */ 4968 if (sc->sc_flags & IWN_FLAG_ADV_BT_COEX) 4969 error = iwn_send_advanced_btcoex(sc); 4970 else 4971 error = iwn_send_btcoex(sc); 4972 if (error != 0) { 4973 printf("%s: could not configure bluetooth coexistence\n", 4974 sc->sc_dev.dv_xname); 4975 return error; 4976 } 4977 4978 /* Set mode, channel, RX filter and enable RX. */ 4979 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4980 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 4981 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 4982 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 4983 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 4984 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4985 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) { 4986 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4987 if (ic->ic_flags & IEEE80211_F_USEPROT) 4988 sc->rxon.flags |= htole32(IWN_RXON_TGG_PROT); 4989 DPRINTF(("%s: 2ghz prot 0x%x\n", __func__, 4990 le32toh(sc->rxon.flags))); 4991 } 4992 switch (ic->ic_opmode) { 4993 case IEEE80211_M_STA: 4994 sc->rxon.mode = IWN_MODE_STA; 4995 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4996 break; 4997 case IEEE80211_M_MONITOR: 4998 sc->rxon.mode = IWN_MODE_MONITOR; 4999 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 5000 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 5001 break; 5002 default: 5003 /* Should not get there. */ 5004 break; 5005 } 5006 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 5007 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 5008 sc->rxon.ht_single_mask = 0xff; 5009 sc->rxon.ht_dual_mask = 0xff; 5010 sc->rxon.ht_triple_mask = 0xff; 5011 rxchain = 5012 IWN_RXCHAIN_VALID(sc->rxchainmask) | 5013 IWN_RXCHAIN_MIMO_COUNT(sc->nrxchains) | 5014 IWN_RXCHAIN_IDLE_COUNT(sc->nrxchains); 5015 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 5016 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 5017 rxchain |= IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask); 5018 rxchain |= (IWN_RXCHAIN_DRIVER_FORCE | IWN_RXCHAIN_MIMO_FORCE); 5019 } 5020 sc->rxon.rxchain = htole16(rxchain); 5021 DPRINTF(("setting configuration\n")); 5022 DPRINTF(("%s: rxon chan %d flags %x cck %x ofdm %x rxchain %x\n", 5023 __func__, sc->rxon.chan, le32toh(sc->rxon.flags), sc->rxon.cck_mask, 5024 sc->rxon.ofdm_mask, sc->rxon.rxchain)); 5025 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 5026 if (error != 0) { 5027 printf("%s: RXON command failed\n", sc->sc_dev.dv_xname); 5028 return error; 5029 } 5030 5031 ridx = (sc->sc_ic.ic_curmode == IEEE80211_MODE_11A) ? 5032 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 5033 if ((error = iwn_add_broadcast_node(sc, 0, ridx)) != 0) { 5034 printf("%s: could not add broadcast node\n", 5035 sc->sc_dev.dv_xname); 5036 return error; 5037 } 5038 5039 /* Configuration has changed, set TX power accordingly. */ 5040 if ((error = ops->set_txpower(sc, 0)) != 0) { 5041 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 5042 return error; 5043 } 5044 5045 if ((error = iwn_set_critical_temp(sc)) != 0) { 5046 printf("%s: could not set critical temperature\n", 5047 sc->sc_dev.dv_xname); 5048 return error; 5049 } 5050 5051 /* Set power saving level to CAM during initialization. */ 5052 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 5053 printf("%s: could not set power saving level\n", 5054 sc->sc_dev.dv_xname); 5055 return error; 5056 } 5057 return 0; 5058 } 5059 5060 uint16_t 5061 iwn_get_active_dwell_time(struct iwn_softc *sc, 5062 uint16_t flags, uint8_t n_probes) 5063 { 5064 /* No channel? Default to 2GHz settings */ 5065 if (flags & IEEE80211_CHAN_2GHZ) { 5066 return (IWN_ACTIVE_DWELL_TIME_2GHZ + 5067 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1)); 5068 } 5069 5070 /* 5GHz dwell time */ 5071 return (IWN_ACTIVE_DWELL_TIME_5GHZ + 5072 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1)); 5073 } 5074 5075 /* 5076 * Limit the total dwell time to 85% of the beacon interval. 5077 * 5078 * Returns the dwell time in milliseconds. 5079 */ 5080 uint16_t 5081 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 5082 { 5083 struct ieee80211com *ic = &sc->sc_ic; 5084 struct ieee80211_node *ni = ic->ic_bss; 5085 int bintval = 0; 5086 5087 /* bintval is in TU (1.024mS) */ 5088 if (ni != NULL) 5089 bintval = ni->ni_intval; 5090 5091 /* 5092 * If it's non-zero, we should calculate the minimum of 5093 * it and the DWELL_BASE. 5094 * 5095 * XXX Yes, the math should take into account that bintval 5096 * is 1.024mS, not 1mS.. 5097 */ 5098 if (ic->ic_state == IEEE80211_S_RUN && bintval > 0) 5099 return (MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100))); 5100 5101 /* No association context? Default */ 5102 return dwell_time; 5103 } 5104 5105 uint16_t 5106 iwn_get_passive_dwell_time(struct iwn_softc *sc, uint16_t flags) 5107 { 5108 uint16_t passive; 5109 if (flags & IEEE80211_CHAN_2GHZ) { 5110 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 5111 } else { 5112 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 5113 } 5114 5115 /* Clamp to the beacon interval if we're associated */ 5116 return (iwn_limit_dwell(sc, passive)); 5117 } 5118 5119 int 5120 iwn_scan(struct iwn_softc *sc, uint16_t flags, int bgscan) 5121 { 5122 struct ieee80211com *ic = &sc->sc_ic; 5123 struct iwn_scan_hdr *hdr; 5124 struct iwn_cmd_data *tx; 5125 struct iwn_scan_essid *essid; 5126 struct iwn_scan_chan *chan; 5127 struct ieee80211_frame *wh; 5128 struct ieee80211_rateset *rs; 5129 struct ieee80211_channel *c; 5130 uint8_t *buf, *frm; 5131 uint16_t rxchain, dwell_active, dwell_passive; 5132 uint8_t txant; 5133 int buflen, error, is_active; 5134 5135 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 5136 if (buf == NULL) { 5137 printf("%s: could not allocate buffer for scan command\n", 5138 sc->sc_dev.dv_xname); 5139 return ENOMEM; 5140 } 5141 hdr = (struct iwn_scan_hdr *)buf; 5142 /* 5143 * Move to the next channel if no frames are received within 10ms 5144 * after sending the probe request. 5145 */ 5146 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 5147 hdr->quiet_threshold = htole16(1); /* min # of packets */ 5148 5149 if (bgscan) { 5150 int bintval; 5151 5152 /* Set maximum off-channel time. */ 5153 hdr->max_out = htole32(200 * 1024); 5154 5155 /* Configure scan pauses which service on-channel traffic. */ 5156 bintval = ic->ic_bss->ni_intval ? ic->ic_bss->ni_intval : 100; 5157 hdr->pause_scan = htole32(((100 / bintval) << 22) | 5158 ((100 % bintval) * 1024)); 5159 } 5160 5161 /* Select antennas for scanning. */ 5162 rxchain = 5163 IWN_RXCHAIN_VALID(sc->rxchainmask) | 5164 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 5165 IWN_RXCHAIN_DRIVER_FORCE; 5166 if ((flags & IEEE80211_CHAN_5GHZ) && 5167 sc->hw_type == IWN_HW_REV_TYPE_4965) { 5168 /* 5169 * On 4965 ant A and C must be avoided in 5GHz because of a 5170 * HW bug which causes very weak RSSI values being reported. 5171 */ 5172 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 5173 } else /* Use all available RX antennas. */ 5174 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 5175 hdr->rxchain = htole16(rxchain); 5176 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 5177 5178 tx = (struct iwn_cmd_data *)(hdr + 1); 5179 tx->flags = htole32(IWN_TX_AUTO_SEQ); 5180 tx->id = sc->broadcast_id; 5181 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 5182 5183 if (flags & IEEE80211_CHAN_5GHZ) { 5184 /* Send probe requests at 6Mbps. */ 5185 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 5186 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 5187 } else { 5188 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 5189 if (bgscan && sc->hw_type == IWN_HW_REV_TYPE_4965 && 5190 sc->rxon.chan > 14) { 5191 /* 5192 * 4965 firmware can crash when sending probe requests 5193 * with CCK rates while associated to a 5GHz AP. 5194 * Send probe requests at 6Mbps OFDM as a workaround. 5195 */ 5196 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 5197 } else { 5198 /* Send probe requests at 1Mbps. */ 5199 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 5200 tx->rflags = IWN_RFLAG_CCK; 5201 } 5202 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 5203 } 5204 /* Use the first valid TX antenna. */ 5205 txant = IWN_LSB(sc->txchainmask); 5206 tx->rflags |= IWN_RFLAG_ANT(txant); 5207 5208 /* 5209 * Only do active scanning if we're announcing a probe request 5210 * for a given SSID (or more, if we ever add it to the driver.) 5211 */ 5212 is_active = 0; 5213 5214 /* 5215 * If we're scanning for a specific SSID, add it to the command. 5216 */ 5217 essid = (struct iwn_scan_essid *)(tx + 1); 5218 if (ic->ic_des_esslen != 0) { 5219 essid[0].id = IEEE80211_ELEMID_SSID; 5220 essid[0].len = ic->ic_des_esslen; 5221 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 5222 5223 is_active = 1; 5224 } 5225 /* 5226 * Build a probe request frame. Most of the following code is a 5227 * copy & paste of what is done in net80211. 5228 */ 5229 wh = (struct ieee80211_frame *)(essid + 20); 5230 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 5231 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 5232 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 5233 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 5234 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 5235 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 5236 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 5237 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 5238 5239 frm = (uint8_t *)(wh + 1); 5240 frm = ieee80211_add_ssid(frm, NULL, 0); 5241 frm = ieee80211_add_rates(frm, rs); 5242 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 5243 frm = ieee80211_add_xrates(frm, rs); 5244 if (ic->ic_flags & IEEE80211_F_HTON) 5245 frm = ieee80211_add_htcaps(frm, ic); 5246 5247 /* Set length of probe request. */ 5248 tx->len = htole16(frm - (uint8_t *)wh); 5249 5250 /* 5251 * If active scanning is requested but a certain channel is 5252 * marked passive, we can do active scanning if we detect 5253 * transmissions. 5254 * 5255 * There is an issue with some firmware versions that triggers 5256 * a sysassert on a "good CRC threshold" of zero (== disabled), 5257 * on a radar channel even though this means that we should NOT 5258 * send probes. 5259 * 5260 * The "good CRC threshold" is the number of frames that we 5261 * need to receive during our dwell time on a channel before 5262 * sending out probes -- setting this to a huge value will 5263 * mean we never reach it, but at the same time work around 5264 * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER 5265 * here instead of IWN_GOOD_CRC_TH_DISABLED. 5266 * 5267 * This was fixed in later versions along with some other 5268 * scan changes, and the threshold behaves as a flag in those 5269 * versions. 5270 */ 5271 5272 /* 5273 * If we're doing active scanning, set the crc_threshold 5274 * to a suitable value. This is different to active veruss 5275 * passive scanning depending upon the channel flags; the 5276 * firmware will obey that particular check for us. 5277 */ 5278 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 5279 hdr->crc_threshold = is_active ? 5280 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 5281 else 5282 hdr->crc_threshold = is_active ? 5283 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 5284 5285 chan = (struct iwn_scan_chan *)frm; 5286 for (c = &ic->ic_channels[1]; 5287 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 5288 if ((c->ic_flags & flags) != flags) 5289 continue; 5290 5291 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 5292 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 5293 chan->flags = 0; 5294 if (ic->ic_des_esslen != 0) 5295 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 5296 5297 if (c->ic_flags & IEEE80211_CHAN_PASSIVE) 5298 chan->flags |= htole32(IWN_CHAN_PASSIVE); 5299 else 5300 chan->flags |= htole32(IWN_CHAN_ACTIVE); 5301 5302 /* 5303 * Calculate the active/passive dwell times. 5304 */ 5305 5306 dwell_active = iwn_get_active_dwell_time(sc, flags, is_active); 5307 dwell_passive = iwn_get_passive_dwell_time(sc, flags); 5308 5309 /* Make sure they're valid */ 5310 if (dwell_passive <= dwell_active) 5311 dwell_passive = dwell_active + 1; 5312 5313 chan->active = htole16(dwell_active); 5314 chan->passive = htole16(dwell_passive); 5315 5316 chan->dsp_gain = 0x6e; 5317 if (IEEE80211_IS_CHAN_5GHZ(c)) { 5318 chan->rf_gain = 0x3b; 5319 } else { 5320 chan->rf_gain = 0x28; 5321 } 5322 hdr->nchan++; 5323 chan++; 5324 } 5325 5326 buflen = (uint8_t *)chan - buf; 5327 hdr->len = htole16(buflen); 5328 5329 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 5330 if (error == 0) { 5331 /* 5332 * The current mode might have been fixed during association. 5333 * Ensure all channels get scanned. 5334 */ 5335 if (IFM_MODE(ic->ic_media.ifm_cur->ifm_media) == IFM_AUTO) 5336 ieee80211_setmode(ic, IEEE80211_MODE_AUTO); 5337 5338 sc->sc_flags |= IWN_FLAG_SCANNING; 5339 if (bgscan) 5340 sc->sc_flags |= IWN_FLAG_BGSCAN; 5341 } 5342 free(buf, M_DEVBUF, IWN_SCAN_MAXSZ); 5343 return error; 5344 } 5345 5346 void 5347 iwn_scan_abort(struct iwn_softc *sc) 5348 { 5349 iwn_cmd(sc, IWN_CMD_SCAN_ABORT, NULL, 0, 1); 5350 5351 /* XXX Cannot wait for status response in interrupt context. */ 5352 DELAY(100); 5353 5354 sc->sc_flags &= ~IWN_FLAG_SCANNING; 5355 sc->sc_flags &= ~IWN_FLAG_BGSCAN; 5356 } 5357 5358 int 5359 iwn_bgscan(struct ieee80211com *ic) 5360 { 5361 struct iwn_softc *sc = ic->ic_softc; 5362 int error; 5363 5364 if (sc->sc_flags & IWN_FLAG_SCANNING) 5365 return 0; 5366 5367 error = iwn_scan(sc, IEEE80211_CHAN_2GHZ, 1); 5368 if (error) 5369 printf("%s: could not initiate background scan\n", 5370 sc->sc_dev.dv_xname); 5371 return error; 5372 } 5373 5374 int 5375 iwn_auth(struct iwn_softc *sc, int arg) 5376 { 5377 struct iwn_ops *ops = &sc->ops; 5378 struct ieee80211com *ic = &sc->sc_ic; 5379 struct ieee80211_node *ni = ic->ic_bss; 5380 int error, ridx; 5381 int bss_switch = 5382 (!IEEE80211_ADDR_EQ(sc->bss_node_addr, etheranyaddr) && 5383 !IEEE80211_ADDR_EQ(sc->bss_node_addr, ni->ni_macaddr)); 5384 5385 /* Update adapter configuration. */ 5386 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 5387 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5388 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5389 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) { 5390 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5391 if (ic->ic_flags & IEEE80211_F_USEPROT) 5392 sc->rxon.flags |= htole32(IWN_RXON_TGG_PROT); 5393 DPRINTF(("%s: 2ghz prot 0x%x\n", __func__, 5394 le32toh(sc->rxon.flags))); 5395 } 5396 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5397 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5398 else 5399 sc->rxon.flags &= ~htole32(IWN_RXON_SHSLOT); 5400 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5401 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5402 else 5403 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE); 5404 switch (ic->ic_curmode) { 5405 case IEEE80211_MODE_11A: 5406 sc->rxon.cck_mask = 0; 5407 sc->rxon.ofdm_mask = 0x15; 5408 break; 5409 case IEEE80211_MODE_11B: 5410 sc->rxon.cck_mask = 0x03; 5411 sc->rxon.ofdm_mask = 0; 5412 break; 5413 default: /* Assume 802.11b/g/n. */ 5414 sc->rxon.cck_mask = 0x0f; 5415 sc->rxon.ofdm_mask = 0x15; 5416 } 5417 DPRINTF(("%s: rxon chan %d flags %x cck %x ofdm %x\n", __func__, 5418 sc->rxon.chan, le32toh(sc->rxon.flags), sc->rxon.cck_mask, 5419 sc->rxon.ofdm_mask)); 5420 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5421 if (error != 0) { 5422 printf("%s: RXON command failed\n", sc->sc_dev.dv_xname); 5423 return error; 5424 } 5425 5426 /* Configuration has changed, set TX power accordingly. */ 5427 if ((error = ops->set_txpower(sc, 1)) != 0) { 5428 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 5429 return error; 5430 } 5431 /* 5432 * Reconfiguring RXON clears the firmware nodes table so we must 5433 * add the broadcast node again. 5434 */ 5435 ridx = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 5436 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 5437 if ((error = iwn_add_broadcast_node(sc, 1, ridx)) != 0) { 5438 printf("%s: could not add broadcast node\n", 5439 sc->sc_dev.dv_xname); 5440 return error; 5441 } 5442 5443 /* 5444 * Make sure the firmware gets to see a beacon before we send 5445 * the auth request. Otherwise the Tx attempt can fail due to 5446 * the firmware's built-in regulatory domain enforcement. 5447 * Delaying here for every incoming deauth frame can result in a DoS. 5448 * Don't delay if we're here because of an incoming frame (arg != -1) 5449 * or if we're already waiting for a response (ic_mgt_timer != 0). 5450 * If we are switching APs after a background scan then net80211 has 5451 * just faked the reception of a deauth frame from our old AP, so it 5452 * is safe to delay in that case. 5453 */ 5454 if ((arg == -1 || bss_switch) && ic->ic_mgt_timer == 0) 5455 DELAY(ni->ni_intval * 3 * IEEE80211_DUR_TU); 5456 5457 /* We can now clear the cached address of our previous AP. */ 5458 memset(sc->bss_node_addr, 0, sizeof(sc->bss_node_addr)); 5459 5460 return 0; 5461 } 5462 5463 int 5464 iwn_run(struct iwn_softc *sc) 5465 { 5466 struct iwn_ops *ops = &sc->ops; 5467 struct ieee80211com *ic = &sc->sc_ic; 5468 struct ieee80211_node *ni = ic->ic_bss; 5469 struct iwn_node *wn = (void *)ni; 5470 struct iwn_node_info node; 5471 int error; 5472 5473 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 5474 /* Link LED blinks while monitoring. */ 5475 iwn_set_led(sc, IWN_LED_LINK, 50, 50); 5476 return 0; 5477 } 5478 if ((error = iwn_set_timing(sc, ni)) != 0) { 5479 printf("%s: could not set timing\n", sc->sc_dev.dv_xname); 5480 return error; 5481 } 5482 5483 /* Update adapter configuration. */ 5484 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 5485 /* Short preamble and slot time are negotiated when associating. */ 5486 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 5487 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5488 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5489 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5490 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5491 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 5492 5493 /* HT is negotiated when associating. */ 5494 if (ni->ni_flags & IEEE80211_NODE_HT) { 5495 enum ieee80211_htprot htprot = 5496 (ni->ni_htop1 & IEEE80211_HTOP1_PROT_MASK); 5497 DPRINTF(("%s: htprot = %d\n", __func__, htprot)); 5498 sc->rxon.flags |= htole32(IWN_RXON_HT_PROTMODE(htprot)); 5499 } else 5500 sc->rxon.flags &= ~htole32(IWN_RXON_HT_PROTMODE(3)); 5501 5502 if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)) { 5503 /* 11a or 11n 5GHz */ 5504 sc->rxon.cck_mask = 0; 5505 sc->rxon.ofdm_mask = 0x15; 5506 } else if (ni->ni_flags & IEEE80211_NODE_HT) { 5507 /* 11n 2GHz */ 5508 sc->rxon.cck_mask = 0x0f; 5509 sc->rxon.ofdm_mask = 0x15; 5510 } else { 5511 if (ni->ni_rates.rs_nrates == 4) { 5512 /* 11b */ 5513 sc->rxon.cck_mask = 0x03; 5514 sc->rxon.ofdm_mask = 0; 5515 } else { 5516 /* assume 11g */ 5517 sc->rxon.cck_mask = 0x0f; 5518 sc->rxon.ofdm_mask = 0x15; 5519 } 5520 } 5521 DPRINTF(("%s: rxon chan %d flags %x cck %x ofdm %x\n", __func__, 5522 sc->rxon.chan, le32toh(sc->rxon.flags), sc->rxon.cck_mask, 5523 sc->rxon.ofdm_mask)); 5524 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5525 if (error != 0) { 5526 printf("%s: could not update configuration\n", 5527 sc->sc_dev.dv_xname); 5528 return error; 5529 } 5530 5531 /* Configuration has changed, set TX power accordingly. */ 5532 if ((error = ops->set_txpower(sc, 1)) != 0) { 5533 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 5534 return error; 5535 } 5536 5537 /* Fake a join to initialize the TX rate. */ 5538 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 5539 iwn_newassoc(ic, ni, 1); 5540 5541 /* Add BSS node. */ 5542 memset(&node, 0, sizeof node); 5543 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 5544 node.id = IWN_ID_BSS; 5545 if (ni->ni_flags & IEEE80211_NODE_HT) { 5546 node.htmask = (IWN_AMDPU_SIZE_FACTOR_MASK | 5547 IWN_AMDPU_DENSITY_MASK); 5548 node.htflags = htole32( 5549 IWN_AMDPU_SIZE_FACTOR( 5550 (ic->ic_ampdu_params & IEEE80211_AMPDU_PARAM_LE)) | 5551 IWN_AMDPU_DENSITY( 5552 (ic->ic_ampdu_params & IEEE80211_AMPDU_PARAM_SS) >> 2)); 5553 } 5554 DPRINTF(("adding BSS node\n")); 5555 error = ops->add_node(sc, &node, 1); 5556 if (error != 0) { 5557 printf("%s: could not add BSS node\n", sc->sc_dev.dv_xname); 5558 return error; 5559 } 5560 5561 /* Cache address of AP in case it changes after a background scan. */ 5562 IEEE80211_ADDR_COPY(sc->bss_node_addr, ni->ni_macaddr); 5563 5564 DPRINTF(("setting link quality for node %d\n", node.id)); 5565 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 5566 printf("%s: could not setup link quality for node %d\n", 5567 sc->sc_dev.dv_xname, node.id); 5568 return error; 5569 } 5570 5571 if ((error = iwn_init_sensitivity(sc)) != 0) { 5572 printf("%s: could not set sensitivity\n", 5573 sc->sc_dev.dv_xname); 5574 return error; 5575 } 5576 /* Start periodic calibration timer. */ 5577 sc->calib.state = IWN_CALIB_STATE_ASSOC; 5578 sc->calib_cnt = 0; 5579 timeout_add_msec(&sc->calib_to, 500); 5580 5581 ieee80211_ra_node_init(&wn->rn); 5582 5583 /* Link LED always on while associated. */ 5584 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 5585 return 0; 5586 } 5587 5588 /* 5589 * We support CCMP hardware encryption/decryption of unicast frames only. 5590 * HW support for TKIP really sucks. We should let TKIP die anyway. 5591 */ 5592 int 5593 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 5594 struct ieee80211_key *k) 5595 { 5596 struct iwn_softc *sc = ic->ic_softc; 5597 struct iwn_ops *ops = &sc->ops; 5598 struct iwn_node *wn = (void *)ni; 5599 struct iwn_node_info node; 5600 uint16_t kflags; 5601 5602 if ((k->k_flags & IEEE80211_KEY_GROUP) || 5603 k->k_cipher != IEEE80211_CIPHER_CCMP) 5604 return ieee80211_set_key(ic, ni, k); 5605 5606 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 5607 if (k->k_flags & IEEE80211_KEY_GROUP) 5608 kflags |= IWN_KFLAG_GROUP; 5609 5610 memset(&node, 0, sizeof node); 5611 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 5612 sc->broadcast_id : wn->id; 5613 node.control = IWN_NODE_UPDATE; 5614 node.flags = IWN_FLAG_SET_KEY; 5615 node.kflags = htole16(kflags); 5616 node.kid = k->k_id; 5617 memcpy(node.key, k->k_key, k->k_len); 5618 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 5619 return ops->add_node(sc, &node, 1); 5620 } 5621 5622 void 5623 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 5624 struct ieee80211_key *k) 5625 { 5626 struct iwn_softc *sc = ic->ic_softc; 5627 struct iwn_ops *ops = &sc->ops; 5628 struct iwn_node *wn = (void *)ni; 5629 struct iwn_node_info node; 5630 5631 if ((k->k_flags & IEEE80211_KEY_GROUP) || 5632 k->k_cipher != IEEE80211_CIPHER_CCMP) { 5633 /* See comment about other ciphers above. */ 5634 ieee80211_delete_key(ic, ni, k); 5635 return; 5636 } 5637 if (ic->ic_state != IEEE80211_S_RUN) 5638 return; /* Nothing to do. */ 5639 memset(&node, 0, sizeof node); 5640 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 5641 sc->broadcast_id : wn->id; 5642 node.control = IWN_NODE_UPDATE; 5643 node.flags = IWN_FLAG_SET_KEY; 5644 node.kflags = htole16(IWN_KFLAG_INVALID); 5645 node.kid = 0xff; 5646 DPRINTF(("delete keys for node %d\n", node.id)); 5647 (void)ops->add_node(sc, &node, 1); 5648 } 5649 5650 void 5651 iwn_updateprot(struct ieee80211com *ic) 5652 { 5653 struct iwn_softc *sc = ic->ic_softc; 5654 enum ieee80211_htprot htprot; 5655 5656 if (ic->ic_state != IEEE80211_S_RUN) 5657 return; 5658 5659 /* Update ERP protection setting. */ 5660 if (ic->ic_flags & IEEE80211_F_USEPROT) 5661 sc->rxon.flags |= htole32(IWN_RXON_TGG_PROT); 5662 else 5663 sc->rxon.flags &= ~htole32(IWN_RXON_TGG_PROT); 5664 5665 /* Update HT protection mode setting. */ 5666 htprot = (ic->ic_bss->ni_htop1 & IEEE80211_HTOP1_PROT_MASK) >> 5667 IEEE80211_HTOP1_PROT_SHIFT; 5668 sc->rxon.flags &= ~htole32(IWN_RXON_HT_PROTMODE(3)); 5669 sc->rxon.flags |= htole32(IWN_RXON_HT_PROTMODE(htprot)); 5670 5671 iwn_update_rxon(sc); 5672 } 5673 5674 void 5675 iwn_updateslot(struct ieee80211com *ic) 5676 { 5677 struct iwn_softc *sc = ic->ic_softc; 5678 5679 if (ic->ic_state != IEEE80211_S_RUN) 5680 return; 5681 5682 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5683 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5684 else 5685 sc->rxon.flags &= ~htole32(IWN_RXON_SHSLOT); 5686 5687 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5688 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5689 else 5690 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE); 5691 5692 iwn_update_rxon(sc); 5693 } 5694 void 5695 iwn_update_rxon(struct iwn_softc *sc) 5696 { 5697 struct ieee80211com *ic = &sc->sc_ic; 5698 struct iwn_ops *ops = &sc->ops; 5699 struct iwn_rxon_assoc rxon_assoc; 5700 int s, error; 5701 5702 /* Update RXON config. */ 5703 memset(&rxon_assoc, 0, sizeof(rxon_assoc)); 5704 rxon_assoc.flags = sc->rxon.flags; 5705 rxon_assoc.filter = sc->rxon.filter; 5706 rxon_assoc.ofdm_mask = sc->rxon.ofdm_mask; 5707 rxon_assoc.cck_mask = sc->rxon.cck_mask; 5708 rxon_assoc.ht_single_mask = sc->rxon.ht_single_mask; 5709 rxon_assoc.ht_dual_mask = sc->rxon.ht_dual_mask; 5710 rxon_assoc.ht_triple_mask = sc->rxon.ht_triple_mask; 5711 rxon_assoc.rxchain = sc->rxon.rxchain; 5712 rxon_assoc.acquisition = sc->rxon.acquisition; 5713 5714 s = splnet(); 5715 5716 error = iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &rxon_assoc, 5717 sizeof(rxon_assoc), 1); 5718 if (error != 0) 5719 printf("%s: RXON_ASSOC command failed\n", sc->sc_dev.dv_xname); 5720 5721 DELAY(100); 5722 5723 /* All RXONs wipe the firmware's txpower table. Restore it. */ 5724 error = ops->set_txpower(sc, 1); 5725 if (error != 0) 5726 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 5727 5728 DELAY(100); 5729 5730 /* Restore power saving level */ 5731 if (ic->ic_flags & IEEE80211_F_PMGTON) 5732 error = iwn_set_pslevel(sc, 0, 3, 1); 5733 else 5734 error = iwn_set_pslevel(sc, 0, 0, 1); 5735 if (error != 0) 5736 printf("%s: could not set PS level\n", sc->sc_dev.dv_xname); 5737 5738 splx(s); 5739 } 5740 5741 /* 5742 * This function is called by upper layer when an ADDBA request is received 5743 * from another STA and before the ADDBA response is sent. 5744 */ 5745 int 5746 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5747 uint8_t tid) 5748 { 5749 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 5750 struct iwn_softc *sc = ic->ic_softc; 5751 struct iwn_ops *ops = &sc->ops; 5752 struct iwn_node *wn = (void *)ni; 5753 struct iwn_node_info node; 5754 5755 memset(&node, 0, sizeof node); 5756 node.id = wn->id; 5757 node.control = IWN_NODE_UPDATE; 5758 node.flags = IWN_FLAG_SET_ADDBA; 5759 node.addba_tid = tid; 5760 node.addba_ssn = htole16(ba->ba_winstart); 5761 DPRINTF(("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 5762 ba->ba_winstart)); 5763 /* XXX async command, so firmware may still fail to add BA agreement */ 5764 return ops->add_node(sc, &node, 1); 5765 } 5766 5767 /* 5768 * This function is called by upper layer on teardown of an HT-immediate 5769 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 5770 */ 5771 void 5772 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5773 uint8_t tid) 5774 { 5775 struct iwn_softc *sc = ic->ic_softc; 5776 struct iwn_ops *ops = &sc->ops; 5777 struct iwn_node *wn = (void *)ni; 5778 struct iwn_node_info node; 5779 5780 memset(&node, 0, sizeof node); 5781 node.id = wn->id; 5782 node.control = IWN_NODE_UPDATE; 5783 node.flags = IWN_FLAG_SET_DELBA; 5784 node.delba_tid = tid; 5785 DPRINTF(("DELBA RA=%d TID=%d\n", wn->id, tid)); 5786 (void)ops->add_node(sc, &node, 1); 5787 } 5788 5789 /* 5790 * This function is called by upper layer when an ADDBA response is received 5791 * from another STA. 5792 */ 5793 int 5794 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5795 uint8_t tid) 5796 { 5797 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5798 struct iwn_softc *sc = ic->ic_softc; 5799 struct iwn_ops *ops = &sc->ops; 5800 struct iwn_node *wn = (void *)ni; 5801 struct iwn_node_info node; 5802 int qid = sc->first_agg_txq + tid; 5803 int error; 5804 5805 /* Ensure we can map this TID to an aggregation queue. */ 5806 if (tid >= IWN_NUM_AMPDU_TID || ba->ba_winsize > IWN_SCHED_WINSZ || 5807 qid > sc->ntxqs || (sc->agg_queue_mask & (1 << qid))) 5808 return ENOSPC; 5809 5810 /* Enable TX for the specified RA/TID. */ 5811 wn->disable_tid &= ~(1 << tid); 5812 memset(&node, 0, sizeof node); 5813 node.id = wn->id; 5814 node.control = IWN_NODE_UPDATE; 5815 node.flags = IWN_FLAG_SET_DISABLE_TID; 5816 node.disable_tid = htole16(wn->disable_tid); 5817 error = ops->add_node(sc, &node, 1); 5818 if (error != 0) 5819 return error; 5820 5821 if ((error = iwn_nic_lock(sc)) != 0) 5822 return error; 5823 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 5824 iwn_nic_unlock(sc); 5825 5826 sc->agg_queue_mask |= (1 << qid); 5827 sc->sc_tx_ba[tid].wn = wn; 5828 ba->ba_bitmap = 0; 5829 5830 return 0; 5831 } 5832 5833 void 5834 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5835 uint8_t tid) 5836 { 5837 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5838 struct iwn_softc *sc = ic->ic_softc; 5839 struct iwn_ops *ops = &sc->ops; 5840 int qid = sc->first_agg_txq + tid; 5841 struct iwn_node *wn = (void *)ni; 5842 struct iwn_node_info node; 5843 5844 /* Discard all frames in the current window. */ 5845 iwn_ampdu_txq_advance(sc, &sc->txq[qid], qid, 5846 IWN_AGG_SSN_TO_TXQ_IDX(ba->ba_winend)); 5847 5848 if (iwn_nic_lock(sc) != 0) 5849 return; 5850 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart); 5851 iwn_nic_unlock(sc); 5852 5853 sc->agg_queue_mask &= ~(1 << qid); 5854 sc->sc_tx_ba[tid].wn = NULL; 5855 ba->ba_bitmap = 0; 5856 5857 /* Disable TX for the specified RA/TID. */ 5858 wn->disable_tid |= (1 << tid); 5859 memset(&node, 0, sizeof node); 5860 node.id = wn->id; 5861 node.control = IWN_NODE_UPDATE; 5862 node.flags = IWN_FLAG_SET_DISABLE_TID; 5863 node.disable_tid = htole16(wn->disable_tid); 5864 ops->add_node(sc, &node, 1); 5865 } 5866 5867 void 5868 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5869 uint8_t tid, uint16_t ssn) 5870 { 5871 struct iwn_node *wn = (void *)ni; 5872 int qid = IWN4965_FIRST_AGG_TXQUEUE + tid; 5873 uint16_t idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 5874 5875 /* Stop TX scheduler while we're changing its configuration. */ 5876 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5877 IWN4965_TXQ_STATUS_CHGACT); 5878 5879 /* Assign RA/TID translation to the queue. */ 5880 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5881 wn->id << 4 | tid); 5882 5883 /* Enable chain-building mode for the queue. */ 5884 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5885 5886 /* Set starting sequence number from the ADDBA request. */ 5887 sc->txq[qid].cur = sc->txq[qid].read = idx; 5888 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 5889 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5890 5891 /* Set scheduler window size. */ 5892 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5893 IWN_SCHED_WINSZ); 5894 /* Set scheduler frame limit. */ 5895 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5896 IWN_SCHED_LIMIT << 16); 5897 5898 /* Enable interrupts for the queue. */ 5899 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5900 5901 /* Mark the queue as active. */ 5902 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5903 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5904 iwn_tid2fifo[tid] << 1); 5905 } 5906 5907 void 5908 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5909 { 5910 int qid = IWN4965_FIRST_AGG_TXQUEUE + tid; 5911 uint16_t idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 5912 5913 /* Stop TX scheduler while we're changing its configuration. */ 5914 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5915 IWN4965_TXQ_STATUS_CHGACT); 5916 5917 /* Set starting sequence number from the ADDBA request. */ 5918 sc->txq[qid].cur = sc->txq[qid].read = idx; 5919 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 5920 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5921 5922 /* Disable interrupts for the queue. */ 5923 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5924 5925 /* Mark the queue as inactive. */ 5926 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5927 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5928 } 5929 5930 void 5931 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5932 uint8_t tid, uint16_t ssn) 5933 { 5934 int qid = IWN5000_FIRST_AGG_TXQUEUE + tid; 5935 int idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 5936 struct iwn_node *wn = (void *)ni; 5937 5938 /* Stop TX scheduler while we're changing its configuration. */ 5939 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5940 IWN5000_TXQ_STATUS_CHGACT); 5941 5942 /* Assign RA/TID translation to the queue. */ 5943 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5944 wn->id << 4 | tid); 5945 5946 /* Enable chain-building mode for the queue. */ 5947 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5948 5949 /* Enable aggregation for the queue. */ 5950 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5951 5952 /* Set starting sequence number from the ADDBA request. */ 5953 sc->txq[qid].cur = sc->txq[qid].read = idx; 5954 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 5955 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5956 5957 /* Set scheduler window size and frame limit. */ 5958 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5959 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5960 5961 /* Enable interrupts for the queue. */ 5962 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5963 5964 /* Mark the queue as active. */ 5965 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5966 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5967 } 5968 5969 void 5970 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5971 { 5972 int qid = IWN5000_FIRST_AGG_TXQUEUE + tid; 5973 int idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 5974 5975 /* Stop TX scheduler while we're changing its configuration. */ 5976 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5977 IWN5000_TXQ_STATUS_CHGACT); 5978 5979 /* Disable aggregation for the queue. */ 5980 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5981 5982 /* Set starting sequence number from the ADDBA request. */ 5983 sc->txq[qid].cur = sc->txq[qid].read = idx; 5984 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 5985 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5986 5987 /* Disable interrupts for the queue. */ 5988 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5989 5990 /* Mark the queue as inactive. */ 5991 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5992 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5993 } 5994 5995 /* 5996 * Query calibration tables from the initialization firmware. We do this 5997 * only once at first boot. Called from a process context. 5998 */ 5999 int 6000 iwn5000_query_calibration(struct iwn_softc *sc) 6001 { 6002 struct iwn5000_calib_config cmd; 6003 int error; 6004 6005 memset(&cmd, 0, sizeof cmd); 6006 cmd.ucode.once.enable = 0xffffffff; 6007 cmd.ucode.once.start = 0xffffffff; 6008 cmd.ucode.once.send = 0xffffffff; 6009 cmd.ucode.flags = 0xffffffff; 6010 DPRINTF(("sending calibration query\n")); 6011 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 6012 if (error != 0) 6013 return error; 6014 6015 /* Wait at most two seconds for calibration to complete. */ 6016 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 6017 error = tsleep_nsec(sc, PCATCH, "iwncal", SEC_TO_NSEC(2)); 6018 return error; 6019 } 6020 6021 /* 6022 * Send calibration results to the runtime firmware. These results were 6023 * obtained on first boot from the initialization firmware. 6024 */ 6025 int 6026 iwn5000_send_calibration(struct iwn_softc *sc) 6027 { 6028 int idx, error; 6029 6030 for (idx = 0; idx < 5; idx++) { 6031 if (sc->calibcmd[idx].buf == NULL) 6032 continue; /* No results available. */ 6033 DPRINTF(("send calibration result idx=%d len=%d\n", 6034 idx, sc->calibcmd[idx].len)); 6035 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 6036 sc->calibcmd[idx].len, 0); 6037 if (error != 0) { 6038 printf("%s: could not send calibration result\n", 6039 sc->sc_dev.dv_xname); 6040 return error; 6041 } 6042 } 6043 return 0; 6044 } 6045 6046 int 6047 iwn5000_send_wimax_coex(struct iwn_softc *sc) 6048 { 6049 struct iwn5000_wimax_coex wimax; 6050 6051 #ifdef notyet 6052 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 6053 /* Enable WiMAX coexistence for combo adapters. */ 6054 wimax.flags = 6055 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 6056 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 6057 IWN_WIMAX_COEX_STA_TABLE_VALID | 6058 IWN_WIMAX_COEX_ENABLE; 6059 memcpy(wimax.events, iwn6050_wimax_events, 6060 sizeof iwn6050_wimax_events); 6061 } else 6062 #endif 6063 { 6064 /* Disable WiMAX coexistence. */ 6065 wimax.flags = 0; 6066 memset(wimax.events, 0, sizeof wimax.events); 6067 } 6068 DPRINTF(("Configuring WiMAX coexistence\n")); 6069 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 6070 } 6071 6072 int 6073 iwn5000_crystal_calib(struct iwn_softc *sc) 6074 { 6075 struct iwn5000_phy_calib_crystal cmd; 6076 6077 memset(&cmd, 0, sizeof cmd); 6078 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 6079 cmd.ngroups = 1; 6080 cmd.isvalid = 1; 6081 cmd.cap_pin[0] = letoh32(sc->eeprom_crystal) & 0xff; 6082 cmd.cap_pin[1] = (letoh32(sc->eeprom_crystal) >> 16) & 0xff; 6083 DPRINTF(("sending crystal calibration %d, %d\n", 6084 cmd.cap_pin[0], cmd.cap_pin[1])); 6085 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 6086 } 6087 6088 int 6089 iwn6000_temp_offset_calib(struct iwn_softc *sc) 6090 { 6091 struct iwn6000_phy_calib_temp_offset cmd; 6092 6093 memset(&cmd, 0, sizeof cmd); 6094 cmd.code = IWN6000_PHY_CALIB_TEMP_OFFSET; 6095 cmd.ngroups = 1; 6096 cmd.isvalid = 1; 6097 if (sc->eeprom_temp != 0) 6098 cmd.offset = htole16(sc->eeprom_temp); 6099 else 6100 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 6101 DPRINTF(("setting radio sensor offset to %d\n", letoh16(cmd.offset))); 6102 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 6103 } 6104 6105 int 6106 iwn2000_temp_offset_calib(struct iwn_softc *sc) 6107 { 6108 struct iwn2000_phy_calib_temp_offset cmd; 6109 6110 memset(&cmd, 0, sizeof cmd); 6111 cmd.code = IWN2000_PHY_CALIB_TEMP_OFFSET; 6112 cmd.ngroups = 1; 6113 cmd.isvalid = 1; 6114 if (sc->eeprom_rawtemp != 0) { 6115 cmd.offset_low = htole16(sc->eeprom_rawtemp); 6116 cmd.offset_high = htole16(sc->eeprom_temp); 6117 } else { 6118 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 6119 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 6120 } 6121 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 6122 DPRINTF(("setting radio sensor offset to %d:%d, voltage to %d\n", 6123 letoh16(cmd.offset_low), letoh16(cmd.offset_high), 6124 letoh16(cmd.burnt_voltage_ref))); 6125 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 6126 } 6127 6128 /* 6129 * This function is called after the runtime firmware notifies us of its 6130 * readiness (called in a process context). 6131 */ 6132 int 6133 iwn4965_post_alive(struct iwn_softc *sc) 6134 { 6135 int error, qid; 6136 6137 if ((error = iwn_nic_lock(sc)) != 0) 6138 return error; 6139 6140 /* Clear TX scheduler state in SRAM. */ 6141 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 6142 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 6143 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 6144 6145 /* Set physical address of TX scheduler rings (1KB aligned). */ 6146 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 6147 6148 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 6149 6150 /* Disable chain mode for all our 16 queues. */ 6151 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 6152 6153 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 6154 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 6155 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 6156 6157 /* Set scheduler window size. */ 6158 iwn_mem_write(sc, sc->sched_base + 6159 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 6160 /* Set scheduler frame limit. */ 6161 iwn_mem_write(sc, sc->sched_base + 6162 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 6163 IWN_SCHED_LIMIT << 16); 6164 } 6165 6166 /* Enable interrupts for all our 16 queues. */ 6167 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 6168 /* Identify TX FIFO rings (0-7). */ 6169 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 6170 6171 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 6172 for (qid = 0; qid < 7; qid++) { 6173 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 6174 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 6175 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 6176 } 6177 iwn_nic_unlock(sc); 6178 return 0; 6179 } 6180 6181 /* 6182 * This function is called after the initialization or runtime firmware 6183 * notifies us of its readiness (called in a process context). 6184 */ 6185 int 6186 iwn5000_post_alive(struct iwn_softc *sc) 6187 { 6188 int error, qid; 6189 6190 /* Switch to using ICT interrupt mode. */ 6191 iwn5000_ict_reset(sc); 6192 6193 if ((error = iwn_nic_lock(sc)) != 0) 6194 return error; 6195 6196 /* Clear TX scheduler state in SRAM. */ 6197 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 6198 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 6199 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 6200 6201 /* Set physical address of TX scheduler rings (1KB aligned). */ 6202 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 6203 6204 /* Disable scheduler chain extension (enabled by default in HW). */ 6205 iwn_prph_write(sc, IWN5000_SCHED_CHAINEXT_EN, 0); 6206 6207 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 6208 6209 /* Enable chain mode for all queues, except command queue. */ 6210 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 6211 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 6212 6213 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 6214 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 6215 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 6216 6217 iwn_mem_write(sc, sc->sched_base + 6218 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 6219 /* Set scheduler window size and frame limit. */ 6220 iwn_mem_write(sc, sc->sched_base + 6221 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 6222 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 6223 } 6224 6225 /* Enable interrupts for all our 20 queues. */ 6226 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 6227 /* Identify TX FIFO rings (0-7). */ 6228 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 6229 6230 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 6231 for (qid = 0; qid < 7; qid++) { 6232 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 6233 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 6234 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 6235 } 6236 iwn_nic_unlock(sc); 6237 6238 /* Configure WiMAX coexistence for combo adapters. */ 6239 error = iwn5000_send_wimax_coex(sc); 6240 if (error != 0) { 6241 printf("%s: could not configure WiMAX coexistence\n", 6242 sc->sc_dev.dv_xname); 6243 return error; 6244 } 6245 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 6246 /* Perform crystal calibration. */ 6247 error = iwn5000_crystal_calib(sc); 6248 if (error != 0) { 6249 printf("%s: crystal calibration failed\n", 6250 sc->sc_dev.dv_xname); 6251 return error; 6252 } 6253 } 6254 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 6255 /* Query calibration from the initialization firmware. */ 6256 if ((error = iwn5000_query_calibration(sc)) != 0) { 6257 printf("%s: could not query calibration\n", 6258 sc->sc_dev.dv_xname); 6259 return error; 6260 } 6261 /* 6262 * We have the calibration results now, reboot with the 6263 * runtime firmware (call ourselves recursively!) 6264 */ 6265 iwn_hw_stop(sc); 6266 error = iwn_hw_init(sc); 6267 } else { 6268 /* Send calibration results to runtime firmware. */ 6269 error = iwn5000_send_calibration(sc); 6270 } 6271 return error; 6272 } 6273 6274 /* 6275 * The firmware boot code is small and is intended to be copied directly into 6276 * the NIC internal memory (no DMA transfer). 6277 */ 6278 int 6279 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 6280 { 6281 int error, ntries; 6282 6283 size /= sizeof (uint32_t); 6284 6285 if ((error = iwn_nic_lock(sc)) != 0) 6286 return error; 6287 6288 /* Copy microcode image into NIC memory. */ 6289 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 6290 (const uint32_t *)ucode, size); 6291 6292 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 6293 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 6294 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 6295 6296 /* Start boot load now. */ 6297 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 6298 6299 /* Wait for transfer to complete. */ 6300 for (ntries = 0; ntries < 1000; ntries++) { 6301 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 6302 IWN_BSM_WR_CTRL_START)) 6303 break; 6304 DELAY(10); 6305 } 6306 if (ntries == 1000) { 6307 printf("%s: could not load boot firmware\n", 6308 sc->sc_dev.dv_xname); 6309 iwn_nic_unlock(sc); 6310 return ETIMEDOUT; 6311 } 6312 6313 /* Enable boot after power up. */ 6314 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 6315 6316 iwn_nic_unlock(sc); 6317 return 0; 6318 } 6319 6320 int 6321 iwn4965_load_firmware(struct iwn_softc *sc) 6322 { 6323 struct iwn_fw_info *fw = &sc->fw; 6324 struct iwn_dma_info *dma = &sc->fw_dma; 6325 int error; 6326 6327 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 6328 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 6329 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 6330 BUS_DMASYNC_PREWRITE); 6331 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 6332 fw->init.text, fw->init.textsz); 6333 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 6334 fw->init.textsz, BUS_DMASYNC_PREWRITE); 6335 6336 /* Tell adapter where to find initialization sections. */ 6337 if ((error = iwn_nic_lock(sc)) != 0) 6338 return error; 6339 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 6340 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 6341 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 6342 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 6343 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 6344 iwn_nic_unlock(sc); 6345 6346 /* Load firmware boot code. */ 6347 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 6348 if (error != 0) { 6349 printf("%s: could not load boot firmware\n", 6350 sc->sc_dev.dv_xname); 6351 return error; 6352 } 6353 /* Now press "execute". */ 6354 IWN_WRITE(sc, IWN_RESET, 0); 6355 6356 /* Wait at most one second for first alive notification. */ 6357 if ((error = tsleep_nsec(sc, PCATCH, "iwninit", SEC_TO_NSEC(1))) != 0) { 6358 printf("%s: timeout waiting for adapter to initialize\n", 6359 sc->sc_dev.dv_xname); 6360 return error; 6361 } 6362 6363 /* Retrieve current temperature for initial TX power calibration. */ 6364 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 6365 sc->temp = iwn4965_get_temperature(sc); 6366 6367 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 6368 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 6369 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 6370 BUS_DMASYNC_PREWRITE); 6371 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 6372 fw->main.text, fw->main.textsz); 6373 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 6374 fw->main.textsz, BUS_DMASYNC_PREWRITE); 6375 6376 /* Tell adapter where to find runtime sections. */ 6377 if ((error = iwn_nic_lock(sc)) != 0) 6378 return error; 6379 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 6380 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 6381 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 6382 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 6383 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 6384 IWN_FW_UPDATED | fw->main.textsz); 6385 iwn_nic_unlock(sc); 6386 6387 return 0; 6388 } 6389 6390 int 6391 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 6392 const uint8_t *section, int size) 6393 { 6394 struct iwn_dma_info *dma = &sc->fw_dma; 6395 int error; 6396 6397 /* Copy firmware section into pre-allocated DMA-safe memory. */ 6398 memcpy(dma->vaddr, section, size); 6399 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 6400 6401 if ((error = iwn_nic_lock(sc)) != 0) 6402 return error; 6403 6404 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 6405 IWN_FH_TX_CONFIG_DMA_PAUSE); 6406 6407 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 6408 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 6409 IWN_LOADDR(dma->paddr)); 6410 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 6411 IWN_HIADDR(dma->paddr) << 28 | size); 6412 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 6413 IWN_FH_TXBUF_STATUS_TBNUM(1) | 6414 IWN_FH_TXBUF_STATUS_TBIDX(1) | 6415 IWN_FH_TXBUF_STATUS_TFBD_VALID); 6416 6417 /* Kick Flow Handler to start DMA transfer. */ 6418 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 6419 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 6420 6421 iwn_nic_unlock(sc); 6422 6423 /* Wait at most five seconds for FH DMA transfer to complete. */ 6424 return tsleep_nsec(sc, PCATCH, "iwninit", SEC_TO_NSEC(5)); 6425 } 6426 6427 int 6428 iwn5000_load_firmware(struct iwn_softc *sc) 6429 { 6430 struct iwn_fw_part *fw; 6431 int error; 6432 6433 /* Load the initialization firmware on first boot only. */ 6434 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 6435 &sc->fw.main : &sc->fw.init; 6436 6437 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 6438 fw->text, fw->textsz); 6439 if (error != 0) { 6440 printf("%s: could not load firmware %s section\n", 6441 sc->sc_dev.dv_xname, ".text"); 6442 return error; 6443 } 6444 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 6445 fw->data, fw->datasz); 6446 if (error != 0) { 6447 printf("%s: could not load firmware %s section\n", 6448 sc->sc_dev.dv_xname, ".data"); 6449 return error; 6450 } 6451 6452 /* Now press "execute". */ 6453 IWN_WRITE(sc, IWN_RESET, 0); 6454 return 0; 6455 } 6456 6457 /* 6458 * Extract text and data sections from a legacy firmware image. 6459 */ 6460 int 6461 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 6462 { 6463 const uint32_t *ptr; 6464 size_t hdrlen = 24; 6465 uint32_t rev; 6466 6467 ptr = (const uint32_t *)fw->data; 6468 rev = letoh32(*ptr++); 6469 6470 /* Check firmware API version. */ 6471 if (IWN_FW_API(rev) <= 1) { 6472 printf("%s: bad firmware, need API version >=2\n", 6473 sc->sc_dev.dv_xname); 6474 return EINVAL; 6475 } 6476 if (IWN_FW_API(rev) >= 3) { 6477 /* Skip build number (version 2 header). */ 6478 hdrlen += 4; 6479 ptr++; 6480 } 6481 if (fw->size < hdrlen) { 6482 printf("%s: firmware too short: %zu bytes\n", 6483 sc->sc_dev.dv_xname, fw->size); 6484 return EINVAL; 6485 } 6486 fw->main.textsz = letoh32(*ptr++); 6487 fw->main.datasz = letoh32(*ptr++); 6488 fw->init.textsz = letoh32(*ptr++); 6489 fw->init.datasz = letoh32(*ptr++); 6490 fw->boot.textsz = letoh32(*ptr++); 6491 6492 /* Check that all firmware sections fit. */ 6493 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 6494 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 6495 printf("%s: firmware too short: %zu bytes\n", 6496 sc->sc_dev.dv_xname, fw->size); 6497 return EINVAL; 6498 } 6499 6500 /* Get pointers to firmware sections. */ 6501 fw->main.text = (const uint8_t *)ptr; 6502 fw->main.data = fw->main.text + fw->main.textsz; 6503 fw->init.text = fw->main.data + fw->main.datasz; 6504 fw->init.data = fw->init.text + fw->init.textsz; 6505 fw->boot.text = fw->init.data + fw->init.datasz; 6506 return 0; 6507 } 6508 6509 /* 6510 * Extract text and data sections from a TLV firmware image. 6511 */ 6512 int 6513 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 6514 uint16_t alt) 6515 { 6516 const struct iwn_fw_tlv_hdr *hdr; 6517 const struct iwn_fw_tlv *tlv; 6518 const uint8_t *ptr, *end; 6519 uint64_t altmask; 6520 uint32_t len; 6521 6522 if (fw->size < sizeof (*hdr)) { 6523 printf("%s: firmware too short: %zu bytes\n", 6524 sc->sc_dev.dv_xname, fw->size); 6525 return EINVAL; 6526 } 6527 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 6528 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 6529 printf("%s: bad firmware signature 0x%08x\n", 6530 sc->sc_dev.dv_xname, letoh32(hdr->signature)); 6531 return EINVAL; 6532 } 6533 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr, 6534 letoh32(hdr->build))); 6535 6536 /* 6537 * Select the closest supported alternative that is less than 6538 * or equal to the specified one. 6539 */ 6540 altmask = letoh64(hdr->altmask); 6541 while (alt > 0 && !(altmask & (1ULL << alt))) 6542 alt--; /* Downgrade. */ 6543 DPRINTF(("using alternative %d\n", alt)); 6544 6545 ptr = (const uint8_t *)(hdr + 1); 6546 end = (const uint8_t *)(fw->data + fw->size); 6547 6548 /* Parse type-length-value fields. */ 6549 while (ptr + sizeof (*tlv) <= end) { 6550 tlv = (const struct iwn_fw_tlv *)ptr; 6551 len = letoh32(tlv->len); 6552 6553 ptr += sizeof (*tlv); 6554 if (ptr + len > end) { 6555 printf("%s: firmware too short: %zu bytes\n", 6556 sc->sc_dev.dv_xname, fw->size); 6557 return EINVAL; 6558 } 6559 /* Skip other alternatives. */ 6560 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 6561 goto next; 6562 6563 switch (letoh16(tlv->type)) { 6564 case IWN_FW_TLV_MAIN_TEXT: 6565 fw->main.text = ptr; 6566 fw->main.textsz = len; 6567 break; 6568 case IWN_FW_TLV_MAIN_DATA: 6569 fw->main.data = ptr; 6570 fw->main.datasz = len; 6571 break; 6572 case IWN_FW_TLV_INIT_TEXT: 6573 fw->init.text = ptr; 6574 fw->init.textsz = len; 6575 break; 6576 case IWN_FW_TLV_INIT_DATA: 6577 fw->init.data = ptr; 6578 fw->init.datasz = len; 6579 break; 6580 case IWN_FW_TLV_BOOT_TEXT: 6581 fw->boot.text = ptr; 6582 fw->boot.textsz = len; 6583 break; 6584 case IWN_FW_TLV_ENH_SENS: 6585 if (len != 0) { 6586 printf("%s: TLV type %d has invalid size %u\n", 6587 sc->sc_dev.dv_xname, letoh16(tlv->type), 6588 len); 6589 goto next; 6590 } 6591 sc->sc_flags |= IWN_FLAG_ENH_SENS; 6592 break; 6593 case IWN_FW_TLV_PHY_CALIB: 6594 if (len != sizeof(uint32_t)) { 6595 printf("%s: TLV type %d has invalid size %u\n", 6596 sc->sc_dev.dv_xname, letoh16(tlv->type), 6597 len); 6598 goto next; 6599 } 6600 if (letoh32(*ptr) <= IWN5000_PHY_CALIB_MAX) { 6601 sc->reset_noise_gain = letoh32(*ptr); 6602 sc->noise_gain = letoh32(*ptr) + 1; 6603 } 6604 break; 6605 case IWN_FW_TLV_FLAGS: 6606 if (len < sizeof(uint32_t)) 6607 break; 6608 if (len % sizeof(uint32_t)) 6609 break; 6610 sc->tlv_feature_flags = letoh32(*ptr); 6611 DPRINTF(("feature: 0x%08x\n", sc->tlv_feature_flags)); 6612 break; 6613 default: 6614 DPRINTF(("TLV type %d not handled\n", 6615 letoh16(tlv->type))); 6616 break; 6617 } 6618 next: /* TLV fields are 32-bit aligned. */ 6619 ptr += (len + 3) & ~3; 6620 } 6621 return 0; 6622 } 6623 6624 int 6625 iwn_read_firmware(struct iwn_softc *sc) 6626 { 6627 struct iwn_fw_info *fw = &sc->fw; 6628 int error; 6629 6630 /* 6631 * Some PHY calibration commands are firmware-dependent; these 6632 * are the default values that will be overridden if 6633 * necessary. 6634 */ 6635 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 6636 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 6637 6638 memset(fw, 0, sizeof (*fw)); 6639 6640 /* Read firmware image from filesystem. */ 6641 if ((error = loadfirmware(sc->fwname, &fw->data, &fw->size)) != 0) { 6642 printf("%s: could not read firmware %s (error %d)\n", 6643 sc->sc_dev.dv_xname, sc->fwname, error); 6644 return error; 6645 } 6646 if (fw->size < sizeof (uint32_t)) { 6647 printf("%s: firmware too short: %zu bytes\n", 6648 sc->sc_dev.dv_xname, fw->size); 6649 free(fw->data, M_DEVBUF, fw->size); 6650 return EINVAL; 6651 } 6652 6653 /* Retrieve text and data sections. */ 6654 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 6655 error = iwn_read_firmware_leg(sc, fw); 6656 else 6657 error = iwn_read_firmware_tlv(sc, fw, 1); 6658 if (error != 0) { 6659 printf("%s: could not read firmware sections\n", 6660 sc->sc_dev.dv_xname); 6661 free(fw->data, M_DEVBUF, fw->size); 6662 return error; 6663 } 6664 6665 /* Make sure text and data sections fit in hardware memory. */ 6666 if (fw->main.textsz > sc->fw_text_maxsz || 6667 fw->main.datasz > sc->fw_data_maxsz || 6668 fw->init.textsz > sc->fw_text_maxsz || 6669 fw->init.datasz > sc->fw_data_maxsz || 6670 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 6671 (fw->boot.textsz & 3) != 0) { 6672 printf("%s: firmware sections too large\n", 6673 sc->sc_dev.dv_xname); 6674 free(fw->data, M_DEVBUF, fw->size); 6675 return EINVAL; 6676 } 6677 6678 /* We can proceed with loading the firmware. */ 6679 return 0; 6680 } 6681 6682 int 6683 iwn_clock_wait(struct iwn_softc *sc) 6684 { 6685 int ntries; 6686 6687 /* Set "initialization complete" bit. */ 6688 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6689 6690 /* Wait for clock stabilization. */ 6691 for (ntries = 0; ntries < 2500; ntries++) { 6692 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 6693 return 0; 6694 DELAY(10); 6695 } 6696 printf("%s: timeout waiting for clock stabilization\n", 6697 sc->sc_dev.dv_xname); 6698 return ETIMEDOUT; 6699 } 6700 6701 int 6702 iwn_apm_init(struct iwn_softc *sc) 6703 { 6704 pcireg_t reg; 6705 int error; 6706 6707 /* Disable L0s exit timer (NMI bug workaround). */ 6708 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 6709 /* Don't wait for ICH L0s (ICH bug workaround). */ 6710 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 6711 6712 /* Set FH wait threshold to max (HW bug under stress workaround). */ 6713 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 6714 6715 /* Enable HAP INTA to move adapter from L1a to L0s. */ 6716 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 6717 6718 /* Retrieve PCIe Active State Power Management (ASPM). */ 6719 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 6720 sc->sc_cap_off + PCI_PCIE_LCSR); 6721 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 6722 if (reg & PCI_PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 6723 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6724 else 6725 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6726 6727 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6728 sc->hw_type <= IWN_HW_REV_TYPE_1000) 6729 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 6730 6731 /* Wait for clock stabilization before accessing prph. */ 6732 if ((error = iwn_clock_wait(sc)) != 0) 6733 return error; 6734 6735 if ((error = iwn_nic_lock(sc)) != 0) 6736 return error; 6737 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 6738 /* Enable DMA and BSM (Bootstrap State Machine). */ 6739 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6740 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 6741 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 6742 } else { 6743 /* Enable DMA. */ 6744 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6745 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6746 } 6747 DELAY(20); 6748 /* Disable L1-Active. */ 6749 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 6750 iwn_nic_unlock(sc); 6751 6752 return 0; 6753 } 6754 6755 void 6756 iwn_apm_stop_master(struct iwn_softc *sc) 6757 { 6758 int ntries; 6759 6760 /* Stop busmaster DMA activity. */ 6761 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 6762 for (ntries = 0; ntries < 100; ntries++) { 6763 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 6764 return; 6765 DELAY(10); 6766 } 6767 printf("%s: timeout waiting for master\n", sc->sc_dev.dv_xname); 6768 } 6769 6770 void 6771 iwn_apm_stop(struct iwn_softc *sc) 6772 { 6773 iwn_apm_stop_master(sc); 6774 6775 /* Reset the entire device. */ 6776 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 6777 DELAY(10); 6778 /* Clear "initialization complete" bit. */ 6779 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6780 } 6781 6782 int 6783 iwn4965_nic_config(struct iwn_softc *sc) 6784 { 6785 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 6786 /* 6787 * I don't believe this to be correct but this is what the 6788 * vendor driver is doing. Probably the bits should not be 6789 * shifted in IWN_RFCFG_*. 6790 */ 6791 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6792 IWN_RFCFG_TYPE(sc->rfcfg) | 6793 IWN_RFCFG_STEP(sc->rfcfg) | 6794 IWN_RFCFG_DASH(sc->rfcfg)); 6795 } 6796 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6797 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6798 return 0; 6799 } 6800 6801 int 6802 iwn5000_nic_config(struct iwn_softc *sc) 6803 { 6804 uint32_t tmp; 6805 int error; 6806 6807 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 6808 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6809 IWN_RFCFG_TYPE(sc->rfcfg) | 6810 IWN_RFCFG_STEP(sc->rfcfg) | 6811 IWN_RFCFG_DASH(sc->rfcfg)); 6812 } 6813 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6814 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6815 6816 if ((error = iwn_nic_lock(sc)) != 0) 6817 return error; 6818 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 6819 6820 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 6821 /* 6822 * Select first Switching Voltage Regulator (1.32V) to 6823 * solve a stability issue related to noisy DC2DC line 6824 * in the silicon of 1000 Series. 6825 */ 6826 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 6827 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 6828 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 6829 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 6830 } 6831 iwn_nic_unlock(sc); 6832 6833 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 6834 /* Use internal power amplifier only. */ 6835 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 6836 } 6837 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 6838 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 6839 /* Indicate that ROM calibration version is >=6. */ 6840 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 6841 } 6842 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 6843 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 6844 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 6845 sc->hw_type == IWN_HW_REV_TYPE_2000 || 6846 sc->hw_type == IWN_HW_REV_TYPE_135 || 6847 sc->hw_type == IWN_HW_REV_TYPE_105) 6848 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_IQ_INVERT); 6849 return 0; 6850 } 6851 6852 /* 6853 * Take NIC ownership over Intel Active Management Technology (AMT). 6854 */ 6855 int 6856 iwn_hw_prepare(struct iwn_softc *sc) 6857 { 6858 int ntries; 6859 6860 /* Check if hardware is ready. */ 6861 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6862 for (ntries = 0; ntries < 5; ntries++) { 6863 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6864 IWN_HW_IF_CONFIG_NIC_READY) 6865 return 0; 6866 DELAY(10); 6867 } 6868 6869 /* Hardware not ready, force into ready state. */ 6870 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 6871 for (ntries = 0; ntries < 15000; ntries++) { 6872 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 6873 IWN_HW_IF_CONFIG_PREPARE_DONE)) 6874 break; 6875 DELAY(10); 6876 } 6877 if (ntries == 15000) 6878 return ETIMEDOUT; 6879 6880 /* Hardware should be ready now. */ 6881 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6882 for (ntries = 0; ntries < 5; ntries++) { 6883 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6884 IWN_HW_IF_CONFIG_NIC_READY) 6885 return 0; 6886 DELAY(10); 6887 } 6888 return ETIMEDOUT; 6889 } 6890 6891 int 6892 iwn_hw_init(struct iwn_softc *sc) 6893 { 6894 struct iwn_ops *ops = &sc->ops; 6895 int error, chnl, qid; 6896 6897 /* Clear pending interrupts. */ 6898 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6899 6900 if ((error = iwn_apm_init(sc)) != 0) { 6901 printf("%s: could not power on adapter\n", 6902 sc->sc_dev.dv_xname); 6903 return error; 6904 } 6905 6906 /* Select VMAIN power source. */ 6907 if ((error = iwn_nic_lock(sc)) != 0) 6908 return error; 6909 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 6910 iwn_nic_unlock(sc); 6911 6912 /* Perform adapter-specific initialization. */ 6913 if ((error = ops->nic_config(sc)) != 0) 6914 return error; 6915 6916 /* Initialize RX ring. */ 6917 if ((error = iwn_nic_lock(sc)) != 0) 6918 return error; 6919 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 6920 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 6921 /* Set physical address of RX ring (256-byte aligned). */ 6922 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 6923 /* Set physical address of RX status (16-byte aligned). */ 6924 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 6925 /* Enable RX. */ 6926 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 6927 IWN_FH_RX_CONFIG_ENA | 6928 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 6929 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 6930 IWN_FH_RX_CONFIG_SINGLE_FRAME | 6931 IWN_FH_RX_CONFIG_RB_TIMEOUT(0x11) | /* about 1/2 msec */ 6932 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 6933 iwn_nic_unlock(sc); 6934 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 6935 6936 if ((error = iwn_nic_lock(sc)) != 0) 6937 return error; 6938 6939 /* Initialize TX scheduler. */ 6940 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6941 6942 /* Set physical address of "keep warm" page (16-byte aligned). */ 6943 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6944 6945 /* Initialize TX rings. */ 6946 for (qid = 0; qid < sc->ntxqs; qid++) { 6947 struct iwn_tx_ring *txq = &sc->txq[qid]; 6948 6949 /* Set physical address of TX ring (256-byte aligned). */ 6950 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6951 txq->desc_dma.paddr >> 8); 6952 } 6953 iwn_nic_unlock(sc); 6954 6955 /* Enable DMA channels. */ 6956 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6957 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6958 IWN_FH_TX_CONFIG_DMA_ENA | 6959 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 6960 } 6961 6962 /* Clear "radio off" and "commands blocked" bits. */ 6963 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6964 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 6965 6966 /* Clear pending interrupts. */ 6967 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6968 /* Enable interrupt coalescing. */ 6969 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 6970 /* Enable interrupts. */ 6971 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6972 6973 /* _Really_ make sure "radio off" bit is cleared! */ 6974 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6975 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6976 6977 /* Enable shadow registers. */ 6978 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 6979 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 6980 6981 if ((error = ops->load_firmware(sc)) != 0) { 6982 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 6983 return error; 6984 } 6985 /* Wait at most one second for firmware alive notification. */ 6986 if ((error = tsleep_nsec(sc, PCATCH, "iwninit", SEC_TO_NSEC(1))) != 0) { 6987 printf("%s: timeout waiting for adapter to initialize\n", 6988 sc->sc_dev.dv_xname); 6989 return error; 6990 } 6991 /* Do post-firmware initialization. */ 6992 return ops->post_alive(sc); 6993 } 6994 6995 void 6996 iwn_hw_stop(struct iwn_softc *sc) 6997 { 6998 int chnl, qid, ntries; 6999 7000 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 7001 7002 /* Disable interrupts. */ 7003 IWN_WRITE(sc, IWN_INT_MASK, 0); 7004 IWN_WRITE(sc, IWN_INT, 0xffffffff); 7005 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 7006 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 7007 7008 /* Make sure we no longer hold the NIC lock. */ 7009 iwn_nic_unlock(sc); 7010 7011 /* Stop TX scheduler. */ 7012 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 7013 7014 /* Stop all DMA channels. */ 7015 if (iwn_nic_lock(sc) == 0) { 7016 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 7017 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 7018 for (ntries = 0; ntries < 200; ntries++) { 7019 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 7020 IWN_FH_TX_STATUS_IDLE(chnl)) 7021 break; 7022 DELAY(10); 7023 } 7024 } 7025 iwn_nic_unlock(sc); 7026 } 7027 7028 /* Stop RX ring. */ 7029 iwn_reset_rx_ring(sc, &sc->rxq); 7030 7031 /* Reset all TX rings. */ 7032 for (qid = 0; qid < sc->ntxqs; qid++) 7033 iwn_reset_tx_ring(sc, &sc->txq[qid]); 7034 7035 if (iwn_nic_lock(sc) == 0) { 7036 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 7037 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 7038 iwn_nic_unlock(sc); 7039 } 7040 DELAY(5); 7041 /* Power OFF adapter. */ 7042 iwn_apm_stop(sc); 7043 } 7044 7045 int 7046 iwn_init(struct ifnet *ifp) 7047 { 7048 struct iwn_softc *sc = ifp->if_softc; 7049 struct ieee80211com *ic = &sc->sc_ic; 7050 int error; 7051 7052 memset(sc->bss_node_addr, 0, sizeof(sc->bss_node_addr)); 7053 sc->agg_queue_mask = 0; 7054 memset(sc->sc_tx_ba, 0, sizeof(sc->sc_tx_ba)); 7055 7056 if ((error = iwn_hw_prepare(sc)) != 0) { 7057 printf("%s: hardware not ready\n", sc->sc_dev.dv_xname); 7058 goto fail; 7059 } 7060 7061 /* Initialize interrupt mask to default value. */ 7062 sc->int_mask = IWN_INT_MASK_DEF; 7063 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 7064 7065 /* Check that the radio is not disabled by hardware switch. */ 7066 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 7067 printf("%s: radio is disabled by hardware switch\n", 7068 sc->sc_dev.dv_xname); 7069 error = EPERM; /* :-) */ 7070 /* Re-enable interrupts. */ 7071 IWN_WRITE(sc, IWN_INT, 0xffffffff); 7072 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 7073 return error; 7074 } 7075 7076 /* Read firmware images from the filesystem. */ 7077 if ((error = iwn_read_firmware(sc)) != 0) { 7078 printf("%s: could not read firmware\n", sc->sc_dev.dv_xname); 7079 goto fail; 7080 } 7081 7082 /* Initialize hardware and upload firmware. */ 7083 error = iwn_hw_init(sc); 7084 free(sc->fw.data, M_DEVBUF, sc->fw.size); 7085 if (error != 0) { 7086 printf("%s: could not initialize hardware\n", 7087 sc->sc_dev.dv_xname); 7088 goto fail; 7089 } 7090 7091 /* Configure adapter now that it is ready. */ 7092 if ((error = iwn_config(sc)) != 0) { 7093 printf("%s: could not configure device\n", 7094 sc->sc_dev.dv_xname); 7095 goto fail; 7096 } 7097 7098 ifq_clr_oactive(&ifp->if_snd); 7099 ifp->if_flags |= IFF_RUNNING; 7100 7101 if (ic->ic_opmode != IEEE80211_M_MONITOR) 7102 ieee80211_begin_scan(ifp); 7103 else 7104 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 7105 7106 return 0; 7107 7108 fail: iwn_stop(ifp); 7109 return error; 7110 } 7111 7112 void 7113 iwn_stop(struct ifnet *ifp) 7114 { 7115 struct iwn_softc *sc = ifp->if_softc; 7116 struct ieee80211com *ic = &sc->sc_ic; 7117 7118 timeout_del(&sc->calib_to); 7119 ifp->if_timer = sc->sc_tx_timer = 0; 7120 ifp->if_flags &= ~IFF_RUNNING; 7121 ifq_clr_oactive(&ifp->if_snd); 7122 7123 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 7124 7125 /* Power OFF hardware. */ 7126 iwn_hw_stop(sc); 7127 } 7128