1 /* $OpenBSD: if_iwn.c,v 1.63 2009/09/20 20:04:07 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2007-2009 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Driver for Intel Wireless WiFi Link 4965 and Intel WiFi Link 5000 Series 21 * 802.11 network adapters. 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/sysctl.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/conf.h> 35 #include <sys/device.h> 36 #include <sys/sensors.h> 37 38 #include <machine/bus.h> 39 #include <machine/endian.h> 40 #include <machine/intr.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 46 #if NBPFILTER > 0 47 #include <net/bpf.h> 48 #endif 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_types.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/if_ether.h> 59 #include <netinet/ip.h> 60 61 #include <net80211/ieee80211_var.h> 62 #include <net80211/ieee80211_amrr.h> 63 #include <net80211/ieee80211_radiotap.h> 64 65 #include <dev/pci/if_iwnreg.h> 66 #include <dev/pci/if_iwnvar.h> 67 68 static const struct pci_matchid iwn_devices[] = { 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_4965_1 }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_4965_2 }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_5100_1 }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_5100_2 }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_5150_1 }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_5150_2 }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_5300_1 }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_5300_2 }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_5350_1 }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_5350_2 }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_6000_1 }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_6000_2 }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_6000_3 }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_6000_4 }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_6000_5 }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_6000_6 }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_6050_1 }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_6050_2 }, 87 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_6050_3 }, 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_6050_4 }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_1000_1 }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WIFI_LINK_1000_2 } 91 }; 92 93 int iwn_match(struct device *, void *, void *); 94 void iwn_attach(struct device *, struct device *, void *); 95 const struct iwn_hal *iwn_hal_attach(struct iwn_softc *); 96 #ifndef SMALL_KERNEL 97 void iwn_sensor_attach(struct iwn_softc *); 98 #endif 99 #if NBPFILTER > 0 100 void iwn_radiotap_attach(struct iwn_softc *); 101 #endif 102 int iwn_detach(struct device *, int); 103 void iwn_power(int, void *); 104 int iwn_nic_lock(struct iwn_softc *); 105 int iwn_eeprom_lock(struct iwn_softc *); 106 int iwn_init_otprom(struct iwn_softc *); 107 int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 108 int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 109 void **, bus_size_t, bus_size_t); 110 void iwn_dma_contig_free(struct iwn_dma_info *); 111 int iwn_alloc_sched(struct iwn_softc *); 112 void iwn_free_sched(struct iwn_softc *); 113 int iwn_alloc_kw(struct iwn_softc *); 114 void iwn_free_kw(struct iwn_softc *); 115 int iwn_alloc_fwmem(struct iwn_softc *); 116 void iwn_free_fwmem(struct iwn_softc *); 117 int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 118 void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 119 void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 120 int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 121 int); 122 void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 123 void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 124 int iwn_read_eeprom(struct iwn_softc *); 125 void iwn4965_read_eeprom(struct iwn_softc *); 126 void iwn4965_print_power_group(struct iwn_softc *, int); 127 void iwn5000_read_eeprom(struct iwn_softc *); 128 void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 129 struct ieee80211_node *iwn_node_alloc(struct ieee80211com *); 130 void iwn_newassoc(struct ieee80211com *, struct ieee80211_node *, 131 int); 132 int iwn_media_change(struct ifnet *); 133 int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 134 void iwn_iter_func(void *, struct ieee80211_node *); 135 void iwn_calib_timeout(void *); 136 int iwn_ccmp_decap(struct iwn_softc *, struct mbuf *, 137 struct ieee80211_key *); 138 void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 139 struct iwn_rx_data *); 140 void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 141 struct iwn_rx_data *); 142 void iwn5000_rx_calib_results(struct iwn_softc *, 143 struct iwn_rx_desc *, struct iwn_rx_data *); 144 void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 145 struct iwn_rx_data *); 146 void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 147 struct iwn_rx_data *); 148 void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 149 struct iwn_rx_data *); 150 void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 151 uint8_t); 152 void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 153 void iwn_notif_intr(struct iwn_softc *); 154 void iwn_wakeup_intr(struct iwn_softc *); 155 void iwn_fatal_intr(struct iwn_softc *); 156 int iwn_intr(void *); 157 void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 158 uint16_t); 159 void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 160 uint16_t); 161 void iwn5000_reset_sched(struct iwn_softc *, int, int); 162 int iwn_tx(struct iwn_softc *, struct mbuf *, 163 struct ieee80211_node *); 164 void iwn_start(struct ifnet *); 165 void iwn_watchdog(struct ifnet *); 166 int iwn_ioctl(struct ifnet *, u_long, caddr_t); 167 int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 168 int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 169 int); 170 int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 171 int); 172 int iwn_set_link_quality(struct iwn_softc *, 173 struct ieee80211_node *); 174 int iwn_add_broadcast_node(struct iwn_softc *, int); 175 void iwn_updateedca(struct ieee80211com *); 176 void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 177 int iwn_set_critical_temp(struct iwn_softc *); 178 int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 179 void iwn4965_power_calibration(struct iwn_softc *, int); 180 int iwn4965_set_txpower(struct iwn_softc *, int); 181 int iwn5000_set_txpower(struct iwn_softc *, int); 182 int iwn4965_get_rssi(const struct iwn_rx_stat *); 183 int iwn5000_get_rssi(const struct iwn_rx_stat *); 184 int iwn_get_noise(const struct iwn_rx_general_stats *); 185 int iwn4965_get_temperature(struct iwn_softc *); 186 int iwn5000_get_temperature(struct iwn_softc *); 187 int iwn_init_sensitivity(struct iwn_softc *); 188 void iwn_collect_noise(struct iwn_softc *, 189 const struct iwn_rx_general_stats *); 190 int iwn4965_init_gains(struct iwn_softc *); 191 int iwn5000_init_gains(struct iwn_softc *); 192 int iwn4965_set_gains(struct iwn_softc *); 193 int iwn5000_set_gains(struct iwn_softc *); 194 void iwn_tune_sensitivity(struct iwn_softc *, 195 const struct iwn_rx_stats *); 196 int iwn_send_sensitivity(struct iwn_softc *); 197 int iwn_set_pslevel(struct iwn_softc *, int, int, int); 198 int iwn_config(struct iwn_softc *); 199 int iwn_scan(struct iwn_softc *, uint16_t); 200 int iwn_auth(struct iwn_softc *); 201 int iwn_run(struct iwn_softc *); 202 int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 203 struct ieee80211_key *); 204 void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 205 struct ieee80211_key *); 206 #ifndef IEEE80211_NO_HT 207 int iwn_ampdu_rx_start(struct ieee80211com *, 208 struct ieee80211_node *, uint8_t); 209 void iwn_ampdu_rx_stop(struct ieee80211com *, 210 struct ieee80211_node *, uint8_t); 211 int iwn_ampdu_tx_start(struct ieee80211com *, 212 struct ieee80211_node *, uint8_t); 213 void iwn_ampdu_tx_stop(struct ieee80211com *, 214 struct ieee80211_node *, uint8_t); 215 void iwn4965_ampdu_tx_start(struct iwn_softc *, 216 struct ieee80211_node *, uint8_t, uint16_t); 217 void iwn4965_ampdu_tx_stop(struct iwn_softc *, 218 uint8_t, uint16_t); 219 void iwn5000_ampdu_tx_start(struct iwn_softc *, 220 struct ieee80211_node *, uint8_t, uint16_t); 221 void iwn5000_ampdu_tx_stop(struct iwn_softc *, 222 uint8_t, uint16_t); 223 #endif 224 int iwn5000_query_calibration(struct iwn_softc *); 225 int iwn5000_send_calibration(struct iwn_softc *); 226 int iwn4965_post_alive(struct iwn_softc *); 227 int iwn5000_post_alive(struct iwn_softc *); 228 int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 229 int); 230 int iwn4965_load_firmware(struct iwn_softc *); 231 int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 232 const uint8_t *, int); 233 int iwn5000_load_firmware(struct iwn_softc *); 234 int iwn_read_firmware(struct iwn_softc *); 235 int iwn_clock_wait(struct iwn_softc *); 236 int iwn4965_apm_init(struct iwn_softc *); 237 int iwn5000_apm_init(struct iwn_softc *); 238 void iwn_apm_stop_master(struct iwn_softc *); 239 void iwn_apm_stop(struct iwn_softc *); 240 int iwn4965_nic_config(struct iwn_softc *); 241 int iwn5000_nic_config(struct iwn_softc *); 242 int iwn_hw_prepare(struct iwn_softc *); 243 int iwn_hw_init(struct iwn_softc *); 244 void iwn_hw_stop(struct iwn_softc *); 245 int iwn_init(struct ifnet *); 246 void iwn_stop(struct ifnet *, int); 247 248 #ifdef IWN_DEBUG 249 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 250 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 251 int iwn_debug = 0; 252 #else 253 #define DPRINTF(x) 254 #define DPRINTFN(n, x) 255 #endif 256 257 static const struct iwn_hal iwn4965_hal = { 258 iwn4965_load_firmware, 259 iwn4965_read_eeprom, 260 iwn4965_post_alive, 261 iwn4965_apm_init, 262 iwn4965_nic_config, 263 iwn4965_update_sched, 264 iwn4965_get_temperature, 265 iwn4965_get_rssi, 266 iwn4965_set_txpower, 267 iwn4965_init_gains, 268 iwn4965_set_gains, 269 iwn4965_add_node, 270 iwn4965_tx_done, 271 #ifndef IEEE80211_NO_HT 272 iwn4965_ampdu_tx_start, 273 iwn4965_ampdu_tx_stop, 274 #endif 275 &iwn4965_sensitivity_limits, 276 IWN4965_NTXQUEUES, 277 IWN4965_NDMACHNLS, 278 IWN4965_ID_BROADCAST, 279 IWN4965_RXONSZ, 280 IWN4965_SCHEDSZ, 281 IWN4965_FW_TEXT_MAXSZ, 282 IWN4965_FW_DATA_MAXSZ, 283 IWN4965_FWSZ, 284 IWN4965_SCHED_TXFACT 285 }; 286 287 static const struct iwn_hal iwn5000_hal = { 288 iwn5000_load_firmware, 289 iwn5000_read_eeprom, 290 iwn5000_post_alive, 291 iwn5000_apm_init, 292 iwn5000_nic_config, 293 iwn5000_update_sched, 294 iwn5000_get_temperature, 295 iwn5000_get_rssi, 296 iwn5000_set_txpower, 297 iwn5000_init_gains, 298 iwn5000_set_gains, 299 iwn5000_add_node, 300 iwn5000_tx_done, 301 #ifndef IEEE80211_NO_HT 302 iwn5000_ampdu_tx_start, 303 iwn5000_ampdu_tx_stop, 304 #endif 305 &iwn5000_sensitivity_limits, 306 IWN5000_NTXQUEUES, 307 IWN5000_NDMACHNLS, 308 IWN5000_ID_BROADCAST, 309 IWN5000_RXONSZ, 310 IWN5000_SCHEDSZ, 311 IWN5000_FW_TEXT_MAXSZ, 312 IWN5000_FW_DATA_MAXSZ, 313 IWN5000_FWSZ, 314 IWN5000_SCHED_TXFACT 315 }; 316 317 struct cfdriver iwn_cd = { 318 NULL, "iwn", DV_IFNET 319 }; 320 321 struct cfattach iwn_ca = { 322 sizeof (struct iwn_softc), iwn_match, iwn_attach, iwn_detach 323 }; 324 325 int 326 iwn_match(struct device *parent, void *match, void *aux) 327 { 328 return pci_matchbyid((struct pci_attach_args *)aux, iwn_devices, 329 nitems(iwn_devices)); 330 } 331 332 void 333 iwn_attach(struct device *parent, struct device *self, void *aux) 334 { 335 struct iwn_softc *sc = (struct iwn_softc *)self; 336 struct ieee80211com *ic = &sc->sc_ic; 337 struct ifnet *ifp = &ic->ic_if; 338 struct pci_attach_args *pa = aux; 339 const struct iwn_hal *hal; 340 const char *intrstr; 341 pci_intr_handle_t ih; 342 pcireg_t memtype, reg; 343 int i, error; 344 345 sc->sc_pct = pa->pa_pc; 346 sc->sc_pcitag = pa->pa_tag; 347 sc->sc_dmat = pa->pa_dmat; 348 349 /* 350 * Get the offset of the PCI Express Capability Structure in PCI 351 * Configuration Space. 352 */ 353 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 354 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 355 if (error == 0) { 356 printf(": PCIe capability structure not found!\n"); 357 return; 358 } 359 360 /* Clear device-specific "PCI retry timeout" register (41h). */ 361 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 362 reg &= ~0xff00; 363 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg); 364 365 /* Hardware bug workaround. */ 366 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 367 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 368 DPRINTF(("PCIe INTx Disable set\n")); 369 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 370 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 371 PCI_COMMAND_STATUS_REG, reg); 372 } 373 374 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 375 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 376 &sc->sc_sh, NULL, &sc->sc_sz, 0); 377 if (error != 0) { 378 printf(": can't map mem space\n"); 379 return; 380 } 381 382 /* Install interrupt handler. */ 383 if (pci_intr_map(pa, &ih) != 0) { 384 printf(": can't map interrupt\n"); 385 return; 386 } 387 intrstr = pci_intr_string(sc->sc_pct, ih); 388 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc, 389 sc->sc_dev.dv_xname); 390 if (sc->sc_ih == NULL) { 391 printf(": can't establish interrupt"); 392 if (intrstr != NULL) 393 printf(" at %s", intrstr); 394 printf("\n"); 395 return; 396 } 397 printf(": %s", intrstr); 398 399 /* Attach Hardware Abstraction Layer. */ 400 if ((hal = iwn_hal_attach(sc)) == NULL) 401 return; 402 403 if ((error = iwn_hw_prepare(sc)) != 0) { 404 printf(": hardware not ready\n"); 405 return; 406 } 407 408 /* Power ON adapter. */ 409 if ((error = hal->apm_init(sc)) != 0) { 410 printf(": could not power ON adapter\n"); 411 return; 412 } 413 414 /* Read MAC address, channels, etc from EEPROM. */ 415 if ((error = iwn_read_eeprom(sc)) != 0) { 416 printf(": could not read EEPROM\n"); 417 return; 418 } 419 420 /* Allocate DMA memory for firmware transfers. */ 421 if ((error = iwn_alloc_fwmem(sc)) != 0) { 422 printf(": could not allocate memory for firmware\n"); 423 return; 424 } 425 426 /* Allocate "Keep Warm" page. */ 427 if ((error = iwn_alloc_kw(sc)) != 0) { 428 printf(": could not allocate keep warm page\n"); 429 goto fail1; 430 } 431 432 /* Allocate TX scheduler "rings". */ 433 if ((error = iwn_alloc_sched(sc)) != 0) { 434 printf(": could not allocate TX scheduler rings\n"); 435 goto fail2; 436 } 437 438 /* Allocate TX rings (16 on 4965AGN, 20 on 5000.) */ 439 for (i = 0; i < hal->ntxqs; i++) { 440 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 441 printf(": could not allocate TX ring %d\n", i); 442 goto fail3; 443 } 444 } 445 446 /* Allocate RX ring. */ 447 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 448 printf(": could not allocate RX ring\n"); 449 goto fail3; 450 } 451 452 /* Power OFF adapter. */ 453 iwn_apm_stop(sc); 454 /* Clear pending interrupts. */ 455 IWN_WRITE(sc, IWN_INT, 0xffffffff); 456 457 printf(", MIMO %dT%dR, %.4s, address %s\n", sc->ntxchains, 458 sc->nrxchains, sc->eeprom_domain, ether_sprintf(ic->ic_myaddr)); 459 460 /* Initialization firmware has not been loaded yet. */ 461 sc->sc_flags |= IWN_FLAG_FIRST_BOOT; 462 463 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 464 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 465 ic->ic_state = IEEE80211_S_INIT; 466 467 /* Set device capabilities. */ 468 ic->ic_caps = 469 IEEE80211_C_WEP | /* WEP */ 470 IEEE80211_C_RSN | /* WPA/RSN */ 471 IEEE80211_C_MONITOR | /* monitor mode supported */ 472 IEEE80211_C_SHSLOT | /* short slot time supported */ 473 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 474 IEEE80211_C_PMGT; /* power saving supported */ 475 476 /* Set supported rates. */ 477 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 478 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 479 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 480 ic->ic_sup_rates[IEEE80211_MODE_11A] = 481 ieee80211_std_rateset_11a; 482 } 483 484 /* IBSS channel undefined for now. */ 485 ic->ic_ibss_chan = &ic->ic_channels[0]; 486 487 ifp->if_softc = sc; 488 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 489 ifp->if_init = iwn_init; 490 ifp->if_ioctl = iwn_ioctl; 491 ifp->if_start = iwn_start; 492 ifp->if_watchdog = iwn_watchdog; 493 IFQ_SET_READY(&ifp->if_snd); 494 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 495 496 if_attach(ifp); 497 ieee80211_ifattach(ifp); 498 ic->ic_node_alloc = iwn_node_alloc; 499 ic->ic_newassoc = iwn_newassoc; 500 ic->ic_updateedca = iwn_updateedca; 501 ic->ic_set_key = iwn_set_key; 502 ic->ic_delete_key = iwn_delete_key; 503 #ifndef IEEE80211_NO_HT 504 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 505 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 506 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 507 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 508 #endif 509 510 /* Override 802.11 state transition machine. */ 511 sc->sc_newstate = ic->ic_newstate; 512 ic->ic_newstate = iwn_newstate; 513 ieee80211_media_init(ifp, iwn_media_change, ieee80211_media_status); 514 515 sc->amrr.amrr_min_success_threshold = 1; 516 sc->amrr.amrr_max_success_threshold = 15; 517 518 #ifndef SMALL_KERNEL 519 iwn_sensor_attach(sc); 520 #endif 521 #if NBPFILTER > 0 522 iwn_radiotap_attach(sc); 523 #endif 524 timeout_set(&sc->calib_to, iwn_calib_timeout, sc); 525 526 sc->powerhook = powerhook_establish(iwn_power, sc); 527 528 return; 529 530 /* Free allocated memory if something failed during attachment. */ 531 fail3: while (--i >= 0) 532 iwn_free_tx_ring(sc, &sc->txq[i]); 533 iwn_free_sched(sc); 534 fail2: iwn_free_kw(sc); 535 fail1: iwn_free_fwmem(sc); 536 } 537 538 const struct iwn_hal * 539 iwn_hal_attach(struct iwn_softc *sc) 540 { 541 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 542 543 switch (sc->hw_type) { 544 case IWN_HW_REV_TYPE_4965: 545 sc->sc_hal = &iwn4965_hal; 546 sc->fwname = "iwn-4965"; 547 sc->critical_temp = IWN_CTOK(110); 548 sc->txantmsk = IWN_ANT_A | IWN_ANT_B; 549 sc->rxantmsk = IWN_ANT_ABC; 550 sc->ntxchains = 2; 551 sc->nrxchains = 3; 552 break; 553 case IWN_HW_REV_TYPE_5100: 554 sc->sc_hal = &iwn5000_hal; 555 sc->fwname = "iwn-5000"; 556 sc->critical_temp = 110; 557 sc->txantmsk = IWN_ANT_B; 558 sc->rxantmsk = IWN_ANT_A | IWN_ANT_B; 559 sc->ntxchains = 1; 560 sc->nrxchains = 2; 561 break; 562 case IWN_HW_REV_TYPE_5150: 563 sc->sc_hal = &iwn5000_hal; 564 sc->fwname = "iwn-5150"; 565 /* NB: critical temperature will be read from EEPROM. */ 566 sc->txantmsk = IWN_ANT_A; 567 sc->rxantmsk = IWN_ANT_A | IWN_ANT_B; 568 sc->ntxchains = 1; 569 sc->nrxchains = 2; 570 break; 571 case IWN_HW_REV_TYPE_5300: 572 case IWN_HW_REV_TYPE_5350: 573 sc->sc_hal = &iwn5000_hal; 574 sc->fwname = "iwn-5000"; 575 sc->critical_temp = 110; 576 sc->txantmsk = sc->rxantmsk = IWN_ANT_ABC; 577 sc->ntxchains = sc->nrxchains = 3; 578 break; 579 case IWN_HW_REV_TYPE_1000: 580 sc->sc_hal = &iwn5000_hal; 581 sc->fwname = "iwn-1000"; 582 sc->critical_temp = 110; 583 sc->txantmsk = IWN_ANT_A; 584 sc->rxantmsk = IWN_ANT_A | IWN_ANT_B; 585 sc->ntxchains = 1; 586 sc->nrxchains = 2; 587 break; 588 case IWN_HW_REV_TYPE_6000: 589 sc->sc_hal = &iwn5000_hal; 590 sc->fwname = "iwn-6000"; 591 sc->critical_temp = 110; 592 sc->txantmsk = IWN_ANT_ABC; 593 sc->rxantmsk = IWN_ANT_ABC; 594 sc->ntxchains = 3; 595 sc->nrxchains = 3; 596 break; 597 case IWN_HW_REV_TYPE_6050: 598 sc->sc_hal = &iwn5000_hal; 599 sc->fwname = "iwn-6050"; 600 sc->critical_temp = 110; 601 sc->txantmsk = IWN_ANT_ABC; 602 sc->rxantmsk = IWN_ANT_ABC; 603 sc->ntxchains = 3; 604 sc->nrxchains = 3; 605 break; 606 default: 607 printf(": adapter type %d not supported\n", sc->hw_type); 608 return NULL; 609 } 610 return sc->sc_hal; 611 } 612 613 #ifndef SMALL_KERNEL 614 /* 615 * Attach the adapter's on-board thermal sensor to the sensors framework. 616 */ 617 void 618 iwn_sensor_attach(struct iwn_softc *sc) 619 { 620 strlcpy(sc->sensordev.xname, sc->sc_dev.dv_xname, 621 sizeof sc->sensordev.xname); 622 sc->sensor.type = SENSOR_TEMP; 623 /* Temperature is not valid unless interface is up. */ 624 sc->sensor.flags = SENSOR_FINVALID; 625 sensor_attach(&sc->sensordev, &sc->sensor); 626 sensordev_install(&sc->sensordev); 627 } 628 #endif 629 630 #if NBPFILTER > 0 631 /* 632 * Attach the interface to 802.11 radiotap. 633 */ 634 void 635 iwn_radiotap_attach(struct iwn_softc *sc) 636 { 637 bpfattach(&sc->sc_drvbpf, &sc->sc_ic.ic_if, DLT_IEEE802_11_RADIO, 638 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 639 640 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 641 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 642 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 643 644 sc->sc_txtap_len = sizeof sc->sc_txtapu; 645 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 646 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 647 } 648 #endif 649 650 int 651 iwn_detach(struct device *self, int flags) 652 { 653 struct iwn_softc *sc = (struct iwn_softc *)self; 654 struct ifnet *ifp = &sc->sc_ic.ic_if; 655 int s, qid; 656 657 s = splnet(); 658 timeout_del(&sc->calib_to); 659 660 /* Uninstall interrupt handler. */ 661 if (sc->sc_ih != NULL) 662 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 663 664 ieee80211_ifdetach(ifp); 665 if_detach(ifp); 666 splx(s); 667 668 /* Free DMA resources. */ 669 iwn_free_rx_ring(sc, &sc->rxq); 670 for (qid = 0; qid < sc->sc_hal->ntxqs; qid++) 671 iwn_free_tx_ring(sc, &sc->txq[qid]); 672 iwn_free_sched(sc); 673 iwn_free_kw(sc); 674 iwn_free_fwmem(sc); 675 676 #ifndef SMALL_KERNEL 677 /* Detach the thermal sensor. */ 678 sensor_detach(&sc->sensordev, &sc->sensor); 679 sensordev_deinstall(&sc->sensordev); 680 #endif 681 682 if (sc->powerhook != NULL) 683 powerhook_disestablish(sc->powerhook); 684 685 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 686 687 return 0; 688 } 689 690 void 691 iwn_power(int why, void *arg) 692 { 693 struct iwn_softc *sc = arg; 694 struct ifnet *ifp; 695 pcireg_t reg; 696 int s; 697 698 if (why != PWR_RESUME) 699 return; 700 701 /* Clear device-specific "PCI retry timeout" register (41h). */ 702 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 703 reg &= ~0xff00; 704 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg); 705 706 s = splnet(); 707 ifp = &sc->sc_ic.ic_if; 708 if (ifp->if_flags & IFF_UP) { 709 ifp->if_init(ifp); 710 if (ifp->if_flags & IFF_RUNNING) 711 ifp->if_start(ifp); 712 } 713 splx(s); 714 } 715 716 int 717 iwn_nic_lock(struct iwn_softc *sc) 718 { 719 int ntries; 720 721 /* Request exclusive access to NIC. */ 722 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 723 724 /* Spin until we actually get the lock. */ 725 for (ntries = 0; ntries < 1000; ntries++) { 726 if ((IWN_READ(sc, IWN_GP_CNTRL) & 727 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 728 IWN_GP_CNTRL_MAC_ACCESS_ENA) 729 return 0; 730 DELAY(10); 731 } 732 return ETIMEDOUT; 733 } 734 735 static __inline void 736 iwn_nic_unlock(struct iwn_softc *sc) 737 { 738 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 739 } 740 741 static __inline uint32_t 742 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 743 { 744 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 745 return IWN_READ(sc, IWN_PRPH_RDATA); 746 } 747 748 static __inline void 749 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 750 { 751 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 752 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 753 } 754 755 static __inline void 756 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 757 { 758 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 759 } 760 761 static __inline void 762 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 763 { 764 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 765 } 766 767 static __inline void 768 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 769 const uint32_t *data, int count) 770 { 771 for (; count > 0; count--, data++, addr += 4) 772 iwn_prph_write(sc, addr, *data); 773 } 774 775 static __inline uint32_t 776 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 777 { 778 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 779 return IWN_READ(sc, IWN_MEM_RDATA); 780 } 781 782 static __inline void 783 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 784 { 785 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 786 IWN_WRITE(sc, IWN_MEM_WDATA, data); 787 } 788 789 static __inline void 790 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 791 { 792 uint32_t tmp; 793 794 tmp = iwn_mem_read(sc, addr & ~3); 795 if (addr & 3) 796 tmp = (tmp & 0x0000ffff) | data << 16; 797 else 798 tmp = (tmp & 0xffff0000) | data; 799 iwn_mem_write(sc, addr & ~3, tmp); 800 } 801 802 static __inline void 803 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 804 int count) 805 { 806 for (; count > 0; count--, addr += 4) 807 *data++ = iwn_mem_read(sc, addr); 808 } 809 810 static __inline void 811 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 812 int count) 813 { 814 for (; count > 0; count--, addr += 4) 815 iwn_mem_write(sc, addr, val); 816 } 817 818 int 819 iwn_eeprom_lock(struct iwn_softc *sc) 820 { 821 int i, ntries; 822 823 for (i = 0; i < 100; i++) { 824 /* Request exclusive access to EEPROM. */ 825 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 826 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 827 828 /* Spin until we actually get the lock. */ 829 for (ntries = 0; ntries < 100; ntries++) { 830 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 831 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 832 return 0; 833 DELAY(10); 834 } 835 } 836 return ETIMEDOUT; 837 } 838 839 static __inline void 840 iwn_eeprom_unlock(struct iwn_softc *sc) 841 { 842 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 843 } 844 845 /* 846 * Initialize access by host to One Time Programmable ROM. 847 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 848 */ 849 int 850 iwn_init_otprom(struct iwn_softc *sc) 851 { 852 int error; 853 854 if ((error = iwn_clock_wait(sc)) != 0) 855 return error; 856 857 if ((error = iwn_nic_lock(sc)) != 0) 858 return error; 859 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 860 DELAY(5); 861 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 862 iwn_nic_unlock(sc); 863 864 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 865 /* Clear ECC status. */ 866 IWN_SETBITS(sc, IWN_OTP_GP, 867 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 868 869 return 0; 870 } 871 872 int 873 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 874 { 875 uint8_t *out = data; 876 uint32_t val, tmp; 877 int ntries; 878 879 for (; count > 0; count -= 2, addr++) { 880 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 881 for (ntries = 0; ntries < 10; ntries++) { 882 val = IWN_READ(sc, IWN_EEPROM); 883 if (val & IWN_EEPROM_READ_VALID) 884 break; 885 DELAY(5); 886 } 887 if (ntries == 10) { 888 printf("%s: timeout reading ROM at 0x%x\n", 889 sc->sc_dev.dv_xname, addr); 890 return ETIMEDOUT; 891 } 892 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 893 /* OTPROM, check for ECC errors. */ 894 tmp = IWN_READ(sc, IWN_OTP_GP); 895 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 896 printf("%s: OTPROM ECC error at 0x%x\n", 897 sc->sc_dev.dv_xname, addr); 898 return EIO; 899 } 900 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 901 /* Correctable ECC error, clear bit. */ 902 IWN_SETBITS(sc, IWN_OTP_GP, 903 IWN_OTP_GP_ECC_CORR_STTS); 904 } 905 } 906 *out++ = val >> 16; 907 if (count > 1) 908 *out++ = val >> 24; 909 } 910 return 0; 911 } 912 913 int 914 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 915 bus_size_t size, bus_size_t alignment) 916 { 917 int nsegs, error; 918 919 dma->tag = tag; 920 dma->size = size; 921 922 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 923 &dma->map); 924 if (error != 0) 925 goto fail; 926 927 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 928 BUS_DMA_NOWAIT | BUS_DMA_ZERO); 929 if (error != 0) 930 goto fail; 931 932 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 933 BUS_DMA_NOWAIT); 934 if (error != 0) 935 goto fail; 936 937 error = bus_dmamap_load_raw(tag, dma->map, &dma->seg, 1, size, 938 BUS_DMA_NOWAIT); 939 if (error != 0) 940 goto fail; 941 942 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 943 944 dma->paddr = dma->map->dm_segs[0].ds_addr; 945 if (kvap != NULL) 946 *kvap = dma->vaddr; 947 948 return 0; 949 950 fail: iwn_dma_contig_free(dma); 951 return error; 952 } 953 954 void 955 iwn_dma_contig_free(struct iwn_dma_info *dma) 956 { 957 if (dma->map != NULL) { 958 if (dma->vaddr != NULL) { 959 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 960 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 961 bus_dmamap_unload(dma->tag, dma->map); 962 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 963 bus_dmamem_free(dma->tag, &dma->seg, 1); 964 dma->vaddr = NULL; 965 } 966 bus_dmamap_destroy(dma->tag, dma->map); 967 dma->map = NULL; 968 } 969 } 970 971 int 972 iwn_alloc_sched(struct iwn_softc *sc) 973 { 974 /* TX scheduler rings must be aligned on a 1KB boundary. */ 975 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 976 (void **)&sc->sched, sc->sc_hal->schedsz, 1024); 977 } 978 979 void 980 iwn_free_sched(struct iwn_softc *sc) 981 { 982 iwn_dma_contig_free(&sc->sched_dma); 983 } 984 985 int 986 iwn_alloc_kw(struct iwn_softc *sc) 987 { 988 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 989 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 990 4096); 991 } 992 993 void 994 iwn_free_kw(struct iwn_softc *sc) 995 { 996 iwn_dma_contig_free(&sc->kw_dma); 997 } 998 999 int 1000 iwn_alloc_fwmem(struct iwn_softc *sc) 1001 { 1002 /* Must be aligned on a 16-byte boundary. */ 1003 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1004 sc->sc_hal->fwsz, 16); 1005 } 1006 1007 void 1008 iwn_free_fwmem(struct iwn_softc *sc) 1009 { 1010 iwn_dma_contig_free(&sc->fw_dma); 1011 } 1012 1013 int 1014 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1015 { 1016 bus_size_t size; 1017 int i, error; 1018 1019 ring->cur = 0; 1020 1021 /* Allocate RX descriptors (256-byte aligned.) */ 1022 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1023 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1024 (void **)&ring->desc, size, 256); 1025 if (error != 0) { 1026 printf("%s: could not allocate RX ring DMA memory\n", 1027 sc->sc_dev.dv_xname); 1028 goto fail; 1029 } 1030 1031 /* Allocate RX status area (16-byte aligned.) */ 1032 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1033 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1034 if (error != 0) { 1035 printf("%s: could not allocate RX status DMA memory\n", 1036 sc->sc_dev.dv_xname); 1037 goto fail; 1038 } 1039 1040 /* 1041 * Allocate and map RX buffers. 1042 */ 1043 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1044 struct iwn_rx_data *data = &ring->data[i]; 1045 1046 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1047 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT, &data->map); 1048 if (error != 0) { 1049 printf("%s: could not create RX buf DMA map\n", 1050 sc->sc_dev.dv_xname); 1051 goto fail; 1052 } 1053 1054 data->m = MCLGETI(NULL, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1055 if (data->m == NULL) { 1056 printf("%s: could not allocate RX mbuf\n", 1057 sc->sc_dev.dv_xname); 1058 error = ENOBUFS; 1059 goto fail; 1060 } 1061 1062 error = bus_dmamap_load(sc->sc_dmat, data->map, 1063 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1064 BUS_DMA_NOWAIT); 1065 if (error != 0) { 1066 printf("%s: can't not map mbuf (error %d)\n", 1067 sc->sc_dev.dv_xname, error); 1068 goto fail; 1069 } 1070 1071 /* Set physical address of RX buffer (256-byte aligned.) */ 1072 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1073 } 1074 1075 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1076 BUS_DMASYNC_PREWRITE); 1077 1078 return 0; 1079 1080 fail: iwn_free_rx_ring(sc, ring); 1081 return error; 1082 } 1083 1084 void 1085 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1086 { 1087 int ntries; 1088 1089 if (iwn_nic_lock(sc) == 0) { 1090 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1091 for (ntries = 0; ntries < 1000; ntries++) { 1092 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1093 IWN_FH_RX_STATUS_IDLE) 1094 break; 1095 DELAY(10); 1096 } 1097 iwn_nic_unlock(sc); 1098 } 1099 ring->cur = 0; 1100 sc->last_rx_valid = 0; 1101 } 1102 1103 void 1104 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1105 { 1106 int i; 1107 1108 iwn_dma_contig_free(&ring->desc_dma); 1109 iwn_dma_contig_free(&ring->stat_dma); 1110 1111 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1112 struct iwn_rx_data *data = &ring->data[i]; 1113 1114 if (data->m != NULL) { 1115 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1116 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1117 bus_dmamap_unload(sc->sc_dmat, data->map); 1118 m_freem(data->m); 1119 } 1120 if (data->map != NULL) 1121 bus_dmamap_destroy(sc->sc_dmat, data->map); 1122 } 1123 } 1124 1125 int 1126 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1127 { 1128 bus_addr_t paddr; 1129 bus_size_t size; 1130 int i, error; 1131 1132 ring->qid = qid; 1133 ring->queued = 0; 1134 ring->cur = 0; 1135 1136 /* Allocate TX descriptors (256-byte aligned.) */ 1137 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1138 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1139 (void **)&ring->desc, size, 256); 1140 if (error != 0) { 1141 printf("%s: could not allocate TX ring DMA memory\n", 1142 sc->sc_dev.dv_xname); 1143 goto fail; 1144 } 1145 /* 1146 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1147 * to allocate commands space for other rings. 1148 * XXX Do we really need to allocate descriptors for other rings? 1149 */ 1150 if (qid > 4) 1151 return 0; 1152 1153 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1154 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1155 (void **)&ring->cmd, size, 4); 1156 if (error != 0) { 1157 printf("%s: could not allocate TX cmd DMA memory\n", 1158 sc->sc_dev.dv_xname); 1159 goto fail; 1160 } 1161 1162 paddr = ring->cmd_dma.paddr; 1163 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1164 struct iwn_tx_data *data = &ring->data[i]; 1165 1166 data->cmd_paddr = paddr; 1167 data->scratch_paddr = paddr + 12; 1168 paddr += sizeof (struct iwn_tx_cmd); 1169 1170 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1171 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1172 &data->map); 1173 if (error != 0) { 1174 printf("%s: could not create TX buf DMA map\n", 1175 sc->sc_dev.dv_xname); 1176 goto fail; 1177 } 1178 } 1179 return 0; 1180 1181 fail: iwn_free_tx_ring(sc, ring); 1182 return error; 1183 } 1184 1185 void 1186 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1187 { 1188 int i; 1189 1190 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1191 struct iwn_tx_data *data = &ring->data[i]; 1192 1193 if (data->m != NULL) { 1194 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1195 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1196 bus_dmamap_unload(sc->sc_dmat, data->map); 1197 m_freem(data->m); 1198 data->m = NULL; 1199 } 1200 } 1201 /* Clear TX descriptors. */ 1202 memset(ring->desc, 0, ring->desc_dma.size); 1203 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1204 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1205 sc->qfullmsk &= ~(1 << ring->qid); 1206 ring->queued = 0; 1207 ring->cur = 0; 1208 } 1209 1210 void 1211 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1212 { 1213 int i; 1214 1215 iwn_dma_contig_free(&ring->desc_dma); 1216 iwn_dma_contig_free(&ring->cmd_dma); 1217 1218 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1219 struct iwn_tx_data *data = &ring->data[i]; 1220 1221 if (data->m != NULL) { 1222 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1223 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1224 bus_dmamap_unload(sc->sc_dmat, data->map); 1225 m_freem(data->m); 1226 } 1227 if (data->map != NULL) 1228 bus_dmamap_destroy(sc->sc_dmat, data->map); 1229 } 1230 } 1231 1232 int 1233 iwn_read_eeprom(struct iwn_softc *sc) 1234 { 1235 const struct iwn_hal *hal = sc->sc_hal; 1236 struct ieee80211com *ic = &sc->sc_ic; 1237 uint16_t val; 1238 int error; 1239 1240 /* Check whether adapter has an EEPROM or an OTPROM. */ 1241 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1242 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1243 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1244 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1245 "OTPROM" : "EEPROM")); 1246 1247 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1248 printf("%s: bad ROM signature\n", sc->sc_dev.dv_xname); 1249 return EIO; 1250 } 1251 if ((error = iwn_eeprom_lock(sc)) != 0) { 1252 printf("%s: could not lock ROM (error=%d)\n", 1253 sc->sc_dev.dv_xname, error); 1254 return error; 1255 } 1256 1257 if ((sc->sc_flags & IWN_FLAG_HAS_OTPROM) && 1258 ((error = iwn_init_otprom(sc)) != 0)) { 1259 printf("%s: could not initialize OTPROM (error=%d)\n", 1260 sc->sc_dev.dv_xname, error); 1261 return error; 1262 } 1263 1264 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1265 sc->rfcfg = letoh16(val); 1266 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1267 1268 /* Read MAC address. */ 1269 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1270 1271 /* Read adapter-specific information from EEPROM. */ 1272 hal->read_eeprom(sc); 1273 1274 iwn_eeprom_unlock(sc); 1275 return 0; 1276 } 1277 1278 void 1279 iwn4965_read_eeprom(struct iwn_softc *sc) 1280 { 1281 uint32_t addr; 1282 uint16_t val; 1283 int i; 1284 1285 /* Read regulatory domain (4 ASCII characters.) */ 1286 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1287 1288 /* Read the list of authorized channels (20MHz ones only.) */ 1289 for (i = 0; i < 5; i++) { 1290 addr = iwn4965_regulatory_bands[i]; 1291 iwn_read_eeprom_channels(sc, i, addr); 1292 } 1293 1294 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1295 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1296 sc->maxpwr2GHz = val & 0xff; 1297 sc->maxpwr5GHz = val >> 8; 1298 /* Check that EEPROM values are within valid range. */ 1299 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1300 sc->maxpwr5GHz = 38; 1301 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1302 sc->maxpwr2GHz = 38; 1303 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1304 1305 /* Read samples for each TX power group. */ 1306 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1307 sizeof sc->bands); 1308 1309 /* Read voltage at which samples were taken. */ 1310 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1311 sc->eeprom_voltage = (int16_t)letoh16(val); 1312 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1313 1314 #ifdef IWN_DEBUG 1315 /* Print samples. */ 1316 if (iwn_debug > 0) { 1317 for (i = 0; i < IWN_NBANDS; i++) 1318 iwn4965_print_power_group(sc, i); 1319 } 1320 #endif 1321 } 1322 1323 #ifdef IWN_DEBUG 1324 void 1325 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1326 { 1327 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1328 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1329 int j, c; 1330 1331 printf("===band %d===\n", i); 1332 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1333 printf("chan1 num=%d\n", chans[0].num); 1334 for (c = 0; c < 2; c++) { 1335 for (j = 0; j < IWN_NSAMPLES; j++) { 1336 printf("chain %d, sample %d: temp=%d gain=%d " 1337 "power=%d pa_det=%d\n", c, j, 1338 chans[0].samples[c][j].temp, 1339 chans[0].samples[c][j].gain, 1340 chans[0].samples[c][j].power, 1341 chans[0].samples[c][j].pa_det); 1342 } 1343 } 1344 printf("chan2 num=%d\n", chans[1].num); 1345 for (c = 0; c < 2; c++) { 1346 for (j = 0; j < IWN_NSAMPLES; j++) { 1347 printf("chain %d, sample %d: temp=%d gain=%d " 1348 "power=%d pa_det=%d\n", c, j, 1349 chans[1].samples[c][j].temp, 1350 chans[1].samples[c][j].gain, 1351 chans[1].samples[c][j].power, 1352 chans[1].samples[c][j].pa_det); 1353 } 1354 } 1355 } 1356 #endif 1357 1358 void 1359 iwn5000_read_eeprom(struct iwn_softc *sc) 1360 { 1361 int32_t temp, volt, delta; 1362 uint32_t base, addr; 1363 uint16_t val; 1364 int i; 1365 1366 /* Read regulatory domain (4 ASCII characters.) */ 1367 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1368 base = letoh16(val); 1369 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1370 sc->eeprom_domain, 4); 1371 1372 /* Read the list of authorized channels (20MHz ones only.) */ 1373 for (i = 0; i < 5; i++) { 1374 addr = base + iwn5000_regulatory_bands[i]; 1375 iwn_read_eeprom_channels(sc, i, addr); 1376 } 1377 1378 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1379 base = letoh16(val); 1380 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1381 /* Compute critical temperature (in Kelvin.) */ 1382 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1383 temp = letoh16(val); 1384 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1385 volt = letoh16(val); 1386 delta = temp - (volt / -5); 1387 sc->critical_temp = (IWN_CTOK(110) - delta) * -5; 1388 DPRINTF(("temp=%d volt=%d delta=%dK\n", 1389 temp, volt, delta)); 1390 } else { 1391 /* Read crystal calibration. */ 1392 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1393 &sc->eeprom_crystal, sizeof (uint32_t)); 1394 DPRINTF(("crystal calibration 0x%08x\n", 1395 letoh32(sc->eeprom_crystal))); 1396 } 1397 } 1398 1399 void 1400 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1401 { 1402 struct ieee80211com *ic = &sc->sc_ic; 1403 const struct iwn_chan_band *band = &iwn_bands[n]; 1404 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1405 uint8_t chan; 1406 int i; 1407 1408 iwn_read_prom_data(sc, addr, channels, 1409 band->nchan * sizeof (struct iwn_eeprom_chan)); 1410 1411 for (i = 0; i < band->nchan; i++) { 1412 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1413 continue; 1414 1415 chan = band->chan[i]; 1416 1417 if (n == 0) { /* 2GHz band */ 1418 ic->ic_channels[chan].ic_freq = 1419 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1420 ic->ic_channels[chan].ic_flags = 1421 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1422 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1423 1424 } else { /* 5GHz band */ 1425 /* 1426 * Some adapters support channels 7, 8, 11 and 12 1427 * both in the 2GHz and 4.9GHz bands. 1428 * Because of limitations in our net80211 layer, 1429 * we don't support them in the 4.9GHz band. 1430 */ 1431 if (chan <= 14) 1432 continue; 1433 1434 ic->ic_channels[chan].ic_freq = 1435 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1436 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1437 /* We have at least one valid 5GHz channel. */ 1438 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1439 } 1440 1441 /* Is active scan allowed on this channel? */ 1442 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1443 ic->ic_channels[chan].ic_flags |= 1444 IEEE80211_CHAN_PASSIVE; 1445 } 1446 1447 /* Save maximum allowed TX power for this channel. */ 1448 sc->maxpwr[chan] = channels[i].maxpwr; 1449 1450 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1451 chan, channels[i].flags, sc->maxpwr[chan])); 1452 } 1453 } 1454 1455 struct ieee80211_node * 1456 iwn_node_alloc(struct ieee80211com *ic) 1457 { 1458 return malloc(sizeof (struct iwn_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1459 } 1460 1461 void 1462 iwn_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 1463 { 1464 struct iwn_softc *sc = ic->ic_if.if_softc; 1465 struct iwn_node *wn = (void *)ni; 1466 uint8_t rate; 1467 int ridx, i; 1468 1469 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1470 1471 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1472 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1473 /* Map 802.11 rate to HW rate index. */ 1474 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1475 if (iwn_rates[ridx].rate == rate) 1476 break; 1477 wn->ridx[i] = ridx; 1478 /* Initial TX rate <= 24Mbps. */ 1479 if (rate <= 48) 1480 ni->ni_txrate = i; 1481 } 1482 } 1483 1484 int 1485 iwn_media_change(struct ifnet *ifp) 1486 { 1487 struct iwn_softc *sc = ifp->if_softc; 1488 struct ieee80211com *ic = &sc->sc_ic; 1489 uint8_t rate, ridx; 1490 int error; 1491 1492 error = ieee80211_media_change(ifp); 1493 if (error != ENETRESET) 1494 return error; 1495 1496 if (ic->ic_fixed_rate != -1) { 1497 rate = ic->ic_sup_rates[ic->ic_curmode]. 1498 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1499 /* Map 802.11 rate to HW rate index. */ 1500 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1501 if (iwn_rates[ridx].rate == rate) 1502 break; 1503 sc->fixed_ridx = ridx; 1504 } 1505 1506 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1507 (IFF_UP | IFF_RUNNING)) { 1508 iwn_stop(ifp, 0); 1509 error = iwn_init(ifp); 1510 } 1511 return error; 1512 } 1513 1514 int 1515 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1516 { 1517 struct ifnet *ifp = &ic->ic_if; 1518 struct iwn_softc *sc = ifp->if_softc; 1519 int error; 1520 1521 timeout_del(&sc->calib_to); 1522 1523 switch (nstate) { 1524 case IEEE80211_S_SCAN: 1525 /* Make the link LED blink while we're scanning. */ 1526 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1527 1528 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ)) != 0) { 1529 printf("%s: could not initiate scan\n", 1530 sc->sc_dev.dv_xname); 1531 return error; 1532 } 1533 ic->ic_state = nstate; 1534 return 0; 1535 1536 case IEEE80211_S_ASSOC: 1537 if (ic->ic_state != IEEE80211_S_RUN) 1538 break; 1539 /* FALLTHROUGH */ 1540 case IEEE80211_S_AUTH: 1541 /* Reset state to handle reassociations correctly. */ 1542 sc->rxon.associd = 0; 1543 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1544 sc->calib.state = IWN_CALIB_STATE_INIT; 1545 1546 if ((error = iwn_auth(sc)) != 0) { 1547 printf("%s: could not move to auth state\n", 1548 sc->sc_dev.dv_xname); 1549 return error; 1550 } 1551 break; 1552 1553 case IEEE80211_S_RUN: 1554 if ((error = iwn_run(sc)) != 0) { 1555 printf("%s: could not move to run state\n", 1556 sc->sc_dev.dv_xname); 1557 return error; 1558 } 1559 break; 1560 1561 case IEEE80211_S_INIT: 1562 sc->calib.state = IWN_CALIB_STATE_INIT; 1563 break; 1564 } 1565 1566 return sc->sc_newstate(ic, nstate, arg); 1567 } 1568 1569 void 1570 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1571 { 1572 struct iwn_softc *sc = arg; 1573 struct iwn_node *wn = (struct iwn_node *)ni; 1574 1575 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1576 } 1577 1578 void 1579 iwn_calib_timeout(void *arg) 1580 { 1581 struct iwn_softc *sc = arg; 1582 struct ieee80211com *ic = &sc->sc_ic; 1583 int s; 1584 1585 if (ic->ic_fixed_rate == -1) { 1586 s = splnet(); 1587 if (ic->ic_opmode == IEEE80211_M_STA) 1588 iwn_iter_func(sc, ic->ic_bss); 1589 else 1590 ieee80211_iterate_nodes(ic, iwn_iter_func, sc); 1591 splx(s); 1592 } 1593 /* Force automatic TX power calibration every 60 secs. */ 1594 if (++sc->calib_cnt >= 120) { 1595 uint32_t flags = 0; 1596 1597 DPRINTF(("sending request for statistics\n")); 1598 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1599 sizeof flags, 1); 1600 sc->calib_cnt = 0; 1601 } 1602 /* Automatic rate control triggered every 500ms. */ 1603 timeout_add_msec(&sc->calib_to, 500); 1604 } 1605 1606 int 1607 iwn_ccmp_decap(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_key *k) 1608 { 1609 struct ieee80211_frame *wh; 1610 uint64_t pn, *prsc; 1611 uint8_t *ivp; 1612 uint8_t tid; 1613 int hdrlen; 1614 1615 wh = mtod(m, struct ieee80211_frame *); 1616 hdrlen = ieee80211_get_hdrlen(wh); 1617 ivp = (uint8_t *)wh + hdrlen; 1618 1619 /* Check that ExtIV bit is be set. */ 1620 if (!(ivp[3] & IEEE80211_WEP_EXTIV)) { 1621 DPRINTF(("CCMP decap ExtIV not set\n")); 1622 return 1; 1623 } 1624 tid = ieee80211_has_qos(wh) ? 1625 ieee80211_get_qos(wh) & IEEE80211_QOS_TID : 0; 1626 prsc = &k->k_rsc[tid]; 1627 1628 /* Extract the 48-bit PN from the CCMP header. */ 1629 pn = (uint64_t)ivp[0] | 1630 (uint64_t)ivp[1] << 8 | 1631 (uint64_t)ivp[4] << 16 | 1632 (uint64_t)ivp[5] << 24 | 1633 (uint64_t)ivp[6] << 32 | 1634 (uint64_t)ivp[7] << 40; 1635 if (pn <= *prsc) { 1636 /* 1637 * Not necessarily a replayed frame since we did not check 1638 * the sequence number of the 802.11 header yet. 1639 */ 1640 DPRINTF(("CCMP replayed\n")); 1641 return 1; 1642 } 1643 /* Update last seen packet number. */ 1644 *prsc = pn; 1645 1646 /* Clear Protected bit and strip IV. */ 1647 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1648 ovbcopy(wh, mtod(m, caddr_t) + IEEE80211_CCMP_HDRLEN, hdrlen); 1649 m_adj(m, IEEE80211_CCMP_HDRLEN); 1650 /* Strip MIC. */ 1651 m_adj(m, -IEEE80211_CCMP_MICLEN); 1652 return 0; 1653 } 1654 1655 /* 1656 * Process an RX_PHY firmware notification. This is usually immediately 1657 * followed by an MPDU_RX_DONE notification. 1658 */ 1659 void 1660 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1661 struct iwn_rx_data *data) 1662 { 1663 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1664 1665 DPRINTFN(2, ("received PHY stats\n")); 1666 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1667 sizeof (*stat), BUS_DMASYNC_POSTREAD); 1668 1669 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1670 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1671 sc->last_rx_valid = 1; 1672 } 1673 1674 /* 1675 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1676 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1677 */ 1678 void 1679 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1680 struct iwn_rx_data *data) 1681 { 1682 const struct iwn_hal *hal = sc->sc_hal; 1683 struct ieee80211com *ic = &sc->sc_ic; 1684 struct ifnet *ifp = &ic->ic_if; 1685 struct iwn_rx_ring *ring = &sc->rxq; 1686 struct ieee80211_frame *wh; 1687 struct ieee80211_rxinfo rxi; 1688 struct ieee80211_node *ni; 1689 struct mbuf *m, *m1; 1690 struct iwn_rx_stat *stat; 1691 caddr_t head; 1692 uint32_t flags; 1693 int error, len, rssi; 1694 1695 if (desc->type == IWN_MPDU_RX_DONE) { 1696 /* Check for prior RX_PHY notification. */ 1697 if (!sc->last_rx_valid) { 1698 DPRINTF(("missing RX_PHY\n")); 1699 ifp->if_ierrors++; 1700 return; 1701 } 1702 sc->last_rx_valid = 0; 1703 stat = &sc->last_rx_stat; 1704 } else 1705 stat = (struct iwn_rx_stat *)(desc + 1); 1706 1707 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 1708 BUS_DMASYNC_POSTREAD); 1709 1710 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 1711 printf("%s: invalid RX statistic header\n", 1712 sc->sc_dev.dv_xname); 1713 ifp->if_ierrors++; 1714 return; 1715 } 1716 if (desc->type == IWN_MPDU_RX_DONE) { 1717 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 1718 head = (caddr_t)(mpdu + 1); 1719 len = letoh16(mpdu->len); 1720 } else { 1721 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 1722 len = letoh16(stat->len); 1723 } 1724 1725 flags = letoh32(*(uint32_t *)(head + len)); 1726 1727 /* Discard frames with a bad FCS early. */ 1728 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 1729 DPRINTFN(2, ("RX flags error %x\n", flags)); 1730 ifp->if_ierrors++; 1731 return; 1732 } 1733 /* Discard frames that are too short. */ 1734 if (len < sizeof (*wh)) { 1735 DPRINTF(("frame too short: %d\n", len)); 1736 ic->ic_stats.is_rx_tooshort++; 1737 ifp->if_ierrors++; 1738 return; 1739 } 1740 1741 m1 = MCLGETI(NULL, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1742 if (m1 == NULL) { 1743 ic->ic_stats.is_rx_nombuf++; 1744 ifp->if_ierrors++; 1745 return; 1746 } 1747 bus_dmamap_unload(sc->sc_dmat, data->map); 1748 1749 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 1750 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT); 1751 if (error != 0) { 1752 m_freem(m1); 1753 1754 /* Try to reload the old mbuf. */ 1755 error = bus_dmamap_load(sc->sc_dmat, data->map, 1756 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1757 BUS_DMA_NOWAIT); 1758 if (error != 0) { 1759 panic("%s: could not load old RX mbuf", 1760 sc->sc_dev.dv_xname); 1761 } 1762 /* Physical address may have changed. */ 1763 ring->desc[ring->cur] = 1764 htole32(data->map->dm_segs[0].ds_addr >> 8); 1765 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 1766 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 1767 BUS_DMASYNC_PREWRITE); 1768 ifp->if_ierrors++; 1769 return; 1770 } 1771 1772 m = data->m; 1773 data->m = m1; 1774 /* Update RX descriptor. */ 1775 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1776 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 1777 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 1778 BUS_DMASYNC_PREWRITE); 1779 1780 /* Finalize mbuf. */ 1781 m->m_pkthdr.rcvif = ifp; 1782 m->m_data = head; 1783 m->m_pkthdr.len = m->m_len = len; 1784 1785 /* Grab a reference to the source node. */ 1786 wh = mtod(m, struct ieee80211_frame *); 1787 ni = ieee80211_find_rxnode(ic, wh); 1788 1789 rxi.rxi_flags = 0; 1790 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1791 !IEEE80211_IS_MULTICAST(wh->i_addr1) && 1792 (ni->ni_flags & IEEE80211_NODE_RXPROT) && 1793 ni->ni_pairwise_key.k_cipher == IEEE80211_CIPHER_CCMP) { 1794 if ((flags & IWN_RX_CIPHER_MASK) != IWN_RX_CIPHER_CCMP) { 1795 ic->ic_stats.is_ccmp_dec_errs++; 1796 ifp->if_ierrors++; 1797 m_freem(m); 1798 return; 1799 } 1800 /* Check whether decryption was successful or not. */ 1801 if ((desc->type == IWN_MPDU_RX_DONE && 1802 (flags & (IWN_RX_MPDU_DEC | IWN_RX_MPDU_MIC_OK)) != 1803 (IWN_RX_MPDU_DEC | IWN_RX_MPDU_MIC_OK)) || 1804 (desc->type != IWN_MPDU_RX_DONE && 1805 (flags & IWN_RX_DECRYPT_MASK) != IWN_RX_DECRYPT_OK)) { 1806 DPRINTF(("CCMP decryption failed 0x%x\n", flags)); 1807 ic->ic_stats.is_ccmp_dec_errs++; 1808 ifp->if_ierrors++; 1809 m_freem(m); 1810 return; 1811 } 1812 if (iwn_ccmp_decap(sc, m, &ni->ni_pairwise_key) != 0) { 1813 ifp->if_ierrors++; 1814 m_freem(m); 1815 return; 1816 } 1817 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 1818 } 1819 1820 rssi = hal->get_rssi(stat); 1821 1822 #if NBPFILTER > 0 1823 if (sc->sc_drvbpf != NULL) { 1824 struct mbuf mb; 1825 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1826 1827 tap->wr_flags = 0; 1828 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 1829 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1830 tap->wr_chan_freq = 1831 htole16(ic->ic_channels[stat->chan].ic_freq); 1832 tap->wr_chan_flags = 1833 htole16(ic->ic_channels[stat->chan].ic_flags); 1834 tap->wr_dbm_antsignal = (int8_t)rssi; 1835 tap->wr_dbm_antnoise = (int8_t)sc->noise; 1836 tap->wr_tsft = stat->tstamp; 1837 switch (stat->rate) { 1838 /* CCK rates. */ 1839 case 10: tap->wr_rate = 2; break; 1840 case 20: tap->wr_rate = 4; break; 1841 case 55: tap->wr_rate = 11; break; 1842 case 110: tap->wr_rate = 22; break; 1843 /* OFDM rates. */ 1844 case 0xd: tap->wr_rate = 12; break; 1845 case 0xf: tap->wr_rate = 18; break; 1846 case 0x5: tap->wr_rate = 24; break; 1847 case 0x7: tap->wr_rate = 36; break; 1848 case 0x9: tap->wr_rate = 48; break; 1849 case 0xb: tap->wr_rate = 72; break; 1850 case 0x1: tap->wr_rate = 96; break; 1851 case 0x3: tap->wr_rate = 108; break; 1852 /* Unknown rate: should not happen. */ 1853 default: tap->wr_rate = 0; 1854 } 1855 1856 mb.m_data = (caddr_t)tap; 1857 mb.m_len = sc->sc_rxtap_len; 1858 mb.m_next = m; 1859 mb.m_nextpkt = NULL; 1860 mb.m_type = 0; 1861 mb.m_flags = 0; 1862 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1863 } 1864 #endif 1865 1866 /* Send the frame to the 802.11 layer. */ 1867 rxi.rxi_rssi = rssi; 1868 rxi.rxi_tstamp = 0; /* unused */ 1869 ieee80211_input(ifp, m, ni, &rxi); 1870 1871 /* Node is no longer needed. */ 1872 ieee80211_release_node(ic, ni); 1873 } 1874 1875 /* 1876 * Process a CALIBRATION_RESULT notification sent by the initialization 1877 * firmware on response to a CMD_CALIB_CONFIG command (5000 only.) 1878 */ 1879 void 1880 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1881 struct iwn_rx_data *data) 1882 { 1883 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 1884 int len, idx = -1; 1885 1886 /* Runtime firmware should not send such a notification. */ 1887 if (!(sc->sc_flags & IWN_FLAG_FIRST_BOOT)) 1888 return; 1889 1890 len = (letoh32(desc->len) & 0x3fff) - 4; 1891 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 1892 BUS_DMASYNC_POSTREAD); 1893 1894 switch (calib->code) { 1895 case IWN5000_PHY_CALIB_DC: 1896 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 1897 idx = 0; 1898 break; 1899 case IWN5000_PHY_CALIB_LO: 1900 idx = 1; 1901 break; 1902 case IWN5000_PHY_CALIB_TX_IQ: 1903 idx = 2; 1904 break; 1905 case IWN5000_PHY_CALIB_TX_IQ_PERD: 1906 if (sc->hw_type != IWN_HW_REV_TYPE_5150) 1907 idx = 3; 1908 break; 1909 case IWN5000_PHY_CALIB_BASE_BAND: 1910 idx = 4; 1911 break; 1912 } 1913 if (idx == -1) /* Ignore other results. */ 1914 return; 1915 1916 /* Save calibration result. */ 1917 if (sc->calibcmd[idx].buf != NULL) 1918 free(sc->calibcmd[idx].buf, M_DEVBUF); 1919 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 1920 if (sc->calibcmd[idx].buf == NULL) { 1921 DPRINTF(("not enough memory for calibration result %d\n", 1922 calib->code)); 1923 return; 1924 } 1925 DPRINTF(("saving calibration result code=%d len=%d\n", 1926 calib->code, len)); 1927 sc->calibcmd[idx].len = len; 1928 memcpy(sc->calibcmd[idx].buf, calib, len); 1929 } 1930 1931 /* 1932 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 1933 * The latter is sent by the firmware after each received beacon. 1934 */ 1935 void 1936 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1937 struct iwn_rx_data *data) 1938 { 1939 const struct iwn_hal *hal = sc->sc_hal; 1940 struct ieee80211com *ic = &sc->sc_ic; 1941 struct iwn_calib_state *calib = &sc->calib; 1942 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 1943 int temp; 1944 1945 /* Ignore statistics received during a scan. */ 1946 if (ic->ic_state != IEEE80211_S_RUN) 1947 return; 1948 1949 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1950 sizeof (*stats), BUS_DMASYNC_POSTREAD); 1951 1952 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 1953 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 1954 1955 /* Test if temperature has changed. */ 1956 if (stats->general.temp != sc->rawtemp) { 1957 /* Convert "raw" temperature to degC. */ 1958 sc->rawtemp = stats->general.temp; 1959 temp = hal->get_temperature(sc); 1960 DPRINTFN(2, ("temperature=%dC\n", temp)); 1961 1962 /* Update temperature sensor. */ 1963 sc->sensor.value = IWN_CTOMUK(temp); 1964 sc->sensor.flags &= ~SENSOR_FINVALID; 1965 1966 /* Update TX power if need be (4965AGN only.) */ 1967 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 1968 iwn4965_power_calibration(sc, temp); 1969 } 1970 1971 if (desc->type != IWN_BEACON_STATISTICS) 1972 return; /* Reply to a statistics request. */ 1973 1974 sc->noise = iwn_get_noise(&stats->rx.general); 1975 1976 /* Test that RSSI and noise are present in stats report. */ 1977 if (letoh32(stats->rx.general.flags) != 1) { 1978 DPRINTF(("received statistics without RSSI\n")); 1979 return; 1980 } 1981 1982 if (calib->state == IWN_CALIB_STATE_ASSOC) 1983 iwn_collect_noise(sc, &stats->rx.general); 1984 else if (calib->state == IWN_CALIB_STATE_RUN) 1985 iwn_tune_sensitivity(sc, &stats->rx); 1986 } 1987 1988 /* 1989 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 1990 * and 5000 adapters have different incompatible TX status formats. 1991 */ 1992 void 1993 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1994 struct iwn_rx_data *data) 1995 { 1996 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 1997 1998 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1999 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2000 iwn_tx_done(sc, desc, stat->retrycnt, letoh32(stat->status) & 0xff); 2001 } 2002 2003 void 2004 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2005 struct iwn_rx_data *data) 2006 { 2007 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2008 2009 /* Reset TX scheduler slot. */ 2010 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2011 2012 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2013 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2014 iwn_tx_done(sc, desc, stat->retrycnt, letoh16(stat->status) & 0xff); 2015 } 2016 2017 /* 2018 * Adapter-independent backend for TX_DONE firmware notifications. 2019 */ 2020 void 2021 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int retrycnt, 2022 uint8_t status) 2023 { 2024 struct ieee80211com *ic = &sc->sc_ic; 2025 struct ifnet *ifp = &ic->ic_if; 2026 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2027 struct iwn_tx_data *data = &ring->data[desc->idx]; 2028 struct iwn_node *wn = (struct iwn_node *)data->ni; 2029 2030 /* Update rate control statistics. */ 2031 wn->amn.amn_txcnt++; 2032 if (retrycnt > 0) 2033 wn->amn.amn_retrycnt++; 2034 2035 if (status != 1 && status != 2) 2036 ifp->if_oerrors++; 2037 else 2038 ifp->if_opackets++; 2039 2040 /* Unmap and free mbuf. */ 2041 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2042 BUS_DMASYNC_POSTWRITE); 2043 bus_dmamap_unload(sc->sc_dmat, data->map); 2044 m_freem(data->m); 2045 data->m = NULL; 2046 ieee80211_release_node(ic, data->ni); 2047 data->ni = NULL; 2048 2049 sc->sc_tx_timer = 0; 2050 if (--ring->queued < IWN_TX_RING_LOMARK) { 2051 sc->qfullmsk &= ~(1 << ring->qid); 2052 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) { 2053 ifp->if_flags &= ~IFF_OACTIVE; 2054 (*ifp->if_start)(ifp); 2055 } 2056 } 2057 } 2058 2059 /* 2060 * Process a "command done" firmware notification. This is where we wakeup 2061 * processes waiting for a synchronous command completion. 2062 */ 2063 void 2064 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2065 { 2066 struct iwn_tx_ring *ring = &sc->txq[4]; 2067 struct iwn_tx_data *data; 2068 2069 if ((desc->qid & 0xf) != 4) 2070 return; /* Not a command ack. */ 2071 2072 data = &ring->data[desc->idx]; 2073 2074 /* If the command was mapped in an mbuf, free it. */ 2075 if (data->m != NULL) { 2076 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2077 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2078 bus_dmamap_unload(sc->sc_dmat, data->map); 2079 m_freem(data->m); 2080 data->m = NULL; 2081 } 2082 wakeup(&ring->desc[desc->idx]); 2083 } 2084 2085 /* 2086 * Process an INT_FH_RX or INT_SW_RX interrupt. 2087 */ 2088 void 2089 iwn_notif_intr(struct iwn_softc *sc) 2090 { 2091 struct ieee80211com *ic = &sc->sc_ic; 2092 struct ifnet *ifp = &ic->ic_if; 2093 uint16_t hw; 2094 2095 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2096 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2097 2098 hw = letoh16(sc->rxq.stat->closed_count) & 0xfff; 2099 while (sc->rxq.cur != hw) { 2100 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2101 struct iwn_rx_desc *desc; 2102 2103 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2104 BUS_DMASYNC_POSTREAD); 2105 desc = mtod(data->m, struct iwn_rx_desc *); 2106 2107 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2108 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2109 2110 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2111 iwn_cmd_done(sc, desc); 2112 2113 switch (desc->type) { 2114 case IWN_RX_PHY: 2115 iwn_rx_phy(sc, desc, data); 2116 break; 2117 2118 case IWN_RX_DONE: /* 4965AGN only. */ 2119 case IWN_MPDU_RX_DONE: 2120 /* An 802.11 frame has been received. */ 2121 iwn_rx_done(sc, desc, data); 2122 break; 2123 2124 case IWN_TX_DONE: 2125 /* An 802.11 frame has been transmitted. */ 2126 sc->sc_hal->tx_done(sc, desc, data); 2127 break; 2128 2129 case IWN_RX_STATISTICS: 2130 case IWN_BEACON_STATISTICS: 2131 iwn_rx_statistics(sc, desc, data); 2132 break; 2133 2134 case IWN_BEACON_MISSED: 2135 { 2136 struct iwn_beacon_missed *miss = 2137 (struct iwn_beacon_missed *)(desc + 1); 2138 2139 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2140 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2141 /* 2142 * If more than 5 consecutive beacons are missed, 2143 * reinitialize the sensitivity state machine. 2144 */ 2145 DPRINTF(("beacons missed %d/%d\n", 2146 letoh32(miss->consecutive), letoh32(miss->total))); 2147 if (ic->ic_state == IEEE80211_S_RUN && 2148 letoh32(miss->consecutive) > 5) 2149 (void)iwn_init_sensitivity(sc); 2150 break; 2151 } 2152 case IWN_UC_READY: 2153 { 2154 struct iwn_ucode_info *uc = 2155 (struct iwn_ucode_info *)(desc + 1); 2156 2157 /* The microcontroller is ready. */ 2158 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2159 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2160 DPRINTF(("microcode alive notification version=%d.%d " 2161 "subtype=%x alive=%x\n", uc->major, uc->minor, 2162 uc->subtype, letoh32(uc->valid))); 2163 2164 if (letoh32(uc->valid) != 1) { 2165 printf("%s: microcontroller initialization " 2166 "failed\n", sc->sc_dev.dv_xname); 2167 break; 2168 } 2169 if (uc->subtype == IWN_UCODE_INIT) { 2170 /* Save microcontroller's report. */ 2171 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2172 } 2173 /* Save the address of the error log in SRAM. */ 2174 sc->errptr = letoh32(uc->errptr); 2175 break; 2176 } 2177 case IWN_STATE_CHANGED: 2178 { 2179 uint32_t *status = (uint32_t *)(desc + 1); 2180 2181 /* Enabled/disabled notification. */ 2182 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2183 sizeof (*status), BUS_DMASYNC_POSTREAD); 2184 DPRINTF(("state changed to %x\n", letoh32(*status))); 2185 2186 if (letoh32(*status) & 1) { 2187 /* The radio button has to be pushed. */ 2188 printf("%s: Radio transmitter is off\n", 2189 sc->sc_dev.dv_xname); 2190 /* Turn the interface down. */ 2191 ifp->if_flags &= ~IFF_UP; 2192 iwn_stop(ifp, 1); 2193 return; /* No further processing. */ 2194 } 2195 break; 2196 } 2197 case IWN_START_SCAN: 2198 { 2199 struct iwn_start_scan *scan = 2200 (struct iwn_start_scan *)(desc + 1); 2201 2202 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2203 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2204 DPRINTFN(2, ("scanning channel %d status %x\n", 2205 scan->chan, letoh32(scan->status))); 2206 2207 /* Fix current channel. */ 2208 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 2209 break; 2210 } 2211 case IWN_STOP_SCAN: 2212 { 2213 struct iwn_stop_scan *scan = 2214 (struct iwn_stop_scan *)(desc + 1); 2215 2216 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2217 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2218 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n", 2219 scan->nchan, scan->status, scan->chan)); 2220 2221 if (scan->status == 1 && scan->chan <= 14 && 2222 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 2223 /* 2224 * We just finished scanning 2GHz channels, 2225 * start scanning 5GHz ones. 2226 */ 2227 if (iwn_scan(sc, IEEE80211_CHAN_5GHZ) == 0) 2228 break; 2229 } 2230 ieee80211_end_scan(ifp); 2231 break; 2232 } 2233 case IWN5000_CALIBRATION_RESULT: 2234 iwn5000_rx_calib_results(sc, desc, data); 2235 break; 2236 2237 case IWN5000_CALIBRATION_DONE: 2238 wakeup(sc); 2239 break; 2240 } 2241 2242 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2243 } 2244 2245 /* Tell the firmware what we have processed. */ 2246 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2247 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2248 } 2249 2250 /* 2251 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2252 * from power-down sleep mode. 2253 */ 2254 void 2255 iwn_wakeup_intr(struct iwn_softc *sc) 2256 { 2257 int qid; 2258 2259 DPRINTF(("ucode wakeup from power-down sleep\n")); 2260 2261 /* Wakeup RX and TX rings. */ 2262 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2263 for (qid = 0; qid < 6; qid++) { 2264 struct iwn_tx_ring *ring = &sc->txq[qid]; 2265 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2266 } 2267 } 2268 2269 /* 2270 * Dump the error log of the firmware when a firmware panic occurs. Although 2271 * we can't debug the firmware because it is neither open source nor free, it 2272 * can help us to identify certain classes of problems. 2273 */ 2274 void 2275 iwn_fatal_intr(struct iwn_softc *sc) 2276 { 2277 const struct iwn_hal *hal = sc->sc_hal; 2278 struct iwn_fw_dump dump; 2279 int i; 2280 2281 /* Check that the error log address is valid. */ 2282 if (sc->errptr < IWN_FW_DATA_BASE || 2283 sc->errptr + sizeof (dump) > 2284 IWN_FW_DATA_BASE + hal->fw_data_maxsz) { 2285 printf("%s: bad firmware error log address 0x%08x\n", 2286 sc->sc_dev.dv_xname, sc->errptr); 2287 return; 2288 } 2289 if (iwn_nic_lock(sc) != 0) { 2290 printf("%s: could not read firmware error log\n", 2291 sc->sc_dev.dv_xname); 2292 return; 2293 } 2294 /* Read firmware error log from SRAM. */ 2295 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2296 sizeof (dump) / sizeof (uint32_t)); 2297 iwn_nic_unlock(sc); 2298 2299 if (dump.valid == 0) { 2300 printf("%s: firmware error log is empty\n", 2301 sc->sc_dev.dv_xname); 2302 return; 2303 } 2304 printf("firmware error log:\n"); 2305 printf(" error type = \"%s\" (0x%08X)\n", 2306 (dump.id < nitems(iwn_fw_errmsg)) ? 2307 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2308 dump.id); 2309 printf(" program counter = 0x%08X\n", dump.pc); 2310 printf(" source line = 0x%08X\n", dump.src_line); 2311 printf(" error data = 0x%08X%08X\n", 2312 dump.error_data[0], dump.error_data[1]); 2313 printf(" branch link = 0x%08X%08X\n", 2314 dump.branch_link[0], dump.branch_link[1]); 2315 printf(" interrupt link = 0x%08X%08X\n", 2316 dump.interrupt_link[0], dump.interrupt_link[1]); 2317 printf(" time = %u\n", dump.time[0]); 2318 2319 /* Dump driver status (TX and RX rings) while we're here. */ 2320 printf("driver status:\n"); 2321 for (i = 0; i < hal->ntxqs; i++) { 2322 struct iwn_tx_ring *ring = &sc->txq[i]; 2323 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2324 i, ring->qid, ring->cur, ring->queued); 2325 } 2326 printf(" rx ring: cur=%d\n", sc->rxq.cur); 2327 printf(" 802.11 state %d\n", sc->sc_ic.ic_state); 2328 } 2329 2330 int 2331 iwn_intr(void *arg) 2332 { 2333 struct iwn_softc *sc = arg; 2334 struct ifnet *ifp = &sc->sc_ic.ic_if; 2335 uint32_t r1, r2; 2336 2337 /* Disable interrupts. */ 2338 IWN_WRITE(sc, IWN_MASK, 0); 2339 2340 r1 = IWN_READ(sc, IWN_INT); 2341 r2 = IWN_READ(sc, IWN_FH_INT); 2342 2343 if (r1 == 0 && r2 == 0) { 2344 if (ifp->if_flags & IFF_UP) 2345 IWN_WRITE(sc, IWN_MASK, IWN_INT_MASK); 2346 return 0; /* Interrupt not for us. */ 2347 } 2348 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2349 return 0; /* Hardware gone! */ 2350 2351 /* Acknowledge interrupts. */ 2352 IWN_WRITE(sc, IWN_INT, r1); 2353 IWN_WRITE(sc, IWN_FH_INT, r2); 2354 2355 if (r1 & IWN_INT_RF_TOGGLED) { 2356 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL); 2357 printf("%s: RF switch: radio %s\n", sc->sc_dev.dv_xname, 2358 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2359 } 2360 if (r1 & IWN_INT_CT_REACHED) { 2361 printf("%s: critical temperature reached!\n", 2362 sc->sc_dev.dv_xname); 2363 /* XXX Reduce TX power? */ 2364 } 2365 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2366 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 2367 /* Dump firmware error log and stop. */ 2368 iwn_fatal_intr(sc); 2369 ifp->if_flags &= ~IFF_UP; 2370 iwn_stop(ifp, 1); 2371 return 1; 2372 } 2373 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) || 2374 (r2 & IWN_FH_INT_RX)) 2375 iwn_notif_intr(sc); 2376 2377 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) 2378 wakeup(sc); /* FH DMA transfer completed. */ 2379 2380 if (r1 & IWN_INT_ALIVE) 2381 wakeup(sc); /* Firmware is alive. */ 2382 2383 if (r1 & IWN_INT_WAKEUP) 2384 iwn_wakeup_intr(sc); 2385 2386 /* Re-enable interrupts. */ 2387 if (ifp->if_flags & IFF_UP) 2388 IWN_WRITE(sc, IWN_MASK, IWN_INT_MASK); 2389 2390 return 1; 2391 } 2392 2393 /* 2394 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2395 * 5000 adapters use a slightly different format.) 2396 */ 2397 void 2398 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2399 uint16_t len) 2400 { 2401 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2402 2403 *w = htole16(len + 8); 2404 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2405 (caddr_t)w - sc->sched_dma.vaddr, sizeof (uint16_t), 2406 BUS_DMASYNC_PREWRITE); 2407 if (idx < IWN_SCHED_WINSZ) { 2408 *(w + IWN_TX_RING_COUNT) = *w; 2409 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2410 (caddr_t)(w + IWN_TX_RING_COUNT) - sc->sched_dma.vaddr, 2411 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2412 } 2413 } 2414 2415 void 2416 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2417 uint16_t len) 2418 { 2419 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2420 2421 *w = htole16(id << 12 | (len + 8)); 2422 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2423 (caddr_t)w - sc->sched_dma.vaddr, sizeof (uint16_t), 2424 BUS_DMASYNC_PREWRITE); 2425 if (idx < IWN_SCHED_WINSZ) { 2426 *(w + IWN_TX_RING_COUNT) = *w; 2427 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2428 (caddr_t)(w + IWN_TX_RING_COUNT) - sc->sched_dma.vaddr, 2429 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2430 } 2431 } 2432 2433 void 2434 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2435 { 2436 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2437 2438 *w = (*w & htole16(0xf000)) | htole16(1); 2439 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2440 (caddr_t)w - sc->sched_dma.vaddr, sizeof (uint16_t), 2441 BUS_DMASYNC_PREWRITE); 2442 if (idx < IWN_SCHED_WINSZ) { 2443 *(w + IWN_TX_RING_COUNT) = *w; 2444 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2445 (caddr_t)(w + IWN_TX_RING_COUNT) - sc->sched_dma.vaddr, 2446 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2447 } 2448 } 2449 2450 int 2451 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2452 { 2453 const struct iwn_hal *hal = sc->sc_hal; 2454 struct ieee80211com *ic = &sc->sc_ic; 2455 struct iwn_node *wn = (void *)ni; 2456 struct iwn_tx_ring *ring; 2457 struct iwn_tx_desc *desc; 2458 struct iwn_tx_data *data; 2459 struct iwn_tx_cmd *cmd; 2460 struct iwn_cmd_data *tx; 2461 const struct iwn_rate *rinfo; 2462 struct ieee80211_frame *wh; 2463 struct ieee80211_key *k = NULL; 2464 struct mbuf *m1; 2465 enum ieee80211_edca_ac ac; 2466 uint32_t flags; 2467 uint16_t qos; 2468 u_int hdrlen; 2469 bus_dma_segment_t *seg; 2470 uint8_t *ivp, tid, ridx, txant, type; 2471 int i, totlen, hasqos, error, pad; 2472 2473 wh = mtod(m, struct ieee80211_frame *); 2474 hdrlen = ieee80211_get_hdrlen(wh); 2475 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2476 2477 /* Select EDCA Access Category and TX ring for this frame. */ 2478 if ((hasqos = ieee80211_has_qos(wh))) { 2479 qos = ieee80211_get_qos(wh); 2480 tid = qos & IEEE80211_QOS_TID; 2481 ac = ieee80211_up_to_ac(ic, tid); 2482 } else { 2483 tid = 0; 2484 ac = EDCA_AC_BE; 2485 } 2486 2487 ring = &sc->txq[ac]; 2488 desc = &ring->desc[ring->cur]; 2489 data = &ring->data[ring->cur]; 2490 2491 /* Choose a TX rate index. */ 2492 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2493 type != IEEE80211_FC0_TYPE_DATA) { 2494 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2495 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 2496 } else if (ic->ic_fixed_rate != -1) { 2497 ridx = sc->fixed_ridx; 2498 } else 2499 ridx = wn->ridx[ni->ni_txrate]; 2500 rinfo = &iwn_rates[ridx]; 2501 2502 #if NBPFILTER > 0 2503 if (sc->sc_drvbpf != NULL) { 2504 struct mbuf mb; 2505 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2506 2507 tap->wt_flags = 0; 2508 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 2509 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 2510 tap->wt_rate = rinfo->rate; 2511 tap->wt_hwqueue = ac; 2512 if ((ic->ic_flags & IEEE80211_F_WEPON) && 2513 (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)) 2514 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2515 2516 mb.m_data = (caddr_t)tap; 2517 mb.m_len = sc->sc_txtap_len; 2518 mb.m_next = m; 2519 mb.m_nextpkt = NULL; 2520 mb.m_type = 0; 2521 mb.m_flags = 0; 2522 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 2523 } 2524 #endif 2525 2526 totlen = m->m_pkthdr.len; 2527 2528 /* Encrypt the frame if need be. */ 2529 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2530 /* Retrieve key for TX. */ 2531 k = ieee80211_get_txkey(ic, wh, ni); 2532 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 2533 /* Do software encryption. */ 2534 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 2535 return ENOBUFS; 2536 /* 802.11 header may have moved. */ 2537 wh = mtod(m, struct ieee80211_frame *); 2538 totlen = m->m_pkthdr.len; 2539 2540 } else /* HW appends CCMP MIC. */ 2541 totlen += IEEE80211_CCMP_HDRLEN; 2542 } 2543 2544 /* Prepare TX firmware command. */ 2545 cmd = &ring->cmd[ring->cur]; 2546 cmd->code = IWN_CMD_TX_DATA; 2547 cmd->flags = 0; 2548 cmd->qid = ring->qid; 2549 cmd->idx = ring->cur; 2550 2551 tx = (struct iwn_cmd_data *)cmd->data; 2552 /* NB: No need to clear tx, all fields are reinitialized here. */ 2553 tx->scratch = 0; /* clear "scratch" area */ 2554 2555 flags = 0; 2556 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2557 /* Unicast frame, check if an ACK is expected. */ 2558 if (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 2559 IEEE80211_QOS_ACK_POLICY_NOACK) 2560 flags |= IWN_TX_NEED_ACK; 2561 } 2562 if ((wh->i_fc[0] & 2563 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2564 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2565 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2566 2567 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2568 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2569 2570 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2571 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2572 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2573 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 2574 flags |= IWN_TX_NEED_RTS; 2575 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2576 ridx >= IWN_RIDX_OFDM6) { 2577 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2578 flags |= IWN_TX_NEED_CTS; 2579 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2580 flags |= IWN_TX_NEED_RTS; 2581 } 2582 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2583 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2584 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2585 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2586 flags |= IWN_TX_NEED_PROTECTION; 2587 } else 2588 flags |= IWN_TX_FULL_TXOP; 2589 } 2590 } 2591 2592 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2593 type != IEEE80211_FC0_TYPE_DATA) 2594 tx->id = hal->broadcast_id; 2595 else 2596 tx->id = wn->id; 2597 2598 if (type == IEEE80211_FC0_TYPE_MGT) { 2599 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2600 2601 #ifndef IEEE80211_STA_ONLY 2602 /* Tell HW to set timestamp in probe responses. */ 2603 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2604 flags |= IWN_TX_INSERT_TSTAMP; 2605 #endif 2606 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 2607 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 2608 tx->timeout = htole16(3); 2609 else 2610 tx->timeout = htole16(2); 2611 } else 2612 tx->timeout = htole16(0); 2613 2614 if (hdrlen & 3) { 2615 /* First segment's length must be a multiple of 4. */ 2616 flags |= IWN_TX_NEED_PADDING; 2617 pad = 4 - (hdrlen & 3); 2618 } else 2619 pad = 0; 2620 2621 tx->len = htole16(totlen); 2622 tx->tid = tid; 2623 tx->rts_ntries = 60; 2624 tx->data_ntries = 15; 2625 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 2626 tx->plcp = rinfo->plcp; 2627 tx->rflags = rinfo->flags; 2628 if (tx->id == hal->broadcast_id) { 2629 /* Group or management frame. */ 2630 tx->linkq = 0; 2631 /* XXX Alternate between antenna A and B? */ 2632 txant = IWN_LSB(sc->txantmsk); 2633 tx->rflags |= IWN_RFLAG_ANT(txant); 2634 } else { 2635 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1; 2636 flags |= IWN_TX_LINKQ; /* enable MRR */ 2637 } 2638 /* Set physical address of "scratch area". */ 2639 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 2640 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 2641 2642 /* Copy 802.11 header in TX command. */ 2643 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 2644 2645 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 2646 /* Trim 802.11 header and prepend CCMP IV. */ 2647 m_adj(m, hdrlen - IEEE80211_CCMP_HDRLEN); 2648 ivp = mtod(m, uint8_t *); 2649 k->k_tsc++; 2650 ivp[0] = k->k_tsc; 2651 ivp[1] = k->k_tsc >> 8; 2652 ivp[2] = 0; 2653 ivp[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 2654 ivp[4] = k->k_tsc >> 16; 2655 ivp[5] = k->k_tsc >> 24; 2656 ivp[6] = k->k_tsc >> 32; 2657 ivp[7] = k->k_tsc >> 40; 2658 2659 tx->security = IWN_CIPHER_CCMP; 2660 /* XXX flags |= IWN_TX_AMPDU_CCMP; */ 2661 memcpy(tx->key, k->k_key, k->k_len); 2662 2663 /* TX scheduler includes CCMP MIC len w/5000 Series. */ 2664 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 2665 totlen += IEEE80211_CCMP_MICLEN; 2666 } else { 2667 /* Trim 802.11 header. */ 2668 m_adj(m, hdrlen); 2669 tx->security = 0; 2670 } 2671 tx->flags = htole32(flags); 2672 2673 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2674 BUS_DMA_NOWAIT); 2675 if (error != 0 && error != EFBIG) { 2676 printf("%s: can't map mbuf (error %d)\n", 2677 sc->sc_dev.dv_xname, error); 2678 m_freem(m); 2679 return error; 2680 } 2681 if (error != 0) { 2682 /* Too many DMA segments, linearize mbuf. */ 2683 MGETHDR(m1, M_DONTWAIT, MT_DATA); 2684 if (m1 == NULL) { 2685 m_freem(m); 2686 return ENOBUFS; 2687 } 2688 if (m->m_pkthdr.len > MHLEN) { 2689 MCLGET(m1, M_DONTWAIT); 2690 if (!(m1->m_flags & M_EXT)) { 2691 m_freem(m); 2692 m_freem(m1); 2693 return ENOBUFS; 2694 } 2695 } 2696 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, caddr_t)); 2697 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 2698 m_freem(m); 2699 m = m1; 2700 2701 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2702 BUS_DMA_NOWAIT); 2703 if (error != 0) { 2704 printf("%s: can't map mbuf (error %d)\n", 2705 sc->sc_dev.dv_xname, error); 2706 m_freem(m); 2707 return error; 2708 } 2709 } 2710 2711 data->m = m; 2712 data->ni = ni; 2713 2714 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 2715 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 2716 2717 /* Fill TX descriptor. */ 2718 desc->nsegs = 1 + data->map->dm_nsegs; 2719 /* First DMA segment is used by the TX command. */ 2720 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 2721 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 2722 (4 + sizeof (*tx) + hdrlen + pad) << 4); 2723 /* Other DMA segments are for data payload. */ 2724 seg = data->map->dm_segs; 2725 for (i = 1; i <= data->map->dm_nsegs; i++) { 2726 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 2727 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 2728 seg->ds_len << 4); 2729 seg++; 2730 } 2731 2732 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2733 BUS_DMASYNC_PREWRITE); 2734 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 2735 (caddr_t)cmd - ring->cmd_dma.vaddr, sizeof (*cmd), 2736 BUS_DMASYNC_PREWRITE); 2737 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2738 (caddr_t)desc - ring->desc_dma.vaddr, sizeof (*desc), 2739 BUS_DMASYNC_PREWRITE); 2740 2741 /* Update TX scheduler. */ 2742 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 2743 2744 /* Kick TX ring. */ 2745 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 2746 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 2747 2748 /* Mark TX ring as full if we reach a certain threshold. */ 2749 if (++ring->queued > IWN_TX_RING_HIMARK) 2750 sc->qfullmsk |= 1 << ring->qid; 2751 2752 return 0; 2753 } 2754 2755 void 2756 iwn_start(struct ifnet *ifp) 2757 { 2758 struct iwn_softc *sc = ifp->if_softc; 2759 struct ieee80211com *ic = &sc->sc_ic; 2760 struct ieee80211_node *ni; 2761 struct mbuf *m; 2762 2763 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2764 return; 2765 2766 for (;;) { 2767 if (sc->qfullmsk != 0) { 2768 ifp->if_flags |= IFF_OACTIVE; 2769 break; 2770 } 2771 /* Send pending management frames first. */ 2772 IF_DEQUEUE(&ic->ic_mgtq, m); 2773 if (m != NULL) { 2774 ni = (void *)m->m_pkthdr.rcvif; 2775 goto sendit; 2776 } 2777 if (ic->ic_state != IEEE80211_S_RUN) 2778 break; 2779 2780 /* Encapsulate and send data frames. */ 2781 IFQ_DEQUEUE(&ifp->if_snd, m); 2782 if (m == NULL) 2783 break; 2784 #if NBPFILTER > 0 2785 if (ifp->if_bpf != NULL) 2786 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 2787 #endif 2788 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 2789 continue; 2790 sendit: 2791 #if NBPFILTER > 0 2792 if (ic->ic_rawbpf != NULL) 2793 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 2794 #endif 2795 if (iwn_tx(sc, m, ni) != 0) { 2796 ieee80211_release_node(ic, ni); 2797 ifp->if_oerrors++; 2798 continue; 2799 } 2800 2801 sc->sc_tx_timer = 5; 2802 ifp->if_timer = 1; 2803 } 2804 } 2805 2806 void 2807 iwn_watchdog(struct ifnet *ifp) 2808 { 2809 struct iwn_softc *sc = ifp->if_softc; 2810 2811 ifp->if_timer = 0; 2812 2813 if (sc->sc_tx_timer > 0) { 2814 if (--sc->sc_tx_timer == 0) { 2815 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 2816 ifp->if_flags &= ~IFF_UP; 2817 iwn_stop(ifp, 1); 2818 ifp->if_oerrors++; 2819 return; 2820 } 2821 ifp->if_timer = 1; 2822 } 2823 2824 ieee80211_watchdog(ifp); 2825 } 2826 2827 int 2828 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2829 { 2830 struct iwn_softc *sc = ifp->if_softc; 2831 struct ieee80211com *ic = &sc->sc_ic; 2832 struct ifaddr *ifa; 2833 struct ifreq *ifr; 2834 int s, error = 0; 2835 2836 s = splnet(); 2837 2838 switch (cmd) { 2839 case SIOCSIFADDR: 2840 ifa = (struct ifaddr *)data; 2841 ifp->if_flags |= IFF_UP; 2842 #ifdef INET 2843 if (ifa->ifa_addr->sa_family == AF_INET) 2844 arp_ifinit(&ic->ic_ac, ifa); 2845 #endif 2846 /* FALLTHROUGH */ 2847 case SIOCSIFFLAGS: 2848 if (ifp->if_flags & IFF_UP) { 2849 if (!(ifp->if_flags & IFF_RUNNING)) 2850 error = iwn_init(ifp); 2851 } else { 2852 if (ifp->if_flags & IFF_RUNNING) 2853 iwn_stop(ifp, 1); 2854 } 2855 break; 2856 2857 case SIOCADDMULTI: 2858 case SIOCDELMULTI: 2859 ifr = (struct ifreq *)data; 2860 error = (cmd == SIOCADDMULTI) ? 2861 ether_addmulti(ifr, &ic->ic_ac) : 2862 ether_delmulti(ifr, &ic->ic_ac); 2863 2864 if (error == ENETRESET) 2865 error = 0; 2866 break; 2867 2868 case SIOCS80211POWER: 2869 error = ieee80211_ioctl(ifp, cmd, data); 2870 if (error != ENETRESET) 2871 break; 2872 if (ic->ic_state == IEEE80211_S_RUN && 2873 sc->calib.state == IWN_CALIB_STATE_RUN) { 2874 if (ic->ic_flags & IEEE80211_F_PMGTON) 2875 error = iwn_set_pslevel(sc, 0, 3, 0); 2876 else /* back to CAM */ 2877 error = iwn_set_pslevel(sc, 0, 0, 0); 2878 } else { 2879 /* Defer until transition to IWN_CALIB_STATE_RUN. */ 2880 error = 0; 2881 } 2882 break; 2883 2884 default: 2885 error = ieee80211_ioctl(ifp, cmd, data); 2886 } 2887 2888 if (error == ENETRESET) { 2889 error = 0; 2890 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2891 (IFF_UP | IFF_RUNNING)) { 2892 iwn_stop(ifp, 0); 2893 error = iwn_init(ifp); 2894 } 2895 } 2896 splx(s); 2897 return error; 2898 } 2899 2900 /* 2901 * Send a command to the firmware. 2902 */ 2903 int 2904 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 2905 { 2906 const struct iwn_hal *hal = sc->sc_hal; 2907 struct iwn_tx_ring *ring = &sc->txq[4]; 2908 struct iwn_tx_desc *desc; 2909 struct iwn_tx_data *data; 2910 struct iwn_tx_cmd *cmd; 2911 struct mbuf *m; 2912 bus_addr_t paddr; 2913 int totlen, error; 2914 2915 desc = &ring->desc[ring->cur]; 2916 data = &ring->data[ring->cur]; 2917 totlen = 4 + size; 2918 2919 if (size > sizeof cmd->data) { 2920 /* Command is too large to fit in a descriptor. */ 2921 if (totlen > MCLBYTES) 2922 return EINVAL; 2923 MGETHDR(m, M_DONTWAIT, MT_DATA); 2924 if (m == NULL) 2925 return ENOMEM; 2926 if (totlen > MHLEN) { 2927 MCLGET(m, M_DONTWAIT); 2928 if (!(m->m_flags & M_EXT)) { 2929 m_freem(m); 2930 return ENOMEM; 2931 } 2932 } 2933 cmd = mtod(m, struct iwn_tx_cmd *); 2934 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 2935 NULL, BUS_DMA_NOWAIT); 2936 if (error != 0) { 2937 m_freem(m); 2938 return error; 2939 } 2940 data->m = m; 2941 paddr = data->map->dm_segs[0].ds_addr; 2942 } else { 2943 cmd = &ring->cmd[ring->cur]; 2944 paddr = data->cmd_paddr; 2945 } 2946 2947 cmd->code = code; 2948 cmd->flags = 0; 2949 cmd->qid = ring->qid; 2950 cmd->idx = ring->cur; 2951 memcpy(cmd->data, buf, size); 2952 2953 desc->nsegs = 1; 2954 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 2955 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 2956 2957 if (size > sizeof cmd->data) { 2958 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 2959 BUS_DMASYNC_PREWRITE); 2960 } else { 2961 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 2962 (caddr_t)cmd - ring->cmd_dma.vaddr, totlen, 2963 BUS_DMASYNC_PREWRITE); 2964 } 2965 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2966 (caddr_t)desc - ring->desc_dma.vaddr, sizeof (*desc), 2967 BUS_DMASYNC_PREWRITE); 2968 2969 /* Update TX scheduler. */ 2970 hal->update_sched(sc, ring->qid, ring->cur, 0, 0); 2971 2972 /* Kick command ring. */ 2973 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 2974 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 2975 2976 return async ? 0 : tsleep(desc, PCATCH, "iwncmd", hz); 2977 } 2978 2979 int 2980 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 2981 { 2982 struct iwn4965_node_info hnode; 2983 caddr_t src, dst; 2984 2985 /* 2986 * We use the node structure for 5000 Series internally (it is 2987 * a superset of the one for 4965AGN). We thus copy the common 2988 * fields before sending the command. 2989 */ 2990 src = (caddr_t)node; 2991 dst = (caddr_t)&hnode; 2992 memcpy(dst, src, 48); 2993 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 2994 memcpy(dst + 48, src + 72, 20); 2995 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 2996 } 2997 2998 int 2999 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3000 { 3001 /* Direct mapping. */ 3002 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3003 } 3004 3005 int 3006 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3007 { 3008 struct iwn_node *wn = (void *)ni; 3009 struct ieee80211_rateset *rs = &ni->ni_rates; 3010 struct iwn_cmd_link_quality linkq; 3011 const struct iwn_rate *rinfo; 3012 uint8_t txant; 3013 int i, txrate; 3014 3015 /* Use the first valid TX antenna. */ 3016 txant = IWN_LSB(sc->txantmsk); 3017 3018 memset(&linkq, 0, sizeof linkq); 3019 linkq.id = wn->id; 3020 linkq.antmsk_1stream = txant; 3021 linkq.antmsk_2stream = IWN_ANT_A | IWN_ANT_B; 3022 linkq.ampdu_max = 64; 3023 linkq.ampdu_threshold = 3; 3024 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3025 3026 /* Start at highest available bit-rate. */ 3027 txrate = rs->rs_nrates - 1; 3028 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3029 rinfo = &iwn_rates[wn->ridx[txrate]]; 3030 linkq.retry[i].plcp = rinfo->plcp; 3031 linkq.retry[i].rflags = rinfo->flags; 3032 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3033 /* Next retry at immediate lower bit-rate. */ 3034 if (txrate > 0) 3035 txrate--; 3036 } 3037 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3038 } 3039 3040 /* 3041 * Broadcast node is used to send group-addressed and management frames. 3042 */ 3043 int 3044 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3045 { 3046 const struct iwn_hal *hal = sc->sc_hal; 3047 struct iwn_node_info node; 3048 struct iwn_cmd_link_quality linkq; 3049 const struct iwn_rate *rinfo; 3050 uint8_t txant; 3051 int i, error; 3052 3053 memset(&node, 0, sizeof node); 3054 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3055 node.id = hal->broadcast_id; 3056 DPRINTF(("adding broadcast node\n")); 3057 if ((error = hal->add_node(sc, &node, async)) != 0) 3058 return error; 3059 3060 /* Use the first valid TX antenna. */ 3061 txant = IWN_LSB(sc->txantmsk); 3062 3063 memset(&linkq, 0, sizeof linkq); 3064 linkq.id = hal->broadcast_id; 3065 linkq.antmsk_1stream = txant; 3066 linkq.antmsk_2stream = IWN_ANT_A | IWN_ANT_B; 3067 linkq.ampdu_max = 64; 3068 linkq.ampdu_threshold = 3; 3069 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3070 3071 /* Use lowest mandatory bit-rate. */ 3072 rinfo = (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) ? 3073 &iwn_rates[IWN_RIDX_CCK1] : &iwn_rates[IWN_RIDX_OFDM6]; 3074 linkq.retry[0].plcp = rinfo->plcp; 3075 linkq.retry[0].rflags = rinfo->flags; 3076 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3077 /* Use same bit-rate for all TX retries. */ 3078 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3079 linkq.retry[i].plcp = linkq.retry[0].plcp; 3080 linkq.retry[i].rflags = linkq.retry[0].rflags; 3081 } 3082 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3083 } 3084 3085 void 3086 iwn_updateedca(struct ieee80211com *ic) 3087 { 3088 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 3089 struct iwn_softc *sc = ic->ic_softc; 3090 struct iwn_edca_params cmd; 3091 int aci; 3092 3093 memset(&cmd, 0, sizeof cmd); 3094 cmd.flags = htole32(IWN_EDCA_UPDATE); 3095 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 3096 const struct ieee80211_edca_ac_params *ac = 3097 &ic->ic_edca_ac[aci]; 3098 cmd.ac[aci].aifsn = ac->ac_aifsn; 3099 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->ac_ecwmin)); 3100 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->ac_ecwmax)); 3101 cmd.ac[aci].txoplimit = 3102 htole16(IEEE80211_TXOP_TO_US(ac->ac_txoplimit)); 3103 } 3104 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 3105 #undef IWN_EXP2 3106 } 3107 3108 void 3109 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3110 { 3111 struct iwn_cmd_led led; 3112 3113 /* Clear microcode LED ownership. */ 3114 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3115 3116 led.which = which; 3117 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3118 led.off = off; 3119 led.on = on; 3120 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3121 } 3122 3123 /* 3124 * Set the critical temperature at which the firmware will notify us. 3125 */ 3126 int 3127 iwn_set_critical_temp(struct iwn_softc *sc) 3128 { 3129 struct iwn_critical_temp crit; 3130 3131 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3132 3133 memset(&crit, 0, sizeof crit); 3134 crit.tempR = htole32(sc->critical_temp); 3135 DPRINTF(("setting critical temperature to %u\n", sc->critical_temp)); 3136 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3137 } 3138 3139 int 3140 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3141 { 3142 struct iwn_cmd_timing cmd; 3143 uint64_t val, mod; 3144 3145 memset(&cmd, 0, sizeof cmd); 3146 memcpy(&cmd.tstamp, ni->ni_tstamp, sizeof (uint64_t)); 3147 cmd.bintval = htole16(ni->ni_intval); 3148 cmd.lintval = htole16(10); 3149 3150 /* Compute remaining time until next beacon. */ 3151 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3152 mod = letoh64(cmd.tstamp) % val; 3153 cmd.binitval = htole32((uint32_t)(val - mod)); 3154 3155 DPRINTF(("timing bintval=%u, tstamp=%llu, init=%u\n", 3156 ni->ni_intval, letoh64(cmd.tstamp), (uint32_t)(val - mod))); 3157 3158 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3159 } 3160 3161 void 3162 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3163 { 3164 /* Adjust TX power if need be (delta >= 3 degC.) */ 3165 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 3166 if (abs(temp - sc->temp) >= 3) { 3167 /* Record temperature of last calibration. */ 3168 sc->temp = temp; 3169 (void)iwn4965_set_txpower(sc, 1); 3170 } 3171 } 3172 3173 /* 3174 * Set TX power for current channel (each rate has its own power settings). 3175 * This function takes into account the regulatory information from EEPROM, 3176 * the current temperature and the current voltage. 3177 */ 3178 int 3179 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3180 { 3181 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3182 #define fdivround(a, b, n) \ 3183 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3184 /* Linear interpolation. */ 3185 #define interpolate(x, x1, y1, x2, y2, n) \ 3186 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3187 3188 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3189 struct ieee80211com *ic = &sc->sc_ic; 3190 struct iwn_ucode_info *uc = &sc->ucode_info; 3191 struct ieee80211_channel *ch; 3192 struct iwn4965_cmd_txpower cmd; 3193 struct iwn4965_eeprom_chan_samples *chans; 3194 const uint8_t *rf_gain, *dsp_gain; 3195 int32_t vdiff, tdiff; 3196 int i, c, grp, maxpwr; 3197 uint8_t chan; 3198 3199 /* Retrieve current channel from last RXON. */ 3200 chan = sc->rxon.chan; 3201 DPRINTF(("setting TX power for channel %d\n", chan)); 3202 ch = &ic->ic_channels[chan]; 3203 3204 memset(&cmd, 0, sizeof cmd); 3205 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3206 cmd.chan = chan; 3207 3208 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3209 maxpwr = sc->maxpwr5GHz; 3210 rf_gain = iwn4965_rf_gain_5ghz; 3211 dsp_gain = iwn4965_dsp_gain_5ghz; 3212 } else { 3213 maxpwr = sc->maxpwr2GHz; 3214 rf_gain = iwn4965_rf_gain_2ghz; 3215 dsp_gain = iwn4965_dsp_gain_2ghz; 3216 } 3217 3218 /* Compute voltage compensation. */ 3219 vdiff = ((int32_t)letoh32(uc->volt) - sc->eeprom_voltage) / 7; 3220 if (vdiff > 0) 3221 vdiff *= 2; 3222 if (abs(vdiff) > 2) 3223 vdiff = 0; 3224 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3225 vdiff, letoh32(uc->volt), sc->eeprom_voltage)); 3226 3227 /* Get channel's attenuation group. */ 3228 if (chan <= 20) /* 1-20 */ 3229 grp = 4; 3230 else if (chan <= 43) /* 34-43 */ 3231 grp = 0; 3232 else if (chan <= 70) /* 44-70 */ 3233 grp = 1; 3234 else if (chan <= 124) /* 71-124 */ 3235 grp = 2; 3236 else /* 125-200 */ 3237 grp = 3; 3238 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 3239 3240 /* Get channel's sub-band. */ 3241 for (i = 0; i < IWN_NBANDS; i++) 3242 if (sc->bands[i].lo != 0 && 3243 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3244 break; 3245 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3246 return EINVAL; 3247 chans = sc->bands[i].chans; 3248 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 3249 3250 for (c = 0; c < 2; c++) { 3251 uint8_t power, gain, temp; 3252 int maxchpwr, pwr, ridx, idx; 3253 3254 power = interpolate(chan, 3255 chans[0].num, chans[0].samples[c][1].power, 3256 chans[1].num, chans[1].samples[c][1].power, 1); 3257 gain = interpolate(chan, 3258 chans[0].num, chans[0].samples[c][1].gain, 3259 chans[1].num, chans[1].samples[c][1].gain, 1); 3260 temp = interpolate(chan, 3261 chans[0].num, chans[0].samples[c][1].temp, 3262 chans[1].num, chans[1].samples[c][1].temp, 1); 3263 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 3264 c, power, gain, temp)); 3265 3266 /* Compute temperature compensation. */ 3267 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3268 DPRINTF(("temperature compensation=%d (current=%d, " 3269 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 3270 3271 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3272 maxchpwr = sc->maxpwr[chan] * 2; 3273 if ((ridx / 8) & 1) 3274 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3275 3276 pwr = maxpwr; 3277 3278 /* Adjust TX power based on rate. */ 3279 if ((ridx % 8) == 5) 3280 pwr -= 15; /* OFDM48: -7.5dB */ 3281 else if ((ridx % 8) == 6) 3282 pwr -= 17; /* OFDM54: -8.5dB */ 3283 else if ((ridx % 8) == 7) 3284 pwr -= 20; /* OFDM60: -10dB */ 3285 else 3286 pwr -= 10; /* Others: -5dB */ 3287 3288 /* Do not exceed channel's max TX power. */ 3289 if (pwr > maxchpwr) 3290 pwr = maxchpwr; 3291 3292 idx = gain - (pwr - power) - tdiff - vdiff; 3293 if ((ridx / 8) & 1) /* MIMO */ 3294 idx += (int32_t)letoh32(uc->atten[grp][c]); 3295 3296 if (cmd.band == 0) 3297 idx += 9; /* 5GHz */ 3298 if (ridx == IWN_RIDX_MAX) 3299 idx += 5; /* CCK */ 3300 3301 /* Make sure idx stays in a valid range. */ 3302 if (idx < 0) 3303 idx = 0; 3304 else if (idx > IWN4965_MAX_PWR_INDEX) 3305 idx = IWN4965_MAX_PWR_INDEX; 3306 3307 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 3308 c, ridx, idx)); 3309 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3310 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3311 } 3312 } 3313 3314 DPRINTF(("setting TX power for chan %d\n", chan)); 3315 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3316 3317 #undef interpolate 3318 #undef fdivround 3319 } 3320 3321 int 3322 iwn5000_set_txpower(struct iwn_softc *sc, int async) 3323 { 3324 struct iwn5000_cmd_txpower cmd; 3325 3326 /* 3327 * TX power calibration is handled automatically by the firmware 3328 * for 5000 Series. 3329 */ 3330 memset(&cmd, 0, sizeof cmd); 3331 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3332 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3333 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3334 DPRINTF(("setting TX power\n")); 3335 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3336 } 3337 3338 /* 3339 * Retrieve the maximum RSSI (in dBm) among receivers. 3340 */ 3341 int 3342 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 3343 { 3344 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 3345 uint8_t mask, agc; 3346 int rssi; 3347 3348 mask = (letoh16(phy->antenna) >> 4) & 0x7; 3349 agc = (letoh16(phy->agc) >> 7) & 0x7f; 3350 3351 rssi = 0; 3352 if (mask & IWN_ANT_A) 3353 rssi = MAX(rssi, phy->rssi[0]); 3354 if (mask & IWN_ANT_B) 3355 rssi = MAX(rssi, phy->rssi[2]); 3356 if (mask & IWN_ANT_C) 3357 rssi = MAX(rssi, phy->rssi[4]); 3358 3359 return rssi - agc - IWN_RSSI_TO_DBM; 3360 } 3361 3362 int 3363 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 3364 { 3365 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 3366 uint8_t agc; 3367 int rssi; 3368 3369 agc = (letoh32(phy->agc) >> 9) & 0x7f; 3370 3371 rssi = MAX(letoh16(phy->rssi[0]) & 0xff, 3372 letoh16(phy->rssi[1]) & 0xff); 3373 rssi = MAX(letoh16(phy->rssi[2]) & 0xff, rssi); 3374 3375 return rssi - agc - IWN_RSSI_TO_DBM; 3376 } 3377 3378 /* 3379 * Retrieve the average noise (in dBm) among receivers. 3380 */ 3381 int 3382 iwn_get_noise(const struct iwn_rx_general_stats *stats) 3383 { 3384 int i, total, nbant, noise; 3385 3386 total = nbant = 0; 3387 for (i = 0; i < 3; i++) { 3388 if ((noise = letoh32(stats->noise[i]) & 0xff) == 0) 3389 continue; 3390 total += noise; 3391 nbant++; 3392 } 3393 /* There should be at least one antenna but check anyway. */ 3394 return (nbant == 0) ? -127 : (total / nbant) - 107; 3395 } 3396 3397 /* 3398 * Compute temperature (in degC) from last received statistics. 3399 */ 3400 int 3401 iwn4965_get_temperature(struct iwn_softc *sc) 3402 { 3403 struct iwn_ucode_info *uc = &sc->ucode_info; 3404 int32_t r1, r2, r3, r4, temp; 3405 3406 r1 = letoh32(uc->temp[0].chan20MHz); 3407 r2 = letoh32(uc->temp[1].chan20MHz); 3408 r3 = letoh32(uc->temp[2].chan20MHz); 3409 r4 = letoh32(sc->rawtemp); 3410 3411 if (r1 == r3) /* Prevents division by 0 (should not happen.) */ 3412 return 0; 3413 3414 /* Sign-extend 23-bit R4 value to 32-bit. */ 3415 r4 = (r4 << 8) >> 8; 3416 /* Compute temperature in Kelvin. */ 3417 temp = (259 * (r4 - r2)) / (r3 - r1); 3418 temp = (temp * 97) / 100 + 8; 3419 3420 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 3421 return IWN_KTOC(temp); 3422 } 3423 3424 int 3425 iwn5000_get_temperature(struct iwn_softc *sc) 3426 { 3427 /* 3428 * Temperature is not used by the driver for 5000 Series because 3429 * TX power calibration is handled by firmware. We export it to 3430 * users through the sensor framework though. 3431 */ 3432 return letoh32(sc->rawtemp); 3433 } 3434 3435 /* 3436 * Initialize sensitivity calibration state machine. 3437 */ 3438 int 3439 iwn_init_sensitivity(struct iwn_softc *sc) 3440 { 3441 const struct iwn_hal *hal = sc->sc_hal; 3442 struct iwn_calib_state *calib = &sc->calib; 3443 uint32_t flags; 3444 int error; 3445 3446 /* Reset calibration state machine. */ 3447 memset(calib, 0, sizeof (*calib)); 3448 calib->state = IWN_CALIB_STATE_INIT; 3449 calib->cck_state = IWN_CCK_STATE_HIFA; 3450 /* Set initial correlation values. */ 3451 calib->ofdm_x1 = hal->limits->min_ofdm_x1; 3452 calib->ofdm_mrc_x1 = hal->limits->min_ofdm_mrc_x1; 3453 calib->ofdm_x4 = 90; 3454 calib->ofdm_mrc_x4 = hal->limits->min_ofdm_mrc_x4; 3455 calib->cck_x4 = 125; 3456 calib->cck_mrc_x4 = hal->limits->min_cck_mrc_x4; 3457 calib->energy_cck = hal->limits->energy_cck; 3458 3459 /* Write initial sensitivity. */ 3460 if ((error = iwn_send_sensitivity(sc)) != 0) 3461 return error; 3462 3463 /* Write initial gains. */ 3464 if ((error = hal->init_gains(sc)) != 0) 3465 return error; 3466 3467 /* Request statistics at each beacon interval. */ 3468 flags = 0; 3469 DPRINTF(("sending request for statistics\n")); 3470 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 3471 } 3472 3473 /* 3474 * Collect noise and RSSI statistics for the first 20 beacons received 3475 * after association and use them to determine connected antennas and 3476 * to set differential gains. 3477 */ 3478 void 3479 iwn_collect_noise(struct iwn_softc *sc, 3480 const struct iwn_rx_general_stats *stats) 3481 { 3482 const struct iwn_hal *hal = sc->sc_hal; 3483 struct iwn_calib_state *calib = &sc->calib; 3484 uint32_t val; 3485 int i; 3486 3487 /* Accumulate RSSI and noise for all 3 antennas. */ 3488 for (i = 0; i < 3; i++) { 3489 calib->rssi[i] += letoh32(stats->rssi[i]) & 0xff; 3490 calib->noise[i] += letoh32(stats->noise[i]) & 0xff; 3491 } 3492 /* NB: We update differential gains only once after 20 beacons. */ 3493 if (++calib->nbeacons < 20) 3494 return; 3495 3496 /* Determine highest average RSSI. */ 3497 val = MAX(calib->rssi[0], calib->rssi[1]); 3498 val = MAX(calib->rssi[2], val); 3499 3500 /* Determine which antennas are connected. */ 3501 sc->antmsk = 0; 3502 for (i = 0; i < 3; i++) 3503 if (val - calib->rssi[i] <= 15 * 20) 3504 sc->antmsk |= 1 << i; 3505 /* If none of the TX antennas are connected, keep at least one. */ 3506 if ((sc->antmsk & sc->txantmsk) == 0) 3507 sc->antmsk |= IWN_LSB(sc->txantmsk); 3508 3509 (void)hal->set_gains(sc); 3510 calib->state = IWN_CALIB_STATE_RUN; 3511 3512 #ifdef notyet 3513 /* XXX Disable RX chains with no antennas connected. */ 3514 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->antmsk)); 3515 (void)iwn_cmd(sc, IWN_CMD_CONFIGURE, &sc->rxon, hal->rxonsz, 1); 3516 #endif 3517 3518 /* Enable power-saving mode if requested by user. */ 3519 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 3520 (void)iwn_set_pslevel(sc, 0, 3, 1); 3521 } 3522 3523 int 3524 iwn4965_init_gains(struct iwn_softc *sc) 3525 { 3526 struct iwn_phy_calib_gain cmd; 3527 3528 memset(&cmd, 0, sizeof cmd); 3529 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3530 /* Differential gains initially set to 0 for all 3 antennas. */ 3531 DPRINTF(("setting initial differential gains\n")); 3532 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3533 } 3534 3535 int 3536 iwn5000_init_gains(struct iwn_softc *sc) 3537 { 3538 struct iwn_phy_calib cmd; 3539 3540 if (sc->hw_type == IWN_HW_REV_TYPE_6000 || 3541 sc->hw_type == IWN_HW_REV_TYPE_6050) 3542 return 0; 3543 3544 memset(&cmd, 0, sizeof cmd); 3545 cmd.code = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 3546 cmd.ngroups = 1; 3547 cmd.isvalid = 1; 3548 DPRINTF(("setting initial differential gains\n")); 3549 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3550 } 3551 3552 int 3553 iwn4965_set_gains(struct iwn_softc *sc) 3554 { 3555 struct iwn_calib_state *calib = &sc->calib; 3556 struct iwn_phy_calib_gain cmd; 3557 int i, delta, noise; 3558 3559 /* Get minimal noise among connected antennas. */ 3560 noise = INT_MAX; /* NB: There's at least one antenna. */ 3561 for (i = 0; i < 3; i++) 3562 if (sc->antmsk & (1 << i)) 3563 noise = MIN(calib->noise[i], noise); 3564 3565 memset(&cmd, 0, sizeof cmd); 3566 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3567 /* Set differential gains for connected antennas. */ 3568 for (i = 0; i < 3; i++) { 3569 if (sc->antmsk & (1 << i)) { 3570 /* Compute attenuation (in unit of 1.5dB). */ 3571 delta = (noise - (int32_t)calib->noise[i]) / 30; 3572 /* NB: delta <= 0 */ 3573 /* Limit to [-4.5dB,0]. */ 3574 cmd.gain[i] = MIN(abs(delta), 3); 3575 if (delta < 0) 3576 cmd.gain[i] |= 1 << 2; /* sign bit */ 3577 } 3578 } 3579 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 3580 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->antmsk)); 3581 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3582 } 3583 3584 int 3585 iwn5000_set_gains(struct iwn_softc *sc) 3586 { 3587 struct iwn_calib_state *calib = &sc->calib; 3588 struct iwn_phy_calib_gain cmd; 3589 int i, delta; 3590 3591 if (sc->hw_type == IWN_HW_REV_TYPE_6000 || 3592 sc->hw_type == IWN_HW_REV_TYPE_6050) 3593 return 0; 3594 3595 memset(&cmd, 0, sizeof cmd); 3596 cmd.code = IWN5000_PHY_CALIB_NOISE_GAIN; 3597 cmd.ngroups = 1; 3598 cmd.isvalid = 1; 3599 /* Set differential gains for antennas B and C. */ 3600 for (i = 1; i < 3; i++) { 3601 if (sc->antmsk & (1 << i)) { 3602 /* The delta is relative to antenna A. */ 3603 delta = ((int32_t)calib->noise[0] - 3604 (int32_t)calib->noise[i]) / 30; 3605 /* Limit to [-4.5dB,+4.5dB]. */ 3606 cmd.gain[i - 1] = MIN(abs(delta), 3); 3607 if (delta < 0) 3608 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 3609 } 3610 } 3611 DPRINTF(("setting differential gains Ant B/C: %x/%x (%x)\n", 3612 cmd.gain[0], cmd.gain[1], sc->antmsk)); 3613 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3614 } 3615 3616 /* 3617 * Tune RF RX sensitivity based on the number of false alarms detected 3618 * during the last beacon period. 3619 */ 3620 void 3621 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 3622 { 3623 #define inc(val, inc, max) \ 3624 if ((val) < (max)) { \ 3625 if ((val) < (max) - (inc)) \ 3626 (val) += (inc); \ 3627 else \ 3628 (val) = (max); \ 3629 needs_update = 1; \ 3630 } 3631 #define dec(val, dec, min) \ 3632 if ((val) > (min)) { \ 3633 if ((val) > (min) + (dec)) \ 3634 (val) -= (dec); \ 3635 else \ 3636 (val) = (min); \ 3637 needs_update = 1; \ 3638 } 3639 3640 const struct iwn_hal *hal = sc->sc_hal; 3641 const struct iwn_sensitivity_limits *limits = hal->limits; 3642 struct iwn_calib_state *calib = &sc->calib; 3643 uint32_t val, rxena, fa; 3644 uint32_t energy[3], energy_min; 3645 uint8_t noise[3], noise_ref; 3646 int i, needs_update = 0; 3647 3648 /* Check that we've been enabled long enough. */ 3649 if ((rxena = letoh32(stats->general.load)) == 0) 3650 return; 3651 3652 /* Compute number of false alarms since last call for OFDM. */ 3653 fa = letoh32(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 3654 fa += letoh32(stats->ofdm.fa) - calib->fa_ofdm; 3655 fa *= 200 * 1024; /* 200TU */ 3656 3657 /* Save counters values for next call. */ 3658 calib->bad_plcp_ofdm = letoh32(stats->ofdm.bad_plcp); 3659 calib->fa_ofdm = letoh32(stats->ofdm.fa); 3660 3661 if (fa > 50 * rxena) { 3662 /* High false alarm count, decrease sensitivity. */ 3663 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 3664 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 3665 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 3666 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 3667 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 3668 3669 } else if (fa < 5 * rxena) { 3670 /* Low false alarm count, increase sensitivity. */ 3671 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 3672 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 3673 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 3674 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 3675 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 3676 } 3677 3678 /* Compute maximum noise among 3 receivers. */ 3679 for (i = 0; i < 3; i++) 3680 noise[i] = (letoh32(stats->general.noise[i]) >> 8) & 0xff; 3681 val = MAX(noise[0], noise[1]); 3682 val = MAX(noise[2], val); 3683 /* Insert it into our samples table. */ 3684 calib->noise_samples[calib->cur_noise_sample] = val; 3685 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 3686 3687 /* Compute maximum noise among last 20 samples. */ 3688 noise_ref = calib->noise_samples[0]; 3689 for (i = 1; i < 20; i++) 3690 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 3691 3692 /* Compute maximum energy among 3 receivers. */ 3693 for (i = 0; i < 3; i++) 3694 energy[i] = letoh32(stats->general.energy[i]); 3695 val = MIN(energy[0], energy[1]); 3696 val = MIN(energy[2], val); 3697 /* Insert it into our samples table. */ 3698 calib->energy_samples[calib->cur_energy_sample] = val; 3699 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 3700 3701 /* Compute minimum energy among last 10 samples. */ 3702 energy_min = calib->energy_samples[0]; 3703 for (i = 1; i < 10; i++) 3704 energy_min = MAX(energy_min, calib->energy_samples[i]); 3705 energy_min += 6; 3706 3707 /* Compute number of false alarms since last call for CCK. */ 3708 fa = letoh32(stats->cck.bad_plcp) - calib->bad_plcp_cck; 3709 fa += letoh32(stats->cck.fa) - calib->fa_cck; 3710 fa *= 200 * 1024; /* 200TU */ 3711 3712 /* Save counters values for next call. */ 3713 calib->bad_plcp_cck = letoh32(stats->cck.bad_plcp); 3714 calib->fa_cck = letoh32(stats->cck.fa); 3715 3716 if (fa > 50 * rxena) { 3717 /* High false alarm count, decrease sensitivity. */ 3718 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 3719 calib->cck_state = IWN_CCK_STATE_HIFA; 3720 calib->low_fa = 0; 3721 3722 if (calib->cck_x4 > 160) { 3723 calib->noise_ref = noise_ref; 3724 if (calib->energy_cck > 2) 3725 dec(calib->energy_cck, 2, energy_min); 3726 } 3727 if (calib->cck_x4 < 160) { 3728 calib->cck_x4 = 161; 3729 needs_update = 1; 3730 } else 3731 inc(calib->cck_x4, 3, limits->max_cck_x4); 3732 3733 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 3734 3735 } else if (fa < 5 * rxena) { 3736 /* Low false alarm count, increase sensitivity. */ 3737 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 3738 calib->cck_state = IWN_CCK_STATE_LOFA; 3739 calib->low_fa++; 3740 3741 if (calib->cck_state != IWN_CCK_STATE_INIT && 3742 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 3743 calib->low_fa > 100)) { 3744 inc(calib->energy_cck, 2, limits->min_energy_cck); 3745 dec(calib->cck_x4, 3, limits->min_cck_x4); 3746 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 3747 } 3748 } else { 3749 /* Not worth to increase or decrease sensitivity. */ 3750 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 3751 calib->low_fa = 0; 3752 calib->noise_ref = noise_ref; 3753 3754 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 3755 /* Previous interval had many false alarms. */ 3756 dec(calib->energy_cck, 8, energy_min); 3757 } 3758 calib->cck_state = IWN_CCK_STATE_INIT; 3759 } 3760 3761 if (needs_update) 3762 (void)iwn_send_sensitivity(sc); 3763 #undef dec 3764 #undef inc 3765 } 3766 3767 int 3768 iwn_send_sensitivity(struct iwn_softc *sc) 3769 { 3770 const struct iwn_hal *hal = sc->sc_hal; 3771 struct iwn_calib_state *calib = &sc->calib; 3772 struct iwn_sensitivity_cmd cmd; 3773 3774 memset(&cmd, 0, sizeof cmd); 3775 cmd.which = IWN_SENSITIVITY_WORKTBL; 3776 /* OFDM modulation. */ 3777 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 3778 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 3779 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 3780 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 3781 cmd.energy_ofdm = htole16(hal->limits->energy_ofdm); 3782 cmd.energy_ofdm_th = htole16(62); 3783 /* CCK modulation. */ 3784 cmd.corr_cck_x4 = htole16(calib->cck_x4); 3785 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 3786 cmd.energy_cck = htole16(calib->energy_cck); 3787 /* Barker modulation: use default values. */ 3788 cmd.corr_barker = htole16(190); 3789 cmd.corr_barker_mrc = htole16(390); 3790 3791 DPRINTFN(2, ("setting sensitivity %d/%d/%d/%d/%d/%d/%d\n", 3792 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 3793 calib->ofdm_mrc_x4, calib->cck_x4, calib->cck_mrc_x4, 3794 calib->energy_cck)); 3795 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, sizeof cmd, 1); 3796 } 3797 3798 /* 3799 * Set STA mode power saving level (between 0 and 5). 3800 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 3801 */ 3802 int 3803 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 3804 { 3805 struct iwn_pmgt_cmd cmd; 3806 const struct iwn_pmgt *pmgt; 3807 uint32_t max, skip_dtim; 3808 pcireg_t reg; 3809 int i; 3810 3811 /* Select which PS parameters to use. */ 3812 if (dtim <= 2) 3813 pmgt = &iwn_pmgt[0][level]; 3814 else if (dtim <= 10) 3815 pmgt = &iwn_pmgt[1][level]; 3816 else 3817 pmgt = &iwn_pmgt[2][level]; 3818 3819 memset(&cmd, 0, sizeof cmd); 3820 if (level != 0) /* not CAM */ 3821 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 3822 if (level == 5) 3823 cmd.flags |= htole16(IWN_PS_FAST_PD); 3824 /* Retrieve PCIe Active State Power Management (ASPM). */ 3825 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 3826 sc->sc_cap_off + PCI_PCIE_LCSR); 3827 if (!(reg & PCI_PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 3828 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 3829 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 3830 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 3831 3832 if (dtim == 0) { 3833 dtim = 1; 3834 skip_dtim = 0; 3835 } else 3836 skip_dtim = pmgt->skip_dtim; 3837 if (skip_dtim != 0) { 3838 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 3839 max = pmgt->intval[4]; 3840 if (max == (uint32_t)-1) 3841 max = dtim * (skip_dtim + 1); 3842 else if (max > dtim) 3843 max = (max / dtim) * dtim; 3844 } else 3845 max = dtim; 3846 for (i = 0; i < 5; i++) 3847 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 3848 3849 DPRINTF(("setting power saving level to %d\n", level)); 3850 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 3851 } 3852 3853 int 3854 iwn_config(struct iwn_softc *sc) 3855 { 3856 const struct iwn_hal *hal = sc->sc_hal; 3857 struct ieee80211com *ic = &sc->sc_ic; 3858 struct ifnet *ifp = &ic->ic_if; 3859 struct iwn_bluetooth bluetooth; 3860 uint16_t rxchain; 3861 int error; 3862 3863 /* Set power saving level to CAM during initialization. */ 3864 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 3865 printf("%s: could not set power saving level\n", 3866 sc->sc_dev.dv_xname); 3867 return error; 3868 } 3869 3870 /* Configure bluetooth coexistence. */ 3871 memset(&bluetooth, 0, sizeof bluetooth); 3872 bluetooth.flags = 3; 3873 bluetooth.lead = 0xaa; 3874 bluetooth.kill = 1; 3875 DPRINTF(("configuring bluetooth coexistence\n")); 3876 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 3877 if (error != 0) { 3878 printf("%s: could not configure bluetooth coexistence\n", 3879 sc->sc_dev.dv_xname); 3880 return error; 3881 } 3882 3883 /* Configure adapter. */ 3884 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 3885 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 3886 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 3887 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 3888 /* Set default channel. */ 3889 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 3890 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 3891 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) 3892 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 3893 switch (ic->ic_opmode) { 3894 case IEEE80211_M_STA: 3895 sc->rxon.mode = IWN_MODE_STA; 3896 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 3897 break; 3898 case IEEE80211_M_MONITOR: 3899 sc->rxon.mode = IWN_MODE_MONITOR; 3900 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 3901 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 3902 break; 3903 default: 3904 /* Should not get there. */ 3905 break; 3906 } 3907 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 3908 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 3909 sc->rxon.ht_single_mask = 0xff; 3910 sc->rxon.ht_dual_mask = 0xff; 3911 rxchain = IWN_RXCHAIN_VALID(IWN_ANT_ABC) | IWN_RXCHAIN_IDLE_COUNT(2) | 3912 IWN_RXCHAIN_MIMO_COUNT(2); 3913 sc->rxon.rxchain = htole16(rxchain); 3914 DPRINTF(("setting configuration\n")); 3915 error = iwn_cmd(sc, IWN_CMD_CONFIGURE, &sc->rxon, hal->rxonsz, 0); 3916 if (error != 0) { 3917 printf("%s: configure command failed\n", sc->sc_dev.dv_xname); 3918 return error; 3919 } 3920 3921 /* Configuration has changed, set TX power accordingly. */ 3922 if ((error = hal->set_txpower(sc, 0)) != 0) { 3923 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 3924 return error; 3925 } 3926 3927 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 3928 printf("%s: could not add broadcast node\n", 3929 sc->sc_dev.dv_xname); 3930 return error; 3931 } 3932 3933 if ((error = iwn_set_critical_temp(sc)) != 0) { 3934 printf("%s: could not set critical temperature\n", 3935 sc->sc_dev.dv_xname); 3936 return error; 3937 } 3938 return 0; 3939 } 3940 3941 int 3942 iwn_scan(struct iwn_softc *sc, uint16_t flags) 3943 { 3944 struct ieee80211com *ic = &sc->sc_ic; 3945 struct iwn_scan_hdr *hdr; 3946 struct iwn_cmd_data *tx; 3947 struct iwn_scan_essid *essid; 3948 struct iwn_scan_chan *chan; 3949 struct ieee80211_frame *wh; 3950 struct ieee80211_rateset *rs; 3951 struct ieee80211_channel *c; 3952 uint8_t *buf, *frm; 3953 uint16_t rxchain; 3954 uint8_t txant; 3955 int buflen, error; 3956 3957 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 3958 if (buf == NULL) { 3959 printf("%s: could not allocate buffer for scan command\n", 3960 sc->sc_dev.dv_xname); 3961 return ENOMEM; 3962 } 3963 hdr = (struct iwn_scan_hdr *)buf; 3964 /* 3965 * Move to the next channel if no frames are received within 10ms 3966 * after sending the probe request. 3967 */ 3968 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 3969 hdr->quiet_threshold = htole16(1); /* min # of packets */ 3970 3971 /* Select antennas for scanning. */ 3972 rxchain = IWN_RXCHAIN_FORCE | IWN_RXCHAIN_VALID(IWN_ANT_ABC) | 3973 IWN_RXCHAIN_MIMO(IWN_ANT_ABC); 3974 if ((flags & IEEE80211_CHAN_5GHZ) && 3975 sc->hw_type == IWN_HW_REV_TYPE_4965) { 3976 /* Ant A must be avoided in 5GHz because of an HW bug. */ 3977 rxchain |= IWN_RXCHAIN_SEL(IWN_ANT_B | IWN_ANT_C); 3978 } else /* Use all available RX antennas. */ 3979 rxchain |= IWN_RXCHAIN_SEL(IWN_ANT_ABC); 3980 hdr->rxchain = htole16(rxchain); 3981 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 3982 3983 tx = (struct iwn_cmd_data *)(hdr + 1); 3984 tx->flags = htole32(IWN_TX_AUTO_SEQ); 3985 tx->id = sc->sc_hal->broadcast_id; 3986 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3987 3988 if (flags & IEEE80211_CHAN_5GHZ) { 3989 hdr->crc_threshold = htole16(1); 3990 /* Send probe requests at 6Mbps. */ 3991 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 3992 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 3993 } else { 3994 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 3995 /* Send probe requests at 1Mbps. */ 3996 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 3997 tx->rflags = IWN_RFLAG_CCK; 3998 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 3999 } 4000 /* Use the first valid TX antenna. */ 4001 txant = IWN_LSB(sc->txantmsk); 4002 tx->rflags |= IWN_RFLAG_ANT(txant); 4003 4004 essid = (struct iwn_scan_essid *)(tx + 1); 4005 if (ic->ic_des_esslen != 0) { 4006 essid[0].id = IEEE80211_ELEMID_SSID; 4007 essid[0].len = ic->ic_des_esslen; 4008 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 4009 } 4010 /* 4011 * Build a probe request frame. Most of the following code is a 4012 * copy & paste of what is done in net80211. 4013 */ 4014 wh = (struct ieee80211_frame *)(essid + 20); 4015 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4016 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4017 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4018 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 4019 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 4020 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 4021 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4022 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4023 4024 frm = (uint8_t *)(wh + 1); 4025 frm = ieee80211_add_ssid(frm, NULL, 0); 4026 frm = ieee80211_add_rates(frm, rs); 4027 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 4028 frm = ieee80211_add_xrates(frm, rs); 4029 4030 /* Set length of probe request. */ 4031 tx->len = htole16(frm - (uint8_t *)wh); 4032 4033 chan = (struct iwn_scan_chan *)frm; 4034 for (c = &ic->ic_channels[1]; 4035 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 4036 if ((c->ic_flags & flags) != flags) 4037 continue; 4038 4039 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4040 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 4041 chan->flags = 0; 4042 if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) 4043 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4044 if (ic->ic_des_esslen != 0) 4045 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4046 chan->dsp_gain = 0x6e; 4047 if (IEEE80211_IS_CHAN_5GHZ(c)) { 4048 chan->rf_gain = 0x3b; 4049 chan->active = htole16(24); 4050 chan->passive = htole16(110); 4051 } else { 4052 chan->rf_gain = 0x28; 4053 chan->active = htole16(36); 4054 chan->passive = htole16(120); 4055 } 4056 hdr->nchan++; 4057 chan++; 4058 } 4059 4060 buflen = (uint8_t *)chan - buf; 4061 hdr->len = htole16(buflen); 4062 4063 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan)); 4064 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4065 free(buf, M_DEVBUF); 4066 return error; 4067 } 4068 4069 int 4070 iwn_auth(struct iwn_softc *sc) 4071 { 4072 const struct iwn_hal *hal = sc->sc_hal; 4073 struct ieee80211com *ic = &sc->sc_ic; 4074 struct ieee80211_node *ni = ic->ic_bss; 4075 int error; 4076 4077 /* Update adapter's configuration. */ 4078 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4079 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 4080 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4081 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4082 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4083 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4084 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4085 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4086 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4087 switch (ic->ic_curmode) { 4088 case IEEE80211_MODE_11A: 4089 sc->rxon.cck_mask = 0; 4090 sc->rxon.ofdm_mask = 0x15; 4091 break; 4092 case IEEE80211_MODE_11B: 4093 sc->rxon.cck_mask = 0x03; 4094 sc->rxon.ofdm_mask = 0; 4095 break; 4096 default: /* Assume 802.11b/g. */ 4097 sc->rxon.cck_mask = 0x0f; 4098 sc->rxon.ofdm_mask = 0x15; 4099 } 4100 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4101 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4102 error = iwn_cmd(sc, IWN_CMD_CONFIGURE, &sc->rxon, hal->rxonsz, 1); 4103 if (error != 0) { 4104 printf("%s: could not configure\n", sc->sc_dev.dv_xname); 4105 return error; 4106 } 4107 4108 /* Configuration has changed, set TX power accordingly. */ 4109 if ((error = hal->set_txpower(sc, 1)) != 0) { 4110 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 4111 return error; 4112 } 4113 /* 4114 * Reconfiguring RXON clears the firmware's nodes table so we must 4115 * add the broadcast node again. 4116 */ 4117 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 4118 printf("%s: could not add broadcast node\n", 4119 sc->sc_dev.dv_xname); 4120 return error; 4121 } 4122 return 0; 4123 } 4124 4125 int 4126 iwn_run(struct iwn_softc *sc) 4127 { 4128 const struct iwn_hal *hal = sc->sc_hal; 4129 struct ieee80211com *ic = &sc->sc_ic; 4130 struct ieee80211_node *ni = ic->ic_bss; 4131 struct iwn_node_info node; 4132 int error; 4133 4134 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4135 /* Link LED blinks while monitoring. */ 4136 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4137 return 0; 4138 } 4139 if ((error = iwn_set_timing(sc, ni)) != 0) { 4140 printf("%s: could not set timing\n", sc->sc_dev.dv_xname); 4141 return error; 4142 } 4143 4144 /* Update adapter's configuration. */ 4145 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4146 /* Short preamble and slot time are negotiated when associating. */ 4147 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4148 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4149 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4150 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4151 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4152 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4153 DPRINTF(("rxon chan %d flags %x\n", sc->rxon.chan, sc->rxon.flags)); 4154 error = iwn_cmd(sc, IWN_CMD_CONFIGURE, &sc->rxon, hal->rxonsz, 1); 4155 if (error != 0) { 4156 printf("%s: could not update configuration\n", 4157 sc->sc_dev.dv_xname); 4158 return error; 4159 } 4160 4161 /* Configuration has changed, set TX power accordingly. */ 4162 if ((error = hal->set_txpower(sc, 1)) != 0) { 4163 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 4164 return error; 4165 } 4166 4167 /* Fake a join to initialize the TX rate. */ 4168 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 4169 iwn_newassoc(ic, ni, 1); 4170 4171 /* Add BSS node. */ 4172 memset(&node, 0, sizeof node); 4173 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4174 node.id = IWN_ID_BSS; 4175 #ifdef notyet 4176 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4177 IWN_AMDPU_DENSITY(5)); /* 2us */ 4178 #endif 4179 DPRINTF(("adding BSS node\n")); 4180 error = hal->add_node(sc, &node, 1); 4181 if (error != 0) { 4182 printf("%s: could not add BSS node\n", sc->sc_dev.dv_xname); 4183 return error; 4184 } 4185 DPRINTF(("setting link quality for node %d\n", node.id)); 4186 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 4187 printf("%s: could not setup link quality for node %d\n", 4188 sc->sc_dev.dv_xname, node.id); 4189 return error; 4190 } 4191 4192 if ((error = iwn_init_sensitivity(sc)) != 0) { 4193 printf("%s: could not set sensitivity\n", 4194 sc->sc_dev.dv_xname); 4195 return error; 4196 } 4197 /* Start periodic calibration timer. */ 4198 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4199 sc->calib_cnt = 0; 4200 timeout_add_msec(&sc->calib_to, 500); 4201 4202 /* Link LED always on while associated. */ 4203 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 4204 return 0; 4205 } 4206 4207 /* 4208 * We support CCMP hardware encryption/decryption of unicast frames only. 4209 * HW support for TKIP really sucks. We should let TKIP die anyway. 4210 */ 4211 int 4212 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4213 struct ieee80211_key *k) 4214 { 4215 struct iwn_softc *sc = ic->ic_softc; 4216 const struct iwn_hal *hal = sc->sc_hal; 4217 struct iwn_node *wn = (void *)ni; 4218 struct iwn_node_info node; 4219 uint16_t kflags; 4220 4221 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4222 k->k_cipher != IEEE80211_CIPHER_CCMP) 4223 return ieee80211_set_key(ic, ni, k); 4224 4225 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 4226 if (k->k_flags & IEEE80211_KEY_GROUP) 4227 kflags |= IWN_KFLAG_GROUP; 4228 4229 memset(&node, 0, sizeof node); 4230 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4231 hal->broadcast_id : wn->id; 4232 node.control = IWN_NODE_UPDATE; 4233 node.flags = IWN_FLAG_SET_KEY; 4234 node.kflags = htole16(kflags); 4235 node.kid = k->k_id; 4236 memcpy(node.key, k->k_key, k->k_len); 4237 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 4238 return hal->add_node(sc, &node, 1); 4239 } 4240 4241 void 4242 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4243 struct ieee80211_key *k) 4244 { 4245 struct iwn_softc *sc = ic->ic_softc; 4246 const struct iwn_hal *hal = sc->sc_hal; 4247 struct iwn_node *wn = (void *)ni; 4248 struct iwn_node_info node; 4249 4250 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4251 k->k_cipher != IEEE80211_CIPHER_CCMP) { 4252 /* See comment about other ciphers above. */ 4253 ieee80211_delete_key(ic, ni, k); 4254 return; 4255 } 4256 if (ic->ic_state != IEEE80211_S_RUN) 4257 return; /* Nothing to do. */ 4258 memset(&node, 0, sizeof node); 4259 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4260 hal->broadcast_id : wn->id; 4261 node.control = IWN_NODE_UPDATE; 4262 node.flags = IWN_FLAG_SET_KEY; 4263 node.kflags = htole16(IWN_KFLAG_INVALID); 4264 node.kid = 0xff; 4265 DPRINTF(("delete keys for node %d\n", node.id)); 4266 (void)hal->add_node(sc, &node, 1); 4267 } 4268 4269 #ifndef IEEE80211_NO_HT 4270 /* 4271 * This function is called by upper layer when an ADDBA request is received 4272 * from another STA and before the ADDBA response is sent. 4273 */ 4274 int 4275 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4276 uint8_t tid) 4277 { 4278 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 4279 struct iwn_softc *sc = ic->ic_softc; 4280 struct iwn_node *wn = (void *)ni; 4281 struct iwn_node_info node; 4282 4283 memset(&node, 0, sizeof node); 4284 node.id = wn->id; 4285 node.control = IWN_NODE_UPDATE; 4286 node.flags = IWN_FLAG_SET_ADDBA; 4287 node.addba_tid = tid; 4288 node.addba_ssn = htole16(ba->ba_winstart); 4289 DPRINTFN(2, ("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 4290 ba->ba_winstart)); 4291 return sc->sc_hal->add_node(sc, &node, 1); 4292 } 4293 4294 /* 4295 * This function is called by upper layer on teardown of an HT-immediate 4296 * Block Ack agreement (eg. uppon receipt of a DELBA frame.) 4297 */ 4298 void 4299 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4300 uint8_t tid) 4301 { 4302 struct iwn_softc *sc = ic->ic_softc; 4303 struct iwn_node *wn = (void *)ni; 4304 struct iwn_node_info node; 4305 4306 memset(&node, 0, sizeof node); 4307 node.id = wn->id; 4308 node.control = IWN_NODE_UPDATE; 4309 node.flags = IWN_FLAG_SET_DELBA; 4310 node.delba_tid = tid; 4311 DPRINTFN(2, ("DELBA RA=%d TID=%d\n", wn->id, tid)); 4312 (void)sc->sc_hal->add_node(sc, &node, 1); 4313 } 4314 4315 /* 4316 * This function is called by upper layer when an ADDBA response is received 4317 * from another STA. 4318 */ 4319 int 4320 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4321 uint8_t tid) 4322 { 4323 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4324 struct iwn_softc *sc = ic->ic_softc; 4325 const struct iwn_hal *hal = sc->sc_hal; 4326 struct iwn_node *wn = (void *)ni; 4327 struct iwn_node_info node; 4328 int error; 4329 4330 /* Enable TX for the specified RA/TID. */ 4331 wn->disable_tid &= ~(1 << tid); 4332 memset(&node, 0, sizeof node); 4333 node.id = wn->id; 4334 node.control = IWN_NODE_UPDATE; 4335 node.flags = IWN_FLAG_SET_DISABLE_TID; 4336 node.disable_tid = htole16(wn->disable_tid); 4337 error = hal->add_node(sc, &node, 1); 4338 if (error != 0) 4339 return error; 4340 4341 if ((error = iwn_nic_lock(sc)) != 0) 4342 return error; 4343 hal->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 4344 iwn_nic_unlock(sc); 4345 return 0; 4346 } 4347 4348 void 4349 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4350 uint8_t tid) 4351 { 4352 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4353 struct iwn_softc *sc = ic->ic_softc; 4354 4355 if (iwn_nic_lock(sc) != 0) 4356 return; 4357 sc->sc_hal->ampdu_tx_stop(sc, tid, ba->ba_winstart); 4358 iwn_nic_unlock(sc); 4359 } 4360 4361 void 4362 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4363 uint8_t tid, uint16_t ssn) 4364 { 4365 struct iwn_node *wn = (void *)ni; 4366 int qid = 7 + tid; 4367 4368 /* Stop TX scheduler while we're changing its configuration. */ 4369 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4370 IWN4965_TXQ_STATUS_CHGACT); 4371 4372 /* Assign RA/TID translation to the queue. */ 4373 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 4374 wn->id << 4 | tid); 4375 4376 /* Enable chain mode for the queue. */ 4377 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 4378 4379 /* Set starting sequence number from the ADDBA request. */ 4380 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ssn); 4381 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4382 4383 /* Set scheduler window size. */ 4384 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 4385 IWN_SCHED_WINSZ); 4386 /* Set scheduler frame limit. */ 4387 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4388 IWN_SCHED_LIMIT << 16); 4389 4390 /* Enable interrupts for the queue. */ 4391 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4392 4393 /* Mark the queue as active. */ 4394 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4395 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 4396 iwn_tid2fifo[tid] << 1); 4397 } 4398 4399 void 4400 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4401 { 4402 int qid = 7 + tid; 4403 4404 /* Stop TX scheduler while we're changing its configuration. */ 4405 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4406 IWN4965_TXQ_STATUS_CHGACT); 4407 4408 /* Set starting sequence number from the ADDBA request. */ 4409 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ssn); 4410 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4411 4412 /* Disable interrupts for the queue. */ 4413 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4414 4415 /* Mark the queue as inactive. */ 4416 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4417 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 4418 } 4419 4420 void 4421 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4422 uint8_t tid, uint16_t ssn) 4423 { 4424 struct iwn_node *wn = (void *)ni; 4425 int qid = 10 + tid; 4426 4427 /* Stop TX scheduler while we're changing its configuration. */ 4428 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4429 IWN5000_TXQ_STATUS_CHGACT); 4430 4431 /* Assign RA/TID translation to the queue. */ 4432 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 4433 wn->id << 4 | tid); 4434 4435 /* Enable chain mode for the queue. */ 4436 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 4437 4438 /* Enable aggregation for the queue. */ 4439 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4440 4441 /* Set starting sequence number from the ADDBA request. */ 4442 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ssn); 4443 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4444 4445 /* Set scheduler window size and frame limit. */ 4446 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 4447 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 4448 4449 /* Enable interrupts for the queue. */ 4450 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4451 4452 /* Mark the queue as active. */ 4453 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4454 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 4455 } 4456 4457 void 4458 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4459 { 4460 int qid = 10 + tid; 4461 4462 /* Stop TX scheduler while we're changing its configuration. */ 4463 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4464 IWN5000_TXQ_STATUS_CHGACT); 4465 4466 /* Disable aggregation for the queue. */ 4467 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4468 4469 /* Set starting sequence number from the ADDBA request. */ 4470 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ssn); 4471 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4472 4473 /* Disable interrupts for the queue. */ 4474 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4475 4476 /* Mark the queue as inactive. */ 4477 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4478 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 4479 } 4480 #endif /* !IEEE80211_NO_HT */ 4481 4482 /* 4483 * Query calibration tables from the initialization firmware. We do this 4484 * only once at first boot. Called from a process context. 4485 */ 4486 int 4487 iwn5000_query_calibration(struct iwn_softc *sc) 4488 { 4489 struct iwn5000_calib_config cmd; 4490 int error; 4491 4492 memset(&cmd, 0, sizeof cmd); 4493 cmd.ucode.once.enable = 0xffffffff; 4494 cmd.ucode.once.start = 0xffffffff; 4495 cmd.ucode.once.send = 0xffffffff; 4496 cmd.ucode.flags = 0xffffffff; 4497 DPRINTF(("sending calibration query\n")); 4498 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 4499 if (error != 0) 4500 return error; 4501 4502 /* Wait at most two seconds for calibration to complete. */ 4503 return tsleep(sc, PCATCH, "iwncal", 2 * hz); 4504 } 4505 4506 /* 4507 * Send calibration results to the runtime firmware. These results were 4508 * obtained on first boot from the initialization firmware. 4509 */ 4510 int 4511 iwn5000_send_calibration(struct iwn_softc *sc) 4512 { 4513 int idx, error; 4514 4515 for (idx = 0; idx < 5; idx++) { 4516 if (sc->calibcmd[idx].buf == NULL) 4517 continue; /* No results available. */ 4518 DPRINTF(("send calibration result idx=%d len=%d\n", 4519 idx, sc->calibcmd[idx].len)); 4520 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 4521 sc->calibcmd[idx].len, 0); 4522 if (error != 0) { 4523 printf("%s: could not send calibration result\n", 4524 sc->sc_dev.dv_xname); 4525 return error; 4526 } 4527 } 4528 return 0; 4529 } 4530 4531 /* 4532 * This function is called after the runtime firmware notifies us of its 4533 * readiness (called in a process context.) 4534 */ 4535 int 4536 iwn4965_post_alive(struct iwn_softc *sc) 4537 { 4538 int error, qid; 4539 4540 if ((error = iwn_nic_lock(sc)) != 0) 4541 return error; 4542 4543 /* Clear TX scheduler's state in SRAM. */ 4544 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 4545 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 4546 IWN4965_SCHED_CTX_LEN); 4547 4548 /* Set physical address of TX scheduler rings (1KB aligned.) */ 4549 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 4550 4551 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 4552 4553 /* Disable chain mode for all our 16 queues. */ 4554 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 4555 4556 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 4557 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 4558 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 4559 4560 /* Set scheduler window size. */ 4561 iwn_mem_write(sc, sc->sched_base + 4562 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 4563 /* Set scheduler frame limit. */ 4564 iwn_mem_write(sc, sc->sched_base + 4565 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4566 IWN_SCHED_LIMIT << 16); 4567 } 4568 4569 /* Enable interrupts for all our 16 queues. */ 4570 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 4571 /* Identify TX FIFO rings (0-7). */ 4572 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 4573 4574 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 4575 for (qid = 0; qid < 7; qid++) { 4576 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 4577 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4578 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 4579 } 4580 iwn_nic_unlock(sc); 4581 return 0; 4582 } 4583 4584 /* 4585 * This function is called after the initialization or runtime firmware 4586 * notifies us of its readiness (called in a process context.) 4587 */ 4588 int 4589 iwn5000_post_alive(struct iwn_softc *sc) 4590 { 4591 struct iwn5000_wimax_coex wimax; 4592 int error, qid; 4593 4594 if ((error = iwn_nic_lock(sc)) != 0) 4595 return error; 4596 4597 /* Clear TX scheduler's state in SRAM. */ 4598 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 4599 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 4600 IWN5000_SCHED_CTX_LEN); 4601 4602 /* Set physical address of TX scheduler rings (1KB aligned.) */ 4603 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 4604 4605 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 4606 4607 /* Enable chain mode for all our 20 queues. */ 4608 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffff); 4609 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 4610 4611 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 4612 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 4613 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 4614 4615 iwn_mem_write(sc, sc->sched_base + 4616 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 4617 /* Set scheduler window size and frame limit. */ 4618 iwn_mem_write(sc, sc->sched_base + 4619 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 4620 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 4621 } 4622 4623 /* Enable interrupts for all our 20 queues. */ 4624 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 4625 /* Identify TX FIFO rings (0-7). */ 4626 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 4627 4628 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 4629 for (qid = 0; qid < 7; qid++) { 4630 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 4631 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4632 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 4633 } 4634 iwn_nic_unlock(sc); 4635 4636 /* Configure WiMAX (IEEE 802.16e) coexistence. */ 4637 memset(&wimax, 0, sizeof wimax); 4638 DPRINTF(("Configuring WiMAX coexistence\n")); 4639 error = iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 4640 if (error != 0) { 4641 printf("%s: could not configure WiMAX coexistence\n", 4642 sc->sc_dev.dv_xname); 4643 return error; 4644 } 4645 4646 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 4647 struct iwn5000_phy_calib_crystal cmd; 4648 4649 /* Perform crystal calibration. */ 4650 memset(&cmd, 0, sizeof cmd); 4651 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 4652 cmd.ngroups = 1; 4653 cmd.isvalid = 1; 4654 cmd.cap_pin[0] = letoh32(sc->eeprom_crystal) & 0xff; 4655 cmd.cap_pin[1] = (letoh32(sc->eeprom_crystal) >> 16) & 0xff; 4656 DPRINTF(("sending crystal calibration %d, %d\n", 4657 cmd.cap_pin[0], cmd.cap_pin[1])); 4658 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 4659 if (error != 0) { 4660 printf("%s: crystal calibration failed\n", 4661 sc->sc_dev.dv_xname); 4662 return error; 4663 } 4664 } 4665 if (sc->sc_flags & IWN_FLAG_FIRST_BOOT) { 4666 /* Query calibration from the initialization firmware. */ 4667 if ((error = iwn5000_query_calibration(sc)) != 0) { 4668 printf("%s: could not query calibration\n", 4669 sc->sc_dev.dv_xname); 4670 return error; 4671 } 4672 /* 4673 * We have the calibration results now so we can skip 4674 * loading the initialization firmware next time. 4675 */ 4676 sc->sc_flags &= ~IWN_FLAG_FIRST_BOOT; 4677 4678 /* Reboot (call ourselves recursively!) */ 4679 iwn_hw_stop(sc); 4680 error = iwn_hw_init(sc); 4681 } else { 4682 /* Send calibration results to runtime firmware. */ 4683 error = iwn5000_send_calibration(sc); 4684 } 4685 return error; 4686 } 4687 4688 /* 4689 * The firmware boot code is small and is intended to be copied directly into 4690 * the NIC internal memory (no DMA transfer.) 4691 */ 4692 int 4693 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 4694 { 4695 int error, ntries; 4696 4697 size /= sizeof (uint32_t); 4698 4699 if ((error = iwn_nic_lock(sc)) != 0) 4700 return error; 4701 4702 /* Copy microcode image into NIC memory. */ 4703 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 4704 (const uint32_t *)ucode, size); 4705 4706 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 4707 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 4708 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 4709 4710 /* Start boot load now. */ 4711 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 4712 4713 /* Wait for transfer to complete. */ 4714 for (ntries = 0; ntries < 1000; ntries++) { 4715 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 4716 IWN_BSM_WR_CTRL_START)) 4717 break; 4718 DELAY(10); 4719 } 4720 if (ntries == 1000) { 4721 printf("%s: could not load boot firmware\n", 4722 sc->sc_dev.dv_xname); 4723 iwn_nic_unlock(sc); 4724 return ETIMEDOUT; 4725 } 4726 4727 /* Enable boot after power up. */ 4728 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 4729 4730 iwn_nic_unlock(sc); 4731 return 0; 4732 } 4733 4734 int 4735 iwn4965_load_firmware(struct iwn_softc *sc) 4736 { 4737 struct iwn_fw_info *fw = &sc->fw; 4738 struct iwn_dma_info *dma = &sc->fw_dma; 4739 int error; 4740 4741 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 4742 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 4743 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 4744 BUS_DMASYNC_PREWRITE); 4745 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 4746 fw->init.text, fw->init.textsz); 4747 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 4748 fw->init.textsz, BUS_DMASYNC_PREWRITE); 4749 4750 /* Tell adapter where to find initialization sections. */ 4751 if ((error = iwn_nic_lock(sc)) != 0) 4752 return error; 4753 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 4754 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 4755 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 4756 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 4757 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 4758 iwn_nic_unlock(sc); 4759 4760 /* Load firmware boot code. */ 4761 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 4762 if (error != 0) { 4763 printf("%s: could not load boot firmware\n", 4764 sc->sc_dev.dv_xname); 4765 return error; 4766 } 4767 /* Now press "execute". */ 4768 IWN_WRITE(sc, IWN_RESET, 0); 4769 4770 /* Wait at most one second for first alive notification. */ 4771 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 4772 printf("%s: timeout waiting for adapter to initialize\n", 4773 sc->sc_dev.dv_xname); 4774 return error; 4775 } 4776 4777 /* Retrieve current temperature for initial TX power calibration. */ 4778 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 4779 sc->temp = iwn4965_get_temperature(sc); 4780 4781 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 4782 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 4783 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 4784 BUS_DMASYNC_PREWRITE); 4785 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 4786 fw->main.text, fw->main.textsz); 4787 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 4788 fw->main.textsz, BUS_DMASYNC_PREWRITE); 4789 4790 /* Tell adapter where to find runtime sections. */ 4791 if ((error = iwn_nic_lock(sc)) != 0) 4792 return error; 4793 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 4794 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 4795 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 4796 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 4797 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 4798 IWN_FW_UPDATED | fw->main.textsz); 4799 iwn_nic_unlock(sc); 4800 4801 return 0; 4802 } 4803 4804 int 4805 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 4806 const uint8_t *section, int size) 4807 { 4808 struct iwn_dma_info *dma = &sc->fw_dma; 4809 int error; 4810 4811 /* Copy firmware section into pre-allocated DMA-safe memory. */ 4812 memcpy(dma->vaddr, section, size); 4813 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 4814 4815 if ((error = iwn_nic_lock(sc)) != 0) 4816 return error; 4817 4818 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 4819 IWN_FH_TX_CONFIG_DMA_PAUSE); 4820 4821 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 4822 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 4823 IWN_LOADDR(dma->paddr)); 4824 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 4825 IWN_HIADDR(dma->paddr) << 28 | size); 4826 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 4827 IWN_FH_TXBUF_STATUS_TBNUM(1) | 4828 IWN_FH_TXBUF_STATUS_TBIDX(1) | 4829 IWN_FH_TXBUF_STATUS_TFBD_VALID); 4830 4831 /* Kick Flow Handler to start DMA transfer. */ 4832 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 4833 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 4834 4835 iwn_nic_unlock(sc); 4836 4837 /* Wait at most five seconds for FH DMA transfer to complete. */ 4838 return tsleep(sc, PCATCH, "iwninit", 5 * hz); 4839 } 4840 4841 int 4842 iwn5000_load_firmware(struct iwn_softc *sc) 4843 { 4844 struct iwn_fw_part *fw; 4845 int error; 4846 4847 /* Load the initialization firmware on first boot only. */ 4848 fw = (sc->sc_flags & IWN_FLAG_FIRST_BOOT) ? 4849 &sc->fw.init : &sc->fw.main; 4850 4851 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 4852 fw->text, fw->textsz); 4853 if (error != 0) { 4854 printf("%s: could not load firmware %s section\n", 4855 sc->sc_dev.dv_xname, ".text"); 4856 return error; 4857 } 4858 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 4859 fw->data, fw->datasz); 4860 if (error != 0) { 4861 printf("%s: could not load firmware %s section\n", 4862 sc->sc_dev.dv_xname, ".data"); 4863 return error; 4864 } 4865 4866 /* Now press "execute". */ 4867 IWN_WRITE(sc, IWN_RESET, 0); 4868 return 0; 4869 } 4870 4871 int 4872 iwn_read_firmware(struct iwn_softc *sc) 4873 { 4874 const struct iwn_hal *hal = sc->sc_hal; 4875 struct iwn_fw_info *fw = &sc->fw; 4876 const struct iwn_firmware_hdr *hdr; 4877 size_t size; 4878 int error; 4879 4880 /* Read firmware image from filesystem. */ 4881 if ((error = loadfirmware(sc->fwname, &fw->data, &size)) != 0) { 4882 printf("%s: error, %d, could not read firmware %s\n", 4883 sc->sc_dev.dv_xname, error, sc->fwname); 4884 return error; 4885 } 4886 if (size < sizeof (*hdr)) { 4887 printf("%s: truncated firmware header: %d bytes\n", 4888 sc->sc_dev.dv_xname, size); 4889 free(fw->data, M_DEVBUF); 4890 return EINVAL; 4891 } 4892 /* Extract firmware header information. */ 4893 hdr = (struct iwn_firmware_hdr *)fw->data; 4894 fw->main.textsz = letoh32(hdr->main_textsz); 4895 fw->main.datasz = letoh32(hdr->main_datasz); 4896 fw->init.textsz = letoh32(hdr->init_textsz); 4897 fw->init.datasz = letoh32(hdr->init_datasz); 4898 fw->boot.textsz = letoh32(hdr->boot_textsz); 4899 fw->boot.datasz = 0; 4900 4901 /* Sanity-check firmware header. */ 4902 if (fw->main.textsz > hal->fw_text_maxsz || 4903 fw->main.datasz > hal->fw_data_maxsz || 4904 fw->init.textsz > hal->fw_text_maxsz || 4905 fw->init.datasz > hal->fw_data_maxsz || 4906 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 4907 (fw->boot.textsz & 3) != 0) { 4908 printf("%s: invalid firmware header\n", sc->sc_dev.dv_xname); 4909 free(fw->data, M_DEVBUF); 4910 return EINVAL; 4911 } 4912 4913 /* Check that all firmware sections fit. */ 4914 if (size < sizeof (*hdr) + fw->main.textsz + fw->main.datasz + 4915 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 4916 printf("%s: firmware file too short: %d bytes\n", 4917 sc->sc_dev.dv_xname, size); 4918 free(fw->data, M_DEVBUF); 4919 return EINVAL; 4920 } 4921 4922 /* Get pointers to firmware sections. */ 4923 fw->main.text = (const uint8_t *)(hdr + 1); 4924 fw->main.data = fw->main.text + fw->main.textsz; 4925 fw->init.text = fw->main.data + fw->main.datasz; 4926 fw->init.data = fw->init.text + fw->init.textsz; 4927 fw->boot.text = fw->init.data + fw->init.datasz; 4928 4929 return 0; 4930 } 4931 4932 int 4933 iwn_clock_wait(struct iwn_softc *sc) 4934 { 4935 int ntries; 4936 4937 /* Set "initialization complete" bit. */ 4938 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 4939 4940 /* Wait for clock stabilization. */ 4941 for (ntries = 0; ntries < 25000; ntries++) { 4942 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 4943 return 0; 4944 DELAY(100); 4945 } 4946 printf("%s: timeout waiting for clock stabilization\n", 4947 sc->sc_dev.dv_xname); 4948 return ETIMEDOUT; 4949 } 4950 4951 int 4952 iwn4965_apm_init(struct iwn_softc *sc) 4953 { 4954 int error; 4955 4956 /* Disable L0s. */ 4957 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 4958 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 4959 4960 if ((error = iwn_clock_wait(sc)) != 0) 4961 return error; 4962 4963 if ((error = iwn_nic_lock(sc)) != 0) 4964 return error; 4965 /* Enable DMA. */ 4966 iwn_prph_write(sc, IWN_APMG_CLK_CTRL, 4967 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 4968 DELAY(20); 4969 /* Disable L1. */ 4970 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 4971 iwn_nic_unlock(sc); 4972 4973 return 0; 4974 } 4975 4976 int 4977 iwn5000_apm_init(struct iwn_softc *sc) 4978 { 4979 int error; 4980 4981 /* Disable L0s. */ 4982 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 4983 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 4984 4985 /* Set Flow Handler wait threshold to the maximum. */ 4986 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 4987 4988 /* Enable HAP to move adapter from L1a to L0s. */ 4989 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 4990 4991 if (sc->hw_type != IWN_HW_REV_TYPE_6000 && 4992 sc->hw_type != IWN_HW_REV_TYPE_6050) 4993 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 4994 4995 if ((error = iwn_clock_wait(sc)) != 0) 4996 return error; 4997 4998 if ((error = iwn_nic_lock(sc)) != 0) 4999 return error; 5000 /* Enable DMA. */ 5001 iwn_prph_write(sc, IWN_APMG_CLK_CTRL, IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5002 DELAY(20); 5003 /* Disable L1. */ 5004 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5005 iwn_nic_unlock(sc); 5006 5007 return 0; 5008 } 5009 5010 void 5011 iwn_apm_stop_master(struct iwn_softc *sc) 5012 { 5013 int ntries; 5014 5015 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5016 for (ntries = 0; ntries < 100; ntries++) { 5017 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5018 return; 5019 DELAY(10); 5020 } 5021 printf("%s: timeout waiting for master\n", sc->sc_dev.dv_xname); 5022 } 5023 5024 void 5025 iwn_apm_stop(struct iwn_softc *sc) 5026 { 5027 iwn_apm_stop_master(sc); 5028 5029 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5030 DELAY(10); 5031 /* Clear "initialization complete" bit. */ 5032 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5033 } 5034 5035 int 5036 iwn4965_nic_config(struct iwn_softc *sc) 5037 { 5038 pcireg_t reg; 5039 5040 /* Retrieve PCIe Active State Power Management (ASPM). */ 5041 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 5042 sc->sc_cap_off + PCI_PCIE_LCSR); 5043 if (reg & PCI_PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 5044 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5045 else 5046 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5047 5048 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5049 /* 5050 * I don't believe this to be correct but this is what the 5051 * vendor driver is doing. Probably the bits should not be 5052 * shifted in IWN_RFCFG_*. 5053 */ 5054 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5055 IWN_RFCFG_TYPE(sc->rfcfg) | 5056 IWN_RFCFG_STEP(sc->rfcfg) | 5057 IWN_RFCFG_DASH(sc->rfcfg)); 5058 } 5059 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5060 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5061 return 0; 5062 } 5063 5064 int 5065 iwn5000_nic_config(struct iwn_softc *sc) 5066 { 5067 pcireg_t reg; 5068 int error; 5069 5070 /* Retrieve PCIe Active State Power Management (ASPM). */ 5071 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 5072 sc->sc_cap_off + PCI_PCIE_LCSR); 5073 if (reg & PCI_PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 5074 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5075 else 5076 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5077 5078 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5079 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5080 IWN_RFCFG_TYPE(sc->rfcfg) | 5081 IWN_RFCFG_STEP(sc->rfcfg) | 5082 IWN_RFCFG_DASH(sc->rfcfg)); 5083 } 5084 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5085 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5086 5087 if ((error = iwn_nic_lock(sc)) != 0) 5088 return error; 5089 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 5090 iwn_nic_unlock(sc); 5091 return 0; 5092 } 5093 5094 /* 5095 * Take NIC ownership over Intel Active Management Technology (AMT). 5096 */ 5097 int 5098 iwn_hw_prepare(struct iwn_softc *sc) 5099 { 5100 int ntries; 5101 5102 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 5103 for (ntries = 0; ntries < 15000; ntries++) { 5104 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 5105 IWN_HW_IF_CONFIG_PREPARE_DONE)) 5106 break; 5107 DELAY(10); 5108 } 5109 if (ntries == 15000) 5110 return ETIMEDOUT; 5111 5112 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5113 for (ntries = 0; ntries < 5; ntries++) { 5114 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5115 IWN_HW_IF_CONFIG_NIC_READY) 5116 return 0; 5117 DELAY(10); 5118 } 5119 return ETIMEDOUT; 5120 } 5121 5122 int 5123 iwn_hw_init(struct iwn_softc *sc) 5124 { 5125 const struct iwn_hal *hal = sc->sc_hal; 5126 int error, chnl, qid; 5127 5128 /* Clear pending interrupts. */ 5129 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5130 5131 if ((error = hal->apm_init(sc)) != 0) { 5132 printf("%s: could not power ON adapter\n", 5133 sc->sc_dev.dv_xname); 5134 return error; 5135 } 5136 5137 /* Select VMAIN power source. */ 5138 if ((error = iwn_nic_lock(sc)) != 0) 5139 return error; 5140 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 5141 iwn_nic_unlock(sc); 5142 5143 /* Perform adapter-specific initialization. */ 5144 if ((error = hal->nic_config(sc)) != 0) 5145 return error; 5146 5147 /* Initialize RX ring. */ 5148 if ((error = iwn_nic_lock(sc)) != 0) 5149 return error; 5150 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 5151 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 5152 /* Set physical address of RX ring (256-byte aligned.) */ 5153 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 5154 /* Set physical address of RX status (16-byte aligned.) */ 5155 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 5156 /* Enable RX. */ 5157 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 5158 IWN_FH_RX_CONFIG_ENA | 5159 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 5160 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 5161 IWN_FH_RX_CONFIG_SINGLE_FRAME | 5162 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 5163 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 5164 iwn_nic_unlock(sc); 5165 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 5166 5167 if ((error = iwn_nic_lock(sc)) != 0) 5168 return error; 5169 5170 /* Initialize TX scheduler. */ 5171 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 5172 5173 /* Set physical address of "keep warm" page (16-byte aligned.) */ 5174 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 5175 5176 /* Initialize TX rings. */ 5177 for (qid = 0; qid < hal->ntxqs; qid++) { 5178 struct iwn_tx_ring *txq = &sc->txq[qid]; 5179 5180 /* Set physical address of TX ring (256-byte aligned.) */ 5181 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 5182 txq->desc_dma.paddr >> 8); 5183 } 5184 iwn_nic_unlock(sc); 5185 5186 /* Enable DMA channels. */ 5187 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 5188 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 5189 IWN_FH_TX_CONFIG_DMA_ENA | 5190 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 5191 } 5192 5193 /* Clear "radio off" and "commands blocked" bits. */ 5194 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5195 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 5196 5197 /* Clear pending interrupts. */ 5198 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5199 /* Enable interrupt coalescing. */ 5200 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 5201 /* Enable interrupts. */ 5202 IWN_WRITE(sc, IWN_MASK, IWN_INT_MASK); 5203 5204 /* _Really_ make sure "radio off" bit is cleared! */ 5205 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5206 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5207 5208 if ((error = hal->load_firmware(sc)) != 0) { 5209 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 5210 return error; 5211 } 5212 /* Wait at most one second for firmware alive notification. */ 5213 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5214 printf("%s: timeout waiting for adapter to initialize\n", 5215 sc->sc_dev.dv_xname); 5216 return error; 5217 } 5218 /* Do post-firmware initialization. */ 5219 return hal->post_alive(sc); 5220 } 5221 5222 void 5223 iwn_hw_stop(struct iwn_softc *sc) 5224 { 5225 const struct iwn_hal *hal = sc->sc_hal; 5226 int chnl, qid, ntries; 5227 uint32_t tmp; 5228 5229 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 5230 5231 /* Disable interrupts. */ 5232 IWN_WRITE(sc, IWN_MASK, 0); 5233 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5234 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 5235 5236 /* Make sure we no longer hold the NIC lock. */ 5237 iwn_nic_unlock(sc); 5238 5239 /* Stop TX scheduler. */ 5240 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 5241 5242 /* Stop all DMA channels. */ 5243 if (iwn_nic_lock(sc) == 0) { 5244 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 5245 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 5246 for (ntries = 0; ntries < 200; ntries++) { 5247 tmp = IWN_READ(sc, IWN_FH_TX_STATUS); 5248 if ((tmp & IWN_FH_TX_STATUS_IDLE(chnl)) == 5249 IWN_FH_TX_STATUS_IDLE(chnl)) 5250 break; 5251 DELAY(10); 5252 } 5253 } 5254 iwn_nic_unlock(sc); 5255 } 5256 5257 /* Stop RX ring. */ 5258 iwn_reset_rx_ring(sc, &sc->rxq); 5259 5260 /* Reset all TX rings. */ 5261 for (qid = 0; qid < hal->ntxqs; qid++) 5262 iwn_reset_tx_ring(sc, &sc->txq[qid]); 5263 5264 if (iwn_nic_lock(sc) == 0) { 5265 iwn_prph_write(sc, IWN_APMG_CLK_DIS, IWN_APMG_CLK_DMA_RQT); 5266 iwn_nic_unlock(sc); 5267 } 5268 DELAY(5); 5269 /* Power OFF adapter. */ 5270 iwn_apm_stop(sc); 5271 } 5272 5273 int 5274 iwn_init(struct ifnet *ifp) 5275 { 5276 struct iwn_softc *sc = ifp->if_softc; 5277 struct ieee80211com *ic = &sc->sc_ic; 5278 int error; 5279 5280 if ((error = iwn_hw_prepare(sc)) != 0) { 5281 printf("%s: hardware not ready\n", sc->sc_dev.dv_xname); 5282 goto fail; 5283 } 5284 5285 /* Check that the radio is not disabled by hardware switch. */ 5286 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 5287 printf("%s: radio is disabled by hardware switch\n", 5288 sc->sc_dev.dv_xname); 5289 error = EPERM; /* :-) */ 5290 goto fail; 5291 } 5292 5293 /* Read firmware images from the filesystem. */ 5294 if ((error = iwn_read_firmware(sc)) != 0) { 5295 printf("%s: could not read firmware\n", sc->sc_dev.dv_xname); 5296 goto fail; 5297 } 5298 5299 /* Initialize hardware and upload firmware. */ 5300 error = iwn_hw_init(sc); 5301 free(sc->fw.data, M_DEVBUF); 5302 if (error != 0) { 5303 printf("%s: could not initialize hardware\n", 5304 sc->sc_dev.dv_xname); 5305 goto fail; 5306 } 5307 5308 /* Configure adapter now that it is ready. */ 5309 if ((error = iwn_config(sc)) != 0) { 5310 printf("%s: could not configure device\n", 5311 sc->sc_dev.dv_xname); 5312 goto fail; 5313 } 5314 5315 ifp->if_flags &= ~IFF_OACTIVE; 5316 ifp->if_flags |= IFF_RUNNING; 5317 5318 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5319 ieee80211_begin_scan(ifp); 5320 else 5321 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5322 5323 return 0; 5324 5325 fail: iwn_stop(ifp, 1); 5326 return error; 5327 } 5328 5329 void 5330 iwn_stop(struct ifnet *ifp, int disable) 5331 { 5332 struct iwn_softc *sc = ifp->if_softc; 5333 struct ieee80211com *ic = &sc->sc_ic; 5334 5335 ifp->if_timer = sc->sc_tx_timer = 0; 5336 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5337 5338 /* In case we were scanning, release the scan "lock". */ 5339 ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; 5340 5341 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5342 5343 /* Power OFF hardware. */ 5344 iwn_hw_stop(sc); 5345 5346 /* Temperature sensor is no longer valid. */ 5347 sc->sensor.value = 0; 5348 sc->sensor.flags |= SENSOR_FINVALID; 5349 } 5350