xref: /openbsd-src/sys/dev/pci/if_iwmvar.h (revision f80108b1e78214934d34a902bf40cba38c2652ba)
1*f80108b1Sstsp /*	$OpenBSD: if_iwmvar.h,v 1.78 2022/05/14 05:47:04 stsp Exp $	*/
2e8078fe0Sstsp 
3e8078fe0Sstsp /*
4e8078fe0Sstsp  * Copyright (c) 2014 genua mbh <info@genua.de>
5e8078fe0Sstsp  * Copyright (c) 2014 Fixup Software Ltd.
6e8078fe0Sstsp  *
7e8078fe0Sstsp  * Permission to use, copy, modify, and distribute this software for any
8e8078fe0Sstsp  * purpose with or without fee is hereby granted, provided that the above
9e8078fe0Sstsp  * copyright notice and this permission notice appear in all copies.
10e8078fe0Sstsp  *
11e8078fe0Sstsp  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12e8078fe0Sstsp  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13e8078fe0Sstsp  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14e8078fe0Sstsp  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15e8078fe0Sstsp  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16e8078fe0Sstsp  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17e8078fe0Sstsp  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18e8078fe0Sstsp  */
19e8078fe0Sstsp 
20e8078fe0Sstsp /*-
21e8078fe0Sstsp  * Based on BSD-licensed source modules in the Linux iwlwifi driver,
22e8078fe0Sstsp  * which were used as the reference documentation for this implementation.
23e8078fe0Sstsp  *
24e8078fe0Sstsp  * Driver version we are currently based off of is
25e8078fe0Sstsp  * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd)
26e8078fe0Sstsp  *
27e8078fe0Sstsp  ***********************************************************************
28e8078fe0Sstsp  *
29e8078fe0Sstsp  * This file is provided under a dual BSD/GPLv2 license.  When using or
30e8078fe0Sstsp  * redistributing this file, you may do so under either license.
31e8078fe0Sstsp  *
32e8078fe0Sstsp  * GPL LICENSE SUMMARY
33e8078fe0Sstsp  *
34e8078fe0Sstsp  * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
35e8078fe0Sstsp  *
36e8078fe0Sstsp  * This program is free software; you can redistribute it and/or modify
37e8078fe0Sstsp  * it under the terms of version 2 of the GNU General Public License as
38e8078fe0Sstsp  * published by the Free Software Foundation.
39e8078fe0Sstsp  *
40e8078fe0Sstsp  * This program is distributed in the hope that it will be useful, but
41e8078fe0Sstsp  * WITHOUT ANY WARRANTY; without even the implied warranty of
42e8078fe0Sstsp  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
43e8078fe0Sstsp  * General Public License for more details.
44e8078fe0Sstsp  *
45e8078fe0Sstsp  * You should have received a copy of the GNU General Public License
46e8078fe0Sstsp  * along with this program; if not, write to the Free Software
47e8078fe0Sstsp  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
48e8078fe0Sstsp  * USA
49e8078fe0Sstsp  *
50e8078fe0Sstsp  * The full GNU General Public License is included in this distribution
51e8078fe0Sstsp  * in the file called COPYING.
52e8078fe0Sstsp  *
53e8078fe0Sstsp  * Contact Information:
54e8078fe0Sstsp  *  Intel Linux Wireless <ilw@linux.intel.com>
55e8078fe0Sstsp  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
56e8078fe0Sstsp  *
57e8078fe0Sstsp  *
58e8078fe0Sstsp  * BSD LICENSE
59e8078fe0Sstsp  *
60e8078fe0Sstsp  * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
61e8078fe0Sstsp  * All rights reserved.
62e8078fe0Sstsp  *
63e8078fe0Sstsp  * Redistribution and use in source and binary forms, with or without
64e8078fe0Sstsp  * modification, are permitted provided that the following conditions
65e8078fe0Sstsp  * are met:
66e8078fe0Sstsp  *
67e8078fe0Sstsp  *  * Redistributions of source code must retain the above copyright
68e8078fe0Sstsp  *    notice, this list of conditions and the following disclaimer.
69e8078fe0Sstsp  *  * Redistributions in binary form must reproduce the above copyright
70e8078fe0Sstsp  *    notice, this list of conditions and the following disclaimer in
71e8078fe0Sstsp  *    the documentation and/or other materials provided with the
72e8078fe0Sstsp  *    distribution.
73e8078fe0Sstsp  *  * Neither the name Intel Corporation nor the names of its
74e8078fe0Sstsp  *    contributors may be used to endorse or promote products derived
75e8078fe0Sstsp  *    from this software without specific prior written permission.
76e8078fe0Sstsp  *
77e8078fe0Sstsp  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
78e8078fe0Sstsp  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
79e8078fe0Sstsp  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
80e8078fe0Sstsp  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
81e8078fe0Sstsp  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
82e8078fe0Sstsp  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
83e8078fe0Sstsp  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
84e8078fe0Sstsp  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
85e8078fe0Sstsp  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
86e8078fe0Sstsp  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
87e8078fe0Sstsp  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
88e8078fe0Sstsp  */
89e8078fe0Sstsp 
90e8078fe0Sstsp /*-
91e8078fe0Sstsp  * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
92e8078fe0Sstsp  *
93e8078fe0Sstsp  * Permission to use, copy, modify, and distribute this software for any
94e8078fe0Sstsp  * purpose with or without fee is hereby granted, provided that the above
95e8078fe0Sstsp  * copyright notice and this permission notice appear in all copies.
96e8078fe0Sstsp  *
97e8078fe0Sstsp  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
98e8078fe0Sstsp  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
99e8078fe0Sstsp  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
100e8078fe0Sstsp  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
101e8078fe0Sstsp  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
102e8078fe0Sstsp  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
103e8078fe0Sstsp  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
104e8078fe0Sstsp  */
105e8078fe0Sstsp 
1068d0ee892Sstsp struct iwm_rx_radiotap_header {
1078d0ee892Sstsp 	struct ieee80211_radiotap_header wr_ihdr;
1088d0ee892Sstsp 	uint64_t	wr_tsft;
1098d0ee892Sstsp 	uint8_t		wr_flags;
1108d0ee892Sstsp 	uint8_t		wr_rate;
1118d0ee892Sstsp 	uint16_t	wr_chan_freq;
1128d0ee892Sstsp 	uint16_t	wr_chan_flags;
1138d0ee892Sstsp 	int8_t		wr_dbm_antsignal;
1148d0ee892Sstsp 	int8_t		wr_dbm_antnoise;
1158d0ee892Sstsp } __packed;
1168d0ee892Sstsp 
1178d0ee892Sstsp #define IWM_RX_RADIOTAP_PRESENT						\
1188d0ee892Sstsp 	((1 << IEEE80211_RADIOTAP_TSFT) |				\
1198d0ee892Sstsp 	 (1 << IEEE80211_RADIOTAP_FLAGS) |				\
1208d0ee892Sstsp 	 (1 << IEEE80211_RADIOTAP_RATE) |				\
1218d0ee892Sstsp 	 (1 << IEEE80211_RADIOTAP_CHANNEL) |				\
1228d0ee892Sstsp 	 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |			\
1238d0ee892Sstsp 	 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE))
1248d0ee892Sstsp 
1258d0ee892Sstsp struct iwm_tx_radiotap_header {
1268d0ee892Sstsp 	struct ieee80211_radiotap_header wt_ihdr;
1278d0ee892Sstsp 	uint8_t		wt_flags;
1288d0ee892Sstsp 	uint8_t		wt_rate;
1298d0ee892Sstsp 	uint16_t	wt_chan_freq;
1308d0ee892Sstsp 	uint16_t	wt_chan_flags;
1318d0ee892Sstsp } __packed;
1328d0ee892Sstsp 
1338d0ee892Sstsp #define IWM_TX_RADIOTAP_PRESENT						\
1348d0ee892Sstsp 	((1 << IEEE80211_RADIOTAP_FLAGS) |				\
1358d0ee892Sstsp 	 (1 << IEEE80211_RADIOTAP_RATE) |				\
136eb1adcecSmpi 	 (1 << IEEE80211_RADIOTAP_CHANNEL))
1378d0ee892Sstsp 
13888a9fda3Sstsp #define IWM_UCODE_SECT_MAX 16
139e8078fe0Sstsp #define IWM_FWDMASEGSZ (192*1024)
1400e4c2833Sstsp #define IWM_FWDMASEGSZ_8000 (320*1024)
141e8078fe0Sstsp /* sanity check value */
142e8078fe0Sstsp #define IWM_FWMAXSIZE (2*1024*1024)
143e8078fe0Sstsp 
144e8078fe0Sstsp /*
145e8078fe0Sstsp  * fw_status is used to determine if we've already parsed the firmware file
146e8078fe0Sstsp  *
147e8078fe0Sstsp  * In addition to the following, status < 0 ==> -error
148e8078fe0Sstsp  */
149e8078fe0Sstsp #define IWM_FW_STATUS_NONE		0
150e8078fe0Sstsp #define IWM_FW_STATUS_INPROGRESS	1
151e8078fe0Sstsp #define IWM_FW_STATUS_DONE		2
152e8078fe0Sstsp 
153e8078fe0Sstsp enum iwm_ucode_type {
154e8078fe0Sstsp 	IWM_UCODE_TYPE_REGULAR,
15588a9fda3Sstsp 	IWM_UCODE_TYPE_INIT,
156e8078fe0Sstsp 	IWM_UCODE_TYPE_WOW,
15788a9fda3Sstsp 	IWM_UCODE_TYPE_REGULAR_USNIFFER,
158e8078fe0Sstsp 	IWM_UCODE_TYPE_MAX
159e8078fe0Sstsp };
160e8078fe0Sstsp 
161e8078fe0Sstsp struct iwm_fw_info {
162e8078fe0Sstsp 	void *fw_rawdata;
163e8078fe0Sstsp 	size_t fw_rawsize;
164e8078fe0Sstsp 	int fw_status;
165e8078fe0Sstsp 
166e8078fe0Sstsp 	struct iwm_fw_sects {
167e8078fe0Sstsp 		struct iwm_fw_onesect {
168e8078fe0Sstsp 			void *fws_data;
169e8078fe0Sstsp 			uint32_t fws_len;
170e8078fe0Sstsp 			uint32_t fws_devoff;
171e8078fe0Sstsp 		} fw_sect[IWM_UCODE_SECT_MAX];
172e8078fe0Sstsp 		size_t fw_totlen;
173e8078fe0Sstsp 		int fw_count;
17449c89610Sstsp 		uint32_t paging_mem_size;
175e8078fe0Sstsp 	} fw_sects[IWM_UCODE_TYPE_MAX];
176e8078fe0Sstsp };
177e8078fe0Sstsp 
178e8078fe0Sstsp struct iwm_nvm_data {
179e8078fe0Sstsp 	int n_hw_addrs;
180e8078fe0Sstsp 	uint8_t hw_addr[ETHER_ADDR_LEN];
181e8078fe0Sstsp 
182e8078fe0Sstsp 	uint8_t calib_version;
183e8078fe0Sstsp 	uint16_t calib_voltage;
184e8078fe0Sstsp 
185e8078fe0Sstsp 	uint16_t raw_temperature;
186e8078fe0Sstsp 	uint16_t kelvin_temperature;
187e8078fe0Sstsp 	uint16_t kelvin_voltage;
188e8078fe0Sstsp 	uint16_t xtal_calib[2];
189e8078fe0Sstsp 
190e8078fe0Sstsp 	int sku_cap_band_24GHz_enable;
191e8078fe0Sstsp 	int sku_cap_band_52GHz_enable;
192e8078fe0Sstsp 	int sku_cap_11n_enable;
19359aafb1aSstsp 	int sku_cap_11ac_enable;
194e8078fe0Sstsp 	int sku_cap_amt_enable;
195e8078fe0Sstsp 	int sku_cap_ipan_enable;
196d1ea7b21Sstsp 	int sku_cap_mimo_disable;
197e8078fe0Sstsp 
198e8078fe0Sstsp 	uint8_t radio_cfg_type;
199e8078fe0Sstsp 	uint8_t radio_cfg_step;
200e8078fe0Sstsp 	uint8_t radio_cfg_dash;
201e8078fe0Sstsp 	uint8_t radio_cfg_pnum;
202e8078fe0Sstsp 	uint8_t valid_tx_ant, valid_rx_ant;
203e8078fe0Sstsp 
204e8078fe0Sstsp 	uint16_t nvm_version;
205e8078fe0Sstsp 	uint8_t max_tx_pwr_half_dbm;
2065383e891Sstsp 
2075383e891Sstsp 	int lar_enabled;
208e8078fe0Sstsp };
209e8078fe0Sstsp 
210e8078fe0Sstsp /* max bufs per tfd the driver will use */
211e8078fe0Sstsp #define IWM_MAX_CMD_TBS_PER_TFD 2
212e8078fe0Sstsp 
213e8078fe0Sstsp struct iwm_host_cmd {
214e8078fe0Sstsp 	const void *data[IWM_MAX_CMD_TBS_PER_TFD];
215e8078fe0Sstsp 	struct iwm_rx_packet *resp_pkt;
216ade4b715Sstsp 	size_t resp_pkt_len;
217e8078fe0Sstsp 	unsigned long _rx_page_addr;
218e8078fe0Sstsp 	uint32_t _rx_page_order;
219e8078fe0Sstsp 	int handler_status;
220e8078fe0Sstsp 
221e8078fe0Sstsp 	uint32_t flags;
222e8078fe0Sstsp 	uint16_t len[IWM_MAX_CMD_TBS_PER_TFD];
223e8078fe0Sstsp 	uint8_t dataflags[IWM_MAX_CMD_TBS_PER_TFD];
22488a9fda3Sstsp 	uint32_t id;
225e8078fe0Sstsp };
226e8078fe0Sstsp 
227e8078fe0Sstsp /*
228e8078fe0Sstsp  * DMA glue is from iwn
229e8078fe0Sstsp  */
230e8078fe0Sstsp 
231e8078fe0Sstsp struct iwm_dma_info {
232e8078fe0Sstsp 	bus_dma_tag_t		tag;
233e8078fe0Sstsp 	bus_dmamap_t		map;
234e8078fe0Sstsp 	bus_dma_segment_t	seg;
235e8078fe0Sstsp 	bus_addr_t		paddr;
236e8078fe0Sstsp 	void 			*vaddr;
237e8078fe0Sstsp 	bus_size_t		size;
238e8078fe0Sstsp };
239e8078fe0Sstsp 
24049c89610Sstsp /**
24149c89610Sstsp  * struct iwm_fw_paging
24249c89610Sstsp  * @fw_paging_block: dma memory info
24349c89610Sstsp  * @fw_paging_size: page size
24449c89610Sstsp  */
24549c89610Sstsp struct iwm_fw_paging {
24649c89610Sstsp 	struct iwm_dma_info fw_paging_block;
24749c89610Sstsp 	uint32_t fw_paging_size;
24849c89610Sstsp };
24949c89610Sstsp 
250e8078fe0Sstsp #define IWM_TX_RING_COUNT	256
251e8078fe0Sstsp #define IWM_TX_RING_LOMARK	192
252e8078fe0Sstsp #define IWM_TX_RING_HIMARK	224
253e8078fe0Sstsp 
254bdd76655Sstsp /* For aggregation queues, index must be aligned to frame sequence number. */
255bdd76655Sstsp #define IWM_AGG_SSN_TO_TXQ_IDX(x)	((x) & (IWM_TX_RING_COUNT - 1))
256bdd76655Sstsp 
257e8078fe0Sstsp struct iwm_tx_data {
258e8078fe0Sstsp 	bus_dmamap_t	map;
259e8078fe0Sstsp 	bus_addr_t	cmd_paddr;
260e8078fe0Sstsp 	bus_addr_t	scratch_paddr;
261e8078fe0Sstsp 	struct mbuf	*m;
262e8078fe0Sstsp 	struct iwm_node *in;
263be0a7268Sstsp 	int txmcs;
264be0a7268Sstsp 	int txrate;
265bdd76655Sstsp 
266bdd76655Sstsp 	/* A-MPDU subframes */
267bdd76655Sstsp 	int ampdu_txmcs;
26859aafb1aSstsp 	int ampdu_txnss;
269bdd76655Sstsp 	int ampdu_nframes;
270e8078fe0Sstsp };
271e8078fe0Sstsp 
272e8078fe0Sstsp struct iwm_tx_ring {
273e8078fe0Sstsp 	struct iwm_dma_info	desc_dma;
274e8078fe0Sstsp 	struct iwm_dma_info	cmd_dma;
275e8078fe0Sstsp 	struct iwm_tfd		*desc;
276e8078fe0Sstsp 	struct iwm_device_cmd	*cmd;
277e8078fe0Sstsp 	struct iwm_tx_data	data[IWM_TX_RING_COUNT];
278e8078fe0Sstsp 	int			qid;
279e8078fe0Sstsp 	int			queued;
280e8078fe0Sstsp 	int			cur;
281eb93640fSstsp 	int			tail;
282e8078fe0Sstsp };
283e8078fe0Sstsp 
2843287dca4Sstsp #define IWM_RX_MQ_RING_COUNT	512
285e8078fe0Sstsp #define IWM_RX_RING_COUNT	256
286e8078fe0Sstsp /* Linux driver optionally uses 8k buffer */
287e8078fe0Sstsp #define IWM_RBUF_SIZE		4096
288e8078fe0Sstsp 
289e8078fe0Sstsp struct iwm_rx_data {
290e8078fe0Sstsp 	struct mbuf	*m;
291e8078fe0Sstsp 	bus_dmamap_t	map;
292e8078fe0Sstsp };
293e8078fe0Sstsp 
294e8078fe0Sstsp struct iwm_rx_ring {
2953287dca4Sstsp 	struct iwm_dma_info	free_desc_dma;
296e8078fe0Sstsp 	struct iwm_dma_info	stat_dma;
2973287dca4Sstsp 	struct iwm_dma_info	used_desc_dma;
2983287dca4Sstsp 	void			*desc;
299e8078fe0Sstsp 	struct iwm_rb_status	*stat;
3003287dca4Sstsp 	struct iwm_rx_data	data[IWM_RX_MQ_RING_COUNT];
301e8078fe0Sstsp 	int			cur;
302e8078fe0Sstsp };
303e8078fe0Sstsp 
304fd759d73Sstsp #define IWM_FLAG_USE_ICT	0x01	/* using Interrupt Cause Table */
305fd759d73Sstsp #define IWM_FLAG_RFKILL		0x02	/* radio kill switch is set */
306fd759d73Sstsp #define IWM_FLAG_SCANNING	0x04	/* scan in progress */
307fd759d73Sstsp #define IWM_FLAG_MAC_ACTIVE	0x08	/* MAC context added to firmware */
308fd759d73Sstsp #define IWM_FLAG_BINDING_ACTIVE	0x10	/* MAC->PHY binding added to firmware */
309fd759d73Sstsp #define IWM_FLAG_STA_ACTIVE	0x20	/* AP added to firmware station table */
3107fd96644Sstsp #define IWM_FLAG_TE_ACTIVE	0x40	/* time event is scheduled */
31183fc9da4Sstsp #define IWM_FLAG_HW_ERR		0x80	/* hardware error occurred */
312085456faSstsp #define IWM_FLAG_SHUTDOWN	0x100	/* shutting down; new tasks forbidden */
31306e069b5Sstsp #define IWM_FLAG_BGSCAN		0x200	/* background scan in progress */
3148dcb626aSstsp #define IWM_FLAG_TXFLUSH	0x400	/* Tx queue flushing in progress */
315e8078fe0Sstsp 
316e8078fe0Sstsp struct iwm_ucode_status {
317e8078fe0Sstsp 	uint32_t uc_error_event_table;
3180e4c2833Sstsp 	uint32_t uc_umac_error_event_table;
319e8078fe0Sstsp 	uint32_t uc_log_event_table;
320e8078fe0Sstsp 
321e8078fe0Sstsp 	int uc_ok;
322e8078fe0Sstsp 	int uc_intr;
323e8078fe0Sstsp };
324e8078fe0Sstsp 
325e8078fe0Sstsp #define IWM_CMD_RESP_MAX PAGE_SIZE
326e8078fe0Sstsp 
32788a9fda3Sstsp /* lower blocks contain EEPROM image and calibration data */
32888a9fda3Sstsp #define IWM_OTP_LOW_IMAGE_SIZE_FAMILY_7000 	16384
3290e4c2833Sstsp #define IWM_OTP_LOW_IMAGE_SIZE_FAMILY_8000	32768
330e8078fe0Sstsp 
33103445d8cSstsp #define IWM_TE_SESSION_PROTECTION_MAX_TIME_MS 1000
33203445d8cSstsp #define IWM_TE_SESSION_PROTECTION_MIN_TIME_MS 400
333e8078fe0Sstsp 
334e8078fe0Sstsp enum IWM_CMD_MODE {
335e8078fe0Sstsp 	IWM_CMD_ASYNC		= (1 << 0),
336ade4b715Sstsp 	IWM_CMD_WANT_RESP	= (1 << 1),
337e8078fe0Sstsp 	IWM_CMD_SEND_IN_RFKILL	= (1 << 2),
338e8078fe0Sstsp };
339e8078fe0Sstsp enum iwm_hcmd_dataflag {
340e8078fe0Sstsp 	IWM_HCMD_DFL_NOCOPY     = (1 << 0),
341e8078fe0Sstsp 	IWM_HCMD_DFL_DUP        = (1 << 1),
342e8078fe0Sstsp };
343e8078fe0Sstsp 
34488a9fda3Sstsp #define IWM_NUM_PAPD_CH_GROUPS	9
345e8078fe0Sstsp #define IWM_NUM_TXP_CH_GROUPS	9
346e8078fe0Sstsp 
347e8078fe0Sstsp struct iwm_phy_db_entry {
348e8078fe0Sstsp 	uint16_t size;
349e8078fe0Sstsp 	uint8_t *data;
350e8078fe0Sstsp };
351e8078fe0Sstsp 
352e8078fe0Sstsp struct iwm_phy_db {
353e8078fe0Sstsp 	struct iwm_phy_db_entry	cfg;
354e8078fe0Sstsp 	struct iwm_phy_db_entry	calib_nch;
355e8078fe0Sstsp 	struct iwm_phy_db_entry	calib_ch_group_papd[IWM_NUM_PAPD_CH_GROUPS];
356e8078fe0Sstsp 	struct iwm_phy_db_entry	calib_ch_group_txp[IWM_NUM_TXP_CH_GROUPS];
357e8078fe0Sstsp };
358e8078fe0Sstsp 
35903445d8cSstsp struct iwm_phy_ctxt {
360e8078fe0Sstsp 	uint16_t id;
361e8078fe0Sstsp 	uint16_t color;
362e8078fe0Sstsp 	uint32_t ref;
363e8078fe0Sstsp 	struct ieee80211_channel *channel;
364880afff8Sstsp 	uint8_t sco; /* 40 MHz secondary channel offset */
36559aafb1aSstsp 	uint8_t vht_chan_width;
366e8078fe0Sstsp };
367e8078fe0Sstsp 
368e8078fe0Sstsp struct iwm_bf_data {
369e8078fe0Sstsp 	int bf_enabled;		/* filtering	*/
370e8078fe0Sstsp 	int ba_enabled;		/* abort	*/
371e8078fe0Sstsp 	int ave_beacon_signal;
372e8078fe0Sstsp 	int last_cqm_event;
373e8078fe0Sstsp };
374e8078fe0Sstsp 
375ccc2d1c4Sstsp /**
376ccc2d1c4Sstsp  * struct iwm_reorder_buffer - per ra/tid/queue reorder buffer
377ccc2d1c4Sstsp  * @head_sn: reorder window head sn
378ccc2d1c4Sstsp  * @num_stored: number of mpdus stored in the buffer
379ccc2d1c4Sstsp  * @buf_size: the reorder buffer size as set by the last addba request
380ccc2d1c4Sstsp  * @queue: queue of this reorder buffer
381ccc2d1c4Sstsp  * @last_amsdu: track last ASMDU SN for duplication detection
382ccc2d1c4Sstsp  * @last_sub_index: track ASMDU sub frame index for duplication detection
383ccc2d1c4Sstsp  * @reorder_timer: timer for frames are in the reorder buffer. For AMSDU
384ccc2d1c4Sstsp  *	it is the time of last received sub-frame
385ccc2d1c4Sstsp  * @removed: prevent timer re-arming
386ccc2d1c4Sstsp  * @valid: reordering is valid for this queue
387ccc2d1c4Sstsp  * @consec_oldsn_drops: consecutive drops due to old SN
388ccc2d1c4Sstsp  * @consec_oldsn_ampdu_gp2: A-MPDU GP2 timestamp to track
389ccc2d1c4Sstsp  *	when to apply old SN consecutive drop workaround
390ccc2d1c4Sstsp  * @consec_oldsn_prev_drop: track whether or not an MPDU
391ccc2d1c4Sstsp  *	that was single/part of the previous A-MPDU was
392ccc2d1c4Sstsp  *	dropped due to old SN
393ccc2d1c4Sstsp  */
394ccc2d1c4Sstsp struct iwm_reorder_buffer {
395ccc2d1c4Sstsp 	uint16_t head_sn;
396ccc2d1c4Sstsp 	uint16_t num_stored;
397ccc2d1c4Sstsp 	uint16_t buf_size;
398ccc2d1c4Sstsp 	uint16_t last_amsdu;
399ccc2d1c4Sstsp 	uint8_t last_sub_index;
400ccc2d1c4Sstsp 	struct timeout reorder_timer;
401ccc2d1c4Sstsp 	int removed;
402ccc2d1c4Sstsp 	int valid;
403ccc2d1c4Sstsp 	unsigned int consec_oldsn_drops;
404ccc2d1c4Sstsp 	uint32_t consec_oldsn_ampdu_gp2;
405ccc2d1c4Sstsp 	unsigned int consec_oldsn_prev_drop;
406ccc2d1c4Sstsp #define IWM_AMPDU_CONSEC_DROPS_DELBA	10
407ccc2d1c4Sstsp };
408ccc2d1c4Sstsp 
409ccc2d1c4Sstsp /**
410ccc2d1c4Sstsp  * struct iwm_reorder_buf_entry - reorder buffer entry per frame sequence number
411ccc2d1c4Sstsp  * @frames: list of mbufs stored (A-MSDU subframes share a sequence number)
412ccc2d1c4Sstsp  * @reorder_time: time the packet was stored in the reorder buffer
413ccc2d1c4Sstsp  */
414ccc2d1c4Sstsp struct iwm_reorder_buf_entry {
415ccc2d1c4Sstsp 	struct mbuf_list frames;
416ccc2d1c4Sstsp 	struct timeval reorder_time;
417ccc2d1c4Sstsp 	uint32_t rx_pkt_status;
418ccc2d1c4Sstsp 	int chanidx;
419ccc2d1c4Sstsp 	int is_shortpre;
420ccc2d1c4Sstsp 	uint32_t rate_n_flags;
421ccc2d1c4Sstsp 	uint32_t device_timestamp;
422ccc2d1c4Sstsp 	struct ieee80211_rxinfo rxi;
423ccc2d1c4Sstsp };
424ccc2d1c4Sstsp 
425ccc2d1c4Sstsp /**
426ccc2d1c4Sstsp  * struct iwm_rxba_data - BA session data
427ccc2d1c4Sstsp  * @sta_id: station id
428ccc2d1c4Sstsp  * @tid: tid of the session
429ccc2d1c4Sstsp  * @baid: baid of the session
430ccc2d1c4Sstsp  * @timeout: the timeout set in the addba request
431ccc2d1c4Sstsp  * @entries_per_queue: # of buffers per queue
432ccc2d1c4Sstsp  * @last_rx: last rx timestamp, updated only if timeout passed from last update
433ccc2d1c4Sstsp  * @session_timer: timer to check if BA session expired, runs at 2 * timeout
434ccc2d1c4Sstsp  * @sc: softc pointer, needed for timer context
435ccc2d1c4Sstsp  * @reorder_buf: reorder buffer
436ccc2d1c4Sstsp  * @reorder_buf_data: buffered frames, one entry per sequence number
437ccc2d1c4Sstsp  */
438ccc2d1c4Sstsp struct iwm_rxba_data {
439ccc2d1c4Sstsp 	uint8_t sta_id;
440ccc2d1c4Sstsp 	uint8_t tid;
441ccc2d1c4Sstsp 	uint8_t baid;
442ccc2d1c4Sstsp 	uint16_t timeout;
443ccc2d1c4Sstsp 	uint16_t entries_per_queue;
444ccc2d1c4Sstsp 	struct timeval last_rx;
445ccc2d1c4Sstsp 	struct timeout session_timer;
446ccc2d1c4Sstsp 	struct iwm_softc *sc;
447ccc2d1c4Sstsp 	struct iwm_reorder_buffer reorder_buf;
448ccc2d1c4Sstsp 	struct iwm_reorder_buf_entry entries[IEEE80211_BA_MAX_WINSZ];
449ccc2d1c4Sstsp };
450ccc2d1c4Sstsp 
451ccc2d1c4Sstsp static inline struct iwm_rxba_data *
iwm_rxba_data_from_reorder_buf(struct iwm_reorder_buffer * buf)452ccc2d1c4Sstsp iwm_rxba_data_from_reorder_buf(struct iwm_reorder_buffer *buf)
453ccc2d1c4Sstsp {
454ccc2d1c4Sstsp 	return (void *)((uint8_t *)buf -
455ccc2d1c4Sstsp 			offsetof(struct iwm_rxba_data, reorder_buf));
456ccc2d1c4Sstsp }
457ccc2d1c4Sstsp 
458ccc2d1c4Sstsp /**
459ccc2d1c4Sstsp  * struct iwm_rxq_dup_data - per station per rx queue data
460ccc2d1c4Sstsp  * @last_seq: last sequence per tid for duplicate packet detection
461ccc2d1c4Sstsp  * @last_sub_frame: last subframe packet
462ccc2d1c4Sstsp  */
463ccc2d1c4Sstsp struct iwm_rxq_dup_data {
464ccc2d1c4Sstsp 	uint16_t last_seq[IWM_MAX_TID_COUNT + 1];
465ccc2d1c4Sstsp 	uint8_t last_sub_frame[IWM_MAX_TID_COUNT + 1];
466ccc2d1c4Sstsp };
467ccc2d1c4Sstsp 
468bdd76655Sstsp struct iwm_ba_task_data {
469bdd76655Sstsp 	uint32_t		start_tidmask;
470bdd76655Sstsp 	uint32_t		stop_tidmask;
471bdd76655Sstsp };
472bdd76655Sstsp 
473e8078fe0Sstsp struct iwm_softc {
474e8078fe0Sstsp 	struct device sc_dev;
475e8078fe0Sstsp 	struct ieee80211com sc_ic;
476e8078fe0Sstsp 	int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int);
477e8078fe0Sstsp 	int sc_newstate_pending;
478f6c92c11Sstsp 	int attached;
479e8078fe0Sstsp 
480e8078fe0Sstsp 	struct ieee80211_amrr sc_amrr;
481e8078fe0Sstsp 	struct timeout sc_calib_to;
482af0046d8Sstsp 	struct timeout sc_led_blink_to;
483e8078fe0Sstsp 
484085456faSstsp 	struct task		init_task; /* NB: not reference-counted */
485085456faSstsp 	struct refcnt		task_refs;
486f5a52199Sstsp 	struct task		newstate_task;
487f5a52199Sstsp 	enum ieee80211_state	ns_nstate;
488f5a52199Sstsp 	int			ns_arg;
489b14235ddSphessler 
490d1ea7b21Sstsp 	/* Task for firmware BlockAck setup/teardown and its arguments. */
491d1ea7b21Sstsp 	struct task		ba_task;
492bdd76655Sstsp 	struct iwm_ba_task_data	ba_rx;
493bdd76655Sstsp 	struct iwm_ba_task_data	ba_tx;
494d1ea7b21Sstsp 
49509268e1fSstsp 	/* Task for ERP/HT prot/slot-time/EDCA updates. */
49609268e1fSstsp 	struct task		mac_ctxt_task;
497cb2109bfSstsp 
498880afff8Sstsp 	/* Task for HT 20/40 MHz channel width updates. */
499880afff8Sstsp 	struct task		phy_ctxt_task;
500880afff8Sstsp 
501e8078fe0Sstsp 	bus_space_tag_t sc_st;
502e8078fe0Sstsp 	bus_space_handle_t sc_sh;
503e8078fe0Sstsp 	bus_size_t sc_sz;
504e8078fe0Sstsp 	bus_dma_tag_t sc_dmat;
505e8078fe0Sstsp 	pci_chipset_tag_t sc_pct;
506e8078fe0Sstsp 	pcitag_t sc_pcitag;
507e8078fe0Sstsp 	const void *sc_ih;
50830289ebaSpatrick 	int sc_msix;
509e8078fe0Sstsp 
510e8078fe0Sstsp 	/* TX scheduler rings. */
511e8078fe0Sstsp 	struct iwm_dma_info		sched_dma;
512e8078fe0Sstsp 	uint32_t			sched_base;
513e8078fe0Sstsp 
514e8078fe0Sstsp 	/* TX/RX rings. */
51503445d8cSstsp 	struct iwm_tx_ring txq[IWM_MAX_QUEUES];
516e8078fe0Sstsp 	struct iwm_rx_ring rxq;
517e8078fe0Sstsp 	int qfullmsk;
518bdd76655Sstsp 	int qenablemsk;
519ac3b7227Sstsp 	int cmdqid;
520e8078fe0Sstsp 
521e8078fe0Sstsp 	int sc_sf_state;
522e8078fe0Sstsp 
523e8078fe0Sstsp 	/* ICT table. */
524e8078fe0Sstsp 	struct iwm_dma_info	ict_dma;
525e8078fe0Sstsp 	int			ict_cur;
526e8078fe0Sstsp 
527e8078fe0Sstsp 	int sc_hw_rev;
5280e4c2833Sstsp #define IWM_SILICON_A_STEP	0
5290e4c2833Sstsp #define IWM_SILICON_B_STEP	1
5300e4c2833Sstsp #define IWM_SILICON_C_STEP	2
5310e4c2833Sstsp #define IWM_SILICON_D_STEP	3
532e8078fe0Sstsp 	int sc_hw_id;
5330e4c2833Sstsp 	int sc_device_family;
5340e4c2833Sstsp #define IWM_DEVICE_FAMILY_7000	1
5350e4c2833Sstsp #define IWM_DEVICE_FAMILY_8000	2
5363287dca4Sstsp #define IWM_DEVICE_FAMILY_9000	3
537e8078fe0Sstsp 
538e8078fe0Sstsp 	struct iwm_dma_info kw_dma;
539e8078fe0Sstsp 	struct iwm_dma_info fw_dma;
540e8078fe0Sstsp 
541e8078fe0Sstsp 	int sc_fw_chunk_done;
542e8078fe0Sstsp 	int sc_init_complete;
543626e1a05Sstsp #define IWM_INIT_COMPLETE	0x01
544626e1a05Sstsp #define IWM_CALIB_COMPLETE	0x02
545e8078fe0Sstsp 
546e8078fe0Sstsp 	struct iwm_ucode_status sc_uc;
547e8078fe0Sstsp 	enum iwm_ucode_type sc_uc_current;
54888a9fda3Sstsp 	char sc_fwver[32];
549e8078fe0Sstsp 
550e8078fe0Sstsp 	int sc_capaflags;
551e8078fe0Sstsp 	int sc_capa_max_probe_len;
55288a9fda3Sstsp 	int sc_capa_n_scan_channels;
55395a45cb0Sstsp 	uint8_t sc_ucode_api[howmany(IWM_NUM_UCODE_TLV_API, NBBY)];
55488a9fda3Sstsp 	uint8_t sc_enabled_capa[howmany(IWM_NUM_UCODE_TLV_CAPA, NBBY)];
555bf5c331bSstsp #define IWM_MAX_FW_CMD_VERSIONS	64
556bf5c331bSstsp 	struct iwm_fw_cmd_version cmd_versions[IWM_MAX_FW_CMD_VERSIONS];
557bf5c331bSstsp 	int n_cmd_versions;
558e8078fe0Sstsp 
559e8078fe0Sstsp 	int sc_intmask;
560e8078fe0Sstsp 	int sc_flags;
561e8078fe0Sstsp 
56230289ebaSpatrick 	uint32_t sc_fh_init_mask;
56330289ebaSpatrick 	uint32_t sc_hw_init_mask;
56430289ebaSpatrick 	uint32_t sc_fh_mask;
56530289ebaSpatrick 	uint32_t sc_hw_mask;
56630289ebaSpatrick 
567e8078fe0Sstsp 	/*
568e8078fe0Sstsp 	 * So why do we need a separate stopped flag and a generation?
5694b1a56afSjsg 	 * the former protects the device from issuing commands when it's
570e8078fe0Sstsp 	 * stopped (duh).  The latter protects against race from a very
571e8078fe0Sstsp 	 * fast stop/unstop cycle where threads waiting for responses do
572e8078fe0Sstsp 	 * not have a chance to run in between.  Notably: we want to stop
573e8078fe0Sstsp 	 * the device from interrupt context when it craps out, so we
5744b1a56afSjsg 	 * don't have the luxury of waiting for quiescence.
575e8078fe0Sstsp 	 */
576e8078fe0Sstsp 	int sc_generation;
577e8078fe0Sstsp 
57830552ff4Sstsp 	struct rwlock ioctl_rwl;
57930552ff4Sstsp 
580e8078fe0Sstsp 	int sc_cap_off; /* PCIe caps */
581e8078fe0Sstsp 
582e8078fe0Sstsp 	const char *sc_fwname;
583e8078fe0Sstsp 	bus_size_t sc_fwdmasegsz;
5849df18847Sstsp 	size_t sc_nvm_max_section_size;
585e8078fe0Sstsp 	struct iwm_fw_info sc_fw;
5867a10236fSstsp 	uint32_t sc_fw_phy_config;
5877a10236fSstsp 	uint32_t sc_extra_phy_config;
588e8078fe0Sstsp 	struct iwm_tlv_calib_ctrl sc_default_calib[IWM_UCODE_TYPE_MAX];
589e8078fe0Sstsp 
590e8078fe0Sstsp 	struct iwm_nvm_data sc_nvm;
591e8078fe0Sstsp 	struct iwm_phy_db sc_phy_db;
592e8078fe0Sstsp 
593e8078fe0Sstsp 	struct iwm_bf_data sc_bf;
594e8078fe0Sstsp 
595f2e52126Sstsp 	int sc_tx_timer[IWM_MAX_QUEUES];
596d1ea7b21Sstsp 	int sc_rx_ba_sessions;
597bdd76655Sstsp 	int tx_ba_queue_mask;
598e8078fe0Sstsp 
59903403584Sstsp 	struct task bgscan_done_task;
60003403584Sstsp 	struct ieee80211_node_switch_bss_arg *bgscan_unref_arg;
60103403584Sstsp 	size_t	bgscan_unref_arg_size;
60203403584Sstsp 
603e8078fe0Sstsp 	int sc_scan_last_antenna;
604e8078fe0Sstsp 
605e8078fe0Sstsp 	int sc_fixed_ridx;
606e8078fe0Sstsp 
607e8078fe0Sstsp 	int sc_staid;
608e8078fe0Sstsp 	int sc_nodecolor;
609e8078fe0Sstsp 
610ade4b715Sstsp 	uint8_t *sc_cmd_resp_pkt[IWM_TX_RING_COUNT];
611ade4b715Sstsp 	size_t sc_cmd_resp_len[IWM_TX_RING_COUNT];
61289b6f1f1Sstsp 	int sc_nic_locks;
613e8078fe0Sstsp 
6145d0f4097Sstsp 	struct taskq *sc_nswq;
615e8078fe0Sstsp 
616e8078fe0Sstsp 	struct iwm_rx_phy_info sc_last_phy_info;
617e8078fe0Sstsp 	int sc_ampdu_ref;
618ccc2d1c4Sstsp #define IWM_MAX_BAID	32
619ccc2d1c4Sstsp 	struct iwm_rxba_data sc_rxba_data[IWM_MAX_BAID];
620e8078fe0Sstsp 
6217fd96644Sstsp 	uint32_t sc_time_event_uid;
6227fd96644Sstsp 
623e8078fe0Sstsp 	/* phy contexts.  we only use the first one */
62403445d8cSstsp 	struct iwm_phy_ctxt sc_phyctxt[IWM_NUM_PHY_CTX];
625e8078fe0Sstsp 
626e8078fe0Sstsp 	struct iwm_notif_statistics sc_stats;
6278d0ee892Sstsp 	int sc_noise;
6288d0ee892Sstsp 
629b8ee8deaSjsg 	int host_interrupt_operation_mode;
63057c862fbSstsp 	int sc_ltr_enabled;
631857796daSstsp 	enum iwm_nvm_type nvm_type;
632b8ee8deaSjsg 
6333287dca4Sstsp 	int sc_mqrx_supported;
6343287dca4Sstsp 	int sc_integrated;
635ce74846cSstsp 	int sc_ltr_delay;
636ce74846cSstsp 	int sc_xtal_latency;
637ce74846cSstsp 	int sc_low_latency_xtal;
6383287dca4Sstsp 
63949c89610Sstsp 	/*
64049c89610Sstsp 	 * Paging parameters - All of the parameters should be set by the
64149c89610Sstsp 	 * opmode when paging is enabled
64249c89610Sstsp 	 */
64349c89610Sstsp 	struct iwm_fw_paging fw_paging_db[IWM_NUM_OF_FW_PAGING_BLOCKS];
64449c89610Sstsp 	uint16_t num_of_paging_blk;
64549c89610Sstsp 	uint16_t num_of_pages_in_last_blk;
64649c89610Sstsp 
6478d0ee892Sstsp #if NBPFILTER > 0
6488d0ee892Sstsp 	caddr_t			sc_drvbpf;
6498d0ee892Sstsp 
6508d0ee892Sstsp 	union {
6518d0ee892Sstsp 		struct iwm_rx_radiotap_header th;
6528d0ee892Sstsp 		uint8_t	pad[IEEE80211_RADIOTAP_HDRLEN];
6538d0ee892Sstsp 	} sc_rxtapu;
6548d0ee892Sstsp #define sc_rxtap	sc_rxtapu.th
6558d0ee892Sstsp 	int			sc_rxtap_len;
6568d0ee892Sstsp 
6578d0ee892Sstsp 	union {
6588d0ee892Sstsp 		struct iwm_tx_radiotap_header th;
6598d0ee892Sstsp 		uint8_t	pad[IEEE80211_RADIOTAP_HDRLEN];
6608d0ee892Sstsp 	} sc_txtapu;
6618d0ee892Sstsp #define sc_txtap	sc_txtapu.th
6628d0ee892Sstsp 	int			sc_txtap_len;
6638d0ee892Sstsp #endif
664e8078fe0Sstsp };
665e8078fe0Sstsp 
666e8078fe0Sstsp struct iwm_node {
667e8078fe0Sstsp 	struct ieee80211_node in_ni;
66803445d8cSstsp 	struct iwm_phy_ctxt *in_phyctxt;
66980a9ea70Sstsp 	uint8_t in_macaddr[ETHER_ADDR_LEN];
670e8078fe0Sstsp 
671e8078fe0Sstsp 	uint16_t in_id;
672e8078fe0Sstsp 	uint16_t in_color;
673e8078fe0Sstsp 
674e8078fe0Sstsp 	struct ieee80211_amrr_node in_amn;
675d6766b2aSstsp 	struct ieee80211_ra_node in_rn;
67659aafb1aSstsp 	struct ieee80211_ra_vht_node in_rn_vht;
677d6766b2aSstsp 	int lq_rate_mismatch;
678ccc2d1c4Sstsp 
679ccc2d1c4Sstsp 	struct iwm_rxq_dup_data dup_data;
680bdd76655Sstsp 
681bdd76655Sstsp 	/* For use with the ADD_STA command. */
682bdd76655Sstsp 	uint32_t tfd_queue_msk;
683bdd76655Sstsp 	uint16_t tid_disable_ampdu;
684e8078fe0Sstsp };
685e8078fe0Sstsp #define IWM_STATION_ID 0
68688a9fda3Sstsp #define IWM_AUX_STA_ID 1
687ea685b82Sstsp #define IWM_MONITOR_STA_ID 2
688e8078fe0Sstsp 
689e8078fe0Sstsp #define IWM_ICT_SIZE		4096
690e8078fe0Sstsp #define IWM_ICT_COUNT		(IWM_ICT_SIZE / sizeof (uint32_t))
691e8078fe0Sstsp #define IWM_ICT_PADDR_SHIFT	12
692