1 /* $OpenBSD: if_iwmreg.h,v 1.19 2016/09/20 11:46:09 stsp Exp $ */ 2 3 /****************************************************************************** 4 * 5 * This file is provided under a dual BSD/GPLv2 license. When using or 6 * redistributing this file, you may do so under either license. 7 * 8 * GPL LICENSE SUMMARY 9 * 10 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24 * USA 25 * 26 * The full GNU General Public License is included in this distribution 27 * in the file called COPYING. 28 * 29 * Contact Information: 30 * Intel Linux Wireless <ilw@linux.intel.com> 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 * 33 * BSD LICENSE 34 * 35 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 42 * * Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * * Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in 46 * the documentation and/or other materials provided with the 47 * distribution. 48 * * Neither the name Intel Corporation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 *****************************************************************************/ 65 66 /* 67 * CSR (control and status registers) 68 * 69 * CSR registers are mapped directly into PCI bus space, and are accessible 70 * whenever platform supplies power to device, even when device is in 71 * low power states due to driver-invoked device resets 72 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 73 * 74 * Use iwl_write32() and iwl_read32() family to access these registers; 75 * these provide simple PCI bus access, without waking up the MAC. 76 * Do not use iwl_write_direct32() family for these registers; 77 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 78 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 79 * the CSR registers. 80 * 81 * NOTE: Device does need to be awake in order to read this memory 82 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 83 */ 84 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 85 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 86 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 87 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 88 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 89 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 90 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 91 #define IWM_CSR_GP_CNTRL (0x024) 92 93 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 94 #define IWM_CSR_INT_PERIODIC_REG (0x005) 95 96 /* 97 * Hardware revision info 98 * Bit fields: 99 * 31-16: Reserved 100 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 101 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 102 * 1-0: "Dash" (-) value, as in A-1, etc. 103 */ 104 #define IWM_CSR_HW_REV (0x028) 105 106 /* 107 * EEPROM and OTP (one-time-programmable) memory reads 108 * 109 * NOTE: Device must be awake, initialized via apm_ops.init(), 110 * in order to read. 111 */ 112 #define IWM_CSR_EEPROM_REG (0x02c) 113 #define IWM_CSR_EEPROM_GP (0x030) 114 #define IWM_CSR_OTP_GP_REG (0x034) 115 116 #define IWM_CSR_GIO_REG (0x03C) 117 #define IWM_CSR_GP_UCODE_REG (0x048) 118 #define IWM_CSR_GP_DRIVER_REG (0x050) 119 120 /* 121 * UCODE-DRIVER GP (general purpose) mailbox registers. 122 * SET/CLR registers set/clear bit(s) if "1" is written. 123 */ 124 #define IWM_CSR_UCODE_DRV_GP1 (0x054) 125 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 126 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 127 #define IWM_CSR_UCODE_DRV_GP2 (0x060) 128 129 #define IWM_CSR_MBOX_SET_REG (0x088) 130 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 131 132 #define IWM_CSR_LED_REG (0x094) 133 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 134 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 135 136 137 /* GIO Chicken Bits (PCI Express bus link power management) */ 138 #define IWM_CSR_GIO_CHICKEN_BITS (0x100) 139 140 /* Analog phase-lock-loop configuration */ 141 #define IWM_CSR_ANA_PLL_CFG (0x20c) 142 143 /* 144 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 145 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 146 * See also IWM_CSR_HW_REV register. 147 * Bit fields: 148 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 149 * 1-0: "Dash" (-) value, as in C-1, etc. 150 */ 151 #define IWM_CSR_HW_REV_WA_REG (0x22C) 152 153 #define IWM_CSR_DBG_HPET_MEM_REG (0x240) 154 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 155 156 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 157 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 158 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 159 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 160 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 161 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 162 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 163 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 164 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 165 166 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 167 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 168 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 169 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 170 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 171 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 172 173 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 174 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 175 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 176 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 177 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 178 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 179 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 180 181 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 182 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 183 184 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 185 * acknowledged (reset) by host writing "1" to flagged bits. */ 186 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 187 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 188 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 189 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 190 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 191 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 192 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 193 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 194 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 195 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 196 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 197 198 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 199 IWM_CSR_INT_BIT_HW_ERR | \ 200 IWM_CSR_INT_BIT_FH_TX | \ 201 IWM_CSR_INT_BIT_SW_ERR | \ 202 IWM_CSR_INT_BIT_RF_KILL | \ 203 IWM_CSR_INT_BIT_SW_RX | \ 204 IWM_CSR_INT_BIT_WAKEUP | \ 205 IWM_CSR_INT_BIT_ALIVE | \ 206 IWM_CSR_INT_BIT_RX_PERIODIC) 207 208 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 209 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 210 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 211 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 212 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 213 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 214 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 215 216 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 217 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 218 IWM_CSR_FH_INT_BIT_RX_CHNL0) 219 220 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 221 IWM_CSR_FH_INT_BIT_TX_CHNL0) 222 223 /* GPIO */ 224 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 225 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 226 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 227 228 /* RESET */ 229 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 230 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 231 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 232 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 233 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 234 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 235 236 /* 237 * GP (general purpose) CONTROL REGISTER 238 * Bit fields: 239 * 27: HW_RF_KILL_SW 240 * Indicates state of (platform's) hardware RF-Kill switch 241 * 26-24: POWER_SAVE_TYPE 242 * Indicates current power-saving mode: 243 * 000 -- No power saving 244 * 001 -- MAC power-down 245 * 010 -- PHY (radio) power-down 246 * 011 -- Error 247 * 9-6: SYS_CONFIG 248 * Indicates current system configuration, reflecting pins on chip 249 * as forced high/low by device circuit board. 250 * 4: GOING_TO_SLEEP 251 * Indicates MAC is entering a power-saving sleep power-down. 252 * Not a good time to access device-internal resources. 253 * 3: MAC_ACCESS_REQ 254 * Host sets this to request and maintain MAC wakeup, to allow host 255 * access to device-internal resources. Host must wait for 256 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 257 * device registers. 258 * 2: INIT_DONE 259 * Host sets this to put device into fully operational D0 power mode. 260 * Host resets this after SW_RESET to put device into low power mode. 261 * 0: MAC_CLOCK_READY 262 * Indicates MAC (ucode processor, etc.) is powered up and can run. 263 * Internal resources are accessible. 264 * NOTE: This does not indicate that the processor is actually running. 265 * NOTE: This does not indicate that device has completed 266 * init or post-power-down restore of internal SRAM memory. 267 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 268 * SRAM is restored and uCode is in normal operation mode. 269 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 270 * do not need to save/restore it. 271 * NOTE: After device reset, this bit remains "0" until host sets 272 * INIT_DONE 273 */ 274 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 275 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 276 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 277 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 278 279 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 280 281 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 282 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 283 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 284 285 286 /* HW REV */ 287 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 288 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 289 290 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 291 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 292 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 293 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 294 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 295 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 296 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 297 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 298 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 299 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 300 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 301 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 302 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 303 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 304 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 305 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 306 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 307 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 308 309 /* EEPROM REG */ 310 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 311 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 312 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 313 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 314 315 /* EEPROM GP */ 316 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 317 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 318 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 319 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 320 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 321 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 322 323 /* One-time-programmable memory general purpose reg */ 324 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 325 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 326 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 327 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 328 329 /* GP REG */ 330 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 331 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 332 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 333 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 334 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 335 336 337 /* CSR GIO */ 338 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 339 340 /* 341 * UCODE-DRIVER GP (general purpose) mailbox register 1 342 * Host driver and uCode write and/or read this register to communicate with 343 * each other. 344 * Bit fields: 345 * 4: UCODE_DISABLE 346 * Host sets this to request permanent halt of uCode, same as 347 * sending CARD_STATE command with "halt" bit set. 348 * 3: CT_KILL_EXIT 349 * Host sets this to request exit from CT_KILL state, i.e. host thinks 350 * device temperature is low enough to continue normal operation. 351 * 2: CMD_BLOCKED 352 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 353 * to release uCode to clear all Tx and command queues, enter 354 * unassociated mode, and power down. 355 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 356 * 1: SW_BIT_RFKILL 357 * Host sets this when issuing CARD_STATE command to request 358 * device sleep. 359 * 0: MAC_SLEEP 360 * uCode sets this when preparing a power-saving power-down. 361 * uCode resets this when power-up is complete and SRAM is sane. 362 * NOTE: device saves internal SRAM data to host when powering down, 363 * and must restore this data after powering back up. 364 * MAC_SLEEP is the best indication that restore is complete. 365 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 366 * do not need to save/restore it. 367 */ 368 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 369 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 370 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 371 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 372 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 373 374 /* GP Driver */ 375 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 376 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 377 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 378 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 379 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 380 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 381 382 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 383 384 /* GIO Chicken Bits (PCI Express bus link power management) */ 385 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 386 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 387 388 /* LED */ 389 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 390 #define IWM_CSR_LED_REG_TURN_ON (0x60) 391 #define IWM_CSR_LED_REG_TURN_OFF (0x20) 392 393 /* ANA_PLL */ 394 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 395 396 /* HPET MEM debug */ 397 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 398 399 /* DRAM INT TABLE */ 400 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 401 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 402 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 403 404 /* SECURE boot registers */ 405 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 406 #define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP 0x00000001 407 #define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ 0x00000002 408 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 409 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 410 #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS 0x00000003 411 #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED 0x00000002 412 #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS 0x00000004 413 #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL 0x00000008 414 #define IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL 0x00000010 415 416 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0 417 #define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70 418 419 #define IWM_LMPM_CPU_UCODE_LOADING_STARTED 0x00000001 420 #define IWM_LMPM_CPU_HDRS_LOADING_COMPLETED 0x00000003 421 #define IWM_LMPM_CPU_UCODE_LOADING_COMPLETED 0x00000007 422 #define IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED 0x000000F8 423 #define IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK 0x0000FF00 424 425 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 426 427 #define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38 428 #define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c 429 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 430 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 431 432 #define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000 433 #define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000 434 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 435 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 436 437 #define IWM_CSR_SECURE_TIME_OUT (100) 438 439 /* extended range in FW SRAM */ 440 #define IWM_FW_MEM_EXTENDED_START 0x40000 441 #define IWM_FW_MEM_EXTENDED_END 0x57FFF 442 443 /* FW chicken bits */ 444 #define IWM_LMPM_CHICK 0xa01ff8 445 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 446 447 #define IWM_FH_TCSR_0_REG0 (0x1D00) 448 449 /* 450 * HBUS (Host-side Bus) 451 * 452 * HBUS registers are mapped directly into PCI bus space, but are used 453 * to indirectly access device's internal memory or registers that 454 * may be powered-down. 455 * 456 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 457 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 458 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 459 * internal resources. 460 * 461 * Do not use iwl_write32()/iwl_read32() family to access these registers; 462 * these provide only simple PCI bus access, without waking up the MAC. 463 */ 464 #define IWM_HBUS_BASE (0x400) 465 466 /* 467 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 468 * structures, error log, event log, verifying uCode load). 469 * First write to address register, then read from or write to data register 470 * to complete the job. Once the address register is set up, accesses to 471 * data registers auto-increment the address by one dword. 472 * Bit usage for address registers (read or write): 473 * 0-31: memory address within device 474 */ 475 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 476 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 477 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 478 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 479 480 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 481 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 482 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 483 484 /* 485 * Registers for accessing device's internal peripheral registers 486 * (e.g. SCD, BSM, etc.). First write to address register, 487 * then read from or write to data register to complete the job. 488 * Bit usage for address registers (read or write): 489 * 0-15: register address (offset) within device 490 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 491 */ 492 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 493 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 494 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 495 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 496 497 /* enable the ID buf for read */ 498 #define IWM_WFPM_PS_CTL_CLR 0xa0300c 499 #define IWM_WFMP_MAC_ADDR_0 0xa03080 500 #define IWM_WFMP_MAC_ADDR_1 0xa03084 501 #define IWM_LMPM_PMG_EN 0xa01cec 502 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 503 #define IWM_RFIC_REG_RD 0xad0470 504 #define IWM_WFPM_CTRL_REG 0xa03030 505 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 506 #define IWM_ENABLE_WFPM 0x80000000 507 508 #define IWM_AUX_MISC_REG 0xa200b0 509 #define IWM_HW_STEP_LOCATION_BITS 24 510 511 #define IWM_AUX_MISC_MASTER1_EN 0xa20818 512 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 513 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 514 #define IWM_RSA_ENABLE 0xa24b08 515 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 516 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 517 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 518 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 519 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088 520 #define IWM_SB_CPU_1_STATUS 0xa01e30 521 #define IWM_SB_CPU_2_STATUS 0Xa01e34 522 523 /* Used to enable DBGM */ 524 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 525 526 /* 527 * Per-Tx-queue write pointer (index, really!) 528 * Indicates index to next TFD that driver will fill (1 past latest filled). 529 * Bit usage: 530 * 0-7: queue write index 531 * 11-8: queue selector 532 */ 533 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 534 535 /********************************************************** 536 * CSR values 537 **********************************************************/ 538 /* 539 * host interrupt timeout value 540 * used with setting interrupt coalescing timer 541 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 542 * 543 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 544 */ 545 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 546 #define IWM_HOST_INT_TIMEOUT_DEF (0x40) 547 #define IWM_HOST_INT_TIMEOUT_MIN (0x0) 548 #define IWM_HOST_INT_OPER_MODE (1 << 31) 549 550 /***************************************************************************** 551 * 7000/3000 series SHR DTS addresses * 552 *****************************************************************************/ 553 554 /* Diode Results Register Structure: */ 555 #define IWM_DTS_DIODE_REG_DIG_VAL 0x000000FF /* bits [7:0] */ 556 #define IWM_DTS_DIODE_REG_VREF_LOW 0x0000FF00 /* bits [15:8] */ 557 #define IWM_DTS_DIODE_REG_VREF_HIGH 0x00FF0000 /* bits [23:16] */ 558 #define IWM_DTS_DIODE_REG_VREF_ID 0x03000000 /* bits [25:24] */ 559 #define IWM_DTS_DIODE_REG_PASS_ONCE 0x80000000 /* bits [31:31] */ 560 #define IWM_DTS_DIODE_REG_FLAGS_MSK 0xFF000000 /* bits [31:24] */ 561 /* Those are the masks INSIDE the flags bit-field: */ 562 #define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS 0 563 #define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID 0x00000003 /* bits [1:0] */ 564 #define IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS 7 565 #define IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE 0x00000080 /* bits [7:7] */ 566 567 /** 568 * uCode API flags 569 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 570 * was a separate TLV but moved here to save space. 571 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 572 * treats good CRC threshold as a boolean 573 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 574 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 575 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 576 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 577 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 578 * offload profile config command. 579 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 580 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 581 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 582 * (rather than two) IPv6 addresses 583 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 584 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 585 * from the probe request template. 586 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 587 * connection when going back to D0 588 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 589 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 590 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 591 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 592 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 593 * containing CAM (Continuous Active Mode) indication. 594 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 595 * single bound interface). 596 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 597 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 598 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 599 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 600 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 601 * 602 */ 603 #define IWM_UCODE_TLV_FLAGS_PAN (1 << 0) 604 #define IWM_UCODE_TLV_FLAGS_NEWSCAN (1 << 1) 605 #define IWM_UCODE_TLV_FLAGS_MFP (1 << 2) 606 #define IWM_UCODE_TLV_FLAGS_P2P (1 << 3) 607 #define IWM_UCODE_TLV_FLAGS_DW_BC_TABLE (1 << 4) 608 #define IWM_UCODE_TLV_FLAGS_NEWBT_COEX (1 << 5) 609 #define IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT (1 << 6) 610 #define IWM_UCODE_TLV_FLAGS_SHORT_BL (1 << 7) 611 #define IWM_UCODE_TLV_FLAGS_RX_ENERGY_API (1 << 8) 612 #define IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 (1 << 9) 613 #define IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS (1 << 10) 614 #define IWM_UCODE_TLV_FLAGS_BF_UPDATED (1 << 11) 615 #define IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID (1 << 12) 616 #define IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API (1 << 14) 617 #define IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL (1 << 15) 618 #define IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE (1 << 16) 619 #define IWM_UCODE_TLV_FLAGS_SCHED_SCAN (1 << 17) 620 #define IWM_UCODE_TLV_FLAGS_STA_KEY_CMD (1 << 19) 621 #define IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD (1 << 20) 622 #define IWM_UCODE_TLV_FLAGS_P2P_PS (1 << 21) 623 #define IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM (1 << 22) 624 #define IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM (1 << 23) 625 #define IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT (1 << 24) 626 #define IWM_UCODE_TLV_FLAGS_EBS_SUPPORT (1 << 25) 627 #define IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD (1 << 26) 628 #define IWM_UCODE_TLV_FLAGS_BCAST_FILTERING (1 << 29) 629 #define IWM_UCODE_TLV_FLAGS_GO_UAPSD (1 << 30) 630 #define IWM_UCODE_TLV_FLAGS_LTE_COEX (1 << 31) 631 632 #define IWM_UCODE_TLV_FLAG_BITS \ 633 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 634 635 /** 636 * uCode TLV api 637 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 638 * longer than the passive one, which is essential for fragmented scan. 639 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 640 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 641 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 642 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 643 * instead of 3. 644 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 645 * (command version 3) that supports per-chain limits 646 * 647 * @IWM_NUM_UCODE_TLV_API: number of bits used 648 */ 649 #define IWM_UCODE_TLV_API_FRAGMENTED_SCAN (1 << 8) 650 #define IWM_UCODE_TLV_API_WIFI_MCC_UPDATE (1 << 9) 651 #define IWM_UCODE_TLV_API_WIDE_CMD_HDR (1 << 14) 652 #define IWM_UCODE_TLV_API_LQ_SS_PARAMS (1 << 18) 653 #define IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY (1 << 24) 654 #define IWM_UCODE_TLV_API_TX_POWER_CHAIN (1 << 27) 655 656 #define IWM_NUM_UCODE_TLV_API = 32 657 658 #define IWM_UCODE_TLV_API_BITS \ 659 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 660 661 /** 662 * uCode capabilities 663 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 664 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 665 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 666 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 667 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 668 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 669 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 670 * tx power value into TPC Report action frame and Link Measurement Report 671 * action frame 672 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 673 * channel in DS parameter set element in probe requests. 674 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 675 * probe requests. 676 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 677 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 678 * which also implies support for the scheduler configuration command 679 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 680 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 681 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 682 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 683 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 684 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 685 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 686 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 687 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 688 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 689 * sources for the MCC. This TLV bit is a future replacement to 690 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 691 * is supported. 692 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 693 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 694 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 695 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 696 * 0=no support) 697 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 698 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 699 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 700 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 701 * antenna the beacon should be transmitted 702 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 703 * from AP and will send it upon d0i3 exit. 704 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 705 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 706 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 707 * thresholds reporting 708 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 709 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 710 * regular image. 711 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 712 * memory addresses from the firmware. 713 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 714 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 715 * 0=no support) 716 * 717 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 718 */ 719 #define IWM_UCODE_TLV_CAPA_D0I3_SUPPORT 0 720 #define IWM_UCODE_TLV_CAPA_LAR_SUPPORT 1 721 #define IWM_UCODE_TLV_CAPA_UMAC_SCAN 2 722 #define IWM_UCODE_TLV_CAPA_BEAMFORMER 3 723 #define IWM_UCODE_TLV_CAPA_TOF_SUPPORT 5 724 #define IWM_UCODE_TLV_CAPA_TDLS_SUPPORT 6 725 #define IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT 8 726 #define IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT 9 727 #define IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT 10 728 #define IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT 11 729 #define IWM_UCODE_TLV_CAPA_DQA_SUPPORT 12 730 #define IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH 13 731 #define IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG 17 732 #define IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT 18 733 #define IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT 19 734 #define IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT 20 735 #define IWM_UCODE_TLV_CAPA_CSUM_SUPPORT 21 736 #define IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS 22 737 #define IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD 26 738 #define IWM_UCODE_TLV_CAPA_BT_COEX_PLCR 28 739 #define IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC 29 740 #define IWM_UCODE_TLV_CAPA_BT_COEX_RRC 30 741 #define IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT 31 742 #define IWM_UCODE_TLV_CAPA_NAN_SUPPORT 34 743 #define IWM_UCODE_TLV_CAPA_UMAC_UPLOAD 35 744 #define IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE 64 745 #define IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS 65 746 #define IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT 67 747 #define IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT 68 748 #define IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION 71 749 #define IWM_UCODE_TLV_CAPA_BEACON_STORING 72 750 #define IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 73 751 #define IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW 74 752 #define IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT 75 753 #define IWM_UCODE_TLV_CAPA_CTDP_SUPPORT 76 754 #define IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED 77 755 #define IWM_UCODE_TLV_CAPA_LMAC_UPLOAD 79 756 #define IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 80 757 #define IWM_UCODE_TLV_CAPA_LQM_SUPPORT 81 758 759 #define IWM_NUM_UCODE_TLV_CAPA 128 760 761 /* The default calibrate table size if not specified by firmware file */ 762 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 763 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 764 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 765 766 /* The default max probe length if not specified by the firmware file */ 767 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200 768 769 /* 770 * For 16.0 uCode and above, there is no differentiation between sections, 771 * just an offset to the HW address. 772 */ 773 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 774 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 775 776 /* uCode version contains 4 values: Major/Minor/API/Serial */ 777 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 778 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 779 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 780 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 781 782 /* 783 * Calibration control struct. 784 * Sent as part of the phy configuration command. 785 * @flow_trigger: bitmap for which calibrations to perform according to 786 * flow triggers. 787 * @event_trigger: bitmap for which calibrations to perform according to 788 * event triggers. 789 */ 790 struct iwm_tlv_calib_ctrl { 791 uint32_t flow_trigger; 792 uint32_t event_trigger; 793 } __packed; 794 795 #define IWM_FW_PHY_CFG_RADIO_TYPE_POS 0 796 #define IWM_FW_PHY_CFG_RADIO_TYPE (0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS) 797 #define IWM_FW_PHY_CFG_RADIO_STEP_POS 2 798 #define IWM_FW_PHY_CFG_RADIO_STEP (0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS) 799 #define IWM_FW_PHY_CFG_RADIO_DASH_POS 4 800 #define IWM_FW_PHY_CFG_RADIO_DASH (0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS) 801 #define IWM_FW_PHY_CFG_TX_CHAIN_POS 16 802 #define IWM_FW_PHY_CFG_TX_CHAIN (0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS) 803 #define IWM_FW_PHY_CFG_RX_CHAIN_POS 20 804 #define IWM_FW_PHY_CFG_RX_CHAIN (0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS) 805 806 #define IWM_UCODE_MAX_CS 1 807 808 /** 809 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 810 * @cipher: a cipher suite selector 811 * @flags: cipher scheme flags (currently reserved for a future use) 812 * @hdr_len: a size of MPDU security header 813 * @pn_len: a size of PN 814 * @pn_off: an offset of pn from the beginning of the security header 815 * @key_idx_off: an offset of key index byte in the security header 816 * @key_idx_mask: a bit mask of key_idx bits 817 * @key_idx_shift: bit shift needed to get key_idx 818 * @mic_len: mic length in bytes 819 * @hw_cipher: a HW cipher index used in host commands 820 */ 821 struct iwm_fw_cipher_scheme { 822 uint32_t cipher; 823 uint8_t flags; 824 uint8_t hdr_len; 825 uint8_t pn_len; 826 uint8_t pn_off; 827 uint8_t key_idx_off; 828 uint8_t key_idx_mask; 829 uint8_t key_idx_shift; 830 uint8_t mic_len; 831 uint8_t hw_cipher; 832 } __packed; 833 834 /** 835 * struct iwm_fw_cscheme_list - a cipher scheme list 836 * @size: a number of entries 837 * @cs: cipher scheme entries 838 */ 839 struct iwm_fw_cscheme_list { 840 uint8_t size; 841 struct iwm_fw_cipher_scheme cs[]; 842 } __packed; 843 844 /* v1/v2 uCode file layout */ 845 struct iwm_ucode_header { 846 uint32_t ver; /* major/minor/API/serial */ 847 union { 848 struct { 849 uint32_t inst_size; /* bytes of runtime code */ 850 uint32_t data_size; /* bytes of runtime data */ 851 uint32_t init_size; /* bytes of init code */ 852 uint32_t init_data_size; /* bytes of init data */ 853 uint32_t boot_size; /* bytes of bootstrap code */ 854 uint8_t data[0]; /* in same order as sizes */ 855 } v1; 856 struct { 857 uint32_t build; /* build number */ 858 uint32_t inst_size; /* bytes of runtime code */ 859 uint32_t data_size; /* bytes of runtime data */ 860 uint32_t init_size; /* bytes of init code */ 861 uint32_t init_data_size; /* bytes of init data */ 862 uint32_t boot_size; /* bytes of bootstrap code */ 863 uint8_t data[0]; /* in same order as sizes */ 864 } v2; 865 } u; 866 }; 867 868 /* 869 * new TLV uCode file layout 870 * 871 * The new TLV file format contains TLVs, that each specify 872 * some piece of data. 873 */ 874 875 #define IWM_UCODE_TLV_INVALID 0 /* unused */ 876 #define IWM_UCODE_TLV_INST 1 877 #define IWM_UCODE_TLV_DATA 2 878 #define IWM_UCODE_TLV_INIT 3 879 #define IWM_UCODE_TLV_INIT_DATA 4 880 #define IWM_UCODE_TLV_BOOT 5 881 #define IWM_UCODE_TLV_PROBE_MAX_LEN 6 /* a uint32_t value */ 882 #define IWM_UCODE_TLV_PAN 7 883 #define IWM_UCODE_TLV_RUNT_EVTLOG_PTR 8 884 #define IWM_UCODE_TLV_RUNT_EVTLOG_SIZE 9 885 #define IWM_UCODE_TLV_RUNT_ERRLOG_PTR 10 886 #define IWM_UCODE_TLV_INIT_EVTLOG_PTR 11 887 #define IWM_UCODE_TLV_INIT_EVTLOG_SIZE 12 888 #define IWM_UCODE_TLV_INIT_ERRLOG_PTR 13 889 #define IWM_UCODE_TLV_ENHANCE_SENS_TBL 14 890 #define IWM_UCODE_TLV_PHY_CALIBRATION_SIZE 15 891 #define IWM_UCODE_TLV_WOWLAN_INST 16 892 #define IWM_UCODE_TLV_WOWLAN_DATA 17 893 #define IWM_UCODE_TLV_FLAGS 18 894 #define IWM_UCODE_TLV_SEC_RT 19 895 #define IWM_UCODE_TLV_SEC_INIT 20 896 #define IWM_UCODE_TLV_SEC_WOWLAN 21 897 #define IWM_UCODE_TLV_DEF_CALIB 22 898 #define IWM_UCODE_TLV_PHY_SKU 23 899 #define IWM_UCODE_TLV_SECURE_SEC_RT 24 900 #define IWM_UCODE_TLV_SECURE_SEC_INIT 25 901 #define IWM_UCODE_TLV_SECURE_SEC_WOWLAN 26 902 #define IWM_UCODE_TLV_NUM_OF_CPU 27 903 #define IWM_UCODE_TLV_CSCHEME 28 904 905 /* 906 * Following two are not in our base tag, but allow 907 * handling ucode version 9. 908 */ 909 #define IWM_UCODE_TLV_API_CHANGES_SET 29 910 #define IWM_UCODE_TLV_ENABLED_CAPABILITIES 30 911 #define IWM_UCODE_TLV_N_SCAN_CHANNELS 31 912 #define IWM_UCODE_TLV_PAGING 32 913 #define IWM_UCODE_TLV_SEC_RT_USNIFFER 34 914 #define IWM_UCODE_TLV_SDIO_ADMA_ADDR 35 915 #define IWM_UCODE_TLV_FW_VERSION 36 916 #define IWM_UCODE_TLV_FW_DBG_DEST 38 917 #define IWM_UCODE_TLV_FW_DBG_CONF 39 918 #define IWM_UCODE_TLV_FW_DBG_TRIGGER 40 919 #define IWM_UCODE_TLV_FW_GSCAN_CAPA 50 920 921 struct iwm_ucode_tlv { 922 uint32_t type; /* see above */ 923 uint32_t length; /* not including type/length fields */ 924 uint8_t data[0]; 925 }; 926 927 struct iwm_ucode_api { 928 uint32_t api_index; 929 uint32_t api_flags; 930 } __packed; 931 932 struct iwm_ucode_capa { 933 uint32_t api_index; 934 uint32_t api_capa; 935 } __packed; 936 937 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749 938 939 struct iwm_tlv_ucode_header { 940 /* 941 * The TLV style ucode header is distinguished from 942 * the v1/v2 style header by first four bytes being 943 * zero, as such is an invalid combination of 944 * major/minor/API/serial versions. 945 */ 946 uint32_t zero; 947 uint32_t magic; 948 uint8_t human_readable[64]; 949 uint32_t ver; /* major/minor/API/serial */ 950 uint32_t build; 951 uint64_t ignore; 952 /* 953 * The data contained herein has a TLV layout, 954 * see above for the TLV header and types. 955 * Note that each TLV is padded to a length 956 * that is a multiple of 4 for alignment. 957 */ 958 uint8_t data[0]; 959 }; 960 961 /* 962 * Registers in this file are internal, not PCI bus memory mapped. 963 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 964 */ 965 #define IWM_PRPH_BASE (0x00000) 966 #define IWM_PRPH_END (0xFFFFF) 967 968 /* APMG (power management) constants */ 969 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 970 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 971 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 972 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 973 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 974 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 975 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 976 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 977 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 978 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 979 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 980 981 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 982 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 983 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 984 985 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 986 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 987 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 988 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 989 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 990 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 991 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 992 993 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 994 995 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 996 997 /* Device system time */ 998 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 999 1000 /* Device NMI register */ 1001 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1002 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1003 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1004 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1005 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1006 1007 /* 1008 * Device reset for family 8000 1009 * write to bit 24 in order to reset the CPU 1010 */ 1011 #define IWM_RELEASE_CPU_RESET 0x300c 1012 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1013 1014 1015 /***************************************************************************** 1016 * 7000/3000 series SHR DTS addresses * 1017 *****************************************************************************/ 1018 1019 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1020 #define IWM_DTSC_CFG_MODE (0x00a10604) 1021 #define IWM_DTSC_VREF_AVG (0x00a10648) 1022 #define IWM_DTSC_VREF5_AVG (0x00a1064c) 1023 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1024 #define IWM_DTSC_PTAT_AVG (0x00a10650) 1025 1026 1027 /** 1028 * Tx Scheduler 1029 * 1030 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1031 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1032 * host DRAM. It steers each frame's Tx command (which contains the frame 1033 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1034 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1035 * but one DMA channel may take input from several queues. 1036 * 1037 * Tx DMA FIFOs have dedicated purposes. 1038 * 1039 * For 5000 series and up, they are used differently 1040 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1041 * 1042 * 0 -- EDCA BK (background) frames, lowest priority 1043 * 1 -- EDCA BE (best effort) frames, normal priority 1044 * 2 -- EDCA VI (video) frames, higher priority 1045 * 3 -- EDCA VO (voice) and management frames, highest priority 1046 * 4 -- unused 1047 * 5 -- unused 1048 * 6 -- unused 1049 * 7 -- Commands 1050 * 1051 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1052 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1053 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1054 * 1055 * The driver sets up each queue to work in one of two modes: 1056 * 1057 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1058 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1059 * contains TFDs for a unique combination of Recipient Address (RA) 1060 * and Traffic Identifier (TID), that is, traffic of a given 1061 * Quality-Of-Service (QOS) priority, destined for a single station. 1062 * 1063 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1064 * each frame within the BA window, including whether it's been transmitted, 1065 * and whether it's been acknowledged by the receiving station. The device 1066 * automatically processes block-acks received from the receiving STA, 1067 * and reschedules un-acked frames to be retransmitted (successful 1068 * Tx completion may end up being out-of-order). 1069 * 1070 * The driver must maintain the queue's Byte Count table in host DRAM 1071 * for this mode. 1072 * This mode does not support fragmentation. 1073 * 1074 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1075 * The device may automatically retry Tx, but will retry only one frame 1076 * at a time, until receiving ACK from receiving station, or reaching 1077 * retry limit and giving up. 1078 * 1079 * The command queue (#4/#9) must use this mode! 1080 * This mode does not require use of the Byte Count table in host DRAM. 1081 * 1082 * Driver controls scheduler operation via 3 means: 1083 * 1) Scheduler registers 1084 * 2) Shared scheduler data base in internal SRAM 1085 * 3) Shared data in host DRAM 1086 * 1087 * Initialization: 1088 * 1089 * When loading, driver should allocate memory for: 1090 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1091 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1092 * (1024 bytes for each queue). 1093 * 1094 * After receiving "Alive" response from uCode, driver must initialize 1095 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1096 * the driver can't issue commands!): 1097 */ 1098 #define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1099 1100 /** 1101 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1102 * can keep track of at one time when creating block-ack chains of frames. 1103 * Note that "64" matches the number of ack bits in a block-ack packet. 1104 */ 1105 #define IWM_SCD_WIN_SIZE 64 1106 #define IWM_SCD_FRAME_LIMIT 64 1107 1108 #define IWM_SCD_TXFIFO_POS_TID (0) 1109 #define IWM_SCD_TXFIFO_POS_RA (4) 1110 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1111 1112 /* agn SCD */ 1113 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1114 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1115 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1116 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1117 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1118 1119 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1120 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1121 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1122 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1123 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1124 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1125 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1126 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1127 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1128 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1129 1130 /* Context Data */ 1131 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1132 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1133 1134 /* Tx status */ 1135 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1136 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1137 1138 /* Translation Data */ 1139 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1140 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1141 1142 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1143 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1144 1145 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1146 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1147 1148 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1149 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1150 1151 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1152 1153 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1154 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1155 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1156 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1157 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1158 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1159 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1160 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1161 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1162 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1163 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1164 1165 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1166 { 1167 if (chnl < 20) 1168 return IWM_SCD_BASE + 0x18 + chnl * 4; 1169 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1170 } 1171 1172 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1173 { 1174 if (chnl < 20) 1175 return IWM_SCD_BASE + 0x68 + chnl * 4; 1176 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1177 } 1178 1179 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1180 { 1181 if (chnl < 20) 1182 return IWM_SCD_BASE + 0x10c + chnl * 4; 1183 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1184 } 1185 1186 /*********************** END TX SCHEDULER *************************************/ 1187 1188 /* Oscillator clock */ 1189 #define IWM_OSC_CLK (0xa04068) 1190 #define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1191 1192 /****************************/ 1193 /* Flow Handler Definitions */ 1194 /****************************/ 1195 1196 /** 1197 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1198 * Addresses are offsets from device's PCI hardware base address. 1199 */ 1200 #define IWM_FH_MEM_LOWER_BOUND (0x1000) 1201 #define IWM_FH_MEM_UPPER_BOUND (0x2000) 1202 1203 /** 1204 * Keep-Warm (KW) buffer base address. 1205 * 1206 * Driver must allocate a 4KByte buffer that is for keeping the 1207 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1208 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1209 * from going into a power-savings mode that would cause higher DRAM latency, 1210 * and possible data over/under-runs, before all Tx/Rx is complete. 1211 * 1212 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1213 * of the buffer, which must be 4K aligned. Once this is set up, the device 1214 * automatically invokes keep-warm accesses when normal accesses might not 1215 * be sufficient to maintain fast DRAM response. 1216 * 1217 * Bit fields: 1218 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1219 */ 1220 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1221 1222 1223 /** 1224 * TFD Circular Buffers Base (CBBC) addresses 1225 * 1226 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1227 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1228 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1229 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1230 * aligned (address bits 0-7 must be 0). 1231 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1232 * for them are in different places. 1233 * 1234 * Bit fields in each pointer register: 1235 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1236 */ 1237 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1238 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1239 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1240 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1241 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1242 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1243 1244 /* Find TFD CB base pointer for given queue */ 1245 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1246 { 1247 if (chnl < 16) 1248 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1249 if (chnl < 20) 1250 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1251 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1252 } 1253 1254 1255 /** 1256 * Rx SRAM Control and Status Registers (RSCSR) 1257 * 1258 * These registers provide handshake between driver and device for the Rx queue 1259 * (this queue handles *all* command responses, notifications, Rx data, etc. 1260 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1261 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1262 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1263 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1264 * mapping between RBDs and RBs. 1265 * 1266 * Driver must allocate host DRAM memory for the following, and set the 1267 * physical address of each into device registers: 1268 * 1269 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1270 * entries (although any power of 2, up to 4096, is selectable by driver). 1271 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1272 * (typically 4K, although 8K or 16K are also selectable by driver). 1273 * Driver sets up RB size and number of RBDs in the CB via Rx config 1274 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1275 * 1276 * Bit fields within one RBD: 1277 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1278 * 1279 * Driver sets physical address [35:8] of base of RBD circular buffer 1280 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1281 * 1282 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1283 * (RBs) have been filled, via a "write pointer", actually the index of 1284 * the RB's corresponding RBD within the circular buffer. Driver sets 1285 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1286 * 1287 * Bit fields in lower dword of Rx status buffer (upper dword not used 1288 * by driver: 1289 * 31-12: Not used by driver 1290 * 11- 0: Index of last filled Rx buffer descriptor 1291 * (device writes, driver reads this value) 1292 * 1293 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1294 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1295 * and update the device's "write" index register, 1296 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1297 * 1298 * This "write" index corresponds to the *next* RBD that the driver will make 1299 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1300 * the circular buffer. This value should initially be 0 (before preparing any 1301 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1302 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1303 * "read" index has advanced past 1! See below). 1304 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1305 * 1306 * As the device fills RBs (referenced from contiguous RBDs within the circular 1307 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1308 * to tell the driver the index of the latest filled RBD. The driver must 1309 * read this "read" index from DRAM after receiving an Rx interrupt from device 1310 * 1311 * The driver must also internally keep track of a third index, which is the 1312 * next RBD to process. When receiving an Rx interrupt, driver should process 1313 * all filled but unprocessed RBs up to, but not including, the RB 1314 * corresponding to the "read" index. For example, if "read" index becomes "1", 1315 * driver may process the RB pointed to by RBD 0. Depending on volume of 1316 * traffic, there may be many RBs to process. 1317 * 1318 * If read index == write index, device thinks there is no room to put new data. 1319 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1320 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1321 * and "read" indexes; that is, make sure that there are no more than 254 1322 * buffers waiting to be filled. 1323 */ 1324 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1325 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1326 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1327 1328 /** 1329 * Physical base address of 8-byte Rx Status buffer. 1330 * Bit fields: 1331 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1332 */ 1333 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1334 1335 /** 1336 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1337 * Bit fields: 1338 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1339 */ 1340 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1341 1342 /** 1343 * Rx write pointer (index, really!). 1344 * Bit fields: 1345 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1346 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1347 */ 1348 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1349 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1350 1351 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1352 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1353 1354 /** 1355 * Rx Config/Status Registers (RCSR) 1356 * Rx Config Reg for channel 0 (only channel used) 1357 * 1358 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1359 * normal operation (see bit fields). 1360 * 1361 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1362 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1363 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1364 * 1365 * Bit fields: 1366 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1367 * '10' operate normally 1368 * 29-24: reserved 1369 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1370 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1371 * 19-18: reserved 1372 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1373 * '10' 12K, '11' 16K. 1374 * 15-14: reserved 1375 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1376 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1377 * typical value 0x10 (about 1/2 msec) 1378 * 3- 0: reserved 1379 */ 1380 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1381 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1382 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1383 1384 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1385 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1386 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1387 1388 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1389 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1390 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1391 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1392 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1393 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1394 1395 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1396 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1397 #define IWM_RX_RB_TIMEOUT (0x11) 1398 1399 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1400 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1401 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1402 1403 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1404 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1405 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1406 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1407 1408 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1409 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1410 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1411 1412 /** 1413 * Rx Shared Status Registers (RSSR) 1414 * 1415 * After stopping Rx DMA channel (writing 0 to 1416 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1417 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1418 * 1419 * Bit fields: 1420 * 24: 1 = Channel 0 is idle 1421 * 1422 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1423 * contain default values that should not be altered by the driver. 1424 */ 1425 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1426 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1427 1428 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1429 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1430 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1431 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1432 1433 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1434 1435 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1436 1437 /* TFDB Area - TFDs buffer table */ 1438 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1439 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1440 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1441 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1442 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1443 1444 /** 1445 * Transmit DMA Channel Control/Status Registers (TCSR) 1446 * 1447 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1448 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1449 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1450 * 1451 * To use a Tx DMA channel, driver must initialize its 1452 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1453 * 1454 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1455 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1456 * 1457 * All other bits should be 0. 1458 * 1459 * Bit fields: 1460 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1461 * '10' operate normally 1462 * 29- 4: Reserved, set to "0" 1463 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1464 * 2- 0: Reserved, set to "0" 1465 */ 1466 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1467 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1468 1469 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 1470 #define IWM_FH_TCSR_CHNL_NUM (8) 1471 1472 /* TCSR: tx_config register values */ 1473 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1474 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1475 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1476 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1477 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1478 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1479 1480 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1481 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1482 1483 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1484 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1485 1486 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1487 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1488 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1489 1490 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1491 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1492 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1493 1494 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1495 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1496 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1497 1498 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1499 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1500 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1501 1502 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1503 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1504 1505 /** 1506 * Tx Shared Status Registers (TSSR) 1507 * 1508 * After stopping Tx DMA channel (writing 0 to 1509 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1510 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1511 * (channel's buffers empty | no pending requests). 1512 * 1513 * Bit fields: 1514 * 31-24: 1 = Channel buffers empty (channel 7:0) 1515 * 23-16: 1 = No pending requests (channel 7:0) 1516 */ 1517 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1518 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1519 1520 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1521 1522 /** 1523 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1524 * 31: Indicates an address error when accessed to internal memory 1525 * uCode/driver must write "1" in order to clear this flag 1526 * 30: Indicates that Host did not send the expected number of dwords to FH 1527 * uCode/driver must write "1" in order to clear this flag 1528 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1529 * command was received from the scheduler while the TRB was already full 1530 * with previous command 1531 * uCode/driver must write "1" in order to clear this flag 1532 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1533 * bit is set, it indicates that the FH has received a full indication 1534 * from the RTC TxFIFO and the current value of the TxCredit counter was 1535 * not equal to zero. This mean that the credit mechanism was not 1536 * synchronized to the TxFIFO status 1537 * uCode/driver must write "1" in order to clear this flag 1538 */ 1539 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1540 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1541 1542 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1543 1544 /* Tx service channels */ 1545 #define IWM_FH_SRVC_CHNL (9) 1546 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1547 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1548 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1549 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1550 1551 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1552 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1553 (_chan) * 4) 1554 1555 /* Instruct FH to increment the retry count of a packet when 1556 * it is brought from the memory to TX-FIFO 1557 */ 1558 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1559 1560 #define IWM_RX_QUEUE_SIZE 256 1561 #define IWM_RX_QUEUE_MASK 255 1562 #define IWM_RX_QUEUE_SIZE_LOG 8 1563 1564 /* 1565 * RX related structures and functions 1566 */ 1567 #define IWM_RX_FREE_BUFFERS 64 1568 #define IWM_RX_LOW_WATERMARK 8 1569 1570 /** 1571 * struct iwm_rb_status - reseve buffer status 1572 * host memory mapped FH registers 1573 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1574 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1575 * @finished_rb_num [0:11] - Indicates the index of the current RB 1576 * in which the last frame was written to 1577 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1578 * which was transferred 1579 */ 1580 struct iwm_rb_status { 1581 uint16_t closed_rb_num; 1582 uint16_t closed_fr_num; 1583 uint16_t finished_rb_num; 1584 uint16_t finished_fr_nam; 1585 uint32_t unused; 1586 } __packed; 1587 1588 1589 #define IWM_TFD_QUEUE_SIZE_MAX (256) 1590 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1591 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1592 IWM_TFD_QUEUE_SIZE_BC_DUP) 1593 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1594 #define IWM_NUM_OF_TBS 20 1595 1596 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1597 { 1598 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1599 } 1600 /** 1601 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1602 * 1603 * This structure contains dma address and length of transmission address 1604 * 1605 * @lo: low [31:0] portion of the dma address of TX buffer 1606 * every even is unaligned on 16 bit boundary 1607 * @hi_n_len 0-3 [35:32] portion of dma 1608 * 4-15 length of the tx buffer 1609 */ 1610 struct iwm_tfd_tb { 1611 uint32_t lo; 1612 uint16_t hi_n_len; 1613 } __packed; 1614 1615 /** 1616 * struct iwm_tfd 1617 * 1618 * Transmit Frame Descriptor (TFD) 1619 * 1620 * @ __reserved1[3] reserved 1621 * @ num_tbs 0-4 number of active tbs 1622 * 5 reserved 1623 * 6-7 padding (not used) 1624 * @ tbs[20] transmit frame buffer descriptors 1625 * @ __pad padding 1626 * 1627 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1628 * Both driver and device share these circular buffers, each of which must be 1629 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1630 * 1631 * Driver must indicate the physical address of the base of each 1632 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1633 * 1634 * Each TFD contains pointer/size information for up to 20 data buffers 1635 * in host DRAM. These buffers collectively contain the (one) frame described 1636 * by the TFD. Each buffer must be a single contiguous block of memory within 1637 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1638 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1639 * Tx frame, up to 8 KBytes in size. 1640 * 1641 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1642 */ 1643 struct iwm_tfd { 1644 uint8_t __reserved1[3]; 1645 uint8_t num_tbs; 1646 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1647 uint32_t __pad; 1648 } __packed; 1649 1650 /* Keep Warm Size */ 1651 #define IWM_KW_SIZE 0x1000 /* 4k */ 1652 1653 /* Fixed (non-configurable) rx data from phy */ 1654 1655 /** 1656 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1657 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1658 * @tfd_offset 0-12 - tx command byte count 1659 * 12-16 - station index 1660 */ 1661 struct iwm_agn_scd_bc_tbl { 1662 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1663 } __packed; 1664 1665 /* Maximum number of Tx queues. */ 1666 #define IWM_MAX_QUEUES 31 1667 1668 /* Tx queue numbers */ 1669 #define IWM_OFFCHANNEL_QUEUE 8 1670 #define IWM_CMD_QUEUE 9 1671 #define IWM_AUX_QUEUE 15 1672 1673 #define IWM_TX_FIFO_BK 0 1674 #define IWM_TX_FIFO_BE 1 1675 #define IWM_TX_FIFO_VI 2 1676 #define IWM_TX_FIFO_VO 3 1677 #define IWM_TX_FIFO_MCAST 5 1678 #define IWM_TX_FIFO_CMD 7 1679 1680 #define IWM_STATION_COUNT 16 1681 1682 /* 1683 * Commands 1684 */ 1685 #define IWM_ALIVE 0x1 1686 #define IWM_REPLY_ERROR 0x2 1687 #define IWM_INIT_COMPLETE_NOTIF 0x4 1688 1689 /* PHY context commands */ 1690 #define IWM_PHY_CONTEXT_CMD 0x8 1691 #define IWM_DBG_CFG 0x9 1692 1693 /* UMAC scan commands */ 1694 #define IWM_SCAN_ITERATION_COMPLETE_UMAC 0xb5 1695 #define IWM_SCAN_CFG_CMD 0xc 1696 #define IWM_SCAN_REQ_UMAC 0xd 1697 #define IWM_SCAN_ABORT_UMAC 0xe 1698 #define IWM_SCAN_COMPLETE_UMAC 0xf 1699 1700 /* station table */ 1701 #define IWM_ADD_STA_KEY 0x17 1702 #define IWM_ADD_STA 0x18 1703 #define IWM_REMOVE_STA 0x19 1704 1705 /* TX */ 1706 #define IWM_TX_CMD 0x1c 1707 #define IWM_TXPATH_FLUSH 0x1e 1708 #define IWM_MGMT_MCAST_KEY 0x1f 1709 1710 /* scheduler config */ 1711 #define IWM_SCD_QUEUE_CFG 0x1d 1712 1713 /* global key */ 1714 #define IWM_WEP_KEY 0x20 1715 1716 /* MAC and Binding commands */ 1717 #define IWM_MAC_CONTEXT_CMD 0x28 1718 #define IWM_TIME_EVENT_CMD 0x29 /* both CMD and response */ 1719 #define IWM_TIME_EVENT_NOTIFICATION 0x2a 1720 #define IWM_BINDING_CONTEXT_CMD 0x2b 1721 #define IWM_TIME_QUOTA_CMD 0x2c 1722 #define IWM_NON_QOS_TX_COUNTER_CMD 0x2d 1723 1724 #define IWM_LQ_CMD 0x4e 1725 1726 /* Calibration */ 1727 #define IWM_TEMPERATURE_NOTIFICATION 0x62 1728 #define IWM_CALIBRATION_CFG_CMD 0x65 1729 #define IWM_CALIBRATION_RES_NOTIFICATION 0x66 1730 #define IWM_CALIBRATION_COMPLETE_NOTIFICATION 0x67 1731 #define IWM_RADIO_VERSION_NOTIFICATION 0x68 1732 1733 /* Scan offload */ 1734 #define IWM_SCAN_OFFLOAD_REQUEST_CMD 0x51 1735 #define IWM_SCAN_OFFLOAD_ABORT_CMD 0x52 1736 #define IWM_HOT_SPOT_CMD 0x53 1737 #define IWM_SCAN_OFFLOAD_COMPLETE 0x6d 1738 #define IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD 0x6e 1739 #define IWM_SCAN_OFFLOAD_CONFIG_CMD 0x6f 1740 #define IWM_MATCH_FOUND_NOTIFICATION 0xd9 1741 #define IWM_SCAN_ITERATION_COMPLETE 0xe7 1742 1743 /* Phy */ 1744 #define IWM_PHY_CONFIGURATION_CMD 0x6a 1745 #define IWM_CALIB_RES_NOTIF_PHY_DB 0x6b 1746 /* IWM_PHY_DB_CMD 0x6c */ 1747 1748 /* Power - legacy power table command */ 1749 #define IWM_POWER_TABLE_CMD 0x77 1750 #define IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION 0x78 1751 1752 /* Thermal Throttling*/ 1753 #define IWM_REPLY_THERMAL_MNG_BACKOFF 0x7e 1754 1755 /* Scanning */ 1756 #define IWM_SCAN_REQUEST_CMD 0x80 1757 #define IWM_SCAN_ABORT_CMD 0x81 1758 #define IWM_SCAN_START_NOTIFICATION 0x82 1759 #define IWM_SCAN_RESULTS_NOTIFICATION 0x83 1760 #define IWM_SCAN_COMPLETE_NOTIFICATION 0x84 1761 1762 /* NVM */ 1763 #define IWM_NVM_ACCESS_CMD 0x88 1764 1765 #define IWM_SET_CALIB_DEFAULT_CMD 0x8e 1766 1767 #define IWM_BEACON_NOTIFICATION 0x90 1768 #define IWM_BEACON_TEMPLATE_CMD 0x91 1769 #define IWM_TX_ANT_CONFIGURATION_CMD 0x98 1770 #define IWM_BT_CONFIG 0x9b 1771 #define IWM_STATISTICS_NOTIFICATION 0x9d 1772 #define IWM_REDUCE_TX_POWER_CMD 0x9f 1773 1774 /* RF-KILL commands and notifications */ 1775 #define IWM_CARD_STATE_CMD 0xa0 1776 #define IWM_CARD_STATE_NOTIFICATION 0xa1 1777 1778 #define IWM_MISSED_BEACONS_NOTIFICATION 0xa2 1779 1780 #define IWM_MFUART_LOAD_NOTIFICATION 0xb1 1781 1782 /* Power - new power table command */ 1783 #define IWM_MAC_PM_POWER_TABLE 0xa9 1784 1785 #define IWM_REPLY_RX_PHY_CMD 0xc0 1786 #define IWM_REPLY_RX_MPDU_CMD 0xc1 1787 #define IWM_BA_NOTIF 0xc5 1788 1789 /* Location Aware Regulatory */ 1790 #define IWM_MCC_UPDATE_CMD 0xc8 1791 #define IWM_MCC_CHUB_UPDATE_CMD 0xc9 1792 1793 /* BT Coex */ 1794 #define IWM_BT_COEX_PRIO_TABLE 0xcc 1795 #define IWM_BT_COEX_PROT_ENV 0xcd 1796 #define IWM_BT_PROFILE_NOTIFICATION 0xce 1797 #define IWM_BT_COEX_CI 0x5d 1798 1799 #define IWM_REPLY_SF_CFG_CMD 0xd1 1800 #define IWM_REPLY_BEACON_FILTERING_CMD 0xd2 1801 1802 /* DTS measurements */ 1803 #define IWM_CMD_DTS_MEASUREMENT_TRIGGER 0xdc 1804 #define IWM_DTS_MEASUREMENT_NOTIFICATION 0xdd 1805 1806 #define IWM_REPLY_DEBUG_CMD 0xf0 1807 #define IWM_DEBUG_LOG_MSG 0xf7 1808 1809 #define IWM_MCAST_FILTER_CMD 0xd0 1810 1811 /* D3 commands/notifications */ 1812 #define IWM_D3_CONFIG_CMD 0xd3 1813 #define IWM_PROT_OFFLOAD_CONFIG_CMD 0xd4 1814 #define IWM_OFFLOADS_QUERY_CMD 0xd5 1815 #define IWM_REMOTE_WAKE_CONFIG_CMD 0xd6 1816 1817 /* for WoWLAN in particular */ 1818 #define IWM_WOWLAN_PATTERNS 0xe0 1819 #define IWM_WOWLAN_CONFIGURATION 0xe1 1820 #define IWM_WOWLAN_TSC_RSC_PARAM 0xe2 1821 #define IWM_WOWLAN_TKIP_PARAM 0xe3 1822 #define IWM_WOWLAN_KEK_KCK_MATERIAL 0xe4 1823 #define IWM_WOWLAN_GET_STATUSES 0xe5 1824 #define IWM_WOWLAN_TX_POWER_PER_DB 0xe6 1825 1826 /* and for NetDetect */ 1827 #define IWM_NET_DETECT_CONFIG_CMD 0x54 1828 #define IWM_NET_DETECT_PROFILES_QUERY_CMD 0x56 1829 #define IWM_NET_DETECT_PROFILES_CMD 0x57 1830 #define IWM_NET_DETECT_HOTSPOTS_CMD 0x58 1831 #define IWM_NET_DETECT_HOTSPOTS_QUERY_CMD 0x59 1832 1833 #define IWM_REPLY_MAX 0xff 1834 1835 /** 1836 * struct iwm_cmd_response - generic response struct for most commands 1837 * @status: status of the command asked, changes for each one 1838 */ 1839 struct iwm_cmd_response { 1840 uint32_t status; 1841 }; 1842 1843 /* 1844 * struct iwm_tx_ant_cfg_cmd 1845 * @valid: valid antenna configuration 1846 */ 1847 struct iwm_tx_ant_cfg_cmd { 1848 uint32_t valid; 1849 } __packed; 1850 1851 /** 1852 * struct iwm_reduce_tx_power_cmd - TX power reduction command 1853 * IWM_REDUCE_TX_POWER_CMD = 0x9f 1854 * @flags: (reserved for future implementation) 1855 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1856 * @pwr_restriction: TX power restriction in dBms. 1857 */ 1858 struct iwm_reduce_tx_power_cmd { 1859 uint8_t flags; 1860 uint8_t mac_context_id; 1861 uint16_t pwr_restriction; 1862 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1863 1864 /* 1865 * Calibration control struct. 1866 * Sent as part of the phy configuration command. 1867 * @flow_trigger: bitmap for which calibrations to perform according to 1868 * flow triggers. 1869 * @event_trigger: bitmap for which calibrations to perform according to 1870 * event triggers. 1871 */ 1872 struct iwm_calib_ctrl { 1873 uint32_t flow_trigger; 1874 uint32_t event_trigger; 1875 } __packed; 1876 1877 /* This defines the bitmap of various calibrations to enable in both 1878 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1879 */ 1880 #define IWM_CALIB_CFG_XTAL_IDX (1 << 0) 1881 #define IWM_CALIB_CFG_TEMPERATURE_IDX (1 << 1) 1882 #define IWM_CALIB_CFG_VOLTAGE_READ_IDX (1 << 2) 1883 #define IWM_CALIB_CFG_PAPD_IDX (1 << 3) 1884 #define IWM_CALIB_CFG_TX_PWR_IDX (1 << 4) 1885 #define IWM_CALIB_CFG_DC_IDX (1 << 5) 1886 #define IWM_CALIB_CFG_BB_FILTER_IDX (1 << 6) 1887 #define IWM_CALIB_CFG_LO_LEAKAGE_IDX (1 << 7) 1888 #define IWM_CALIB_CFG_TX_IQ_IDX (1 << 8) 1889 #define IWM_CALIB_CFG_TX_IQ_SKEW_IDX (1 << 9) 1890 #define IWM_CALIB_CFG_RX_IQ_IDX (1 << 10) 1891 #define IWM_CALIB_CFG_RX_IQ_SKEW_IDX (1 << 11) 1892 #define IWM_CALIB_CFG_SENSITIVITY_IDX (1 << 12) 1893 #define IWM_CALIB_CFG_CHAIN_NOISE_IDX (1 << 13) 1894 #define IWM_CALIB_CFG_DISCONNECTED_ANT_IDX (1 << 14) 1895 #define IWM_CALIB_CFG_ANT_COUPLING_IDX (1 << 15) 1896 #define IWM_CALIB_CFG_DAC_IDX (1 << 16) 1897 #define IWM_CALIB_CFG_ABS_IDX (1 << 17) 1898 #define IWM_CALIB_CFG_AGC_IDX (1 << 18) 1899 1900 /* 1901 * Phy configuration command. 1902 */ 1903 struct iwm_phy_cfg_cmd { 1904 uint32_t phy_cfg; 1905 struct iwm_calib_ctrl calib_control; 1906 } __packed; 1907 1908 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 1909 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 1910 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 1911 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 1912 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 1913 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 1914 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 1915 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 1916 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 1917 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 1918 1919 /* 1920 * PHY db 1921 */ 1922 1923 #define IWM_PHY_DB_CFG 1 1924 #define IWM_PHY_DB_CALIB_NCH 2 1925 #define IWM_PHY_DB_UNUSED 3 1926 #define IWM_PHY_DB_CALIB_CHG_PAPD 4 1927 #define IWM_PHY_DB_CALIB_CHG_TXP 5 1928 #define IWM_PHY_DB_MAX 6 1929 1930 #define IWM_PHY_DB_CMD 0x6c /* TEMP API - The actual is 0x8c */ 1931 1932 /* 1933 * phy db - configure operational ucode 1934 */ 1935 struct iwm_phy_db_cmd { 1936 uint16_t type; 1937 uint16_t length; 1938 uint8_t data[]; 1939 } __packed; 1940 1941 /* for parsing of tx power channel group data that comes from the firmware*/ 1942 struct iwm_phy_db_chg_txp { 1943 uint32_t space; 1944 uint16_t max_channel_idx; 1945 } __packed; 1946 1947 /* 1948 * phy db - Receive phy db chunk after calibrations 1949 */ 1950 struct iwm_calib_res_notif_phy_db { 1951 uint16_t type; 1952 uint16_t length; 1953 uint8_t data[]; 1954 } __packed; 1955 1956 /* 7k family NVM HW-Section offset (in words) definitions */ 1957 #define IWM_HW_ADDR 0x15 1958 /* 7k family NVM SW-Section offset (in words) definitions */ 1959 #define IWM_NVM_SW_SECTION 0x1C0 1960 #define IWM_NVM_VERSION 0 1961 #define IWM_RADIO_CFG 1 1962 #define IWM_SKU 2 1963 #define IWM_N_HW_ADDRS 3 1964 #define IWM_NVM_CHANNELS 0x1E0 - IWM_NVM_SW_SECTION 1965 /* 7k family NVM calibration section offset (in words) definitions */ 1966 #define IWM_NVM_CALIB_SECTION 0x2B8 1967 #define IWM_XTAL_CALIB (0x316 - IWM_NVM_CALIB_SECTION) 1968 1969 /* 8k family NVM HW-Section offset (in words) definitions */ 1970 #define IWM_HW_ADDR0_WFPM_8000 0x12 1971 #define IWM_HW_ADDR1_WFPM_8000 0x16 1972 #define IWM_HW_ADDR0_PCIE_8000 0x8A 1973 #define IWM_HW_ADDR1_PCIE_8000 0x8E 1974 #define IWM_MAC_ADDRESS_OVERRIDE_8000 1 1975 1976 /* 8k family NVM SW-Section offset (in words) definitions */ 1977 #define IWM_NVM_SW_SECTION_8000 0x1C0 1978 #define IWM_NVM_VERSION_8000 0 1979 #define IWM_RADIO_CFG_8000 0 1980 #define IWM_SKU_8000 2 1981 #define IWM_N_HW_ADDRS_8000 3 1982 1983 /* 8k family NVM REGULATORY -Section offset (in words) definitions */ 1984 #define IWM_NVM_CHANNELS_8000 0 1985 #define IWM_NVM_LAR_OFFSET_8000_OLD 0x4C7 1986 #define IWM_NVM_LAR_OFFSET_8000 0x507 1987 #define IWM_NVM_LAR_ENABLED_8000 0x7 1988 1989 /* 8k family NVM calibration section offset (in words) definitions */ 1990 #define IWM_NVM_CALIB_SECTION_8000 0x2B8 1991 #define IWM_XTAL_CALIB_8000 (0x316 - IWM_NVM_CALIB_SECTION_8000) 1992 1993 /* SKU Capabilities (actual values from NVM definition) */ 1994 #define IWM_NVM_SKU_CAP_BAND_24GHZ (1 << 0) 1995 #define IWM_NVM_SKU_CAP_BAND_52GHZ (1 << 1) 1996 #define IWM_NVM_SKU_CAP_11N_ENABLE (1 << 2) 1997 #define IWM_NVM_SKU_CAP_11AC_ENABLE (1 << 3) 1998 #define IWM_NVM_SKU_CAP_MIMO_DISABLE (1 << 5) 1999 2000 /* radio config bits (actual values from NVM definition) */ 2001 #define IWM_NVM_RF_CFG_DASH_MSK(x) (x & 0x3) /* bits 0-1 */ 2002 #define IWM_NVM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */ 2003 #define IWM_NVM_RF_CFG_TYPE_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */ 2004 #define IWM_NVM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */ 2005 #define IWM_NVM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ 2006 #define IWM_NVM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ 2007 2008 #define IWM_NVM_RF_CFG_PNUM_MSK_8000(x) (x & 0xF) 2009 #define IWM_NVM_RF_CFG_DASH_MSK_8000(x) ((x >> 4) & 0xF) 2010 #define IWM_NVM_RF_CFG_STEP_MSK_8000(x) ((x >> 8) & 0xF) 2011 #define IWM_NVM_RF_CFG_TYPE_MSK_8000(x) ((x >> 12) & 0xFFF) 2012 #define IWM_NVM_RF_CFG_TX_ANT_MSK_8000(x) ((x >> 24) & 0xF) 2013 #define IWM_NVM_RF_CFG_RX_ANT_MSK_8000(x) ((x >> 28) & 0xF) 2014 2015 #define DEFAULT_MAX_TX_POWER 16 2016 2017 /* 2018 * channel flags in NVM 2019 * @IWM_NVM_CHANNEL_VALID: channel is usable for this SKU/geo 2020 * @IWM_NVM_CHANNEL_IBSS: usable as an IBSS channel 2021 * @IWM_NVM_CHANNEL_ACTIVE: active scanning allowed 2022 * @IWM_NVM_CHANNEL_RADAR: radar detection required 2023 * @IWM_NVM_CHANNEL_DFS: dynamic freq selection candidate 2024 * @IWM_NVM_CHANNEL_WIDE: 20 MHz channel okay (?) 2025 * @IWM_NVM_CHANNEL_40MHZ: 40 MHz channel okay (?) 2026 * @IWM_NVM_CHANNEL_80MHZ: 80 MHz channel okay (?) 2027 * @IWM_NVM_CHANNEL_160MHZ: 160 MHz channel okay (?) 2028 */ 2029 #define IWM_NVM_CHANNEL_VALID (1 << 0) 2030 #define IWM_NVM_CHANNEL_IBSS (1 << 1) 2031 #define IWM_NVM_CHANNEL_ACTIVE (1 << 3) 2032 #define IWM_NVM_CHANNEL_RADAR (1 << 4) 2033 #define IWM_NVM_CHANNEL_DFS (1 << 7) 2034 #define IWM_NVM_CHANNEL_WIDE (1 << 8) 2035 #define IWM_NVM_CHANNEL_40MHZ (1 << 9) 2036 #define IWM_NVM_CHANNEL_80MHZ (1 << 10) 2037 #define IWM_NVM_CHANNEL_160MHZ (1 << 11) 2038 2039 /* Target of the IWM_NVM_ACCESS_CMD */ 2040 #define IWM_NVM_ACCESS_TARGET_CACHE 0 2041 #define IWM_NVM_ACCESS_TARGET_OTP 1 2042 #define IWM_NVM_ACCESS_TARGET_EEPROM 2 2043 2044 /* Section types for IWM_NVM_ACCESS_CMD */ 2045 #define IWM_NVM_SECTION_TYPE_HW 0 2046 #define IWM_NVM_SECTION_TYPE_SW 1 2047 #define IWM_NVM_SECTION_TYPE_PAPD 2 2048 #define IWM_NVM_SECTION_TYPE_REGULATORY 3 2049 #define IWM_NVM_SECTION_TYPE_CALIBRATION 4 2050 #define IWM_NVM_SECTION_TYPE_PRODUCTION 5 2051 #define IWM_NVM_SECTION_TYPE_POST_FCS_CALIB 6 2052 /* 7, 8, 9 unknown */ 2053 #define IWM_NVM_SECTION_TYPE_HW_8000 10 2054 #define IWM_NVM_SECTION_TYPE_MAC_OVERRIDE 11 2055 #define IWM_NVM_SECTION_TYPE_PHY_SKU 12 2056 #define IWM_NVM_NUM_OF_SECTIONS 13 2057 2058 /** 2059 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2060 * @op_code: 0 - read, 1 - write 2061 * @target: IWM_NVM_ACCESS_TARGET_* 2062 * @type: IWM_NVM_SECTION_TYPE_* 2063 * @offset: offset in bytes into the section 2064 * @length: in bytes, to read/write 2065 * @data: if write operation, the data to write. On read its empty 2066 */ 2067 struct iwm_nvm_access_cmd { 2068 uint8_t op_code; 2069 uint8_t target; 2070 uint16_t type; 2071 uint16_t offset; 2072 uint16_t length; 2073 uint8_t data[]; 2074 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2075 2076 /** 2077 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2078 * @offset: offset in bytes into the section 2079 * @length: in bytes, either how much was written or read 2080 * @type: IWM_NVM_SECTION_TYPE_* 2081 * @status: 0 for success, fail otherwise 2082 * @data: if read operation, the data returned. Empty on write. 2083 */ 2084 struct iwm_nvm_access_resp { 2085 uint16_t offset; 2086 uint16_t length; 2087 uint16_t type; 2088 uint16_t status; 2089 uint8_t data[]; 2090 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2091 2092 /* IWM_ALIVE 0x1 */ 2093 2094 /* alive response is_valid values */ 2095 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2096 #define IWM_ALIVE_RESP_RFKILL (1 << 1) 2097 2098 /* alive response ver_type values */ 2099 #define IWM_FW_TYPE_HW 0 2100 #define IWM_FW_TYPE_PROT 1 2101 #define IWM_FW_TYPE_AP 2 2102 #define IWM_FW_TYPE_WOWLAN 3 2103 #define IWM_FW_TYPE_TIMING 4 2104 #define IWM_FW_TYPE_WIPAN 5 2105 2106 /* alive response ver_subtype values */ 2107 #define IWM_FW_SUBTYPE_FULL_FEATURE 0 2108 #define IWM_FW_SUBTYPE_BOOTSRAP 1 /* Not valid */ 2109 #define IWM_FW_SUBTYPE_REDUCED 2 2110 #define IWM_FW_SUBTYPE_ALIVE_ONLY 3 2111 #define IWM_FW_SUBTYPE_WOWLAN 4 2112 #define IWM_FW_SUBTYPE_AP_SUBTYPE 5 2113 #define IWM_FW_SUBTYPE_WIPAN 6 2114 #define IWM_FW_SUBTYPE_INITIALIZE 9 2115 2116 #define IWM_ALIVE_STATUS_ERR 0xDEAD 2117 #define IWM_ALIVE_STATUS_OK 0xCAFE 2118 2119 #define IWM_ALIVE_FLG_RFKILL (1 << 0) 2120 2121 struct iwm_alive_resp_v1 { 2122 uint16_t status; 2123 uint16_t flags; 2124 uint8_t ucode_minor; 2125 uint8_t ucode_major; 2126 uint16_t id; 2127 uint8_t api_minor; 2128 uint8_t api_major; 2129 uint8_t ver_subtype; 2130 uint8_t ver_type; 2131 uint8_t mac; 2132 uint8_t opt; 2133 uint16_t reserved2; 2134 uint32_t timestamp; 2135 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2136 uint32_t log_event_table_ptr; /* SRAM address for event log */ 2137 uint32_t cpu_register_ptr; 2138 uint32_t dbgm_config_ptr; 2139 uint32_t alive_counter_ptr; 2140 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2141 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2142 2143 struct iwm_alive_resp_v2 { 2144 uint16_t status; 2145 uint16_t flags; 2146 uint8_t ucode_minor; 2147 uint8_t ucode_major; 2148 uint16_t id; 2149 uint8_t api_minor; 2150 uint8_t api_major; 2151 uint8_t ver_subtype; 2152 uint8_t ver_type; 2153 uint8_t mac; 2154 uint8_t opt; 2155 uint16_t reserved2; 2156 uint32_t timestamp; 2157 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2158 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2159 uint32_t cpu_register_ptr; 2160 uint32_t dbgm_config_ptr; 2161 uint32_t alive_counter_ptr; 2162 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2163 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2164 uint32_t st_fwrd_size; 2165 uint8_t umac_minor; /* UMAC version: minor */ 2166 uint8_t umac_major; /* UMAC version: major */ 2167 uint16_t umac_id; /* UMAC version: id */ 2168 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2169 uint32_t dbg_print_buff_addr; 2170 } __packed; /* ALIVE_RES_API_S_VER_2 */ 2171 2172 struct iwm_alive_resp_v3 { 2173 uint16_t status; 2174 uint16_t flags; 2175 uint32_t ucode_minor; 2176 uint32_t ucode_major; 2177 uint8_t ver_subtype; 2178 uint8_t ver_type; 2179 uint8_t mac; 2180 uint8_t opt; 2181 uint32_t timestamp; 2182 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2183 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2184 uint32_t cpu_register_ptr; 2185 uint32_t dbgm_config_ptr; 2186 uint32_t alive_counter_ptr; 2187 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2188 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2189 uint32_t st_fwrd_size; 2190 uint32_t umac_minor; /* UMAC version: minor */ 2191 uint32_t umac_major; /* UMAC version: major */ 2192 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2193 uint32_t dbg_print_buff_addr; 2194 } __packed; /* ALIVE_RES_API_S_VER_3 */ 2195 2196 /* Error response/notification */ 2197 #define IWM_FW_ERR_UNKNOWN_CMD 0x0 2198 #define IWM_FW_ERR_INVALID_CMD_PARAM 0x1 2199 #define IWM_FW_ERR_SERVICE 0x2 2200 #define IWM_FW_ERR_ARC_MEMORY 0x3 2201 #define IWM_FW_ERR_ARC_CODE 0x4 2202 #define IWM_FW_ERR_WATCH_DOG 0x5 2203 #define IWM_FW_ERR_WEP_GRP_KEY_INDX 0x10 2204 #define IWM_FW_ERR_WEP_KEY_SIZE 0x11 2205 #define IWM_FW_ERR_OBSOLETE_FUNC 0x12 2206 #define IWM_FW_ERR_UNEXPECTED 0xFE 2207 #define IWM_FW_ERR_FATAL 0xFF 2208 2209 /** 2210 * struct iwm_error_resp - FW error indication 2211 * ( IWM_REPLY_ERROR = 0x2 ) 2212 * @error_type: one of IWM_FW_ERR_* 2213 * @cmd_id: the command ID for which the error occured 2214 * @bad_cmd_seq_num: sequence number of the erroneous command 2215 * @error_service: which service created the error, applicable only if 2216 * error_type = 2, otherwise 0 2217 * @timestamp: TSF in usecs. 2218 */ 2219 struct iwm_error_resp { 2220 uint32_t error_type; 2221 uint8_t cmd_id; 2222 uint8_t reserved1; 2223 uint16_t bad_cmd_seq_num; 2224 uint32_t error_service; 2225 uint64_t timestamp; 2226 } __packed; 2227 2228 2229 /* Common PHY, MAC and Bindings definitions */ 2230 2231 #define IWM_MAX_MACS_IN_BINDING (3) 2232 #define IWM_MAX_BINDINGS (4) 2233 #define IWM_AUX_BINDING_INDEX (3) 2234 #define IWM_MAX_PHYS (4) 2235 2236 /* Used to extract ID and color from the context dword */ 2237 #define IWM_FW_CTXT_ID_POS (0) 2238 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2239 #define IWM_FW_CTXT_COLOR_POS (8) 2240 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2241 #define IWM_FW_CTXT_INVALID (0xffffffff) 2242 2243 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2244 (_color << IWM_FW_CTXT_COLOR_POS)) 2245 2246 /* Possible actions on PHYs, MACs and Bindings */ 2247 #define IWM_FW_CTXT_ACTION_STUB 0 2248 #define IWM_FW_CTXT_ACTION_ADD 1 2249 #define IWM_FW_CTXT_ACTION_MODIFY 2 2250 #define IWM_FW_CTXT_ACTION_REMOVE 3 2251 #define IWM_FW_CTXT_ACTION_NUM 4 2252 /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2253 2254 /* Time Events */ 2255 2256 /* Time Event types, according to MAC type */ 2257 2258 /* BSS Station Events */ 2259 #define IWM_TE_BSS_STA_AGGRESSIVE_ASSOC 0 2260 #define IWM_TE_BSS_STA_ASSOC 1 2261 #define IWM_TE_BSS_EAP_DHCP_PROT 2 2262 #define IWM_TE_BSS_QUIET_PERIOD 3 2263 2264 /* P2P Device Events */ 2265 #define IWM_TE_P2P_DEVICE_DISCOVERABLE 4 2266 #define IWM_TE_P2P_DEVICE_LISTEN 5 2267 #define IWM_TE_P2P_DEVICE_ACTION_SCAN 6 2268 #define IWM_TE_P2P_DEVICE_FULL_SCAN 7 2269 2270 /* P2P Client Events */ 2271 #define IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC 8 2272 #define IWM_TE_P2P_CLIENT_ASSOC 9 2273 #define IWM_TE_P2P_CLIENT_QUIET_PERIOD 10 2274 2275 /* P2P GO Events */ 2276 #define IWM_TE_P2P_GO_ASSOC_PROT 11 2277 #define IWM_TE_P2P_GO_REPETITIVE_NOA 12 2278 #define IWM_TE_P2P_GO_CT_WINDOW 13 2279 2280 /* WiDi Sync Events */ 2281 #define IWM_TE_WIDI_TX_SYNC 14 2282 2283 #define IWM_TE_MAX 15 2284 /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2285 2286 2287 2288 /* Time event - defines for command API v1 */ 2289 2290 /* 2291 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2292 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2293 * the first fragment is scheduled. 2294 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2295 * the first 2 fragments are scheduled. 2296 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2297 * number of fragments are valid. 2298 * 2299 * Other than the constant defined above, specifying a fragmentation value 'x' 2300 * means that the event can be fragmented but only the first 'x' will be 2301 * scheduled. 2302 */ 2303 #define IWM_TE_V1_FRAG_NONE 0 2304 #define IWM_TE_V1_FRAG_SINGLE 1 2305 #define IWM_TE_V1_FRAG_DUAL 2 2306 #define IWM_TE_V1_FRAG_ENDLESS 0xffffffff 2307 2308 /* If a Time Event can be fragmented, this is the max number of fragments */ 2309 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2310 /* Repeat the time event endlessly (until removed) */ 2311 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2312 /* If a Time Event has bounded repetitions, this is the maximal value */ 2313 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2314 2315 /* Time Event dependencies: none, on another TE, or in a specific time */ 2316 #define IWM_TE_V1_INDEPENDENT 0 2317 #define IWM_TE_V1_DEP_OTHER (1 << 0) 2318 #define IWM_TE_V1_DEP_TSF (1 << 1) 2319 #define IWM_TE_V1_EVENT_SOCIOPATHIC (1 << 2) 2320 /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2321 2322 /* 2323 * @IWM_TE_V1_NOTIF_NONE: no notifications 2324 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2325 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2326 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2327 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2328 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2329 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2330 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2331 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2332 * 2333 * Supported Time event notifications configuration. 2334 * A notification (both event and fragment) includes a status indicating weather 2335 * the FW was able to schedule the event or not. For fragment start/end 2336 * notification the status is always success. There is no start/end fragment 2337 * notification for monolithic events. 2338 */ 2339 #define IWM_TE_V1_NOTIF_NONE 0 2340 #define IWM_TE_V1_NOTIF_HOST_EVENT_START (1 << 0) 2341 #define IWM_TE_V1_NOTIF_HOST_EVENT_END (1 << 1) 2342 #define IWM_TE_V1_NOTIF_INTERNAL_EVENT_START (1 << 2) 2343 #define IWM_TE_V1_NOTIF_INTERNAL_EVENT_END (1 << 3) 2344 #define IWM_TE_V1_NOTIF_HOST_FRAG_START (1 << 4) 2345 #define IWM_TE_V1_NOTIF_HOST_FRAG_END (1 << 5) 2346 #define IWM_TE_V1_NOTIF_INTERNAL_FRAG_START (1 << 6) 2347 #define IWM_TE_V1_NOTIF_INTERNAL_FRAG_END (1 << 7) 2348 /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2349 2350 2351 /** 2352 * struct iwm_time_event_cmd_api_v1 - configuring Time Events 2353 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also 2354 * with version 2. determined by IWM_UCODE_TLV_FLAGS) 2355 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2356 * @id_and_color: ID and color of the relevant MAC 2357 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2358 * @id: this field has two meanings, depending on the action: 2359 * If the action is ADD, then it means the type of event to add. 2360 * For all other actions it is the unique event ID assigned when the 2361 * event was added by the FW. 2362 * @apply_time: When to start the Time Event (in GP2) 2363 * @max_delay: maximum delay to event's start (apply time), in TU 2364 * @depends_on: the unique ID of the event we depend on (if any) 2365 * @interval: interval between repetitions, in TU 2366 * @interval_reciprocal: 2^32 / interval 2367 * @duration: duration of event in TU 2368 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2369 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF 2370 * and IWM_TE_V1_EVENT_SOCIOPATHIC 2371 * @is_present: 0 or 1, are we present or absent during the Time Event 2372 * @max_frags: maximal number of fragments the Time Event can be divided to 2373 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when) 2374 */ 2375 struct iwm_time_event_cmd_v1 { 2376 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2377 uint32_t id_and_color; 2378 uint32_t action; 2379 uint32_t id; 2380 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */ 2381 uint32_t apply_time; 2382 uint32_t max_delay; 2383 uint32_t dep_policy; 2384 uint32_t depends_on; 2385 uint32_t is_present; 2386 uint32_t max_frags; 2387 uint32_t interval; 2388 uint32_t interval_reciprocal; 2389 uint32_t duration; 2390 uint32_t repeat; 2391 uint32_t notify; 2392 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */ 2393 2394 2395 /* Time event - defines for command API v2 */ 2396 2397 /** 2398 * DOC: Time Events - what is it? 2399 * 2400 * Time Events are a fw feature that allows the driver to control the presence 2401 * of the device on the channel. Since the fw supports multiple channels 2402 * concurrently, the fw may choose to jump to another channel at any time. 2403 * In order to make sure that the fw is on a specific channel at a certain time 2404 * and for a certain duration, the driver needs to issue a time event. 2405 * 2406 * The simplest example is for BSS association. The driver issues a time event, 2407 * waits for it to start, and only then tells mac80211 that we can start the 2408 * association. This way, we make sure that the association will be done 2409 * smoothly and won't be interrupted by channel switch decided within the fw. 2410 */ 2411 2412 /** 2413 * DOC: The flow against the fw 2414 * 2415 * When the driver needs to make sure we are in a certain channel, at a certain 2416 * time and for a certain duration, it sends a Time Event. The flow against the 2417 * fw goes like this: 2418 * 1) Driver sends a TIME_EVENT_CMD to the fw 2419 * 2) Driver gets the response for that command. This response contains the 2420 * Unique ID (UID) of the event. 2421 * 3) The fw sends notification when the event starts. 2422 * 2423 * Of course the API provides various options that allow to cover parameters 2424 * of the flow. 2425 * What is the duration of the event? 2426 * What is the start time of the event? 2427 * Is there an end-time for the event? 2428 * How much can the event be delayed? 2429 * Can the event be split? 2430 * If yes what is the maximal number of chunks? 2431 * etc... 2432 */ 2433 2434 /* 2435 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2436 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2437 * the first fragment is scheduled. 2438 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2439 * the first 2 fragments are scheduled. 2440 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2441 * number of fragments are valid. 2442 * 2443 * Other than the constant defined above, specifying a fragmentation value 'x' 2444 * means that the event can be fragmented but only the first 'x' will be 2445 * scheduled. 2446 */ 2447 #define IWM_TE_V2_FRAG_NONE 0 2448 #define IWM_TE_V2_FRAG_SINGLE 1 2449 #define IWM_TE_V2_FRAG_DUAL 2 2450 #define IWM_TE_V2_FRAG_MAX 0xfe 2451 #define IWM_TE_V2_FRAG_ENDLESS 0xff 2452 2453 /* Repeat the time event endlessly (until removed) */ 2454 #define IWM_TE_V2_REPEAT_ENDLESS 0xff 2455 /* If a Time Event has bounded repetitions, this is the maximal value */ 2456 #define IWM_TE_V2_REPEAT_MAX 0xfe 2457 2458 #define IWM_TE_V2_PLACEMENT_POS 12 2459 #define IWM_TE_V2_ABSENCE_POS 15 2460 2461 /* Time event policy values (for time event cmd api v2) 2462 * A notification (both event and fragment) includes a status indicating weather 2463 * the FW was able to schedule the event or not. For fragment start/end 2464 * notification the status is always success. There is no start/end fragment 2465 * notification for monolithic events. 2466 * 2467 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2468 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2469 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2470 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2471 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2472 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2473 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2474 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2475 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2476 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2477 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2478 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2479 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2480 */ 2481 #define IWM_TE_V2_DEFAULT_POLICY 0x0 2482 2483 /* notifications (event start/stop, fragment start/stop) */ 2484 #define IWM_TE_V2_NOTIF_HOST_EVENT_START (1 << 0) 2485 #define IWM_TE_V2_NOTIF_HOST_EVENT_END (1 << 1) 2486 #define IWM_TE_V2_NOTIF_INTERNAL_EVENT_START (1 << 2) 2487 #define IWM_TE_V2_NOTIF_INTERNAL_EVENT_END (1 << 3) 2488 2489 #define IWM_TE_V2_NOTIF_HOST_FRAG_START (1 << 4) 2490 #define IWM_TE_V2_NOTIF_HOST_FRAG_END (1 << 5) 2491 #define IWM_TE_V2_NOTIF_INTERNAL_FRAG_START (1 << 6) 2492 #define IWM_TE_V2_NOTIF_INTERNAL_FRAG_END (1 << 7) 2493 #define IWM_T2_V2_START_IMMEDIATELY (1 << 11) 2494 2495 #define IWM_TE_V2_NOTIF_MSK 0xff 2496 2497 /* placement characteristics */ 2498 #define IWM_TE_V2_DEP_OTHER (1 << IWM_TE_V2_PLACEMENT_POS) 2499 #define IWM_TE_V2_DEP_TSF (1 << (IWM_TE_V2_PLACEMENT_POS + 1)) 2500 #define IWM_TE_V2_EVENT_SOCIOPATHIC (1 << (IWM_TE_V2_PLACEMENT_POS + 2)) 2501 2502 /* are we present or absent during the Time Event. */ 2503 #define IWM_TE_V2_ABSENCE (1 << IWM_TE_V2_ABSENCE_POS) 2504 2505 /** 2506 * struct iwm_time_event_cmd_api_v2 - configuring Time Events 2507 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2508 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2509 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2510 * @id_and_color: ID and color of the relevant MAC 2511 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2512 * @id: this field has two meanings, depending on the action: 2513 * If the action is ADD, then it means the type of event to add. 2514 * For all other actions it is the unique event ID assigned when the 2515 * event was added by the FW. 2516 * @apply_time: When to start the Time Event (in GP2) 2517 * @max_delay: maximum delay to event's start (apply time), in TU 2518 * @depends_on: the unique ID of the event we depend on (if any) 2519 * @interval: interval between repetitions, in TU 2520 * @duration: duration of event in TU 2521 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2522 * @max_frags: maximal number of fragments the Time Event can be divided to 2523 * @policy: defines whether uCode shall notify the host or other uCode modules 2524 * on event and/or fragment start and/or end 2525 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2526 * IWM_TE_EVENT_SOCIOPATHIC 2527 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2528 */ 2529 struct iwm_time_event_cmd_v2 { 2530 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2531 uint32_t id_and_color; 2532 uint32_t action; 2533 uint32_t id; 2534 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2535 uint32_t apply_time; 2536 uint32_t max_delay; 2537 uint32_t depends_on; 2538 uint32_t interval; 2539 uint32_t duration; 2540 uint8_t repeat; 2541 uint8_t max_frags; 2542 uint16_t policy; 2543 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2544 2545 /** 2546 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2547 * @status: bit 0 indicates success, all others specify errors 2548 * @id: the Time Event type 2549 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2550 * @id_and_color: ID and color of the relevant MAC 2551 */ 2552 struct iwm_time_event_resp { 2553 uint32_t status; 2554 uint32_t id; 2555 uint32_t unique_id; 2556 uint32_t id_and_color; 2557 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2558 2559 /** 2560 * struct iwm_time_event_notif - notifications of time event start/stop 2561 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2562 * @timestamp: action timestamp in GP2 2563 * @session_id: session's unique id 2564 * @unique_id: unique id of the Time Event itself 2565 * @id_and_color: ID and color of the relevant MAC 2566 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2567 * @status: true if scheduled, false otherwise (not executed) 2568 */ 2569 struct iwm_time_event_notif { 2570 uint32_t timestamp; 2571 uint32_t session_id; 2572 uint32_t unique_id; 2573 uint32_t id_and_color; 2574 uint32_t action; 2575 uint32_t status; 2576 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2577 2578 2579 /* Bindings and Time Quota */ 2580 2581 /** 2582 * struct iwm_binding_cmd - configuring bindings 2583 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2584 * @id_and_color: ID and color of the relevant Binding 2585 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2586 * @macs: array of MAC id and colors which belong to the binding 2587 * @phy: PHY id and color which belongs to the binding 2588 */ 2589 struct iwm_binding_cmd { 2590 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2591 uint32_t id_and_color; 2592 uint32_t action; 2593 /* IWM_BINDING_DATA_API_S_VER_1 */ 2594 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2595 uint32_t phy; 2596 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2597 2598 /* The maximal number of fragments in the FW's schedule session */ 2599 #define IWM_MAX_QUOTA 128 2600 2601 /** 2602 * struct iwm_time_quota_data - configuration of time quota per binding 2603 * @id_and_color: ID and color of the relevant Binding 2604 * @quota: absolute time quota in TU. The scheduler will try to divide the 2605 * remainig quota (after Time Events) according to this quota. 2606 * @max_duration: max uninterrupted context duration in TU 2607 */ 2608 struct iwm_time_quota_data { 2609 uint32_t id_and_color; 2610 uint32_t quota; 2611 uint32_t max_duration; 2612 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2613 2614 /** 2615 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2616 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2617 * @quotas: allocations per binding 2618 */ 2619 struct iwm_time_quota_cmd { 2620 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2621 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2622 2623 2624 /* PHY context */ 2625 2626 /* Supported bands */ 2627 #define IWM_PHY_BAND_5 (0) 2628 #define IWM_PHY_BAND_24 (1) 2629 2630 /* Supported channel width, vary if there is VHT support */ 2631 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2632 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2633 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2634 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2635 2636 /* 2637 * Control channel position: 2638 * For legacy set bit means upper channel, otherwise lower. 2639 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2640 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2641 * center_freq 2642 * | 2643 * 40Mhz |_______|_______| 2644 * 80Mhz |_______|_______|_______|_______| 2645 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2646 * code 011 010 001 000 | 100 101 110 111 2647 */ 2648 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2649 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2650 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2651 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2652 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2653 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2654 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2655 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2656 2657 /* 2658 * @band: IWM_PHY_BAND_* 2659 * @channel: channel number 2660 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2661 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2662 */ 2663 struct iwm_fw_channel_info { 2664 uint8_t band; 2665 uint8_t channel; 2666 uint8_t width; 2667 uint8_t ctrl_pos; 2668 } __packed; 2669 2670 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2671 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2672 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2673 #define IWM_PHY_RX_CHAIN_VALID_POS (1) 2674 #define IWM_PHY_RX_CHAIN_VALID_MSK \ 2675 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2676 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2677 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2678 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2679 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2680 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2681 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2682 #define IWM_PHY_RX_CHAIN_CNT_POS (10) 2683 #define IWM_PHY_RX_CHAIN_CNT_MSK \ 2684 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2685 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2686 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2687 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2688 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2689 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2690 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2691 2692 /* TODO: fix the value, make it depend on firmware at runtime? */ 2693 #define IWM_NUM_PHY_CTX 3 2694 2695 /* TODO: complete missing documentation */ 2696 /** 2697 * struct iwm_phy_context_cmd - config of the PHY context 2698 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2699 * @id_and_color: ID and color of the relevant Binding 2700 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2701 * @apply_time: 0 means immediate apply and context switch. 2702 * other value means apply new params after X usecs 2703 * @tx_param_color: ??? 2704 * @channel_info: 2705 * @txchain_info: ??? 2706 * @rxchain_info: ??? 2707 * @acquisition_data: ??? 2708 * @dsp_cfg_flags: set to 0 2709 */ 2710 struct iwm_phy_context_cmd { 2711 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2712 uint32_t id_and_color; 2713 uint32_t action; 2714 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2715 uint32_t apply_time; 2716 uint32_t tx_param_color; 2717 struct iwm_fw_channel_info ci; 2718 uint32_t txchain_info; 2719 uint32_t rxchain_info; 2720 uint32_t acquisition_data; 2721 uint32_t dsp_cfg_flags; 2722 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2723 2724 #define IWM_RX_INFO_PHY_CNT 8 2725 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2726 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2727 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2728 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2729 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2730 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2731 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2732 2733 #define IWM_RX_INFO_AGC_IDX 1 2734 #define IWM_RX_INFO_RSSI_AB_IDX 2 2735 #define IWM_OFDM_AGC_A_MSK 0x0000007f 2736 #define IWM_OFDM_AGC_A_POS 0 2737 #define IWM_OFDM_AGC_B_MSK 0x00003f80 2738 #define IWM_OFDM_AGC_B_POS 7 2739 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2740 #define IWM_OFDM_AGC_CODE_POS 20 2741 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2742 #define IWM_OFDM_RSSI_A_POS 0 2743 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2744 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2745 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2746 #define IWM_OFDM_RSSI_B_POS 16 2747 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2748 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2749 2750 /** 2751 * struct iwm_rx_phy_info - phy info 2752 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2753 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2754 * @cfg_phy_cnt: configurable DSP phy data byte count 2755 * @stat_id: configurable DSP phy data set ID 2756 * @reserved1: 2757 * @system_timestamp: GP2 at on air rise 2758 * @timestamp: TSF at on air rise 2759 * @beacon_time_stamp: beacon at on-air rise 2760 * @phy_flags: general phy flags: band, modulation, ... 2761 * @channel: channel number 2762 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2763 * @rate_n_flags: IWM_RATE_MCS_* 2764 * @byte_count: frame's byte-count 2765 * @frame_time: frame's time on the air, based on byte count and frame rate 2766 * calculation 2767 * @mac_active_msk: what MACs were active when the frame was received 2768 * 2769 * Before each Rx, the device sends this data. It contains PHY information 2770 * about the reception of the packet. 2771 */ 2772 struct iwm_rx_phy_info { 2773 uint8_t non_cfg_phy_cnt; 2774 uint8_t cfg_phy_cnt; 2775 uint8_t stat_id; 2776 uint8_t reserved1; 2777 uint32_t system_timestamp; 2778 uint64_t timestamp; 2779 uint32_t beacon_time_stamp; 2780 uint16_t phy_flags; 2781 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2782 uint16_t channel; 2783 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2784 uint32_t rate_n_flags; 2785 uint32_t byte_count; 2786 uint16_t mac_active_msk; 2787 uint16_t frame_time; 2788 } __packed; 2789 2790 struct iwm_rx_mpdu_res_start { 2791 uint16_t byte_count; 2792 uint16_t reserved; 2793 } __packed; 2794 2795 /** 2796 * Values to parse %iwm_rx_phy_info phy_flags 2797 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2798 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2799 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2800 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2801 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2802 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2803 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2804 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2805 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2806 */ 2807 #define IWM_RX_RES_PHY_FLAGS_BAND_24 (1 << 0) 2808 #define IWM_RX_RES_PHY_FLAGS_MOD_CCK (1 << 1) 2809 #define IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE (1 << 2) 2810 #define IWM_RX_RES_PHY_FLAGS_NARROW_BAND (1 << 3) 2811 #define IWM_RX_RES_PHY_FLAGS_ANTENNA (0x7 << 4) 2812 #define IWM_RX_RES_PHY_FLAGS_ANTENNA_POS 4 2813 #define IWM_RX_RES_PHY_FLAGS_AGG (1 << 7) 2814 #define IWM_RX_RES_PHY_FLAGS_OFDM_HT (1 << 8) 2815 #define IWM_RX_RES_PHY_FLAGS_OFDM_GF (1 << 9) 2816 #define IWM_RX_RES_PHY_FLAGS_OFDM_VHT (1 << 10) 2817 2818 /** 2819 * Values written by fw for each Rx packet 2820 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2821 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2822 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2823 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2824 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2825 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2826 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2827 * in the driver. 2828 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2829 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2830 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2831 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2832 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2833 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2834 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2835 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2836 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2837 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2838 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2839 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2840 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2841 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2842 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2843 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2844 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2845 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2846 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2847 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2848 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2849 */ 2850 #define IWM_RX_MPDU_RES_STATUS_CRC_OK (1 << 0) 2851 #define IWM_RX_MPDU_RES_STATUS_OVERRUN_OK (1 << 1) 2852 #define IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND (1 << 2) 2853 #define IWM_RX_MPDU_RES_STATUS_KEY_VALID (1 << 3) 2854 #define IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK (1 << 4) 2855 #define IWM_RX_MPDU_RES_STATUS_ICV_OK (1 << 5) 2856 #define IWM_RX_MPDU_RES_STATUS_MIC_OK (1 << 6) 2857 #define IWM_RX_MPDU_RES_STATUS_TTAK_OK (1 << 7) 2858 #define IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR (1 << 7) 2859 #define IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC (0 << 8) 2860 #define IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC (1 << 8) 2861 #define IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC (2 << 8) 2862 #define IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC (3 << 8) 2863 #define IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC (4 << 8) 2864 #define IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC (6 << 8) 2865 #define IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR (7 << 8) 2866 #define IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK (7 << 8) 2867 #define IWM_RX_MPDU_RES_STATUS_DEC_DONE (1 << 11) 2868 #define IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP (1 << 12) 2869 #define IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP (1 << 13) 2870 #define IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT (1 << 14) 2871 #define IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME (1 << 15) 2872 #define IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK (0x3F0000) 2873 #define IWM_RX_MPDU_RES_STATUS_STA_ID_MSK (0x1f000000) 2874 #define IWM_RX_MPDU_RES_STATUS_RRF_KILL (1 << 29) 2875 #define IWM_RX_MPDU_RES_STATUS_FILTERING_MSK (0xc00000) 2876 #define IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK (0xc0000000) 2877 2878 /** 2879 * struct iwm_radio_version_notif - information on the radio version 2880 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2881 * @radio_flavor: 2882 * @radio_step: 2883 * @radio_dash: 2884 */ 2885 struct iwm_radio_version_notif { 2886 uint32_t radio_flavor; 2887 uint32_t radio_step; 2888 uint32_t radio_dash; 2889 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2890 2891 #define IWM_CARD_ENABLED 0x00 2892 #define IWM_HW_CARD_DISABLED 0x01 2893 #define IWM_SW_CARD_DISABLED 0x02 2894 #define IWM_CT_KILL_CARD_DISABLED 0x04 2895 #define IWM_HALT_CARD_DISABLED 0x08 2896 #define IWM_CARD_DISABLED_MSK 0x0f 2897 #define IWM_CARD_IS_RX_ON 0x10 2898 2899 /** 2900 * struct iwm_radio_version_notif - information on the radio version 2901 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2902 * @flags: %iwm_card_state_flags 2903 */ 2904 struct iwm_card_state_notif { 2905 uint32_t flags; 2906 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2907 2908 /** 2909 * struct iwm_missed_beacons_notif - information on missed beacons 2910 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2911 * @mac_id: interface ID 2912 * @consec_missed_beacons_since_last_rx: number of consecutive missed 2913 * beacons since last RX. 2914 * @consec_missed_beacons: number of consecutive missed beacons 2915 * @num_expected_beacons: 2916 * @num_recvd_beacons: 2917 */ 2918 struct iwm_missed_beacons_notif { 2919 uint32_t mac_id; 2920 uint32_t consec_missed_beacons_since_last_rx; 2921 uint32_t consec_missed_beacons; 2922 uint32_t num_expected_beacons; 2923 uint32_t num_recvd_beacons; 2924 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2925 2926 /** 2927 * struct iwm_mfuart_load_notif - mfuart image version & status 2928 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2929 * @installed_ver: installed image version 2930 * @external_ver: external image version 2931 * @status: MFUART loading status 2932 * @duration: MFUART loading time 2933 */ 2934 struct iwm_mfuart_load_notif { 2935 uint32_t installed_ver; 2936 uint32_t external_ver; 2937 uint32_t status; 2938 uint32_t duration; 2939 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2940 2941 /** 2942 * struct iwm_set_calib_default_cmd - set default value for calibration. 2943 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2944 * @calib_index: the calibration to set value for 2945 * @length: of data 2946 * @data: the value to set for the calibration result 2947 */ 2948 struct iwm_set_calib_default_cmd { 2949 uint16_t calib_index; 2950 uint16_t length; 2951 uint8_t data[0]; 2952 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2953 2954 #define IWM_MAX_PORT_ID_NUM 2 2955 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2956 2957 /** 2958 * struct iwm_mcast_filter_cmd - configure multicast filter. 2959 * @filter_own: Set 1 to filter out multicast packets sent by station itself 2960 * @port_id: Multicast MAC addresses array specifier. This is a strange way 2961 * to identify network interface adopted in host-device IF. 2962 * It is used by FW as index in array of addresses. This array has 2963 * IWM_MAX_PORT_ID_NUM members. 2964 * @count: Number of MAC addresses in the array 2965 * @pass_all: Set 1 to pass all multicast packets. 2966 * @bssid: current association BSSID. 2967 * @addr_list: Place holder for array of MAC addresses. 2968 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2969 */ 2970 struct iwm_mcast_filter_cmd { 2971 uint8_t filter_own; 2972 uint8_t port_id; 2973 uint8_t count; 2974 uint8_t pass_all; 2975 uint8_t bssid[6]; 2976 uint8_t reserved[2]; 2977 uint8_t addr_list[0]; 2978 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2979 2980 struct iwm_statistics_dbg { 2981 uint32_t burst_check; 2982 uint32_t burst_count; 2983 uint32_t wait_for_silence_timeout_cnt; 2984 uint32_t reserved[3]; 2985 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2986 2987 struct iwm_statistics_div { 2988 uint32_t tx_on_a; 2989 uint32_t tx_on_b; 2990 uint32_t exec_time; 2991 uint32_t probe_time; 2992 uint32_t rssi_ant; 2993 uint32_t reserved2; 2994 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 2995 2996 struct iwm_statistics_general_common { 2997 uint32_t temperature; /* radio temperature */ 2998 uint32_t temperature_m; /* radio voltage */ 2999 struct iwm_statistics_dbg dbg; 3000 uint32_t sleep_time; 3001 uint32_t slots_out; 3002 uint32_t slots_idle; 3003 uint32_t ttl_timestamp; 3004 struct iwm_statistics_div div; 3005 uint32_t rx_enable_counter; 3006 /* 3007 * num_of_sos_states: 3008 * count the number of times we have to re-tune 3009 * in order to get out of bad PHY status 3010 */ 3011 uint32_t num_of_sos_states; 3012 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3013 3014 struct iwm_statistics_rx_non_phy { 3015 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 3016 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 3017 uint32_t non_bssid_frames; /* number of frames with BSSID that 3018 * doesn't belong to the STA BSSID */ 3019 uint32_t filtered_frames; /* count frames that were dumped in the 3020 * filtering process */ 3021 uint32_t non_channel_beacons; /* beacons with our bss id but not on 3022 * our serving channel */ 3023 uint32_t channel_beacons; /* beacons with our bss id and in our 3024 * serving channel */ 3025 uint32_t num_missed_bcon; /* number of missed beacons */ 3026 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3027 * ADC was in saturation */ 3028 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3029 * for INA */ 3030 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3031 uint32_t interference_data_flag; /* flag for interference data 3032 * availability. 1 when data is 3033 * available. */ 3034 uint32_t channel_load; /* counts RX Enable time in uSec */ 3035 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3036 * and CCK) counter */ 3037 uint32_t beacon_rssi_a; 3038 uint32_t beacon_rssi_b; 3039 uint32_t beacon_rssi_c; 3040 uint32_t beacon_energy_a; 3041 uint32_t beacon_energy_b; 3042 uint32_t beacon_energy_c; 3043 uint32_t num_bt_kills; 3044 uint32_t mac_id; 3045 uint32_t directed_data_mpdu; 3046 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3047 3048 struct iwm_statistics_rx_phy { 3049 uint32_t ina_cnt; 3050 uint32_t fina_cnt; 3051 uint32_t plcp_err; 3052 uint32_t crc32_err; 3053 uint32_t overrun_err; 3054 uint32_t early_overrun_err; 3055 uint32_t crc32_good; 3056 uint32_t false_alarm_cnt; 3057 uint32_t fina_sync_err_cnt; 3058 uint32_t sfd_timeout; 3059 uint32_t fina_timeout; 3060 uint32_t unresponded_rts; 3061 uint32_t rxe_frame_limit_overrun; 3062 uint32_t sent_ack_cnt; 3063 uint32_t sent_cts_cnt; 3064 uint32_t sent_ba_rsp_cnt; 3065 uint32_t dsp_self_kill; 3066 uint32_t mh_format_err; 3067 uint32_t re_acq_main_rssi_sum; 3068 uint32_t reserved; 3069 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 3070 3071 struct iwm_statistics_rx_ht_phy { 3072 uint32_t plcp_err; 3073 uint32_t overrun_err; 3074 uint32_t early_overrun_err; 3075 uint32_t crc32_good; 3076 uint32_t crc32_err; 3077 uint32_t mh_format_err; 3078 uint32_t agg_crc32_good; 3079 uint32_t agg_mpdu_cnt; 3080 uint32_t agg_cnt; 3081 uint32_t unsupport_mcs; 3082 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3083 3084 #define IWM_MAX_CHAINS 3 3085 3086 struct iwm_statistics_tx_non_phy_agg { 3087 uint32_t ba_timeout; 3088 uint32_t ba_reschedule_frames; 3089 uint32_t scd_query_agg_frame_cnt; 3090 uint32_t scd_query_no_agg; 3091 uint32_t scd_query_agg; 3092 uint32_t scd_query_mismatch; 3093 uint32_t frame_not_ready; 3094 uint32_t underrun; 3095 uint32_t bt_prio_kill; 3096 uint32_t rx_ba_rsp_cnt; 3097 int8_t txpower[IWM_MAX_CHAINS]; 3098 int8_t reserved; 3099 uint32_t reserved2; 3100 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3101 3102 struct iwm_statistics_tx_channel_width { 3103 uint32_t ext_cca_narrow_ch20[1]; 3104 uint32_t ext_cca_narrow_ch40[2]; 3105 uint32_t ext_cca_narrow_ch80[3]; 3106 uint32_t ext_cca_narrow_ch160[4]; 3107 uint32_t last_tx_ch_width_indx; 3108 uint32_t rx_detected_per_ch_width[4]; 3109 uint32_t success_per_ch_width[4]; 3110 uint32_t fail_per_ch_width[4]; 3111 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3112 3113 struct iwm_statistics_tx { 3114 uint32_t preamble_cnt; 3115 uint32_t rx_detected_cnt; 3116 uint32_t bt_prio_defer_cnt; 3117 uint32_t bt_prio_kill_cnt; 3118 uint32_t few_bytes_cnt; 3119 uint32_t cts_timeout; 3120 uint32_t ack_timeout; 3121 uint32_t expected_ack_cnt; 3122 uint32_t actual_ack_cnt; 3123 uint32_t dump_msdu_cnt; 3124 uint32_t burst_abort_next_frame_mismatch_cnt; 3125 uint32_t burst_abort_missing_next_frame_cnt; 3126 uint32_t cts_timeout_collision; 3127 uint32_t ack_or_ba_timeout_collision; 3128 struct iwm_statistics_tx_non_phy_agg agg; 3129 struct iwm_statistics_tx_channel_width channel_width; 3130 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3131 3132 3133 struct iwm_statistics_bt_activity { 3134 uint32_t hi_priority_tx_req_cnt; 3135 uint32_t hi_priority_tx_denied_cnt; 3136 uint32_t lo_priority_tx_req_cnt; 3137 uint32_t lo_priority_tx_denied_cnt; 3138 uint32_t hi_priority_rx_req_cnt; 3139 uint32_t hi_priority_rx_denied_cnt; 3140 uint32_t lo_priority_rx_req_cnt; 3141 uint32_t lo_priority_rx_denied_cnt; 3142 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3143 3144 struct iwm_statistics_general { 3145 struct iwm_statistics_general_common common; 3146 uint32_t beacon_filtered; 3147 uint32_t missed_beacons; 3148 int8_t beacon_filter_average_energy; 3149 int8_t beacon_filter_reason; 3150 int8_t beacon_filter_current_energy; 3151 int8_t beacon_filter_reserved; 3152 uint32_t beacon_filter_delta_time; 3153 struct iwm_statistics_bt_activity bt_activity; 3154 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3155 3156 struct iwm_statistics_rx { 3157 struct iwm_statistics_rx_phy ofdm; 3158 struct iwm_statistics_rx_phy cck; 3159 struct iwm_statistics_rx_non_phy general; 3160 struct iwm_statistics_rx_ht_phy ofdm_ht; 3161 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3162 3163 /* 3164 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3165 * 3166 * By default, uCode issues this notification after receiving a beacon 3167 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3168 * IWM_REPLY_STATISTICS_CMD 0x9c, above. 3169 * 3170 * Statistics counters continue to increment beacon after beacon, but are 3171 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 3172 * 0x9c with CLEAR_STATS bit set (see above). 3173 * 3174 * uCode also issues this notification during scans. uCode clears statistics 3175 * appropriately so that each notification contains statistics for only the 3176 * one channel that has just been scanned. 3177 */ 3178 3179 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 3180 uint32_t flag; 3181 struct iwm_statistics_rx rx; 3182 struct iwm_statistics_tx tx; 3183 struct iwm_statistics_general general; 3184 } __packed; 3185 3186 /*********************************** 3187 * Smart Fifo API 3188 ***********************************/ 3189 /* Smart Fifo state */ 3190 #define IWM_SF_LONG_DELAY_ON 0 /* should never be called by driver */ 3191 #define IWM_SF_FULL_ON 1 3192 #define IWM_SF_UNINIT 2 3193 #define IWM_SF_INIT_OFF 3 3194 #define IWM_SF_HW_NUM_STATES 4 3195 3196 /* Smart Fifo possible scenario */ 3197 #define IWM_SF_SCENARIO_SINGLE_UNICAST 0 3198 #define IWM_SF_SCENARIO_AGG_UNICAST 1 3199 #define IWM_SF_SCENARIO_MULTICAST 2 3200 #define IWM_SF_SCENARIO_BA_RESP 3 3201 #define IWM_SF_SCENARIO_TX_RESP 4 3202 #define IWM_SF_NUM_SCENARIO 5 3203 3204 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3205 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3206 3207 /* smart FIFO default values */ 3208 #define IWM_SF_W_MARK_SISO 4096 3209 #define IWM_SF_W_MARK_MIMO2 8192 3210 #define IWM_SF_W_MARK_MIMO3 6144 3211 #define IWM_SF_W_MARK_LEGACY 4096 3212 #define IWM_SF_W_MARK_SCAN 4096 3213 3214 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3215 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3216 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3217 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3218 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3219 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */ 3220 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3221 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3222 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3223 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3224 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3225 3226 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3227 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3228 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3229 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3230 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3231 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3232 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3233 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3234 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3235 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3236 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3237 3238 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3239 3240 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3241 3242 /** 3243 * Smart Fifo configuration command. 3244 * @state: smart fifo state, types listed in enum %iwm_sf_state. 3245 * @watermark: Minimum allowed availabe free space in RXF for transient state. 3246 * @long_delay_timeouts: aging and idle timer values for each scenario 3247 * in long delay state. 3248 * @full_on_timeouts: timer values for each scenario in full on state. 3249 */ 3250 struct iwm_sf_cfg_cmd { 3251 uint32_t state; 3252 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3253 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3254 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3255 } __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3256 3257 /* 3258 * The first MAC indices (starting from 0) 3259 * are available to the driver, AUX follows 3260 */ 3261 #define IWM_MAC_INDEX_AUX 4 3262 #define IWM_MAC_INDEX_MIN_DRIVER 0 3263 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 3264 3265 #define IWM_AC_BK 0 3266 #define IWM_AC_BE 1 3267 #define IWM_AC_VI 2 3268 #define IWM_AC_VO 3 3269 #define IWM_AC_NUM 4 3270 3271 /** 3272 * MAC context flags 3273 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3274 * this will require CCK RTS/CTS2self. 3275 * RTS/CTS will protect full burst time. 3276 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3277 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3278 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3279 */ 3280 #define IWM_MAC_PROT_FLG_TGG_PROTECT (1 << 3) 3281 #define IWM_MAC_PROT_FLG_HT_PROT (1 << 23) 3282 #define IWM_MAC_PROT_FLG_FAT_PROT (1 << 24) 3283 #define IWM_MAC_PROT_FLG_SELF_CTS_EN (1 << 30) 3284 3285 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3286 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3287 3288 /** 3289 * Supported MAC types 3290 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3291 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3292 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3293 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3294 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3295 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3296 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3297 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3298 * @IWM_FW_MAC_TYPE_GO: P2P GO 3299 * @IWM_FW_MAC_TYPE_TEST: ? 3300 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3301 */ 3302 #define IWM_FW_MAC_TYPE_FIRST 1 3303 #define IWM_FW_MAC_TYPE_AUX IWM_FW_MAC_TYPE_FIRST 3304 #define IWM_FW_MAC_TYPE_LISTENER 2 3305 #define IWM_FW_MAC_TYPE_PIBSS 3 3306 #define IWM_FW_MAC_TYPE_IBSS 4 3307 #define IWM_FW_MAC_TYPE_BSS_STA 5 3308 #define IWM_FW_MAC_TYPE_P2P_DEVICE 6 3309 #define IWM_FW_MAC_TYPE_P2P_STA 7 3310 #define IWM_FW_MAC_TYPE_GO 8 3311 #define IWM_FW_MAC_TYPE_TEST 9 3312 #define IWM_FW_MAC_TYPE_MAX IWM_FW_MAC_TYPE_TEST 3313 /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3314 3315 /** 3316 * TSF hw timer ID 3317 * @IWM_TSF_ID_A: use TSF A 3318 * @IWM_TSF_ID_B: use TSF B 3319 * @IWM_TSF_ID_C: use TSF C 3320 * @IWM_TSF_ID_D: use TSF D 3321 * @IWM_NUM_TSF_IDS: number of TSF timers available 3322 */ 3323 #define IWM_TSF_ID_A 0 3324 #define IWM_TSF_ID_B 1 3325 #define IWM_TSF_ID_C 2 3326 #define IWM_TSF_ID_D 3 3327 #define IWM_NUM_TSF_IDS 4 3328 /* IWM_TSF_ID_API_E_VER_1 */ 3329 3330 /** 3331 * struct iwm_mac_data_ap - configuration data for AP MAC context 3332 * @beacon_time: beacon transmit time in system time 3333 * @beacon_tsf: beacon transmit time in TSF 3334 * @bi: beacon interval in TU 3335 * @bi_reciprocal: 2^32 / bi 3336 * @dtim_interval: dtim transmit time in TU 3337 * @dtim_reciprocal: 2^32 / dtim_interval 3338 * @mcast_qid: queue ID for multicast traffic 3339 * @beacon_template: beacon template ID 3340 */ 3341 struct iwm_mac_data_ap { 3342 uint32_t beacon_time; 3343 uint64_t beacon_tsf; 3344 uint32_t bi; 3345 uint32_t bi_reciprocal; 3346 uint32_t dtim_interval; 3347 uint32_t dtim_reciprocal; 3348 uint32_t mcast_qid; 3349 uint32_t beacon_template; 3350 } __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3351 3352 /** 3353 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3354 * @beacon_time: beacon transmit time in system time 3355 * @beacon_tsf: beacon transmit time in TSF 3356 * @bi: beacon interval in TU 3357 * @bi_reciprocal: 2^32 / bi 3358 * @beacon_template: beacon template ID 3359 */ 3360 struct iwm_mac_data_ibss { 3361 uint32_t beacon_time; 3362 uint64_t beacon_tsf; 3363 uint32_t bi; 3364 uint32_t bi_reciprocal; 3365 uint32_t beacon_template; 3366 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3367 3368 /** 3369 * struct iwm_mac_data_sta - configuration data for station MAC context 3370 * @is_assoc: 1 for associated state, 0 otherwise 3371 * @dtim_time: DTIM arrival time in system time 3372 * @dtim_tsf: DTIM arrival time in TSF 3373 * @bi: beacon interval in TU, applicable only when associated 3374 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3375 * @dtim_interval: DTIM interval in TU, applicable only when associated 3376 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3377 * @listen_interval: in beacon intervals, applicable only when associated 3378 * @assoc_id: unique ID assigned by the AP during association 3379 */ 3380 struct iwm_mac_data_sta { 3381 uint32_t is_assoc; 3382 uint32_t dtim_time; 3383 uint64_t dtim_tsf; 3384 uint32_t bi; 3385 uint32_t bi_reciprocal; 3386 uint32_t dtim_interval; 3387 uint32_t dtim_reciprocal; 3388 uint32_t listen_interval; 3389 uint32_t assoc_id; 3390 uint32_t assoc_beacon_arrive_time; 3391 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3392 3393 /** 3394 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3395 * @ap: iwm_mac_data_ap struct with most config data 3396 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3397 * 0 indicates that there is no CT window. 3398 * @opp_ps_enabled: indicate that opportunistic PS allowed 3399 */ 3400 struct iwm_mac_data_go { 3401 struct iwm_mac_data_ap ap; 3402 uint32_t ctwin; 3403 uint32_t opp_ps_enabled; 3404 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3405 3406 /** 3407 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3408 * @sta: iwm_mac_data_sta struct with most config data 3409 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3410 * 0 indicates that there is no CT window. 3411 */ 3412 struct iwm_mac_data_p2p_sta { 3413 struct iwm_mac_data_sta sta; 3414 uint32_t ctwin; 3415 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3416 3417 /** 3418 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3419 * @stats_interval: interval in TU between statistics notifications to host. 3420 */ 3421 struct iwm_mac_data_pibss { 3422 uint32_t stats_interval; 3423 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3424 3425 /* 3426 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3427 * context. 3428 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3429 * other channels as well. This should be to true only in case that the 3430 * device is discoverable and there is an active GO. Note that setting this 3431 * field when not needed, will increase the number of interrupts and have 3432 * effect on the platform power, as this setting opens the Rx filters on 3433 * all macs. 3434 */ 3435 struct iwm_mac_data_p2p_dev { 3436 uint32_t is_disc_extended; 3437 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3438 3439 /** 3440 * MAC context filter flags 3441 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3442 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3443 * control frames to the host 3444 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3445 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3446 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3447 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3448 * (in station mode when associated) 3449 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3450 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3451 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3452 */ 3453 #define IWM_MAC_FILTER_IN_PROMISC (1 << 0) 3454 #define IWM_MAC_FILTER_IN_CONTROL_AND_MGMT (1 << 1) 3455 #define IWM_MAC_FILTER_ACCEPT_GRP (1 << 2) 3456 #define IWM_MAC_FILTER_DIS_DECRYPT (1 << 3) 3457 #define IWM_MAC_FILTER_DIS_GRP_DECRYPT (1 << 4) 3458 #define IWM_MAC_FILTER_IN_BEACON (1 << 6) 3459 #define IWM_MAC_FILTER_OUT_BCAST (1 << 8) 3460 #define IWM_MAC_FILTER_IN_CRC32 (1 << 11) 3461 #define IWM_MAC_FILTER_IN_PROBE_REQUEST (1 << 12) 3462 3463 /** 3464 * QoS flags 3465 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3466 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3467 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3468 * 3469 */ 3470 #define IWM_MAC_QOS_FLG_UPDATE_EDCA (1 << 0) 3471 #define IWM_MAC_QOS_FLG_TGN (1 << 1) 3472 #define IWM_MAC_QOS_FLG_TXOP_TYPE (1 << 4) 3473 3474 /** 3475 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3476 * @cw_min: Contention window, start value in numbers of slots. 3477 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3478 * @cw_max: Contention window, max value in numbers of slots. 3479 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3480 * @aifsn: Number of slots in Arbitration Interframe Space (before 3481 * performing random backoff timing prior to Tx). Device default 1. 3482 * @fifos_mask: FIFOs used by this MAC for this AC 3483 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3484 * 3485 * One instance of this config struct for each of 4 EDCA access categories 3486 * in struct iwm_qosparam_cmd. 3487 * 3488 * Device will automatically increase contention window by (2*CW) + 1 for each 3489 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3490 * value, to cap the CW value. 3491 */ 3492 struct iwm_ac_qos { 3493 uint16_t cw_min; 3494 uint16_t cw_max; 3495 uint8_t aifsn; 3496 uint8_t fifos_mask; 3497 uint16_t edca_txop; 3498 } __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3499 3500 /** 3501 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3502 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3503 * @id_and_color: ID and color of the MAC 3504 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3505 * @mac_type: one of IWM_FW_MAC_TYPE_* 3506 * @tsf_id: TSF HW timer, one of IWM_TSF_ID_* 3507 * @node_addr: MAC address 3508 * @bssid_addr: BSSID 3509 * @cck_rates: basic rates available for CCK 3510 * @ofdm_rates: basic rates available for OFDM 3511 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3512 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3513 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3514 * @filter_flags: combination of IWM_MAC_FILTER_* 3515 * @qos_flags: from IWM_MAC_QOS_FLG_* 3516 * @ac: one iwm_mac_qos configuration for each AC 3517 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3518 */ 3519 struct iwm_mac_ctx_cmd { 3520 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3521 uint32_t id_and_color; 3522 uint32_t action; 3523 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3524 uint32_t mac_type; 3525 uint32_t tsf_id; 3526 uint8_t node_addr[6]; 3527 uint16_t reserved_for_node_addr; 3528 uint8_t bssid_addr[6]; 3529 uint16_t reserved_for_bssid_addr; 3530 uint32_t cck_rates; 3531 uint32_t ofdm_rates; 3532 uint32_t protection_flags; 3533 uint32_t cck_short_preamble; 3534 uint32_t short_slot; 3535 uint32_t filter_flags; 3536 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3537 uint32_t qos_flags; 3538 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3539 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3540 union { 3541 struct iwm_mac_data_ap ap; 3542 struct iwm_mac_data_go go; 3543 struct iwm_mac_data_sta sta; 3544 struct iwm_mac_data_p2p_sta p2p_sta; 3545 struct iwm_mac_data_p2p_dev p2p_dev; 3546 struct iwm_mac_data_pibss pibss; 3547 struct iwm_mac_data_ibss ibss; 3548 }; 3549 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3550 3551 static inline uint32_t iwm_reciprocal(uint32_t v) 3552 { 3553 if (!v) 3554 return 0; 3555 return 0xFFFFFFFF / v; 3556 } 3557 3558 #define IWM_NONQOS_SEQ_GET 0x1 3559 #define IWM_NONQOS_SEQ_SET 0x2 3560 struct iwm_nonqos_seq_query_cmd { 3561 uint32_t get_set_flag; 3562 uint32_t mac_id_n_color; 3563 uint16_t value; 3564 uint16_t reserved; 3565 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3566 3567 /* Power Management Commands, Responses, Notifications */ 3568 3569 /* Radio LP RX Energy Threshold measured in dBm */ 3570 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3571 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3572 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3573 3574 /** 3575 * Masks for iwm_mac_power_cmd command flags 3576 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3577 * receiver and transmitter. '0' - does not allow. 3578 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3579 * '1' Driver enables PM (use rest of parameters) 3580 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3581 * '1' PM could sleep over DTIM till listen Interval. 3582 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3583 * access categories are both delivery and trigger enabled. 3584 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3585 * PBW Snoozing enabled 3586 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3587 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3588 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3589 * detection enablement 3590 */ 3591 #define IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0) 3592 #define IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK (1 << 1) 3593 #define IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK (1 << 2) 3594 #define IWM_POWER_FLAGS_SNOOZE_ENA_MSK (1 << 5) 3595 #define IWM_POWER_FLAGS_BT_SCO_ENA (1 << 8) 3596 #define IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK (1 << 9) 3597 #define IWM_POWER_FLAGS_LPRX_ENA_MSK (1 << 11) 3598 #define IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK (1 << 12) 3599 3600 #define IWM_POWER_VEC_SIZE 5 3601 3602 /** 3603 * Masks for device power command flags 3604 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: 3605 * '1' Allow to save power by turning off receiver and transmitter. 3606 * '0' Do not allow. This flag should be always set to '1' unless 3607 * one needs to disable actual power down for debug purposes. 3608 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: 3609 * '1' CAM (Continuous Active Mode) is set, power management is disabled. 3610 * '0' Power management is enabled, one of the power schemes is applied. 3611 */ 3612 #define IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0) 3613 #define IWM_DEVICE_POWER_FLAGS_CAM_MSK (1 << 13) 3614 3615 /** 3616 * struct iwm_device_power_cmd - device wide power command. 3617 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3618 * 3619 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3620 */ 3621 struct iwm_device_power_cmd { 3622 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3623 uint16_t flags; 3624 uint16_t reserved; 3625 } __packed; 3626 3627 /** 3628 * struct iwm_mac_power_cmd - New power command containing uAPSD support 3629 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3630 * @id_and_color: MAC contex identifier 3631 * @flags: Power table command flags from POWER_FLAGS_* 3632 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3633 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3634 * set regardless of power scheme or current power state. 3635 * FW use this value also when PM is disabled. 3636 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3637 * PSM transition - legacy PM 3638 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3639 * PSM transition - legacy PM 3640 * @sleep_interval: not in use 3641 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3642 * is set. For example, if it is required to skip over 3643 * one DTIM, this value need to be set to 2 (DTIM periods). 3644 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3645 * PSM transition - uAPSD 3646 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3647 * PSM transition - uAPSD 3648 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3649 * Default: 80dbm 3650 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3651 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3652 * from the AP [msec] 3653 * @snooze_window: A window of time in which PBW snoozing insures that all 3654 * packets received. It is also the minimum time from last 3655 * received unicast RX packet, before client stops snoozing 3656 * for data. [msec] 3657 * @snooze_step: TBD 3658 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3659 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3660 * each corresponding AC. 3661 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3662 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3663 * values. 3664 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3665 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3666 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3667 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3668 * @limited_ps_threshold: 3669 */ 3670 struct iwm_mac_power_cmd { 3671 /* CONTEXT_DESC_API_T_VER_1 */ 3672 uint32_t id_and_color; 3673 3674 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3675 uint16_t flags; 3676 uint16_t keep_alive_seconds; 3677 uint32_t rx_data_timeout; 3678 uint32_t tx_data_timeout; 3679 uint32_t rx_data_timeout_uapsd; 3680 uint32_t tx_data_timeout_uapsd; 3681 uint8_t lprx_rssi_threshold; 3682 uint8_t skip_dtim_periods; 3683 uint16_t snooze_interval; 3684 uint16_t snooze_window; 3685 uint8_t snooze_step; 3686 uint8_t qndp_tid; 3687 uint8_t uapsd_ac_flags; 3688 uint8_t uapsd_max_sp; 3689 uint8_t heavy_tx_thld_packets; 3690 uint8_t heavy_rx_thld_packets; 3691 uint8_t heavy_tx_thld_percentage; 3692 uint8_t heavy_rx_thld_percentage; 3693 uint8_t limited_ps_threshold; 3694 uint8_t reserved; 3695 } __packed; 3696 3697 #define IWM_DEFAULT_PS_TX_DATA_TIMEOUT (100 * 1000) 3698 #define IWM_DEFAULT_PS_RX_DATA_TIMEOUT (100 * 1000) 3699 3700 /* 3701 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3702 * associated AP is identified as improperly implementing uAPSD protocol. 3703 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3704 * @sta_id: index of station in uCode's station table - associated AP ID in 3705 * this context. 3706 */ 3707 struct iwm_uapsd_misbehaving_ap_notif { 3708 uint32_t sta_id; 3709 uint8_t mac_id; 3710 uint8_t reserved[3]; 3711 } __packed; 3712 3713 /** 3714 * struct iwm_beacon_filter_cmd 3715 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3716 * @id_and_color: MAC contex identifier 3717 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3718 * to driver if delta in Energy values calculated for this and last 3719 * passed beacon is greater than this threshold. Zero value means that 3720 * the Energy change is ignored for beacon filtering, and beacon will 3721 * not be forced to be sent to driver regardless of this delta. Typical 3722 * energy delta 5dB. 3723 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3724 * Send beacon to driver if delta in Energy values calculated for this 3725 * and last passed beacon is greater than this threshold. Zero value 3726 * means that the Energy change is ignored for beacon filtering while in 3727 * Roaming state, typical energy delta 1dB. 3728 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3729 * calculated for current beacon is less than the threshold, use 3730 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3731 * Threshold. Typical energy threshold is -72dBm. 3732 * @bf_temp_threshold: This threshold determines the type of temperature 3733 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3734 * If the current temperature is above this threshold - Fast filter 3735 * will be used, If the current temperature is below this threshold - 3736 * Slow filter will be used. 3737 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3738 * calculated for this and the last passed beacon is greater than this 3739 * threshold. Zero value means that the temperature change is ignored for 3740 * beacon filtering; beacons will not be forced to be sent to driver 3741 * regardless of whether its temerature has been changed. 3742 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3743 * calculated for this and the last passed beacon is greater than this 3744 * threshold. Zero value means that the temperature change is ignored for 3745 * beacon filtering; beacons will not be forced to be sent to driver 3746 * regardless of whether its temerature has been changed. 3747 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3748 * @bf_escape_timer: Send beacons to driver if no beacons were passed 3749 * for a specific period of time. Units: Beacons. 3750 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3751 * for a longer period of time then this escape-timeout. Units: Beacons. 3752 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3753 */ 3754 struct iwm_beacon_filter_cmd { 3755 uint32_t bf_energy_delta; 3756 uint32_t bf_roaming_energy_delta; 3757 uint32_t bf_roaming_state; 3758 uint32_t bf_temp_threshold; 3759 uint32_t bf_temp_fast_filter; 3760 uint32_t bf_temp_slow_filter; 3761 uint32_t bf_enable_beacon_filter; 3762 uint32_t bf_debug_flag; 3763 uint32_t bf_escape_timer; 3764 uint32_t ba_escape_timer; 3765 uint32_t ba_enable_beacon_abort; 3766 } __packed; 3767 3768 /* Beacon filtering and beacon abort */ 3769 #define IWM_BF_ENERGY_DELTA_DEFAULT 5 3770 #define IWM_BF_ENERGY_DELTA_MAX 255 3771 #define IWM_BF_ENERGY_DELTA_MIN 0 3772 3773 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3774 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3775 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3776 3777 #define IWM_BF_ROAMING_STATE_DEFAULT 72 3778 #define IWM_BF_ROAMING_STATE_MAX 255 3779 #define IWM_BF_ROAMING_STATE_MIN 0 3780 3781 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3782 #define IWM_BF_TEMP_THRESHOLD_MAX 255 3783 #define IWM_BF_TEMP_THRESHOLD_MIN 0 3784 3785 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3786 #define IWM_BF_TEMP_FAST_FILTER_MAX 255 3787 #define IWM_BF_TEMP_FAST_FILTER_MIN 0 3788 3789 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3790 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3791 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3792 3793 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3794 3795 #define IWM_BF_DEBUG_FLAG_DEFAULT 0 3796 3797 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3798 #define IWM_BF_ESCAPE_TIMER_MAX 1024 3799 #define IWM_BF_ESCAPE_TIMER_MIN 0 3800 3801 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3802 #define IWM_BA_ESCAPE_TIMER_D3 9 3803 #define IWM_BA_ESCAPE_TIMER_MAX 1024 3804 #define IWM_BA_ESCAPE_TIMER_MIN 0 3805 3806 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3807 3808 #define IWM_BF_CMD_CONFIG_DEFAULTS \ 3809 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3810 .bf_roaming_energy_delta = \ 3811 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3812 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3813 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3814 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3815 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3816 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3817 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3818 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3819 3820 /* uCode API values for HT/VHT bit rates */ 3821 #define IWM_RATE_HT_SISO_MCS_0_PLCP 0 3822 #define IWM_RATE_HT_SISO_MCS_1_PLCP 1 3823 #define IWM_RATE_HT_SISO_MCS_2_PLCP 2 3824 #define IWM_RATE_HT_SISO_MCS_3_PLCP 3 3825 #define IWM_RATE_HT_SISO_MCS_4_PLCP 4 3826 #define IWM_RATE_HT_SISO_MCS_5_PLCP 5 3827 #define IWM_RATE_HT_SISO_MCS_6_PLCP 6 3828 #define IWM_RATE_HT_SISO_MCS_7_PLCP 7 3829 #define IWM_RATE_HT_MIMO2_MCS_0_PLCP 0x8 3830 #define IWM_RATE_HT_MIMO2_MCS_1_PLCP 0x9 3831 #define IWM_RATE_HT_MIMO2_MCS_2_PLCP 0xA 3832 #define IWM_RATE_HT_MIMO2_MCS_3_PLCP 0xB 3833 #define IWM_RATE_HT_MIMO2_MCS_4_PLCP 0xC 3834 #define IWM_RATE_HT_MIMO2_MCS_5_PLCP 0xD 3835 #define IWM_RATE_HT_MIMO2_MCS_6_PLCP 0xE 3836 #define IWM_RATE_HT_MIMO2_MCS_7_PLCP 0xF 3837 #define IWM_RATE_VHT_SISO_MCS_0_PLCP 0 3838 #define IWM_RATE_VHT_SISO_MCS_1_PLCP 1 3839 #define IWM_RATE_VHT_SISO_MCS_2_PLCP 2 3840 #define IWM_RATE_VHT_SISO_MCS_3_PLCP 3 3841 #define IWM_RATE_VHT_SISO_MCS_4_PLCP 4 3842 #define IWM_RATE_VHT_SISO_MCS_5_PLCP 5 3843 #define IWM_RATE_VHT_SISO_MCS_6_PLCP 6 3844 #define IWM_RATE_VHT_SISO_MCS_7_PLCP 7 3845 #define IWM_RATE_VHT_SISO_MCS_8_PLCP 8 3846 #define IWM_RATE_VHT_SISO_MCS_9_PLCP 9 3847 #define IWM_RATE_VHT_MIMO2_MCS_0_PLCP 0x10 3848 #define IWM_RATE_VHT_MIMO2_MCS_1_PLCP 0x11 3849 #define IWM_RATE_VHT_MIMO2_MCS_2_PLCP 0x12 3850 #define IWM_RATE_VHT_MIMO2_MCS_3_PLCP 0x13 3851 #define IWM_RATE_VHT_MIMO2_MCS_4_PLCP 0x14 3852 #define IWM_RATE_VHT_MIMO2_MCS_5_PLCP 0x15 3853 #define IWM_RATE_VHT_MIMO2_MCS_6_PLCP 0x16 3854 #define IWM_RATE_VHT_MIMO2_MCS_7_PLCP 0x17 3855 #define IWM_RATE_VHT_MIMO2_MCS_8_PLCP 0x18 3856 #define IWM_RATE_VHT_MIMO2_MCS_9_PLCP 0x19 3857 #define IWM_RATE_HT_SISO_MCS_INV_PLCP 0x20 3858 #define IWM_RATE_HT_MIMO2_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 3859 #define IWM_RATE_VHT_SISO_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 3860 #define IWM_RATE_VHT_MIMO2_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 3861 #define IWM_RATE_HT_SISO_MCS_8_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 3862 #define IWM_RATE_HT_SISO_MCS_9_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 3863 #define IWM_RATE_HT_MIMO2_MCS_8_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 3864 #define IWM_RATE_HT_MIMO2_MCS_9_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP 3865 3866 /* 3867 * These serve as indexes into struct iwm_rate iwm_rates[IWM_RIDX_MAX]. 3868 */ 3869 enum { 3870 IWM_RATE_1M_INDEX = 0, 3871 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3872 IWM_RATE_2M_INDEX, 3873 IWM_RATE_5M_INDEX, 3874 IWM_RATE_11M_INDEX, 3875 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3876 IWM_RATE_6M_INDEX, 3877 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3878 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3879 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3880 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3881 IWM_RATE_9M_INDEX, 3882 IWM_RATE_12M_INDEX, 3883 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3884 IWM_RATE_18M_INDEX, 3885 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3886 IWM_RATE_24M_INDEX, 3887 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3888 IWM_RATE_36M_INDEX, 3889 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3890 IWM_RATE_48M_INDEX, 3891 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3892 IWM_RATE_54M_INDEX, 3893 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3894 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3895 IWM_RATE_60M_INDEX, 3896 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3897 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3898 IWM_RATE_MCS_8_INDEX, 3899 IWM_RATE_MCS_9_INDEX, 3900 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3901 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3902 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3903 }; 3904 3905 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3906 3907 /* fw API values for legacy bit rates, both OFDM and CCK */ 3908 #define IWM_RATE_6M_PLCP 13 3909 #define IWM_RATE_9M_PLCP 15 3910 #define IWM_RATE_12M_PLCP 5 3911 #define IWM_RATE_18M_PLCP 7 3912 #define IWM_RATE_24M_PLCP 9 3913 #define IWM_RATE_36M_PLCP 11 3914 #define IWM_RATE_48M_PLCP 1 3915 #define IWM_RATE_54M_PLCP 3 3916 #define IWM_RATE_1M_PLCP 10 3917 #define IWM_RATE_2M_PLCP 20 3918 #define IWM_RATE_5M_PLCP 55 3919 #define IWM_RATE_11M_PLCP 110 3920 #define IWM_RATE_INVM_PLCP 0xff 3921 3922 /* 3923 * rate_n_flags bit fields 3924 * 3925 * The 32-bit value has different layouts in the low 8 bites depending on the 3926 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3927 * for CCK and OFDM). 3928 * 3929 * High-throughput (HT) rate format 3930 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3931 * Very High-throughput (VHT) rate format 3932 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3933 * Legacy OFDM rate format for bits 7:0 3934 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3935 * Legacy CCK rate format for bits 7:0: 3936 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3937 */ 3938 3939 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 3940 #define IWM_RATE_MCS_HT_POS 8 3941 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3942 3943 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3944 #define IWM_RATE_MCS_CCK_POS 9 3945 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3946 3947 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3948 #define IWM_RATE_MCS_VHT_POS 26 3949 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3950 3951 3952 /* 3953 * High-throughput (HT) rate format for bits 7:0 3954 * 3955 * 2-0: MCS rate base 3956 * 0) 6 Mbps 3957 * 1) 12 Mbps 3958 * 2) 18 Mbps 3959 * 3) 24 Mbps 3960 * 4) 36 Mbps 3961 * 5) 48 Mbps 3962 * 6) 54 Mbps 3963 * 7) 60 Mbps 3964 * 4-3: 0) Single stream (SISO) 3965 * 1) Dual stream (MIMO) 3966 * 2) Triple stream (MIMO) 3967 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 3968 * (bits 7-6 are zero) 3969 * 3970 * Together the low 5 bits work out to the MCS index because we don't 3971 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 3972 * streams and 16-23 have three streams. We could also support MCS 32 3973 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 3974 */ 3975 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 3976 #define IWM_RATE_HT_MCS_NSS_POS 3 3977 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 3978 3979 /* Bit 10: (1) Use Green Field preamble */ 3980 #define IWM_RATE_HT_MCS_GF_POS 10 3981 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 3982 3983 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 3984 3985 /* 3986 * Very High-throughput (VHT) rate format for bits 7:0 3987 * 3988 * 3-0: VHT MCS (0-9) 3989 * 5-4: number of streams - 1: 3990 * 0) Single stream (SISO) 3991 * 1) Dual stream (MIMO) 3992 * 2) Triple stream (MIMO) 3993 */ 3994 3995 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 3996 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 3997 #define IWM_RATE_VHT_MCS_NSS_POS 4 3998 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 3999 4000 /* 4001 * Legacy OFDM rate format for bits 7:0 4002 * 4003 * 3-0: 0xD) 6 Mbps 4004 * 0xF) 9 Mbps 4005 * 0x5) 12 Mbps 4006 * 0x7) 18 Mbps 4007 * 0x9) 24 Mbps 4008 * 0xB) 36 Mbps 4009 * 0x1) 48 Mbps 4010 * 0x3) 54 Mbps 4011 * (bits 7-4 are 0) 4012 * 4013 * Legacy CCK rate format for bits 7:0: 4014 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 4015 * 4016 * 6-0: 10) 1 Mbps 4017 * 20) 2 Mbps 4018 * 55) 5.5 Mbps 4019 * 110) 11 Mbps 4020 * (bit 7 is 0) 4021 */ 4022 #define IWM_RATE_LEGACY_RATE_MSK 0xff 4023 4024 4025 /* 4026 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4027 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4028 */ 4029 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4030 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4031 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4032 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4033 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4034 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4035 4036 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4037 #define IWM_RATE_MCS_SGI_POS 13 4038 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4039 4040 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4041 #define IWM_RATE_MCS_ANT_POS 14 4042 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4043 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4044 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4045 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4046 IWM_RATE_MCS_ANT_B_MSK) 4047 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4048 IWM_RATE_MCS_ANT_C_MSK) 4049 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4050 #define IWM_RATE_MCS_ANT_NUM 3 4051 4052 /* Bit 17-18: (0) SS, (1) SS*2 */ 4053 #define IWM_RATE_MCS_STBC_POS 17 4054 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4055 4056 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4057 #define IWM_RATE_MCS_BF_POS 19 4058 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4059 4060 /* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4061 #define IWM_RATE_MCS_ZLF_POS 20 4062 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4063 4064 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4065 #define IWM_RATE_MCS_DUP_POS 24 4066 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4067 4068 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4069 #define IWM_RATE_MCS_LDPC_POS 27 4070 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4071 4072 4073 /* Link Quality definitions */ 4074 4075 /* # entries in rate scale table to support Tx retries */ 4076 #define IWM_LQ_MAX_RETRY_NUM 16 4077 4078 /* Link quality command flags bit fields */ 4079 4080 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 4081 #define IWM_LQ_FLAG_USE_RTS_POS 0 4082 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4083 4084 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4085 #define IWM_LQ_FLAG_COLOR_POS 1 4086 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4087 4088 /* Bit 4-5: Tx RTS BW Signalling 4089 * (0) No RTS BW signalling 4090 * (1) Static BW signalling 4091 * (2) Dynamic BW signalling 4092 */ 4093 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4094 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4095 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4096 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4097 4098 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4099 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4100 */ 4101 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4102 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4103 4104 /* Antenna flags. */ 4105 #define IWM_ANT_A (1 << 0) 4106 #define IWM_ANT_B (1 << 1) 4107 #define IWM_ANT_C (1 << 2) 4108 /* Shortcuts. */ 4109 #define IWM_ANT_AB (IWM_ANT_A | IWM_ANT_B) 4110 #define IWM_ANT_BC (IWM_ANT_B | IWM_ANT_C) 4111 #define IWM_ANT_ABC (IWM_ANT_A | IWM_ANT_B | IWM_ANT_C) 4112 4113 /** 4114 * struct iwm_lq_cmd - link quality command 4115 * @sta_id: station to update 4116 * @control: not used 4117 * @flags: combination of IWM_LQ_FLAG_* 4118 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4119 * and SISO rates 4120 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4121 * Should be IWM_ANT_[ABC] 4122 * @dual_stream_ant_msk: best antennas for MIMO, combination of IWM_ANT_[ABC] 4123 * @initial_rate_index: first index from rs_table per AC category 4124 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4125 * value of 100 is one usec. Range is 100 to 8000 4126 * @agg_disable_start_th: try-count threshold for starting aggregation. 4127 * If a frame has higher try-count, it should not be selected for 4128 * starting an aggregation sequence. 4129 * @agg_frame_cnt_limit: max frame count in an aggregation. 4130 * 0: no limit 4131 * 1: no aggregation (one frame per aggregation) 4132 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4133 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4134 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4135 * @bf_params: beam forming params, currently not used 4136 */ 4137 struct iwm_lq_cmd { 4138 uint8_t sta_id; 4139 uint8_t reserved1; 4140 uint16_t control; 4141 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4142 uint8_t flags; 4143 uint8_t mimo_delim; 4144 uint8_t single_stream_ant_msk; 4145 uint8_t dual_stream_ant_msk; 4146 uint8_t initial_rate_index[IWM_AC_NUM]; 4147 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4148 uint16_t agg_time_limit; 4149 uint8_t agg_disable_start_th; 4150 uint8_t agg_frame_cnt_limit; 4151 uint32_t reserved2; 4152 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4153 uint32_t bf_params; 4154 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4155 4156 /** 4157 * bitmasks for tx_flags in TX command 4158 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4159 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4160 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4161 * Otherwise, use rate_n_flags from the TX command 4162 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4163 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4164 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4165 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4166 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4167 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4168 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4169 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4170 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4171 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4172 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4173 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4174 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4175 * Should be set for beacons and probe responses 4176 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4177 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4178 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4179 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4180 * Should be set for 26/30 length MAC headers 4181 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4182 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4183 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4184 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4185 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4186 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4187 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4188 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4189 */ 4190 #define IWM_TX_CMD_FLG_PROT_REQUIRE (1 << 0) 4191 #define IWM_TX_CMD_FLG_ACK (1 << 3) 4192 #define IWM_TX_CMD_FLG_STA_RATE (1 << 4) 4193 #define IWM_TX_CMD_FLG_BA (1 << 5) 4194 #define IWM_TX_CMD_FLG_BAR (1 << 6) 4195 #define IWM_TX_CMD_FLG_TXOP_PROT (1 << 7) 4196 #define IWM_TX_CMD_FLG_VHT_NDPA (1 << 8) 4197 #define IWM_TX_CMD_FLG_HT_NDPA (1 << 9) 4198 #define IWM_TX_CMD_FLG_CSI_FDBK2HOST (1 << 10) 4199 #define IWM_TX_CMD_FLG_BT_DIS (1 << 12) 4200 #define IWM_TX_CMD_FLG_SEQ_CTL (1 << 13) 4201 #define IWM_TX_CMD_FLG_MORE_FRAG (1 << 14) 4202 #define IWM_TX_CMD_FLG_NEXT_FRAME (1 << 15) 4203 #define IWM_TX_CMD_FLG_TSF (1 << 16) 4204 #define IWM_TX_CMD_FLG_CALIB (1 << 17) 4205 #define IWM_TX_CMD_FLG_KEEP_SEQ_CTL (1 << 18) 4206 #define IWM_TX_CMD_FLG_AGG_START (1 << 19) 4207 #define IWM_TX_CMD_FLG_MH_PAD (1 << 20) 4208 #define IWM_TX_CMD_FLG_RESP_TO_DRV (1 << 21) 4209 #define IWM_TX_CMD_FLG_CCMP_AGG (1 << 22) 4210 #define IWM_TX_CMD_FLG_TKIP_MIC_DONE (1 << 23) 4211 #define IWM_TX_CMD_FLG_DUR (1 << 25) 4212 #define IWM_TX_CMD_FLG_FW_DROP (1 << 26) 4213 #define IWM_TX_CMD_FLG_EXEC_PAPD (1 << 27) 4214 #define IWM_TX_CMD_FLG_PAPD_TYPE (1 << 28) 4215 #define IWM_TX_CMD_FLG_HCCA_CHUNK (1 << 31) 4216 /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4217 4218 /* 4219 * TX command security control 4220 */ 4221 #define IWM_TX_CMD_SEC_WEP 0x01 4222 #define IWM_TX_CMD_SEC_CCM 0x02 4223 #define IWM_TX_CMD_SEC_TKIP 0x03 4224 #define IWM_TX_CMD_SEC_EXT 0x04 4225 #define IWM_TX_CMD_SEC_MSK 0x07 4226 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4227 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4228 #define IWM_TX_CMD_SEC_KEY128 0x08 4229 4230 /* TODO: how does these values are OK with only 16 bit variable??? */ 4231 /* 4232 * TX command next frame info 4233 * 4234 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4235 * bit 3 - immediate ACK required 4236 * bit 4 - rate is taken from STA table 4237 * bit 5 - frame belongs to BA stream 4238 * bit 6 - immediate BA response expected 4239 * bit 7 - unused 4240 * bits 8:15 - Station ID 4241 * bits 16:31 - rate 4242 */ 4243 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4244 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4245 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4246 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4247 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4248 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4249 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4250 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4251 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4252 4253 /* 4254 * TX command Frame life time in us - to be written in pm_frame_timeout 4255 */ 4256 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4257 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4258 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4259 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4260 4261 /* 4262 * TID for non QoS frames - to be written in tid_tspec 4263 */ 4264 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4265 4266 /* 4267 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4268 */ 4269 #define IWM_DEFAULT_TX_RETRY 15 4270 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4271 #define IWM_RTS_DFAULT_RETRY_LIMIT 60 4272 #define IWM_BAR_DFAULT_RETRY_LIMIT 60 4273 #define IWM_LOW_RETRY_LIMIT 7 4274 4275 /* TODO: complete documentation for try_cnt and btkill_cnt */ 4276 /** 4277 * struct iwm_tx_cmd - TX command struct to FW 4278 * ( IWM_TX_CMD = 0x1c ) 4279 * @len: in bytes of the payload, see below for details 4280 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4281 * Used for fragmentation and bursting, but not in 11n aggregation. 4282 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4283 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4284 * cleared. Combination of IWM_RATE_MCS_* 4285 * @sta_id: index of destination station in FW station table 4286 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4287 * @initial_rate_index: index into the rate table for initial TX attempt. 4288 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4289 * @key: security key 4290 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4291 * @life_time: frame life time (usecs??) 4292 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4293 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4294 * @dram_msb_ptr: upper bits of the scratch physical address 4295 * @rts_retry_limit: max attempts for RTS 4296 * @data_retry_limit: max attempts to send the data packet 4297 * @tid_spec: TID/tspec 4298 * @pm_frame_timeout: PM TX frame timeout 4299 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4300 * specified by HCCA protocol 4301 * 4302 * The byte count (both len and next_frame_len) includes MAC header 4303 * (24/26/30/32 bytes) 4304 * + 2 bytes pad if 26/30 header size 4305 * + 8 byte IV for CCM or TKIP (not used for WEP) 4306 * + Data payload 4307 * + 8-byte MIC (not used for CCM/WEP) 4308 * It does not include post-MAC padding, i.e., 4309 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4310 * Range of len: 14-2342 bytes. 4311 * 4312 * After the struct fields the MAC header is placed, plus any padding, 4313 * and then the actial payload. 4314 */ 4315 struct iwm_tx_cmd { 4316 uint16_t len; 4317 uint16_t next_frame_len; 4318 uint32_t tx_flags; 4319 struct { 4320 uint8_t try_cnt; 4321 uint8_t btkill_cnt; 4322 uint16_t reserved; 4323 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4324 uint32_t rate_n_flags; 4325 uint8_t sta_id; 4326 uint8_t sec_ctl; 4327 uint8_t initial_rate_index; 4328 uint8_t reserved2; 4329 uint8_t key[16]; 4330 uint16_t next_frame_flags; 4331 uint16_t reserved3; 4332 uint32_t life_time; 4333 uint32_t dram_lsb_ptr; 4334 uint8_t dram_msb_ptr; 4335 uint8_t rts_retry_limit; 4336 uint8_t data_retry_limit; 4337 uint8_t tid_tspec; 4338 uint16_t pm_frame_timeout; 4339 uint16_t driver_txop; 4340 uint8_t payload[0]; 4341 struct ieee80211_frame hdr[0]; 4342 } __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4343 4344 /* 4345 * TX response related data 4346 */ 4347 4348 /* 4349 * status that is returned by the fw after attempts to Tx 4350 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4351 * STA table 4352 * Valid only if frame_count =1 4353 */ 4354 #define IWM_TX_STATUS_MSK 0x000000ff 4355 #define IWM_TX_STATUS_SUCCESS 0x01 4356 #define IWM_TX_STATUS_DIRECT_DONE 0x02 4357 /* postpone TX */ 4358 #define IWM_TX_STATUS_POSTPONE_DELAY 0x40 4359 #define IWM_TX_STATUS_POSTPONE_FEW_BYTES 0x41 4360 #define IWM_TX_STATUS_POSTPONE_BT_PRIO 0x42 4361 #define IWM_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43 4362 #define IWM_TX_STATUS_POSTPONE_CALC_TTAK 0x44 4363 /* abort TX */ 4364 #define IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81 4365 #define IWM_TX_STATUS_FAIL_SHORT_LIMIT 0x82 4366 #define IWM_TX_STATUS_FAIL_LONG_LIMIT 0x83 4367 #define IWM_TX_STATUS_FAIL_UNDERRUN 0x84 4368 #define IWM_TX_STATUS_FAIL_DRAIN_FLOW 0x85 4369 #define IWM_TX_STATUS_FAIL_RFKILL_FLUSH 0x86 4370 #define IWM_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 4371 #define IWM_TX_STATUS_FAIL_DEST_PS 0x88 4372 #define IWM_TX_STATUS_FAIL_HOST_ABORTED 0x89 4373 #define IWM_TX_STATUS_FAIL_BT_RETRY 0x8a 4374 #define IWM_TX_STATUS_FAIL_STA_INVALID 0x8b 4375 #define IWM_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 4376 #define IWM_TX_STATUS_FAIL_TID_DISABLE 0x8d 4377 #define IWM_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e 4378 #define IWM_TX_STATUS_FAIL_SMALL_CF_POLL 0x8f 4379 #define IWM_TX_STATUS_FAIL_FW_DROP 0x90 4380 #define IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH 0x91 4381 #define IWM_TX_STATUS_INTERNAL_ABORT 0x92 4382 #define IWM_TX_MODE_MSK 0x00000f00 4383 #define IWM_TX_MODE_NO_BURST 0x00000000 4384 #define IWM_TX_MODE_IN_BURST_SEQ 0x00000100 4385 #define IWM_TX_MODE_FIRST_IN_BURST 0x00000200 4386 #define IWM_TX_QUEUE_NUM_MSK 0x0001f000 4387 #define IWM_TX_NARROW_BW_MSK 0x00060000 4388 #define IWM_TX_NARROW_BW_1DIV2 0x00020000 4389 #define IWM_TX_NARROW_BW_1DIV4 0x00040000 4390 #define IWM_TX_NARROW_BW_1DIV8 0x00060000 4391 4392 /* 4393 * TX aggregation status 4394 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4395 * occur if tx failed for this frame when it was a member of a previous 4396 * aggregation block). If rate scaling is used, retry count indicates the 4397 * rate table entry used for all frames in the new agg. 4398 * @IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4399 * this frame 4400 */ 4401 #define IWM_AGG_TX_STATE_STATUS_MSK 0x0fff 4402 #define IWM_AGG_TX_STATE_TRANSMITTED 0x0000 4403 #define IWM_AGG_TX_STATE_UNDERRUN 0x0001 4404 #define IWM_AGG_TX_STATE_BT_PRIO 0x0002 4405 #define IWM_AGG_TX_STATE_FEW_BYTES 0x0004 4406 #define IWM_AGG_TX_STATE_ABORT 0x0008 4407 #define IWM_AGG_TX_STATE_LAST_SENT_TTL 0x0010 4408 #define IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020 4409 #define IWM_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040 4410 #define IWM_AGG_TX_STATE_SCD_QUERY 0x0080 4411 #define IWM_AGG_TX_STATE_TEST_BAD_CRC32 0x0100 4412 #define IWM_AGG_TX_STATE_RESPONSE 0x01ff 4413 #define IWM_AGG_TX_STATE_DUMP_TX 0x0200 4414 #define IWM_AGG_TX_STATE_DELAY_TX 0x0400 4415 #define IWM_AGG_TX_STATE_TRY_CNT_POS 12 4416 #define IWM_AGG_TX_STATE_TRY_CNT_MSK (0xf << IWM_AGG_TX_STATE_TRY_CNT_POS) 4417 4418 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4419 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4420 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4421 4422 /* 4423 * The mask below describes a status where we are absolutely sure that the MPDU 4424 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4425 * written the bytes to the TXE, but we know nothing about what the DSP did. 4426 */ 4427 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4428 IWM_AGG_TX_STATE_ABORT | \ 4429 IWM_AGG_TX_STATE_SCD_QUERY) 4430 4431 /* 4432 * IWM_REPLY_TX = 0x1c (response) 4433 * 4434 * This response may be in one of two slightly different formats, indicated 4435 * by the frame_count field: 4436 * 4437 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4438 * frame. Multiple attempts, at various bit rates, may have been made for 4439 * this frame. 4440 * 4441 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4442 * frames that used block-acknowledge. All frames were transmitted at 4443 * same rate. Rate scaling may have been used if first frame in this new 4444 * agg block failed in previous agg block(s). 4445 * 4446 * Note that, for aggregation, ACK (block-ack) status is not delivered 4447 * here; block-ack has not been received by the time the device records 4448 * this status. 4449 * This status relates to reasons the tx might have been blocked or aborted 4450 * within the device, rather than whether it was received successfully by 4451 * the destination station. 4452 */ 4453 4454 /** 4455 * struct iwm_agg_tx_status - per packet TX aggregation status 4456 * @status: enum iwm_tx_agg_status 4457 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4458 */ 4459 struct iwm_agg_tx_status { 4460 uint16_t status; 4461 uint16_t sequence; 4462 } __packed; 4463 4464 /* 4465 * definitions for initial rate index field 4466 * bits [3:0] initial rate index 4467 * bits [6:4] rate table color, used for the initial rate 4468 * bit-7 invalid rate indication 4469 */ 4470 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4471 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4472 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4473 4474 #define IWM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4475 #define IWM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4476 4477 /** 4478 * struct iwm_tx_resp - notifies that fw is TXing a packet 4479 * ( IWM_REPLY_TX = 0x1c ) 4480 * @frame_count: 1 no aggregation, >1 aggregation 4481 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4482 * @failure_rts: num of failures due to unsuccessful RTS 4483 * @failure_frame: num failures due to no ACK (unused for agg) 4484 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4485 * Tx of all the batch. IWM_RATE_MCS_* 4486 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4487 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4488 * in usec. 4489 * @pa_status: tx power info 4490 * @pa_integ_res_a: tx power info 4491 * @pa_integ_res_b: tx power info 4492 * @pa_integ_res_c: tx power info 4493 * @measurement_req_id: tx power info 4494 * @tfd_info: TFD information set by the FH 4495 * @seq_ctl: sequence control from the Tx cmd 4496 * @byte_cnt: byte count from the Tx cmd 4497 * @tlc_info: TLC rate info 4498 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4499 * @frame_ctrl: frame control 4500 * @status: for non-agg: frame status IWM_TX_STATUS_* 4501 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4502 * follow this one, up to frame_count. 4503 * 4504 * After the array of statuses comes the SSN of the SCD. Look at 4505 * %iwm_get_scd_ssn for more details. 4506 */ 4507 struct iwm_tx_resp { 4508 uint8_t frame_count; 4509 uint8_t bt_kill_count; 4510 uint8_t failure_rts; 4511 uint8_t failure_frame; 4512 uint32_t initial_rate; 4513 uint16_t wireless_media_time; 4514 4515 uint8_t pa_status; 4516 uint8_t pa_integ_res_a[3]; 4517 uint8_t pa_integ_res_b[3]; 4518 uint8_t pa_integ_res_c[3]; 4519 uint16_t measurement_req_id; 4520 uint16_t reserved; 4521 4522 uint32_t tfd_info; 4523 uint16_t seq_ctl; 4524 uint16_t byte_cnt; 4525 uint8_t tlc_info; 4526 uint8_t ra_tid; 4527 uint16_t frame_ctrl; 4528 4529 struct iwm_agg_tx_status status; 4530 } __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4531 4532 /** 4533 * struct iwm_ba_notif - notifies about reception of BA 4534 * ( IWM_BA_NOTIF = 0xc5 ) 4535 * @sta_addr_lo32: lower 32 bits of the MAC address 4536 * @sta_addr_hi16: upper 16 bits of the MAC address 4537 * @sta_id: Index of recipient (BA-sending) station in fw's station table 4538 * @tid: tid of the session 4539 * @seq_ctl: 4540 * @bitmap: the bitmap of the BA notification as seen in the air 4541 * @scd_flow: the tx queue this BA relates to 4542 * @scd_ssn: the index of the last contiguously sent packet 4543 * @txed: number of Txed frames in this batch 4544 * @txed_2_done: number of Acked frames in this batch 4545 */ 4546 struct iwm_ba_notif { 4547 uint32_t sta_addr_lo32; 4548 uint16_t sta_addr_hi16; 4549 uint16_t reserved; 4550 4551 uint8_t sta_id; 4552 uint8_t tid; 4553 uint16_t seq_ctl; 4554 uint64_t bitmap; 4555 uint16_t scd_flow; 4556 uint16_t scd_ssn; 4557 uint8_t txed; 4558 uint8_t txed_2_done; 4559 uint16_t reserved1; 4560 } __packed; 4561 4562 /* 4563 * struct iwm_mac_beacon_cmd - beacon template command 4564 * @tx: the tx commands associated with the beacon frame 4565 * @template_id: currently equal to the mac context id of the coresponding 4566 * mac. 4567 * @tim_idx: the offset of the tim IE in the beacon 4568 * @tim_size: the length of the tim IE 4569 * @frame: the template of the beacon frame 4570 */ 4571 struct iwm_mac_beacon_cmd { 4572 struct iwm_tx_cmd tx; 4573 uint32_t template_id; 4574 uint32_t tim_idx; 4575 uint32_t tim_size; 4576 struct ieee80211_frame frame[0]; 4577 } __packed; 4578 4579 struct iwm_beacon_notif { 4580 struct iwm_tx_resp beacon_notify_hdr; 4581 uint64_t tsf; 4582 uint32_t ibss_mgr_status; 4583 } __packed; 4584 4585 /** 4586 * dump (flush) control flags 4587 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4588 * and the TFD queues are empty. 4589 */ 4590 #define IWM_DUMP_TX_FIFO_FLUSH (1 << 1) 4591 4592 /** 4593 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4594 * @queues_ctl: bitmap of queues to flush 4595 * @flush_ctl: control flags 4596 * @reserved: reserved 4597 */ 4598 struct iwm_tx_path_flush_cmd { 4599 uint32_t queues_ctl; 4600 uint16_t flush_ctl; 4601 uint16_t reserved; 4602 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4603 4604 /** 4605 * iwm_get_scd_ssn - returns the SSN of the SCD 4606 * @tx_resp: the Tx response from the fw (agg or non-agg) 4607 * 4608 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4609 * it can't know that everything will go well until the end of the AMPDU, it 4610 * can't know in advance the number of MPDUs that will be sent in the current 4611 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4612 * Hence, it can't know in advance what the SSN of the SCD will be at the end 4613 * of the batch. This is why the SSN of the SCD is written at the end of the 4614 * whole struct at a variable offset. This function knows how to cope with the 4615 * variable offset and returns the SSN of the SCD. 4616 */ 4617 static inline uint32_t iwm_get_scd_ssn(struct iwm_tx_resp *tx_resp) 4618 { 4619 return le32_to_cpup((uint32_t *)&tx_resp->status + 4620 tx_resp->frame_count) & 0xfff; 4621 } 4622 4623 /** 4624 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4625 * @token: 4626 * @sta_id: station id 4627 * @tid: 4628 * @scd_queue: scheduler queue to confiug 4629 * @enable: 1 queue enable, 0 queue disable 4630 * @aggregate: 1 aggregated queue, 0 otherwise 4631 * @tx_fifo: %enum iwm_tx_fifo 4632 * @window: BA window size 4633 * @ssn: SSN for the BA agreement 4634 */ 4635 struct iwm_scd_txq_cfg_cmd { 4636 uint8_t token; 4637 uint8_t sta_id; 4638 uint8_t tid; 4639 uint8_t scd_queue; 4640 uint8_t enable; 4641 uint8_t aggregate; 4642 uint8_t tx_fifo; 4643 uint8_t window; 4644 uint16_t ssn; 4645 uint16_t reserved; 4646 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4647 4648 /** 4649 * struct iwm_scd_txq_cfg_rsp 4650 * @token: taken from the command 4651 * @sta_id: station id from the command 4652 * @tid: tid from the command 4653 * @scd_queue: scd_queue from the command 4654 */ 4655 struct iwm_scd_txq_cfg_rsp { 4656 uint8_t token; 4657 uint8_t sta_id; 4658 uint8_t tid; 4659 uint8_t scd_queue; 4660 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4661 4662 4663 /* Scan Commands, Responses, Notifications */ 4664 4665 /* Masks for iwm_scan_channel.type flags */ 4666 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4667 #define IWM_SCAN_CHANNEL_NARROW_BAND (1 << 22) 4668 4669 /* Max number of IEs for direct SSID scans in a command */ 4670 #define IWM_PROBE_OPTION_MAX 20 4671 4672 /** 4673 * struct iwm_scan_channel - entry in IWM_REPLY_SCAN_CMD channel table 4674 * @channel: band is selected by iwm_scan_cmd "flags" field 4675 * @tx_gain: gain for analog radio 4676 * @dsp_atten: gain for DSP 4677 * @active_dwell: dwell time for active scan in TU, typically 5-50 4678 * @passive_dwell: dwell time for passive scan in TU, typically 20-500 4679 * @type: type is broken down to these bits: 4680 * bit 0: 0 = passive, 1 = active 4681 * bits 1-20: SSID direct bit map. If any of these bits is set then 4682 * the corresponding SSID IE is transmitted in probe request 4683 * (bit i adds IE in position i to the probe request) 4684 * bit 22: channel width, 0 = regular, 1 = TGj narrow channel 4685 * 4686 * @iteration_count: 4687 * @iteration_interval: 4688 * This struct is used once for each channel in the scan list. 4689 * Each channel can independently select: 4690 * 1) SSID for directed active scans 4691 * 2) Txpower setting (for rate specified within Tx command) 4692 * 3) How long to stay on-channel (behavior may be modified by quiet_time, 4693 * quiet_plcp_th, good_CRC_th) 4694 * 4695 * To avoid uCode errors, make sure the following are true (see comments 4696 * under struct iwm_scan_cmd about max_out_time and quiet_time): 4697 * 1) If using passive_dwell (i.e. passive_dwell != 0): 4698 * active_dwell <= passive_dwell (< max_out_time if max_out_time != 0) 4699 * 2) quiet_time <= active_dwell 4700 * 3) If restricting off-channel time (i.e. max_out_time !=0): 4701 * passive_dwell < max_out_time 4702 * active_dwell < max_out_time 4703 */ 4704 struct iwm_scan_channel { 4705 uint32_t type; 4706 uint16_t channel; 4707 uint16_t iteration_count; 4708 uint32_t iteration_interval; 4709 uint16_t active_dwell; 4710 uint16_t passive_dwell; 4711 } __packed; /* IWM_SCAN_CHANNEL_CONTROL_API_S_VER_1 */ 4712 4713 /** 4714 * struct iwm_ssid_ie - directed scan network information element 4715 * 4716 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4717 * selected by "type" bit field in struct iwm_scan_channel; 4718 * each channel may select different ssids from among the 20 entries. 4719 * SSID IEs get transmitted in reverse order of entry. 4720 */ 4721 struct iwm_ssid_ie { 4722 uint8_t id; 4723 uint8_t len; 4724 uint8_t ssid[IEEE80211_NWID_LEN]; 4725 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4726 4727 /* scan offload */ 4728 #define IWM_MAX_SCAN_CHANNELS 40 4729 #define IWM_SCAN_MAX_BLACKLIST_LEN 64 4730 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4731 #define IWM_SCAN_MAX_PROFILES 11 4732 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4733 4734 /* Default watchdog (in MS) for scheduled scan iteration */ 4735 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4736 4737 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4738 #define IWM_CAN_ABORT_STATUS 1 4739 4740 #define IWM_FULL_SCAN_MULTIPLIER 5 4741 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4742 #define IWM_MAX_SCHED_SCAN_PLANS 2 4743 4744 /** 4745 * masks for scan command flags 4746 * @IWM_SCAN_FLAGS_PASSIVE2ACTIVE: use active scan on channels that was active 4747 * in the past hour, even if they are marked as passive. 4748 */ 4749 #define IWM_SCAN_FLAGS_PERIODIC_SCAN (1 << 0) 4750 #define IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX (1 << 1) 4751 #define IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND (1 << 2) 4752 #define IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND (1 << 3) 4753 #define IWM_SCAN_FLAGS_FRAGMENTED_SCAN (1 << 4) 4754 #define IWM_SCAN_FLAGS_PASSIVE2ACTIVE (1 << 5) 4755 4756 /** 4757 * Scan types for scan command. 4758 */ 4759 #define IWM_SCAN_TYPE_FORCED 0 4760 #define IWM_SCAN_TYPE_BACKGROUND 1 4761 #define IWM_SCAN_TYPE_OS 2 4762 #define IWM_SCAN_TYPE_ROAMING 3 4763 #define IWM_SCAN_TYPE_ACTION 4 4764 #define IWM_SCAN_TYPE_DISCOVERY 5 4765 #define IWM_SCAN_TYPE_DISCOVERY_FORCED 6 4766 /* IWM_SCAN_ACTIVITY_TYPE_E_VER_1 */ 4767 4768 /* Maximal number of channels to scan */ 4769 #define IWM_MAX_NUM_SCAN_CHANNELS 0x24 4770 4771 /** 4772 * iwm_scan_schedule_lmac - schedule of scan offload 4773 * @delay: delay between iterations, in seconds. 4774 * @iterations: num of scan iterations 4775 * @full_scan_mul: number of partial scans before each full scan 4776 */ 4777 struct iwm_scan_schedule_lmac { 4778 uint16_t delay; 4779 uint8_t iterations; 4780 uint8_t full_scan_mul; 4781 } __packed; /* SCAN_SCHEDULE_API_S */ 4782 4783 /** 4784 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4785 * @tx_flags: combination of TX_CMD_FLG_* 4786 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4787 * cleared. Combination of RATE_MCS_* 4788 * @sta_id: index of destination station in FW station table 4789 * @reserved: for alignment and future use 4790 */ 4791 struct iwm_scan_req_tx_cmd { 4792 uint32_t tx_flags; 4793 uint32_t rate_n_flags; 4794 uint8_t sta_id; 4795 uint8_t reserved[3]; 4796 } __packed; 4797 4798 #define IWM_UNIFIED_SCAN_CHANNEL_FULL (1 << 27) 4799 #define IWM_UNIFIED_SCAN_CHANNEL_PARTIAL (1 << 28) 4800 4801 /** 4802 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4803 * @flags: bits 1-20: directed scan to i'th ssid 4804 * other bits &enum iwm_scan_channel_flags_lmac 4805 * @channel_number: channel number 1-13 etc 4806 * @iter_count: scan iteration on this channel 4807 * @iter_interval: interval in seconds between iterations on one channel 4808 */ 4809 struct iwm_scan_channel_cfg_lmac { 4810 uint32_t flags; 4811 uint16_t channel_num; 4812 uint16_t iter_count; 4813 uint32_t iter_interval; 4814 } __packed; 4815 4816 /* 4817 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4818 * @offset: offset in the data block 4819 * @len: length of the segment 4820 */ 4821 struct iwm_scan_probe_segment { 4822 uint16_t offset; 4823 uint16_t len; 4824 } __packed; 4825 4826 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4827 * @mac_header: first (and common) part of the probe 4828 * @band_data: band specific data 4829 * @common_data: last (and common) part of the probe 4830 * @buf: raw data block 4831 */ 4832 struct iwm_scan_probe_req { 4833 struct iwm_scan_probe_segment mac_header; 4834 struct iwm_scan_probe_segment band_data[2]; 4835 struct iwm_scan_probe_segment common_data; 4836 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4837 } __packed; 4838 4839 #define IWM_SCAN_CHANNEL_FLAG_EBS (1 << 0) 4840 #define IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE (1 << 1) 4841 #define IWM_SCAN_CHANNEL_FLAG_CACHE_ADD (1 << 2) 4842 4843 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4844 * @flags: enum iwm_scan_channel_flags 4845 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4846 * involved. 4847 * 1 - EBS is disabled. 4848 * 2 - every second scan will be full scan(and so on). 4849 */ 4850 struct iwm_scan_channel_opt { 4851 uint16_t flags; 4852 uint16_t non_ebs_ratio; 4853 } __packed; 4854 4855 /** 4856 * LMAC scan flags 4857 * @IWM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4858 * without filtering. 4859 * @IWM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4860 * @IWM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4861 * @IWM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4862 * @IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4863 * @IWM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4864 * @IWM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4865 * and DS parameter set IEs into probe requests. 4866 * @IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4867 * 1, 6 and 11. 4868 * @IWM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4869 */ 4870 #define IWM_LMAC_SCAN_FLAG_PASS_ALL (1 << 0) 4871 #define IWM_LMAC_SCAN_FLAG_PASSIVE (1 << 1) 4872 #define IWM_LMAC_SCAN_FLAG_PRE_CONNECTION (1 << 2) 4873 #define IWM_LMAC_SCAN_FLAG_ITER_COMPLETE (1 << 3) 4874 #define IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS (1 << 4) 4875 #define IWM_LMAC_SCAN_FLAG_FRAGMENTED (1 << 5) 4876 #define IWM_LMAC_SCAN_FLAGS_RRM_ENABLED (1 << 6) 4877 #define IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL (1 << 7) 4878 #define IWM_LMAC_SCAN_FLAG_MATCH (1 << 9) 4879 4880 #define IWM_SCAN_PRIORITY_LOW 0 4881 #define IWM_SCAN_PRIORITY_MEDIUM 1 4882 #define IWM_SCAN_PRIORITY_HIGH 2 4883 4884 /** 4885 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 4886 * @reserved1: for alignment and future use 4887 * @channel_num: num of channels to scan 4888 * @active-dwell: dwell time for active channels 4889 * @passive-dwell: dwell time for passive channels 4890 * @fragmented-dwell: dwell time for fragmented passive scan 4891 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 4892 * @reserved2: for alignment and future use 4893 * @rx_chain_selct: PHY_RX_CHAIN_* flags 4894 * @scan_flags: &enum iwm_lmac_scan_flags 4895 * @max_out_time: max time (in TU) to be out of associated channel 4896 * @suspend_time: pause scan this long (TUs) when returning to service channel 4897 * @flags: RXON flags 4898 * @filter_flags: RXON filter 4899 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 4900 * @direct_scan: list of SSIDs for directed active scan 4901 * @scan_prio: enum iwm_scan_priority 4902 * @iter_num: number of scan iterations 4903 * @delay: delay in seconds before first iteration 4904 * @schedule: two scheduling plans. The first one is finite, the second one can 4905 * be infinite. 4906 * @channel_opt: channel optimization options, for full and partial scan 4907 * @data: channel configuration and probe request packet. 4908 */ 4909 struct iwm_scan_req_lmac { 4910 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 4911 uint32_t reserved1; 4912 uint8_t n_channels; 4913 uint8_t active_dwell; 4914 uint8_t passive_dwell; 4915 uint8_t fragmented_dwell; 4916 uint8_t extended_dwell; 4917 uint8_t reserved2; 4918 uint16_t rx_chain_select; 4919 uint32_t scan_flags; 4920 uint32_t max_out_time; 4921 uint32_t suspend_time; 4922 /* RX_ON_FLAGS_API_S_VER_1 */ 4923 uint32_t flags; 4924 uint32_t filter_flags; 4925 struct iwm_scan_req_tx_cmd tx_cmd[2]; 4926 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4927 uint32_t scan_prio; 4928 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 4929 uint32_t iter_num; 4930 uint32_t delay; 4931 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 4932 struct iwm_scan_channel_opt channel_opt[2]; 4933 uint8_t data[]; 4934 } __packed; 4935 4936 /** 4937 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 4938 * @last_schedule_line: last schedule line executed (fast or regular) 4939 * @last_schedule_iteration: last scan iteration executed before scan abort 4940 * @status: enum iwm_scan_offload_complete_status 4941 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 4942 * @time_after_last_iter; time in seconds elapsed after last iteration 4943 */ 4944 struct iwm_periodic_scan_complete { 4945 uint8_t last_schedule_line; 4946 uint8_t last_schedule_iteration; 4947 uint8_t status; 4948 uint8_t ebs_status; 4949 uint32_t time_after_last_iter; 4950 uint32_t reserved; 4951 } __packed; 4952 4953 /* Response to scan request contains only status with one of these values */ 4954 #define IWM_SCAN_RESPONSE_OK 0x1 4955 #define IWM_SCAN_RESPONSE_ERROR 0x2 4956 4957 /* 4958 * IWM_SCAN_ABORT_CMD = 0x81 4959 * When scan abort is requested, the command has no fields except the common 4960 * header. The response contains only a status with one of these values. 4961 */ 4962 #define IWM_SCAN_ABORT_POSSIBLE 0x1 4963 #define IWM_SCAN_ABORT_IGNORED 0x2 /* no pending scans */ 4964 4965 /* TODO: complete documentation */ 4966 #define IWM_SCAN_OWNER_STATUS 0x1 4967 #define IWM_MEASURE_OWNER_STATUS 0x2 4968 4969 /** 4970 * struct iwm_scan_start_notif - notifies start of scan in the device 4971 * ( IWM_SCAN_START_NOTIFICATION = 0x82 ) 4972 * @tsf_low: TSF timer (lower half) in usecs 4973 * @tsf_high: TSF timer (higher half) in usecs 4974 * @beacon_timer: structured as follows: 4975 * bits 0:19 - beacon interval in usecs 4976 * bits 20:23 - reserved (0) 4977 * bits 24:31 - number of beacons 4978 * @channel: which channel is scanned 4979 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 4980 * @status: one of *_OWNER_STATUS 4981 */ 4982 struct iwm_scan_start_notif { 4983 uint32_t tsf_low; 4984 uint32_t tsf_high; 4985 uint32_t beacon_timer; 4986 uint8_t channel; 4987 uint8_t band; 4988 uint8_t reserved[2]; 4989 uint32_t status; 4990 } __packed; /* IWM_SCAN_START_NTF_API_S_VER_1 */ 4991 4992 /* scan results probe_status first bit indicates success */ 4993 #define IWM_SCAN_PROBE_STATUS_OK 0 4994 #define IWM_SCAN_PROBE_STATUS_TX_FAILED (1 << 0) 4995 /* error statuses combined with TX_FAILED */ 4996 #define IWM_SCAN_PROBE_STATUS_FAIL_TTL (1 << 1) 4997 #define IWM_SCAN_PROBE_STATUS_FAIL_BT (1 << 2) 4998 4999 /* How many statistics are gathered for each channel */ 5000 #define IWM_SCAN_RESULTS_STATISTICS 1 5001 5002 /** 5003 * status codes for scan complete notifications 5004 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 5005 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 5006 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 5007 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 5008 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 5009 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 5010 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 5011 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 5012 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 5013 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 5014 * (not an error!) 5015 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 5016 * asked for 5017 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 5018 */ 5019 #define IWM_SCAN_COMP_STATUS_OK 0x1 5020 #define IWM_SCAN_COMP_STATUS_ABORT 0x2 5021 #define IWM_SCAN_COMP_STATUS_ERR_SLEEP 0x3 5022 #define IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT 0x4 5023 #define IWM_SCAN_COMP_STATUS_ERR_PROBE 0x5 5024 #define IWM_SCAN_COMP_STATUS_ERR_WAKEUP 0x6 5025 #define IWM_SCAN_COMP_STATUS_ERR_ANTENNAS 0x7 5026 #define IWM_SCAN_COMP_STATUS_ERR_INTERNAL 0x8 5027 #define IWM_SCAN_COMP_STATUS_ERR_COEX 0x9 5028 #define IWM_SCAN_COMP_STATUS_P2P_ACTION_OK 0xA 5029 #define IWM_SCAN_COMP_STATUS_ITERATION_END 0x0B 5030 #define IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE 0x0C 5031 5032 /** 5033 * struct iwm_scan_results_notif - scan results for one channel 5034 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 5035 * @channel: which channel the results are from 5036 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5037 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 5038 * @num_probe_not_sent: # of request that weren't sent due to not enough time 5039 * @duration: duration spent in channel, in usecs 5040 * @statistics: statistics gathered for this channel 5041 */ 5042 struct iwm_scan_results_notif { 5043 uint8_t channel; 5044 uint8_t band; 5045 uint8_t probe_status; 5046 uint8_t num_probe_not_sent; 5047 uint32_t duration; 5048 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 5049 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 5050 5051 /** 5052 * struct iwm_scan_complete_notif - notifies end of scanning (all channels) 5053 * ( IWM_SCAN_COMPLETE_NOTIFICATION = 0x84 ) 5054 * @scanned_channels: number of channels scanned (and number of valid results) 5055 * @status: one of IWM_SCAN_COMP_STATUS_* 5056 * @bt_status: BT on/off status 5057 * @last_channel: last channel that was scanned 5058 * @tsf_low: TSF timer (lower half) in usecs 5059 * @tsf_high: TSF timer (higher half) in usecs 5060 * @results: all scan results, only "scanned_channels" of them are valid 5061 */ 5062 struct iwm_scan_complete_notif { 5063 uint8_t scanned_channels; 5064 uint8_t status; 5065 uint8_t bt_status; 5066 uint8_t last_channel; 5067 uint32_t tsf_low; 5068 uint32_t tsf_high; 5069 struct iwm_scan_results_notif results[IWM_MAX_NUM_SCAN_CHANNELS]; 5070 } __packed; /* IWM_SCAN_COMPLETE_NTF_API_S_VER_2 */ 5071 5072 #define IWM_SCAN_CLIENT_SCHED_SCAN (1 << 0) 5073 #define IWM_SCAN_CLIENT_NETDETECT (1 << 1) 5074 #define IWM_SCAN_CLIENT_ASSET_TRACKING (1 << 2) 5075 5076 /** 5077 * struct iwm_scan_offload_cmd - IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_6 5078 * @scan_flags: see enum iwm_scan_flags 5079 * @channel_count: channels in channel list 5080 * @quiet_time: dwell time, in milisiconds, on quiet channel 5081 * @quiet_plcp_th: quiet channel num of packets threshold 5082 * @good_CRC_th: passive to active promotion threshold 5083 * @rx_chain: RXON rx chain. 5084 * @max_out_time: max uSec to be out of assoceated channel 5085 * @suspend_time: pause scan this long when returning to service channel 5086 * @flags: RXON flags 5087 * @filter_flags: RXONfilter 5088 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz. 5089 * @direct_scan: list of SSIDs for directed active scan 5090 * @scan_type: see enum iwm_scan_type. 5091 * @rep_count: repetition count for each scheduled scan iteration. 5092 */ 5093 struct iwm_scan_offload_cmd { 5094 uint16_t len; 5095 uint8_t scan_flags; 5096 uint8_t channel_count; 5097 uint16_t quiet_time; 5098 uint16_t quiet_plcp_th; 5099 uint16_t good_CRC_th; 5100 uint16_t rx_chain; 5101 uint32_t max_out_time; 5102 uint32_t suspend_time; 5103 /* IWM_RX_ON_FLAGS_API_S_VER_1 */ 5104 uint32_t flags; 5105 uint32_t filter_flags; 5106 struct iwm_tx_cmd tx_cmd[2]; 5107 /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 5108 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5109 uint32_t scan_type; 5110 uint32_t rep_count; 5111 } __packed; 5112 5113 #define IWM_SCAN_OFFLOAD_CHANNEL_ACTIVE (1 << 0) 5114 #define IWM_SCAN_OFFLOAD_CHANNEL_NARROW (1 << 22) 5115 #define IWM_SCAN_OFFLOAD_CHANNEL_FULL (1 << 24) 5116 #define IWM_SCAN_OFFLOAD_CHANNEL_PARTIAL (1 << 25) 5117 5118 /** 5119 * iwm_scan_channel_cfg - IWM_SCAN_CHANNEL_CFG_S 5120 * @type: bitmap - see enum iwm_scan_offload_channel_flags. 5121 * 0: passive (0) or active (1) scan. 5122 * 1-20: directed scan to i'th ssid. 5123 * 22: channel width configuation - 1 for narrow. 5124 * 24: full scan. 5125 * 25: partial scan. 5126 * @channel_number: channel number 1-13 etc. 5127 * @iter_count: repetition count for the channel. 5128 * @iter_interval: interval between two innteration on one channel. 5129 * @dwell_time: entry 0 - active scan, entry 1 - passive scan. 5130 */ 5131 struct iwm_scan_channel_cfg { 5132 uint32_t type[IWM_MAX_SCAN_CHANNELS]; 5133 uint16_t channel_number[IWM_MAX_SCAN_CHANNELS]; 5134 uint16_t iter_count[IWM_MAX_SCAN_CHANNELS]; 5135 uint32_t iter_interval[IWM_MAX_SCAN_CHANNELS]; 5136 uint8_t dwell_time[IWM_MAX_SCAN_CHANNELS][2]; 5137 } __packed; 5138 5139 /** 5140 * iwm_scan_offload_cfg - IWM_SCAN_OFFLOAD_CONFIG_API_S 5141 * @scan_cmd: scan command fixed part 5142 * @channel_cfg: scan channel configuration 5143 * @data: probe request frames (one per band) 5144 */ 5145 struct iwm_scan_offload_cfg { 5146 struct iwm_scan_offload_cmd scan_cmd; 5147 struct iwm_scan_channel_cfg channel_cfg; 5148 uint8_t data[0]; 5149 } __packed; 5150 5151 /** 5152 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5153 * @ssid: MAC address to filter out 5154 * @reported_rssi: AP rssi reported to the host 5155 * @client_bitmap: clients ignore this entry - enum scan_framework_client 5156 */ 5157 struct iwm_scan_offload_blacklist { 5158 uint8_t ssid[ETHER_ADDR_LEN]; 5159 uint8_t reported_rssi; 5160 uint8_t client_bitmap; 5161 } __packed; 5162 5163 #define IWM_NETWORK_TYPE_BSS 1 5164 #define IWM_NETWORK_TYPE_IBSS 2 5165 #define IWM_NETWORK_TYPE_ANY 3 5166 5167 #define IWM_SCAN_OFFLOAD_SELECT_2_4 0x4 5168 #define IWM_SCAN_OFFLOAD_SELECT_5_2 0x8 5169 #define IWM_SCAN_OFFLOAD_SELECT_ANY 0xc 5170 5171 /** 5172 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5173 * @ssid_index: index to ssid list in fixed part 5174 * @unicast_cipher: encryption olgorithm to match - bitmap 5175 * @aut_alg: authentication olgorithm to match - bitmap 5176 * @network_type: enum iwm_scan_offload_network_type 5177 * @band_selection: enum iwm_scan_offload_band_selection 5178 * @client_bitmap: clients waiting for match - enum scan_framework_client 5179 */ 5180 struct iwm_scan_offload_profile { 5181 uint8_t ssid_index; 5182 uint8_t unicast_cipher; 5183 uint8_t auth_alg; 5184 uint8_t network_type; 5185 uint8_t band_selection; 5186 uint8_t client_bitmap; 5187 uint8_t reserved[2]; 5188 } __packed; 5189 5190 /** 5191 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5192 * @blaclist: AP list to filter off from scan results 5193 * @profiles: profiles to search for match 5194 * @blacklist_len: length of blacklist 5195 * @num_profiles: num of profiles in the list 5196 * @match_notify: clients waiting for match found notification 5197 * @pass_match: clients waiting for the results 5198 * @active_clients: active clients bitmap - enum scan_framework_client 5199 * @any_beacon_notify: clients waiting for match notification without match 5200 */ 5201 struct iwm_scan_offload_profile_cfg { 5202 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5203 uint8_t blacklist_len; 5204 uint8_t num_profiles; 5205 uint8_t match_notify; 5206 uint8_t pass_match; 5207 uint8_t active_clients; 5208 uint8_t any_beacon_notify; 5209 uint8_t reserved[2]; 5210 } __packed; 5211 5212 /** 5213 * iwm_scan_offload_schedule - schedule of scan offload 5214 * @delay: delay between iterations, in seconds. 5215 * @iterations: num of scan iterations 5216 * @full_scan_mul: number of partial scans before each full scan 5217 */ 5218 struct iwm_scan_offload_schedule { 5219 uint16_t delay; 5220 uint8_t iterations; 5221 uint8_t full_scan_mul; 5222 } __packed; 5223 5224 /* 5225 * scan offload flags 5226 * 5227 * IWM_SCAN_OFFLOAD_FLAG_PASS_ALL: pass all results - no filtering. 5228 * IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL: add cached channels to partial scan. 5229 * IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN: use energy based scan before partial scan 5230 * on A band. 5231 */ 5232 #define IWM_SCAN_OFFLOAD_FLAG_PASS_ALL (1 << 0) 5233 #define IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL (1 << 2) 5234 #define IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN (1 << 3) 5235 5236 /** 5237 * iwm_scan_offload_req - scan offload request command 5238 * @flags: bitmap - enum iwm_scan_offload_flags. 5239 * @watchdog: maximum scan duration in TU. 5240 * @delay: delay in seconds before first iteration. 5241 * @schedule_line: scan offload schedule, for fast and regular scan. 5242 */ 5243 struct iwm_scan_offload_req { 5244 uint16_t flags; 5245 uint16_t watchdog; 5246 uint16_t delay; 5247 uint16_t reserved; 5248 struct iwm_scan_offload_schedule schedule_line[2]; 5249 } __packed; 5250 5251 #define IWM_SCAN_OFFLOAD_COMPLETED 1 5252 #define IWM_SCAN_OFFLOAD_ABORTED 2 5253 5254 /** 5255 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5256 * SCAN_COMPLETE_NTF_API_S_VER_3 5257 * @scanned_channels: number of channels scanned (and number of valid results) 5258 * @status: one of SCAN_COMP_STATUS_* 5259 * @bt_status: BT on/off status 5260 * @last_channel: last channel that was scanned 5261 * @tsf_low: TSF timer (lower half) in usecs 5262 * @tsf_high: TSF timer (higher half) in usecs 5263 * @results: an array of scan results, only "scanned_channels" of them are valid 5264 */ 5265 struct iwm_lmac_scan_complete_notif { 5266 uint8_t scanned_channels; 5267 uint8_t status; 5268 uint8_t bt_status; 5269 uint8_t last_channel; 5270 uint32_t tsf_low; 5271 uint32_t tsf_high; 5272 struct iwm_scan_results_notif results[]; 5273 } __packed; 5274 5275 5276 /** 5277 * iwm_scan_offload_complete - IWM_SCAN_OFFLOAD_COMPLETE_NTF_API_S_VER_1 5278 * @last_schedule_line: last schedule line executed (fast or regular) 5279 * @last_schedule_iteration: last scan iteration executed before scan abort 5280 * @status: enum iwm_scan_offload_compleate_status 5281 */ 5282 struct iwm_scan_offload_complete { 5283 uint8_t last_schedule_line; 5284 uint8_t last_schedule_iteration; 5285 uint8_t status; 5286 uint8_t reserved; 5287 } __packed; 5288 5289 /** 5290 * iwm_sched_scan_results - IWM_SCAN_OFFLOAD_MATCH_FOUND_NTF_API_S_VER_1 5291 * @ssid_bitmap: SSIDs indexes found in this iteration 5292 * @client_bitmap: clients that are active and wait for this notification 5293 */ 5294 struct iwm_sched_scan_results { 5295 uint16_t ssid_bitmap; 5296 uint8_t client_bitmap; 5297 uint8_t reserved; 5298 }; 5299 5300 /* UMAC Scan API */ 5301 5302 /* The maximum of either of these cannot exceed 8, because we use an 5303 * 8-bit mask (see IWM_SCAN_MASK). 5304 */ 5305 #define IWM_MAX_UMAC_SCANS 8 5306 #define IWM_MAX_LMAC_SCANS 1 5307 5308 #define IWM_SCAN_CONFIG_FLAG_ACTIVATE (1 << 0) 5309 #define IWM_SCAN_CONFIG_FLAG_DEACTIVATE (1 << 1) 5310 #define IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS (1 << 2) 5311 #define IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS (1 << 3) 5312 #define IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS (1 << 8) 5313 #define IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS (1 << 9) 5314 #define IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID (1 << 10) 5315 #define IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES (1 << 11) 5316 #define IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES (1 << 12) 5317 #define IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS (1 << 13) 5318 #define IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES (1 << 14) 5319 #define IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR (1 << 15) 5320 #define IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED (1 << 16) 5321 #define IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED (1 << 17) 5322 #define IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE (1 << 18) 5323 #define IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE (1 << 19) 5324 #define IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE (1 << 20) 5325 #define IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE (1 << 21) 5326 5327 /* Bits 26-31 are for num of channels in channel_array */ 5328 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5329 5330 /* OFDM basic rates */ 5331 #define IWM_SCAN_CONFIG_RATE_6M (1 << 0) 5332 #define IWM_SCAN_CONFIG_RATE_9M (1 << 1) 5333 #define IWM_SCAN_CONFIG_RATE_12M (1 << 2) 5334 #define IWM_SCAN_CONFIG_RATE_18M (1 << 3) 5335 #define IWM_SCAN_CONFIG_RATE_24M (1 << 4) 5336 #define IWM_SCAN_CONFIG_RATE_36M (1 << 5) 5337 #define IWM_SCAN_CONFIG_RATE_48M (1 << 6) 5338 #define IWM_SCAN_CONFIG_RATE_54M (1 << 7) 5339 /* CCK basic rates */ 5340 #define IWM_SCAN_CONFIG_RATE_1M (1 << 8) 5341 #define IWM_SCAN_CONFIG_RATE_2M (1 << 9) 5342 #define IWM_SCAN_CONFIG_RATE_5M (1 << 10) 5343 #define IWM_SCAN_CONFIG_RATE_11M (1 << 11) 5344 5345 /* Bits 16-27 are for supported rates */ 5346 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5347 5348 #define IWM_CHANNEL_FLAG_EBS (1 << 0) 5349 #define IWM_CHANNEL_FLAG_ACCURATE_EBS (1 << 1) 5350 #define IWM_CHANNEL_FLAG_EBS_ADD (1 << 2) 5351 #define IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE (1 << 3) 5352 5353 /** 5354 * struct iwm_scan_config 5355 * @flags: enum scan_config_flags 5356 * @tx_chains: valid_tx antenna - ANT_* definitions 5357 * @rx_chains: valid_rx antenna - ANT_* definitions 5358 * @legacy_rates: default legacy rates - enum scan_config_rates 5359 * @out_of_channel_time: default max out of serving channel time 5360 * @suspend_time: default max suspend time 5361 * @dwell_active: default dwell time for active scan 5362 * @dwell_passive: default dwell time for passive scan 5363 * @dwell_fragmented: default dwell time for fragmented scan 5364 * @dwell_extended: default dwell time for channels 1, 6 and 11 5365 * @mac_addr: default mac address to be used in probes 5366 * @bcast_sta_id: the index of the station in the fw 5367 * @channel_flags: default channel flags - enum iwm_channel_flags 5368 * scan_config_channel_flag 5369 * @channel_array: default supported channels 5370 */ 5371 struct iwm_scan_config { 5372 uint32_t flags; 5373 uint32_t tx_chains; 5374 uint32_t rx_chains; 5375 uint32_t legacy_rates; 5376 uint32_t out_of_channel_time; 5377 uint32_t suspend_time; 5378 uint8_t dwell_active; 5379 uint8_t dwell_passive; 5380 uint8_t dwell_fragmented; 5381 uint8_t dwell_extended; 5382 uint8_t mac_addr[ETHER_ADDR_LEN]; 5383 uint8_t bcast_sta_id; 5384 uint8_t channel_flags; 5385 uint8_t channel_array[]; 5386 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5387 5388 /** 5389 * iwm_umac_scan_flags 5390 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5391 * can be preempted by other scan requests with higher priority. 5392 * The low priority scan will be resumed when the higher proirity scan is 5393 * completed. 5394 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5395 * when scan starts. 5396 */ 5397 #define IWM_UMAC_SCAN_FLAG_PREEMPTIVE (1 << 0) 5398 #define IWM_UMAC_SCAN_FLAG_START_NOTIF (1 << 1) 5399 5400 #define IWM_UMAC_SCAN_UID_TYPE_OFFSET 0 5401 #define IWM_UMAC_SCAN_UID_SEQ_OFFSET 8 5402 5403 #define IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC (1 << 0) 5404 #define IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT (1 << 1) 5405 #define IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL (1 << 2) 5406 #define IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE (1 << 3) 5407 #define IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT (1 << 4) 5408 #define IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE (1 << 5) 5409 #define IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID (1 << 6) 5410 #define IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED (1 << 7) 5411 #define IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED (1 << 8) 5412 #define IWM_UMAC_SCAN_GEN_FLAGS_MATCH (1 << 9) 5413 #define IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL (1 << 10) 5414 5415 /** 5416 * struct iwm_scan_channel_cfg_umac 5417 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5418 * @channel_num: channel number 1-13 etc. 5419 * @iter_count: repetition count for the channel. 5420 * @iter_interval: interval between two scan iterations on one channel. 5421 */ 5422 struct iwm_scan_channel_cfg_umac { 5423 uint32_t flags; 5424 uint8_t channel_num; 5425 uint8_t iter_count; 5426 uint16_t iter_interval; 5427 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5428 5429 /** 5430 * struct iwm_scan_umac_schedule 5431 * @interval: interval in seconds between scan iterations 5432 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5433 * @reserved: for alignment and future use 5434 */ 5435 struct iwm_scan_umac_schedule { 5436 uint16_t interval; 5437 uint8_t iter_count; 5438 uint8_t reserved; 5439 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5440 5441 /** 5442 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5443 * parameters following channels configuration array. 5444 * @schedule: two scheduling plans. 5445 * @delay: delay in TUs before starting the first scan iteration 5446 * @reserved: for future use and alignment 5447 * @preq: probe request with IEs blocks 5448 * @direct_scan: list of SSIDs for directed active scan 5449 */ 5450 struct iwm_scan_req_umac_tail { 5451 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5452 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5453 uint16_t delay; 5454 uint16_t reserved; 5455 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5456 struct iwm_scan_probe_req preq; 5457 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5458 } __packed; 5459 5460 /** 5461 * struct iwm_scan_req_umac 5462 * @flags: &enum iwm_umac_scan_flags 5463 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5464 * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5465 * @general_flags: &enum iwm_umac_scan_general_flags 5466 * @extended_dwell: dwell time for channels 1, 6 and 11 5467 * @active_dwell: dwell time for active scan 5468 * @passive_dwell: dwell time for passive scan 5469 * @fragmented_dwell: dwell time for fragmented passive scan 5470 * @max_out_time: max out of serving channel time 5471 * @suspend_time: max suspend time 5472 * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5473 * @channel_flags: &enum iwm_scan_channel_flags 5474 * @n_channels: num of channels in scan request 5475 * @reserved: for future use and alignment 5476 * @data: &struct iwm_scan_channel_cfg_umac and 5477 * &struct iwm_scan_req_umac_tail 5478 */ 5479 struct iwm_scan_req_umac { 5480 uint32_t flags; 5481 uint32_t uid; 5482 uint32_t ooc_priority; 5483 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5484 uint32_t general_flags; 5485 uint8_t extended_dwell; 5486 uint8_t active_dwell; 5487 uint8_t passive_dwell; 5488 uint8_t fragmented_dwell; 5489 uint32_t max_out_time; 5490 uint32_t suspend_time; 5491 uint32_t scan_priority; 5492 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5493 uint8_t channel_flags; 5494 uint8_t n_channels; 5495 uint16_t reserved; 5496 uint8_t data[]; 5497 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5498 5499 /** 5500 * struct iwm_umac_scan_abort 5501 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5502 * @flags: reserved 5503 */ 5504 struct iwm_umac_scan_abort { 5505 uint32_t uid; 5506 uint32_t flags; 5507 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5508 5509 /** 5510 * struct iwm_umac_scan_complete 5511 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5512 * @last_schedule: last scheduling line 5513 * @last_iter: last scan iteration number 5514 * @scan status: &enum iwm_scan_offload_complete_status 5515 * @ebs_status: &enum iwm_scan_ebs_status 5516 * @time_from_last_iter: time elapsed from last iteration 5517 * @reserved: for future use 5518 */ 5519 struct iwm_umac_scan_complete { 5520 uint32_t uid; 5521 uint8_t last_schedule; 5522 uint8_t last_iter; 5523 uint8_t status; 5524 uint8_t ebs_status; 5525 uint32_t time_from_last_iter; 5526 uint32_t reserved; 5527 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5528 5529 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5530 /** 5531 * struct iwm_scan_offload_profile_match - match information 5532 * @bssid: matched bssid 5533 * @channel: channel where the match occurred 5534 * @energy: 5535 * @matching_feature: 5536 * @matching_channels: bitmap of channels that matched, referencing 5537 * the channels passed in tue scan offload request 5538 */ 5539 struct iwm_scan_offload_profile_match { 5540 uint8_t bssid[ETHER_ADDR_LEN]; 5541 uint16_t reserved; 5542 uint8_t channel; 5543 uint8_t energy; 5544 uint8_t matching_feature; 5545 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5546 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5547 5548 /** 5549 * struct iwm_scan_offload_profiles_query - match results query response 5550 * @matched_profiles: bitmap of matched profiles, referencing the 5551 * matches passed in the scan offload request 5552 * @last_scan_age: age of the last offloaded scan 5553 * @n_scans_done: number of offloaded scans done 5554 * @gp2_d0u: GP2 when D0U occurred 5555 * @gp2_invoked: GP2 when scan offload was invoked 5556 * @resume_while_scanning: not used 5557 * @self_recovery: obsolete 5558 * @reserved: reserved 5559 * @matches: array of match information, one for each match 5560 */ 5561 struct iwm_scan_offload_profiles_query { 5562 uint32_t matched_profiles; 5563 uint32_t last_scan_age; 5564 uint32_t n_scans_done; 5565 uint32_t gp2_d0u; 5566 uint32_t gp2_invoked; 5567 uint8_t resume_while_scanning; 5568 uint8_t self_recovery; 5569 uint16_t reserved; 5570 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5571 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5572 5573 /** 5574 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5575 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5576 * @scanned_channels: number of channels scanned and number of valid elements in 5577 * results array 5578 * @status: one of SCAN_COMP_STATUS_* 5579 * @bt_status: BT on/off status 5580 * @last_channel: last channel that was scanned 5581 * @tsf_low: TSF timer (lower half) in usecs 5582 * @tsf_high: TSF timer (higher half) in usecs 5583 * @results: array of scan results, only "scanned_channels" of them are valid 5584 */ 5585 struct iwm_umac_scan_iter_complete_notif { 5586 uint32_t uid; 5587 uint8_t scanned_channels; 5588 uint8_t status; 5589 uint8_t bt_status; 5590 uint8_t last_channel; 5591 uint32_t tsf_low; 5592 uint32_t tsf_high; 5593 struct iwm_scan_results_notif results[]; 5594 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5595 5596 #define IWM_GSCAN_START_CMD 0x0 5597 #define IWM_GSCAN_STOP_CMD 0x1 5598 #define IWM_GSCAN_SET_HOTLIST_CMD 0x2 5599 #define IWM_GSCAN_RESET_HOTLIST_CMD 0x3 5600 #define IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD 0x4 5601 #define IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD 0x5 5602 #define IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT 0xFD 5603 #define IWM_GSCAN_HOTLIST_CHANGE_EVENT 0xFE 5604 #define IWM_GSCAN_RESULTS_AVAILABLE_EVENT 0xFF 5605 5606 /* STA API */ 5607 5608 /** 5609 * flags for the ADD_STA host command 5610 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5611 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5612 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5613 * @IWM_STA_FLG_PS: set if STA is in Power Save 5614 * @IWM_STA_FLG_INVALID: set if STA is invalid 5615 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5616 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5617 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5618 * @IWM_STA_FLG_PAN: STA is for PAN interface 5619 * @IWM_STA_FLG_CLASS_AUTH: 5620 * @IWM_STA_FLG_CLASS_ASSOC: 5621 * @IWM_STA_FLG_CLASS_MIMO_PROT: 5622 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5623 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5624 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5625 * initialised by driver and can be updated by fw upon reception of 5626 * action frames that can change the channel width. When cleared the fw 5627 * will send all the frames in 20MHz even when FAT channel is requested. 5628 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5629 * driver and can be updated by fw upon reception of action frames. 5630 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5631 */ 5632 #define IWM_STA_FLG_REDUCED_TX_PWR_CTRL (1 << 3) 5633 #define IWM_STA_FLG_REDUCED_TX_PWR_DATA (1 << 6) 5634 5635 #define IWM_STA_FLG_DISABLE_TX (1 << 4) 5636 5637 #define IWM_STA_FLG_PS (1 << 8) 5638 #define IWM_STA_FLG_DRAIN_FLOW (1 << 12) 5639 #define IWM_STA_FLG_PAN (1 << 13) 5640 #define IWM_STA_FLG_CLASS_AUTH (1 << 14) 5641 #define IWM_STA_FLG_CLASS_ASSOC (1 << 15) 5642 #define IWM_STA_FLG_RTS_MIMO_PROT (1 << 17) 5643 5644 #define IWM_STA_FLG_MAX_AGG_SIZE_SHIFT 19 5645 #define IWM_STA_FLG_MAX_AGG_SIZE_8K (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 5646 #define IWM_STA_FLG_MAX_AGG_SIZE_16K (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 5647 #define IWM_STA_FLG_MAX_AGG_SIZE_32K (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 5648 #define IWM_STA_FLG_MAX_AGG_SIZE_64K (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 5649 #define IWM_STA_FLG_MAX_AGG_SIZE_128K (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 5650 #define IWM_STA_FLG_MAX_AGG_SIZE_256K (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 5651 #define IWM_STA_FLG_MAX_AGG_SIZE_512K (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 5652 #define IWM_STA_FLG_MAX_AGG_SIZE_1024K (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 5653 #define IWM_STA_FLG_MAX_AGG_SIZE_MSK (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT) 5654 5655 #define IWM_STA_FLG_AGG_MPDU_DENS_SHIFT 23 5656 #define IWM_STA_FLG_AGG_MPDU_DENS_2US (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT) 5657 #define IWM_STA_FLG_AGG_MPDU_DENS_4US (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT) 5658 #define IWM_STA_FLG_AGG_MPDU_DENS_8US (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT) 5659 #define IWM_STA_FLG_AGG_MPDU_DENS_16US (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT) 5660 #define IWM_STA_FLG_AGG_MPDU_DENS_MSK (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT) 5661 5662 #define IWM_STA_FLG_FAT_EN_20MHZ (0 << 26) 5663 #define IWM_STA_FLG_FAT_EN_40MHZ (1 << 26) 5664 #define IWM_STA_FLG_FAT_EN_80MHZ (2 << 26) 5665 #define IWM_STA_FLG_FAT_EN_160MHZ (3 << 26) 5666 #define IWM_STA_FLG_FAT_EN_MSK (3 << 26) 5667 5668 #define IWM_STA_FLG_MIMO_EN_SISO (0 << 28) 5669 #define IWM_STA_FLG_MIMO_EN_MIMO2 (1 << 28) 5670 #define IWM_STA_FLG_MIMO_EN_MIMO3 (2 << 28) 5671 #define IWM_STA_FLG_MIMO_EN_MSK (3 << 28) 5672 5673 /** 5674 * key flags for the ADD_STA host command 5675 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5676 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5677 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5678 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5679 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5680 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5681 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5682 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5683 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5684 * station info array (1 - n 1X mode) 5685 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5686 * @IWM_STA_KEY_NOT_VALID: key is invalid 5687 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5688 * @IWM_STA_KEY_MULTICAST: set for multical key 5689 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5690 */ 5691 #define IWM_STA_KEY_FLG_NO_ENC (0 << 0) 5692 #define IWM_STA_KEY_FLG_WEP (1 << 0) 5693 #define IWM_STA_KEY_FLG_CCM (2 << 0) 5694 #define IWM_STA_KEY_FLG_TKIP (3 << 0) 5695 #define IWM_STA_KEY_FLG_EXT (4 << 0) 5696 #define IWM_STA_KEY_FLG_CMAC (6 << 0) 5697 #define IWM_STA_KEY_FLG_ENC_UNKNOWN (7 << 0) 5698 #define IWM_STA_KEY_FLG_EN_MSK (7 << 0) 5699 #define IWM_STA_KEY_FLG_WEP_KEY_MAP (1 << 3) 5700 #define IWM_STA_KEY_FLG_KEYID_POS 8 5701 #define IWM_STA_KEY_FLG_KEYID_MSK (3 << IWM_STA_KEY_FLG_KEYID_POS) 5702 #define IWM_STA_KEY_NOT_VALID (1 << 11) 5703 #define IWM_STA_KEY_FLG_WEP_13BYTES (1 << 12) 5704 #define IWM_STA_KEY_MULTICAST (1 << 14) 5705 #define IWM_STA_KEY_MFP (1 << 15) 5706 5707 /** 5708 * indicate to the fw what flag are being changed 5709 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5710 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5711 * @IWM_STA_MODIFY_TX_RATE: unused 5712 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5713 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5714 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5715 * @IWM_STA_MODIFY_PROT_TH: 5716 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5717 */ 5718 #define IWM_STA_MODIFY_QUEUE_REMOVAL (1 << 0) 5719 #define IWM_STA_MODIFY_TID_DISABLE_TX (1 << 1) 5720 #define IWM_STA_MODIFY_TX_RATE (1 << 2) 5721 #define IWM_STA_MODIFY_ADD_BA_TID (1 << 3) 5722 #define IWM_STA_MODIFY_REMOVE_BA_TID (1 << 4) 5723 #define IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT (1 << 5) 5724 #define IWM_STA_MODIFY_PROT_TH (1 << 6) 5725 #define IWM_STA_MODIFY_QUEUES (1 << 7) 5726 5727 #define IWM_STA_MODE_MODIFY 1 5728 5729 /** 5730 * type of sleep of the station 5731 * @IWM_STA_SLEEP_STATE_AWAKE: 5732 * @IWM_STA_SLEEP_STATE_PS_POLL: 5733 * @IWM_STA_SLEEP_STATE_UAPSD: 5734 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5735 * (last) released frame 5736 */ 5737 #define IWM_STA_SLEEP_STATE_AWAKE 0 5738 #define IWM_STA_SLEEP_STATE_PS_POLL (1 << 0) 5739 #define IWM_STA_SLEEP_STATE_UAPSD (1 << 1) 5740 #define IWM_STA_SLEEP_STATE_MOREDATA (1 << 2) 5741 5742 /* STA ID and color bits definitions */ 5743 #define IWM_STA_ID_SEED (0x0f) 5744 #define IWM_STA_ID_POS (0) 5745 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5746 5747 #define IWM_STA_COLOR_SEED (0x7) 5748 #define IWM_STA_COLOR_POS (4) 5749 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5750 5751 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5752 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5753 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5754 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5755 5756 #define IWM_STA_KEY_MAX_NUM (16) 5757 #define IWM_STA_KEY_IDX_INVALID (0xff) 5758 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5759 #define IWM_MAX_GLOBAL_KEYS (4) 5760 #define IWM_STA_KEY_LEN_WEP40 (5) 5761 #define IWM_STA_KEY_LEN_WEP104 (13) 5762 5763 /** 5764 * struct iwm_keyinfo - key information 5765 * @key_flags: type %iwm_sta_key_flag 5766 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5767 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5768 * @key_offset: key offset in the fw's key table 5769 * @key: 16-byte unicast decryption key 5770 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5771 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5772 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5773 */ 5774 struct iwm_keyinfo { 5775 uint16_t key_flags; 5776 uint8_t tkip_rx_tsc_byte2; 5777 uint8_t reserved1; 5778 uint16_t tkip_rx_ttak[5]; 5779 uint8_t key_offset; 5780 uint8_t reserved2; 5781 uint8_t key[16]; 5782 uint64_t tx_secur_seq_cnt; 5783 uint64_t hw_tkip_mic_rx_key; 5784 uint64_t hw_tkip_mic_tx_key; 5785 } __packed; 5786 5787 #define IWM_ADD_STA_STATUS_MASK 0xFF 5788 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5789 #define IWM_ADD_STA_BAID_MASK 0x7F00 5790 #define IWM_ADD_STA_BAID_SHIFT 8 5791 5792 /** 5793 * struct iwm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table. 5794 * ( REPLY_ADD_STA = 0x18 ) 5795 * @add_modify: 1: modify existing, 0: add new station 5796 * @awake_acs: 5797 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5798 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5799 * @mac_id_n_color: the Mac context this station belongs to 5800 * @addr[ETHER_ADDR_LEN]: station's MAC address 5801 * @sta_id: index of station in uCode's station table 5802 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5803 * alone. 1 - modify, 0 - don't change. 5804 * @station_flags: look at %iwm_sta_flags 5805 * @station_flags_msk: what of %station_flags have changed 5806 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5807 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5808 * add_immediate_ba_ssn. 5809 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5810 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5811 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5812 * add_immediate_ba_tid. 5813 * @sleep_tx_count: number of packets to transmit to station even though it is 5814 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5815 * keeps track of STA sleep state. 5816 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5817 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5818 * mac-addr. 5819 * @beamform_flags: beam forming controls 5820 * @tfd_queue_msk: tfd queues used by this station 5821 * 5822 * The device contains an internal table of per-station information, with info 5823 * on security keys, aggregation parameters, and Tx rates for initial Tx 5824 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5825 * 5826 * ADD_STA sets up the table entry for one station, either creating a new 5827 * entry, or modifying a pre-existing one. 5828 */ 5829 struct iwm_add_sta_cmd_v7 { 5830 uint8_t add_modify; 5831 uint8_t awake_acs; 5832 uint16_t tid_disable_tx; 5833 uint32_t mac_id_n_color; 5834 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5835 uint16_t reserved2; 5836 uint8_t sta_id; 5837 uint8_t modify_mask; 5838 uint16_t reserved3; 5839 uint32_t station_flags; 5840 uint32_t station_flags_msk; 5841 uint8_t add_immediate_ba_tid; 5842 uint8_t remove_immediate_ba_tid; 5843 uint16_t add_immediate_ba_ssn; 5844 uint16_t sleep_tx_count; 5845 uint16_t sleep_state_flags; 5846 uint16_t assoc_id; 5847 uint16_t beamform_flags; 5848 uint32_t tfd_queue_msk; 5849 } __packed; /* ADD_STA_CMD_API_S_VER_7 */ 5850 5851 /** 5852 * struct iwm_add_sta_key_cmd - add/modify sta key 5853 * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5854 * @sta_id: index of station in uCode's station table 5855 * @key_offset: key offset in key storage 5856 * @key_flags: type %iwm_sta_key_flag 5857 * @key: key material data 5858 * @key2: key material data 5859 * @rx_secur_seq_cnt: RX security sequence counter for the key 5860 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5861 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5862 */ 5863 struct iwm_add_sta_key_cmd { 5864 uint8_t sta_id; 5865 uint8_t key_offset; 5866 uint16_t key_flags; 5867 uint8_t key[16]; 5868 uint8_t key2[16]; 5869 uint8_t rx_secur_seq_cnt[16]; 5870 uint8_t tkip_rx_tsc_byte2; 5871 uint8_t reserved; 5872 uint16_t tkip_rx_ttak[5]; 5873 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5874 5875 /** 5876 * status in the response to ADD_STA command 5877 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5878 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5879 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5880 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5881 * that doesn't exist. 5882 */ 5883 #define IWM_ADD_STA_SUCCESS 0x1 5884 #define IWM_ADD_STA_STATIONS_OVERLOAD 0x2 5885 #define IWM_ADD_STA_IMMEDIATE_BA_FAILURE 0x4 5886 #define IWM_ADD_STA_MODIFY_NON_EXISTING_STA 0x8 5887 5888 /** 5889 * struct iwm_rm_sta_cmd - Add / modify a station in the fw's station table 5890 * ( IWM_REMOVE_STA = 0x19 ) 5891 * @sta_id: the station id of the station to be removed 5892 */ 5893 struct iwm_rm_sta_cmd { 5894 uint8_t sta_id; 5895 uint8_t reserved[3]; 5896 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5897 5898 /** 5899 * struct iwm_mgmt_mcast_key_cmd 5900 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5901 * @ctrl_flags: %iwm_sta_key_flag 5902 * @IGTK: 5903 * @K1: IGTK master key 5904 * @K2: IGTK sub key 5905 * @sta_id: station ID that support IGTK 5906 * @key_id: 5907 * @receive_seq_cnt: initial RSC/PN needed for replay check 5908 */ 5909 struct iwm_mgmt_mcast_key_cmd { 5910 uint32_t ctrl_flags; 5911 uint8_t IGTK[16]; 5912 uint8_t K1[16]; 5913 uint8_t K2[16]; 5914 uint32_t key_id; 5915 uint32_t sta_id; 5916 uint64_t receive_seq_cnt; 5917 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5918 5919 struct iwm_wep_key { 5920 uint8_t key_index; 5921 uint8_t key_offset; 5922 uint16_t reserved1; 5923 uint8_t key_size; 5924 uint8_t reserved2[3]; 5925 uint8_t key[16]; 5926 } __packed; 5927 5928 struct iwm_wep_key_cmd { 5929 uint32_t mac_id_n_color; 5930 uint8_t num_keys; 5931 uint8_t decryption_type; 5932 uint8_t flags; 5933 uint8_t reserved; 5934 struct iwm_wep_key wep_key[0]; 5935 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5936 5937 /* 5938 * BT coex 5939 */ 5940 5941 #define IWM_BT_COEX_DISABLE 0x0 5942 #define IWM_BT_COEX_NW 0x1 5943 #define IWM_BT_COEX_BT 0x2 5944 #define IWM_BT_COEX_WIFI 0x3 5945 /* BT_COEX_MODES_E */ 5946 5947 #define IWM_BT_COEX_MPLUT_ENABLED (1 << 0) 5948 #define IWM_BT_COEX_MPLUT_BOOST_ENABLED (1 << 1) 5949 #define IWM_BT_COEX_SYNC2SCO_ENABLED (1 << 2) 5950 #define IWM_BT_COEX_CORUN_ENABLED (1 << 3) 5951 #define IWM_BT_COEX_HIGH_BAND_RET (1 << 4) 5952 /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 5953 5954 /** 5955 * struct iwm_bt_coex_cmd - bt coex configuration command 5956 * @mode: enum %iwm_bt_coex_mode 5957 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 5958 * 5959 * The structure is used for the BT_COEX command. 5960 */ 5961 struct iwm_bt_coex_cmd { 5962 uint32_t mode; 5963 uint32_t enabled_modules; 5964 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 5965 5966 5967 /* 5968 * Location Aware Regulatory (LAR) API - MCC updates 5969 */ 5970 5971 /** 5972 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 5973 * regulatory profile according to the given MCC (Mobile Country Code). 5974 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5975 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5976 * MCC in the cmd response will be the relevant MCC in the NVM. 5977 * @mcc: given mobile country code 5978 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5979 * @reserved: reserved for alignment 5980 */ 5981 struct iwm_mcc_update_cmd_v1 { 5982 uint16_t mcc; 5983 uint8_t source_id; 5984 uint8_t reserved; 5985 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 5986 5987 /** 5988 * struct iwm_mcc_update_cmd - Request the device to update geographic 5989 * regulatory profile according to the given MCC (Mobile Country Code). 5990 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5991 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5992 * MCC in the cmd response will be the relevant MCC in the NVM. 5993 * @mcc: given mobile country code 5994 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5995 * @reserved: reserved for alignment 5996 * @key: integrity key for MCC API OEM testing 5997 * @reserved2: reserved 5998 */ 5999 struct iwm_mcc_update_cmd { 6000 uint16_t mcc; 6001 uint8_t source_id; 6002 uint8_t reserved; 6003 uint32_t key; 6004 uint32_t reserved2[5]; 6005 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 6006 6007 /** 6008 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 6009 * Contains the new channel control profile map, if changed, and the new MCC 6010 * (mobile country code). 6011 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6012 * @status: see &enum iwm_mcc_update_status 6013 * @mcc: the new applied MCC 6014 * @cap: capabilities for all channels which matches the MCC 6015 * @source_id: the MCC source, see iwm_mcc_source 6016 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6017 * channels, depending on platform) 6018 * @channels: channel control data map, DWORD for each channel. Only the first 6019 * 16bits are used. 6020 */ 6021 struct iwm_mcc_update_resp_v1 { 6022 uint32_t status; 6023 uint16_t mcc; 6024 uint8_t cap; 6025 uint8_t source_id; 6026 uint32_t n_channels; 6027 uint32_t channels[0]; 6028 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 6029 6030 /** 6031 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 6032 * Contains the new channel control profile map, if changed, and the new MCC 6033 * (mobile country code). 6034 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6035 * @status: see &enum iwm_mcc_update_status 6036 * @mcc: the new applied MCC 6037 * @cap: capabilities for all channels which matches the MCC 6038 * @source_id: the MCC source, see iwm_mcc_source 6039 * @time: time elapsed from the MCC test start (in 30 seconds TU) 6040 * @reserved: reserved. 6041 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6042 * channels, depending on platform) 6043 * @channels: channel control data map, DWORD for each channel. Only the first 6044 * 16bits are used. 6045 */ 6046 struct iwm_mcc_update_resp { 6047 uint32_t status; 6048 uint16_t mcc; 6049 uint8_t cap; 6050 uint8_t source_id; 6051 uint16_t time; 6052 uint16_t reserved; 6053 uint32_t n_channels; 6054 uint32_t channels[0]; 6055 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 6056 6057 /** 6058 * struct iwm_mcc_chub_notif - chub notifies of mcc change 6059 * (MCC_CHUB_UPDATE_CMD = 0xc9) 6060 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 6061 * the cellular and connectivity cores that gets updates of the mcc, and 6062 * notifies the ucode directly of any mcc change. 6063 * The ucode requests the driver to request the device to update geographic 6064 * regulatory profile according to the given MCC (Mobile Country Code). 6065 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6066 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6067 * MCC in the cmd response will be the relevant MCC in the NVM. 6068 * @mcc: given mobile country code 6069 * @source_id: identity of the change originator, see iwm_mcc_source 6070 * @reserved1: reserved for alignment 6071 */ 6072 struct iwm_mcc_chub_notif { 6073 uint16_t mcc; 6074 uint8_t source_id; 6075 uint8_t reserved1; 6076 } __packed; /* LAR_MCC_NOTIFY_S */ 6077 6078 #define IWM_MCC_RESP_NEW_CHAN_PROFILE 0 6079 #define IWM_MCC_RESP_SAME_CHAN_PROFILE 1 6080 #define IWM_MCC_RESP_INVALID 2 6081 #define IWM_MCC_RESP_NVM_DISABLED 3 6082 #define IWM_MCC_RESP_ILLEGAL 4 6083 #define IWM_MCC_RESP_LOW_PRIORITY 5 6084 #define IWM_MCC_RESP_TEST_MODE_ACTIVE 6 6085 #define IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE 7 6086 #define IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE 8 6087 6088 #define IWM_MCC_SOURCE_OLD_FW 0 6089 #define IWM_MCC_SOURCE_ME 1 6090 #define IWM_MCC_SOURCE_BIOS 2 6091 #define IWM_MCC_SOURCE_3G_LTE_HOST 3 6092 #define IWM_MCC_SOURCE_3G_LTE_DEVICE 4 6093 #define IWM_MCC_SOURCE_WIFI 5 6094 #define IWM_MCC_SOURCE_RESERVED 6 6095 #define IWM_MCC_SOURCE_DEFAULT 7 6096 #define IWM_MCC_SOURCE_UNINITIALIZED 8 6097 #define IWM_MCC_SOURCE_MCC_API 9 6098 #define IWM_MCC_SOURCE_GET_CURRENT 0x10 6099 #define IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE 0x11 6100 6101 /* 6102 * Some cherry-picked definitions 6103 */ 6104 6105 #define IWM_FRAME_LIMIT 64 6106 6107 /* 6108 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 6109 * As the firmware is slowly running out of command IDs and grouping of 6110 * commands is desirable anyway, the firmware is extending the command 6111 * header from 4 bytes to 8 bytes to introduce a group (in place of the 6112 * former flags field, since that's always 0 on commands and thus can 6113 * be easily used to distinguish between the two). 6114 * 6115 * These functions retrieve specific information from the id field in 6116 * the iwm_host_cmd struct which contains the command id, the group id, 6117 * and the version of the command. 6118 */ 6119 static inline uint8_t 6120 iwm_cmd_opcode(uint32_t cmdid) 6121 { 6122 return cmdid & 0xff; 6123 } 6124 6125 static inline uint8_t 6126 iwm_cmd_groupid(uint32_t cmdid) 6127 { 6128 return ((cmdid & 0Xff00) >> 8); 6129 } 6130 6131 static inline uint8_t 6132 iwm_cmd_version(uint32_t cmdid) 6133 { 6134 return ((cmdid & 0xff0000) >> 16); 6135 } 6136 6137 static inline uint32_t 6138 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6139 { 6140 return opcode + (groupid << 8) + (version << 16); 6141 } 6142 6143 /* make uint16_t wide id out of uint8_t group and opcode */ 6144 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6145 6146 /* due to the conversion, this group is special */ 6147 #define IWM_ALWAYS_LONG_GROUP 1 6148 6149 struct iwm_cmd_header { 6150 uint8_t code; 6151 uint8_t flags; 6152 uint8_t idx; 6153 uint8_t qid; 6154 } __packed; 6155 6156 struct iwm_cmd_header_wide { 6157 uint8_t opcode; 6158 uint8_t group_id; 6159 uint8_t idx; 6160 uint8_t qid; 6161 uint16_t length; 6162 uint8_t reserved; 6163 uint8_t version; 6164 } __packed; 6165 6166 #define IWM_POWER_SCHEME_CAM 1 6167 #define IWM_POWER_SCHEME_BPS 2 6168 #define IWM_POWER_SCHEME_LP 3 6169 6170 #define IWM_DEF_CMD_PAYLOAD_SIZE 320 6171 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6172 #define IWM_CMD_FAILED_MSK 0x40 6173 6174 /** 6175 * struct iwm_device_cmd 6176 * 6177 * For allocation of the command and tx queues, this establishes the overall 6178 * size of the largest command we send to uCode, except for commands that 6179 * aren't fully copied and use other TFD space. 6180 */ 6181 struct iwm_device_cmd { 6182 union { 6183 struct { 6184 struct iwm_cmd_header hdr; 6185 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6186 }; 6187 struct { 6188 struct iwm_cmd_header_wide hdr_wide; 6189 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6190 sizeof(struct iwm_cmd_header_wide) + 6191 sizeof(struct iwm_cmd_header)]; 6192 }; 6193 }; 6194 } __packed; 6195 6196 struct iwm_rx_packet { 6197 /* 6198 * The first 4 bytes of the RX frame header contain both the RX frame 6199 * size and some flags. 6200 * Bit fields: 6201 * 31: flag flush RB request 6202 * 30: flag ignore TC (terminal counter) request 6203 * 29: flag fast IRQ request 6204 * 28-14: Reserved 6205 * 13-00: RX frame size 6206 */ 6207 uint32_t len_n_flags; 6208 struct iwm_cmd_header hdr; 6209 uint8_t data[]; 6210 } __packed; 6211 6212 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6213 6214 static uint32_t 6215 iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6216 { 6217 6218 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6219 } 6220 6221 static uint32_t 6222 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6223 { 6224 6225 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6226 } 6227 6228 6229 #define IWM_MIN_DBM -100 6230 #define IWM_MAX_DBM -33 /* realistic guess */ 6231 6232 #define IWM_READ(sc, reg) \ 6233 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6234 6235 #define IWM_WRITE(sc, reg, val) \ 6236 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6237 6238 #define IWM_WRITE_1(sc, reg, val) \ 6239 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6240 6241 #define IWM_SETBITS(sc, reg, mask) \ 6242 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6243 6244 #define IWM_CLRBITS(sc, reg, mask) \ 6245 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6246 6247 #define IWM_BARRIER_WRITE(sc) \ 6248 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6249 BUS_SPACE_BARRIER_WRITE) 6250 6251 #define IWM_BARRIER_READ_WRITE(sc) \ 6252 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6253 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6254