1 /* $OpenBSD: if_ipw.c,v 1.118 2016/09/05 10:17:30 tedu Exp $ */ 2 3 /*- 4 * Copyright (c) 2004-2008 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Intel PRO/Wireless 2100 802.11 network adapters. 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/task.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/rwlock.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/conf.h> 35 #include <sys/device.h> 36 #include <sys/endian.h> 37 38 #include <machine/bus.h> 39 #include <machine/intr.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcidevs.h> 44 45 #if NBPFILTER > 0 46 #include <net/bpf.h> 47 #endif 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include <net80211/ieee80211_var.h> 56 #include <net80211/ieee80211_radiotap.h> 57 58 #include <dev/pci/if_ipwreg.h> 59 #include <dev/pci/if_ipwvar.h> 60 61 int ipw_match(struct device *, void *, void *); 62 void ipw_attach(struct device *, struct device *, void *); 63 int ipw_activate(struct device *, int); 64 void ipw_wakeup(struct ipw_softc *); 65 int ipw_dma_alloc(struct ipw_softc *); 66 void ipw_release(struct ipw_softc *); 67 int ipw_media_change(struct ifnet *); 68 void ipw_media_status(struct ifnet *, struct ifmediareq *); 69 int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 70 uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 71 void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 72 void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 73 void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 74 struct ipw_soft_bd *, struct ipw_soft_buf *); 75 void ipw_notification_intr(struct ipw_softc *, 76 struct ipw_soft_buf *); 77 void ipw_rx_intr(struct ipw_softc *); 78 void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 79 void ipw_tx_intr(struct ipw_softc *); 80 int ipw_intr(void *); 81 int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 82 int ipw_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 83 int, int, int); 84 int ipw_tx_start(struct ifnet *, struct mbuf *, 85 struct ieee80211_node *); 86 void ipw_start(struct ifnet *); 87 void ipw_watchdog(struct ifnet *); 88 int ipw_ioctl(struct ifnet *, u_long, caddr_t); 89 uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 90 void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 91 int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 92 uint32_t *); 93 void ipw_stop_master(struct ipw_softc *); 94 int ipw_reset(struct ipw_softc *); 95 int ipw_load_ucode(struct ipw_softc *, u_char *, int); 96 int ipw_load_firmware(struct ipw_softc *, u_char *, int); 97 int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 98 void ipw_scan(void *); 99 void ipw_auth_and_assoc(void *); 100 int ipw_config(struct ipw_softc *); 101 int ipw_init(struct ifnet *); 102 void ipw_stop(struct ifnet *, int); 103 void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 104 bus_size_t); 105 void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 106 bus_size_t); 107 108 static __inline uint8_t 109 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 110 { 111 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 112 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 113 } 114 115 static __inline uint32_t 116 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 117 { 118 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 119 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 120 } 121 122 #ifdef IPW_DEBUG 123 #define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 124 #define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 125 int ipw_debug = 0; 126 #else 127 #define DPRINTF(x) 128 #define DPRINTFN(n, x) 129 #endif 130 131 struct cfattach ipw_ca = { 132 sizeof (struct ipw_softc), ipw_match, ipw_attach, NULL, 133 ipw_activate 134 }; 135 136 int 137 ipw_match(struct device *parent, void *match, void *aux) 138 { 139 struct pci_attach_args *pa = aux; 140 141 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 142 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 143 return 1; 144 145 return 0; 146 } 147 148 /* Base Address Register */ 149 #define IPW_PCI_BAR0 0x10 150 151 void 152 ipw_attach(struct device *parent, struct device *self, void *aux) 153 { 154 struct ipw_softc *sc = (struct ipw_softc *)self; 155 struct ieee80211com *ic = &sc->sc_ic; 156 struct ifnet *ifp = &ic->ic_if; 157 struct pci_attach_args *pa = aux; 158 const char *intrstr; 159 bus_space_tag_t memt; 160 bus_space_handle_t memh; 161 bus_addr_t base; 162 pci_intr_handle_t ih; 163 pcireg_t data; 164 uint16_t val; 165 int error, i; 166 167 sc->sc_pct = pa->pa_pc; 168 sc->sc_pcitag = pa->pa_tag, 169 170 /* clear device specific PCI configuration register 0x41 */ 171 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 172 data &= ~0x0000ff00; 173 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 174 175 /* map the register window */ 176 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 177 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 178 if (error != 0) { 179 printf(": can't map mem space\n"); 180 return; 181 } 182 183 sc->sc_st = memt; 184 sc->sc_sh = memh; 185 sc->sc_dmat = pa->pa_dmat; 186 187 /* disable interrupts */ 188 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 189 190 if (pci_intr_map(pa, &ih) != 0) { 191 printf(": can't map interrupt\n"); 192 return; 193 } 194 195 intrstr = pci_intr_string(sc->sc_pct, ih); 196 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 197 sc->sc_dev.dv_xname); 198 if (sc->sc_ih == NULL) { 199 printf(": can't establish interrupt"); 200 if (intrstr != NULL) 201 printf(" at %s", intrstr); 202 printf("\n"); 203 return; 204 } 205 printf(": %s", intrstr); 206 207 rw_init(&sc->sc_rwlock, "ipwlock"); 208 task_set(&sc->sc_scantask, ipw_scan, sc); 209 task_set(&sc->sc_authandassoctask, ipw_auth_and_assoc, sc); 210 211 if (ipw_reset(sc) != 0) { 212 printf(": could not reset adapter\n"); 213 return; 214 } 215 216 if (ipw_dma_alloc(sc) != 0) { 217 printf(": failed to allocate DMA resources\n"); 218 return; 219 } 220 221 ic->ic_phytype = IEEE80211_T_DS; 222 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 223 ic->ic_state = IEEE80211_S_INIT; 224 225 /* set device capabilities */ 226 ic->ic_caps = 227 #ifndef IEEE80211_STA_ONLY 228 IEEE80211_C_IBSS | /* IBSS mode supported */ 229 #endif 230 IEEE80211_C_MONITOR | /* monitor mode supported */ 231 IEEE80211_C_TXPMGT | /* tx power management */ 232 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 233 IEEE80211_C_WEP | /* s/w WEP */ 234 IEEE80211_C_RSN | /* WPA/RSN */ 235 IEEE80211_C_SCANALL; /* h/w scanning */ 236 237 /* read MAC address from EEPROM */ 238 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 239 ic->ic_myaddr[0] = val >> 8; 240 ic->ic_myaddr[1] = val & 0xff; 241 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 242 ic->ic_myaddr[2] = val >> 8; 243 ic->ic_myaddr[3] = val & 0xff; 244 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 245 ic->ic_myaddr[4] = val >> 8; 246 ic->ic_myaddr[5] = val & 0xff; 247 248 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 249 250 /* set supported .11b rates */ 251 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 252 253 /* set supported .11b channels (1 through 14) */ 254 for (i = 1; i <= 14; i++) { 255 ic->ic_channels[i].ic_freq = 256 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 257 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 258 } 259 260 /* IBSS channel undefined for now */ 261 ic->ic_ibss_chan = &ic->ic_channels[0]; 262 263 ifp->if_softc = sc; 264 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 265 ifp->if_ioctl = ipw_ioctl; 266 ifp->if_start = ipw_start; 267 ifp->if_watchdog = ipw_watchdog; 268 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 269 270 if_attach(ifp); 271 ieee80211_ifattach(ifp); 272 /* override state transition machine */ 273 sc->sc_newstate = ic->ic_newstate; 274 ic->ic_newstate = ipw_newstate; 275 ic->ic_send_mgmt = ipw_send_mgmt; 276 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 277 278 #if NBPFILTER > 0 279 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 280 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 281 282 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 283 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 284 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 285 286 sc->sc_txtap_len = sizeof sc->sc_txtapu; 287 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 288 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 289 #endif 290 } 291 292 int 293 ipw_activate(struct device *self, int act) 294 { 295 struct ipw_softc *sc = (struct ipw_softc *)self; 296 struct ifnet *ifp = &sc->sc_ic.ic_if; 297 298 switch (act) { 299 case DVACT_SUSPEND: 300 if (ifp->if_flags & IFF_RUNNING) 301 ipw_stop(ifp, 0); 302 break; 303 case DVACT_WAKEUP: 304 ipw_wakeup(sc); 305 break; 306 } 307 308 return 0; 309 } 310 311 void 312 ipw_wakeup(struct ipw_softc *sc) 313 { 314 struct ifnet *ifp = &sc->sc_ic.ic_if; 315 pcireg_t data; 316 int s; 317 318 /* clear device specific PCI configuration register 0x41 */ 319 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 320 data &= ~0x0000ff00; 321 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 322 323 rw_enter_write(&sc->sc_rwlock); 324 s = splnet(); 325 326 if (ifp->if_flags & IFF_UP) 327 ipw_init(ifp); 328 329 splx(s); 330 rw_exit_write(&sc->sc_rwlock); 331 } 332 333 int 334 ipw_dma_alloc(struct ipw_softc *sc) 335 { 336 struct ipw_soft_bd *sbd; 337 struct ipw_soft_hdr *shdr; 338 struct ipw_soft_buf *sbuf; 339 int i, nsegs, error; 340 341 /* 342 * Allocate and map tx ring. 343 */ 344 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 345 BUS_DMA_NOWAIT, &sc->tbd_map); 346 if (error != 0) { 347 printf("%s: could not create tx ring DMA map\n", 348 sc->sc_dev.dv_xname); 349 goto fail; 350 } 351 352 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 353 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 354 if (error != 0) { 355 printf("%s: could not allocate tx ring DMA memory\n", 356 sc->sc_dev.dv_xname); 357 goto fail; 358 } 359 360 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 361 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 362 if (error != 0) { 363 printf("%s: can't map tx ring DMA memory\n", 364 sc->sc_dev.dv_xname); 365 goto fail; 366 } 367 368 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 369 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 370 if (error != 0) { 371 printf("%s: could not load tx ring DMA map\n", 372 sc->sc_dev.dv_xname); 373 goto fail; 374 } 375 376 /* 377 * Allocate and map rx ring. 378 */ 379 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 380 BUS_DMA_NOWAIT, &sc->rbd_map); 381 if (error != 0) { 382 printf("%s: could not create rx ring DMA map\n", 383 sc->sc_dev.dv_xname); 384 goto fail; 385 } 386 387 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 388 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 389 if (error != 0) { 390 printf("%s: could not allocate rx ring DMA memory\n", 391 sc->sc_dev.dv_xname); 392 goto fail; 393 } 394 395 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 396 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 397 if (error != 0) { 398 printf("%s: can't map rx ring DMA memory\n", 399 sc->sc_dev.dv_xname); 400 goto fail; 401 } 402 403 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 404 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 405 if (error != 0) { 406 printf("%s: could not load tx ring DMA map\n", 407 sc->sc_dev.dv_xname); 408 goto fail; 409 } 410 411 /* 412 * Allocate and map status ring. 413 */ 414 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 415 0, BUS_DMA_NOWAIT, &sc->status_map); 416 if (error != 0) { 417 printf("%s: could not create status ring DMA map\n", 418 sc->sc_dev.dv_xname); 419 goto fail; 420 } 421 422 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 423 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 424 if (error != 0) { 425 printf("%s: could not allocate status ring DMA memory\n", 426 sc->sc_dev.dv_xname); 427 goto fail; 428 } 429 430 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 431 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 432 if (error != 0) { 433 printf("%s: can't map status ring DMA memory\n", 434 sc->sc_dev.dv_xname); 435 goto fail; 436 } 437 438 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 439 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 440 if (error != 0) { 441 printf("%s: could not load status ring DMA map\n", 442 sc->sc_dev.dv_xname); 443 goto fail; 444 } 445 446 /* 447 * Allocate command DMA map. 448 */ 449 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 450 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 451 if (error != 0) { 452 printf("%s: could not create command DMA map\n", 453 sc->sc_dev.dv_xname); 454 goto fail; 455 } 456 457 /* 458 * Allocate headers DMA maps. 459 */ 460 SLIST_INIT(&sc->free_shdr); 461 for (i = 0; i < IPW_NDATA; i++) { 462 shdr = &sc->shdr_list[i]; 463 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 464 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 465 if (error != 0) { 466 printf("%s: could not create header DMA map\n", 467 sc->sc_dev.dv_xname); 468 goto fail; 469 } 470 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 471 } 472 473 /* 474 * Allocate tx buffers DMA maps. 475 */ 476 SLIST_INIT(&sc->free_sbuf); 477 for (i = 0; i < IPW_NDATA; i++) { 478 sbuf = &sc->tx_sbuf_list[i]; 479 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 480 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 481 if (error != 0) { 482 printf("%s: could not create tx DMA map\n", 483 sc->sc_dev.dv_xname); 484 goto fail; 485 } 486 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 487 } 488 489 /* 490 * Initialize tx ring. 491 */ 492 for (i = 0; i < IPW_NTBD; i++) { 493 sbd = &sc->stbd_list[i]; 494 sbd->bd = &sc->tbd_list[i]; 495 sbd->type = IPW_SBD_TYPE_NOASSOC; 496 } 497 498 /* 499 * Pre-allocate rx buffers and DMA maps. 500 */ 501 for (i = 0; i < IPW_NRBD; i++) { 502 sbd = &sc->srbd_list[i]; 503 sbuf = &sc->rx_sbuf_list[i]; 504 sbd->bd = &sc->rbd_list[i]; 505 506 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 507 if (sbuf->m == NULL) { 508 printf("%s: could not allocate rx mbuf\n", 509 sc->sc_dev.dv_xname); 510 error = ENOMEM; 511 goto fail; 512 } 513 MCLGET(sbuf->m, M_DONTWAIT); 514 if (!(sbuf->m->m_flags & M_EXT)) { 515 m_freem(sbuf->m); 516 printf("%s: could not allocate rx mbuf cluster\n", 517 sc->sc_dev.dv_xname); 518 error = ENOMEM; 519 goto fail; 520 } 521 522 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 523 0, BUS_DMA_NOWAIT, &sbuf->map); 524 if (error != 0) { 525 printf("%s: could not create rx DMA map\n", 526 sc->sc_dev.dv_xname); 527 goto fail; 528 } 529 530 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 531 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 532 if (error != 0) { 533 printf("%s: can't map rx DMA memory\n", 534 sc->sc_dev.dv_xname); 535 goto fail; 536 } 537 538 sbd->type = IPW_SBD_TYPE_DATA; 539 sbd->priv = sbuf; 540 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 541 sbd->bd->len = htole32(MCLBYTES); 542 } 543 544 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 545 BUS_DMASYNC_PREWRITE); 546 547 return 0; 548 549 fail: ipw_release(sc); 550 return error; 551 } 552 553 void 554 ipw_release(struct ipw_softc *sc) 555 { 556 struct ipw_soft_buf *sbuf; 557 int i; 558 559 if (sc->tbd_map != NULL) { 560 if (sc->tbd_list != NULL) { 561 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 562 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 563 IPW_TBD_SZ); 564 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 565 } 566 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 567 } 568 569 if (sc->rbd_map != NULL) { 570 if (sc->rbd_list != NULL) { 571 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 572 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 573 IPW_RBD_SZ); 574 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 575 } 576 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 577 } 578 579 if (sc->status_map != NULL) { 580 if (sc->status_list != NULL) { 581 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 582 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 583 IPW_RBD_SZ); 584 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 585 } 586 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 587 } 588 589 if (sc->cmd_map != NULL) 590 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 591 592 for (i = 0; i < IPW_NDATA; i++) 593 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 594 595 for (i = 0; i < IPW_NDATA; i++) 596 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 597 598 for (i = 0; i < IPW_NRBD; i++) { 599 sbuf = &sc->rx_sbuf_list[i]; 600 if (sbuf->map != NULL) { 601 if (sbuf->m != NULL) { 602 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 603 m_freem(sbuf->m); 604 } 605 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 606 } 607 } 608 609 task_del(systq, &sc->sc_scantask); 610 task_del(systq, &sc->sc_authandassoctask); 611 } 612 613 int 614 ipw_media_change(struct ifnet *ifp) 615 { 616 int error; 617 618 error = ieee80211_media_change(ifp); 619 if (error != ENETRESET) 620 return error; 621 622 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 623 ipw_init(ifp); 624 625 return 0; 626 } 627 628 void 629 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 630 { 631 struct ipw_softc *sc = ifp->if_softc; 632 struct ieee80211com *ic = &sc->sc_ic; 633 static const struct { 634 uint32_t val; 635 int rate; 636 } rates[] = { 637 { IPW_RATE_DS1, 2 }, 638 { IPW_RATE_DS2, 4 }, 639 { IPW_RATE_DS5, 11 }, 640 { IPW_RATE_DS11, 22 }, 641 }; 642 uint32_t val; 643 int rate, i; 644 645 imr->ifm_status = IFM_AVALID; 646 imr->ifm_active = IFM_IEEE80211; 647 if (ic->ic_state == IEEE80211_S_RUN) 648 imr->ifm_status |= IFM_ACTIVE; 649 650 /* read current transmission rate from adapter */ 651 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 652 val &= 0xf; 653 654 /* convert rate to 802.11 rate */ 655 for (i = 0; i < nitems(rates) && rates[i].val != val; i++); 656 rate = (i < nitems(rates)) ? rates[i].rate : 0; 657 658 imr->ifm_active |= IFM_IEEE80211_11B; 659 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 660 switch (ic->ic_opmode) { 661 case IEEE80211_M_STA: 662 break; 663 #ifndef IEEE80211_STA_ONLY 664 case IEEE80211_M_IBSS: 665 imr->ifm_active |= IFM_IEEE80211_IBSS; 666 break; 667 #endif 668 case IEEE80211_M_MONITOR: 669 imr->ifm_active |= IFM_IEEE80211_MONITOR; 670 break; 671 default: 672 /* should not get there */ 673 break; 674 } 675 } 676 677 int 678 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 679 { 680 struct ipw_softc *sc = ic->ic_softc; 681 682 switch (nstate) { 683 case IEEE80211_S_SCAN: 684 task_add(systq, &sc->sc_scantask); 685 break; 686 687 case IEEE80211_S_AUTH: 688 task_add(systq, &sc->sc_authandassoctask); 689 break; 690 691 case IEEE80211_S_RUN: 692 case IEEE80211_S_INIT: 693 case IEEE80211_S_ASSOC: 694 /* nothing to do */ 695 break; 696 } 697 698 ic->ic_state = nstate; 699 return 0; 700 } 701 702 /* 703 * Read 16 bits at address 'addr' from the Microwire EEPROM. 704 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 705 */ 706 uint16_t 707 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 708 { 709 uint32_t tmp; 710 uint16_t val; 711 int n; 712 713 /* clock C once before the first command */ 714 IPW_EEPROM_CTL(sc, 0); 715 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 716 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 717 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 718 719 /* write start bit (1) */ 720 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 721 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 722 723 /* write READ opcode (10) */ 724 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 725 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 726 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 727 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 728 729 /* write address A7-A0 */ 730 for (n = 7; n >= 0; n--) { 731 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 732 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 733 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 734 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 735 } 736 737 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 738 739 /* read data Q15-Q0 */ 740 val = 0; 741 for (n = 15; n >= 0; n--) { 742 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 743 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 744 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 745 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 746 } 747 748 IPW_EEPROM_CTL(sc, 0); 749 750 /* clear Chip Select and clock C */ 751 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 752 IPW_EEPROM_CTL(sc, 0); 753 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 754 755 return val; 756 } 757 758 void 759 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 760 { 761 struct ipw_cmd *cmd; 762 763 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 764 BUS_DMASYNC_POSTREAD); 765 766 cmd = mtod(sbuf->m, struct ipw_cmd *); 767 768 DPRINTFN(2, ("received command ack type=%u,status=%u\n", 769 letoh32(cmd->type), letoh32(cmd->status))); 770 771 wakeup(&sc->cmd); 772 } 773 774 void 775 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 776 { 777 struct ieee80211com *ic = &sc->sc_ic; 778 struct ifnet *ifp = &ic->ic_if; 779 uint32_t state; 780 781 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 782 BUS_DMASYNC_POSTREAD); 783 784 state = letoh32(*mtod(sbuf->m, uint32_t *)); 785 786 DPRINTFN(2, ("firmware state changed to 0x%x\n", state)); 787 788 switch (state) { 789 case IPW_STATE_ASSOCIATED: 790 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 791 break; 792 793 case IPW_STATE_SCANNING: 794 if (ic->ic_state == IEEE80211_S_RUN) 795 ieee80211_begin_scan(ifp); 796 break; 797 798 case IPW_STATE_SCAN_COMPLETE: 799 if (ic->ic_state == IEEE80211_S_SCAN) 800 ieee80211_end_scan(ifp); 801 break; 802 803 case IPW_STATE_ASSOCIATION_LOST: 804 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 805 break; 806 807 case IPW_STATE_DISABLED: 808 wakeup(sc); 809 break; 810 811 case IPW_STATE_RADIO_DISABLED: 812 ifp->if_flags &= ~IFF_UP; 813 ipw_stop(&ic->ic_if, 1); 814 break; 815 } 816 } 817 818 void 819 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 820 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 821 { 822 struct ieee80211com *ic = &sc->sc_ic; 823 struct ifnet *ifp = &ic->ic_if; 824 struct mbuf *mnew, *m; 825 struct ieee80211_frame *wh; 826 struct ieee80211_rxinfo rxi; 827 struct ieee80211_node *ni; 828 int error; 829 830 DPRINTFN(5, ("received data frame len=%u,rssi=%u\n", 831 letoh32(status->len), status->rssi)); 832 833 /* 834 * Try to allocate a new mbuf for this ring element and load it before 835 * processing the current mbuf. If the ring element cannot be loaded, 836 * drop the received packet and reuse the old mbuf. In the unlikely 837 * case that the old mbuf can't be reloaded either, explicitly panic. 838 */ 839 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 840 if (mnew == NULL) { 841 ifp->if_ierrors++; 842 return; 843 } 844 MCLGET(mnew, M_DONTWAIT); 845 if (!(mnew->m_flags & M_EXT)) { 846 m_freem(mnew); 847 ifp->if_ierrors++; 848 return; 849 } 850 851 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 852 BUS_DMASYNC_POSTREAD); 853 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 854 855 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(mnew, void *), 856 MCLBYTES, NULL, BUS_DMA_NOWAIT); 857 if (error != 0) { 858 m_freem(mnew); 859 860 /* try to reload the old mbuf */ 861 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 862 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 863 if (error != 0) { 864 /* very unlikely that it will fail... */ 865 panic("%s: could not load old rx mbuf", 866 sc->sc_dev.dv_xname); 867 } 868 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 869 ifp->if_ierrors++; 870 return; 871 } 872 873 m = sbuf->m; 874 sbuf->m = mnew; 875 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 876 877 /* finalize mbuf */ 878 m->m_pkthdr.len = m->m_len = letoh32(status->len); 879 880 #if NBPFILTER > 0 881 if (sc->sc_drvbpf != NULL) { 882 struct mbuf mb; 883 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 884 885 tap->wr_flags = 0; 886 tap->wr_antsignal = status->rssi; 887 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 888 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 889 890 mb.m_data = (caddr_t)tap; 891 mb.m_len = sc->sc_rxtap_len; 892 mb.m_next = m; 893 mb.m_nextpkt = NULL; 894 mb.m_type = 0; 895 mb.m_flags = 0; 896 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 897 } 898 #endif 899 900 wh = mtod(m, struct ieee80211_frame *); 901 ni = ieee80211_find_rxnode(ic, wh); 902 903 /* send the frame to the upper layer */ 904 rxi.rxi_flags = 0; 905 rxi.rxi_rssi = status->rssi; 906 rxi.rxi_tstamp = 0; /* unused */ 907 ieee80211_input(ifp, m, ni, &rxi); 908 909 ieee80211_release_node(ic, ni); 910 } 911 912 void 913 ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 914 { 915 DPRINTFN(2, ("received notification\n")); 916 } 917 918 void 919 ipw_rx_intr(struct ipw_softc *sc) 920 { 921 struct ipw_status *status; 922 struct ipw_soft_bd *sbd; 923 struct ipw_soft_buf *sbuf; 924 uint32_t r, i; 925 926 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 927 928 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 929 930 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 931 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 932 BUS_DMASYNC_POSTREAD); 933 934 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 935 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 936 BUS_DMASYNC_POSTREAD); 937 938 status = &sc->status_list[i]; 939 sbd = &sc->srbd_list[i]; 940 sbuf = sbd->priv; 941 942 switch (letoh16(status->code) & 0xf) { 943 case IPW_STATUS_CODE_COMMAND: 944 ipw_command_intr(sc, sbuf); 945 break; 946 947 case IPW_STATUS_CODE_NEWSTATE: 948 ipw_newstate_intr(sc, sbuf); 949 break; 950 951 case IPW_STATUS_CODE_DATA_802_3: 952 case IPW_STATUS_CODE_DATA_802_11: 953 ipw_data_intr(sc, status, sbd, sbuf); 954 break; 955 956 case IPW_STATUS_CODE_NOTIFICATION: 957 ipw_notification_intr(sc, sbuf); 958 break; 959 960 default: 961 printf("%s: unknown status code %u\n", 962 sc->sc_dev.dv_xname, letoh16(status->code)); 963 } 964 sbd->bd->flags = 0; 965 966 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 967 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 968 BUS_DMASYNC_PREWRITE); 969 } 970 971 /* tell the firmware what we have processed */ 972 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 973 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 974 } 975 976 void 977 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 978 { 979 struct ieee80211com *ic = &sc->sc_ic; 980 struct ipw_soft_hdr *shdr; 981 struct ipw_soft_buf *sbuf; 982 983 switch (sbd->type) { 984 case IPW_SBD_TYPE_COMMAND: 985 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 986 break; 987 988 case IPW_SBD_TYPE_HEADER: 989 shdr = sbd->priv; 990 bus_dmamap_unload(sc->sc_dmat, shdr->map); 991 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 992 break; 993 994 case IPW_SBD_TYPE_DATA: 995 sbuf = sbd->priv; 996 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 997 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 998 999 m_freem(sbuf->m); 1000 1001 if (sbuf->ni != NULL) 1002 ieee80211_release_node(ic, sbuf->ni); 1003 1004 /* kill watchdog timer */ 1005 sc->sc_tx_timer = 0; 1006 break; 1007 } 1008 sbd->type = IPW_SBD_TYPE_NOASSOC; 1009 } 1010 1011 void 1012 ipw_tx_intr(struct ipw_softc *sc) 1013 { 1014 struct ifnet *ifp = &sc->sc_ic.ic_if; 1015 struct ipw_soft_bd *sbd; 1016 uint32_t r, i; 1017 1018 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1019 1020 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1021 sbd = &sc->stbd_list[i]; 1022 1023 if (sbd->type == IPW_SBD_TYPE_DATA) 1024 ifp->if_opackets++; 1025 1026 ipw_release_sbd(sc, sbd); 1027 sc->txfree++; 1028 } 1029 1030 /* remember what the firmware has processed */ 1031 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1032 1033 /* call start() since some buffer descriptors have been released */ 1034 ifq_clr_oactive(&ifp->if_snd); 1035 (*ifp->if_start)(ifp); 1036 } 1037 1038 int 1039 ipw_intr(void *arg) 1040 { 1041 struct ipw_softc *sc = arg; 1042 struct ifnet *ifp = &sc->sc_ic.ic_if; 1043 uint32_t r; 1044 1045 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1046 return 0; 1047 1048 /* disable interrupts */ 1049 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1050 1051 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1052 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 1053 ifp->if_flags &= ~IFF_UP; 1054 ipw_stop(ifp, 1); 1055 return 1; 1056 } 1057 1058 if (r & IPW_INTR_FW_INIT_DONE) 1059 wakeup(sc); 1060 1061 if (r & IPW_INTR_RX_TRANSFER) 1062 ipw_rx_intr(sc); 1063 1064 if (r & IPW_INTR_TX_TRANSFER) 1065 ipw_tx_intr(sc); 1066 1067 /* acknowledge interrupts */ 1068 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1069 1070 /* re-enable interrupts */ 1071 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1072 1073 return 1; 1074 } 1075 1076 int 1077 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1078 { 1079 struct ipw_soft_bd *sbd; 1080 int s, error; 1081 1082 s = splnet(); 1083 1084 sc->cmd.type = htole32(type); 1085 sc->cmd.subtype = htole32(0); 1086 sc->cmd.len = htole32(len); 1087 sc->cmd.seq = htole32(0); 1088 if (data != NULL) 1089 bcopy(data, sc->cmd.data, len); 1090 1091 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1092 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1093 if (error != 0) { 1094 printf("%s: can't map command DMA memory\n", 1095 sc->sc_dev.dv_xname); 1096 splx(s); 1097 return error; 1098 } 1099 1100 sbd = &sc->stbd_list[sc->txcur]; 1101 sbd->type = IPW_SBD_TYPE_COMMAND; 1102 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1103 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1104 sbd->bd->nfrag = 1; 1105 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1106 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1107 1108 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1109 BUS_DMASYNC_PREWRITE); 1110 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1111 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1112 BUS_DMASYNC_PREWRITE); 1113 1114 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1115 sc->txfree--; 1116 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1117 1118 DPRINTFN(2, ("sending command type=%u,len=%u\n", type, len)); 1119 1120 /* wait at most one second for command to complete */ 1121 error = tsleep(&sc->cmd, 0, "ipwcmd", hz); 1122 splx(s); 1123 1124 return error; 1125 } 1126 1127 /* ARGSUSED */ 1128 int 1129 ipw_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1130 int arg1, int arg2) 1131 { 1132 return EOPNOTSUPP; 1133 } 1134 1135 int 1136 ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1137 { 1138 struct ipw_softc *sc = ifp->if_softc; 1139 struct ieee80211com *ic = &sc->sc_ic; 1140 struct ieee80211_frame *wh; 1141 struct ieee80211_key *k; 1142 struct ipw_soft_bd *sbd; 1143 struct ipw_soft_hdr *shdr; 1144 struct ipw_soft_buf *sbuf; 1145 int error, i; 1146 1147 wh = mtod(m, struct ieee80211_frame *); 1148 1149 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1150 k = ieee80211_get_txkey(ic, wh, ni); 1151 1152 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1153 return ENOBUFS; 1154 1155 /* packet header may have moved, reset our local pointer */ 1156 wh = mtod(m, struct ieee80211_frame *); 1157 } 1158 1159 #if NBPFILTER > 0 1160 if (sc->sc_drvbpf != NULL) { 1161 struct mbuf mb; 1162 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1163 1164 tap->wt_flags = 0; 1165 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1166 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1167 1168 mb.m_data = (caddr_t)tap; 1169 mb.m_len = sc->sc_txtap_len; 1170 mb.m_next = m; 1171 mb.m_nextpkt = NULL; 1172 mb.m_type = 0; 1173 mb.m_flags = 0; 1174 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1175 } 1176 #endif 1177 1178 shdr = SLIST_FIRST(&sc->free_shdr); 1179 sbuf = SLIST_FIRST(&sc->free_sbuf); 1180 1181 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1182 shdr->hdr.subtype = htole32(0); 1183 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) ? 1 : 0; 1184 shdr->hdr.encrypt = 0; 1185 shdr->hdr.keyidx = 0; 1186 shdr->hdr.keysz = 0; 1187 shdr->hdr.fragmentsz = htole16(0); 1188 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1189 if (ic->ic_opmode == IEEE80211_M_STA) 1190 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1191 else 1192 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1193 1194 /* trim IEEE802.11 header */ 1195 m_adj(m, sizeof (struct ieee80211_frame)); 1196 1197 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1198 if (error != 0 && error != EFBIG) { 1199 printf("%s: can't map mbuf (error %d)\n", 1200 sc->sc_dev.dv_xname, error); 1201 m_freem(m); 1202 return error; 1203 } 1204 if (error != 0) { 1205 /* too many fragments, linearize */ 1206 if (m_defrag(m, M_DONTWAIT)) { 1207 m_freem(m); 1208 return ENOBUFS; 1209 } 1210 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1211 BUS_DMA_NOWAIT); 1212 if (error != 0) { 1213 printf("%s: can't map mbuf (error %d)\n", 1214 sc->sc_dev.dv_xname, error); 1215 m_freem(m); 1216 return error; 1217 } 1218 } 1219 1220 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1221 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1222 if (error != 0) { 1223 printf("%s: can't map header DMA memory (error %d)\n", 1224 sc->sc_dev.dv_xname, error); 1225 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1226 m_freem(m); 1227 return error; 1228 } 1229 1230 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1231 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1232 1233 sbd = &sc->stbd_list[sc->txcur]; 1234 sbd->type = IPW_SBD_TYPE_HEADER; 1235 sbd->priv = shdr; 1236 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1237 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1238 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1239 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1240 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1241 1242 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1243 sc->txcur * sizeof (struct ipw_bd), 1244 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1245 1246 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1247 sc->txfree--; 1248 1249 sbuf->m = m; 1250 sbuf->ni = ni; 1251 1252 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1253 sbd = &sc->stbd_list[sc->txcur]; 1254 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1255 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1256 sbd->bd->nfrag = 0; /* used only in first bd */ 1257 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1258 if (i == sbuf->map->dm_nsegs - 1) { 1259 sbd->type = IPW_SBD_TYPE_DATA; 1260 sbd->priv = sbuf; 1261 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1262 } else { 1263 sbd->type = IPW_SBD_TYPE_NOASSOC; 1264 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1265 } 1266 1267 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1268 sc->txcur * sizeof (struct ipw_bd), 1269 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1270 1271 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1272 sc->txfree--; 1273 } 1274 1275 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1276 BUS_DMASYNC_PREWRITE); 1277 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1278 BUS_DMASYNC_PREWRITE); 1279 1280 /* inform firmware about this new packet */ 1281 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1282 1283 return 0; 1284 } 1285 1286 void 1287 ipw_start(struct ifnet *ifp) 1288 { 1289 struct ipw_softc *sc = ifp->if_softc; 1290 struct ieee80211com *ic = &sc->sc_ic; 1291 struct ieee80211_node *ni; 1292 struct mbuf *m; 1293 1294 if (ic->ic_state != IEEE80211_S_RUN) 1295 return; 1296 1297 for (;;) { 1298 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1299 ifq_set_oactive(&ifp->if_snd); 1300 break; 1301 } 1302 1303 IFQ_DEQUEUE(&ifp->if_snd, m); 1304 if (m == NULL) 1305 break; 1306 1307 #if NBPFILTER > 0 1308 if (ifp->if_bpf != NULL) 1309 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1310 #endif 1311 1312 m = ieee80211_encap(ifp, m, &ni); 1313 if (m == NULL) 1314 continue; 1315 #if NBPFILTER > 0 1316 if (ic->ic_rawbpf != NULL) 1317 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1318 #endif 1319 if (ipw_tx_start(ifp, m, ni) != 0) { 1320 if (ni != NULL) 1321 ieee80211_release_node(ic, ni); 1322 ifp->if_oerrors++; 1323 break; 1324 } 1325 1326 /* start watchdog timer */ 1327 sc->sc_tx_timer = 5; 1328 ifp->if_timer = 1; 1329 } 1330 } 1331 1332 void 1333 ipw_watchdog(struct ifnet *ifp) 1334 { 1335 struct ipw_softc *sc = ifp->if_softc; 1336 1337 ifp->if_timer = 0; 1338 1339 if (sc->sc_tx_timer > 0) { 1340 if (--sc->sc_tx_timer == 0) { 1341 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1342 ifp->if_flags &= ~IFF_UP; 1343 ipw_stop(ifp, 1); 1344 ifp->if_oerrors++; 1345 return; 1346 } 1347 ifp->if_timer = 1; 1348 } 1349 1350 ieee80211_watchdog(ifp); 1351 } 1352 1353 int 1354 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1355 { 1356 struct ipw_softc *sc = ifp->if_softc; 1357 struct ieee80211com *ic = &sc->sc_ic; 1358 struct ifreq *ifr; 1359 int s, error = 0; 1360 1361 error = rw_enter(&sc->sc_rwlock, RW_WRITE | RW_INTR); 1362 if (error) 1363 return error; 1364 s = splnet(); 1365 1366 switch (cmd) { 1367 case SIOCSIFADDR: 1368 ifp->if_flags |= IFF_UP; 1369 /* FALLTHROUGH */ 1370 case SIOCSIFFLAGS: 1371 if (ifp->if_flags & IFF_UP) { 1372 if (!(ifp->if_flags & IFF_RUNNING)) 1373 ipw_init(ifp); 1374 } else { 1375 if (ifp->if_flags & IFF_RUNNING) 1376 ipw_stop(ifp, 1); 1377 } 1378 break; 1379 1380 case SIOCADDMULTI: 1381 case SIOCDELMULTI: 1382 ifr = (struct ifreq *)data; 1383 error = (cmd == SIOCADDMULTI) ? 1384 ether_addmulti(ifr, &ic->ic_ac) : 1385 ether_delmulti(ifr, &ic->ic_ac); 1386 1387 if (error == ENETRESET) 1388 error = 0; 1389 break; 1390 1391 case SIOCG80211TXPOWER: 1392 /* 1393 * If the hardware radio transmitter switch is off, report a 1394 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1395 * transmitter is killed. 1396 */ 1397 ((struct ieee80211_txpower *)data)->i_val = 1398 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1399 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1400 break; 1401 1402 default: 1403 error = ieee80211_ioctl(ifp, cmd, data); 1404 } 1405 1406 if (error == ENETRESET) { 1407 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1408 (IFF_UP | IFF_RUNNING)) 1409 ipw_init(ifp); 1410 error = 0; 1411 } 1412 1413 splx(s); 1414 rw_exit_write(&sc->sc_rwlock); 1415 return error; 1416 } 1417 1418 uint32_t 1419 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1420 { 1421 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1422 } 1423 1424 void 1425 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1426 { 1427 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1428 } 1429 1430 int 1431 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1432 { 1433 uint32_t addr, info; 1434 uint16_t count, size; 1435 uint32_t total; 1436 1437 /* addr[4] + count[2] + size[2] */ 1438 addr = MEM_READ_4(sc, sc->table2_base + off); 1439 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1440 1441 count = info >> 16; 1442 size = info & 0xffff; 1443 total = count * size; 1444 1445 if (total > *len) { 1446 *len = total; 1447 return EINVAL; 1448 } 1449 *len = total; 1450 ipw_read_mem_1(sc, addr, buf, total); 1451 1452 return 0; 1453 } 1454 1455 void 1456 ipw_stop_master(struct ipw_softc *sc) 1457 { 1458 uint32_t tmp; 1459 int ntries; 1460 1461 /* disable interrupts */ 1462 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1463 1464 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1465 for (ntries = 0; ntries < 50; ntries++) { 1466 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1467 break; 1468 DELAY(10); 1469 } 1470 if (ntries == 50) 1471 printf("%s: timeout waiting for master\n", 1472 sc->sc_dev.dv_xname); 1473 1474 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1475 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1476 } 1477 1478 int 1479 ipw_reset(struct ipw_softc *sc) 1480 { 1481 uint32_t tmp; 1482 int ntries; 1483 1484 ipw_stop_master(sc); 1485 1486 /* move adapter to D0 state */ 1487 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1488 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1489 1490 /* wait for clock stabilization */ 1491 for (ntries = 0; ntries < 1000; ntries++) { 1492 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1493 break; 1494 DELAY(200); 1495 } 1496 if (ntries == 1000) 1497 return EIO; 1498 1499 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1500 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1501 1502 DELAY(10); 1503 1504 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1505 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1506 1507 return 0; 1508 } 1509 1510 int 1511 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1512 { 1513 int ntries; 1514 1515 /* voodoo from the Intel Linux driver */ 1516 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1517 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1518 1519 MEM_WRITE_2(sc, 0x220000, 0x0703); 1520 MEM_WRITE_2(sc, 0x220000, 0x0707); 1521 1522 MEM_WRITE_1(sc, 0x210014, 0x72); 1523 MEM_WRITE_1(sc, 0x210014, 0x72); 1524 1525 MEM_WRITE_1(sc, 0x210000, 0x40); 1526 MEM_WRITE_1(sc, 0x210000, 0x00); 1527 MEM_WRITE_1(sc, 0x210000, 0x40); 1528 1529 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1530 1531 MEM_WRITE_1(sc, 0x210000, 0x00); 1532 MEM_WRITE_1(sc, 0x210000, 0x00); 1533 MEM_WRITE_1(sc, 0x210000, 0x80); 1534 1535 MEM_WRITE_2(sc, 0x220000, 0x0703); 1536 MEM_WRITE_2(sc, 0x220000, 0x0707); 1537 1538 MEM_WRITE_1(sc, 0x210014, 0x72); 1539 MEM_WRITE_1(sc, 0x210014, 0x72); 1540 1541 MEM_WRITE_1(sc, 0x210000, 0x00); 1542 MEM_WRITE_1(sc, 0x210000, 0x80); 1543 1544 for (ntries = 0; ntries < 100; ntries++) { 1545 if (MEM_READ_1(sc, 0x210000) & 1) 1546 break; 1547 DELAY(1000); 1548 } 1549 if (ntries == 100) { 1550 printf("%s: timeout waiting for ucode to initialize\n", 1551 sc->sc_dev.dv_xname); 1552 return EIO; 1553 } 1554 1555 MEM_WRITE_4(sc, 0x3000e0, 0); 1556 1557 return 0; 1558 } 1559 1560 /* set of macros to handle unaligned little endian data in firmware image */ 1561 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1562 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1563 int 1564 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1565 { 1566 u_char *p, *end; 1567 uint32_t tmp, dst; 1568 uint16_t len; 1569 int error; 1570 1571 p = fw; 1572 end = fw + size; 1573 while (p < end) { 1574 if (p + 6 > end) 1575 return EINVAL; 1576 1577 dst = GETLE32(p); p += 4; 1578 len = GETLE16(p); p += 2; 1579 1580 if (p + len > end) 1581 return EINVAL; 1582 1583 ipw_write_mem_1(sc, dst, p, len); 1584 p += len; 1585 } 1586 1587 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1588 IPW_IO_LED_OFF); 1589 1590 /* allow interrupts so we know when the firmware is inited */ 1591 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1592 1593 /* tell the adapter to initialize the firmware */ 1594 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1595 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1596 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1597 1598 /* wait at most one second for firmware initialization to complete */ 1599 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1600 printf("%s: timeout waiting for firmware initialization to " 1601 "complete\n", sc->sc_dev.dv_xname); 1602 return error; 1603 } 1604 1605 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1606 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1607 IPW_IO_GPIO3_MASK); 1608 1609 return 0; 1610 } 1611 1612 int 1613 ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1614 { 1615 const struct ipw_firmware_hdr *hdr; 1616 const char *name; 1617 int error; 1618 1619 switch (sc->sc_ic.ic_opmode) { 1620 case IEEE80211_M_STA: 1621 name = "ipw-bss"; 1622 break; 1623 #ifndef IEEE80211_STA_ONLY 1624 case IEEE80211_M_IBSS: 1625 name = "ipw-ibss"; 1626 break; 1627 #endif 1628 case IEEE80211_M_MONITOR: 1629 name = "ipw-monitor"; 1630 break; 1631 default: 1632 /* should not get there */ 1633 return ENODEV; 1634 } 1635 if ((error = loadfirmware(name, &fw->data, &fw->size)) != 0) 1636 return error; 1637 1638 if (fw->size < sizeof (*hdr)) { 1639 error = EINVAL; 1640 goto fail; 1641 } 1642 hdr = (const struct ipw_firmware_hdr *)fw->data; 1643 fw->main_size = letoh32(hdr->main_size); 1644 fw->ucode_size = letoh32(hdr->ucode_size); 1645 1646 if (fw->size < sizeof (*hdr) + fw->main_size + fw->ucode_size) { 1647 error = EINVAL; 1648 goto fail; 1649 } 1650 fw->main = fw->data + sizeof (*hdr); 1651 fw->ucode = fw->main + fw->main_size; 1652 1653 return 0; 1654 1655 fail: free(fw->data, M_DEVBUF, fw->size); 1656 return error; 1657 } 1658 1659 void 1660 ipw_scan(void *arg1) 1661 { 1662 struct ipw_softc *sc = arg1; 1663 struct ifnet *ifp = &sc->sc_ic.ic_if; 1664 struct ipw_scan_options scan; 1665 uint8_t ssid[IEEE80211_NWID_LEN]; 1666 int error; 1667 1668 /* 1669 * Firmware has a bug and does not honour the ``do not associate 1670 * after scan'' bit in the scan command. To prevent the firmware 1671 * from associating after the scan, we set the ESSID to something 1672 * unlikely to be used by a real AP. 1673 * XXX would setting the desired BSSID to a multicast address work? 1674 */ 1675 memset(ssid, '\r', sizeof ssid); 1676 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ssid, sizeof ssid); 1677 if (error != 0) 1678 goto fail; 1679 1680 /* no mandatory BSSID */ 1681 DPRINTF(("Setting mandatory BSSID to null\n")); 1682 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1683 if (error != 0) 1684 goto fail; 1685 1686 scan.flags = htole32(IPW_SCAN_DO_NOT_ASSOCIATE | IPW_SCAN_MIXED_CELL); 1687 scan.channels = htole32(0x3fff); /* scan channels 1-14 */ 1688 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1689 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1690 if (error != 0) 1691 goto fail; 1692 1693 /* start scanning */ 1694 DPRINTF(("Enabling adapter\n")); 1695 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1696 if (error != 0) 1697 goto fail; 1698 1699 return; 1700 fail: 1701 printf("%s: scan request failed (error=%d)\n", sc->sc_dev.dv_xname, 1702 error); 1703 ieee80211_end_scan(ifp); 1704 } 1705 1706 void 1707 ipw_auth_and_assoc(void *arg1) 1708 { 1709 struct ipw_softc *sc = arg1; 1710 struct ieee80211com *ic = &sc->sc_ic; 1711 struct ieee80211_node *ni = ic->ic_bss; 1712 struct ipw_scan_options scan; 1713 struct ipw_security security; 1714 struct ipw_assoc_req assoc; 1715 uint32_t data; 1716 uint8_t chan; 1717 int s, error; 1718 1719 DPRINTF(("Disabling adapter\n")); 1720 error = ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1721 if (error != 0) 1722 goto fail; 1723 #if 1 1724 /* wait at most one second for card to be disabled */ 1725 s = splnet(); 1726 error = tsleep(sc, 0, "ipwdis", hz); 1727 splx(s); 1728 if (error != 0) { 1729 printf("%s: timeout waiting for disabled state\n", 1730 sc->sc_dev.dv_xname); 1731 goto fail; 1732 } 1733 #else 1734 /* Intel's Linux driver polls for the DISABLED state instead.. */ 1735 for (ntries = 0; ntries < 1000; ntries++) { 1736 if (ipw_read_table1(sc, IPW_INFO_CARD_DISABLED) == 1) 1737 break; 1738 DELAY(10); 1739 } 1740 if (ntries == 1000) { 1741 printf("%s: timeout waiting for disabled state\n", 1742 sc->sc_dev.dv_xname); 1743 goto fail; 1744 } 1745 #endif 1746 1747 bzero(&security, sizeof security); 1748 security.authmode = IPW_AUTH_OPEN; 1749 security.ciphers = htole32(IPW_CIPHER_NONE); 1750 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1751 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1752 sizeof security); 1753 if (error != 0) 1754 goto fail; 1755 1756 #ifdef IPW_DEBUG 1757 if (ipw_debug > 0) { 1758 printf("Setting ESSID to "); 1759 ieee80211_print_essid(ni->ni_essid, ni->ni_esslen); 1760 printf("\n"); 1761 } 1762 #endif 1763 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ni->ni_essid, ni->ni_esslen); 1764 if (error != 0) 1765 goto fail; 1766 1767 DPRINTF(("Setting BSSID to %s\n", ether_sprintf(ni->ni_bssid))); 1768 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, ni->ni_bssid, 1769 IEEE80211_ADDR_LEN); 1770 if (error != 0) 1771 goto fail; 1772 1773 data = htole32((ic->ic_flags & (IEEE80211_F_WEPON | 1774 IEEE80211_F_RSNON)) ? IPW_PRIVACYON : 0); 1775 DPRINTF(("Setting privacy flags to 0x%x\n", letoh32(data))); 1776 error = ipw_cmd(sc, IPW_CMD_SET_PRIVACY_FLAGS, &data, sizeof data); 1777 if (error != 0) 1778 goto fail; 1779 1780 /* let firmware set the capinfo, lintval, and bssid fixed fields */ 1781 bzero(&assoc, sizeof assoc); 1782 if (ic->ic_flags & IEEE80211_F_RSNON) { 1783 uint8_t *frm = assoc.optie; 1784 1785 /* tell firmware to add a WPA or RSN IE in (Re)Assoc req */ 1786 if (ni->ni_rsnprotos & IEEE80211_PROTO_RSN) 1787 frm = ieee80211_add_rsn(frm, ic, ni); 1788 else if (ni->ni_rsnprotos & IEEE80211_PROTO_WPA) 1789 frm = ieee80211_add_wpa(frm, ic, ni); 1790 assoc.optie_len = htole32(frm - assoc.optie); 1791 } 1792 DPRINTF(("Preparing assocation request (optional IE length=%d)\n", 1793 letoh32(assoc.optie_len))); 1794 error = ipw_cmd(sc, IPW_CMD_SET_ASSOC_REQ, &assoc, sizeof assoc); 1795 if (error != 0) 1796 goto fail; 1797 1798 scan.flags = htole32(IPW_SCAN_MIXED_CELL); 1799 chan = ieee80211_chan2ieee(ic, ni->ni_chan); 1800 scan.channels = htole32(1 << (chan - 1)); 1801 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1802 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1803 if (error != 0) 1804 goto fail; 1805 1806 /* trigger scan+association */ 1807 DPRINTF(("Enabling adapter\n")); 1808 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1809 if (error != 0) 1810 goto fail; 1811 1812 return; 1813 fail: 1814 printf("%s: association failed (error=%d)\n", sc->sc_dev.dv_xname, 1815 error); 1816 ieee80211_begin_scan(&ic->ic_if); 1817 } 1818 1819 int 1820 ipw_config(struct ipw_softc *sc) 1821 { 1822 struct ieee80211com *ic = &sc->sc_ic; 1823 struct ifnet *ifp = &ic->ic_if; 1824 struct ipw_configuration config; 1825 uint32_t data; 1826 int error; 1827 1828 switch (ic->ic_opmode) { 1829 case IEEE80211_M_STA: 1830 data = htole32(IPW_MODE_BSS); 1831 break; 1832 #ifndef IEEE80211_STA_ONLY 1833 case IEEE80211_M_IBSS: 1834 data = htole32(IPW_MODE_IBSS); 1835 break; 1836 #endif 1837 case IEEE80211_M_MONITOR: 1838 data = htole32(IPW_MODE_MONITOR); 1839 break; 1840 default: 1841 /* should not get there */ 1842 return ENODEV; 1843 } 1844 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1845 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1846 if (error != 0) 1847 return error; 1848 1849 if ( 1850 #ifndef IEEE80211_STA_ONLY 1851 ic->ic_opmode == IEEE80211_M_IBSS || 1852 #endif 1853 ic->ic_opmode == IEEE80211_M_MONITOR) { 1854 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1855 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1856 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1857 if (error != 0) 1858 return error; 1859 } 1860 1861 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1862 DPRINTF(("Enabling adapter\n")); 1863 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1864 } 1865 1866 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1867 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1868 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1869 IEEE80211_ADDR_LEN); 1870 if (error != 0) 1871 return error; 1872 1873 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1874 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1X_ENABLE); 1875 #ifndef IEEE80211_STA_ONLY 1876 if (ic->ic_opmode == IEEE80211_M_IBSS) 1877 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1878 #endif 1879 if (ifp->if_flags & IFF_PROMISC) 1880 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1881 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1882 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1883 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1884 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1885 if (error != 0) 1886 return error; 1887 1888 data = htole32(ic->ic_rtsthreshold); 1889 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1890 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1891 if (error != 0) 1892 return error; 1893 1894 data = htole32(ic->ic_fragthreshold); 1895 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1896 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1897 if (error != 0) 1898 return error; 1899 1900 data = htole32(0x3); /* 1, 2 */ 1901 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1902 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1903 if (error != 0) 1904 return error; 1905 1906 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1907 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1908 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1909 if (error != 0) 1910 return error; 1911 1912 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1913 DPRINTF(("Setting MSDU tx rates to 0x%x\n", letoh32(data))); 1914 error = ipw_cmd(sc, IPW_CMD_SET_MSDU_TX_RATES, &data, sizeof data); 1915 if (error != 0) 1916 return error; 1917 1918 data = htole32(IPW_POWER_MODE_CAM); 1919 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1920 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1921 if (error != 0) 1922 return error; 1923 1924 #ifndef IEEE80211_STA_ONLY 1925 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1926 data = htole32(32); /* default value */ 1927 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1928 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1929 sizeof data); 1930 if (error != 0) 1931 return error; 1932 1933 data = htole32(ic->ic_lintval); 1934 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1935 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1936 sizeof data); 1937 if (error != 0) 1938 return error; 1939 } 1940 #endif 1941 return 0; 1942 } 1943 1944 int 1945 ipw_init(struct ifnet *ifp) 1946 { 1947 struct ipw_softc *sc = ifp->if_softc; 1948 struct ieee80211com *ic = &sc->sc_ic; 1949 struct ipw_firmware fw; 1950 int error; 1951 1952 ipw_stop(ifp, 0); 1953 1954 if ((error = ipw_reset(sc)) != 0) { 1955 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1956 goto fail1; 1957 } 1958 1959 if ((error = ipw_read_firmware(sc, &fw)) != 0) { 1960 printf("%s: error %d, could not read firmware\n", 1961 sc->sc_dev.dv_xname, error); 1962 goto fail1; 1963 } 1964 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 1965 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 1966 goto fail2; 1967 } 1968 1969 ipw_stop_master(sc); 1970 1971 /* 1972 * Setup tx, rx and status rings. 1973 */ 1974 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1975 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1976 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1977 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1978 sc->txold = IPW_NTBD - 1; /* latest bd index ack by firmware */ 1979 sc->txcur = 0; /* bd index to write to */ 1980 sc->txfree = IPW_NTBD - 2; 1981 1982 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1983 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1984 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1985 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1986 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1987 1988 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1989 sc->status_map->dm_segs[0].ds_addr); 1990 1991 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 1992 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 1993 goto fail2; 1994 } 1995 free(fw.data, M_DEVBUF, fw.size); 1996 fw.data = NULL; 1997 1998 /* retrieve information tables base addresses */ 1999 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2000 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2001 2002 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2003 2004 if ((error = ipw_config(sc)) != 0) { 2005 printf("%s: device configuration failed\n", 2006 sc->sc_dev.dv_xname); 2007 goto fail1; 2008 } 2009 2010 ifq_clr_oactive(&ifp->if_snd); 2011 ifp->if_flags |= IFF_RUNNING; 2012 2013 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2014 ieee80211_begin_scan(ifp); 2015 else 2016 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2017 2018 return 0; 2019 2020 fail2: free(fw.data, M_DEVBUF, fw.size); 2021 fw.data = NULL; 2022 fail1: ipw_stop(ifp, 0); 2023 return error; 2024 } 2025 2026 void 2027 ipw_stop(struct ifnet *ifp, int disable) 2028 { 2029 struct ipw_softc *sc = ifp->if_softc; 2030 struct ieee80211com *ic = &sc->sc_ic; 2031 int i; 2032 2033 ipw_stop_master(sc); 2034 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2035 2036 ifp->if_timer = 0; 2037 ifp->if_flags &= ~IFF_RUNNING; 2038 ifq_clr_oactive(&ifp->if_snd); 2039 2040 /* 2041 * Release tx buffers. 2042 */ 2043 for (i = 0; i < IPW_NTBD; i++) 2044 ipw_release_sbd(sc, &sc->stbd_list[i]); 2045 2046 /* in case we were scanning, release the scan "lock" */ 2047 ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; 2048 2049 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2050 } 2051 2052 void 2053 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2054 bus_size_t count) 2055 { 2056 for (; count > 0; offset++, datap++, count--) { 2057 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2058 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2059 } 2060 } 2061 2062 void 2063 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2064 bus_size_t count) 2065 { 2066 for (; count > 0; offset++, datap++, count--) { 2067 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2068 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2069 } 2070 } 2071 2072 struct cfdriver ipw_cd = { 2073 NULL, "ipw", DV_IFNET 2074 }; 2075