1 /* $OpenBSD: if_ipw.c,v 1.122 2018/04/26 12:50:07 pirofti Exp $ */ 2 3 /*- 4 * Copyright (c) 2004-2008 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Intel PRO/Wireless 2100 802.11 network adapters. 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/task.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/rwlock.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/conf.h> 35 #include <sys/device.h> 36 #include <sys/endian.h> 37 38 #include <machine/bus.h> 39 #include <machine/intr.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcidevs.h> 44 45 #if NBPFILTER > 0 46 #include <net/bpf.h> 47 #endif 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include <net80211/ieee80211_var.h> 56 #include <net80211/ieee80211_radiotap.h> 57 58 #include <dev/pci/if_ipwreg.h> 59 #include <dev/pci/if_ipwvar.h> 60 61 int ipw_match(struct device *, void *, void *); 62 void ipw_attach(struct device *, struct device *, void *); 63 int ipw_activate(struct device *, int); 64 void ipw_wakeup(struct ipw_softc *); 65 int ipw_dma_alloc(struct ipw_softc *); 66 void ipw_release(struct ipw_softc *); 67 int ipw_media_change(struct ifnet *); 68 void ipw_media_status(struct ifnet *, struct ifmediareq *); 69 int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 70 uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 71 void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 72 void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 73 void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 74 struct ipw_soft_bd *, struct ipw_soft_buf *); 75 void ipw_notification_intr(struct ipw_softc *, 76 struct ipw_soft_buf *); 77 void ipw_rx_intr(struct ipw_softc *); 78 void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 79 void ipw_tx_intr(struct ipw_softc *); 80 int ipw_intr(void *); 81 int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 82 int ipw_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 83 int, int, int); 84 int ipw_tx_start(struct ifnet *, struct mbuf *, 85 struct ieee80211_node *); 86 void ipw_start(struct ifnet *); 87 void ipw_watchdog(struct ifnet *); 88 int ipw_ioctl(struct ifnet *, u_long, caddr_t); 89 uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 90 void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 91 int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 92 uint32_t *); 93 void ipw_stop_master(struct ipw_softc *); 94 int ipw_reset(struct ipw_softc *); 95 int ipw_load_ucode(struct ipw_softc *, u_char *, int); 96 int ipw_load_firmware(struct ipw_softc *, u_char *, int); 97 int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 98 void ipw_scan(void *); 99 void ipw_auth_and_assoc(void *); 100 int ipw_config(struct ipw_softc *); 101 int ipw_init(struct ifnet *); 102 void ipw_stop(struct ifnet *, int); 103 void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 104 bus_size_t); 105 void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 106 bus_size_t); 107 108 static __inline uint8_t 109 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 110 { 111 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 112 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 113 } 114 115 static __inline uint32_t 116 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 117 { 118 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 119 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 120 } 121 122 #ifdef IPW_DEBUG 123 #define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 124 #define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 125 int ipw_debug = 0; 126 #else 127 #define DPRINTF(x) 128 #define DPRINTFN(n, x) 129 #endif 130 131 struct cfattach ipw_ca = { 132 sizeof (struct ipw_softc), ipw_match, ipw_attach, NULL, 133 ipw_activate 134 }; 135 136 int 137 ipw_match(struct device *parent, void *match, void *aux) 138 { 139 struct pci_attach_args *pa = aux; 140 141 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 142 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 143 return 1; 144 145 return 0; 146 } 147 148 /* Base Address Register */ 149 #define IPW_PCI_BAR0 0x10 150 151 void 152 ipw_attach(struct device *parent, struct device *self, void *aux) 153 { 154 struct ipw_softc *sc = (struct ipw_softc *)self; 155 struct ieee80211com *ic = &sc->sc_ic; 156 struct ifnet *ifp = &ic->ic_if; 157 struct pci_attach_args *pa = aux; 158 const char *intrstr; 159 bus_space_tag_t memt; 160 bus_space_handle_t memh; 161 bus_addr_t base; 162 pci_intr_handle_t ih; 163 pcireg_t data; 164 uint16_t val; 165 int error, i; 166 167 sc->sc_pct = pa->pa_pc; 168 sc->sc_pcitag = pa->pa_tag, 169 170 /* clear device specific PCI configuration register 0x41 */ 171 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 172 data &= ~0x0000ff00; 173 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 174 175 /* map the register window */ 176 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 177 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 178 if (error != 0) { 179 printf(": can't map mem space\n"); 180 return; 181 } 182 183 sc->sc_st = memt; 184 sc->sc_sh = memh; 185 sc->sc_dmat = pa->pa_dmat; 186 187 /* disable interrupts */ 188 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 189 190 if (pci_intr_map(pa, &ih) != 0) { 191 printf(": can't map interrupt\n"); 192 return; 193 } 194 195 intrstr = pci_intr_string(sc->sc_pct, ih); 196 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 197 sc->sc_dev.dv_xname); 198 if (sc->sc_ih == NULL) { 199 printf(": can't establish interrupt"); 200 if (intrstr != NULL) 201 printf(" at %s", intrstr); 202 printf("\n"); 203 return; 204 } 205 printf(": %s", intrstr); 206 207 rw_init(&sc->sc_rwlock, "ipwlock"); 208 task_set(&sc->sc_scantask, ipw_scan, sc); 209 task_set(&sc->sc_authandassoctask, ipw_auth_and_assoc, sc); 210 211 if (ipw_reset(sc) != 0) { 212 printf(": could not reset adapter\n"); 213 return; 214 } 215 216 if (ipw_dma_alloc(sc) != 0) { 217 printf(": failed to allocate DMA resources\n"); 218 return; 219 } 220 221 ic->ic_phytype = IEEE80211_T_DS; 222 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 223 ic->ic_state = IEEE80211_S_INIT; 224 225 /* set device capabilities */ 226 ic->ic_caps = 227 #ifndef IEEE80211_STA_ONLY 228 IEEE80211_C_IBSS | /* IBSS mode supported */ 229 #endif 230 IEEE80211_C_MONITOR | /* monitor mode supported */ 231 IEEE80211_C_TXPMGT | /* tx power management */ 232 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 233 IEEE80211_C_WEP | /* s/w WEP */ 234 IEEE80211_C_RSN | /* WPA/RSN */ 235 IEEE80211_C_SCANALL; /* h/w scanning */ 236 237 /* read MAC address from EEPROM */ 238 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 239 ic->ic_myaddr[0] = val >> 8; 240 ic->ic_myaddr[1] = val & 0xff; 241 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 242 ic->ic_myaddr[2] = val >> 8; 243 ic->ic_myaddr[3] = val & 0xff; 244 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 245 ic->ic_myaddr[4] = val >> 8; 246 ic->ic_myaddr[5] = val & 0xff; 247 248 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 249 250 /* set supported .11b rates */ 251 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 252 253 /* set supported .11b channels (1 through 14) */ 254 for (i = 1; i <= 14; i++) { 255 ic->ic_channels[i].ic_freq = 256 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 257 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 258 } 259 260 /* IBSS channel undefined for now */ 261 ic->ic_ibss_chan = &ic->ic_channels[0]; 262 263 ifp->if_softc = sc; 264 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 265 ifp->if_ioctl = ipw_ioctl; 266 ifp->if_start = ipw_start; 267 ifp->if_watchdog = ipw_watchdog; 268 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 269 270 if_attach(ifp); 271 ieee80211_ifattach(ifp); 272 /* override state transition machine */ 273 sc->sc_newstate = ic->ic_newstate; 274 ic->ic_newstate = ipw_newstate; 275 ic->ic_send_mgmt = ipw_send_mgmt; 276 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 277 278 #if NBPFILTER > 0 279 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 280 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 281 282 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 283 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 284 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 285 286 sc->sc_txtap_len = sizeof sc->sc_txtapu; 287 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 288 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 289 #endif 290 } 291 292 int 293 ipw_activate(struct device *self, int act) 294 { 295 struct ipw_softc *sc = (struct ipw_softc *)self; 296 struct ifnet *ifp = &sc->sc_ic.ic_if; 297 298 switch (act) { 299 case DVACT_SUSPEND: 300 if (ifp->if_flags & IFF_RUNNING) 301 ipw_stop(ifp, 0); 302 break; 303 case DVACT_WAKEUP: 304 ipw_wakeup(sc); 305 break; 306 } 307 308 return 0; 309 } 310 311 void 312 ipw_wakeup(struct ipw_softc *sc) 313 { 314 struct ifnet *ifp = &sc->sc_ic.ic_if; 315 pcireg_t data; 316 int s; 317 318 /* clear device specific PCI configuration register 0x41 */ 319 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 320 data &= ~0x0000ff00; 321 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 322 323 rw_enter_write(&sc->sc_rwlock); 324 s = splnet(); 325 326 if (ifp->if_flags & IFF_UP) 327 ipw_init(ifp); 328 329 splx(s); 330 rw_exit_write(&sc->sc_rwlock); 331 } 332 333 int 334 ipw_dma_alloc(struct ipw_softc *sc) 335 { 336 struct ipw_soft_bd *sbd; 337 struct ipw_soft_hdr *shdr; 338 struct ipw_soft_buf *sbuf; 339 int i, nsegs, error; 340 341 /* 342 * Allocate and map tx ring. 343 */ 344 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 345 BUS_DMA_NOWAIT, &sc->tbd_map); 346 if (error != 0) { 347 printf("%s: could not create tx ring DMA map\n", 348 sc->sc_dev.dv_xname); 349 goto fail; 350 } 351 352 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 353 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 354 if (error != 0) { 355 printf("%s: could not allocate tx ring DMA memory\n", 356 sc->sc_dev.dv_xname); 357 goto fail; 358 } 359 360 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 361 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 362 if (error != 0) { 363 printf("%s: can't map tx ring DMA memory\n", 364 sc->sc_dev.dv_xname); 365 goto fail; 366 } 367 368 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 369 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 370 if (error != 0) { 371 printf("%s: could not load tx ring DMA map\n", 372 sc->sc_dev.dv_xname); 373 goto fail; 374 } 375 376 /* 377 * Allocate and map rx ring. 378 */ 379 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 380 BUS_DMA_NOWAIT, &sc->rbd_map); 381 if (error != 0) { 382 printf("%s: could not create rx ring DMA map\n", 383 sc->sc_dev.dv_xname); 384 goto fail; 385 } 386 387 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 388 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 389 if (error != 0) { 390 printf("%s: could not allocate rx ring DMA memory\n", 391 sc->sc_dev.dv_xname); 392 goto fail; 393 } 394 395 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 396 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 397 if (error != 0) { 398 printf("%s: can't map rx ring DMA memory\n", 399 sc->sc_dev.dv_xname); 400 goto fail; 401 } 402 403 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 404 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 405 if (error != 0) { 406 printf("%s: could not load tx ring DMA map\n", 407 sc->sc_dev.dv_xname); 408 goto fail; 409 } 410 411 /* 412 * Allocate and map status ring. 413 */ 414 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 415 0, BUS_DMA_NOWAIT, &sc->status_map); 416 if (error != 0) { 417 printf("%s: could not create status ring DMA map\n", 418 sc->sc_dev.dv_xname); 419 goto fail; 420 } 421 422 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 423 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 424 if (error != 0) { 425 printf("%s: could not allocate status ring DMA memory\n", 426 sc->sc_dev.dv_xname); 427 goto fail; 428 } 429 430 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 431 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 432 if (error != 0) { 433 printf("%s: can't map status ring DMA memory\n", 434 sc->sc_dev.dv_xname); 435 goto fail; 436 } 437 438 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 439 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 440 if (error != 0) { 441 printf("%s: could not load status ring DMA map\n", 442 sc->sc_dev.dv_xname); 443 goto fail; 444 } 445 446 /* 447 * Allocate command DMA map. 448 */ 449 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 450 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 451 if (error != 0) { 452 printf("%s: could not create command DMA map\n", 453 sc->sc_dev.dv_xname); 454 goto fail; 455 } 456 457 /* 458 * Allocate headers DMA maps. 459 */ 460 SLIST_INIT(&sc->free_shdr); 461 for (i = 0; i < IPW_NDATA; i++) { 462 shdr = &sc->shdr_list[i]; 463 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 464 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 465 if (error != 0) { 466 printf("%s: could not create header DMA map\n", 467 sc->sc_dev.dv_xname); 468 goto fail; 469 } 470 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 471 } 472 473 /* 474 * Allocate tx buffers DMA maps. 475 */ 476 SLIST_INIT(&sc->free_sbuf); 477 for (i = 0; i < IPW_NDATA; i++) { 478 sbuf = &sc->tx_sbuf_list[i]; 479 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 480 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 481 if (error != 0) { 482 printf("%s: could not create tx DMA map\n", 483 sc->sc_dev.dv_xname); 484 goto fail; 485 } 486 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 487 } 488 489 /* 490 * Initialize tx ring. 491 */ 492 for (i = 0; i < IPW_NTBD; i++) { 493 sbd = &sc->stbd_list[i]; 494 sbd->bd = &sc->tbd_list[i]; 495 sbd->type = IPW_SBD_TYPE_NOASSOC; 496 } 497 498 /* 499 * Pre-allocate rx buffers and DMA maps. 500 */ 501 for (i = 0; i < IPW_NRBD; i++) { 502 sbd = &sc->srbd_list[i]; 503 sbuf = &sc->rx_sbuf_list[i]; 504 sbd->bd = &sc->rbd_list[i]; 505 506 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 507 if (sbuf->m == NULL) { 508 printf("%s: could not allocate rx mbuf\n", 509 sc->sc_dev.dv_xname); 510 error = ENOMEM; 511 goto fail; 512 } 513 MCLGET(sbuf->m, M_DONTWAIT); 514 if (!(sbuf->m->m_flags & M_EXT)) { 515 m_freem(sbuf->m); 516 printf("%s: could not allocate rx mbuf cluster\n", 517 sc->sc_dev.dv_xname); 518 error = ENOMEM; 519 goto fail; 520 } 521 522 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 523 0, BUS_DMA_NOWAIT, &sbuf->map); 524 if (error != 0) { 525 printf("%s: could not create rx DMA map\n", 526 sc->sc_dev.dv_xname); 527 goto fail; 528 } 529 530 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 531 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 532 if (error != 0) { 533 printf("%s: can't map rx DMA memory\n", 534 sc->sc_dev.dv_xname); 535 goto fail; 536 } 537 538 sbd->type = IPW_SBD_TYPE_DATA; 539 sbd->priv = sbuf; 540 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 541 sbd->bd->len = htole32(MCLBYTES); 542 } 543 544 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 545 BUS_DMASYNC_PREWRITE); 546 547 return 0; 548 549 fail: ipw_release(sc); 550 return error; 551 } 552 553 void 554 ipw_release(struct ipw_softc *sc) 555 { 556 struct ipw_soft_buf *sbuf; 557 int i; 558 559 if (sc->tbd_map != NULL) { 560 if (sc->tbd_list != NULL) { 561 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 562 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 563 IPW_TBD_SZ); 564 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 565 } 566 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 567 } 568 569 if (sc->rbd_map != NULL) { 570 if (sc->rbd_list != NULL) { 571 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 572 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 573 IPW_RBD_SZ); 574 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 575 } 576 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 577 } 578 579 if (sc->status_map != NULL) { 580 if (sc->status_list != NULL) { 581 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 582 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 583 IPW_RBD_SZ); 584 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 585 } 586 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 587 } 588 589 if (sc->cmd_map != NULL) 590 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 591 592 for (i = 0; i < IPW_NDATA; i++) 593 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 594 595 for (i = 0; i < IPW_NDATA; i++) 596 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 597 598 for (i = 0; i < IPW_NRBD; i++) { 599 sbuf = &sc->rx_sbuf_list[i]; 600 if (sbuf->map != NULL) { 601 if (sbuf->m != NULL) { 602 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 603 m_freem(sbuf->m); 604 } 605 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 606 } 607 } 608 609 task_del(systq, &sc->sc_scantask); 610 task_del(systq, &sc->sc_authandassoctask); 611 } 612 613 int 614 ipw_media_change(struct ifnet *ifp) 615 { 616 int error; 617 618 error = ieee80211_media_change(ifp); 619 if (error != ENETRESET) 620 return error; 621 622 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 623 ipw_init(ifp); 624 625 return 0; 626 } 627 628 void 629 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 630 { 631 struct ipw_softc *sc = ifp->if_softc; 632 struct ieee80211com *ic = &sc->sc_ic; 633 static const struct { 634 uint32_t val; 635 int rate; 636 } rates[] = { 637 { IPW_RATE_DS1, 2 }, 638 { IPW_RATE_DS2, 4 }, 639 { IPW_RATE_DS5, 11 }, 640 { IPW_RATE_DS11, 22 }, 641 }; 642 uint32_t val; 643 int rate, i; 644 645 imr->ifm_status = IFM_AVALID; 646 imr->ifm_active = IFM_IEEE80211; 647 if (ic->ic_state == IEEE80211_S_RUN) 648 imr->ifm_status |= IFM_ACTIVE; 649 650 /* read current transmission rate from adapter */ 651 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 652 val &= 0xf; 653 654 /* convert rate to 802.11 rate */ 655 for (i = 0; i < nitems(rates) && rates[i].val != val; i++); 656 rate = (i < nitems(rates)) ? rates[i].rate : 0; 657 658 imr->ifm_active |= IFM_IEEE80211_11B; 659 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 660 switch (ic->ic_opmode) { 661 case IEEE80211_M_STA: 662 break; 663 #ifndef IEEE80211_STA_ONLY 664 case IEEE80211_M_IBSS: 665 imr->ifm_active |= IFM_IEEE80211_IBSS; 666 break; 667 #endif 668 case IEEE80211_M_MONITOR: 669 imr->ifm_active |= IFM_IEEE80211_MONITOR; 670 break; 671 default: 672 /* should not get there */ 673 break; 674 } 675 } 676 677 int 678 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 679 { 680 struct ipw_softc *sc = ic->ic_softc; 681 682 switch (nstate) { 683 case IEEE80211_S_SCAN: 684 task_add(systq, &sc->sc_scantask); 685 break; 686 687 case IEEE80211_S_AUTH: 688 task_add(systq, &sc->sc_authandassoctask); 689 break; 690 691 case IEEE80211_S_RUN: 692 case IEEE80211_S_INIT: 693 case IEEE80211_S_ASSOC: 694 /* nothing to do */ 695 break; 696 } 697 698 ic->ic_state = nstate; 699 return 0; 700 } 701 702 /* 703 * Read 16 bits at address 'addr' from the Microwire EEPROM. 704 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 705 */ 706 uint16_t 707 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 708 { 709 uint32_t tmp; 710 uint16_t val; 711 int n; 712 713 /* clock C once before the first command */ 714 IPW_EEPROM_CTL(sc, 0); 715 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 716 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 717 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 718 719 /* write start bit (1) */ 720 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 721 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 722 723 /* write READ opcode (10) */ 724 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 725 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 726 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 727 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 728 729 /* write address A7-A0 */ 730 for (n = 7; n >= 0; n--) { 731 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 732 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 733 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 734 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 735 } 736 737 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 738 739 /* read data Q15-Q0 */ 740 val = 0; 741 for (n = 15; n >= 0; n--) { 742 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 743 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 744 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 745 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 746 } 747 748 IPW_EEPROM_CTL(sc, 0); 749 750 /* clear Chip Select and clock C */ 751 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 752 IPW_EEPROM_CTL(sc, 0); 753 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 754 755 return val; 756 } 757 758 void 759 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 760 { 761 struct ipw_cmd *cmd; 762 763 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 764 BUS_DMASYNC_POSTREAD); 765 766 cmd = mtod(sbuf->m, struct ipw_cmd *); 767 768 DPRINTFN(2, ("received command ack type=%u,status=%u\n", 769 letoh32(cmd->type), letoh32(cmd->status))); 770 771 wakeup(&sc->cmd); 772 } 773 774 void 775 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 776 { 777 struct ieee80211com *ic = &sc->sc_ic; 778 struct ifnet *ifp = &ic->ic_if; 779 uint32_t state; 780 781 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 782 BUS_DMASYNC_POSTREAD); 783 784 state = letoh32(*mtod(sbuf->m, uint32_t *)); 785 786 DPRINTFN(2, ("firmware state changed to 0x%x\n", state)); 787 788 switch (state) { 789 case IPW_STATE_ASSOCIATED: 790 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 791 break; 792 793 case IPW_STATE_SCANNING: 794 if (ic->ic_state == IEEE80211_S_RUN) 795 ieee80211_begin_scan(ifp); 796 break; 797 798 case IPW_STATE_SCAN_COMPLETE: 799 if (ic->ic_state == IEEE80211_S_SCAN) 800 ieee80211_end_scan(ifp); 801 break; 802 803 case IPW_STATE_ASSOCIATION_LOST: 804 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 805 break; 806 807 case IPW_STATE_DISABLED: 808 wakeup(sc); 809 break; 810 811 case IPW_STATE_RADIO_DISABLED: 812 ipw_stop(&ic->ic_if, 1); 813 break; 814 } 815 } 816 817 void 818 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 819 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 820 { 821 struct ieee80211com *ic = &sc->sc_ic; 822 struct ifnet *ifp = &ic->ic_if; 823 struct mbuf *mnew, *m; 824 struct ieee80211_frame *wh; 825 struct ieee80211_rxinfo rxi; 826 struct ieee80211_node *ni; 827 int error; 828 829 DPRINTFN(5, ("received data frame len=%u,rssi=%u\n", 830 letoh32(status->len), status->rssi)); 831 832 /* 833 * Try to allocate a new mbuf for this ring element and load it before 834 * processing the current mbuf. If the ring element cannot be loaded, 835 * drop the received packet and reuse the old mbuf. In the unlikely 836 * case that the old mbuf can't be reloaded either, explicitly panic. 837 */ 838 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 839 if (mnew == NULL) { 840 ifp->if_ierrors++; 841 return; 842 } 843 MCLGET(mnew, M_DONTWAIT); 844 if (!(mnew->m_flags & M_EXT)) { 845 m_freem(mnew); 846 ifp->if_ierrors++; 847 return; 848 } 849 850 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 851 BUS_DMASYNC_POSTREAD); 852 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 853 854 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(mnew, void *), 855 MCLBYTES, NULL, BUS_DMA_NOWAIT); 856 if (error != 0) { 857 m_freem(mnew); 858 859 /* try to reload the old mbuf */ 860 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 861 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 862 if (error != 0) { 863 /* very unlikely that it will fail... */ 864 panic("%s: could not load old rx mbuf", 865 sc->sc_dev.dv_xname); 866 } 867 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 868 ifp->if_ierrors++; 869 return; 870 } 871 872 m = sbuf->m; 873 sbuf->m = mnew; 874 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 875 876 /* finalize mbuf */ 877 m->m_pkthdr.len = m->m_len = letoh32(status->len); 878 879 #if NBPFILTER > 0 880 if (sc->sc_drvbpf != NULL) { 881 struct mbuf mb; 882 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 883 884 tap->wr_flags = 0; 885 tap->wr_antsignal = status->rssi; 886 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 887 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 888 889 mb.m_data = (caddr_t)tap; 890 mb.m_len = sc->sc_rxtap_len; 891 mb.m_next = m; 892 mb.m_nextpkt = NULL; 893 mb.m_type = 0; 894 mb.m_flags = 0; 895 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 896 } 897 #endif 898 899 wh = mtod(m, struct ieee80211_frame *); 900 ni = ieee80211_find_rxnode(ic, wh); 901 902 /* send the frame to the upper layer */ 903 rxi.rxi_flags = 0; 904 rxi.rxi_rssi = status->rssi; 905 rxi.rxi_tstamp = 0; /* unused */ 906 ieee80211_input(ifp, m, ni, &rxi); 907 908 ieee80211_release_node(ic, ni); 909 } 910 911 void 912 ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 913 { 914 DPRINTFN(2, ("received notification\n")); 915 } 916 917 void 918 ipw_rx_intr(struct ipw_softc *sc) 919 { 920 struct ipw_status *status; 921 struct ipw_soft_bd *sbd; 922 struct ipw_soft_buf *sbuf; 923 uint32_t r, i; 924 925 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 926 927 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 928 929 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 930 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 931 BUS_DMASYNC_POSTREAD); 932 933 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 934 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 935 BUS_DMASYNC_POSTREAD); 936 937 status = &sc->status_list[i]; 938 sbd = &sc->srbd_list[i]; 939 sbuf = sbd->priv; 940 941 switch (letoh16(status->code) & 0xf) { 942 case IPW_STATUS_CODE_COMMAND: 943 ipw_command_intr(sc, sbuf); 944 break; 945 946 case IPW_STATUS_CODE_NEWSTATE: 947 ipw_newstate_intr(sc, sbuf); 948 break; 949 950 case IPW_STATUS_CODE_DATA_802_3: 951 case IPW_STATUS_CODE_DATA_802_11: 952 ipw_data_intr(sc, status, sbd, sbuf); 953 break; 954 955 case IPW_STATUS_CODE_NOTIFICATION: 956 ipw_notification_intr(sc, sbuf); 957 break; 958 959 default: 960 printf("%s: unknown status code %u\n", 961 sc->sc_dev.dv_xname, letoh16(status->code)); 962 } 963 sbd->bd->flags = 0; 964 965 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 966 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 967 BUS_DMASYNC_PREWRITE); 968 } 969 970 /* tell the firmware what we have processed */ 971 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 972 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 973 } 974 975 void 976 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 977 { 978 struct ieee80211com *ic = &sc->sc_ic; 979 struct ipw_soft_hdr *shdr; 980 struct ipw_soft_buf *sbuf; 981 982 switch (sbd->type) { 983 case IPW_SBD_TYPE_COMMAND: 984 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 985 break; 986 987 case IPW_SBD_TYPE_HEADER: 988 shdr = sbd->priv; 989 bus_dmamap_unload(sc->sc_dmat, shdr->map); 990 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 991 break; 992 993 case IPW_SBD_TYPE_DATA: 994 sbuf = sbd->priv; 995 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 996 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 997 998 m_freem(sbuf->m); 999 1000 if (sbuf->ni != NULL) 1001 ieee80211_release_node(ic, sbuf->ni); 1002 1003 /* kill watchdog timer */ 1004 sc->sc_tx_timer = 0; 1005 break; 1006 } 1007 sbd->type = IPW_SBD_TYPE_NOASSOC; 1008 } 1009 1010 void 1011 ipw_tx_intr(struct ipw_softc *sc) 1012 { 1013 struct ifnet *ifp = &sc->sc_ic.ic_if; 1014 struct ipw_soft_bd *sbd; 1015 uint32_t r, i; 1016 1017 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1018 1019 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1020 sbd = &sc->stbd_list[i]; 1021 1022 ipw_release_sbd(sc, sbd); 1023 sc->txfree++; 1024 } 1025 1026 /* remember what the firmware has processed */ 1027 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1028 1029 /* call start() since some buffer descriptors have been released */ 1030 ifq_clr_oactive(&ifp->if_snd); 1031 (*ifp->if_start)(ifp); 1032 } 1033 1034 int 1035 ipw_intr(void *arg) 1036 { 1037 struct ipw_softc *sc = arg; 1038 struct ifnet *ifp = &sc->sc_ic.ic_if; 1039 uint32_t r; 1040 1041 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1042 return 0; 1043 1044 /* disable interrupts */ 1045 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1046 1047 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1048 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 1049 ipw_stop(ifp, 1); 1050 return 1; 1051 } 1052 1053 if (r & IPW_INTR_FW_INIT_DONE) 1054 wakeup(sc); 1055 1056 if (r & IPW_INTR_RX_TRANSFER) 1057 ipw_rx_intr(sc); 1058 1059 if (r & IPW_INTR_TX_TRANSFER) 1060 ipw_tx_intr(sc); 1061 1062 /* acknowledge interrupts */ 1063 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1064 1065 /* re-enable interrupts */ 1066 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1067 1068 return 1; 1069 } 1070 1071 int 1072 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1073 { 1074 struct ipw_soft_bd *sbd; 1075 int s, error; 1076 1077 s = splnet(); 1078 1079 sc->cmd.type = htole32(type); 1080 sc->cmd.subtype = htole32(0); 1081 sc->cmd.len = htole32(len); 1082 sc->cmd.seq = htole32(0); 1083 if (data != NULL) 1084 bcopy(data, sc->cmd.data, len); 1085 1086 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1087 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1088 if (error != 0) { 1089 printf("%s: can't map command DMA memory\n", 1090 sc->sc_dev.dv_xname); 1091 splx(s); 1092 return error; 1093 } 1094 1095 sbd = &sc->stbd_list[sc->txcur]; 1096 sbd->type = IPW_SBD_TYPE_COMMAND; 1097 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1098 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1099 sbd->bd->nfrag = 1; 1100 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1101 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1102 1103 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1104 BUS_DMASYNC_PREWRITE); 1105 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1106 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1107 BUS_DMASYNC_PREWRITE); 1108 1109 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1110 sc->txfree--; 1111 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1112 1113 DPRINTFN(2, ("sending command type=%u,len=%u\n", type, len)); 1114 1115 /* wait at most one second for command to complete */ 1116 error = tsleep(&sc->cmd, 0, "ipwcmd", hz); 1117 splx(s); 1118 1119 return error; 1120 } 1121 1122 /* ARGSUSED */ 1123 int 1124 ipw_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1125 int arg1, int arg2) 1126 { 1127 return EOPNOTSUPP; 1128 } 1129 1130 int 1131 ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1132 { 1133 struct ipw_softc *sc = ifp->if_softc; 1134 struct ieee80211com *ic = &sc->sc_ic; 1135 struct ieee80211_frame *wh; 1136 struct ieee80211_key *k; 1137 struct ipw_soft_bd *sbd; 1138 struct ipw_soft_hdr *shdr; 1139 struct ipw_soft_buf *sbuf; 1140 int error, i; 1141 1142 wh = mtod(m, struct ieee80211_frame *); 1143 1144 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1145 k = ieee80211_get_txkey(ic, wh, ni); 1146 1147 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1148 return ENOBUFS; 1149 1150 /* packet header may have moved, reset our local pointer */ 1151 wh = mtod(m, struct ieee80211_frame *); 1152 } 1153 1154 #if NBPFILTER > 0 1155 if (sc->sc_drvbpf != NULL) { 1156 struct mbuf mb; 1157 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1158 1159 tap->wt_flags = 0; 1160 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1161 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1162 1163 mb.m_data = (caddr_t)tap; 1164 mb.m_len = sc->sc_txtap_len; 1165 mb.m_next = m; 1166 mb.m_nextpkt = NULL; 1167 mb.m_type = 0; 1168 mb.m_flags = 0; 1169 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1170 } 1171 #endif 1172 1173 shdr = SLIST_FIRST(&sc->free_shdr); 1174 sbuf = SLIST_FIRST(&sc->free_sbuf); 1175 1176 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1177 shdr->hdr.subtype = htole32(0); 1178 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) ? 1 : 0; 1179 shdr->hdr.encrypt = 0; 1180 shdr->hdr.keyidx = 0; 1181 shdr->hdr.keysz = 0; 1182 shdr->hdr.fragmentsz = htole16(0); 1183 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1184 if (ic->ic_opmode == IEEE80211_M_STA) 1185 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1186 else 1187 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1188 1189 /* trim IEEE802.11 header */ 1190 m_adj(m, sizeof (struct ieee80211_frame)); 1191 1192 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1193 if (error != 0 && error != EFBIG) { 1194 printf("%s: can't map mbuf (error %d)\n", 1195 sc->sc_dev.dv_xname, error); 1196 m_freem(m); 1197 return error; 1198 } 1199 if (error != 0) { 1200 /* too many fragments, linearize */ 1201 if (m_defrag(m, M_DONTWAIT)) { 1202 m_freem(m); 1203 return ENOBUFS; 1204 } 1205 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1206 BUS_DMA_NOWAIT); 1207 if (error != 0) { 1208 printf("%s: can't map mbuf (error %d)\n", 1209 sc->sc_dev.dv_xname, error); 1210 m_freem(m); 1211 return error; 1212 } 1213 } 1214 1215 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1216 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1217 if (error != 0) { 1218 printf("%s: can't map header DMA memory (error %d)\n", 1219 sc->sc_dev.dv_xname, error); 1220 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1221 m_freem(m); 1222 return error; 1223 } 1224 1225 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1226 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1227 1228 sbd = &sc->stbd_list[sc->txcur]; 1229 sbd->type = IPW_SBD_TYPE_HEADER; 1230 sbd->priv = shdr; 1231 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1232 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1233 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1234 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1235 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1236 1237 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1238 sc->txcur * sizeof (struct ipw_bd), 1239 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1240 1241 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1242 sc->txfree--; 1243 1244 sbuf->m = m; 1245 sbuf->ni = ni; 1246 1247 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1248 sbd = &sc->stbd_list[sc->txcur]; 1249 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1250 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1251 sbd->bd->nfrag = 0; /* used only in first bd */ 1252 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1253 if (i == sbuf->map->dm_nsegs - 1) { 1254 sbd->type = IPW_SBD_TYPE_DATA; 1255 sbd->priv = sbuf; 1256 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1257 } else { 1258 sbd->type = IPW_SBD_TYPE_NOASSOC; 1259 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1260 } 1261 1262 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1263 sc->txcur * sizeof (struct ipw_bd), 1264 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1265 1266 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1267 sc->txfree--; 1268 } 1269 1270 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1271 BUS_DMASYNC_PREWRITE); 1272 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1273 BUS_DMASYNC_PREWRITE); 1274 1275 /* inform firmware about this new packet */ 1276 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1277 1278 return 0; 1279 } 1280 1281 void 1282 ipw_start(struct ifnet *ifp) 1283 { 1284 struct ipw_softc *sc = ifp->if_softc; 1285 struct ieee80211com *ic = &sc->sc_ic; 1286 struct ieee80211_node *ni; 1287 struct mbuf *m; 1288 1289 if (ic->ic_state != IEEE80211_S_RUN) 1290 return; 1291 1292 for (;;) { 1293 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1294 ifq_set_oactive(&ifp->if_snd); 1295 break; 1296 } 1297 1298 IFQ_DEQUEUE(&ifp->if_snd, m); 1299 if (m == NULL) 1300 break; 1301 1302 #if NBPFILTER > 0 1303 if (ifp->if_bpf != NULL) 1304 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1305 #endif 1306 1307 m = ieee80211_encap(ifp, m, &ni); 1308 if (m == NULL) 1309 continue; 1310 #if NBPFILTER > 0 1311 if (ic->ic_rawbpf != NULL) 1312 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1313 #endif 1314 if (ipw_tx_start(ifp, m, ni) != 0) { 1315 if (ni != NULL) 1316 ieee80211_release_node(ic, ni); 1317 ifp->if_oerrors++; 1318 break; 1319 } 1320 1321 /* start watchdog timer */ 1322 sc->sc_tx_timer = 5; 1323 ifp->if_timer = 1; 1324 } 1325 } 1326 1327 void 1328 ipw_watchdog(struct ifnet *ifp) 1329 { 1330 struct ipw_softc *sc = ifp->if_softc; 1331 1332 ifp->if_timer = 0; 1333 1334 if (sc->sc_tx_timer > 0) { 1335 if (--sc->sc_tx_timer == 0) { 1336 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1337 ipw_stop(ifp, 1); 1338 ifp->if_oerrors++; 1339 return; 1340 } 1341 ifp->if_timer = 1; 1342 } 1343 1344 ieee80211_watchdog(ifp); 1345 } 1346 1347 int 1348 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1349 { 1350 struct ipw_softc *sc = ifp->if_softc; 1351 int s, error = 0; 1352 1353 error = rw_enter(&sc->sc_rwlock, RW_WRITE | RW_INTR); 1354 if (error) 1355 return error; 1356 s = splnet(); 1357 1358 switch (cmd) { 1359 case SIOCSIFADDR: 1360 ifp->if_flags |= IFF_UP; 1361 /* FALLTHROUGH */ 1362 case SIOCSIFFLAGS: 1363 if (ifp->if_flags & IFF_UP) { 1364 if (!(ifp->if_flags & IFF_RUNNING)) 1365 ipw_init(ifp); 1366 } else { 1367 if (ifp->if_flags & IFF_RUNNING) 1368 ipw_stop(ifp, 1); 1369 } 1370 break; 1371 1372 case SIOCG80211TXPOWER: 1373 /* 1374 * If the hardware radio transmitter switch is off, report a 1375 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1376 * transmitter is killed. 1377 */ 1378 ((struct ieee80211_txpower *)data)->i_val = 1379 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1380 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1381 break; 1382 1383 default: 1384 error = ieee80211_ioctl(ifp, cmd, data); 1385 } 1386 1387 if (error == ENETRESET) { 1388 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1389 (IFF_UP | IFF_RUNNING)) 1390 ipw_init(ifp); 1391 error = 0; 1392 } 1393 1394 splx(s); 1395 rw_exit_write(&sc->sc_rwlock); 1396 return error; 1397 } 1398 1399 uint32_t 1400 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1401 { 1402 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1403 } 1404 1405 void 1406 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1407 { 1408 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1409 } 1410 1411 int 1412 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1413 { 1414 uint32_t addr, info; 1415 uint16_t count, size; 1416 uint32_t total; 1417 1418 /* addr[4] + count[2] + size[2] */ 1419 addr = MEM_READ_4(sc, sc->table2_base + off); 1420 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1421 1422 count = info >> 16; 1423 size = info & 0xffff; 1424 total = count * size; 1425 1426 if (total > *len) { 1427 *len = total; 1428 return EINVAL; 1429 } 1430 *len = total; 1431 ipw_read_mem_1(sc, addr, buf, total); 1432 1433 return 0; 1434 } 1435 1436 void 1437 ipw_stop_master(struct ipw_softc *sc) 1438 { 1439 uint32_t tmp; 1440 int ntries; 1441 1442 /* disable interrupts */ 1443 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1444 1445 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1446 for (ntries = 0; ntries < 50; ntries++) { 1447 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1448 break; 1449 DELAY(10); 1450 } 1451 if (ntries == 50) 1452 printf("%s: timeout waiting for master\n", 1453 sc->sc_dev.dv_xname); 1454 1455 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1456 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1457 } 1458 1459 int 1460 ipw_reset(struct ipw_softc *sc) 1461 { 1462 uint32_t tmp; 1463 int ntries; 1464 1465 ipw_stop_master(sc); 1466 1467 /* move adapter to D0 state */ 1468 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1469 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1470 1471 /* wait for clock stabilization */ 1472 for (ntries = 0; ntries < 1000; ntries++) { 1473 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1474 break; 1475 DELAY(200); 1476 } 1477 if (ntries == 1000) 1478 return EIO; 1479 1480 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1481 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1482 1483 DELAY(10); 1484 1485 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1486 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1487 1488 return 0; 1489 } 1490 1491 int 1492 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1493 { 1494 int ntries; 1495 1496 /* voodoo from the Intel Linux driver */ 1497 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1498 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1499 1500 MEM_WRITE_2(sc, 0x220000, 0x0703); 1501 MEM_WRITE_2(sc, 0x220000, 0x0707); 1502 1503 MEM_WRITE_1(sc, 0x210014, 0x72); 1504 MEM_WRITE_1(sc, 0x210014, 0x72); 1505 1506 MEM_WRITE_1(sc, 0x210000, 0x40); 1507 MEM_WRITE_1(sc, 0x210000, 0x00); 1508 MEM_WRITE_1(sc, 0x210000, 0x40); 1509 1510 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1511 1512 MEM_WRITE_1(sc, 0x210000, 0x00); 1513 MEM_WRITE_1(sc, 0x210000, 0x00); 1514 MEM_WRITE_1(sc, 0x210000, 0x80); 1515 1516 MEM_WRITE_2(sc, 0x220000, 0x0703); 1517 MEM_WRITE_2(sc, 0x220000, 0x0707); 1518 1519 MEM_WRITE_1(sc, 0x210014, 0x72); 1520 MEM_WRITE_1(sc, 0x210014, 0x72); 1521 1522 MEM_WRITE_1(sc, 0x210000, 0x00); 1523 MEM_WRITE_1(sc, 0x210000, 0x80); 1524 1525 for (ntries = 0; ntries < 100; ntries++) { 1526 if (MEM_READ_1(sc, 0x210000) & 1) 1527 break; 1528 DELAY(1000); 1529 } 1530 if (ntries == 100) { 1531 printf("%s: timeout waiting for ucode to initialize\n", 1532 sc->sc_dev.dv_xname); 1533 return EIO; 1534 } 1535 1536 MEM_WRITE_4(sc, 0x3000e0, 0); 1537 1538 return 0; 1539 } 1540 1541 /* set of macros to handle unaligned little endian data in firmware image */ 1542 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1543 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1544 int 1545 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1546 { 1547 u_char *p, *end; 1548 uint32_t tmp, dst; 1549 uint16_t len; 1550 int error; 1551 1552 p = fw; 1553 end = fw + size; 1554 while (p < end) { 1555 if (p + 6 > end) 1556 return EINVAL; 1557 1558 dst = GETLE32(p); p += 4; 1559 len = GETLE16(p); p += 2; 1560 1561 if (p + len > end) 1562 return EINVAL; 1563 1564 ipw_write_mem_1(sc, dst, p, len); 1565 p += len; 1566 } 1567 1568 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1569 IPW_IO_LED_OFF); 1570 1571 /* allow interrupts so we know when the firmware is inited */ 1572 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1573 1574 /* tell the adapter to initialize the firmware */ 1575 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1576 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1577 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1578 1579 /* wait at most one second for firmware initialization to complete */ 1580 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1581 printf("%s: timeout waiting for firmware initialization to " 1582 "complete\n", sc->sc_dev.dv_xname); 1583 return error; 1584 } 1585 1586 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1587 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1588 IPW_IO_GPIO3_MASK); 1589 1590 return 0; 1591 } 1592 1593 int 1594 ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1595 { 1596 const struct ipw_firmware_hdr *hdr; 1597 const char *name; 1598 int error; 1599 1600 switch (sc->sc_ic.ic_opmode) { 1601 case IEEE80211_M_STA: 1602 name = "ipw-bss"; 1603 break; 1604 #ifndef IEEE80211_STA_ONLY 1605 case IEEE80211_M_IBSS: 1606 name = "ipw-ibss"; 1607 break; 1608 #endif 1609 case IEEE80211_M_MONITOR: 1610 name = "ipw-monitor"; 1611 break; 1612 default: 1613 /* should not get there */ 1614 return ENODEV; 1615 } 1616 if ((error = loadfirmware(name, &fw->data, &fw->size)) != 0) 1617 return error; 1618 1619 if (fw->size < sizeof (*hdr)) { 1620 error = EINVAL; 1621 goto fail; 1622 } 1623 hdr = (const struct ipw_firmware_hdr *)fw->data; 1624 fw->main_size = letoh32(hdr->main_size); 1625 fw->ucode_size = letoh32(hdr->ucode_size); 1626 1627 if (fw->size < sizeof (*hdr) + fw->main_size + fw->ucode_size) { 1628 error = EINVAL; 1629 goto fail; 1630 } 1631 fw->main = fw->data + sizeof (*hdr); 1632 fw->ucode = fw->main + fw->main_size; 1633 1634 return 0; 1635 1636 fail: free(fw->data, M_DEVBUF, fw->size); 1637 return error; 1638 } 1639 1640 void 1641 ipw_scan(void *arg1) 1642 { 1643 struct ipw_softc *sc = arg1; 1644 struct ifnet *ifp = &sc->sc_ic.ic_if; 1645 struct ipw_scan_options scan; 1646 uint8_t ssid[IEEE80211_NWID_LEN]; 1647 int error; 1648 1649 /* 1650 * Firmware has a bug and does not honour the ``do not associate 1651 * after scan'' bit in the scan command. To prevent the firmware 1652 * from associating after the scan, we set the ESSID to something 1653 * unlikely to be used by a real AP. 1654 * XXX would setting the desired BSSID to a multicast address work? 1655 */ 1656 memset(ssid, '\r', sizeof ssid); 1657 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ssid, sizeof ssid); 1658 if (error != 0) 1659 goto fail; 1660 1661 /* no mandatory BSSID */ 1662 DPRINTF(("Setting mandatory BSSID to null\n")); 1663 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1664 if (error != 0) 1665 goto fail; 1666 1667 scan.flags = htole32(IPW_SCAN_DO_NOT_ASSOCIATE | IPW_SCAN_MIXED_CELL); 1668 scan.channels = htole32(0x3fff); /* scan channels 1-14 */ 1669 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1670 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1671 if (error != 0) 1672 goto fail; 1673 1674 /* start scanning */ 1675 DPRINTF(("Enabling adapter\n")); 1676 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1677 if (error != 0) 1678 goto fail; 1679 1680 return; 1681 fail: 1682 printf("%s: scan request failed (error=%d)\n", sc->sc_dev.dv_xname, 1683 error); 1684 ieee80211_end_scan(ifp); 1685 } 1686 1687 void 1688 ipw_auth_and_assoc(void *arg1) 1689 { 1690 struct ipw_softc *sc = arg1; 1691 struct ieee80211com *ic = &sc->sc_ic; 1692 struct ieee80211_node *ni = ic->ic_bss; 1693 struct ipw_scan_options scan; 1694 struct ipw_security security; 1695 struct ipw_assoc_req assoc; 1696 uint32_t data; 1697 uint8_t chan; 1698 int s, error; 1699 1700 DPRINTF(("Disabling adapter\n")); 1701 error = ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1702 if (error != 0) 1703 goto fail; 1704 #if 1 1705 /* wait at most one second for card to be disabled */ 1706 s = splnet(); 1707 error = tsleep(sc, 0, "ipwdis", hz); 1708 splx(s); 1709 if (error != 0) { 1710 printf("%s: timeout waiting for disabled state\n", 1711 sc->sc_dev.dv_xname); 1712 goto fail; 1713 } 1714 #else 1715 /* Intel's Linux driver polls for the DISABLED state instead.. */ 1716 for (ntries = 0; ntries < 1000; ntries++) { 1717 if (ipw_read_table1(sc, IPW_INFO_CARD_DISABLED) == 1) 1718 break; 1719 DELAY(10); 1720 } 1721 if (ntries == 1000) { 1722 printf("%s: timeout waiting for disabled state\n", 1723 sc->sc_dev.dv_xname); 1724 goto fail; 1725 } 1726 #endif 1727 1728 bzero(&security, sizeof security); 1729 security.authmode = IPW_AUTH_OPEN; 1730 security.ciphers = htole32(IPW_CIPHER_NONE); 1731 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1732 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1733 sizeof security); 1734 if (error != 0) 1735 goto fail; 1736 1737 #ifdef IPW_DEBUG 1738 if (ipw_debug > 0) { 1739 printf("Setting ESSID to "); 1740 ieee80211_print_essid(ni->ni_essid, ni->ni_esslen); 1741 printf("\n"); 1742 } 1743 #endif 1744 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ni->ni_essid, ni->ni_esslen); 1745 if (error != 0) 1746 goto fail; 1747 1748 DPRINTF(("Setting BSSID to %s\n", ether_sprintf(ni->ni_bssid))); 1749 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, ni->ni_bssid, 1750 IEEE80211_ADDR_LEN); 1751 if (error != 0) 1752 goto fail; 1753 1754 data = htole32((ic->ic_flags & (IEEE80211_F_WEPON | 1755 IEEE80211_F_RSNON)) ? IPW_PRIVACYON : 0); 1756 DPRINTF(("Setting privacy flags to 0x%x\n", letoh32(data))); 1757 error = ipw_cmd(sc, IPW_CMD_SET_PRIVACY_FLAGS, &data, sizeof data); 1758 if (error != 0) 1759 goto fail; 1760 1761 /* let firmware set the capinfo, lintval, and bssid fixed fields */ 1762 bzero(&assoc, sizeof assoc); 1763 if (ic->ic_flags & IEEE80211_F_RSNON) { 1764 uint8_t *frm = assoc.optie; 1765 1766 /* tell firmware to add a WPA or RSN IE in (Re)Assoc req */ 1767 if (ni->ni_rsnprotos & IEEE80211_PROTO_RSN) 1768 frm = ieee80211_add_rsn(frm, ic, ni); 1769 else if (ni->ni_rsnprotos & IEEE80211_PROTO_WPA) 1770 frm = ieee80211_add_wpa(frm, ic, ni); 1771 assoc.optie_len = htole32(frm - assoc.optie); 1772 } 1773 DPRINTF(("Preparing assocation request (optional IE length=%d)\n", 1774 letoh32(assoc.optie_len))); 1775 error = ipw_cmd(sc, IPW_CMD_SET_ASSOC_REQ, &assoc, sizeof assoc); 1776 if (error != 0) 1777 goto fail; 1778 1779 scan.flags = htole32(IPW_SCAN_MIXED_CELL); 1780 chan = ieee80211_chan2ieee(ic, ni->ni_chan); 1781 scan.channels = htole32(1 << (chan - 1)); 1782 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1783 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1784 if (error != 0) 1785 goto fail; 1786 1787 /* trigger scan+association */ 1788 DPRINTF(("Enabling adapter\n")); 1789 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1790 if (error != 0) 1791 goto fail; 1792 1793 return; 1794 fail: 1795 printf("%s: association failed (error=%d)\n", sc->sc_dev.dv_xname, 1796 error); 1797 ieee80211_begin_scan(&ic->ic_if); 1798 } 1799 1800 int 1801 ipw_config(struct ipw_softc *sc) 1802 { 1803 struct ieee80211com *ic = &sc->sc_ic; 1804 struct ifnet *ifp = &ic->ic_if; 1805 struct ipw_configuration config; 1806 uint32_t data; 1807 int error; 1808 1809 switch (ic->ic_opmode) { 1810 case IEEE80211_M_STA: 1811 data = htole32(IPW_MODE_BSS); 1812 break; 1813 #ifndef IEEE80211_STA_ONLY 1814 case IEEE80211_M_IBSS: 1815 data = htole32(IPW_MODE_IBSS); 1816 break; 1817 #endif 1818 case IEEE80211_M_MONITOR: 1819 data = htole32(IPW_MODE_MONITOR); 1820 break; 1821 default: 1822 /* should not get there */ 1823 return ENODEV; 1824 } 1825 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1826 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1827 if (error != 0) 1828 return error; 1829 1830 if ( 1831 #ifndef IEEE80211_STA_ONLY 1832 ic->ic_opmode == IEEE80211_M_IBSS || 1833 #endif 1834 ic->ic_opmode == IEEE80211_M_MONITOR) { 1835 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1836 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1837 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1838 if (error != 0) 1839 return error; 1840 } 1841 1842 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1843 DPRINTF(("Enabling adapter\n")); 1844 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1845 } 1846 1847 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1848 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1849 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1850 IEEE80211_ADDR_LEN); 1851 if (error != 0) 1852 return error; 1853 1854 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1855 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1X_ENABLE); 1856 #ifndef IEEE80211_STA_ONLY 1857 if (ic->ic_opmode == IEEE80211_M_IBSS) 1858 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1859 #endif 1860 if (ifp->if_flags & IFF_PROMISC) 1861 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1862 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1863 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1864 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1865 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1866 if (error != 0) 1867 return error; 1868 1869 data = htole32(ic->ic_rtsthreshold); 1870 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1871 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1872 if (error != 0) 1873 return error; 1874 1875 data = htole32(ic->ic_fragthreshold); 1876 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1877 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1878 if (error != 0) 1879 return error; 1880 1881 data = htole32(0x3); /* 1, 2 */ 1882 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1883 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1884 if (error != 0) 1885 return error; 1886 1887 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1888 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1889 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1890 if (error != 0) 1891 return error; 1892 1893 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1894 DPRINTF(("Setting MSDU tx rates to 0x%x\n", letoh32(data))); 1895 error = ipw_cmd(sc, IPW_CMD_SET_MSDU_TX_RATES, &data, sizeof data); 1896 if (error != 0) 1897 return error; 1898 1899 data = htole32(IPW_POWER_MODE_CAM); 1900 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1901 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1902 if (error != 0) 1903 return error; 1904 1905 #ifndef IEEE80211_STA_ONLY 1906 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1907 data = htole32(32); /* default value */ 1908 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1909 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1910 sizeof data); 1911 if (error != 0) 1912 return error; 1913 1914 data = htole32(ic->ic_lintval); 1915 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1916 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1917 sizeof data); 1918 if (error != 0) 1919 return error; 1920 } 1921 #endif 1922 return 0; 1923 } 1924 1925 int 1926 ipw_init(struct ifnet *ifp) 1927 { 1928 struct ipw_softc *sc = ifp->if_softc; 1929 struct ieee80211com *ic = &sc->sc_ic; 1930 struct ipw_firmware fw; 1931 int error; 1932 1933 ipw_stop(ifp, 0); 1934 1935 if ((error = ipw_reset(sc)) != 0) { 1936 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1937 goto fail1; 1938 } 1939 1940 if ((error = ipw_read_firmware(sc, &fw)) != 0) { 1941 printf("%s: error %d, could not read firmware\n", 1942 sc->sc_dev.dv_xname, error); 1943 goto fail1; 1944 } 1945 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 1946 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 1947 goto fail2; 1948 } 1949 1950 ipw_stop_master(sc); 1951 1952 /* 1953 * Setup tx, rx and status rings. 1954 */ 1955 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1956 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1957 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1958 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1959 sc->txold = IPW_NTBD - 1; /* latest bd index ack by firmware */ 1960 sc->txcur = 0; /* bd index to write to */ 1961 sc->txfree = IPW_NTBD - 2; 1962 1963 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1964 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1965 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1966 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1967 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1968 1969 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1970 sc->status_map->dm_segs[0].ds_addr); 1971 1972 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 1973 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 1974 goto fail2; 1975 } 1976 free(fw.data, M_DEVBUF, fw.size); 1977 fw.data = NULL; 1978 1979 /* retrieve information tables base addresses */ 1980 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1981 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1982 1983 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1984 1985 if ((error = ipw_config(sc)) != 0) { 1986 printf("%s: device configuration failed\n", 1987 sc->sc_dev.dv_xname); 1988 goto fail1; 1989 } 1990 1991 ifq_clr_oactive(&ifp->if_snd); 1992 ifp->if_flags |= IFF_RUNNING; 1993 1994 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1995 ieee80211_begin_scan(ifp); 1996 else 1997 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1998 1999 return 0; 2000 2001 fail2: free(fw.data, M_DEVBUF, fw.size); 2002 fw.data = NULL; 2003 fail1: ipw_stop(ifp, 0); 2004 return error; 2005 } 2006 2007 void 2008 ipw_stop(struct ifnet *ifp, int disable) 2009 { 2010 struct ipw_softc *sc = ifp->if_softc; 2011 struct ieee80211com *ic = &sc->sc_ic; 2012 int i; 2013 2014 ipw_stop_master(sc); 2015 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2016 2017 ifp->if_timer = 0; 2018 ifp->if_flags &= ~IFF_RUNNING; 2019 ifq_clr_oactive(&ifp->if_snd); 2020 2021 /* 2022 * Release tx buffers. 2023 */ 2024 for (i = 0; i < IPW_NTBD; i++) 2025 ipw_release_sbd(sc, &sc->stbd_list[i]); 2026 2027 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2028 } 2029 2030 void 2031 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2032 bus_size_t count) 2033 { 2034 for (; count > 0; offset++, datap++, count--) { 2035 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2036 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2037 } 2038 } 2039 2040 void 2041 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2042 bus_size_t count) 2043 { 2044 for (; count > 0; offset++, datap++, count--) { 2045 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2046 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2047 } 2048 } 2049 2050 struct cfdriver ipw_cd = { 2051 NULL, "ipw", DV_IFNET 2052 }; 2053