1 /* $OpenBSD: if_ipw.c,v 1.133 2023/03/08 04:43:08 guenther Exp $ */ 2 3 /*- 4 * Copyright (c) 2004-2008 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Intel PRO/Wireless 2100 802.11 network adapters. 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/task.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/rwlock.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/conf.h> 35 #include <sys/device.h> 36 #include <sys/endian.h> 37 38 #include <machine/bus.h> 39 #include <machine/intr.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcidevs.h> 44 45 #if NBPFILTER > 0 46 #include <net/bpf.h> 47 #endif 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include <net80211/ieee80211_var.h> 56 #include <net80211/ieee80211_radiotap.h> 57 58 #include <dev/pci/if_ipwreg.h> 59 #include <dev/pci/if_ipwvar.h> 60 61 int ipw_match(struct device *, void *, void *); 62 void ipw_attach(struct device *, struct device *, void *); 63 int ipw_activate(struct device *, int); 64 void ipw_wakeup(struct ipw_softc *); 65 int ipw_dma_alloc(struct ipw_softc *); 66 void ipw_release(struct ipw_softc *); 67 int ipw_media_change(struct ifnet *); 68 void ipw_media_status(struct ifnet *, struct ifmediareq *); 69 int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 70 uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 71 void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 72 void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 73 void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 74 struct ipw_soft_bd *, struct ipw_soft_buf *, 75 struct mbuf_list *); 76 void ipw_notification_intr(struct ipw_softc *, 77 struct ipw_soft_buf *); 78 void ipw_rx_intr(struct ipw_softc *); 79 void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 80 void ipw_tx_intr(struct ipw_softc *); 81 int ipw_intr(void *); 82 int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 83 int ipw_send_mgmt(struct ieee80211com *, struct ieee80211_node *, 84 int, int, int); 85 int ipw_tx_start(struct ifnet *, struct mbuf *, 86 struct ieee80211_node *); 87 void ipw_start(struct ifnet *); 88 void ipw_watchdog(struct ifnet *); 89 int ipw_ioctl(struct ifnet *, u_long, caddr_t); 90 uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 91 void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 92 int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 93 uint32_t *); 94 void ipw_stop_master(struct ipw_softc *); 95 int ipw_reset(struct ipw_softc *); 96 int ipw_load_ucode(struct ipw_softc *, u_char *, int); 97 int ipw_load_firmware(struct ipw_softc *, u_char *, int); 98 int ipw_read_firmware(struct ipw_softc *, struct ipw_firmware *); 99 void ipw_scan(void *); 100 void ipw_auth_and_assoc(void *); 101 int ipw_config(struct ipw_softc *); 102 int ipw_init(struct ifnet *); 103 void ipw_stop(struct ifnet *, int); 104 void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 105 bus_size_t); 106 void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 107 bus_size_t); 108 109 static __inline uint8_t 110 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 111 { 112 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 113 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 114 } 115 116 static __inline uint32_t 117 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 118 { 119 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 120 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 121 } 122 123 #ifdef IPW_DEBUG 124 #define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 125 #define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 126 int ipw_debug = 0; 127 #else 128 #define DPRINTF(x) 129 #define DPRINTFN(n, x) 130 #endif 131 132 const struct cfattach ipw_ca = { 133 sizeof (struct ipw_softc), ipw_match, ipw_attach, NULL, 134 ipw_activate 135 }; 136 137 int 138 ipw_match(struct device *parent, void *match, void *aux) 139 { 140 struct pci_attach_args *pa = aux; 141 142 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 143 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 144 return 1; 145 146 return 0; 147 } 148 149 /* Base Address Register */ 150 #define IPW_PCI_BAR0 0x10 151 152 void 153 ipw_attach(struct device *parent, struct device *self, void *aux) 154 { 155 struct ipw_softc *sc = (struct ipw_softc *)self; 156 struct ieee80211com *ic = &sc->sc_ic; 157 struct ifnet *ifp = &ic->ic_if; 158 struct pci_attach_args *pa = aux; 159 const char *intrstr; 160 bus_space_tag_t memt; 161 bus_space_handle_t memh; 162 bus_addr_t base; 163 pci_intr_handle_t ih; 164 pcireg_t data; 165 uint16_t val; 166 int error, i; 167 168 sc->sc_pct = pa->pa_pc; 169 sc->sc_pcitag = pa->pa_tag, 170 171 /* clear device specific PCI configuration register 0x41 */ 172 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 173 data &= ~0x0000ff00; 174 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 175 176 /* map the register window */ 177 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 178 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz, 0); 179 if (error != 0) { 180 printf(": can't map mem space\n"); 181 return; 182 } 183 184 sc->sc_st = memt; 185 sc->sc_sh = memh; 186 sc->sc_dmat = pa->pa_dmat; 187 188 /* disable interrupts */ 189 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 190 191 if (pci_intr_map(pa, &ih) != 0) { 192 printf(": can't map interrupt\n"); 193 return; 194 } 195 196 intrstr = pci_intr_string(sc->sc_pct, ih); 197 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc, 198 sc->sc_dev.dv_xname); 199 if (sc->sc_ih == NULL) { 200 printf(": can't establish interrupt"); 201 if (intrstr != NULL) 202 printf(" at %s", intrstr); 203 printf("\n"); 204 return; 205 } 206 printf(": %s", intrstr); 207 208 rw_init(&sc->sc_rwlock, "ipwlock"); 209 task_set(&sc->sc_scantask, ipw_scan, sc); 210 task_set(&sc->sc_authandassoctask, ipw_auth_and_assoc, sc); 211 212 if (ipw_reset(sc) != 0) { 213 printf(": could not reset adapter\n"); 214 return; 215 } 216 217 if (ipw_dma_alloc(sc) != 0) { 218 printf(": failed to allocate DMA resources\n"); 219 return; 220 } 221 222 ic->ic_phytype = IEEE80211_T_DS; 223 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 224 ic->ic_state = IEEE80211_S_INIT; 225 226 /* set device capabilities */ 227 ic->ic_caps = 228 #ifndef IEEE80211_STA_ONLY 229 IEEE80211_C_IBSS | /* IBSS mode supported */ 230 #endif 231 IEEE80211_C_MONITOR | /* monitor mode supported */ 232 IEEE80211_C_TXPMGT | /* tx power management */ 233 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 234 IEEE80211_C_WEP | /* s/w WEP */ 235 IEEE80211_C_RSN | /* WPA/RSN */ 236 IEEE80211_C_SCANALL; /* h/w scanning */ 237 238 /* read MAC address from EEPROM */ 239 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 240 ic->ic_myaddr[0] = val >> 8; 241 ic->ic_myaddr[1] = val & 0xff; 242 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 243 ic->ic_myaddr[2] = val >> 8; 244 ic->ic_myaddr[3] = val & 0xff; 245 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 246 ic->ic_myaddr[4] = val >> 8; 247 ic->ic_myaddr[5] = val & 0xff; 248 249 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 250 251 /* set supported .11b rates */ 252 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 253 254 /* set supported .11b channels (1 through 14) */ 255 for (i = 1; i <= 14; i++) { 256 ic->ic_channels[i].ic_freq = 257 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 258 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 259 } 260 261 /* IBSS channel undefined for now */ 262 ic->ic_ibss_chan = &ic->ic_channels[0]; 263 264 ifp->if_softc = sc; 265 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 266 ifp->if_ioctl = ipw_ioctl; 267 ifp->if_start = ipw_start; 268 ifp->if_watchdog = ipw_watchdog; 269 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 270 271 if_attach(ifp); 272 ieee80211_ifattach(ifp); 273 /* override state transition machine */ 274 sc->sc_newstate = ic->ic_newstate; 275 ic->ic_newstate = ipw_newstate; 276 ic->ic_send_mgmt = ipw_send_mgmt; 277 ieee80211_media_init(ifp, ipw_media_change, ipw_media_status); 278 279 #if NBPFILTER > 0 280 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 281 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 282 283 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 284 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 285 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 286 287 sc->sc_txtap_len = sizeof sc->sc_txtapu; 288 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 289 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 290 #endif 291 } 292 293 int 294 ipw_activate(struct device *self, int act) 295 { 296 struct ipw_softc *sc = (struct ipw_softc *)self; 297 struct ifnet *ifp = &sc->sc_ic.ic_if; 298 299 switch (act) { 300 case DVACT_SUSPEND: 301 if (ifp->if_flags & IFF_RUNNING) 302 ipw_stop(ifp, 0); 303 break; 304 case DVACT_WAKEUP: 305 ipw_wakeup(sc); 306 break; 307 } 308 309 return 0; 310 } 311 312 void 313 ipw_wakeup(struct ipw_softc *sc) 314 { 315 struct ifnet *ifp = &sc->sc_ic.ic_if; 316 pcireg_t data; 317 int s; 318 319 /* clear device specific PCI configuration register 0x41 */ 320 data = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 321 data &= ~0x0000ff00; 322 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, data); 323 324 rw_enter_write(&sc->sc_rwlock); 325 s = splnet(); 326 327 if (ifp->if_flags & IFF_UP) 328 ipw_init(ifp); 329 330 splx(s); 331 rw_exit_write(&sc->sc_rwlock); 332 } 333 334 int 335 ipw_dma_alloc(struct ipw_softc *sc) 336 { 337 struct ipw_soft_bd *sbd; 338 struct ipw_soft_hdr *shdr; 339 struct ipw_soft_buf *sbuf; 340 int i, nsegs, error; 341 342 /* 343 * Allocate and map tx ring. 344 */ 345 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 346 BUS_DMA_NOWAIT, &sc->tbd_map); 347 if (error != 0) { 348 printf("%s: could not create tx ring DMA map\n", 349 sc->sc_dev.dv_xname); 350 goto fail; 351 } 352 353 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 354 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 355 if (error != 0) { 356 printf("%s: could not allocate tx ring DMA memory\n", 357 sc->sc_dev.dv_xname); 358 goto fail; 359 } 360 361 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 362 (caddr_t *)&sc->tbd_list, BUS_DMA_NOWAIT); 363 if (error != 0) { 364 printf("%s: can't map tx ring DMA memory\n", 365 sc->sc_dev.dv_xname); 366 goto fail; 367 } 368 369 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 370 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 371 if (error != 0) { 372 printf("%s: could not load tx ring DMA map\n", 373 sc->sc_dev.dv_xname); 374 goto fail; 375 } 376 377 /* 378 * Allocate and map rx ring. 379 */ 380 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 381 BUS_DMA_NOWAIT, &sc->rbd_map); 382 if (error != 0) { 383 printf("%s: could not create rx ring DMA map\n", 384 sc->sc_dev.dv_xname); 385 goto fail; 386 } 387 388 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 389 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 390 if (error != 0) { 391 printf("%s: could not allocate rx ring DMA memory\n", 392 sc->sc_dev.dv_xname); 393 goto fail; 394 } 395 396 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 397 (caddr_t *)&sc->rbd_list, BUS_DMA_NOWAIT); 398 if (error != 0) { 399 printf("%s: can't map rx ring DMA memory\n", 400 sc->sc_dev.dv_xname); 401 goto fail; 402 } 403 404 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 405 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 406 if (error != 0) { 407 printf("%s: could not load tx ring DMA map\n", 408 sc->sc_dev.dv_xname); 409 goto fail; 410 } 411 412 /* 413 * Allocate and map status ring. 414 */ 415 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 416 0, BUS_DMA_NOWAIT, &sc->status_map); 417 if (error != 0) { 418 printf("%s: could not create status ring DMA map\n", 419 sc->sc_dev.dv_xname); 420 goto fail; 421 } 422 423 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 424 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 425 if (error != 0) { 426 printf("%s: could not allocate status ring DMA memory\n", 427 sc->sc_dev.dv_xname); 428 goto fail; 429 } 430 431 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 432 IPW_STATUS_SZ, (caddr_t *)&sc->status_list, BUS_DMA_NOWAIT); 433 if (error != 0) { 434 printf("%s: can't map status ring DMA memory\n", 435 sc->sc_dev.dv_xname); 436 goto fail; 437 } 438 439 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 440 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 441 if (error != 0) { 442 printf("%s: could not load status ring DMA map\n", 443 sc->sc_dev.dv_xname); 444 goto fail; 445 } 446 447 /* 448 * Allocate command DMA map. 449 */ 450 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 1, 451 sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 452 if (error != 0) { 453 printf("%s: could not create command DMA map\n", 454 sc->sc_dev.dv_xname); 455 goto fail; 456 } 457 458 /* 459 * Allocate headers DMA maps. 460 */ 461 SLIST_INIT(&sc->free_shdr); 462 for (i = 0; i < IPW_NDATA; i++) { 463 shdr = &sc->shdr_list[i]; 464 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_hdr), 465 1, sizeof (struct ipw_hdr), 0, BUS_DMA_NOWAIT, &shdr->map); 466 if (error != 0) { 467 printf("%s: could not create header DMA map\n", 468 sc->sc_dev.dv_xname); 469 goto fail; 470 } 471 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 472 } 473 474 /* 475 * Allocate tx buffers DMA maps. 476 */ 477 SLIST_INIT(&sc->free_sbuf); 478 for (i = 0; i < IPW_NDATA; i++) { 479 sbuf = &sc->tx_sbuf_list[i]; 480 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, IPW_MAX_NSEG, 481 MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 482 if (error != 0) { 483 printf("%s: could not create tx DMA map\n", 484 sc->sc_dev.dv_xname); 485 goto fail; 486 } 487 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 488 } 489 490 /* 491 * Initialize tx ring. 492 */ 493 for (i = 0; i < IPW_NTBD; i++) { 494 sbd = &sc->stbd_list[i]; 495 sbd->bd = &sc->tbd_list[i]; 496 sbd->type = IPW_SBD_TYPE_NOASSOC; 497 } 498 499 /* 500 * Pre-allocate rx buffers and DMA maps. 501 */ 502 for (i = 0; i < IPW_NRBD; i++) { 503 sbd = &sc->srbd_list[i]; 504 sbuf = &sc->rx_sbuf_list[i]; 505 sbd->bd = &sc->rbd_list[i]; 506 507 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 508 if (sbuf->m == NULL) { 509 printf("%s: could not allocate rx mbuf\n", 510 sc->sc_dev.dv_xname); 511 error = ENOMEM; 512 goto fail; 513 } 514 MCLGET(sbuf->m, M_DONTWAIT); 515 if (!(sbuf->m->m_flags & M_EXT)) { 516 m_freem(sbuf->m); 517 printf("%s: could not allocate rx mbuf cluster\n", 518 sc->sc_dev.dv_xname); 519 error = ENOMEM; 520 goto fail; 521 } 522 523 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 524 0, BUS_DMA_NOWAIT, &sbuf->map); 525 if (error != 0) { 526 printf("%s: could not create rx DMA map\n", 527 sc->sc_dev.dv_xname); 528 goto fail; 529 } 530 531 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 532 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 533 if (error != 0) { 534 printf("%s: can't map rx DMA memory\n", 535 sc->sc_dev.dv_xname); 536 goto fail; 537 } 538 539 sbd->type = IPW_SBD_TYPE_DATA; 540 sbd->priv = sbuf; 541 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 542 sbd->bd->len = htole32(MCLBYTES); 543 } 544 545 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 546 BUS_DMASYNC_PREWRITE); 547 548 return 0; 549 550 fail: ipw_release(sc); 551 return error; 552 } 553 554 void 555 ipw_release(struct ipw_softc *sc) 556 { 557 struct ipw_soft_buf *sbuf; 558 int i; 559 560 if (sc->tbd_map != NULL) { 561 if (sc->tbd_list != NULL) { 562 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 563 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->tbd_list, 564 IPW_TBD_SZ); 565 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 566 } 567 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 568 } 569 570 if (sc->rbd_map != NULL) { 571 if (sc->rbd_list != NULL) { 572 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 573 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rbd_list, 574 IPW_RBD_SZ); 575 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 576 } 577 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 578 } 579 580 if (sc->status_map != NULL) { 581 if (sc->status_list != NULL) { 582 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 583 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->status_list, 584 IPW_RBD_SZ); 585 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 586 } 587 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 588 } 589 590 if (sc->cmd_map != NULL) 591 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 592 593 for (i = 0; i < IPW_NDATA; i++) 594 bus_dmamap_destroy(sc->sc_dmat, sc->shdr_list[i].map); 595 596 for (i = 0; i < IPW_NDATA; i++) 597 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 598 599 for (i = 0; i < IPW_NRBD; i++) { 600 sbuf = &sc->rx_sbuf_list[i]; 601 if (sbuf->map != NULL) { 602 if (sbuf->m != NULL) { 603 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 604 m_freem(sbuf->m); 605 } 606 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 607 } 608 } 609 610 task_del(systq, &sc->sc_scantask); 611 task_del(systq, &sc->sc_authandassoctask); 612 } 613 614 int 615 ipw_media_change(struct ifnet *ifp) 616 { 617 int error; 618 619 error = ieee80211_media_change(ifp); 620 if (error != ENETRESET) 621 return error; 622 623 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 624 ipw_init(ifp); 625 626 return 0; 627 } 628 629 void 630 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 631 { 632 struct ipw_softc *sc = ifp->if_softc; 633 struct ieee80211com *ic = &sc->sc_ic; 634 static const struct { 635 uint32_t val; 636 int rate; 637 } rates[] = { 638 { IPW_RATE_DS1, 2 }, 639 { IPW_RATE_DS2, 4 }, 640 { IPW_RATE_DS5, 11 }, 641 { IPW_RATE_DS11, 22 }, 642 }; 643 uint32_t val; 644 int rate, i; 645 646 imr->ifm_status = IFM_AVALID; 647 imr->ifm_active = IFM_IEEE80211; 648 if (ic->ic_state == IEEE80211_S_RUN) 649 imr->ifm_status |= IFM_ACTIVE; 650 651 /* read current transmission rate from adapter */ 652 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE); 653 val &= 0xf; 654 655 /* convert rate to 802.11 rate */ 656 for (i = 0; i < nitems(rates) && rates[i].val != val; i++); 657 rate = (i < nitems(rates)) ? rates[i].rate : 0; 658 659 imr->ifm_active |= IFM_IEEE80211_11B; 660 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 661 switch (ic->ic_opmode) { 662 case IEEE80211_M_STA: 663 break; 664 #ifndef IEEE80211_STA_ONLY 665 case IEEE80211_M_IBSS: 666 imr->ifm_active |= IFM_IEEE80211_IBSS; 667 break; 668 #endif 669 case IEEE80211_M_MONITOR: 670 imr->ifm_active |= IFM_IEEE80211_MONITOR; 671 break; 672 default: 673 /* should not get there */ 674 break; 675 } 676 } 677 678 int 679 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 680 { 681 struct ipw_softc *sc = ic->ic_softc; 682 struct ifnet *ifp = &ic->ic_if; 683 684 if (LINK_STATE_IS_UP(ifp->if_link_state)) 685 ieee80211_set_link_state(ic, LINK_STATE_DOWN); 686 687 switch (nstate) { 688 case IEEE80211_S_SCAN: 689 task_add(systq, &sc->sc_scantask); 690 break; 691 692 case IEEE80211_S_AUTH: 693 task_add(systq, &sc->sc_authandassoctask); 694 break; 695 696 case IEEE80211_S_RUN: 697 if (!(ic->ic_flags & IEEE80211_F_RSNON)) { 698 /* 699 * NB: When RSN is enabled, we defer setting 700 * the link up until the port is valid. 701 */ 702 ieee80211_set_link_state(ic, LINK_STATE_UP); 703 } 704 break; 705 case IEEE80211_S_INIT: 706 case IEEE80211_S_ASSOC: 707 /* nothing to do */ 708 break; 709 } 710 711 ic->ic_state = nstate; 712 return 0; 713 } 714 715 /* 716 * Read 16 bits at address 'addr' from the Microwire EEPROM. 717 * DON'T PLAY WITH THIS CODE UNLESS YOU KNOW *EXACTLY* WHAT YOU'RE DOING! 718 */ 719 uint16_t 720 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 721 { 722 uint32_t tmp; 723 uint16_t val; 724 int n; 725 726 /* clock C once before the first command */ 727 IPW_EEPROM_CTL(sc, 0); 728 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 729 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 730 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 731 732 /* write start bit (1) */ 733 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 734 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 735 736 /* write READ opcode (10) */ 737 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 738 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 739 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 740 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 741 742 /* write address A7-A0 */ 743 for (n = 7; n >= 0; n--) { 744 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 745 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 746 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 747 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 748 } 749 750 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 751 752 /* read data Q15-Q0 */ 753 val = 0; 754 for (n = 15; n >= 0; n--) { 755 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 756 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 757 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 758 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 759 } 760 761 IPW_EEPROM_CTL(sc, 0); 762 763 /* clear Chip Select and clock C */ 764 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 765 IPW_EEPROM_CTL(sc, 0); 766 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 767 768 return val; 769 } 770 771 void 772 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 773 { 774 struct ipw_cmd *cmd; 775 776 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 777 BUS_DMASYNC_POSTREAD); 778 779 cmd = mtod(sbuf->m, struct ipw_cmd *); 780 781 DPRINTFN(2, ("received command ack type=%u,status=%u\n", 782 letoh32(cmd->type), letoh32(cmd->status))); 783 784 wakeup(&sc->cmd); 785 } 786 787 void 788 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 789 { 790 struct ieee80211com *ic = &sc->sc_ic; 791 struct ifnet *ifp = &ic->ic_if; 792 uint32_t state; 793 794 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 795 BUS_DMASYNC_POSTREAD); 796 797 state = letoh32(*mtod(sbuf->m, uint32_t *)); 798 799 DPRINTFN(2, ("firmware state changed to 0x%x\n", state)); 800 801 switch (state) { 802 case IPW_STATE_ASSOCIATED: 803 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 804 break; 805 806 case IPW_STATE_SCANNING: 807 if (ic->ic_state == IEEE80211_S_RUN) 808 ieee80211_begin_scan(ifp); 809 break; 810 811 case IPW_STATE_SCAN_COMPLETE: 812 if (ic->ic_state == IEEE80211_S_SCAN) 813 ieee80211_end_scan(ifp); 814 break; 815 816 case IPW_STATE_ASSOCIATION_LOST: 817 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 818 break; 819 820 case IPW_STATE_DISABLED: 821 wakeup(sc); 822 break; 823 824 case IPW_STATE_RADIO_DISABLED: 825 ipw_stop(&ic->ic_if, 1); 826 break; 827 } 828 } 829 830 void 831 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 832 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf, struct mbuf_list *ml) 833 { 834 struct ieee80211com *ic = &sc->sc_ic; 835 struct ifnet *ifp = &ic->ic_if; 836 struct mbuf *mnew, *m; 837 struct ieee80211_frame *wh; 838 struct ieee80211_rxinfo rxi; 839 struct ieee80211_node *ni; 840 int error; 841 842 DPRINTFN(5, ("received data frame len=%u,rssi=%u\n", 843 letoh32(status->len), status->rssi)); 844 845 /* 846 * Try to allocate a new mbuf for this ring element and load it before 847 * processing the current mbuf. If the ring element cannot be loaded, 848 * drop the received packet and reuse the old mbuf. In the unlikely 849 * case that the old mbuf can't be reloaded either, explicitly panic. 850 */ 851 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 852 if (mnew == NULL) { 853 ifp->if_ierrors++; 854 return; 855 } 856 MCLGET(mnew, M_DONTWAIT); 857 if (!(mnew->m_flags & M_EXT)) { 858 m_freem(mnew); 859 ifp->if_ierrors++; 860 return; 861 } 862 863 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, letoh32(status->len), 864 BUS_DMASYNC_POSTREAD); 865 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 866 867 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, mtod(mnew, void *), 868 MCLBYTES, NULL, BUS_DMA_NOWAIT); 869 if (error != 0) { 870 m_freem(mnew); 871 872 /* try to reload the old mbuf */ 873 error = bus_dmamap_load(sc->sc_dmat, sbuf->map, 874 mtod(sbuf->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 875 if (error != 0) { 876 /* very unlikely that it will fail... */ 877 panic("%s: could not load old rx mbuf", 878 sc->sc_dev.dv_xname); 879 } 880 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 881 ifp->if_ierrors++; 882 return; 883 } 884 885 m = sbuf->m; 886 sbuf->m = mnew; 887 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 888 889 /* finalize mbuf */ 890 m->m_pkthdr.len = m->m_len = letoh32(status->len); 891 892 #if NBPFILTER > 0 893 if (sc->sc_drvbpf != NULL) { 894 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 895 896 tap->wr_flags = 0; 897 tap->wr_antsignal = status->rssi; 898 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 899 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 900 901 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_rxtap_len, 902 m, BPF_DIRECTION_IN); 903 } 904 #endif 905 906 wh = mtod(m, struct ieee80211_frame *); 907 ni = ieee80211_find_rxnode(ic, wh); 908 909 /* send the frame to the upper layer */ 910 memset(&rxi, 0, sizeof(rxi)); 911 rxi.rxi_rssi = status->rssi; 912 ieee80211_inputm(ifp, m, ni, &rxi, ml); 913 914 ieee80211_release_node(ic, ni); 915 } 916 917 void 918 ipw_notification_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 919 { 920 DPRINTFN(2, ("received notification\n")); 921 } 922 923 void 924 ipw_rx_intr(struct ipw_softc *sc) 925 { 926 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 927 struct ipw_status *status; 928 struct ipw_soft_bd *sbd; 929 struct ipw_soft_buf *sbuf; 930 uint32_t r, i; 931 932 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); 933 934 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 935 936 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 937 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 938 BUS_DMASYNC_POSTREAD); 939 940 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 941 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 942 BUS_DMASYNC_POSTREAD); 943 944 status = &sc->status_list[i]; 945 sbd = &sc->srbd_list[i]; 946 sbuf = sbd->priv; 947 948 switch (letoh16(status->code) & 0xf) { 949 case IPW_STATUS_CODE_COMMAND: 950 ipw_command_intr(sc, sbuf); 951 break; 952 953 case IPW_STATUS_CODE_NEWSTATE: 954 ipw_newstate_intr(sc, sbuf); 955 break; 956 957 case IPW_STATUS_CODE_DATA_802_3: 958 case IPW_STATUS_CODE_DATA_802_11: 959 ipw_data_intr(sc, status, sbd, sbuf, &ml); 960 break; 961 962 case IPW_STATUS_CODE_NOTIFICATION: 963 ipw_notification_intr(sc, sbuf); 964 break; 965 966 default: 967 printf("%s: unknown status code %u\n", 968 sc->sc_dev.dv_xname, letoh16(status->code)); 969 } 970 sbd->bd->flags = 0; 971 972 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 973 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 974 BUS_DMASYNC_PREWRITE); 975 } 976 if_input(&sc->sc_ic.ic_if, &ml); 977 978 /* tell the firmware what we have processed */ 979 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 980 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, sc->rxcur); 981 } 982 983 void 984 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 985 { 986 struct ieee80211com *ic = &sc->sc_ic; 987 struct ipw_soft_hdr *shdr; 988 struct ipw_soft_buf *sbuf; 989 990 switch (sbd->type) { 991 case IPW_SBD_TYPE_COMMAND: 992 bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); 993 break; 994 995 case IPW_SBD_TYPE_HEADER: 996 shdr = sbd->priv; 997 bus_dmamap_unload(sc->sc_dmat, shdr->map); 998 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 999 break; 1000 1001 case IPW_SBD_TYPE_DATA: 1002 sbuf = sbd->priv; 1003 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1004 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1005 1006 m_freem(sbuf->m); 1007 1008 if (sbuf->ni != NULL) 1009 ieee80211_release_node(ic, sbuf->ni); 1010 1011 /* kill watchdog timer */ 1012 sc->sc_tx_timer = 0; 1013 break; 1014 } 1015 sbd->type = IPW_SBD_TYPE_NOASSOC; 1016 } 1017 1018 void 1019 ipw_tx_intr(struct ipw_softc *sc) 1020 { 1021 struct ifnet *ifp = &sc->sc_ic.ic_if; 1022 struct ipw_soft_bd *sbd; 1023 uint32_t r, i; 1024 1025 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); 1026 1027 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1028 sbd = &sc->stbd_list[i]; 1029 1030 ipw_release_sbd(sc, sbd); 1031 sc->txfree++; 1032 } 1033 1034 /* remember what the firmware has processed */ 1035 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1036 1037 /* call start() since some buffer descriptors have been released */ 1038 ifq_clr_oactive(&ifp->if_snd); 1039 (*ifp->if_start)(ifp); 1040 } 1041 1042 int 1043 ipw_intr(void *arg) 1044 { 1045 struct ipw_softc *sc = arg; 1046 struct ifnet *ifp = &sc->sc_ic.ic_if; 1047 uint32_t r; 1048 1049 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) 1050 return 0; 1051 1052 /* disable interrupts */ 1053 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1054 1055 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1056 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 1057 ipw_stop(ifp, 1); 1058 return 1; 1059 } 1060 1061 if (r & IPW_INTR_FW_INIT_DONE) 1062 wakeup(sc); 1063 1064 if (r & IPW_INTR_RX_TRANSFER) 1065 ipw_rx_intr(sc); 1066 1067 if (r & IPW_INTR_TX_TRANSFER) 1068 ipw_tx_intr(sc); 1069 1070 /* acknowledge interrupts */ 1071 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1072 1073 /* re-enable interrupts */ 1074 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1075 1076 return 1; 1077 } 1078 1079 int 1080 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1081 { 1082 struct ipw_soft_bd *sbd; 1083 int s, error; 1084 1085 s = splnet(); 1086 1087 sc->cmd.type = htole32(type); 1088 sc->cmd.subtype = htole32(0); 1089 sc->cmd.len = htole32(len); 1090 sc->cmd.seq = htole32(0); 1091 if (data != NULL) 1092 bcopy(data, sc->cmd.data, len); 1093 1094 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 1095 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 1096 if (error != 0) { 1097 printf("%s: can't map command DMA memory\n", 1098 sc->sc_dev.dv_xname); 1099 splx(s); 1100 return error; 1101 } 1102 1103 sbd = &sc->stbd_list[sc->txcur]; 1104 sbd->type = IPW_SBD_TYPE_COMMAND; 1105 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1106 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1107 sbd->bd->nfrag = 1; 1108 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1109 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1110 1111 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1112 BUS_DMASYNC_PREWRITE); 1113 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1114 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1115 BUS_DMASYNC_PREWRITE); 1116 1117 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1118 sc->txfree--; 1119 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1120 1121 DPRINTFN(2, ("sending command type=%u,len=%u\n", type, len)); 1122 1123 /* wait at most one second for command to complete */ 1124 error = tsleep_nsec(&sc->cmd, 0, "ipwcmd", SEC_TO_NSEC(1)); 1125 splx(s); 1126 1127 return error; 1128 } 1129 1130 int 1131 ipw_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type, 1132 int arg1, int arg2) 1133 { 1134 return EOPNOTSUPP; 1135 } 1136 1137 int 1138 ipw_tx_start(struct ifnet *ifp, struct mbuf *m, struct ieee80211_node *ni) 1139 { 1140 struct ipw_softc *sc = ifp->if_softc; 1141 struct ieee80211com *ic = &sc->sc_ic; 1142 struct ieee80211_frame *wh; 1143 struct ieee80211_key *k; 1144 struct ipw_soft_bd *sbd; 1145 struct ipw_soft_hdr *shdr; 1146 struct ipw_soft_buf *sbuf; 1147 int error, i; 1148 1149 wh = mtod(m, struct ieee80211_frame *); 1150 1151 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1152 k = ieee80211_get_txkey(ic, wh, ni); 1153 1154 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1155 return ENOBUFS; 1156 1157 /* packet header may have moved, reset our local pointer */ 1158 wh = mtod(m, struct ieee80211_frame *); 1159 } 1160 1161 #if NBPFILTER > 0 1162 if (sc->sc_drvbpf != NULL) { 1163 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1164 1165 tap->wt_flags = 0; 1166 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1167 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1168 1169 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_txtap_len, 1170 m, BPF_DIRECTION_OUT); 1171 } 1172 #endif 1173 1174 shdr = SLIST_FIRST(&sc->free_shdr); 1175 sbuf = SLIST_FIRST(&sc->free_sbuf); 1176 1177 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1178 shdr->hdr.subtype = htole32(0); 1179 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) ? 1 : 0; 1180 shdr->hdr.encrypt = 0; 1181 shdr->hdr.keyidx = 0; 1182 shdr->hdr.keysz = 0; 1183 shdr->hdr.fragmentsz = htole16(0); 1184 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1185 if (ic->ic_opmode == IEEE80211_M_STA) 1186 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1187 else 1188 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1189 1190 /* trim IEEE802.11 header */ 1191 m_adj(m, sizeof (struct ieee80211_frame)); 1192 1193 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, BUS_DMA_NOWAIT); 1194 if (error != 0 && error != EFBIG) { 1195 printf("%s: can't map mbuf (error %d)\n", 1196 sc->sc_dev.dv_xname, error); 1197 m_freem(m); 1198 return error; 1199 } 1200 if (error != 0) { 1201 /* too many fragments, linearize */ 1202 if (m_defrag(m, M_DONTWAIT)) { 1203 m_freem(m); 1204 return ENOBUFS; 1205 } 1206 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m, 1207 BUS_DMA_NOWAIT); 1208 if (error != 0) { 1209 printf("%s: can't map mbuf (error %d)\n", 1210 sc->sc_dev.dv_xname, error); 1211 m_freem(m); 1212 return error; 1213 } 1214 } 1215 1216 error = bus_dmamap_load(sc->sc_dmat, shdr->map, &shdr->hdr, 1217 sizeof (struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 1218 if (error != 0) { 1219 printf("%s: can't map header DMA memory (error %d)\n", 1220 sc->sc_dev.dv_xname, error); 1221 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1222 m_freem(m); 1223 return error; 1224 } 1225 1226 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1227 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1228 1229 sbd = &sc->stbd_list[sc->txcur]; 1230 sbd->type = IPW_SBD_TYPE_HEADER; 1231 sbd->priv = shdr; 1232 sbd->bd->physaddr = htole32(shdr->map->dm_segs[0].ds_addr); 1233 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1234 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1235 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1236 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1237 1238 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1239 sc->txcur * sizeof (struct ipw_bd), 1240 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1241 1242 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1243 sc->txfree--; 1244 1245 sbuf->m = m; 1246 sbuf->ni = ni; 1247 1248 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1249 sbd = &sc->stbd_list[sc->txcur]; 1250 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1251 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1252 sbd->bd->nfrag = 0; /* used only in first bd */ 1253 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1254 if (i == sbuf->map->dm_nsegs - 1) { 1255 sbd->type = IPW_SBD_TYPE_DATA; 1256 sbd->priv = sbuf; 1257 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1258 } else { 1259 sbd->type = IPW_SBD_TYPE_NOASSOC; 1260 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1261 } 1262 1263 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1264 sc->txcur * sizeof (struct ipw_bd), 1265 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1266 1267 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1268 sc->txfree--; 1269 } 1270 1271 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1272 BUS_DMASYNC_PREWRITE); 1273 bus_dmamap_sync(sc->sc_dmat, shdr->map, 0, sizeof (struct ipw_hdr), 1274 BUS_DMASYNC_PREWRITE); 1275 1276 /* inform firmware about this new packet */ 1277 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, sc->txcur); 1278 1279 return 0; 1280 } 1281 1282 void 1283 ipw_start(struct ifnet *ifp) 1284 { 1285 struct ipw_softc *sc = ifp->if_softc; 1286 struct ieee80211com *ic = &sc->sc_ic; 1287 struct ieee80211_node *ni; 1288 struct mbuf *m; 1289 1290 if (ic->ic_state != IEEE80211_S_RUN) 1291 return; 1292 1293 for (;;) { 1294 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1295 ifq_set_oactive(&ifp->if_snd); 1296 break; 1297 } 1298 1299 m = ifq_dequeue(&ifp->if_snd); 1300 if (m == NULL) 1301 break; 1302 1303 #if NBPFILTER > 0 1304 if (ifp->if_bpf != NULL) 1305 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1306 #endif 1307 1308 m = ieee80211_encap(ifp, m, &ni); 1309 if (m == NULL) 1310 continue; 1311 #if NBPFILTER > 0 1312 if (ic->ic_rawbpf != NULL) 1313 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1314 #endif 1315 if (ipw_tx_start(ifp, m, ni) != 0) { 1316 if (ni != NULL) 1317 ieee80211_release_node(ic, ni); 1318 ifp->if_oerrors++; 1319 break; 1320 } 1321 1322 /* start watchdog timer */ 1323 sc->sc_tx_timer = 5; 1324 ifp->if_timer = 1; 1325 } 1326 } 1327 1328 void 1329 ipw_watchdog(struct ifnet *ifp) 1330 { 1331 struct ipw_softc *sc = ifp->if_softc; 1332 1333 ifp->if_timer = 0; 1334 1335 if (sc->sc_tx_timer > 0) { 1336 if (--sc->sc_tx_timer == 0) { 1337 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1338 ipw_stop(ifp, 1); 1339 ifp->if_oerrors++; 1340 return; 1341 } 1342 ifp->if_timer = 1; 1343 } 1344 1345 ieee80211_watchdog(ifp); 1346 } 1347 1348 int 1349 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1350 { 1351 struct ipw_softc *sc = ifp->if_softc; 1352 int s, error = 0; 1353 1354 error = rw_enter(&sc->sc_rwlock, RW_WRITE | RW_INTR); 1355 if (error) 1356 return error; 1357 s = splnet(); 1358 1359 switch (cmd) { 1360 case SIOCSIFADDR: 1361 ifp->if_flags |= IFF_UP; 1362 /* FALLTHROUGH */ 1363 case SIOCSIFFLAGS: 1364 if (ifp->if_flags & IFF_UP) { 1365 if (!(ifp->if_flags & IFF_RUNNING)) 1366 ipw_init(ifp); 1367 } else { 1368 if (ifp->if_flags & IFF_RUNNING) 1369 ipw_stop(ifp, 1); 1370 } 1371 break; 1372 1373 case SIOCG80211TXPOWER: 1374 /* 1375 * If the hardware radio transmitter switch is off, report a 1376 * tx power of IEEE80211_TXPOWER_MIN to indicate that radio 1377 * transmitter is killed. 1378 */ 1379 ((struct ieee80211_txpower *)data)->i_val = 1380 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? 1381 IEEE80211_TXPOWER_MIN : sc->sc_ic.ic_txpower; 1382 break; 1383 1384 default: 1385 error = ieee80211_ioctl(ifp, cmd, data); 1386 } 1387 1388 if (error == ENETRESET) { 1389 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1390 (IFF_UP | IFF_RUNNING)) 1391 ipw_init(ifp); 1392 error = 0; 1393 } 1394 1395 splx(s); 1396 rw_exit_write(&sc->sc_rwlock); 1397 return error; 1398 } 1399 1400 uint32_t 1401 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1402 { 1403 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1404 } 1405 1406 void 1407 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1408 { 1409 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1410 } 1411 1412 int 1413 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1414 { 1415 uint32_t addr, info; 1416 uint16_t count, size; 1417 uint32_t total; 1418 1419 /* addr[4] + count[2] + size[2] */ 1420 addr = MEM_READ_4(sc, sc->table2_base + off); 1421 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1422 1423 count = info >> 16; 1424 size = info & 0xffff; 1425 total = count * size; 1426 1427 if (total > *len) { 1428 *len = total; 1429 return EINVAL; 1430 } 1431 *len = total; 1432 ipw_read_mem_1(sc, addr, buf, total); 1433 1434 return 0; 1435 } 1436 1437 void 1438 ipw_stop_master(struct ipw_softc *sc) 1439 { 1440 uint32_t tmp; 1441 int ntries; 1442 1443 /* disable interrupts */ 1444 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1445 1446 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1447 for (ntries = 0; ntries < 50; ntries++) { 1448 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1449 break; 1450 DELAY(10); 1451 } 1452 if (ntries == 50) 1453 printf("%s: timeout waiting for master\n", 1454 sc->sc_dev.dv_xname); 1455 1456 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1457 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1458 } 1459 1460 int 1461 ipw_reset(struct ipw_softc *sc) 1462 { 1463 uint32_t tmp; 1464 int ntries; 1465 1466 ipw_stop_master(sc); 1467 1468 /* move adapter to D0 state */ 1469 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1470 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1471 1472 /* wait for clock stabilization */ 1473 for (ntries = 0; ntries < 1000; ntries++) { 1474 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1475 break; 1476 DELAY(200); 1477 } 1478 if (ntries == 1000) 1479 return EIO; 1480 1481 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1482 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1483 1484 DELAY(10); 1485 1486 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1487 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1488 1489 return 0; 1490 } 1491 1492 int 1493 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1494 { 1495 int ntries; 1496 1497 /* voodoo from the Intel Linux driver */ 1498 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1499 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1500 1501 MEM_WRITE_2(sc, 0x220000, 0x0703); 1502 MEM_WRITE_2(sc, 0x220000, 0x0707); 1503 1504 MEM_WRITE_1(sc, 0x210014, 0x72); 1505 MEM_WRITE_1(sc, 0x210014, 0x72); 1506 1507 MEM_WRITE_1(sc, 0x210000, 0x40); 1508 MEM_WRITE_1(sc, 0x210000, 0x00); 1509 MEM_WRITE_1(sc, 0x210000, 0x40); 1510 1511 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1512 1513 MEM_WRITE_1(sc, 0x210000, 0x00); 1514 MEM_WRITE_1(sc, 0x210000, 0x00); 1515 MEM_WRITE_1(sc, 0x210000, 0x80); 1516 1517 MEM_WRITE_2(sc, 0x220000, 0x0703); 1518 MEM_WRITE_2(sc, 0x220000, 0x0707); 1519 1520 MEM_WRITE_1(sc, 0x210014, 0x72); 1521 MEM_WRITE_1(sc, 0x210014, 0x72); 1522 1523 MEM_WRITE_1(sc, 0x210000, 0x00); 1524 MEM_WRITE_1(sc, 0x210000, 0x80); 1525 1526 for (ntries = 0; ntries < 100; ntries++) { 1527 if (MEM_READ_1(sc, 0x210000) & 1) 1528 break; 1529 DELAY(1000); 1530 } 1531 if (ntries == 100) { 1532 printf("%s: timeout waiting for ucode to initialize\n", 1533 sc->sc_dev.dv_xname); 1534 return EIO; 1535 } 1536 1537 MEM_WRITE_4(sc, 0x3000e0, 0); 1538 1539 return 0; 1540 } 1541 1542 /* set of macros to handle unaligned little endian data in firmware image */ 1543 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1544 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1545 int 1546 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1547 { 1548 u_char *p, *end; 1549 uint32_t tmp, dst; 1550 uint16_t len; 1551 int error; 1552 1553 p = fw; 1554 end = fw + size; 1555 while (p < end) { 1556 if (p + 6 > end) 1557 return EINVAL; 1558 1559 dst = GETLE32(p); p += 4; 1560 len = GETLE16(p); p += 2; 1561 1562 if (p + len > end) 1563 return EINVAL; 1564 1565 ipw_write_mem_1(sc, dst, p, len); 1566 p += len; 1567 } 1568 1569 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1570 IPW_IO_LED_OFF); 1571 1572 /* allow interrupts so we know when the firmware is inited */ 1573 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1574 1575 /* tell the adapter to initialize the firmware */ 1576 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1577 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1578 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1579 1580 /* wait at most one second for firmware initialization to complete */ 1581 if ((error = tsleep_nsec(sc, 0, "ipwinit", SEC_TO_NSEC(1))) != 0) { 1582 printf("%s: timeout waiting for firmware initialization to " 1583 "complete\n", sc->sc_dev.dv_xname); 1584 return error; 1585 } 1586 1587 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1588 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1589 IPW_IO_GPIO3_MASK); 1590 1591 return 0; 1592 } 1593 1594 int 1595 ipw_read_firmware(struct ipw_softc *sc, struct ipw_firmware *fw) 1596 { 1597 const struct ipw_firmware_hdr *hdr; 1598 const char *name; 1599 int error; 1600 1601 switch (sc->sc_ic.ic_opmode) { 1602 case IEEE80211_M_STA: 1603 name = "ipw-bss"; 1604 break; 1605 #ifndef IEEE80211_STA_ONLY 1606 case IEEE80211_M_IBSS: 1607 name = "ipw-ibss"; 1608 break; 1609 #endif 1610 case IEEE80211_M_MONITOR: 1611 name = "ipw-monitor"; 1612 break; 1613 default: 1614 /* should not get there */ 1615 return ENODEV; 1616 } 1617 if ((error = loadfirmware(name, &fw->data, &fw->size)) != 0) 1618 return error; 1619 1620 if (fw->size < sizeof (*hdr)) { 1621 error = EINVAL; 1622 goto fail; 1623 } 1624 hdr = (const struct ipw_firmware_hdr *)fw->data; 1625 fw->main_size = letoh32(hdr->main_size); 1626 fw->ucode_size = letoh32(hdr->ucode_size); 1627 1628 if (fw->size < sizeof (*hdr) + fw->main_size + fw->ucode_size) { 1629 error = EINVAL; 1630 goto fail; 1631 } 1632 fw->main = fw->data + sizeof (*hdr); 1633 fw->ucode = fw->main + fw->main_size; 1634 1635 return 0; 1636 1637 fail: free(fw->data, M_DEVBUF, fw->size); 1638 return error; 1639 } 1640 1641 void 1642 ipw_scan(void *arg1) 1643 { 1644 struct ipw_softc *sc = arg1; 1645 struct ifnet *ifp = &sc->sc_ic.ic_if; 1646 struct ipw_scan_options scan; 1647 uint8_t ssid[IEEE80211_NWID_LEN]; 1648 int error; 1649 1650 /* 1651 * Firmware has a bug and does not honour the ``do not associate 1652 * after scan'' bit in the scan command. To prevent the firmware 1653 * from associating after the scan, we set the ESSID to something 1654 * unlikely to be used by a real AP. 1655 * XXX would setting the desired BSSID to a multicast address work? 1656 */ 1657 memset(ssid, '\r', sizeof ssid); 1658 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ssid, sizeof ssid); 1659 if (error != 0) 1660 goto fail; 1661 1662 /* no mandatory BSSID */ 1663 DPRINTF(("Setting mandatory BSSID to null\n")); 1664 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1665 if (error != 0) 1666 goto fail; 1667 1668 scan.flags = htole32(IPW_SCAN_DO_NOT_ASSOCIATE | IPW_SCAN_MIXED_CELL); 1669 scan.channels = htole32(0x3fff); /* scan channels 1-14 */ 1670 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1671 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1672 if (error != 0) 1673 goto fail; 1674 1675 /* start scanning */ 1676 DPRINTF(("Enabling adapter\n")); 1677 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1678 if (error != 0) 1679 goto fail; 1680 1681 return; 1682 fail: 1683 printf("%s: scan request failed (error=%d)\n", sc->sc_dev.dv_xname, 1684 error); 1685 ieee80211_end_scan(ifp); 1686 } 1687 1688 void 1689 ipw_auth_and_assoc(void *arg1) 1690 { 1691 struct ipw_softc *sc = arg1; 1692 struct ieee80211com *ic = &sc->sc_ic; 1693 struct ieee80211_node *ni = ic->ic_bss; 1694 struct ipw_scan_options scan; 1695 struct ipw_security security; 1696 struct ipw_assoc_req assoc; 1697 uint32_t data; 1698 uint8_t chan; 1699 int s, error; 1700 1701 DPRINTF(("Disabling adapter\n")); 1702 error = ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); 1703 if (error != 0) 1704 goto fail; 1705 #if 1 1706 /* wait at most one second for card to be disabled */ 1707 s = splnet(); 1708 error = tsleep_nsec(sc, 0, "ipwdis", SEC_TO_NSEC(1)); 1709 splx(s); 1710 if (error != 0) { 1711 printf("%s: timeout waiting for disabled state\n", 1712 sc->sc_dev.dv_xname); 1713 goto fail; 1714 } 1715 #else 1716 /* Intel's Linux driver polls for the DISABLED state instead.. */ 1717 for (ntries = 0; ntries < 1000; ntries++) { 1718 if (ipw_read_table1(sc, IPW_INFO_CARD_DISABLED) == 1) 1719 break; 1720 DELAY(10); 1721 } 1722 if (ntries == 1000) { 1723 printf("%s: timeout waiting for disabled state\n", 1724 sc->sc_dev.dv_xname); 1725 goto fail; 1726 } 1727 #endif 1728 1729 bzero(&security, sizeof security); 1730 security.authmode = IPW_AUTH_OPEN; 1731 security.ciphers = htole32(IPW_CIPHER_NONE); 1732 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1733 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1734 sizeof security); 1735 if (error != 0) 1736 goto fail; 1737 1738 #ifdef IPW_DEBUG 1739 if (ipw_debug > 0) { 1740 printf("Setting ESSID to "); 1741 ieee80211_print_essid(ni->ni_essid, ni->ni_esslen); 1742 printf("\n"); 1743 } 1744 #endif 1745 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ni->ni_essid, ni->ni_esslen); 1746 if (error != 0) 1747 goto fail; 1748 1749 DPRINTF(("Setting BSSID to %s\n", ether_sprintf(ni->ni_bssid))); 1750 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, ni->ni_bssid, 1751 IEEE80211_ADDR_LEN); 1752 if (error != 0) 1753 goto fail; 1754 1755 data = htole32((ic->ic_flags & (IEEE80211_F_WEPON | 1756 IEEE80211_F_RSNON)) ? IPW_PRIVACYON : 0); 1757 DPRINTF(("Setting privacy flags to 0x%x\n", letoh32(data))); 1758 error = ipw_cmd(sc, IPW_CMD_SET_PRIVACY_FLAGS, &data, sizeof data); 1759 if (error != 0) 1760 goto fail; 1761 1762 /* let firmware set the capinfo, lintval, and bssid fixed fields */ 1763 bzero(&assoc, sizeof assoc); 1764 if (ic->ic_flags & IEEE80211_F_RSNON) { 1765 uint8_t *frm = assoc.optie; 1766 1767 /* tell firmware to add a WPA or RSN IE in (Re)Assoc req */ 1768 if (ni->ni_rsnprotos & IEEE80211_PROTO_RSN) 1769 frm = ieee80211_add_rsn(frm, ic, ni); 1770 else if (ni->ni_rsnprotos & IEEE80211_PROTO_WPA) 1771 frm = ieee80211_add_wpa(frm, ic, ni); 1772 assoc.optie_len = htole32(frm - assoc.optie); 1773 } 1774 DPRINTF(("Preparing association request (optional IE length=%d)\n", 1775 letoh32(assoc.optie_len))); 1776 error = ipw_cmd(sc, IPW_CMD_SET_ASSOC_REQ, &assoc, sizeof assoc); 1777 if (error != 0) 1778 goto fail; 1779 1780 scan.flags = htole32(IPW_SCAN_MIXED_CELL); 1781 chan = ieee80211_chan2ieee(ic, ni->ni_chan); 1782 scan.channels = htole32(1 << (chan - 1)); 1783 DPRINTF(("Setting scan options to 0x%x\n", letoh32(scan.flags))); 1784 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &scan, sizeof scan); 1785 if (error != 0) 1786 goto fail; 1787 1788 /* trigger scan+association */ 1789 DPRINTF(("Enabling adapter\n")); 1790 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1791 if (error != 0) 1792 goto fail; 1793 1794 /* 1795 * net80211 won't see the AP's auth response. Move to ASSOC state 1796 * in order to make net80211 accept the AP's assoc response. 1797 */ 1798 ic->ic_newstate(ic, IEEE80211_S_ASSOC, -1); 1799 1800 return; 1801 fail: 1802 printf("%s: association failed (error=%d)\n", sc->sc_dev.dv_xname, 1803 error); 1804 ieee80211_begin_scan(&ic->ic_if); 1805 } 1806 1807 int 1808 ipw_config(struct ipw_softc *sc) 1809 { 1810 struct ieee80211com *ic = &sc->sc_ic; 1811 struct ifnet *ifp = &ic->ic_if; 1812 struct ipw_configuration config; 1813 uint32_t data; 1814 int error; 1815 1816 switch (ic->ic_opmode) { 1817 case IEEE80211_M_STA: 1818 data = htole32(IPW_MODE_BSS); 1819 break; 1820 #ifndef IEEE80211_STA_ONLY 1821 case IEEE80211_M_IBSS: 1822 data = htole32(IPW_MODE_IBSS); 1823 break; 1824 #endif 1825 case IEEE80211_M_MONITOR: 1826 data = htole32(IPW_MODE_MONITOR); 1827 break; 1828 default: 1829 /* should not get there */ 1830 return ENODEV; 1831 } 1832 DPRINTF(("Setting mode to %u\n", letoh32(data))); 1833 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1834 if (error != 0) 1835 return error; 1836 1837 if ( 1838 #ifndef IEEE80211_STA_ONLY 1839 ic->ic_opmode == IEEE80211_M_IBSS || 1840 #endif 1841 ic->ic_opmode == IEEE80211_M_MONITOR) { 1842 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1843 DPRINTF(("Setting channel to %u\n", letoh32(data))); 1844 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1845 if (error != 0) 1846 return error; 1847 } 1848 1849 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1850 DPRINTF(("Enabling adapter\n")); 1851 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1852 } 1853 1854 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 1855 DPRINTF(("Setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr))); 1856 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1857 IEEE80211_ADDR_LEN); 1858 if (error != 0) 1859 return error; 1860 1861 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1862 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1X_ENABLE); 1863 #ifndef IEEE80211_STA_ONLY 1864 if (ic->ic_opmode == IEEE80211_M_IBSS) 1865 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1866 #endif 1867 if (ifp->if_flags & IFF_PROMISC) 1868 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1869 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1870 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1871 DPRINTF(("Setting configuration 0x%x\n", config.flags)); 1872 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1873 if (error != 0) 1874 return error; 1875 1876 data = htole32(ic->ic_rtsthreshold); 1877 DPRINTF(("Setting RTS threshold to %u\n", letoh32(data))); 1878 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1879 if (error != 0) 1880 return error; 1881 1882 data = htole32(ic->ic_fragthreshold); 1883 DPRINTF(("Setting frag threshold to %u\n", letoh32(data))); 1884 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1885 if (error != 0) 1886 return error; 1887 1888 data = htole32(0x3); /* 1, 2 */ 1889 DPRINTF(("Setting basic tx rates to 0x%x\n", letoh32(data))); 1890 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1891 if (error != 0) 1892 return error; 1893 1894 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1895 DPRINTF(("Setting tx rates to 0x%x\n", letoh32(data))); 1896 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1897 if (error != 0) 1898 return error; 1899 1900 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1901 DPRINTF(("Setting MSDU tx rates to 0x%x\n", letoh32(data))); 1902 error = ipw_cmd(sc, IPW_CMD_SET_MSDU_TX_RATES, &data, sizeof data); 1903 if (error != 0) 1904 return error; 1905 1906 data = htole32(IPW_POWER_MODE_CAM); 1907 DPRINTF(("Setting power mode to %u\n", letoh32(data))); 1908 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1909 if (error != 0) 1910 return error; 1911 1912 #ifndef IEEE80211_STA_ONLY 1913 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1914 data = htole32(32); /* default value */ 1915 DPRINTF(("Setting tx power index to %u\n", letoh32(data))); 1916 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1917 sizeof data); 1918 if (error != 0) 1919 return error; 1920 1921 data = htole32(ic->ic_lintval); 1922 DPRINTF(("Setting beacon interval to %u\n", letoh32(data))); 1923 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1924 sizeof data); 1925 if (error != 0) 1926 return error; 1927 } 1928 #endif 1929 return 0; 1930 } 1931 1932 int 1933 ipw_init(struct ifnet *ifp) 1934 { 1935 struct ipw_softc *sc = ifp->if_softc; 1936 struct ieee80211com *ic = &sc->sc_ic; 1937 struct ipw_firmware fw; 1938 int error; 1939 1940 ipw_stop(ifp, 0); 1941 1942 if ((error = ipw_reset(sc)) != 0) { 1943 printf("%s: could not reset adapter\n", sc->sc_dev.dv_xname); 1944 goto fail1; 1945 } 1946 1947 if ((error = ipw_read_firmware(sc, &fw)) != 0) { 1948 printf("%s: error %d, could not read firmware\n", 1949 sc->sc_dev.dv_xname, error); 1950 goto fail1; 1951 } 1952 if ((error = ipw_load_ucode(sc, fw.ucode, fw.ucode_size)) != 0) { 1953 printf("%s: could not load microcode\n", sc->sc_dev.dv_xname); 1954 goto fail2; 1955 } 1956 1957 ipw_stop_master(sc); 1958 1959 /* 1960 * Setup tx, rx and status rings. 1961 */ 1962 CSR_WRITE_4(sc, IPW_CSR_TX_BD_BASE, sc->tbd_map->dm_segs[0].ds_addr); 1963 CSR_WRITE_4(sc, IPW_CSR_TX_BD_SIZE, IPW_NTBD); 1964 CSR_WRITE_4(sc, IPW_CSR_TX_READ_INDEX, 0); 1965 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE_INDEX, 0); 1966 sc->txold = IPW_NTBD - 1; /* latest bd index ack by firmware */ 1967 sc->txcur = 0; /* bd index to write to */ 1968 sc->txfree = IPW_NTBD - 2; 1969 1970 CSR_WRITE_4(sc, IPW_CSR_RX_BD_BASE, sc->rbd_map->dm_segs[0].ds_addr); 1971 CSR_WRITE_4(sc, IPW_CSR_RX_BD_SIZE, IPW_NRBD); 1972 CSR_WRITE_4(sc, IPW_CSR_RX_READ_INDEX, 0); 1973 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE_INDEX, IPW_NRBD - 1); 1974 sc->rxcur = IPW_NRBD - 1; /* latest bd index I've read */ 1975 1976 CSR_WRITE_4(sc, IPW_CSR_RX_STATUS_BASE, 1977 sc->status_map->dm_segs[0].ds_addr); 1978 1979 if ((error = ipw_load_firmware(sc, fw.main, fw.main_size)) != 0) { 1980 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 1981 goto fail2; 1982 } 1983 free(fw.data, M_DEVBUF, fw.size); 1984 fw.data = NULL; 1985 1986 /* retrieve information tables base addresses */ 1987 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 1988 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 1989 1990 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 1991 1992 if ((error = ipw_config(sc)) != 0) { 1993 printf("%s: device configuration failed\n", 1994 sc->sc_dev.dv_xname); 1995 goto fail1; 1996 } 1997 1998 ifq_clr_oactive(&ifp->if_snd); 1999 ifp->if_flags |= IFF_RUNNING; 2000 2001 if (ic->ic_opmode != IEEE80211_M_MONITOR) 2002 ieee80211_begin_scan(ifp); 2003 else 2004 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2005 2006 return 0; 2007 2008 fail2: free(fw.data, M_DEVBUF, fw.size); 2009 fw.data = NULL; 2010 fail1: ipw_stop(ifp, 0); 2011 return error; 2012 } 2013 2014 void 2015 ipw_stop(struct ifnet *ifp, int disable) 2016 { 2017 struct ipw_softc *sc = ifp->if_softc; 2018 struct ieee80211com *ic = &sc->sc_ic; 2019 int i; 2020 2021 ipw_stop_master(sc); 2022 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2023 2024 ifp->if_timer = 0; 2025 ifp->if_flags &= ~IFF_RUNNING; 2026 ifq_clr_oactive(&ifp->if_snd); 2027 2028 /* 2029 * Release tx buffers. 2030 */ 2031 for (i = 0; i < IPW_NTBD; i++) 2032 ipw_release_sbd(sc, &sc->stbd_list[i]); 2033 2034 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2035 } 2036 2037 void 2038 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2039 bus_size_t count) 2040 { 2041 for (; count > 0; offset++, datap++, count--) { 2042 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2043 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2044 } 2045 } 2046 2047 void 2048 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2049 bus_size_t count) 2050 { 2051 for (; count > 0; offset++, datap++, count--) { 2052 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2053 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2054 } 2055 } 2056 2057 struct cfdriver ipw_cd = { 2058 NULL, "ipw", DV_IFNET 2059 }; 2060