1 /* $OpenBSD: if_igc.c,v 1.22 2024/05/06 04:25:52 dlg Exp $ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause 4 * 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * All rights reserved. 7 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate) 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include "bpfilter.h" 32 #include "vlan.h" 33 #include "kstat.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/device.h> 43 #include <sys/endian.h> 44 #include <sys/intrmap.h> 45 #include <sys/kstat.h> 46 47 #include <net/if.h> 48 #include <net/if_media.h> 49 #include <net/route.h> 50 #include <net/toeplitz.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 #include <netinet/tcp.h> 55 #include <netinet/tcp_timer.h> 56 #include <netinet/tcp_var.h> 57 58 #if NBPFILTER > 0 59 #include <net/bpf.h> 60 #endif 61 62 #include <machine/bus.h> 63 #include <machine/intr.h> 64 65 #include <dev/pci/pcivar.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcidevs.h> 68 #include <dev/pci/if_igc.h> 69 #include <dev/pci/igc_hw.h> 70 71 const struct pci_matchid igc_devices[] = { 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I220_V }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I221_V }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_BLANK_NVM }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_I }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_IT }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_K }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_K2 }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_LM }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_LMVP }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_V }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I226_BLANK_NVM }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I226_IT }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I226_LM }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I226_K }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I226_V } 87 }; 88 89 /********************************************************************* 90 * Function Prototypes 91 *********************************************************************/ 92 int igc_match(struct device *, void *, void *); 93 void igc_attach(struct device *, struct device *, void *); 94 int igc_detach(struct device *, int); 95 96 void igc_identify_hardware(struct igc_softc *); 97 int igc_allocate_pci_resources(struct igc_softc *); 98 int igc_allocate_queues(struct igc_softc *); 99 void igc_free_pci_resources(struct igc_softc *); 100 void igc_reset(struct igc_softc *); 101 void igc_init_dmac(struct igc_softc *, uint32_t); 102 int igc_allocate_msix(struct igc_softc *); 103 void igc_setup_msix(struct igc_softc *); 104 int igc_dma_malloc(struct igc_softc *, bus_size_t, struct igc_dma_alloc *); 105 void igc_dma_free(struct igc_softc *, struct igc_dma_alloc *); 106 void igc_setup_interface(struct igc_softc *); 107 108 void igc_init(void *); 109 void igc_start(struct ifqueue *); 110 int igc_txeof(struct tx_ring *); 111 void igc_stop(struct igc_softc *); 112 int igc_ioctl(struct ifnet *, u_long, caddr_t); 113 int igc_rxrinfo(struct igc_softc *, struct if_rxrinfo *); 114 int igc_rxfill(struct rx_ring *); 115 void igc_rxrefill(void *); 116 int igc_rxeof(struct rx_ring *); 117 void igc_rx_checksum(uint32_t, struct mbuf *, uint32_t); 118 void igc_watchdog(struct ifnet *); 119 void igc_media_status(struct ifnet *, struct ifmediareq *); 120 int igc_media_change(struct ifnet *); 121 void igc_iff(struct igc_softc *); 122 void igc_update_link_status(struct igc_softc *); 123 int igc_get_buf(struct rx_ring *, int); 124 int igc_tx_ctx_setup(struct tx_ring *, struct mbuf *, int, uint32_t *, 125 uint32_t *); 126 127 void igc_configure_queues(struct igc_softc *); 128 void igc_set_queues(struct igc_softc *, uint32_t, uint32_t, int); 129 void igc_enable_queue(struct igc_softc *, uint32_t); 130 void igc_enable_intr(struct igc_softc *); 131 void igc_disable_intr(struct igc_softc *); 132 int igc_intr_link(void *); 133 int igc_intr_queue(void *); 134 135 int igc_allocate_transmit_buffers(struct tx_ring *); 136 int igc_setup_transmit_structures(struct igc_softc *); 137 int igc_setup_transmit_ring(struct tx_ring *); 138 void igc_initialize_transmit_unit(struct igc_softc *); 139 void igc_free_transmit_structures(struct igc_softc *); 140 void igc_free_transmit_buffers(struct tx_ring *); 141 int igc_allocate_receive_buffers(struct rx_ring *); 142 int igc_setup_receive_structures(struct igc_softc *); 143 int igc_setup_receive_ring(struct rx_ring *); 144 void igc_initialize_receive_unit(struct igc_softc *); 145 void igc_free_receive_structures(struct igc_softc *); 146 void igc_free_receive_buffers(struct rx_ring *); 147 void igc_initialize_rss_mapping(struct igc_softc *); 148 149 void igc_get_hw_control(struct igc_softc *); 150 void igc_release_hw_control(struct igc_softc *); 151 int igc_is_valid_ether_addr(uint8_t *); 152 153 #if NKSTAT > 0 154 void igc_kstat_attach(struct igc_softc *); 155 #endif 156 157 /********************************************************************* 158 * OpenBSD Device Interface Entry Points 159 *********************************************************************/ 160 161 struct cfdriver igc_cd = { 162 NULL, "igc", DV_IFNET 163 }; 164 165 const struct cfattach igc_ca = { 166 sizeof(struct igc_softc), igc_match, igc_attach, igc_detach 167 }; 168 169 /********************************************************************* 170 * Device identification routine 171 * 172 * igc_match determines if the driver should be loaded on 173 * adapter based on PCI vendor/device id of the adapter. 174 * 175 * return 0 on success, positive on failure 176 *********************************************************************/ 177 int 178 igc_match(struct device *parent, void *match, void *aux) 179 { 180 return pci_matchbyid((struct pci_attach_args *)aux, igc_devices, 181 nitems(igc_devices)); 182 } 183 184 /********************************************************************* 185 * Device initialization routine 186 * 187 * The attach entry point is called when the driver is being loaded. 188 * This routine identifies the type of hardware, allocates all resources 189 * and initializes the hardware. 190 * 191 * return 0 on success, positive on failure 192 *********************************************************************/ 193 void 194 igc_attach(struct device *parent, struct device *self, void *aux) 195 { 196 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 197 struct igc_softc *sc = (struct igc_softc *)self; 198 struct igc_hw *hw = &sc->hw; 199 200 sc->osdep.os_sc = sc; 201 sc->osdep.os_pa = *pa; 202 203 /* Determine hardware and mac info */ 204 igc_identify_hardware(sc); 205 206 sc->num_tx_desc = IGC_DEFAULT_TXD; 207 sc->num_rx_desc = IGC_DEFAULT_RXD; 208 209 /* Setup PCI resources */ 210 if (igc_allocate_pci_resources(sc)) 211 goto err_pci; 212 213 /* Allocate TX/RX queues */ 214 if (igc_allocate_queues(sc)) 215 goto err_pci; 216 217 /* Do shared code initialization */ 218 if (igc_setup_init_funcs(hw, true)) { 219 printf(": Setup of shared code failed\n"); 220 goto err_pci; 221 } 222 223 hw->mac.autoneg = DO_AUTO_NEG; 224 hw->phy.autoneg_wait_to_complete = false; 225 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 226 227 /* Copper options. */ 228 if (hw->phy.media_type == igc_media_type_copper) 229 hw->phy.mdix = AUTO_ALL_MODES; 230 231 /* Set the max frame size. */ 232 sc->hw.mac.max_frame_size = 9234; 233 234 /* Allocate multicast array memory. */ 235 sc->mta = mallocarray(ETHER_ADDR_LEN, MAX_NUM_MULTICAST_ADDRESSES, 236 M_DEVBUF, M_NOWAIT); 237 if (sc->mta == NULL) { 238 printf(": Can not allocate multicast setup array\n"); 239 goto err_late; 240 } 241 242 /* Check SOL/IDER usage. */ 243 if (igc_check_reset_block(hw)) 244 printf(": PHY reset is blocked due to SOL/IDER session\n"); 245 246 /* Disable Energy Efficient Ethernet. */ 247 sc->hw.dev_spec._i225.eee_disable = true; 248 249 igc_reset_hw(hw); 250 251 /* Make sure we have a good EEPROM before we read from it. */ 252 if (igc_validate_nvm_checksum(hw) < 0) { 253 /* 254 * Some PCI-E parts fail the first check due to 255 * the link being in sleep state, call it again, 256 * if it fails a second time its a real issue. 257 */ 258 if (igc_validate_nvm_checksum(hw) < 0) { 259 printf(": The EEPROM checksum is not valid\n"); 260 goto err_late; 261 } 262 } 263 264 /* Copy the permanent MAC address out of the EEPROM. */ 265 if (igc_read_mac_addr(hw) < 0) { 266 printf(": EEPROM read error while reading MAC address\n"); 267 goto err_late; 268 } 269 270 if (!igc_is_valid_ether_addr(hw->mac.addr)) { 271 printf(": Invalid MAC address\n"); 272 goto err_late; 273 } 274 275 memcpy(sc->sc_ac.ac_enaddr, sc->hw.mac.addr, ETHER_ADDR_LEN); 276 277 if (igc_allocate_msix(sc)) 278 goto err_late; 279 280 /* Setup OS specific network interface. */ 281 igc_setup_interface(sc); 282 283 igc_reset(sc); 284 hw->mac.get_link_status = true; 285 igc_update_link_status(sc); 286 287 /* The driver can now take control from firmware. */ 288 igc_get_hw_control(sc); 289 290 printf(", address %s\n", ether_sprintf(sc->hw.mac.addr)); 291 292 #if NKSTAT > 0 293 igc_kstat_attach(sc); 294 #endif 295 return; 296 297 err_late: 298 igc_release_hw_control(sc); 299 err_pci: 300 igc_free_pci_resources(sc); 301 free(sc->mta, M_DEVBUF, ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 302 } 303 304 /********************************************************************* 305 * Device removal routine 306 * 307 * The detach entry point is called when the driver is being removed. 308 * This routine stops the adapter and deallocates all the resources 309 * that were allocated for driver operation. 310 * 311 * return 0 on success, positive on failure 312 *********************************************************************/ 313 int 314 igc_detach(struct device *self, int flags) 315 { 316 struct igc_softc *sc = (struct igc_softc *)self; 317 struct ifnet *ifp = &sc->sc_ac.ac_if; 318 319 igc_stop(sc); 320 321 igc_phy_hw_reset(&sc->hw); 322 igc_release_hw_control(sc); 323 324 ether_ifdetach(ifp); 325 if_detach(ifp); 326 327 igc_free_pci_resources(sc); 328 329 igc_free_transmit_structures(sc); 330 igc_free_receive_structures(sc); 331 free(sc->mta, M_DEVBUF, ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 332 333 return 0; 334 } 335 336 void 337 igc_identify_hardware(struct igc_softc *sc) 338 { 339 struct igc_osdep *os = &sc->osdep; 340 struct pci_attach_args *pa = &os->os_pa; 341 342 /* Save off the information about this board. */ 343 sc->hw.device_id = PCI_PRODUCT(pa->pa_id); 344 345 /* Do shared code init and setup. */ 346 if (igc_set_mac_type(&sc->hw)) { 347 printf(": Setup init failure\n"); 348 return; 349 } 350 } 351 352 int 353 igc_allocate_pci_resources(struct igc_softc *sc) 354 { 355 struct igc_osdep *os = &sc->osdep; 356 struct pci_attach_args *pa = &os->os_pa; 357 pcireg_t memtype; 358 359 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IGC_PCIREG); 360 if (pci_mapreg_map(pa, IGC_PCIREG, memtype, 0, &os->os_memt, 361 &os->os_memh, &os->os_membase, &os->os_memsize, 0)) { 362 printf(": unable to map registers\n"); 363 return ENXIO; 364 } 365 sc->hw.hw_addr = (uint8_t *)os->os_membase; 366 sc->hw.back = os; 367 368 igc_setup_msix(sc); 369 370 return 0; 371 } 372 373 int 374 igc_allocate_queues(struct igc_softc *sc) 375 { 376 struct igc_queue *iq; 377 struct tx_ring *txr; 378 struct rx_ring *rxr; 379 int i, rsize, rxconf, tsize, txconf; 380 381 /* Allocate the top level queue structs. */ 382 sc->queues = mallocarray(sc->sc_nqueues, sizeof(struct igc_queue), 383 M_DEVBUF, M_NOWAIT | M_ZERO); 384 if (sc->queues == NULL) { 385 printf("%s: unable to allocate queue\n", DEVNAME(sc)); 386 goto fail; 387 } 388 389 /* Allocate the TX ring. */ 390 sc->tx_rings = mallocarray(sc->sc_nqueues, sizeof(struct tx_ring), 391 M_DEVBUF, M_NOWAIT | M_ZERO); 392 if (sc->tx_rings == NULL) { 393 printf("%s: unable to allocate TX ring\n", DEVNAME(sc)); 394 goto fail; 395 } 396 397 /* Allocate the RX ring. */ 398 sc->rx_rings = mallocarray(sc->sc_nqueues, sizeof(struct rx_ring), 399 M_DEVBUF, M_NOWAIT | M_ZERO); 400 if (sc->rx_rings == NULL) { 401 printf("%s: unable to allocate RX ring\n", DEVNAME(sc)); 402 goto rx_fail; 403 } 404 405 txconf = rxconf = 0; 406 407 /* Set up the TX queues. */ 408 tsize = roundup2(sc->num_tx_desc * sizeof(union igc_adv_tx_desc), 409 IGC_DBA_ALIGN); 410 for (i = 0; i < sc->sc_nqueues; i++, txconf++) { 411 txr = &sc->tx_rings[i]; 412 txr->sc = sc; 413 txr->me = i; 414 415 if (igc_dma_malloc(sc, tsize, &txr->txdma)) { 416 printf("%s: unable to allocate TX descriptor\n", 417 DEVNAME(sc)); 418 goto err_tx_desc; 419 } 420 txr->tx_base = (union igc_adv_tx_desc *)txr->txdma.dma_vaddr; 421 bzero((void *)txr->tx_base, tsize); 422 } 423 424 /* Set up the RX queues. */ 425 rsize = roundup2(sc->num_rx_desc * sizeof(union igc_adv_rx_desc), 426 IGC_DBA_ALIGN); 427 for (i = 0; i < sc->sc_nqueues; i++, rxconf++) { 428 rxr = &sc->rx_rings[i]; 429 rxr->sc = sc; 430 rxr->me = i; 431 timeout_set(&rxr->rx_refill, igc_rxrefill, rxr); 432 433 if (igc_dma_malloc(sc, rsize, &rxr->rxdma)) { 434 printf("%s: unable to allocate RX descriptor\n", 435 DEVNAME(sc)); 436 goto err_rx_desc; 437 } 438 rxr->rx_base = (union igc_adv_rx_desc *)rxr->rxdma.dma_vaddr; 439 bzero((void *)rxr->rx_base, rsize); 440 } 441 442 /* Set up the queue holding structs. */ 443 for (i = 0; i < sc->sc_nqueues; i++) { 444 iq = &sc->queues[i]; 445 iq->sc = sc; 446 iq->txr = &sc->tx_rings[i]; 447 iq->rxr = &sc->rx_rings[i]; 448 snprintf(iq->name, sizeof(iq->name), "%s:%d", DEVNAME(sc), i); 449 } 450 451 return 0; 452 453 err_rx_desc: 454 for (rxr = sc->rx_rings; rxconf > 0; rxr++, rxconf--) 455 igc_dma_free(sc, &rxr->rxdma); 456 err_tx_desc: 457 for (txr = sc->tx_rings; txconf > 0; txr++, txconf--) 458 igc_dma_free(sc, &txr->txdma); 459 free(sc->rx_rings, M_DEVBUF, sc->sc_nqueues * sizeof(struct rx_ring)); 460 sc->rx_rings = NULL; 461 rx_fail: 462 free(sc->tx_rings, M_DEVBUF, sc->sc_nqueues * sizeof(struct tx_ring)); 463 sc->tx_rings = NULL; 464 fail: 465 return ENOMEM; 466 } 467 468 void 469 igc_free_pci_resources(struct igc_softc *sc) 470 { 471 struct igc_osdep *os = &sc->osdep; 472 struct pci_attach_args *pa = &os->os_pa; 473 struct igc_queue *iq = sc->queues; 474 int i; 475 476 /* Release all msix queue resources. */ 477 for (i = 0; i < sc->sc_nqueues; i++, iq++) { 478 if (iq->tag) 479 pci_intr_disestablish(pa->pa_pc, iq->tag); 480 iq->tag = NULL; 481 } 482 483 if (sc->tag) 484 pci_intr_disestablish(pa->pa_pc, sc->tag); 485 sc->tag = NULL; 486 if (os->os_membase != 0) 487 bus_space_unmap(os->os_memt, os->os_memh, os->os_memsize); 488 os->os_membase = 0; 489 } 490 491 /********************************************************************* 492 * 493 * Initialize the hardware to a configuration as specified by the 494 * adapter structure. 495 * 496 **********************************************************************/ 497 void 498 igc_reset(struct igc_softc *sc) 499 { 500 struct igc_hw *hw = &sc->hw; 501 uint32_t pba; 502 uint16_t rx_buffer_size; 503 504 /* Let the firmware know the OS is in control */ 505 igc_get_hw_control(sc); 506 507 /* 508 * Packet Buffer Allocation (PBA) 509 * Writing PBA sets the receive portion of the buffer 510 * the remainder is used for the transmit buffer. 511 */ 512 pba = IGC_PBA_34K; 513 514 /* 515 * These parameters control the automatic generation (Tx) and 516 * response (Rx) to Ethernet PAUSE frames. 517 * - High water mark should allow for at least two frames to be 518 * received after sending an XOFF. 519 * - Low water mark works best when it is very near the high water mark. 520 * This allows the receiver to restart by sending XON when it has 521 * drained a bit. Here we use an arbitrary value of 1500 which will 522 * restart after one full frame is pulled from the buffer. There 523 * could be several smaller frames in the buffer and if so they will 524 * not trigger the XON until their total number reduces the buffer 525 * by 1500. 526 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 527 */ 528 rx_buffer_size = (pba & 0xffff) << 10; 529 hw->fc.high_water = rx_buffer_size - 530 roundup2(sc->hw.mac.max_frame_size, 1024); 531 /* 16-byte granularity */ 532 hw->fc.low_water = hw->fc.high_water - 16; 533 534 if (sc->fc) /* locally set flow control value? */ 535 hw->fc.requested_mode = sc->fc; 536 else 537 hw->fc.requested_mode = igc_fc_full; 538 539 hw->fc.pause_time = IGC_FC_PAUSE_TIME; 540 541 hw->fc.send_xon = true; 542 543 /* Issue a global reset */ 544 igc_reset_hw(hw); 545 IGC_WRITE_REG(hw, IGC_WUC, 0); 546 547 /* and a re-init */ 548 if (igc_init_hw(hw) < 0) { 549 printf(": Hardware Initialization Failed\n"); 550 return; 551 } 552 553 /* Setup DMA Coalescing */ 554 igc_init_dmac(sc, pba); 555 556 IGC_WRITE_REG(hw, IGC_VET, ETHERTYPE_VLAN); 557 igc_get_phy_info(hw); 558 igc_check_for_link(hw); 559 } 560 561 /********************************************************************* 562 * 563 * Initialize the DMA Coalescing feature 564 * 565 **********************************************************************/ 566 void 567 igc_init_dmac(struct igc_softc *sc, uint32_t pba) 568 { 569 struct igc_hw *hw = &sc->hw; 570 uint32_t dmac, reg = ~IGC_DMACR_DMAC_EN; 571 uint16_t hwm, max_frame_size; 572 int status; 573 574 max_frame_size = sc->hw.mac.max_frame_size; 575 576 if (sc->dmac == 0) { /* Disabling it */ 577 IGC_WRITE_REG(hw, IGC_DMACR, reg); 578 return; 579 } else 580 printf(": DMA Coalescing enabled\n"); 581 582 /* Set starting threshold */ 583 IGC_WRITE_REG(hw, IGC_DMCTXTH, 0); 584 585 hwm = 64 * pba - max_frame_size / 16; 586 if (hwm < 64 * (pba - 6)) 587 hwm = 64 * (pba - 6); 588 reg = IGC_READ_REG(hw, IGC_FCRTC); 589 reg &= ~IGC_FCRTC_RTH_COAL_MASK; 590 reg |= ((hwm << IGC_FCRTC_RTH_COAL_SHIFT) 591 & IGC_FCRTC_RTH_COAL_MASK); 592 IGC_WRITE_REG(hw, IGC_FCRTC, reg); 593 594 dmac = pba - max_frame_size / 512; 595 if (dmac < pba - 10) 596 dmac = pba - 10; 597 reg = IGC_READ_REG(hw, IGC_DMACR); 598 reg &= ~IGC_DMACR_DMACTHR_MASK; 599 reg |= ((dmac << IGC_DMACR_DMACTHR_SHIFT) 600 & IGC_DMACR_DMACTHR_MASK); 601 602 /* transition to L0x or L1 if available..*/ 603 reg |= (IGC_DMACR_DMAC_EN | IGC_DMACR_DMAC_LX_MASK); 604 605 /* Check if status is 2.5Gb backplane connection 606 * before configuration of watchdog timer, which is 607 * in msec values in 12.8usec intervals 608 * watchdog timer= msec values in 32usec intervals 609 * for non 2.5Gb connection 610 */ 611 status = IGC_READ_REG(hw, IGC_STATUS); 612 if ((status & IGC_STATUS_2P5_SKU) && 613 (!(status & IGC_STATUS_2P5_SKU_OVER))) 614 reg |= ((sc->dmac * 5) >> 6); 615 else 616 reg |= (sc->dmac >> 5); 617 618 IGC_WRITE_REG(hw, IGC_DMACR, reg); 619 620 IGC_WRITE_REG(hw, IGC_DMCRTRH, 0); 621 622 /* Set the interval before transition */ 623 reg = IGC_READ_REG(hw, IGC_DMCTLX); 624 reg |= IGC_DMCTLX_DCFLUSH_DIS; 625 626 /* 627 ** in 2.5Gb connection, TTLX unit is 0.4 usec 628 ** which is 0x4*2 = 0xA. But delay is still 4 usec 629 */ 630 status = IGC_READ_REG(hw, IGC_STATUS); 631 if ((status & IGC_STATUS_2P5_SKU) && 632 (!(status & IGC_STATUS_2P5_SKU_OVER))) 633 reg |= 0xA; 634 else 635 reg |= 0x4; 636 637 IGC_WRITE_REG(hw, IGC_DMCTLX, reg); 638 639 /* free space in tx packet buffer to wake from DMA coal */ 640 IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE - 641 (2 * max_frame_size)) >> 6); 642 643 /* make low power state decision controlled by DMA coal */ 644 reg = IGC_READ_REG(hw, IGC_PCIEMISC); 645 reg &= ~IGC_PCIEMISC_LX_DECISION; 646 IGC_WRITE_REG(hw, IGC_PCIEMISC, reg); 647 } 648 649 int 650 igc_allocate_msix(struct igc_softc *sc) 651 { 652 struct igc_osdep *os = &sc->osdep; 653 struct pci_attach_args *pa = &os->os_pa; 654 struct igc_queue *iq; 655 pci_intr_handle_t ih; 656 int i, error = 0; 657 658 for (i = 0, iq = sc->queues; i < sc->sc_nqueues; i++, iq++) { 659 if (pci_intr_map_msix(pa, i, &ih)) { 660 printf("%s: unable to map msi-x vector %d\n", 661 DEVNAME(sc), i); 662 error = ENOMEM; 663 goto fail; 664 } 665 666 iq->tag = pci_intr_establish_cpu(pa->pa_pc, ih, 667 IPL_NET | IPL_MPSAFE, intrmap_cpu(sc->sc_intrmap, i), 668 igc_intr_queue, iq, iq->name); 669 if (iq->tag == NULL) { 670 printf("%s: unable to establish interrupt %d\n", 671 DEVNAME(sc), i); 672 error = ENOMEM; 673 goto fail; 674 } 675 676 iq->msix = i; 677 iq->eims = 1 << i; 678 } 679 680 /* Now the link status/control last MSI-X vector. */ 681 if (pci_intr_map_msix(pa, i, &ih)) { 682 printf("%s: unable to map link vector\n", DEVNAME(sc)); 683 error = ENOMEM; 684 goto fail; 685 } 686 687 sc->tag = pci_intr_establish(pa->pa_pc, ih, IPL_NET | IPL_MPSAFE, 688 igc_intr_link, sc, sc->sc_dev.dv_xname); 689 if (sc->tag == NULL) { 690 printf("%s: unable to establish link interrupt\n", DEVNAME(sc)); 691 error = ENOMEM; 692 goto fail; 693 } 694 695 sc->linkvec = i; 696 printf(", %s, %d queue%s", pci_intr_string(pa->pa_pc, ih), 697 i, (i > 1) ? "s" : ""); 698 699 return 0; 700 fail: 701 for (iq = sc->queues; i > 0; i--, iq++) { 702 if (iq->tag == NULL) 703 continue; 704 pci_intr_disestablish(pa->pa_pc, iq->tag); 705 iq->tag = NULL; 706 } 707 708 return error; 709 } 710 711 void 712 igc_setup_msix(struct igc_softc *sc) 713 { 714 struct igc_osdep *os = &sc->osdep; 715 struct pci_attach_args *pa = &os->os_pa; 716 int nmsix; 717 718 nmsix = pci_intr_msix_count(pa); 719 if (nmsix <= 1) 720 printf(": not enough msi-x vectors\n"); 721 722 /* Give one vector to events. */ 723 nmsix--; 724 725 sc->sc_intrmap = intrmap_create(&sc->sc_dev, nmsix, IGC_MAX_VECTORS, 726 INTRMAP_POWEROF2); 727 sc->sc_nqueues = intrmap_count(sc->sc_intrmap); 728 } 729 730 int 731 igc_dma_malloc(struct igc_softc *sc, bus_size_t size, struct igc_dma_alloc *dma) 732 { 733 struct igc_osdep *os = &sc->osdep; 734 735 dma->dma_tag = os->os_pa.pa_dmat; 736 737 if (bus_dmamap_create(dma->dma_tag, size, 1, size, 0, BUS_DMA_NOWAIT, 738 &dma->dma_map)) 739 return 1; 740 if (bus_dmamem_alloc(dma->dma_tag, size, PAGE_SIZE, 0, &dma->dma_seg, 741 1, &dma->dma_nseg, BUS_DMA_NOWAIT)) 742 goto destroy; 743 if (bus_dmamem_map(dma->dma_tag, &dma->dma_seg, dma->dma_nseg, size, 744 &dma->dma_vaddr, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) 745 goto free; 746 if (bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size, 747 NULL, BUS_DMA_NOWAIT)) 748 goto unmap; 749 750 dma->dma_size = size; 751 752 return 0; 753 unmap: 754 bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size); 755 free: 756 bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg); 757 destroy: 758 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 759 dma->dma_map = NULL; 760 dma->dma_tag = NULL; 761 return 1; 762 } 763 764 void 765 igc_dma_free(struct igc_softc *sc, struct igc_dma_alloc *dma) 766 { 767 if (dma->dma_tag == NULL) 768 return; 769 770 if (dma->dma_map != NULL) { 771 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, 772 dma->dma_map->dm_mapsize, 773 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 774 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 775 bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, dma->dma_size); 776 bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg); 777 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 778 dma->dma_map = NULL; 779 } 780 } 781 782 /********************************************************************* 783 * 784 * Setup networking device structure and register an interface. 785 * 786 **********************************************************************/ 787 void 788 igc_setup_interface(struct igc_softc *sc) 789 { 790 struct ifnet *ifp = &sc->sc_ac.ac_if; 791 int i; 792 793 ifp->if_softc = sc; 794 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 795 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 796 ifp->if_xflags = IFXF_MPSAFE; 797 ifp->if_ioctl = igc_ioctl; 798 ifp->if_qstart = igc_start; 799 ifp->if_watchdog = igc_watchdog; 800 ifp->if_hardmtu = sc->hw.mac.max_frame_size - ETHER_HDR_LEN - 801 ETHER_CRC_LEN; 802 ifq_init_maxlen(&ifp->if_snd, sc->num_tx_desc - 1); 803 804 ifp->if_capabilities = IFCAP_VLAN_MTU; 805 806 #if NVLAN > 0 807 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 808 #endif 809 810 ifp->if_capabilities |= IFCAP_CSUM_IPv4; 811 ifp->if_capabilities |= IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 812 ifp->if_capabilities |= IFCAP_CSUM_TCPv6 | IFCAP_CSUM_UDPv6; 813 ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6; 814 815 /* Initialize ifmedia structures. */ 816 ifmedia_init(&sc->media, IFM_IMASK, igc_media_change, igc_media_status); 817 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 818 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 819 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 820 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 821 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 822 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 823 ifmedia_add(&sc->media, IFM_ETHER | IFM_2500_T, 0, NULL); 824 825 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 826 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 827 828 if_attach(ifp); 829 ether_ifattach(ifp); 830 831 if_attach_queues(ifp, sc->sc_nqueues); 832 if_attach_iqueues(ifp, sc->sc_nqueues); 833 for (i = 0; i < sc->sc_nqueues; i++) { 834 struct ifqueue *ifq = ifp->if_ifqs[i]; 835 struct ifiqueue *ifiq = ifp->if_iqs[i]; 836 struct tx_ring *txr = &sc->tx_rings[i]; 837 struct rx_ring *rxr = &sc->rx_rings[i]; 838 839 ifq->ifq_softc = txr; 840 txr->ifq = ifq; 841 842 ifiq->ifiq_softc = rxr; 843 rxr->ifiq = ifiq; 844 } 845 } 846 847 void 848 igc_init(void *arg) 849 { 850 struct igc_softc *sc = (struct igc_softc *)arg; 851 struct ifnet *ifp = &sc->sc_ac.ac_if; 852 struct rx_ring *rxr; 853 uint32_t ctrl = 0; 854 int i, s; 855 856 s = splnet(); 857 858 igc_stop(sc); 859 860 /* Get the latest mac address, user can use a LAA. */ 861 bcopy(sc->sc_ac.ac_enaddr, sc->hw.mac.addr, ETHER_ADDR_LEN); 862 863 /* Put the address into the receive address array. */ 864 igc_rar_set(&sc->hw, sc->hw.mac.addr, 0); 865 866 /* Initialize the hardware. */ 867 igc_reset(sc); 868 igc_update_link_status(sc); 869 870 /* Setup VLAN support, basic and offload if available. */ 871 IGC_WRITE_REG(&sc->hw, IGC_VET, ETHERTYPE_VLAN); 872 873 /* Prepare transmit descriptors and buffers. */ 874 if (igc_setup_transmit_structures(sc)) { 875 printf("%s: Could not setup transmit structures\n", 876 DEVNAME(sc)); 877 igc_stop(sc); 878 splx(s); 879 return; 880 } 881 igc_initialize_transmit_unit(sc); 882 883 sc->rx_mbuf_sz = MCLBYTES + ETHER_ALIGN; 884 /* Prepare receive descriptors and buffers. */ 885 if (igc_setup_receive_structures(sc)) { 886 printf("%s: Could not setup receive structures\n", 887 DEVNAME(sc)); 888 igc_stop(sc); 889 splx(s); 890 return; 891 } 892 igc_initialize_receive_unit(sc); 893 894 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) { 895 ctrl = IGC_READ_REG(&sc->hw, IGC_CTRL); 896 ctrl |= IGC_CTRL_VME; 897 IGC_WRITE_REG(&sc->hw, IGC_CTRL, ctrl); 898 } 899 900 /* Setup multicast table. */ 901 igc_iff(sc); 902 903 igc_clear_hw_cntrs_base_generic(&sc->hw); 904 905 igc_configure_queues(sc); 906 907 /* This clears any pending interrupts */ 908 IGC_READ_REG(&sc->hw, IGC_ICR); 909 IGC_WRITE_REG(&sc->hw, IGC_ICS, IGC_ICS_LSC); 910 911 /* The driver can now take control from firmware. */ 912 igc_get_hw_control(sc); 913 914 /* Set Energy Efficient Ethernet. */ 915 igc_set_eee_i225(&sc->hw, true, true, true); 916 917 for (i = 0; i < sc->sc_nqueues; i++) { 918 rxr = &sc->rx_rings[i]; 919 igc_rxfill(rxr); 920 if (if_rxr_inuse(&rxr->rx_ring) == 0) { 921 printf("%s: Unable to fill any rx descriptors\n", 922 DEVNAME(sc)); 923 igc_stop(sc); 924 splx(s); 925 } 926 IGC_WRITE_REG(&sc->hw, IGC_RDT(i), 927 (rxr->last_desc_filled + 1) % sc->num_rx_desc); 928 } 929 930 igc_enable_intr(sc); 931 932 ifp->if_flags |= IFF_RUNNING; 933 for (i = 0; i < sc->sc_nqueues; i++) 934 ifq_clr_oactive(ifp->if_ifqs[i]); 935 936 splx(s); 937 } 938 939 static inline int 940 igc_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, struct mbuf *m) 941 { 942 int error; 943 944 error = bus_dmamap_load_mbuf(dmat, map, m, 945 BUS_DMA_STREAMING | BUS_DMA_NOWAIT); 946 if (error != EFBIG) 947 return (error); 948 949 error = m_defrag(m, M_DONTWAIT); 950 if (error != 0) 951 return (error); 952 953 return (bus_dmamap_load_mbuf(dmat, map, m, 954 BUS_DMA_STREAMING | BUS_DMA_NOWAIT)); 955 } 956 957 void 958 igc_start(struct ifqueue *ifq) 959 { 960 struct ifnet *ifp = ifq->ifq_if; 961 struct igc_softc *sc = ifp->if_softc; 962 struct tx_ring *txr = ifq->ifq_softc; 963 union igc_adv_tx_desc *txdesc; 964 struct igc_tx_buf *txbuf; 965 bus_dmamap_t map; 966 struct mbuf *m; 967 unsigned int prod, free, last, i; 968 unsigned int mask; 969 uint32_t cmd_type_len; 970 uint32_t olinfo_status; 971 int post = 0; 972 #if NBPFILTER > 0 973 caddr_t if_bpf; 974 #endif 975 976 if (!sc->link_active) { 977 ifq_purge(ifq); 978 return; 979 } 980 981 prod = txr->next_avail_desc; 982 free = txr->next_to_clean; 983 if (free <= prod) 984 free += sc->num_tx_desc; 985 free -= prod; 986 987 bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0, 988 txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 989 990 mask = sc->num_tx_desc - 1; 991 992 for (;;) { 993 if (free <= IGC_MAX_SCATTER + 1) { 994 ifq_set_oactive(ifq); 995 break; 996 } 997 998 m = ifq_dequeue(ifq); 999 if (m == NULL) 1000 break; 1001 1002 txbuf = &txr->tx_buffers[prod]; 1003 map = txbuf->map; 1004 1005 if (igc_load_mbuf(txr->txdma.dma_tag, map, m) != 0) { 1006 ifq->ifq_errors++; 1007 m_freem(m); 1008 continue; 1009 } 1010 1011 olinfo_status = m->m_pkthdr.len << IGC_ADVTXD_PAYLEN_SHIFT; 1012 1013 bus_dmamap_sync(txr->txdma.dma_tag, map, 0, 1014 map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1015 1016 cmd_type_len = IGC_ADVTXD_DCMD_IFCS | IGC_ADVTXD_DTYP_DATA | 1017 IGC_ADVTXD_DCMD_DEXT; 1018 1019 if (igc_tx_ctx_setup(txr, m, prod, &cmd_type_len, 1020 &olinfo_status)) { 1021 /* Consume the first descriptor */ 1022 prod++; 1023 prod &= mask; 1024 free--; 1025 } 1026 1027 for (i = 0; i < map->dm_nsegs; i++) { 1028 txdesc = &txr->tx_base[prod]; 1029 1030 CLR(cmd_type_len, IGC_ADVTXD_DTALEN_MASK); 1031 cmd_type_len |= map->dm_segs[i].ds_len; 1032 if (i == map->dm_nsegs - 1) 1033 cmd_type_len |= IGC_ADVTXD_DCMD_EOP | 1034 IGC_ADVTXD_DCMD_RS; 1035 1036 htolem64(&txdesc->read.buffer_addr, 1037 map->dm_segs[i].ds_addr); 1038 htolem32(&txdesc->read.cmd_type_len, cmd_type_len); 1039 htolem32(&txdesc->read.olinfo_status, olinfo_status); 1040 1041 last = prod; 1042 1043 prod++; 1044 prod &= mask; 1045 } 1046 1047 txbuf->m_head = m; 1048 txbuf->eop_index = last; 1049 1050 #if NBPFILTER > 0 1051 if_bpf = ifp->if_bpf; 1052 if (if_bpf) 1053 bpf_mtap_ether(if_bpf, m, BPF_DIRECTION_OUT); 1054 #endif 1055 1056 free -= i; 1057 post = 1; 1058 } 1059 1060 bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0, 1061 txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1062 1063 if (post) { 1064 txr->next_avail_desc = prod; 1065 IGC_WRITE_REG(&sc->hw, IGC_TDT(txr->me), prod); 1066 } 1067 } 1068 1069 int 1070 igc_txeof(struct tx_ring *txr) 1071 { 1072 struct igc_softc *sc = txr->sc; 1073 struct ifqueue *ifq = txr->ifq; 1074 union igc_adv_tx_desc *txdesc; 1075 struct igc_tx_buf *txbuf; 1076 bus_dmamap_t map; 1077 unsigned int cons, prod, last; 1078 unsigned int mask; 1079 int done = 0; 1080 1081 prod = txr->next_avail_desc; 1082 cons = txr->next_to_clean; 1083 1084 if (cons == prod) 1085 return (0); 1086 1087 bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0, 1088 txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1089 1090 mask = sc->num_tx_desc - 1; 1091 1092 do { 1093 txbuf = &txr->tx_buffers[cons]; 1094 last = txbuf->eop_index; 1095 txdesc = &txr->tx_base[last]; 1096 1097 if (!(txdesc->wb.status & htole32(IGC_TXD_STAT_DD))) 1098 break; 1099 1100 map = txbuf->map; 1101 1102 bus_dmamap_sync(txr->txdma.dma_tag, map, 0, map->dm_mapsize, 1103 BUS_DMASYNC_POSTWRITE); 1104 bus_dmamap_unload(txr->txdma.dma_tag, map); 1105 m_freem(txbuf->m_head); 1106 1107 txbuf->m_head = NULL; 1108 txbuf->eop_index = -1; 1109 1110 cons = last + 1; 1111 cons &= mask; 1112 1113 done = 1; 1114 } while (cons != prod); 1115 1116 bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0, 1117 txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1118 1119 txr->next_to_clean = cons; 1120 1121 if (ifq_is_oactive(ifq)) 1122 ifq_restart(ifq); 1123 1124 return (done); 1125 } 1126 1127 /********************************************************************* 1128 * 1129 * This routine disables all traffic on the adapter by issuing a 1130 * global reset on the MAC. 1131 * 1132 **********************************************************************/ 1133 void 1134 igc_stop(struct igc_softc *sc) 1135 { 1136 struct ifnet *ifp = &sc->sc_ac.ac_if; 1137 int i; 1138 1139 /* Tell the stack that the interface is no longer active. */ 1140 ifp->if_flags &= ~IFF_RUNNING; 1141 1142 igc_disable_intr(sc); 1143 1144 igc_reset_hw(&sc->hw); 1145 IGC_WRITE_REG(&sc->hw, IGC_WUC, 0); 1146 1147 intr_barrier(sc->tag); 1148 for (i = 0; i < sc->sc_nqueues; i++) { 1149 struct ifqueue *ifq = ifp->if_ifqs[i]; 1150 ifq_barrier(ifq); 1151 ifq_clr_oactive(ifq); 1152 1153 if (sc->queues[i].tag != NULL) 1154 intr_barrier(sc->queues[i].tag); 1155 timeout_del(&sc->rx_rings[i].rx_refill); 1156 } 1157 1158 igc_free_transmit_structures(sc); 1159 igc_free_receive_structures(sc); 1160 1161 igc_update_link_status(sc); 1162 } 1163 1164 /********************************************************************* 1165 * Ioctl entry point 1166 * 1167 * igc_ioctl is called when the user wants to configure the 1168 * interface. 1169 * 1170 * return 0 on success, positive on failure 1171 **********************************************************************/ 1172 int 1173 igc_ioctl(struct ifnet * ifp, u_long cmd, caddr_t data) 1174 { 1175 struct igc_softc *sc = ifp->if_softc; 1176 struct ifreq *ifr = (struct ifreq *)data; 1177 int s, error = 0; 1178 1179 s = splnet(); 1180 1181 switch (cmd) { 1182 case SIOCSIFADDR: 1183 ifp->if_flags |= IFF_UP; 1184 if (!(ifp->if_flags & IFF_RUNNING)) 1185 igc_init(sc); 1186 break; 1187 case SIOCSIFFLAGS: 1188 if (ifp->if_flags & IFF_UP) { 1189 if (ifp->if_flags & IFF_RUNNING) 1190 error = ENETRESET; 1191 else 1192 igc_init(sc); 1193 } else { 1194 if (ifp->if_flags & IFF_RUNNING) 1195 igc_stop(sc); 1196 } 1197 break; 1198 case SIOCSIFMEDIA: 1199 case SIOCGIFMEDIA: 1200 error = ifmedia_ioctl(ifp, ifr, &sc->media, cmd); 1201 break; 1202 case SIOCGIFRXR: 1203 error = igc_rxrinfo(sc, (struct if_rxrinfo *)ifr->ifr_data); 1204 break; 1205 default: 1206 error = ether_ioctl(ifp, &sc->sc_ac, cmd, data); 1207 } 1208 1209 if (error == ENETRESET) { 1210 if (ifp->if_flags & IFF_RUNNING) { 1211 igc_disable_intr(sc); 1212 igc_iff(sc); 1213 igc_enable_intr(sc); 1214 } 1215 error = 0; 1216 } 1217 1218 splx(s); 1219 return error; 1220 } 1221 1222 int 1223 igc_rxrinfo(struct igc_softc *sc, struct if_rxrinfo *ifri) 1224 { 1225 struct if_rxring_info *ifr; 1226 struct rx_ring *rxr; 1227 int error, i, n = 0; 1228 1229 ifr = mallocarray(sc->sc_nqueues, sizeof(*ifr), M_DEVBUF, 1230 M_WAITOK | M_ZERO); 1231 1232 for (i = 0; i < sc->sc_nqueues; i++) { 1233 rxr = &sc->rx_rings[i]; 1234 ifr[n].ifr_size = MCLBYTES; 1235 snprintf(ifr[n].ifr_name, sizeof(ifr[n].ifr_name), "%d", i); 1236 ifr[n].ifr_info = rxr->rx_ring; 1237 n++; 1238 } 1239 1240 error = if_rxr_info_ioctl(ifri, sc->sc_nqueues, ifr); 1241 free(ifr, M_DEVBUF, sc->sc_nqueues * sizeof(*ifr)); 1242 1243 return error; 1244 } 1245 1246 int 1247 igc_rxfill(struct rx_ring *rxr) 1248 { 1249 struct igc_softc *sc = rxr->sc; 1250 int i, post = 0; 1251 u_int slots; 1252 1253 bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0, 1254 rxr->rxdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1255 1256 i = rxr->last_desc_filled; 1257 for (slots = if_rxr_get(&rxr->rx_ring, sc->num_rx_desc); slots > 0; 1258 slots--) { 1259 if (++i == sc->num_rx_desc) 1260 i = 0; 1261 1262 if (igc_get_buf(rxr, i) != 0) 1263 break; 1264 1265 rxr->last_desc_filled = i; 1266 post = 1; 1267 } 1268 1269 bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0, 1270 rxr->rxdma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1271 1272 if_rxr_put(&rxr->rx_ring, slots); 1273 1274 return post; 1275 } 1276 1277 void 1278 igc_rxrefill(void *xrxr) 1279 { 1280 struct rx_ring *rxr = xrxr; 1281 struct igc_softc *sc = rxr->sc; 1282 1283 if (igc_rxfill(rxr)) { 1284 IGC_WRITE_REG(&sc->hw, IGC_RDT(rxr->me), 1285 (rxr->last_desc_filled + 1) % sc->num_rx_desc); 1286 } 1287 else if (if_rxr_inuse(&rxr->rx_ring) == 0) 1288 timeout_add(&rxr->rx_refill, 1); 1289 } 1290 1291 /********************************************************************* 1292 * 1293 * This routine executes in interrupt context. It replenishes 1294 * the mbufs in the descriptor and sends data which has been 1295 * dma'ed into host memory to upper layer. 1296 * 1297 *********************************************************************/ 1298 int 1299 igc_rxeof(struct rx_ring *rxr) 1300 { 1301 struct igc_softc *sc = rxr->sc; 1302 struct ifnet *ifp = &sc->sc_ac.ac_if; 1303 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1304 struct mbuf *mp, *m; 1305 struct igc_rx_buf *rxbuf, *nxbuf; 1306 union igc_adv_rx_desc *rxdesc; 1307 uint32_t ptype, staterr = 0; 1308 uint16_t len, vtag; 1309 uint8_t eop = 0; 1310 int i, nextp; 1311 1312 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 1313 return 0; 1314 1315 i = rxr->next_to_check; 1316 while (if_rxr_inuse(&rxr->rx_ring) > 0) { 1317 uint32_t hash; 1318 uint16_t hashtype; 1319 1320 bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 1321 i * sizeof(union igc_adv_rx_desc), 1322 sizeof(union igc_adv_rx_desc), BUS_DMASYNC_POSTREAD); 1323 1324 rxdesc = &rxr->rx_base[i]; 1325 staterr = letoh32(rxdesc->wb.upper.status_error); 1326 if (!ISSET(staterr, IGC_RXD_STAT_DD)) { 1327 bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 1328 i * sizeof(union igc_adv_rx_desc), 1329 sizeof(union igc_adv_rx_desc), BUS_DMASYNC_PREREAD); 1330 break; 1331 } 1332 1333 /* Zero out the receive descriptors status. */ 1334 rxdesc->wb.upper.status_error = 0; 1335 rxbuf = &rxr->rx_buffers[i]; 1336 1337 /* Pull the mbuf off the ring. */ 1338 bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->map, 0, 1339 rxbuf->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1340 bus_dmamap_unload(rxr->rxdma.dma_tag, rxbuf->map); 1341 1342 mp = rxbuf->buf; 1343 len = letoh16(rxdesc->wb.upper.length); 1344 vtag = letoh16(rxdesc->wb.upper.vlan); 1345 eop = ((staterr & IGC_RXD_STAT_EOP) == IGC_RXD_STAT_EOP); 1346 ptype = letoh32(rxdesc->wb.lower.lo_dword.data) & 1347 IGC_PKTTYPE_MASK; 1348 hash = letoh32(rxdesc->wb.lower.hi_dword.rss); 1349 hashtype = le16toh(rxdesc->wb.lower.lo_dword.hs_rss.pkt_info) & 1350 IGC_RXDADV_RSSTYPE_MASK; 1351 1352 if (staterr & IGC_RXDEXT_STATERR_RXE) { 1353 if (rxbuf->fmp) { 1354 m_freem(rxbuf->fmp); 1355 rxbuf->fmp = NULL; 1356 } 1357 1358 m_freem(mp); 1359 rxbuf->buf = NULL; 1360 goto next_desc; 1361 } 1362 1363 if (mp == NULL) { 1364 panic("%s: igc_rxeof: NULL mbuf in slot %d " 1365 "(nrx %d, filled %d)", DEVNAME(sc), i, 1366 if_rxr_inuse(&rxr->rx_ring), rxr->last_desc_filled); 1367 } 1368 1369 if (!eop) { 1370 /* 1371 * Figure out the next descriptor of this frame. 1372 */ 1373 nextp = i + 1; 1374 if (nextp == sc->num_rx_desc) 1375 nextp = 0; 1376 nxbuf = &rxr->rx_buffers[nextp]; 1377 /* prefetch(nxbuf); */ 1378 } 1379 1380 mp->m_len = len; 1381 1382 m = rxbuf->fmp; 1383 rxbuf->buf = rxbuf->fmp = NULL; 1384 1385 if (m != NULL) 1386 m->m_pkthdr.len += mp->m_len; 1387 else { 1388 m = mp; 1389 m->m_pkthdr.len = mp->m_len; 1390 #if NVLAN > 0 1391 if (staterr & IGC_RXD_STAT_VP) { 1392 m->m_pkthdr.ether_vtag = vtag; 1393 m->m_flags |= M_VLANTAG; 1394 } 1395 #endif 1396 } 1397 1398 /* Pass the head pointer on */ 1399 if (eop == 0) { 1400 nxbuf->fmp = m; 1401 m = NULL; 1402 mp->m_next = nxbuf->buf; 1403 } else { 1404 igc_rx_checksum(staterr, m, ptype); 1405 1406 if (hashtype != IGC_RXDADV_RSSTYPE_NONE) { 1407 m->m_pkthdr.ph_flowid = hash; 1408 SET(m->m_pkthdr.csum_flags, M_FLOWID); 1409 } 1410 1411 ml_enqueue(&ml, m); 1412 } 1413 next_desc: 1414 if_rxr_put(&rxr->rx_ring, 1); 1415 bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 1416 i * sizeof(union igc_adv_rx_desc), 1417 sizeof(union igc_adv_rx_desc), BUS_DMASYNC_PREREAD); 1418 1419 /* Advance our pointers to the next descriptor. */ 1420 if (++i == sc->num_rx_desc) 1421 i = 0; 1422 } 1423 rxr->next_to_check = i; 1424 1425 if (ifiq_input(rxr->ifiq, &ml)) 1426 if_rxr_livelocked(&rxr->rx_ring); 1427 1428 if (!(staterr & IGC_RXD_STAT_DD)) 1429 return 0; 1430 1431 return 1; 1432 } 1433 1434 /********************************************************************* 1435 * 1436 * Verify that the hardware indicated that the checksum is valid. 1437 * Inform the stack about the status of checksum so that stack 1438 * doesn't spend time verifying the checksum. 1439 * 1440 *********************************************************************/ 1441 void 1442 igc_rx_checksum(uint32_t staterr, struct mbuf *m, uint32_t ptype) 1443 { 1444 uint16_t status = (uint16_t)staterr; 1445 uint8_t errors = (uint8_t)(staterr >> 24); 1446 1447 if (status & IGC_RXD_STAT_IPCS) { 1448 if (!(errors & IGC_RXD_ERR_IPE)) { 1449 /* IP Checksum Good */ 1450 m->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 1451 } else 1452 m->m_pkthdr.csum_flags = 0; 1453 } 1454 1455 if (status & (IGC_RXD_STAT_TCPCS | IGC_RXD_STAT_UDPCS)) { 1456 if (!(errors & IGC_RXD_ERR_TCPE)) 1457 m->m_pkthdr.csum_flags |= 1458 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1459 } 1460 } 1461 1462 void 1463 igc_watchdog(struct ifnet * ifp) 1464 { 1465 } 1466 1467 /********************************************************************* 1468 * 1469 * Media Ioctl callback 1470 * 1471 * This routine is called whenever the user queries the status of 1472 * the interface using ifconfig. 1473 * 1474 **********************************************************************/ 1475 void 1476 igc_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1477 { 1478 struct igc_softc *sc = ifp->if_softc; 1479 1480 igc_update_link_status(sc); 1481 1482 ifmr->ifm_status = IFM_AVALID; 1483 ifmr->ifm_active = IFM_ETHER; 1484 1485 if (!sc->link_active) { 1486 ifmr->ifm_active |= IFM_NONE; 1487 return; 1488 } 1489 1490 ifmr->ifm_status |= IFM_ACTIVE; 1491 1492 switch (sc->link_speed) { 1493 case 10: 1494 ifmr->ifm_active |= IFM_10_T; 1495 break; 1496 case 100: 1497 ifmr->ifm_active |= IFM_100_TX; 1498 break; 1499 case 1000: 1500 ifmr->ifm_active |= IFM_1000_T; 1501 break; 1502 case 2500: 1503 ifmr->ifm_active |= IFM_2500_T; 1504 break; 1505 } 1506 1507 if (sc->link_duplex == FULL_DUPLEX) 1508 ifmr->ifm_active |= IFM_FDX; 1509 else 1510 ifmr->ifm_active |= IFM_HDX; 1511 1512 switch (sc->hw.fc.current_mode) { 1513 case igc_fc_tx_pause: 1514 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 1515 break; 1516 case igc_fc_rx_pause: 1517 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 1518 break; 1519 case igc_fc_full: 1520 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE | 1521 IFM_ETH_TXPAUSE; 1522 break; 1523 default: 1524 ifmr->ifm_active &= ~(IFM_FLOW | IFM_ETH_RXPAUSE | 1525 IFM_ETH_TXPAUSE); 1526 break; 1527 } 1528 } 1529 1530 /********************************************************************* 1531 * 1532 * Media Ioctl callback 1533 * 1534 * This routine is called when the user changes speed/duplex using 1535 * media/mediopt option with ifconfig. 1536 * 1537 **********************************************************************/ 1538 int 1539 igc_media_change(struct ifnet *ifp) 1540 { 1541 struct igc_softc *sc = ifp->if_softc; 1542 struct ifmedia *ifm = &sc->media; 1543 1544 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1545 return (EINVAL); 1546 1547 sc->hw.mac.autoneg = DO_AUTO_NEG; 1548 1549 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1550 case IFM_AUTO: 1551 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1552 break; 1553 case IFM_2500_T: 1554 sc->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL; 1555 break; 1556 case IFM_1000_T: 1557 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1558 break; 1559 case IFM_100_TX: 1560 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1561 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; 1562 else 1563 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; 1564 break; 1565 case IFM_10_T: 1566 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1567 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; 1568 else 1569 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; 1570 break; 1571 default: 1572 return EINVAL; 1573 } 1574 1575 igc_init(sc); 1576 1577 return 0; 1578 } 1579 1580 void 1581 igc_iff(struct igc_softc *sc) 1582 { 1583 struct ifnet *ifp = &sc->sc_ac.ac_if; 1584 struct arpcom *ac = &sc->sc_ac; 1585 struct ether_multi *enm; 1586 struct ether_multistep step; 1587 uint32_t reg_rctl = 0; 1588 uint8_t *mta; 1589 int mcnt = 0; 1590 1591 mta = sc->mta; 1592 bzero(mta, sizeof(uint8_t) * ETHER_ADDR_LEN * 1593 MAX_NUM_MULTICAST_ADDRESSES); 1594 1595 reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL); 1596 reg_rctl &= ~(IGC_RCTL_UPE | IGC_RCTL_MPE); 1597 ifp->if_flags &= ~IFF_ALLMULTI; 1598 1599 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0 || 1600 ac->ac_multicnt > MAX_NUM_MULTICAST_ADDRESSES) { 1601 ifp->if_flags |= IFF_ALLMULTI; 1602 reg_rctl |= IGC_RCTL_MPE; 1603 if (ifp->if_flags & IFF_PROMISC) 1604 reg_rctl |= IGC_RCTL_UPE; 1605 } else { 1606 ETHER_FIRST_MULTI(step, ac, enm); 1607 while (enm != NULL) { 1608 bcopy(enm->enm_addrlo, 1609 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1610 mcnt++; 1611 1612 ETHER_NEXT_MULTI(step, enm); 1613 } 1614 1615 igc_update_mc_addr_list(&sc->hw, mta, mcnt); 1616 } 1617 1618 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl); 1619 } 1620 1621 void 1622 igc_update_link_status(struct igc_softc *sc) 1623 { 1624 struct ifnet *ifp = &sc->sc_ac.ac_if; 1625 struct igc_hw *hw = &sc->hw; 1626 int link_state; 1627 1628 if (hw->mac.get_link_status == true) 1629 igc_check_for_link(hw); 1630 1631 if (IGC_READ_REG(&sc->hw, IGC_STATUS) & IGC_STATUS_LU) { 1632 if (sc->link_active == 0) { 1633 igc_get_speed_and_duplex(hw, &sc->link_speed, 1634 &sc->link_duplex); 1635 sc->link_active = 1; 1636 ifp->if_baudrate = IF_Mbps(sc->link_speed); 1637 } 1638 link_state = (sc->link_duplex == FULL_DUPLEX) ? 1639 LINK_STATE_FULL_DUPLEX : LINK_STATE_HALF_DUPLEX; 1640 } else { 1641 if (sc->link_active == 1) { 1642 ifp->if_baudrate = sc->link_speed = 0; 1643 sc->link_duplex = 0; 1644 sc->link_active = 0; 1645 } 1646 link_state = LINK_STATE_DOWN; 1647 } 1648 if (ifp->if_link_state != link_state) { 1649 ifp->if_link_state = link_state; 1650 if_link_state_change(ifp); 1651 } 1652 } 1653 1654 /********************************************************************* 1655 * 1656 * Get a buffer from system mbuf buffer pool. 1657 * 1658 **********************************************************************/ 1659 int 1660 igc_get_buf(struct rx_ring *rxr, int i) 1661 { 1662 struct igc_softc *sc = rxr->sc; 1663 struct igc_rx_buf *rxbuf; 1664 struct mbuf *m; 1665 union igc_adv_rx_desc *rxdesc; 1666 int error; 1667 1668 rxbuf = &rxr->rx_buffers[i]; 1669 rxdesc = &rxr->rx_base[i]; 1670 if (rxbuf->buf) { 1671 printf("%s: slot %d already has an mbuf\n", DEVNAME(sc), i); 1672 return ENOBUFS; 1673 } 1674 1675 m = MCLGETL(NULL, M_DONTWAIT, sc->rx_mbuf_sz); 1676 if (!m) 1677 return ENOBUFS; 1678 1679 m->m_data += (m->m_ext.ext_size - sc->rx_mbuf_sz); 1680 m->m_len = m->m_pkthdr.len = sc->rx_mbuf_sz; 1681 1682 error = bus_dmamap_load_mbuf(rxr->rxdma.dma_tag, rxbuf->map, m, 1683 BUS_DMA_NOWAIT); 1684 if (error) { 1685 m_freem(m); 1686 return error; 1687 } 1688 1689 bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->map, 0, 1690 rxbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1691 rxbuf->buf = m; 1692 1693 rxdesc->read.pkt_addr = htole64(rxbuf->map->dm_segs[0].ds_addr); 1694 1695 return 0; 1696 } 1697 1698 void 1699 igc_configure_queues(struct igc_softc *sc) 1700 { 1701 struct igc_hw *hw = &sc->hw; 1702 struct igc_queue *iq = sc->queues; 1703 uint32_t ivar, newitr = 0; 1704 int i; 1705 1706 /* First turn on RSS capability */ 1707 IGC_WRITE_REG(hw, IGC_GPIE, IGC_GPIE_MSIX_MODE | IGC_GPIE_EIAME | 1708 IGC_GPIE_PBA | IGC_GPIE_NSICR); 1709 1710 /* Set the starting interrupt rate */ 1711 newitr = (4000000 / MAX_INTS_PER_SEC) & 0x7FFC; 1712 1713 newitr |= IGC_EITR_CNT_IGNR; 1714 1715 /* Turn on MSI-X */ 1716 for (i = 0; i < sc->sc_nqueues; i++, iq++) { 1717 /* RX entries */ 1718 igc_set_queues(sc, i, iq->msix, 0); 1719 /* TX entries */ 1720 igc_set_queues(sc, i, iq->msix, 1); 1721 sc->msix_queuesmask |= iq->eims; 1722 IGC_WRITE_REG(hw, IGC_EITR(iq->msix), newitr); 1723 } 1724 1725 /* And for the link interrupt */ 1726 ivar = (sc->linkvec | IGC_IVAR_VALID) << 8; 1727 sc->msix_linkmask = 1 << sc->linkvec; 1728 IGC_WRITE_REG(hw, IGC_IVAR_MISC, ivar); 1729 } 1730 1731 void 1732 igc_set_queues(struct igc_softc *sc, uint32_t entry, uint32_t vector, int type) 1733 { 1734 struct igc_hw *hw = &sc->hw; 1735 uint32_t ivar, index; 1736 1737 index = entry >> 1; 1738 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1739 if (type) { 1740 if (entry & 1) { 1741 ivar &= 0x00FFFFFF; 1742 ivar |= (vector | IGC_IVAR_VALID) << 24; 1743 } else { 1744 ivar &= 0xFFFF00FF; 1745 ivar |= (vector | IGC_IVAR_VALID) << 8; 1746 } 1747 } else { 1748 if (entry & 1) { 1749 ivar &= 0xFF00FFFF; 1750 ivar |= (vector | IGC_IVAR_VALID) << 16; 1751 } else { 1752 ivar &= 0xFFFFFF00; 1753 ivar |= vector | IGC_IVAR_VALID; 1754 } 1755 } 1756 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1757 } 1758 1759 void 1760 igc_enable_queue(struct igc_softc *sc, uint32_t eims) 1761 { 1762 IGC_WRITE_REG(&sc->hw, IGC_EIMS, eims); 1763 } 1764 1765 void 1766 igc_enable_intr(struct igc_softc *sc) 1767 { 1768 struct igc_hw *hw = &sc->hw; 1769 uint32_t mask; 1770 1771 mask = (sc->msix_queuesmask | sc->msix_linkmask); 1772 IGC_WRITE_REG(hw, IGC_EIAC, mask); 1773 IGC_WRITE_REG(hw, IGC_EIAM, mask); 1774 IGC_WRITE_REG(hw, IGC_EIMS, mask); 1775 IGC_WRITE_REG(hw, IGC_IMS, IGC_IMS_LSC); 1776 IGC_WRITE_FLUSH(hw); 1777 } 1778 1779 void 1780 igc_disable_intr(struct igc_softc *sc) 1781 { 1782 struct igc_hw *hw = &sc->hw; 1783 1784 IGC_WRITE_REG(hw, IGC_EIMC, 0xffffffff); 1785 IGC_WRITE_REG(hw, IGC_EIAC, 0); 1786 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 1787 IGC_WRITE_FLUSH(hw); 1788 } 1789 1790 int 1791 igc_intr_link(void *arg) 1792 { 1793 struct igc_softc *sc = (struct igc_softc *)arg; 1794 uint32_t reg_icr = IGC_READ_REG(&sc->hw, IGC_ICR); 1795 1796 if (reg_icr & IGC_ICR_LSC) { 1797 KERNEL_LOCK(); 1798 sc->hw.mac.get_link_status = true; 1799 igc_update_link_status(sc); 1800 KERNEL_UNLOCK(); 1801 } 1802 1803 IGC_WRITE_REG(&sc->hw, IGC_IMS, IGC_IMS_LSC); 1804 IGC_WRITE_REG(&sc->hw, IGC_EIMS, sc->msix_linkmask); 1805 1806 return 1; 1807 } 1808 1809 int 1810 igc_intr_queue(void *arg) 1811 { 1812 struct igc_queue *iq = arg; 1813 struct igc_softc *sc = iq->sc; 1814 struct ifnet *ifp = &sc->sc_ac.ac_if; 1815 struct rx_ring *rxr = iq->rxr; 1816 struct tx_ring *txr = iq->txr; 1817 1818 if (ifp->if_flags & IFF_RUNNING) { 1819 igc_txeof(txr); 1820 igc_rxeof(rxr); 1821 igc_rxrefill(rxr); 1822 } 1823 1824 igc_enable_queue(sc, iq->eims); 1825 1826 return 1; 1827 } 1828 1829 /********************************************************************* 1830 * 1831 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1832 * the information needed to transmit a packet on the wire. 1833 * 1834 **********************************************************************/ 1835 int 1836 igc_allocate_transmit_buffers(struct tx_ring *txr) 1837 { 1838 struct igc_softc *sc = txr->sc; 1839 struct igc_tx_buf *txbuf; 1840 int error, i; 1841 1842 txr->tx_buffers = mallocarray(sc->num_tx_desc, 1843 sizeof(struct igc_tx_buf), M_DEVBUF, M_NOWAIT | M_ZERO); 1844 if (txr->tx_buffers == NULL) { 1845 printf("%s: Unable to allocate tx_buffer memory\n", 1846 DEVNAME(sc)); 1847 error = ENOMEM; 1848 goto fail; 1849 } 1850 txr->txtag = txr->txdma.dma_tag; 1851 1852 /* Create the descriptor buffer dma maps. */ 1853 for (i = 0; i < sc->num_tx_desc; i++) { 1854 txbuf = &txr->tx_buffers[i]; 1855 error = bus_dmamap_create(txr->txdma.dma_tag, IGC_TSO_SIZE, 1856 IGC_MAX_SCATTER, PAGE_SIZE, 0, BUS_DMA_NOWAIT, &txbuf->map); 1857 if (error != 0) { 1858 printf("%s: Unable to create TX DMA map\n", 1859 DEVNAME(sc)); 1860 goto fail; 1861 } 1862 } 1863 1864 return 0; 1865 fail: 1866 return error; 1867 } 1868 1869 1870 /********************************************************************* 1871 * 1872 * Allocate and initialize transmit structures. 1873 * 1874 **********************************************************************/ 1875 int 1876 igc_setup_transmit_structures(struct igc_softc *sc) 1877 { 1878 struct tx_ring *txr = sc->tx_rings; 1879 int i; 1880 1881 for (i = 0; i < sc->sc_nqueues; i++, txr++) { 1882 if (igc_setup_transmit_ring(txr)) 1883 goto fail; 1884 } 1885 1886 return 0; 1887 fail: 1888 igc_free_transmit_structures(sc); 1889 return ENOBUFS; 1890 } 1891 1892 /********************************************************************* 1893 * 1894 * Initialize a transmit ring. 1895 * 1896 **********************************************************************/ 1897 int 1898 igc_setup_transmit_ring(struct tx_ring *txr) 1899 { 1900 struct igc_softc *sc = txr->sc; 1901 1902 /* Now allocate transmit buffers for the ring. */ 1903 if (igc_allocate_transmit_buffers(txr)) 1904 return ENOMEM; 1905 1906 /* Clear the old ring contents */ 1907 bzero((void *)txr->tx_base, 1908 (sizeof(union igc_adv_tx_desc)) * sc->num_tx_desc); 1909 1910 /* Reset indices. */ 1911 txr->next_avail_desc = 0; 1912 txr->next_to_clean = 0; 1913 1914 bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0, 1915 txr->txdma.dma_map->dm_mapsize, 1916 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1917 1918 return 0; 1919 } 1920 1921 /********************************************************************* 1922 * 1923 * Enable transmit unit. 1924 * 1925 **********************************************************************/ 1926 void 1927 igc_initialize_transmit_unit(struct igc_softc *sc) 1928 { 1929 struct ifnet *ifp = &sc->sc_ac.ac_if; 1930 struct tx_ring *txr; 1931 struct igc_hw *hw = &sc->hw; 1932 uint64_t bus_addr; 1933 uint32_t tctl, txdctl = 0; 1934 int i; 1935 1936 /* Setup the Base and Length of the TX descriptor ring. */ 1937 for (i = 0; i < sc->sc_nqueues; i++) { 1938 txr = &sc->tx_rings[i]; 1939 1940 bus_addr = txr->txdma.dma_map->dm_segs[0].ds_addr; 1941 1942 /* Base and len of TX ring */ 1943 IGC_WRITE_REG(hw, IGC_TDLEN(i), 1944 sc->num_tx_desc * sizeof(union igc_adv_tx_desc)); 1945 IGC_WRITE_REG(hw, IGC_TDBAH(i), (uint32_t)(bus_addr >> 32)); 1946 IGC_WRITE_REG(hw, IGC_TDBAL(i), (uint32_t)bus_addr); 1947 1948 /* Init the HEAD/TAIL indices */ 1949 IGC_WRITE_REG(hw, IGC_TDT(i), 0); 1950 IGC_WRITE_REG(hw, IGC_TDH(i), 0); 1951 1952 txr->watchdog_timer = 0; 1953 1954 txdctl = 0; /* Clear txdctl */ 1955 txdctl |= 0x1f; /* PTHRESH */ 1956 txdctl |= 1 << 8; /* HTHRESH */ 1957 txdctl |= 1 << 16; /* WTHRESH */ 1958 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 1959 txdctl |= IGC_TXDCTL_GRAN; 1960 txdctl |= 1 << 25; /* LWTHRESH */ 1961 1962 IGC_WRITE_REG(hw, IGC_TXDCTL(i), txdctl); 1963 } 1964 ifp->if_timer = 0; 1965 1966 /* Program the Transmit Control Register */ 1967 tctl = IGC_READ_REG(&sc->hw, IGC_TCTL); 1968 tctl &= ~IGC_TCTL_CT; 1969 tctl |= (IGC_TCTL_PSP | IGC_TCTL_RTLC | IGC_TCTL_EN | 1970 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT)); 1971 1972 /* This write will effectively turn on the transmit unit. */ 1973 IGC_WRITE_REG(&sc->hw, IGC_TCTL, tctl); 1974 } 1975 1976 /********************************************************************* 1977 * 1978 * Free all transmit rings. 1979 * 1980 **********************************************************************/ 1981 void 1982 igc_free_transmit_structures(struct igc_softc *sc) 1983 { 1984 struct tx_ring *txr = sc->tx_rings; 1985 int i; 1986 1987 for (i = 0; i < sc->sc_nqueues; i++, txr++) 1988 igc_free_transmit_buffers(txr); 1989 } 1990 1991 /********************************************************************* 1992 * 1993 * Free transmit ring related data structures. 1994 * 1995 **********************************************************************/ 1996 void 1997 igc_free_transmit_buffers(struct tx_ring *txr) 1998 { 1999 struct igc_softc *sc = txr->sc; 2000 struct igc_tx_buf *txbuf; 2001 int i; 2002 2003 if (txr->tx_buffers == NULL) 2004 return; 2005 2006 txbuf = txr->tx_buffers; 2007 for (i = 0; i < sc->num_tx_desc; i++, txbuf++) { 2008 if (txbuf->map != NULL && txbuf->map->dm_nsegs > 0) { 2009 bus_dmamap_sync(txr->txdma.dma_tag, txbuf->map, 2010 0, txbuf->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2011 bus_dmamap_unload(txr->txdma.dma_tag, txbuf->map); 2012 } 2013 if (txbuf->m_head != NULL) { 2014 m_freem(txbuf->m_head); 2015 txbuf->m_head = NULL; 2016 } 2017 if (txbuf->map != NULL) { 2018 bus_dmamap_destroy(txr->txdma.dma_tag, txbuf->map); 2019 txbuf->map = NULL; 2020 } 2021 } 2022 2023 if (txr->tx_buffers != NULL) 2024 free(txr->tx_buffers, M_DEVBUF, 2025 sc->num_tx_desc * sizeof(struct igc_tx_buf)); 2026 txr->tx_buffers = NULL; 2027 txr->txtag = NULL; 2028 } 2029 2030 2031 /********************************************************************* 2032 * 2033 * Advanced Context Descriptor setup for VLAN, CSUM or TSO 2034 * 2035 **********************************************************************/ 2036 2037 int 2038 igc_tx_ctx_setup(struct tx_ring *txr, struct mbuf *mp, int prod, 2039 uint32_t *cmd_type_len, uint32_t *olinfo_status) 2040 { 2041 struct ether_extracted ext; 2042 struct igc_adv_tx_context_desc *txdesc; 2043 uint32_t mss_l4len_idx = 0; 2044 uint32_t type_tucmd_mlhl = 0; 2045 uint32_t vlan_macip_lens = 0; 2046 int off = 0; 2047 2048 /* 2049 * In advanced descriptors the vlan tag must 2050 * be placed into the context descriptor. Hence 2051 * we need to make one even if not doing offloads. 2052 */ 2053 #if NVLAN > 0 2054 if (ISSET(mp->m_flags, M_VLANTAG)) { 2055 uint32_t vtag = mp->m_pkthdr.ether_vtag; 2056 vlan_macip_lens |= (vtag << IGC_ADVTXD_VLAN_SHIFT); 2057 *cmd_type_len |= IGC_ADVTXD_DCMD_VLE; 2058 off = 1; 2059 } 2060 #endif 2061 2062 ether_extract_headers(mp, &ext); 2063 2064 vlan_macip_lens |= (sizeof(*ext.eh) << IGC_ADVTXD_MACLEN_SHIFT); 2065 2066 if (ext.ip4) { 2067 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV4; 2068 if (ISSET(mp->m_pkthdr.csum_flags, M_IPV4_CSUM_OUT)) { 2069 *olinfo_status |= IGC_TXD_POPTS_IXSM << 8; 2070 off = 1; 2071 } 2072 #ifdef INET6 2073 } else if (ext.ip6) { 2074 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV6; 2075 #endif 2076 } 2077 2078 vlan_macip_lens |= ext.iphlen; 2079 type_tucmd_mlhl |= IGC_ADVTXD_DCMD_DEXT | IGC_ADVTXD_DTYP_CTXT; 2080 2081 if (ext.tcp) { 2082 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_TCP; 2083 if (ISSET(mp->m_pkthdr.csum_flags, M_TCP_CSUM_OUT)) { 2084 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8; 2085 off = 1; 2086 } 2087 } else if (ext.udp) { 2088 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_UDP; 2089 if (ISSET(mp->m_pkthdr.csum_flags, M_UDP_CSUM_OUT)) { 2090 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8; 2091 off = 1; 2092 } 2093 } 2094 2095 if (ISSET(mp->m_pkthdr.csum_flags, M_TCP_TSO)) { 2096 if (ext.tcp) { 2097 uint32_t hdrlen, thlen, paylen, outlen; 2098 2099 thlen = ext.tcphlen; 2100 2101 outlen = mp->m_pkthdr.ph_mss; 2102 mss_l4len_idx |= outlen << IGC_ADVTXD_MSS_SHIFT; 2103 mss_l4len_idx |= thlen << IGC_ADVTXD_L4LEN_SHIFT; 2104 2105 hdrlen = sizeof(*ext.eh) + ext.iphlen + thlen; 2106 paylen = mp->m_pkthdr.len - hdrlen; 2107 CLR(*olinfo_status, IGC_ADVTXD_PAYLEN_MASK); 2108 *olinfo_status |= paylen << IGC_ADVTXD_PAYLEN_SHIFT; 2109 2110 *cmd_type_len |= IGC_ADVTXD_DCMD_TSE; 2111 off = 1; 2112 2113 tcpstat_add(tcps_outpkttso, 2114 (paylen + outlen - 1) / outlen); 2115 } else 2116 tcpstat_inc(tcps_outbadtso); 2117 } 2118 2119 if (off == 0) 2120 return 0; 2121 2122 /* Now ready a context descriptor */ 2123 txdesc = (struct igc_adv_tx_context_desc *)&txr->tx_base[prod]; 2124 2125 /* Now copy bits into descriptor */ 2126 htolem32(&txdesc->vlan_macip_lens, vlan_macip_lens); 2127 htolem32(&txdesc->type_tucmd_mlhl, type_tucmd_mlhl); 2128 htolem32(&txdesc->seqnum_seed, 0); 2129 htolem32(&txdesc->mss_l4len_idx, mss_l4len_idx); 2130 2131 return 1; 2132 } 2133 2134 /********************************************************************* 2135 * 2136 * Allocate memory for rx_buffer structures. Since we use one 2137 * rx_buffer per received packet, the maximum number of rx_buffer's 2138 * that we'll need is equal to the number of receive descriptors 2139 * that we've allocated. 2140 * 2141 **********************************************************************/ 2142 int 2143 igc_allocate_receive_buffers(struct rx_ring *rxr) 2144 { 2145 struct igc_softc *sc = rxr->sc; 2146 struct igc_rx_buf *rxbuf; 2147 int i, error; 2148 2149 rxr->rx_buffers = mallocarray(sc->num_rx_desc, 2150 sizeof(struct igc_rx_buf), M_DEVBUF, M_NOWAIT | M_ZERO); 2151 if (rxr->rx_buffers == NULL) { 2152 printf("%s: Unable to allocate rx_buffer memory\n", 2153 DEVNAME(sc)); 2154 error = ENOMEM; 2155 goto fail; 2156 } 2157 2158 rxbuf = rxr->rx_buffers; 2159 for (i = 0; i < sc->num_rx_desc; i++, rxbuf++) { 2160 error = bus_dmamap_create(rxr->rxdma.dma_tag, 2161 MAX_JUMBO_FRAME_SIZE, 1, MAX_JUMBO_FRAME_SIZE, 0, 2162 BUS_DMA_NOWAIT, &rxbuf->map); 2163 if (error) { 2164 printf("%s: Unable to create RX DMA map\n", 2165 DEVNAME(sc)); 2166 goto fail; 2167 } 2168 } 2169 bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0, 2170 rxr->rxdma.dma_map->dm_mapsize, 2171 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2172 2173 return 0; 2174 fail: 2175 return error; 2176 } 2177 2178 /********************************************************************* 2179 * 2180 * Allocate and initialize receive structures. 2181 * 2182 **********************************************************************/ 2183 int 2184 igc_setup_receive_structures(struct igc_softc *sc) 2185 { 2186 struct rx_ring *rxr = sc->rx_rings; 2187 int i; 2188 2189 for (i = 0; i < sc->sc_nqueues; i++, rxr++) { 2190 if (igc_setup_receive_ring(rxr)) 2191 goto fail; 2192 } 2193 2194 return 0; 2195 fail: 2196 igc_free_receive_structures(sc); 2197 return ENOBUFS; 2198 } 2199 2200 /********************************************************************* 2201 * 2202 * Initialize a receive ring and its buffers. 2203 * 2204 **********************************************************************/ 2205 int 2206 igc_setup_receive_ring(struct rx_ring *rxr) 2207 { 2208 struct igc_softc *sc = rxr->sc; 2209 struct ifnet *ifp = &sc->sc_ac.ac_if; 2210 int rsize; 2211 2212 rsize = roundup2(sc->num_rx_desc * sizeof(union igc_adv_rx_desc), 2213 IGC_DBA_ALIGN); 2214 2215 /* Clear the ring contents. */ 2216 bzero((void *)rxr->rx_base, rsize); 2217 2218 if (igc_allocate_receive_buffers(rxr)) 2219 return ENOMEM; 2220 2221 /* Setup our descriptor indices. */ 2222 rxr->next_to_check = 0; 2223 rxr->last_desc_filled = sc->num_rx_desc - 1; 2224 2225 if_rxr_init(&rxr->rx_ring, 2 * ((ifp->if_hardmtu / MCLBYTES) + 1), 2226 sc->num_rx_desc - 1); 2227 2228 return 0; 2229 } 2230 2231 /********************************************************************* 2232 * 2233 * Enable receive unit. 2234 * 2235 **********************************************************************/ 2236 #define BSIZEPKT_ROUNDUP ((1 << IGC_SRRCTL_BSIZEPKT_SHIFT) - 1) 2237 2238 void 2239 igc_initialize_receive_unit(struct igc_softc *sc) 2240 { 2241 struct rx_ring *rxr = sc->rx_rings; 2242 struct igc_hw *hw = &sc->hw; 2243 uint32_t rctl, rxcsum, srrctl = 0; 2244 int i; 2245 2246 /* 2247 * Make sure receives are disabled while setting 2248 * up the descriptor ring. 2249 */ 2250 rctl = IGC_READ_REG(hw, IGC_RCTL); 2251 IGC_WRITE_REG(hw, IGC_RCTL, rctl & ~IGC_RCTL_EN); 2252 2253 /* Setup the Receive Control Register */ 2254 rctl &= ~(3 << IGC_RCTL_MO_SHIFT); 2255 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | IGC_RCTL_LBM_NO | 2256 IGC_RCTL_RDMTS_HALF | (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 2257 2258 /* Do not store bad packets */ 2259 rctl &= ~IGC_RCTL_SBP; 2260 2261 /* Enable Long Packet receive */ 2262 if (sc->hw.mac.max_frame_size != ETHER_MAX_LEN) 2263 rctl |= IGC_RCTL_LPE; 2264 2265 /* Strip the CRC */ 2266 rctl |= IGC_RCTL_SECRC; 2267 2268 /* 2269 * Set the interrupt throttling rate. Value is calculated 2270 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2271 */ 2272 IGC_WRITE_REG(hw, IGC_ITR, DEFAULT_ITR); 2273 2274 rxcsum = IGC_READ_REG(hw, IGC_RXCSUM); 2275 rxcsum &= ~IGC_RXCSUM_PCSD; 2276 2277 if (sc->sc_nqueues > 1) 2278 rxcsum |= IGC_RXCSUM_PCSD; 2279 2280 IGC_WRITE_REG(hw, IGC_RXCSUM, rxcsum); 2281 2282 if (sc->sc_nqueues > 1) 2283 igc_initialize_rss_mapping(sc); 2284 2285 /* Set maximum packet buffer len */ 2286 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 2287 IGC_SRRCTL_BSIZEPKT_SHIFT; 2288 /* srrctl above overrides this but set the register to a sane value */ 2289 rctl |= IGC_RCTL_SZ_2048; 2290 2291 /* 2292 * If TX flow control is disabled and there's > 1 queue defined, 2293 * enable DROP. 2294 * 2295 * This drops frames rather than hanging the RX MAC for all queues. 2296 */ 2297 if ((sc->sc_nqueues > 1) && (sc->fc == igc_fc_none || 2298 sc->fc == igc_fc_rx_pause)) { 2299 srrctl |= IGC_SRRCTL_DROP_EN; 2300 } 2301 2302 /* Setup the Base and Length of the RX descriptor rings. */ 2303 for (i = 0; i < sc->sc_nqueues; i++, rxr++) { 2304 IGC_WRITE_REG(hw, IGC_RXDCTL(i), 0); 2305 uint64_t bus_addr = rxr->rxdma.dma_map->dm_segs[0].ds_addr; 2306 uint32_t rxdctl; 2307 2308 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF; 2309 2310 IGC_WRITE_REG(hw, IGC_RDLEN(i), 2311 sc->num_rx_desc * sizeof(union igc_adv_rx_desc)); 2312 IGC_WRITE_REG(hw, IGC_RDBAH(i), (uint32_t)(bus_addr >> 32)); 2313 IGC_WRITE_REG(hw, IGC_RDBAL(i), (uint32_t)bus_addr); 2314 IGC_WRITE_REG(hw, IGC_SRRCTL(i), srrctl); 2315 2316 /* Setup the Head and Tail Descriptor Pointers */ 2317 IGC_WRITE_REG(hw, IGC_RDH(i), 0); 2318 IGC_WRITE_REG(hw, IGC_RDT(i), 0); 2319 2320 /* Enable this Queue */ 2321 rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i)); 2322 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE; 2323 rxdctl &= 0xFFF00000; 2324 rxdctl |= IGC_RX_PTHRESH; 2325 rxdctl |= IGC_RX_HTHRESH << 8; 2326 rxdctl |= IGC_RX_WTHRESH << 16; 2327 IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl); 2328 } 2329 2330 /* Make sure VLAN Filters are off */ 2331 rctl &= ~IGC_RCTL_VFE; 2332 2333 /* Write out the settings */ 2334 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 2335 } 2336 2337 /********************************************************************* 2338 * 2339 * Free all receive rings. 2340 * 2341 **********************************************************************/ 2342 void 2343 igc_free_receive_structures(struct igc_softc *sc) 2344 { 2345 struct rx_ring *rxr; 2346 int i; 2347 2348 for (i = 0, rxr = sc->rx_rings; i < sc->sc_nqueues; i++, rxr++) 2349 if_rxr_init(&rxr->rx_ring, 0, 0); 2350 2351 for (i = 0, rxr = sc->rx_rings; i < sc->sc_nqueues; i++, rxr++) 2352 igc_free_receive_buffers(rxr); 2353 } 2354 2355 /********************************************************************* 2356 * 2357 * Free receive ring data structures 2358 * 2359 **********************************************************************/ 2360 void 2361 igc_free_receive_buffers(struct rx_ring *rxr) 2362 { 2363 struct igc_softc *sc = rxr->sc; 2364 struct igc_rx_buf *rxbuf; 2365 int i; 2366 2367 if (rxr->rx_buffers != NULL) { 2368 for (i = 0; i < sc->num_rx_desc; i++) { 2369 rxbuf = &rxr->rx_buffers[i]; 2370 if (rxbuf->buf != NULL) { 2371 bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->map, 2372 0, rxbuf->map->dm_mapsize, 2373 BUS_DMASYNC_POSTREAD); 2374 bus_dmamap_unload(rxr->rxdma.dma_tag, 2375 rxbuf->map); 2376 m_freem(rxbuf->buf); 2377 rxbuf->buf = NULL; 2378 } 2379 bus_dmamap_destroy(rxr->rxdma.dma_tag, rxbuf->map); 2380 rxbuf->map = NULL; 2381 } 2382 free(rxr->rx_buffers, M_DEVBUF, 2383 sc->num_rx_desc * sizeof(struct igc_rx_buf)); 2384 rxr->rx_buffers = NULL; 2385 } 2386 } 2387 2388 /* 2389 * Initialise the RSS mapping for NICs that support multiple transmit/ 2390 * receive rings. 2391 */ 2392 void 2393 igc_initialize_rss_mapping(struct igc_softc *sc) 2394 { 2395 struct igc_hw *hw = &sc->hw; 2396 uint32_t rss_key[10], mrqc, reta, shift = 0; 2397 int i, queue_id; 2398 2399 /* 2400 * The redirection table controls which destination 2401 * queue each bucket redirects traffic to. 2402 * Each DWORD represents four queues, with the LSB 2403 * being the first queue in the DWORD. 2404 * 2405 * This just allocates buckets to queues using round-robin 2406 * allocation. 2407 * 2408 * NOTE: It Just Happens to line up with the default 2409 * RSS allocation method. 2410 */ 2411 2412 /* Warning FM follows */ 2413 reta = 0; 2414 for (i = 0; i < 128; i++) { 2415 queue_id = (i % sc->sc_nqueues); 2416 /* Adjust if required */ 2417 queue_id = queue_id << shift; 2418 2419 /* 2420 * The low 8 bits are for hash value (n+0); 2421 * The next 8 bits are for hash value (n+1), etc. 2422 */ 2423 reta = reta >> 8; 2424 reta = reta | ( ((uint32_t) queue_id) << 24); 2425 if ((i & 3) == 3) { 2426 IGC_WRITE_REG(hw, IGC_RETA(i >> 2), reta); 2427 reta = 0; 2428 } 2429 } 2430 2431 /* 2432 * MRQC: Multiple Receive Queues Command 2433 * Set queuing to RSS control, number depends on the device. 2434 */ 2435 mrqc = IGC_MRQC_ENABLE_RSS_4Q; 2436 2437 /* Set up random bits */ 2438 stoeplitz_to_key(&rss_key, sizeof(rss_key)); 2439 2440 /* Now fill our hash function seeds */ 2441 for (i = 0; i < 10; i++) 2442 IGC_WRITE_REG_ARRAY(hw, IGC_RSSRK(0), i, rss_key[i]); 2443 2444 /* 2445 * Configure the RSS fields to hash upon. 2446 */ 2447 mrqc |= (IGC_MRQC_RSS_FIELD_IPV4 | IGC_MRQC_RSS_FIELD_IPV4_TCP); 2448 mrqc |= (IGC_MRQC_RSS_FIELD_IPV6 | IGC_MRQC_RSS_FIELD_IPV6_TCP); 2449 mrqc |= IGC_MRQC_RSS_FIELD_IPV6_TCP_EX; 2450 2451 IGC_WRITE_REG(hw, IGC_MRQC, mrqc); 2452 } 2453 2454 /* 2455 * igc_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 2456 * For ASF and Pass Through versions of f/w this means 2457 * that the driver is loaded. For AMT version type f/w 2458 * this means that the network i/f is open. 2459 */ 2460 void 2461 igc_get_hw_control(struct igc_softc *sc) 2462 { 2463 uint32_t ctrl_ext; 2464 2465 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT); 2466 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 2467 } 2468 2469 /* 2470 * igc_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 2471 * For ASF and Pass Through versions of f/w this means that 2472 * the driver is no longer loaded. For AMT versions of the 2473 * f/w this means that the network i/f is closed. 2474 */ 2475 void 2476 igc_release_hw_control(struct igc_softc *sc) 2477 { 2478 uint32_t ctrl_ext; 2479 2480 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT); 2481 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 2482 } 2483 2484 int 2485 igc_is_valid_ether_addr(uint8_t *addr) 2486 { 2487 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 2488 2489 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 2490 return 0; 2491 } 2492 2493 return 1; 2494 } 2495 2496 #if NKSTAT > 0 2497 2498 /* 2499 * the below are read to clear, so they need to be accumulated for 2500 * userland to see counters. periodically fetch the counters from a 2501 * timeout to avoid a 32 roll-over between kstat reads. 2502 */ 2503 2504 enum igc_stat { 2505 igc_stat_crcerrs, 2506 igc_stat_algnerrc, 2507 igc_stat_rxerrc, 2508 igc_stat_mpc, 2509 igc_stat_scc, 2510 igc_stat_ecol, 2511 igc_stat_mcc, 2512 igc_stat_latecol, 2513 igc_stat_colc, 2514 igc_stat_rerc, 2515 igc_stat_dc, 2516 igc_stat_tncrs, 2517 igc_stat_htdpmc, 2518 igc_stat_rlec, 2519 igc_stat_xonrxc, 2520 igc_stat_xontxc, 2521 igc_stat_xoffrxc, 2522 igc_stat_xofftxc, 2523 igc_stat_fcruc, 2524 igc_stat_prc64, 2525 igc_stat_prc127, 2526 igc_stat_prc255, 2527 igc_stat_prc511, 2528 igc_stat_prc1023, 2529 igc_stat_prc1522, 2530 igc_stat_gprc, 2531 igc_stat_bprc, 2532 igc_stat_mprc, 2533 igc_stat_gptc, 2534 igc_stat_gorc, 2535 igc_stat_gotc, 2536 igc_stat_rnbc, 2537 igc_stat_ruc, 2538 igc_stat_rfc, 2539 igc_stat_roc, 2540 igc_stat_rjc, 2541 igc_stat_mgtprc, 2542 igc_stat_mgtpdc, 2543 igc_stat_mgtptc, 2544 igc_stat_tor, 2545 igc_stat_tot, 2546 igc_stat_tpr, 2547 igc_stat_tpt, 2548 igc_stat_ptc64, 2549 igc_stat_ptc127, 2550 igc_stat_ptc255, 2551 igc_stat_ptc511, 2552 igc_stat_ptc1023, 2553 igc_stat_ptc1522, 2554 igc_stat_mptc, 2555 igc_stat_bptc, 2556 igc_stat_tsctc, 2557 2558 igc_stat_iac, 2559 igc_stat_rpthc, 2560 igc_stat_tlpic, 2561 igc_stat_rlpic, 2562 igc_stat_hgptc, 2563 igc_stat_rxdmtc, 2564 igc_stat_hgorc, 2565 igc_stat_hgotc, 2566 igc_stat_lenerrs, 2567 2568 igc_stat_count 2569 }; 2570 2571 struct igc_counter { 2572 const char *name; 2573 enum kstat_kv_unit unit; 2574 uint32_t reg; 2575 }; 2576 2577 static const struct igc_counter igc_counters[igc_stat_count] = { 2578 [igc_stat_crcerrs] = 2579 { "crc errs", KSTAT_KV_U_NONE, IGC_CRCERRS }, 2580 [igc_stat_algnerrc] = 2581 { "alignment errs", KSTAT_KV_U_NONE, IGC_ALGNERRC }, 2582 [igc_stat_rxerrc] = 2583 { "rx errs", KSTAT_KV_U_NONE, IGC_RXERRC }, 2584 [igc_stat_mpc] = 2585 { "missed pkts", KSTAT_KV_U_NONE, IGC_MPC }, 2586 [igc_stat_scc] = 2587 { "single colls", KSTAT_KV_U_NONE, IGC_SCC }, 2588 [igc_stat_ecol] = 2589 { "excessive colls", KSTAT_KV_U_NONE, IGC_ECOL }, 2590 [igc_stat_mcc] = 2591 { "multiple colls", KSTAT_KV_U_NONE, IGC_MCC }, 2592 [igc_stat_latecol] = 2593 { "late colls", KSTAT_KV_U_NONE, IGC_LATECOL }, 2594 [igc_stat_colc] = 2595 { "collisions", KSTAT_KV_U_NONE, IGC_COLC }, 2596 [igc_stat_rerc] = 2597 { "recv errs", KSTAT_KV_U_NONE, IGC_RERC }, 2598 [igc_stat_dc] = 2599 { "defers", KSTAT_KV_U_NONE, IGC_DC }, 2600 [igc_stat_tncrs] = 2601 { "tx no crs", KSTAT_KV_U_NONE, IGC_TNCRS}, 2602 [igc_stat_htdpmc] = 2603 { "host tx discards", KSTAT_KV_U_NONE, IGC_HTDPMC }, 2604 [igc_stat_rlec] = 2605 { "recv len errs", KSTAT_KV_U_NONE, IGC_RLEC }, 2606 [igc_stat_xonrxc] = 2607 { "xon rx", KSTAT_KV_U_NONE, IGC_XONRXC }, 2608 [igc_stat_xontxc] = 2609 { "xon tx", KSTAT_KV_U_NONE, IGC_XONTXC }, 2610 [igc_stat_xoffrxc] = 2611 { "xoff rx", KSTAT_KV_U_NONE, IGC_XOFFRXC }, 2612 [igc_stat_xofftxc] = 2613 { "xoff tx", KSTAT_KV_U_NONE, IGC_XOFFTXC }, 2614 [igc_stat_fcruc] = 2615 { "fc rx unsupp", KSTAT_KV_U_NONE, IGC_FCRUC }, 2616 [igc_stat_prc64] = 2617 { "rx 64B", KSTAT_KV_U_PACKETS, IGC_PRC64 }, 2618 [igc_stat_prc127] = 2619 { "rx 65-127B", KSTAT_KV_U_PACKETS, IGC_PRC127 }, 2620 [igc_stat_prc255] = 2621 { "rx 128-255B", KSTAT_KV_U_PACKETS, IGC_PRC255 }, 2622 [igc_stat_prc511] = 2623 { "rx 256-511B", KSTAT_KV_U_PACKETS, IGC_PRC511 }, 2624 [igc_stat_prc1023] = 2625 { "rx 512-1023B", KSTAT_KV_U_PACKETS, IGC_PRC1023 }, 2626 [igc_stat_prc1522] = 2627 { "rx 1024-maxB", KSTAT_KV_U_PACKETS, IGC_PRC1522 }, 2628 [igc_stat_gprc] = 2629 { "rx good", KSTAT_KV_U_PACKETS, IGC_GPRC }, 2630 [igc_stat_bprc] = 2631 { "rx bcast", KSTAT_KV_U_PACKETS, IGC_BPRC }, 2632 [igc_stat_mprc] = 2633 { "rx mcast", KSTAT_KV_U_PACKETS, IGC_MPRC }, 2634 [igc_stat_gptc] = 2635 { "tx good", KSTAT_KV_U_PACKETS, IGC_GPTC }, 2636 [igc_stat_gorc] = 2637 { "rx good bytes", KSTAT_KV_U_BYTES, 0 }, 2638 [igc_stat_gotc] = 2639 { "tx good bytes", KSTAT_KV_U_BYTES, 0 }, 2640 [igc_stat_rnbc] = 2641 { "rx no bufs", KSTAT_KV_U_NONE, IGC_RNBC }, 2642 [igc_stat_ruc] = 2643 { "rx undersize", KSTAT_KV_U_NONE, IGC_RUC }, 2644 [igc_stat_rfc] = 2645 { "rx frags", KSTAT_KV_U_NONE, IGC_RFC }, 2646 [igc_stat_roc] = 2647 { "rx oversize", KSTAT_KV_U_NONE, IGC_ROC }, 2648 [igc_stat_rjc] = 2649 { "rx jabbers", KSTAT_KV_U_NONE, IGC_RJC }, 2650 [igc_stat_mgtprc] = 2651 { "rx mgmt", KSTAT_KV_U_PACKETS, IGC_MGTPRC }, 2652 [igc_stat_mgtpdc] = 2653 { "rx mgmt drops", KSTAT_KV_U_PACKETS, IGC_MGTPDC }, 2654 [igc_stat_mgtptc] = 2655 { "tx mgmt", KSTAT_KV_U_PACKETS, IGC_MGTPTC }, 2656 [igc_stat_tor] = 2657 { "rx total bytes", KSTAT_KV_U_BYTES, 0 }, 2658 [igc_stat_tot] = 2659 { "tx total bytes", KSTAT_KV_U_BYTES, 0 }, 2660 [igc_stat_tpr] = 2661 { "rx total", KSTAT_KV_U_PACKETS, IGC_TPR }, 2662 [igc_stat_tpt] = 2663 { "tx total", KSTAT_KV_U_PACKETS, IGC_TPT }, 2664 [igc_stat_ptc64] = 2665 { "tx 64B", KSTAT_KV_U_PACKETS, IGC_PTC64 }, 2666 [igc_stat_ptc127] = 2667 { "tx 65-127B", KSTAT_KV_U_PACKETS, IGC_PTC127 }, 2668 [igc_stat_ptc255] = 2669 { "tx 128-255B", KSTAT_KV_U_PACKETS, IGC_PTC255 }, 2670 [igc_stat_ptc511] = 2671 { "tx 256-511B", KSTAT_KV_U_PACKETS, IGC_PTC511 }, 2672 [igc_stat_ptc1023] = 2673 { "tx 512-1023B", KSTAT_KV_U_PACKETS, IGC_PTC1023 }, 2674 [igc_stat_ptc1522] = 2675 { "tx 1024-maxB", KSTAT_KV_U_PACKETS, IGC_PTC1522 }, 2676 [igc_stat_mptc] = 2677 { "tx mcast", KSTAT_KV_U_PACKETS, IGC_MPTC }, 2678 [igc_stat_bptc] = 2679 { "tx bcast", KSTAT_KV_U_PACKETS, IGC_BPTC }, 2680 [igc_stat_tsctc] = 2681 { "tx tso ctx", KSTAT_KV_U_NONE, IGC_TSCTC }, 2682 2683 [igc_stat_iac] = 2684 { "interrupts", KSTAT_KV_U_NONE, IGC_IAC }, 2685 [igc_stat_rpthc] = 2686 { "rx to host", KSTAT_KV_U_PACKETS, IGC_RPTHC }, 2687 [igc_stat_tlpic] = 2688 { "eee tx lpi", KSTAT_KV_U_NONE, IGC_TLPIC }, 2689 [igc_stat_rlpic] = 2690 { "eee rx lpi", KSTAT_KV_U_NONE, IGC_RLPIC }, 2691 [igc_stat_hgptc] = 2692 { "host rx", KSTAT_KV_U_PACKETS, IGC_HGPTC }, 2693 [igc_stat_rxdmtc] = 2694 { "rxd min thresh", KSTAT_KV_U_NONE, IGC_RXDMTC }, 2695 [igc_stat_hgorc] = 2696 { "host good rx", KSTAT_KV_U_BYTES, 0 }, 2697 [igc_stat_hgotc] = 2698 { "host good tx", KSTAT_KV_U_BYTES, 0 }, 2699 [igc_stat_lenerrs] = 2700 { "len errs", KSTAT_KV_U_NONE, IGC_LENERRS }, 2701 }; 2702 2703 static void 2704 igc_stat_read(struct igc_softc *sc) 2705 { 2706 struct igc_hw *hw = &sc->hw; 2707 struct kstat *ks = sc->ks; 2708 struct kstat_kv *kvs = ks->ks_data; 2709 uint32_t hi, lo; 2710 unsigned int i; 2711 2712 for (i = 0; i < nitems(igc_counters); i++) { 2713 const struct igc_counter *c = &igc_counters[i]; 2714 if (c->reg == 0) 2715 continue; 2716 2717 kstat_kv_u64(&kvs[i]) += IGC_READ_REG(hw, c->reg); 2718 } 2719 2720 lo = IGC_READ_REG(hw, IGC_GORCL); 2721 hi = IGC_READ_REG(hw, IGC_GORCH); 2722 kstat_kv_u64(&kvs[igc_stat_gorc]) += 2723 ((uint64_t)hi << 32) | ((uint64_t)lo << 0); 2724 2725 lo = IGC_READ_REG(hw, IGC_GOTCL); 2726 hi = IGC_READ_REG(hw, IGC_GOTCH); 2727 kstat_kv_u64(&kvs[igc_stat_gotc]) += 2728 ((uint64_t)hi << 32) | ((uint64_t)lo << 0); 2729 2730 lo = IGC_READ_REG(hw, IGC_TORL); 2731 hi = IGC_READ_REG(hw, IGC_TORH); 2732 kstat_kv_u64(&kvs[igc_stat_tor]) += 2733 ((uint64_t)hi << 32) | ((uint64_t)lo << 0); 2734 2735 lo = IGC_READ_REG(hw, IGC_TOTL); 2736 hi = IGC_READ_REG(hw, IGC_TOTH); 2737 kstat_kv_u64(&kvs[igc_stat_tot]) += 2738 ((uint64_t)hi << 32) | ((uint64_t)lo << 0); 2739 2740 lo = IGC_READ_REG(hw, IGC_HGORCL); 2741 hi = IGC_READ_REG(hw, IGC_HGORCH); 2742 kstat_kv_u64(&kvs[igc_stat_hgorc]) += 2743 ((uint64_t)hi << 32) | ((uint64_t)lo << 0); 2744 2745 lo = IGC_READ_REG(hw, IGC_HGOTCL); 2746 hi = IGC_READ_REG(hw, IGC_HGOTCH); 2747 kstat_kv_u64(&kvs[igc_stat_hgotc]) += 2748 ((uint64_t)hi << 32) | ((uint64_t)lo << 0); 2749 } 2750 2751 static void 2752 igc_kstat_tick(void *arg) 2753 { 2754 struct igc_softc *sc = arg; 2755 2756 if (mtx_enter_try(&sc->ks_mtx)) { 2757 igc_stat_read(sc); 2758 mtx_leave(&sc->ks_mtx); 2759 } 2760 2761 timeout_add_sec(&sc->ks_tmo, 4); 2762 } 2763 2764 static int 2765 igc_kstat_read(struct kstat *ks) 2766 { 2767 struct igc_softc *sc = ks->ks_softc; 2768 2769 igc_stat_read(sc); 2770 nanouptime(&ks->ks_updated); 2771 2772 return (0); 2773 } 2774 2775 void 2776 igc_kstat_attach(struct igc_softc *sc) 2777 { 2778 struct kstat *ks; 2779 struct kstat_kv *kvs; 2780 size_t len; 2781 unsigned int i; 2782 2783 mtx_init(&sc->ks_mtx, IPL_SOFTCLOCK); 2784 timeout_set(&sc->ks_tmo, igc_kstat_tick, sc); 2785 2786 kvs = mallocarray(sizeof(*kvs), nitems(igc_counters), M_DEVBUF, 2787 M_WAITOK|M_ZERO|M_CANFAIL); 2788 if (kvs == NULL) { 2789 printf("%s: unable to allocate igc kstats\n", DEVNAME(sc)); 2790 return; 2791 } 2792 len = sizeof(*kvs) * nitems(igc_counters); 2793 2794 ks = kstat_create(DEVNAME(sc), 0, "igc-stats", 0, KSTAT_T_KV, 0); 2795 if (ks == NULL) { 2796 printf("%s: unable to create igc kstats\n", DEVNAME(sc)); 2797 free(kvs, M_DEVBUF, len); 2798 return; 2799 } 2800 2801 for (i = 0; i < nitems(igc_counters); i++) { 2802 const struct igc_counter *c = &igc_counters[i]; 2803 kstat_kv_unit_init(&kvs[i], c->name, 2804 KSTAT_KV_T_COUNTER64, c->unit); 2805 } 2806 2807 ks->ks_softc = sc; 2808 ks->ks_data = kvs; 2809 ks->ks_datalen = len; 2810 ks->ks_read = igc_kstat_read; 2811 kstat_set_mutex(ks, &sc->ks_mtx); 2812 2813 kstat_install(ks); 2814 2815 sc->ks = ks; 2816 2817 igc_kstat_tick(sc); /* let's gooo */ 2818 } 2819 #endif /* NKSTAT > 0 */ 2820