1 /* $OpenBSD: if_igc.c,v 1.3 2021/10/31 15:22:40 patrick Exp $ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause 4 * 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * All rights reserved. 7 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate) 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include "bpfilter.h" 32 #include "vlan.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/sockio.h> 37 #include <sys/mbuf.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/device.h> 42 #include <sys/endian.h> 43 #include <sys/intrmap.h> 44 45 #include <net/if.h> 46 #include <net/if_media.h> 47 #include <net/toeplitz.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #if NBPFILTER > 0 53 #include <net/bpf.h> 54 #endif 55 56 #include <machine/bus.h> 57 #include <machine/intr.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 #include <dev/pci/if_igc.h> 63 #include <dev/pci/igc_hw.h> 64 65 const struct pci_matchid igc_devices[] = { 66 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I220_V }, 67 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I221_V }, 68 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_BLANK_NVM }, 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_I }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_IT }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_K }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_K2 }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_LM }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_LMVP }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I225_V }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I226_BLANK_NVM }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I226_IT }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I226_LM }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I226_K }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I226_V } 81 }; 82 83 /********************************************************************* 84 * Function Prototypes 85 *********************************************************************/ 86 int igc_match(struct device *, void *, void *); 87 void igc_attach(struct device *, struct device *, void *); 88 int igc_detach(struct device *, int); 89 90 void igc_identify_hardware(struct igc_softc *); 91 int igc_allocate_pci_resources(struct igc_softc *); 92 int igc_allocate_queues(struct igc_softc *); 93 void igc_free_pci_resources(struct igc_softc *); 94 void igc_reset(struct igc_softc *); 95 void igc_init_dmac(struct igc_softc *, uint32_t); 96 int igc_allocate_msix(struct igc_softc *); 97 void igc_setup_msix(struct igc_softc *); 98 int igc_dma_malloc(struct igc_softc *, bus_size_t, struct igc_dma_alloc *); 99 void igc_dma_free(struct igc_softc *, struct igc_dma_alloc *); 100 void igc_setup_interface(struct igc_softc *); 101 102 void igc_init(void *); 103 void igc_start(struct ifqueue *); 104 int igc_txeof(struct tx_ring *); 105 void igc_stop(struct igc_softc *); 106 int igc_ioctl(struct ifnet *, u_long, caddr_t); 107 int igc_rxrinfo(struct igc_softc *, struct if_rxrinfo *); 108 int igc_rxfill(struct rx_ring *); 109 void igc_rxrefill(void *); 110 int igc_rxeof(struct rx_ring *); 111 void igc_rx_checksum(uint32_t, struct mbuf *, uint32_t); 112 void igc_watchdog(struct ifnet *); 113 void igc_media_status(struct ifnet *, struct ifmediareq *); 114 int igc_media_change(struct ifnet *); 115 void igc_iff(struct igc_softc *); 116 void igc_update_link_status(struct igc_softc *); 117 int igc_get_buf(struct rx_ring *, int); 118 119 void igc_configure_queues(struct igc_softc *); 120 void igc_set_queues(struct igc_softc *, uint32_t, uint32_t, int); 121 void igc_enable_queue(struct igc_softc *, uint32_t); 122 void igc_enable_intr(struct igc_softc *); 123 void igc_disable_intr(struct igc_softc *); 124 int igc_intr_link(void *); 125 int igc_intr_queue(void *); 126 127 int igc_allocate_transmit_buffers(struct tx_ring *); 128 int igc_setup_transmit_structures(struct igc_softc *); 129 int igc_setup_transmit_ring(struct tx_ring *); 130 void igc_initialize_transmit_unit(struct igc_softc *); 131 void igc_free_transmit_structures(struct igc_softc *); 132 void igc_free_transmit_buffers(struct tx_ring *); 133 int igc_allocate_receive_buffers(struct rx_ring *); 134 int igc_setup_receive_structures(struct igc_softc *); 135 int igc_setup_receive_ring(struct rx_ring *); 136 void igc_initialize_receive_unit(struct igc_softc *); 137 void igc_free_receive_structures(struct igc_softc *); 138 void igc_free_receive_buffers(struct rx_ring *); 139 void igc_initialize_rss_mapping(struct igc_softc *); 140 141 void igc_get_hw_control(struct igc_softc *); 142 void igc_release_hw_control(struct igc_softc *); 143 int igc_is_valid_ether_addr(uint8_t *); 144 145 /********************************************************************* 146 * OpenBSD Device Interface Entry Points 147 *********************************************************************/ 148 149 struct cfdriver igc_cd = { 150 NULL, "igc", DV_IFNET 151 }; 152 153 struct cfattach igc_ca = { 154 sizeof(struct igc_softc), igc_match, igc_attach, igc_detach 155 }; 156 157 /********************************************************************* 158 * Device identification routine 159 * 160 * igc_match determines if the driver should be loaded on 161 * adapter based on PCI vendor/device id of the adapter. 162 * 163 * return 0 on success, positive on failure 164 *********************************************************************/ 165 int 166 igc_match(struct device *parent, void *match, void *aux) 167 { 168 return pci_matchbyid((struct pci_attach_args *)aux, igc_devices, 169 nitems(igc_devices)); 170 } 171 172 /********************************************************************* 173 * Device initialization routine 174 * 175 * The attach entry point is called when the driver is being loaded. 176 * This routine identifies the type of hardware, allocates all resources 177 * and initializes the hardware. 178 * 179 * return 0 on success, positive on failure 180 *********************************************************************/ 181 void 182 igc_attach(struct device *parent, struct device *self, void *aux) 183 { 184 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 185 struct igc_softc *sc = (struct igc_softc *)self; 186 struct igc_hw *hw = &sc->hw; 187 188 sc->osdep.os_sc = sc; 189 sc->osdep.os_pa = *pa; 190 191 /* Determine hardware and mac info */ 192 igc_identify_hardware(sc); 193 194 sc->num_tx_desc = IGC_DEFAULT_TXD; 195 sc->num_rx_desc = IGC_DEFAULT_RXD; 196 197 /* Setup PCI resources */ 198 if (igc_allocate_pci_resources(sc)) 199 goto err_pci; 200 201 /* Allocate TX/RX queues */ 202 if (igc_allocate_queues(sc)) 203 goto err_pci; 204 205 /* Do shared code initialization */ 206 if (igc_setup_init_funcs(hw, true)) { 207 printf(": Setup of shared code failed\n"); 208 goto err_pci; 209 } 210 211 hw->mac.autoneg = DO_AUTO_NEG; 212 hw->phy.autoneg_wait_to_complete = false; 213 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 214 215 /* Copper options. */ 216 if (hw->phy.media_type == igc_media_type_copper) 217 hw->phy.mdix = AUTO_ALL_MODES; 218 219 /* Set the max frame size. */ 220 sc->hw.mac.max_frame_size = 9234; 221 222 /* Allocate multicast array memory. */ 223 sc->mta = mallocarray(ETHER_ADDR_LEN, MAX_NUM_MULTICAST_ADDRESSES, 224 M_DEVBUF, M_NOWAIT); 225 if (sc->mta == NULL) { 226 printf(": Can not allocate multicast setup array\n"); 227 goto err_late; 228 } 229 230 /* Check SOL/IDER usage. */ 231 if (igc_check_reset_block(hw)) 232 printf(": PHY reset is blocked due to SOL/IDER session\n"); 233 234 /* Enable Energy Efficient Ethernet. */ 235 sc->hw.dev_spec._i225.eee_disable = true; 236 237 igc_reset_hw(hw); 238 239 /* Make sure we have a good EEPROM before we read from it. */ 240 if (igc_validate_nvm_checksum(hw) < 0) { 241 /* 242 * Some PCI-E parts fail the first check due to 243 * the link being in sleep state, call it again, 244 * if it fails a second time its a real issue. 245 */ 246 if (igc_validate_nvm_checksum(hw) < 0) { 247 printf(": The EEPROM checksum is not valid\n"); 248 goto err_late; 249 } 250 } 251 252 /* Copy the permanent MAC address out of the EEPROM. */ 253 if (igc_read_mac_addr(hw) < 0) { 254 printf(": EEPROM read error while reading MAC address\n"); 255 goto err_late; 256 } 257 258 if (!igc_is_valid_ether_addr(hw->mac.addr)) { 259 printf(": Invalid MAC address\n"); 260 goto err_late; 261 } 262 263 memcpy(sc->sc_ac.ac_enaddr, sc->hw.mac.addr, ETHER_ADDR_LEN); 264 265 if (igc_allocate_msix(sc)) 266 goto err_late; 267 268 /* Setup OS specific network interface. */ 269 igc_setup_interface(sc); 270 271 igc_reset(sc); 272 hw->mac.get_link_status = true; 273 igc_update_link_status(sc); 274 275 /* The driver can now take control from firmware. */ 276 igc_get_hw_control(sc); 277 278 printf(", address %s\n", ether_sprintf(sc->hw.mac.addr)); 279 return; 280 281 err_late: 282 igc_release_hw_control(sc); 283 err_pci: 284 igc_free_pci_resources(sc); 285 free(sc->mta, M_DEVBUF, ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 286 } 287 288 /********************************************************************* 289 * Device removal routine 290 * 291 * The detach entry point is called when the driver is being removed. 292 * This routine stops the adapter and deallocates all the resources 293 * that were allocated for driver operation. 294 * 295 * return 0 on success, positive on failure 296 *********************************************************************/ 297 int 298 igc_detach(struct device *self, int flags) 299 { 300 struct igc_softc *sc = (struct igc_softc *)self; 301 struct ifnet *ifp = &sc->sc_ac.ac_if; 302 303 igc_stop(sc); 304 305 igc_phy_hw_reset(&sc->hw); 306 igc_release_hw_control(sc); 307 308 ether_ifdetach(ifp); 309 if_detach(ifp); 310 311 igc_free_pci_resources(sc); 312 313 igc_free_transmit_structures(sc); 314 igc_free_receive_structures(sc); 315 free(sc->mta, M_DEVBUF, ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 316 317 return 0; 318 } 319 320 void 321 igc_identify_hardware(struct igc_softc *sc) 322 { 323 struct igc_osdep *os = &sc->osdep; 324 struct pci_attach_args *pa = &os->os_pa; 325 326 /* Save off the information about this board. */ 327 sc->hw.device_id = PCI_PRODUCT(pa->pa_id); 328 329 /* Do shared code init and setup. */ 330 if (igc_set_mac_type(&sc->hw)) { 331 printf(": Setup init failure\n"); 332 return; 333 } 334 } 335 336 int 337 igc_allocate_pci_resources(struct igc_softc *sc) 338 { 339 struct igc_osdep *os = &sc->osdep; 340 struct pci_attach_args *pa = &os->os_pa; 341 pcireg_t memtype; 342 343 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IGC_PCIREG); 344 if (pci_mapreg_map(pa, IGC_PCIREG, memtype, 0, &os->os_memt, 345 &os->os_memh, &os->os_membase, &os->os_memsize, 0)) { 346 printf(": unable to map registers\n"); 347 return ENXIO; 348 } 349 sc->hw.hw_addr = (uint8_t *)os->os_membase; 350 sc->hw.back = os; 351 352 igc_setup_msix(sc); 353 354 return 0; 355 } 356 357 int 358 igc_allocate_queues(struct igc_softc *sc) 359 { 360 struct igc_queue *iq; 361 struct tx_ring *txr; 362 struct rx_ring *rxr; 363 int i, rsize, rxconf, tsize, txconf; 364 365 /* Allocate the top level queue structs. */ 366 sc->queues = mallocarray(sc->sc_nqueues, sizeof(struct igc_queue), 367 M_DEVBUF, M_NOWAIT | M_ZERO); 368 if (sc->queues == NULL) { 369 printf("%s: unable to allocate queue\n", DEVNAME(sc)); 370 goto fail; 371 } 372 373 /* Allocate the TX ring. */ 374 sc->tx_rings = mallocarray(sc->sc_nqueues, sizeof(struct tx_ring), 375 M_DEVBUF, M_NOWAIT | M_ZERO); 376 if (sc->tx_rings == NULL) { 377 printf("%s: unable to allocate TX ring\n", DEVNAME(sc)); 378 goto fail; 379 } 380 381 /* Allocate the RX ring. */ 382 sc->rx_rings = mallocarray(sc->sc_nqueues, sizeof(struct rx_ring), 383 M_DEVBUF, M_NOWAIT | M_ZERO); 384 if (sc->rx_rings == NULL) { 385 printf("%s: unable to allocate RX ring\n", DEVNAME(sc)); 386 goto rx_fail; 387 } 388 389 txconf = rxconf = 0; 390 391 /* Set up the TX queues. */ 392 tsize = roundup2(sc->num_tx_desc * sizeof(union igc_adv_tx_desc), 393 IGC_DBA_ALIGN); 394 for (i = 0; i < sc->sc_nqueues; i++, txconf++) { 395 txr = &sc->tx_rings[i]; 396 txr->sc = sc; 397 txr->me = i; 398 399 if (igc_dma_malloc(sc, tsize, &txr->txdma)) { 400 printf("%s: unable to allocate TX descriptor\n", 401 DEVNAME(sc)); 402 goto err_tx_desc; 403 } 404 txr->tx_base = (union igc_adv_tx_desc *)txr->txdma.dma_vaddr; 405 bzero((void *)txr->tx_base, tsize); 406 } 407 408 /* Set up the RX queues. */ 409 rsize = roundup2(sc->num_rx_desc * sizeof(union igc_adv_rx_desc), 410 IGC_DBA_ALIGN); 411 for (i = 0; i < sc->sc_nqueues; i++, rxconf++) { 412 rxr = &sc->rx_rings[i]; 413 rxr->sc = sc; 414 rxr->me = i; 415 timeout_set(&rxr->rx_refill, igc_rxrefill, rxr); 416 417 if (igc_dma_malloc(sc, rsize, &rxr->rxdma)) { 418 printf("%s: unable to allocate RX descriptor\n", 419 DEVNAME(sc)); 420 goto err_rx_desc; 421 } 422 rxr->rx_base = (union igc_adv_rx_desc *)rxr->rxdma.dma_vaddr; 423 bzero((void *)rxr->rx_base, rsize); 424 } 425 426 /* Set up the queue holding structs. */ 427 for (i = 0; i < sc->sc_nqueues; i++) { 428 iq = &sc->queues[i]; 429 iq->sc = sc; 430 iq->txr = &sc->tx_rings[i]; 431 iq->rxr = &sc->rx_rings[i]; 432 snprintf(iq->name, sizeof(iq->name), "%s:%d", DEVNAME(sc), i); 433 } 434 435 return 0; 436 437 err_rx_desc: 438 for (rxr = sc->rx_rings; rxconf > 0; rxr++, rxconf--) 439 igc_dma_free(sc, &rxr->rxdma); 440 err_tx_desc: 441 for (txr = sc->tx_rings; txconf > 0; txr++, txconf--) 442 igc_dma_free(sc, &txr->txdma); 443 free(sc->rx_rings, M_DEVBUF, sc->sc_nqueues * sizeof(struct rx_ring)); 444 sc->rx_rings = NULL; 445 rx_fail: 446 free(sc->tx_rings, M_DEVBUF, sc->sc_nqueues * sizeof(struct tx_ring)); 447 sc->tx_rings = NULL; 448 fail: 449 return ENOMEM; 450 } 451 452 void 453 igc_free_pci_resources(struct igc_softc *sc) 454 { 455 struct igc_osdep *os = &sc->osdep; 456 struct pci_attach_args *pa = &os->os_pa; 457 struct igc_queue *iq = sc->queues; 458 int i; 459 460 /* Release all msix queue resources. */ 461 for (i = 0; i < sc->sc_nqueues; i++, iq++) { 462 if (iq->tag) 463 pci_intr_disestablish(pa->pa_pc, iq->tag); 464 iq->tag = NULL; 465 } 466 467 if (sc->tag) 468 pci_intr_disestablish(pa->pa_pc, sc->tag); 469 sc->tag = NULL; 470 if (os->os_membase != 0) 471 bus_space_unmap(os->os_memt, os->os_memh, os->os_memsize); 472 os->os_membase = 0; 473 } 474 475 /********************************************************************* 476 * 477 * Initialize the hardware to a configuration as specified by the 478 * adapter structure. 479 * 480 **********************************************************************/ 481 void 482 igc_reset(struct igc_softc *sc) 483 { 484 struct igc_hw *hw = &sc->hw; 485 uint32_t pba; 486 uint16_t rx_buffer_size; 487 488 /* Let the firmware know the OS is in control */ 489 igc_get_hw_control(sc); 490 491 /* 492 * Packet Buffer Allocation (PBA) 493 * Writing PBA sets the receive portion of the buffer 494 * the remainder is used for the transmit buffer. 495 */ 496 pba = IGC_PBA_34K; 497 498 /* 499 * These parameters control the automatic generation (Tx) and 500 * response (Rx) to Ethernet PAUSE frames. 501 * - High water mark should allow for at least two frames to be 502 * received after sending an XOFF. 503 * - Low water mark works best when it is very near the high water mark. 504 * This allows the receiver to restart by sending XON when it has 505 * drained a bit. Here we use an arbitrary value of 1500 which will 506 * restart after one full frame is pulled from the buffer. There 507 * could be several smaller frames in the buffer and if so they will 508 * not trigger the XON until their total number reduces the buffer 509 * by 1500. 510 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 511 */ 512 rx_buffer_size = (pba & 0xffff) << 10; 513 hw->fc.high_water = rx_buffer_size - 514 roundup2(sc->hw.mac.max_frame_size, 1024); 515 /* 16-byte granularity */ 516 hw->fc.low_water = hw->fc.high_water - 16; 517 518 if (sc->fc) /* locally set flow control value? */ 519 hw->fc.requested_mode = sc->fc; 520 else 521 hw->fc.requested_mode = igc_fc_full; 522 523 hw->fc.pause_time = IGC_FC_PAUSE_TIME; 524 525 hw->fc.send_xon = true; 526 527 /* Issue a global reset */ 528 igc_reset_hw(hw); 529 IGC_WRITE_REG(hw, IGC_WUC, 0); 530 531 /* and a re-init */ 532 if (igc_init_hw(hw) < 0) { 533 printf(": Hardware Initialization Failed\n"); 534 return; 535 } 536 537 /* Setup DMA Coalescing */ 538 igc_init_dmac(sc, pba); 539 540 IGC_WRITE_REG(hw, IGC_VET, ETHERTYPE_VLAN); 541 igc_get_phy_info(hw); 542 igc_check_for_link(hw); 543 } 544 545 /********************************************************************* 546 * 547 * Initialize the DMA Coalescing feature 548 * 549 **********************************************************************/ 550 void 551 igc_init_dmac(struct igc_softc *sc, uint32_t pba) 552 { 553 struct igc_hw *hw = &sc->hw; 554 uint32_t dmac, reg = ~IGC_DMACR_DMAC_EN; 555 uint16_t hwm, max_frame_size; 556 int status; 557 558 max_frame_size = sc->hw.mac.max_frame_size; 559 560 if (sc->dmac == 0) { /* Disabling it */ 561 IGC_WRITE_REG(hw, IGC_DMACR, reg); 562 return; 563 } else 564 printf(": DMA Coalescing enabled\n"); 565 566 /* Set starting threshold */ 567 IGC_WRITE_REG(hw, IGC_DMCTXTH, 0); 568 569 hwm = 64 * pba - max_frame_size / 16; 570 if (hwm < 64 * (pba - 6)) 571 hwm = 64 * (pba - 6); 572 reg = IGC_READ_REG(hw, IGC_FCRTC); 573 reg &= ~IGC_FCRTC_RTH_COAL_MASK; 574 reg |= ((hwm << IGC_FCRTC_RTH_COAL_SHIFT) 575 & IGC_FCRTC_RTH_COAL_MASK); 576 IGC_WRITE_REG(hw, IGC_FCRTC, reg); 577 578 dmac = pba - max_frame_size / 512; 579 if (dmac < pba - 10) 580 dmac = pba - 10; 581 reg = IGC_READ_REG(hw, IGC_DMACR); 582 reg &= ~IGC_DMACR_DMACTHR_MASK; 583 reg |= ((dmac << IGC_DMACR_DMACTHR_SHIFT) 584 & IGC_DMACR_DMACTHR_MASK); 585 586 /* transition to L0x or L1 if available..*/ 587 reg |= (IGC_DMACR_DMAC_EN | IGC_DMACR_DMAC_LX_MASK); 588 589 /* Check if status is 2.5Gb backplane connection 590 * before configuration of watchdog timer, which is 591 * in msec values in 12.8usec intervals 592 * watchdog timer= msec values in 32usec intervals 593 * for non 2.5Gb connection 594 */ 595 status = IGC_READ_REG(hw, IGC_STATUS); 596 if ((status & IGC_STATUS_2P5_SKU) && 597 (!(status & IGC_STATUS_2P5_SKU_OVER))) 598 reg |= ((sc->dmac * 5) >> 6); 599 else 600 reg |= (sc->dmac >> 5); 601 602 IGC_WRITE_REG(hw, IGC_DMACR, reg); 603 604 IGC_WRITE_REG(hw, IGC_DMCRTRH, 0); 605 606 /* Set the interval before transition */ 607 reg = IGC_READ_REG(hw, IGC_DMCTLX); 608 reg |= IGC_DMCTLX_DCFLUSH_DIS; 609 610 /* 611 ** in 2.5Gb connection, TTLX unit is 0.4 usec 612 ** which is 0x4*2 = 0xA. But delay is still 4 usec 613 */ 614 status = IGC_READ_REG(hw, IGC_STATUS); 615 if ((status & IGC_STATUS_2P5_SKU) && 616 (!(status & IGC_STATUS_2P5_SKU_OVER))) 617 reg |= 0xA; 618 else 619 reg |= 0x4; 620 621 IGC_WRITE_REG(hw, IGC_DMCTLX, reg); 622 623 /* free space in tx packet buffer to wake from DMA coal */ 624 IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE - 625 (2 * max_frame_size)) >> 6); 626 627 /* make low power state decision controlled by DMA coal */ 628 reg = IGC_READ_REG(hw, IGC_PCIEMISC); 629 reg &= ~IGC_PCIEMISC_LX_DECISION; 630 IGC_WRITE_REG(hw, IGC_PCIEMISC, reg); 631 } 632 633 int 634 igc_allocate_msix(struct igc_softc *sc) 635 { 636 struct igc_osdep *os = &sc->osdep; 637 struct pci_attach_args *pa = &os->os_pa; 638 struct igc_queue *iq; 639 pci_intr_handle_t ih; 640 int i, error = 0; 641 642 for (i = 0, iq = sc->queues; i < sc->sc_nqueues; i++, iq++) { 643 if (pci_intr_map_msix(pa, i, &ih)) { 644 printf("%s: unable to map msi-x vector %d\n", 645 DEVNAME(sc), i); 646 error = ENOMEM; 647 goto fail; 648 } 649 650 iq->tag = pci_intr_establish_cpu(pa->pa_pc, ih, 651 IPL_NET | IPL_MPSAFE, intrmap_cpu(sc->sc_intrmap, i), 652 igc_intr_queue, iq, iq->name); 653 if (iq->tag == NULL) { 654 printf("%s: unable to establish interrupt %d\n", 655 DEVNAME(sc), i); 656 error = ENOMEM; 657 goto fail; 658 } 659 660 iq->msix = i; 661 iq->eims = 1 << i; 662 } 663 664 /* Now the link status/control last MSI-X vector. */ 665 if (pci_intr_map_msix(pa, i, &ih)) { 666 printf("%s: unable to map link vector\n", DEVNAME(sc)); 667 error = ENOMEM; 668 goto fail; 669 } 670 671 sc->tag = pci_intr_establish(pa->pa_pc, ih, IPL_NET | IPL_MPSAFE, 672 igc_intr_link, sc, sc->sc_dev.dv_xname); 673 if (sc->tag == NULL) { 674 printf("%s: unable to establish link interrupt\n", DEVNAME(sc)); 675 error = ENOMEM; 676 goto fail; 677 } 678 679 sc->linkvec = i; 680 printf(", %s, %d queue%s", pci_intr_string(pa->pa_pc, ih), 681 i, (i > 1) ? "s" : ""); 682 683 return 0; 684 fail: 685 for (iq = sc->queues; i > 0; i--, iq++) { 686 if (iq->tag == NULL) 687 continue; 688 pci_intr_disestablish(pa->pa_pc, iq->tag); 689 iq->tag = NULL; 690 } 691 692 return error; 693 } 694 695 void 696 igc_setup_msix(struct igc_softc *sc) 697 { 698 struct igc_osdep *os = &sc->osdep; 699 struct pci_attach_args *pa = &os->os_pa; 700 int nmsix; 701 702 nmsix = pci_intr_msix_count(pa); 703 if (nmsix <= 1) 704 printf(": not enough msi-x vectors\n"); 705 706 /* Give one vector to events. */ 707 nmsix--; 708 709 sc->sc_intrmap = intrmap_create(&sc->sc_dev, nmsix, IGC_MAX_VECTORS, 710 INTRMAP_POWEROF2); 711 sc->sc_nqueues = intrmap_count(sc->sc_intrmap); 712 } 713 714 int 715 igc_dma_malloc(struct igc_softc *sc, bus_size_t size, struct igc_dma_alloc *dma) 716 { 717 struct igc_osdep *os = &sc->osdep; 718 719 dma->dma_tag = os->os_pa.pa_dmat; 720 721 if (bus_dmamap_create(dma->dma_tag, size, 1, size, 0, BUS_DMA_NOWAIT, 722 &dma->dma_map)) 723 return 1; 724 if (bus_dmamem_alloc(dma->dma_tag, size, PAGE_SIZE, 0, &dma->dma_seg, 725 1, &dma->dma_nseg, BUS_DMA_NOWAIT)) 726 goto destroy; 727 if (bus_dmamem_map(dma->dma_tag, &dma->dma_seg, dma->dma_nseg, size, 728 &dma->dma_vaddr, BUS_DMA_NOWAIT)) 729 goto free; 730 if (bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size, 731 NULL, BUS_DMA_NOWAIT)) 732 goto unmap; 733 734 dma->dma_size = size; 735 736 return 0; 737 unmap: 738 bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size); 739 free: 740 bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg); 741 destroy: 742 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 743 dma->dma_map = NULL; 744 dma->dma_tag = NULL; 745 return 1; 746 } 747 748 void 749 igc_dma_free(struct igc_softc *sc, struct igc_dma_alloc *dma) 750 { 751 if (dma->dma_tag == NULL) 752 return; 753 754 if (dma->dma_map != NULL) { 755 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, 756 dma->dma_map->dm_mapsize, 757 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 758 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 759 bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, dma->dma_size); 760 bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg); 761 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 762 dma->dma_map = NULL; 763 } 764 } 765 766 /********************************************************************* 767 * 768 * Setup networking device structure and register an interface. 769 * 770 **********************************************************************/ 771 void 772 igc_setup_interface(struct igc_softc *sc) 773 { 774 struct ifnet *ifp = &sc->sc_ac.ac_if; 775 int i; 776 777 ifp->if_softc = sc; 778 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 779 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 780 ifp->if_xflags = IFXF_MPSAFE; 781 ifp->if_ioctl = igc_ioctl; 782 ifp->if_qstart = igc_start; 783 ifp->if_watchdog = igc_watchdog; 784 ifp->if_hardmtu = sc->hw.mac.max_frame_size - ETHER_HDR_LEN - 785 ETHER_CRC_LEN; 786 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1); 787 788 ifp->if_capabilities = IFCAP_VLAN_MTU; 789 790 #if NVLAN > 0 791 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 792 #endif 793 794 ifp->if_capabilities |= IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 795 796 /* Initialize ifmedia structures. */ 797 ifmedia_init(&sc->media, IFM_IMASK, igc_media_change, igc_media_status); 798 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 799 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 800 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 801 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 802 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 803 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 804 ifmedia_add(&sc->media, IFM_ETHER | IFM_2500_T, 0, NULL); 805 806 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 807 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 808 809 if_attach(ifp); 810 ether_ifattach(ifp); 811 812 if_attach_queues(ifp, sc->sc_nqueues); 813 if_attach_iqueues(ifp, sc->sc_nqueues); 814 for (i = 0; i < sc->sc_nqueues; i++) { 815 struct ifqueue *ifq = ifp->if_ifqs[i]; 816 struct ifiqueue *ifiq = ifp->if_iqs[i]; 817 struct tx_ring *txr = &sc->tx_rings[i]; 818 struct rx_ring *rxr = &sc->rx_rings[i]; 819 820 ifq->ifq_softc = txr; 821 txr->ifq = ifq; 822 823 ifiq->ifiq_softc = rxr; 824 rxr->ifiq = ifiq; 825 } 826 } 827 828 void 829 igc_init(void *arg) 830 { 831 struct igc_softc *sc = (struct igc_softc *)arg; 832 struct ifnet *ifp = &sc->sc_ac.ac_if; 833 struct rx_ring *rxr; 834 uint32_t ctrl = 0; 835 int i, s; 836 837 s = splnet(); 838 839 igc_stop(sc); 840 841 /* Get the latest mac address, user can use a LAA. */ 842 bcopy(sc->sc_ac.ac_enaddr, sc->hw.mac.addr, ETHER_ADDR_LEN); 843 844 /* Put the address into the receive address array. */ 845 igc_rar_set(&sc->hw, sc->hw.mac.addr, 0); 846 847 /* Initialize the hardware. */ 848 igc_reset(sc); 849 igc_update_link_status(sc); 850 851 /* Setup VLAN support, basic and offload if available. */ 852 IGC_WRITE_REG(&sc->hw, IGC_VET, ETHERTYPE_VLAN); 853 854 /* Prepare transmit descriptors and buffers. */ 855 if (igc_setup_transmit_structures(sc)) { 856 printf("%s: Could not setup transmit structures\n", 857 DEVNAME(sc)); 858 igc_stop(sc); 859 splx(s); 860 return; 861 } 862 igc_initialize_transmit_unit(sc); 863 864 sc->rx_mbuf_sz = MCLBYTES + ETHER_ALIGN; 865 /* Prepare receive descriptors and buffers. */ 866 if (igc_setup_receive_structures(sc)) { 867 printf("%s: Could not setup receive structures\n", 868 DEVNAME(sc)); 869 igc_stop(sc); 870 splx(s); 871 return; 872 } 873 igc_initialize_receive_unit(sc); 874 875 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) { 876 ctrl = IGC_READ_REG(&sc->hw, IGC_CTRL); 877 ctrl |= IGC_CTRL_VME; 878 IGC_WRITE_REG(&sc->hw, IGC_CTRL, ctrl); 879 } 880 881 /* Setup multicast table. */ 882 igc_iff(sc); 883 884 igc_clear_hw_cntrs_base_generic(&sc->hw); 885 886 igc_configure_queues(sc); 887 888 /* This clears any pending interrupts */ 889 IGC_READ_REG(&sc->hw, IGC_ICR); 890 IGC_WRITE_REG(&sc->hw, IGC_ICS, IGC_ICS_LSC); 891 892 /* The driver can now take control from firmware. */ 893 igc_get_hw_control(sc); 894 895 /* Set Energy Efficient Ethernet. */ 896 igc_set_eee_i225(&sc->hw, true, true, true); 897 898 for (i = 0; i < sc->sc_nqueues; i++) { 899 rxr = &sc->rx_rings[i]; 900 igc_rxfill(rxr); 901 if (if_rxr_inuse(&rxr->rx_ring) == 0) { 902 printf("%s: Unable to fill any rx descriptors\n", 903 DEVNAME(sc)); 904 igc_stop(sc); 905 splx(s); 906 } 907 IGC_WRITE_REG(&sc->hw, IGC_RDT(i), 908 (rxr->last_desc_filled + 1) % sc->num_rx_desc); 909 } 910 911 igc_enable_intr(sc); 912 913 ifp->if_flags |= IFF_RUNNING; 914 for (i = 0; i < sc->sc_nqueues; i++) 915 ifq_clr_oactive(ifp->if_ifqs[i]); 916 917 splx(s); 918 } 919 920 static inline int 921 igc_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, struct mbuf *m) 922 { 923 int error; 924 925 error = bus_dmamap_load_mbuf(dmat, map, m, 926 BUS_DMA_STREAMING | BUS_DMA_NOWAIT); 927 if (error != EFBIG) 928 return (error); 929 930 error = m_defrag(m, M_DONTWAIT); 931 if (error != 0) 932 return (error); 933 934 return (bus_dmamap_load_mbuf(dmat, map, m, 935 BUS_DMA_STREAMING | BUS_DMA_NOWAIT)); 936 } 937 938 void 939 igc_start(struct ifqueue *ifq) 940 { 941 struct ifnet *ifp = ifq->ifq_if; 942 struct igc_softc *sc = ifp->if_softc; 943 struct tx_ring *txr = ifq->ifq_softc; 944 union igc_adv_tx_desc *txdesc; 945 struct igc_tx_buf *txbuf; 946 bus_dmamap_t map; 947 struct mbuf *m; 948 unsigned int prod, free, last, i; 949 unsigned int mask; 950 uint32_t cmd_type_len; 951 uint32_t olinfo_status; 952 int post = 0; 953 #if NBPFILTER > 0 954 caddr_t if_bpf; 955 #endif 956 957 if (!sc->link_active) { 958 ifq_purge(ifq); 959 return; 960 } 961 962 prod = txr->next_avail_desc; 963 free = txr->next_to_clean; 964 if (free <= prod) 965 free += sc->num_tx_desc; 966 free -= prod; 967 968 bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0, 969 txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 970 971 mask = sc->num_tx_desc - 1; 972 973 for (;;) { 974 if (free <= IGC_MAX_SCATTER) { 975 ifq_set_oactive(ifq); 976 break; 977 } 978 979 m = ifq_dequeue(ifq); 980 if (m == NULL) 981 break; 982 983 txbuf = &txr->tx_buffers[prod]; 984 map = txbuf->map; 985 986 if (igc_load_mbuf(txr->txdma.dma_tag, map, m) != 0) { 987 ifq->ifq_errors++; 988 m_freem(m); 989 continue; 990 } 991 992 olinfo_status = m->m_pkthdr.len << IGC_ADVTXD_PAYLEN_SHIFT; 993 994 bus_dmamap_sync(txr->txdma.dma_tag, map, 0, 995 map->dm_mapsize, BUS_DMASYNC_PREWRITE); 996 997 for (i = 0; i < map->dm_nsegs; i++) { 998 txdesc = &txr->tx_base[prod]; 999 1000 cmd_type_len = IGC_ADVTXD_DCMD_IFCS | IGC_ADVTXD_DTYP_DATA | 1001 IGC_ADVTXD_DCMD_DEXT | map->dm_segs[i].ds_len; 1002 if (i == map->dm_nsegs - 1) 1003 cmd_type_len |= IGC_ADVTXD_DCMD_EOP | 1004 IGC_ADVTXD_DCMD_RS; 1005 1006 htolem64(&txdesc->read.buffer_addr, map->dm_segs[i].ds_addr); 1007 htolem32(&txdesc->read.cmd_type_len, cmd_type_len); 1008 htolem32(&txdesc->read.olinfo_status, olinfo_status); 1009 1010 last = prod; 1011 1012 prod++; 1013 prod &= mask; 1014 } 1015 1016 txbuf->m_head = m; 1017 txbuf->eop_index = last; 1018 1019 #if NBPFILTER > 0 1020 if_bpf = ifp->if_bpf; 1021 if (if_bpf) 1022 bpf_mtap_ether(if_bpf, m, BPF_DIRECTION_OUT); 1023 #endif 1024 1025 free -= i; 1026 post = 1; 1027 } 1028 1029 bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0, 1030 txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1031 1032 if (post) { 1033 txr->next_avail_desc = prod; 1034 IGC_WRITE_REG(&sc->hw, IGC_TDT(txr->me), prod); 1035 } 1036 } 1037 1038 int 1039 igc_txeof(struct tx_ring *txr) 1040 { 1041 struct igc_softc *sc = txr->sc; 1042 struct ifqueue *ifq = txr->ifq; 1043 union igc_adv_tx_desc *txdesc; 1044 struct igc_tx_buf *txbuf; 1045 bus_dmamap_t map; 1046 unsigned int cons, prod, last; 1047 unsigned int mask; 1048 int done = 0; 1049 1050 prod = txr->next_avail_desc; 1051 cons = txr->next_to_clean; 1052 1053 if (cons == prod) 1054 return (0); 1055 1056 bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0, 1057 txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1058 1059 mask = sc->num_tx_desc - 1; 1060 1061 do { 1062 txbuf = &txr->tx_buffers[cons]; 1063 last = txbuf->eop_index; 1064 txdesc = &txr->tx_base[last]; 1065 1066 if (!(txdesc->wb.status & htole32(IGC_TXD_STAT_DD))) 1067 break; 1068 1069 map = txbuf->map; 1070 1071 bus_dmamap_sync(txr->txdma.dma_tag, map, 0, map->dm_mapsize, 1072 BUS_DMASYNC_POSTWRITE); 1073 bus_dmamap_unload(txr->txdma.dma_tag, map); 1074 m_freem(txbuf->m_head); 1075 1076 txbuf->m_head = NULL; 1077 txbuf->eop_index = -1; 1078 1079 cons = last + 1; 1080 cons &= mask; 1081 1082 done = 1; 1083 } while (cons != prod); 1084 1085 bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0, 1086 txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1087 1088 txr->next_to_clean = cons; 1089 1090 if (ifq_is_oactive(ifq)) 1091 ifq_restart(ifq); 1092 1093 return (done); 1094 } 1095 1096 /********************************************************************* 1097 * 1098 * This routine disables all traffic on the adapter by issuing a 1099 * global reset on the MAC. 1100 * 1101 **********************************************************************/ 1102 void 1103 igc_stop(struct igc_softc *sc) 1104 { 1105 struct ifnet *ifp = &sc->sc_ac.ac_if; 1106 int i; 1107 1108 /* Tell the stack that the interface is no longer active. */ 1109 ifp->if_flags &= ~IFF_RUNNING; 1110 1111 igc_disable_intr(sc); 1112 1113 igc_reset_hw(&sc->hw); 1114 IGC_WRITE_REG(&sc->hw, IGC_WUC, 0); 1115 1116 intr_barrier(sc->tag); 1117 for (i = 0; i < sc->sc_nqueues; i++) { 1118 struct ifqueue *ifq = ifp->if_ifqs[i]; 1119 ifq_barrier(ifq); 1120 ifq_clr_oactive(ifq); 1121 1122 if (sc->queues[i].tag != NULL) 1123 intr_barrier(sc->queues[i].tag); 1124 timeout_del(&sc->rx_rings[i].rx_refill); 1125 } 1126 1127 igc_free_transmit_structures(sc); 1128 igc_free_receive_structures(sc); 1129 1130 igc_update_link_status(sc); 1131 } 1132 1133 /********************************************************************* 1134 * Ioctl entry point 1135 * 1136 * igc_ioctl is called when the user wants to configure the 1137 * interface. 1138 * 1139 * return 0 on success, positive on failure 1140 **********************************************************************/ 1141 int 1142 igc_ioctl(struct ifnet * ifp, u_long cmd, caddr_t data) 1143 { 1144 struct igc_softc *sc = ifp->if_softc; 1145 struct ifreq *ifr = (struct ifreq *)data; 1146 int s, error = 0; 1147 1148 s = splnet(); 1149 1150 switch (cmd) { 1151 case SIOCSIFADDR: 1152 ifp->if_flags |= IFF_UP; 1153 if (!(ifp->if_flags & IFF_RUNNING)) 1154 igc_init(sc); 1155 break; 1156 case SIOCSIFFLAGS: 1157 if (ifp->if_flags & IFF_UP) { 1158 if (ifp->if_flags & IFF_RUNNING) 1159 error = ENETRESET; 1160 else 1161 igc_init(sc); 1162 } else { 1163 if (ifp->if_flags & IFF_RUNNING) 1164 igc_stop(sc); 1165 } 1166 break; 1167 case SIOCSIFMEDIA: 1168 case SIOCGIFMEDIA: 1169 error = ifmedia_ioctl(ifp, ifr, &sc->media, cmd); 1170 break; 1171 case SIOCGIFRXR: 1172 error = igc_rxrinfo(sc, (struct if_rxrinfo *)ifr->ifr_data); 1173 break; 1174 default: 1175 error = ether_ioctl(ifp, &sc->sc_ac, cmd, data); 1176 } 1177 1178 if (error == ENETRESET) { 1179 if (ifp->if_flags & IFF_RUNNING) { 1180 igc_disable_intr(sc); 1181 igc_iff(sc); 1182 igc_enable_intr(sc); 1183 } 1184 error = 0; 1185 } 1186 1187 splx(s); 1188 return error; 1189 } 1190 1191 int 1192 igc_rxrinfo(struct igc_softc *sc, struct if_rxrinfo *ifri) 1193 { 1194 struct if_rxring_info *ifr, ifr1; 1195 struct rx_ring *rxr; 1196 int error, i, n = 0; 1197 1198 if (sc->sc_nqueues > 1) { 1199 if ((ifr = mallocarray(sc->sc_nqueues, sizeof(*ifr), M_DEVBUF, 1200 M_WAITOK | M_ZERO)) == NULL) 1201 return ENOMEM; 1202 } else 1203 ifr = &ifr1; 1204 1205 for (i = 0; i < sc->sc_nqueues; i++) { 1206 rxr = &sc->rx_rings[i]; 1207 ifr[n].ifr_size = MCLBYTES; 1208 snprintf(ifr[n].ifr_name, sizeof(ifr[n].ifr_name), "%d", i); 1209 ifr[n].ifr_info = rxr->rx_ring; 1210 n++; 1211 } 1212 1213 error = if_rxr_info_ioctl(ifri, sc->sc_nqueues, ifr); 1214 if (sc->sc_nqueues > 1) 1215 free(ifr, M_DEVBUF, sc->sc_nqueues * sizeof(*ifr)); 1216 1217 return error; 1218 } 1219 1220 int 1221 igc_rxfill(struct rx_ring *rxr) 1222 { 1223 struct igc_softc *sc = rxr->sc; 1224 int i, post = 0; 1225 u_int slots; 1226 1227 bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0, 1228 rxr->rxdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1229 1230 i = rxr->last_desc_filled; 1231 for (slots = if_rxr_get(&rxr->rx_ring, sc->num_rx_desc); slots > 0; 1232 slots--) { 1233 if (++i == sc->num_rx_desc) 1234 i = 0; 1235 1236 if (igc_get_buf(rxr, i) != 0) 1237 break; 1238 1239 rxr->last_desc_filled = i; 1240 post = 1; 1241 } 1242 1243 bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0, 1244 rxr->rxdma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1245 1246 if_rxr_put(&rxr->rx_ring, slots); 1247 1248 return post; 1249 } 1250 1251 void 1252 igc_rxrefill(void *xrxr) 1253 { 1254 struct rx_ring *rxr = xrxr; 1255 struct igc_softc *sc = rxr->sc; 1256 1257 if (igc_rxfill(rxr)) { 1258 IGC_WRITE_REG(&sc->hw, IGC_RDT(rxr->me), 1259 (rxr->last_desc_filled + 1) % sc->num_rx_desc); 1260 } 1261 else if (if_rxr_inuse(&rxr->rx_ring) == 0) 1262 timeout_add(&rxr->rx_refill, 1); 1263 } 1264 1265 /********************************************************************* 1266 * 1267 * This routine executes in interrupt context. It replenishes 1268 * the mbufs in the descriptor and sends data which has been 1269 * dma'ed into host memory to upper layer. 1270 * 1271 *********************************************************************/ 1272 int 1273 igc_rxeof(struct rx_ring *rxr) 1274 { 1275 struct igc_softc *sc = rxr->sc; 1276 struct ifnet *ifp = &sc->sc_ac.ac_if; 1277 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1278 struct mbuf *mp, *m; 1279 struct igc_rx_buf *rxbuf, *nxbuf; 1280 union igc_adv_rx_desc *rxdesc; 1281 uint32_t ptype, staterr = 0; 1282 uint16_t len, vtag; 1283 uint8_t eop = 0; 1284 int i; 1285 1286 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 1287 return 0; 1288 1289 i = rxr->next_to_check; 1290 while (if_rxr_inuse(&rxr->rx_ring) > 0) { 1291 uint32_t hash; 1292 uint16_t hashtype; 1293 1294 bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 1295 i * sizeof(union igc_adv_rx_desc), 1296 sizeof(union igc_adv_rx_desc), BUS_DMASYNC_POSTREAD); 1297 1298 rxdesc = &rxr->rx_base[i]; 1299 staterr = letoh32(rxdesc->wb.upper.status_error); 1300 if (!ISSET(staterr, IGC_RXD_STAT_DD)) { 1301 bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 1302 i * sizeof(union igc_adv_rx_desc), 1303 sizeof(union igc_adv_rx_desc), BUS_DMASYNC_PREREAD); 1304 break; 1305 } 1306 1307 /* Zero out the receive descriptors status. */ 1308 rxdesc->wb.upper.status_error = 0; 1309 rxbuf = &rxr->rx_buffers[i]; 1310 1311 /* Pull the mbuf off the ring. */ 1312 bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->map, 0, 1313 rxbuf->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1314 bus_dmamap_unload(rxr->rxdma.dma_tag, rxbuf->map); 1315 1316 mp = rxbuf->buf; 1317 len = letoh16(rxdesc->wb.upper.length); 1318 vtag = letoh16(rxdesc->wb.upper.vlan); 1319 eop = ((staterr & IGC_RXD_STAT_EOP) == IGC_RXD_STAT_EOP); 1320 ptype = letoh32(rxdesc->wb.lower.lo_dword.data) & 1321 IGC_PKTTYPE_MASK; 1322 hash = letoh32(rxdesc->wb.lower.hi_dword.rss); 1323 hashtype = le16toh(rxdesc->wb.lower.lo_dword.hs_rss.pkt_info) & 1324 IGC_RXDADV_RSSTYPE_MASK; 1325 1326 if (staterr & IGC_RXDEXT_STATERR_RXE) { 1327 if (rxbuf->fmp) { 1328 m_freem(rxbuf->fmp); 1329 rxbuf->fmp = NULL; 1330 } 1331 1332 m_freem(mp); 1333 rxbuf->buf = NULL; 1334 goto next_desc; 1335 } 1336 1337 if (mp == NULL) { 1338 panic("%s: igc_rxeof: NULL mbuf in slot %d " 1339 "(nrx %d, filled %d)", DEVNAME(sc), i, 1340 if_rxr_inuse(&rxr->rx_ring), rxr->last_desc_filled); 1341 } 1342 1343 mp->m_len = len; 1344 1345 m = rxbuf->fmp; 1346 rxbuf->buf = rxbuf->fmp = NULL; 1347 1348 if (m != NULL) 1349 m->m_pkthdr.len += mp->m_len; 1350 else { 1351 m = mp; 1352 m->m_pkthdr.len = mp->m_len; 1353 #if NVLAN > 0 1354 if (staterr & IGC_RXD_STAT_VP) { 1355 m->m_pkthdr.ether_vtag = vtag; 1356 m->m_flags |= M_VLANTAG; 1357 } 1358 #endif 1359 } 1360 1361 /* Pass the head pointer on */ 1362 if (eop == 0) { 1363 nxbuf->fmp = m; 1364 m = NULL; 1365 mp->m_next = nxbuf->buf; 1366 } else { 1367 igc_rx_checksum(staterr, m, ptype); 1368 1369 if (hashtype != IGC_RXDADV_RSSTYPE_NONE) { 1370 m->m_pkthdr.ph_flowid = hash; 1371 SET(m->m_pkthdr.csum_flags, M_FLOWID); 1372 } 1373 1374 ml_enqueue(&ml, m); 1375 } 1376 next_desc: 1377 if_rxr_put(&rxr->rx_ring, 1); 1378 bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 1379 i * sizeof(union igc_adv_rx_desc), 1380 sizeof(union igc_adv_rx_desc), BUS_DMASYNC_PREREAD); 1381 1382 /* Advance our pointers to the next descriptor. */ 1383 if (++i == sc->num_rx_desc) 1384 i = 0; 1385 } 1386 rxr->next_to_check = i; 1387 1388 if (ifiq_input(rxr->ifiq, &ml)) 1389 if_rxr_livelocked(&rxr->rx_ring); 1390 1391 if (!(staterr & IGC_RXD_STAT_DD)) 1392 return 0; 1393 1394 return 1; 1395 } 1396 1397 /********************************************************************* 1398 * 1399 * Verify that the hardware indicated that the checksum is valid. 1400 * Inform the stack about the status of checksum so that stack 1401 * doesn't spend time verifying the checksum. 1402 * 1403 *********************************************************************/ 1404 void 1405 igc_rx_checksum(uint32_t staterr, struct mbuf *m, uint32_t ptype) 1406 { 1407 uint16_t status = (uint16_t)staterr; 1408 uint8_t errors = (uint8_t)(staterr >> 24); 1409 1410 if (status & IGC_RXD_STAT_IPCS) { 1411 if (!(errors & IGC_RXD_ERR_IPE)) { 1412 /* IP Checksum Good */ 1413 m->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 1414 } else 1415 m->m_pkthdr.csum_flags = 0; 1416 } 1417 1418 if (status & (IGC_RXD_STAT_TCPCS | IGC_RXD_STAT_UDPCS)) { 1419 if (!(errors & IGC_RXD_ERR_TCPE)) 1420 m->m_pkthdr.csum_flags |= 1421 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1422 } 1423 } 1424 1425 void 1426 igc_watchdog(struct ifnet * ifp) 1427 { 1428 } 1429 1430 /********************************************************************* 1431 * 1432 * Media Ioctl callback 1433 * 1434 * This routine is called whenever the user queries the status of 1435 * the interface using ifconfig. 1436 * 1437 **********************************************************************/ 1438 void 1439 igc_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1440 { 1441 struct igc_softc *sc = ifp->if_softc; 1442 1443 igc_update_link_status(sc); 1444 1445 ifmr->ifm_status = IFM_AVALID; 1446 ifmr->ifm_active = IFM_ETHER; 1447 1448 if (!sc->link_active) { 1449 ifmr->ifm_active |= IFM_NONE; 1450 return; 1451 } 1452 1453 ifmr->ifm_status |= IFM_ACTIVE; 1454 1455 switch (sc->link_speed) { 1456 case 10: 1457 ifmr->ifm_active |= IFM_10_T; 1458 break; 1459 case 100: 1460 ifmr->ifm_active |= IFM_100_TX; 1461 break; 1462 case 1000: 1463 ifmr->ifm_active |= IFM_1000_T; 1464 break; 1465 case 2500: 1466 ifmr->ifm_active |= IFM_2500_T; 1467 break; 1468 } 1469 1470 if (sc->link_duplex == FULL_DUPLEX) 1471 ifmr->ifm_active |= IFM_FDX; 1472 else 1473 ifmr->ifm_active |= IFM_HDX; 1474 } 1475 1476 /********************************************************************* 1477 * 1478 * Media Ioctl callback 1479 * 1480 * This routine is called when the user changes speed/duplex using 1481 * media/mediopt option with ifconfig. 1482 * 1483 **********************************************************************/ 1484 int 1485 igc_media_change(struct ifnet *ifp) 1486 { 1487 struct igc_softc *sc = ifp->if_softc; 1488 struct ifmedia *ifm = &sc->media; 1489 1490 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1491 return (EINVAL); 1492 1493 sc->hw.mac.autoneg = DO_AUTO_NEG; 1494 1495 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1496 case IFM_AUTO: 1497 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1498 break; 1499 case IFM_2500_T: 1500 sc->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL; 1501 break; 1502 case IFM_1000_T: 1503 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1504 break; 1505 case IFM_100_TX: 1506 if ((ifm->ifm_media & IFM_GMASK) == IFM_HDX) 1507 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; 1508 else 1509 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; 1510 break; 1511 case IFM_10_T: 1512 if ((ifm->ifm_media & IFM_GMASK) == IFM_HDX) 1513 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; 1514 else 1515 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; 1516 break; 1517 default: 1518 return EINVAL; 1519 } 1520 1521 igc_init(sc); 1522 1523 return 0; 1524 } 1525 1526 void 1527 igc_iff(struct igc_softc *sc) 1528 { 1529 struct ifnet *ifp = &sc->sc_ac.ac_if; 1530 struct arpcom *ac = &sc->sc_ac; 1531 struct ether_multi *enm; 1532 struct ether_multistep step; 1533 uint32_t reg_rctl = 0; 1534 uint8_t *mta; 1535 int mcnt = 0; 1536 1537 mta = sc->mta; 1538 bzero(mta, sizeof(uint8_t) * ETHER_ADDR_LEN * 1539 MAX_NUM_MULTICAST_ADDRESSES); 1540 1541 reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL); 1542 reg_rctl &= ~(IGC_RCTL_UPE | IGC_RCTL_MPE); 1543 ifp->if_flags &= ~IFF_ALLMULTI; 1544 1545 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0 || 1546 ac->ac_multicnt > MAX_NUM_MULTICAST_ADDRESSES) { 1547 ifp->if_flags |= IFF_ALLMULTI; 1548 reg_rctl |= IGC_RCTL_MPE; 1549 if (ifp->if_flags & IFF_PROMISC) 1550 reg_rctl |= IGC_RCTL_UPE; 1551 } else { 1552 ETHER_FIRST_MULTI(step, ac, enm); 1553 while (enm != NULL) { 1554 bcopy(enm->enm_addrlo, 1555 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1556 mcnt++; 1557 1558 ETHER_NEXT_MULTI(step, enm); 1559 } 1560 1561 igc_update_mc_addr_list(&sc->hw, mta, mcnt); 1562 } 1563 1564 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl); 1565 } 1566 1567 void 1568 igc_update_link_status(struct igc_softc *sc) 1569 { 1570 struct ifnet *ifp = &sc->sc_ac.ac_if; 1571 struct igc_hw *hw = &sc->hw; 1572 int link_state; 1573 1574 if (IGC_READ_REG(&sc->hw, IGC_STATUS) & IGC_STATUS_LU) { 1575 if (sc->link_active == 0) { 1576 igc_get_speed_and_duplex(hw, &sc->link_speed, 1577 &sc->link_duplex); 1578 sc->link_active = 1; 1579 ifp->if_baudrate = IF_Mbps(sc->link_speed); 1580 } 1581 link_state = (sc->link_duplex == FULL_DUPLEX) ? 1582 LINK_STATE_FULL_DUPLEX : LINK_STATE_HALF_DUPLEX; 1583 } else { 1584 if (sc->link_active == 1) { 1585 ifp->if_baudrate = sc->link_speed = 0; 1586 sc->link_duplex = 0; 1587 sc->link_active = 0; 1588 } 1589 link_state = LINK_STATE_DOWN; 1590 } 1591 if (ifp->if_link_state != link_state) { 1592 ifp->if_link_state = link_state; 1593 if_link_state_change(ifp); 1594 } 1595 } 1596 1597 /********************************************************************* 1598 * 1599 * Get a buffer from system mbuf buffer pool. 1600 * 1601 **********************************************************************/ 1602 int 1603 igc_get_buf(struct rx_ring *rxr, int i) 1604 { 1605 struct igc_softc *sc = rxr->sc; 1606 struct igc_rx_buf *rxbuf; 1607 struct mbuf *m; 1608 union igc_adv_rx_desc *rxdesc; 1609 int error; 1610 1611 rxbuf = &rxr->rx_buffers[i]; 1612 rxdesc = &rxr->rx_base[i]; 1613 if (rxbuf->buf) { 1614 printf("%s: slot %d already has an mbuf\n", DEVNAME(sc), i); 1615 return ENOBUFS; 1616 } 1617 1618 m = MCLGETL(NULL, M_DONTWAIT, sc->rx_mbuf_sz); 1619 if (!m) 1620 return ENOBUFS; 1621 1622 m->m_data += (m->m_ext.ext_size - sc->rx_mbuf_sz); 1623 m->m_len = m->m_pkthdr.len = sc->rx_mbuf_sz; 1624 1625 error = bus_dmamap_load_mbuf(rxr->rxdma.dma_tag, rxbuf->map, m, 1626 BUS_DMA_NOWAIT); 1627 if (error) { 1628 m_freem(m); 1629 return error; 1630 } 1631 1632 bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->map, 0, 1633 rxbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1634 rxbuf->buf = m; 1635 1636 rxdesc->read.pkt_addr = htole64(rxbuf->map->dm_segs[0].ds_addr); 1637 1638 return 0; 1639 } 1640 1641 void 1642 igc_configure_queues(struct igc_softc *sc) 1643 { 1644 struct igc_hw *hw = &sc->hw; 1645 struct igc_queue *iq = sc->queues; 1646 uint32_t ivar, newitr = 0; 1647 int i; 1648 1649 /* First turn on RSS capability */ 1650 IGC_WRITE_REG(hw, IGC_GPIE, IGC_GPIE_MSIX_MODE | IGC_GPIE_EIAME | 1651 IGC_GPIE_PBA | IGC_GPIE_NSICR); 1652 1653 /* Set the starting interrupt rate */ 1654 newitr = (4000000 / MAX_INTS_PER_SEC) & 0x7FFC; 1655 1656 newitr |= IGC_EITR_CNT_IGNR; 1657 1658 /* Turn on MSI-X */ 1659 for (i = 0; i < sc->sc_nqueues; i++, iq++) { 1660 /* RX entries */ 1661 igc_set_queues(sc, i, iq->msix, 0); 1662 /* TX entries */ 1663 igc_set_queues(sc, i, iq->msix, 1); 1664 sc->msix_queuesmask |= iq->eims; 1665 IGC_WRITE_REG(hw, IGC_EITR(iq->msix), newitr); 1666 } 1667 1668 /* And for the link interrupt */ 1669 ivar = (sc->linkvec | IGC_IVAR_VALID) << 8; 1670 sc->msix_linkmask = 1 << sc->linkvec; 1671 IGC_WRITE_REG(hw, IGC_IVAR_MISC, ivar); 1672 } 1673 1674 void 1675 igc_set_queues(struct igc_softc *sc, uint32_t entry, uint32_t vector, int type) 1676 { 1677 struct igc_hw *hw = &sc->hw; 1678 uint32_t ivar, index; 1679 1680 index = entry >> 1; 1681 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1682 if (type) { 1683 if (entry & 1) { 1684 ivar &= 0x00FFFFFF; 1685 ivar |= (vector | IGC_IVAR_VALID) << 24; 1686 } else { 1687 ivar &= 0xFFFF00FF; 1688 ivar |= (vector | IGC_IVAR_VALID) << 8; 1689 } 1690 } else { 1691 if (entry & 1) { 1692 ivar &= 0xFF00FFFF; 1693 ivar |= (vector | IGC_IVAR_VALID) << 16; 1694 } else { 1695 ivar &= 0xFFFFFF00; 1696 ivar |= vector | IGC_IVAR_VALID; 1697 } 1698 } 1699 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1700 } 1701 1702 void 1703 igc_enable_queue(struct igc_softc *sc, uint32_t eims) 1704 { 1705 IGC_WRITE_REG(&sc->hw, IGC_EIMS, eims); 1706 } 1707 1708 void 1709 igc_enable_intr(struct igc_softc *sc) 1710 { 1711 struct igc_hw *hw = &sc->hw; 1712 uint32_t mask; 1713 1714 mask = (sc->msix_queuesmask | sc->msix_linkmask); 1715 IGC_WRITE_REG(hw, IGC_EIAC, mask); 1716 IGC_WRITE_REG(hw, IGC_EIAM, mask); 1717 IGC_WRITE_REG(hw, IGC_EIMS, mask); 1718 IGC_WRITE_REG(hw, IGC_IMS, IGC_IMS_LSC); 1719 IGC_WRITE_FLUSH(hw); 1720 } 1721 1722 void 1723 igc_disable_intr(struct igc_softc *sc) 1724 { 1725 struct igc_hw *hw = &sc->hw; 1726 1727 IGC_WRITE_REG(hw, IGC_EIMC, 0xffffffff); 1728 IGC_WRITE_REG(hw, IGC_EIAC, 0); 1729 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 1730 IGC_WRITE_FLUSH(hw); 1731 } 1732 1733 int 1734 igc_intr_link(void *arg) 1735 { 1736 struct igc_softc *sc = (struct igc_softc *)arg; 1737 uint32_t reg_icr; 1738 1739 if (reg_icr & IGC_ICR_LSC) { 1740 KERNEL_LOCK(); 1741 sc->hw.mac.get_link_status = true; 1742 igc_update_link_status(sc); 1743 KERNEL_UNLOCK(); 1744 } 1745 1746 IGC_WRITE_REG(&sc->hw, IGC_IMS, IGC_IMS_LSC); 1747 IGC_WRITE_REG(&sc->hw, IGC_EIMS, sc->msix_linkmask); 1748 1749 return 1; 1750 } 1751 1752 int 1753 igc_intr_queue(void *arg) 1754 { 1755 struct igc_queue *iq = arg; 1756 struct igc_softc *sc = iq->sc; 1757 struct ifnet *ifp = &sc->sc_ac.ac_if; 1758 struct rx_ring *rxr = iq->rxr; 1759 struct tx_ring *txr = iq->txr; 1760 1761 if (ifp->if_flags & IFF_RUNNING) { 1762 igc_txeof(txr); 1763 igc_rxeof(rxr); 1764 igc_rxrefill(rxr); 1765 } 1766 1767 igc_enable_queue(sc, iq->eims); 1768 1769 return 1; 1770 } 1771 1772 /********************************************************************* 1773 * 1774 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1775 * the information needed to transmit a packet on the wire. 1776 * 1777 **********************************************************************/ 1778 int 1779 igc_allocate_transmit_buffers(struct tx_ring *txr) 1780 { 1781 struct igc_softc *sc = txr->sc; 1782 struct igc_tx_buf *txbuf; 1783 int error, i; 1784 1785 txr->tx_buffers = mallocarray(sc->num_tx_desc, 1786 sizeof(struct igc_tx_buf), M_DEVBUF, M_NOWAIT | M_ZERO); 1787 if (txr->tx_buffers == NULL) { 1788 printf("%s: Unable to allocate tx_buffer memory\n", 1789 DEVNAME(sc)); 1790 error = ENOMEM; 1791 goto fail; 1792 } 1793 txr->txtag = txr->txdma.dma_tag; 1794 1795 /* Create the descriptor buffer dma maps. */ 1796 for (i = 0; i < sc->num_tx_desc; i++) { 1797 txbuf = &txr->tx_buffers[i]; 1798 error = bus_dmamap_create(txr->txdma.dma_tag, IGC_TSO_SIZE, 1799 IGC_MAX_SCATTER, PAGE_SIZE, 0, BUS_DMA_NOWAIT, &txbuf->map); 1800 if (error != 0) { 1801 printf("%s: Unable to create TX DMA map\n", 1802 DEVNAME(sc)); 1803 goto fail; 1804 } 1805 } 1806 1807 return 0; 1808 fail: 1809 return error; 1810 } 1811 1812 1813 /********************************************************************* 1814 * 1815 * Allocate and initialize transmit structures. 1816 * 1817 **********************************************************************/ 1818 int 1819 igc_setup_transmit_structures(struct igc_softc *sc) 1820 { 1821 struct tx_ring *txr = sc->tx_rings; 1822 int i; 1823 1824 for (i = 0; i < sc->sc_nqueues; i++, txr++) { 1825 if (igc_setup_transmit_ring(txr)) 1826 goto fail; 1827 } 1828 1829 return 0; 1830 fail: 1831 igc_free_transmit_structures(sc); 1832 return ENOBUFS; 1833 } 1834 1835 /********************************************************************* 1836 * 1837 * Initialize a transmit ring. 1838 * 1839 **********************************************************************/ 1840 int 1841 igc_setup_transmit_ring(struct tx_ring *txr) 1842 { 1843 struct igc_softc *sc = txr->sc; 1844 1845 /* Now allocate transmit buffers for the ring. */ 1846 if (igc_allocate_transmit_buffers(txr)) 1847 return ENOMEM; 1848 1849 /* Clear the old ring contents */ 1850 bzero((void *)txr->tx_base, 1851 (sizeof(union igc_adv_tx_desc)) * sc->num_tx_desc); 1852 1853 /* Reset indices. */ 1854 txr->next_avail_desc = 0; 1855 txr->next_to_clean = 0; 1856 1857 bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0, 1858 txr->txdma.dma_map->dm_mapsize, 1859 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1860 1861 return 0; 1862 } 1863 1864 /********************************************************************* 1865 * 1866 * Enable transmit unit. 1867 * 1868 **********************************************************************/ 1869 void 1870 igc_initialize_transmit_unit(struct igc_softc *sc) 1871 { 1872 struct ifnet *ifp = &sc->sc_ac.ac_if; 1873 struct tx_ring *txr; 1874 struct igc_hw *hw = &sc->hw; 1875 uint64_t bus_addr; 1876 uint32_t tctl, txdctl = 0; 1877 int i; 1878 1879 /* Setup the Base and Length of the TX descriptor ring. */ 1880 for (i = 0; i < sc->sc_nqueues; i++) { 1881 txr = &sc->tx_rings[i]; 1882 1883 bus_addr = txr->txdma.dma_map->dm_segs[0].ds_addr; 1884 1885 /* Base and len of TX ring */ 1886 IGC_WRITE_REG(hw, IGC_TDLEN(i), 1887 sc->num_tx_desc * sizeof(union igc_adv_tx_desc)); 1888 IGC_WRITE_REG(hw, IGC_TDBAH(i), (uint32_t)(bus_addr >> 32)); 1889 IGC_WRITE_REG(hw, IGC_TDBAL(i), (uint32_t)bus_addr); 1890 1891 /* Init the HEAD/TAIL indices */ 1892 IGC_WRITE_REG(hw, IGC_TDT(i), 0); 1893 IGC_WRITE_REG(hw, IGC_TDH(i), 0); 1894 1895 txr->watchdog_timer = 0; 1896 1897 txdctl = 0; /* Clear txdctl */ 1898 txdctl |= 0x1f; /* PTHRESH */ 1899 txdctl |= 1 << 8; /* HTHRESH */ 1900 txdctl |= 1 << 16; /* WTHRESH */ 1901 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 1902 txdctl |= IGC_TXDCTL_GRAN; 1903 txdctl |= 1 << 25; /* LWTHRESH */ 1904 1905 IGC_WRITE_REG(hw, IGC_TXDCTL(i), txdctl); 1906 } 1907 ifp->if_timer = 0; 1908 1909 /* Program the Transmit Control Register */ 1910 tctl = IGC_READ_REG(&sc->hw, IGC_TCTL); 1911 tctl &= ~IGC_TCTL_CT; 1912 tctl |= (IGC_TCTL_PSP | IGC_TCTL_RTLC | IGC_TCTL_EN | 1913 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT)); 1914 1915 /* This write will effectively turn on the transmit unit. */ 1916 IGC_WRITE_REG(&sc->hw, IGC_TCTL, tctl); 1917 } 1918 1919 /********************************************************************* 1920 * 1921 * Free all transmit rings. 1922 * 1923 **********************************************************************/ 1924 void 1925 igc_free_transmit_structures(struct igc_softc *sc) 1926 { 1927 struct tx_ring *txr = sc->tx_rings; 1928 int i; 1929 1930 for (i = 0; i < sc->sc_nqueues; i++, txr++) 1931 igc_free_transmit_buffers(txr); 1932 } 1933 1934 /********************************************************************* 1935 * 1936 * Free transmit ring related data structures. 1937 * 1938 **********************************************************************/ 1939 void 1940 igc_free_transmit_buffers(struct tx_ring *txr) 1941 { 1942 struct igc_softc *sc = txr->sc; 1943 struct igc_tx_buf *txbuf; 1944 int i; 1945 1946 if (txr->tx_buffers == NULL) 1947 return; 1948 1949 txbuf = txr->tx_buffers; 1950 for (i = 0; i < sc->num_tx_desc; i++, txbuf++) { 1951 if (txbuf->map != NULL && txbuf->map->dm_nsegs > 0) { 1952 bus_dmamap_sync(txr->txdma.dma_tag, txbuf->map, 1953 0, txbuf->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1954 bus_dmamap_unload(txr->txdma.dma_tag, txbuf->map); 1955 } 1956 if (txbuf->m_head != NULL) { 1957 m_freem(txbuf->m_head); 1958 txbuf->m_head = NULL; 1959 } 1960 if (txbuf->map != NULL) { 1961 bus_dmamap_destroy(txr->txdma.dma_tag, txbuf->map); 1962 txbuf->map = NULL; 1963 } 1964 } 1965 1966 if (txr->tx_buffers != NULL) 1967 free(txr->tx_buffers, M_DEVBUF, 1968 sc->num_tx_desc * sizeof(struct igc_tx_buf)); 1969 txr->tx_buffers = NULL; 1970 txr->txtag = NULL; 1971 } 1972 1973 /********************************************************************* 1974 * 1975 * Allocate memory for rx_buffer structures. Since we use one 1976 * rx_buffer per received packet, the maximum number of rx_buffer's 1977 * that we'll need is equal to the number of receive descriptors 1978 * that we've allocated. 1979 * 1980 **********************************************************************/ 1981 int 1982 igc_allocate_receive_buffers(struct rx_ring *rxr) 1983 { 1984 struct igc_softc *sc = rxr->sc; 1985 struct igc_rx_buf *rxbuf; 1986 int i, error; 1987 1988 rxr->rx_buffers = mallocarray(sc->num_rx_desc, 1989 sizeof(struct igc_rx_buf), M_DEVBUF, M_NOWAIT | M_ZERO); 1990 if (rxr->rx_buffers == NULL) { 1991 printf("%s: Unable to allocate rx_buffer memory\n", 1992 DEVNAME(sc)); 1993 error = ENOMEM; 1994 goto fail; 1995 } 1996 1997 rxbuf = rxr->rx_buffers; 1998 for (i = 0; i < sc->num_rx_desc; i++, rxbuf++) { 1999 error = bus_dmamap_create(rxr->rxdma.dma_tag, 2000 MAX_JUMBO_FRAME_SIZE, 1, MAX_JUMBO_FRAME_SIZE, 0, 2001 BUS_DMA_NOWAIT, &rxbuf->map); 2002 if (error) { 2003 printf("%s: Unable to create RX DMA map\n", 2004 DEVNAME(sc)); 2005 goto fail; 2006 } 2007 } 2008 bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0, 2009 rxr->rxdma.dma_map->dm_mapsize, 2010 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2011 2012 return 0; 2013 fail: 2014 return error; 2015 } 2016 2017 /********************************************************************* 2018 * 2019 * Allocate and initialize receive structures. 2020 * 2021 **********************************************************************/ 2022 int 2023 igc_setup_receive_structures(struct igc_softc *sc) 2024 { 2025 struct rx_ring *rxr = sc->rx_rings; 2026 int i; 2027 2028 for (i = 0; i < sc->sc_nqueues; i++, rxr++) { 2029 if (igc_setup_receive_ring(rxr)) 2030 goto fail; 2031 } 2032 2033 return 0; 2034 fail: 2035 igc_free_receive_structures(sc); 2036 return ENOBUFS; 2037 } 2038 2039 /********************************************************************* 2040 * 2041 * Initialize a receive ring and its buffers. 2042 * 2043 **********************************************************************/ 2044 int 2045 igc_setup_receive_ring(struct rx_ring *rxr) 2046 { 2047 struct igc_softc *sc = rxr->sc; 2048 struct ifnet *ifp = &sc->sc_ac.ac_if; 2049 int rsize; 2050 2051 rsize = roundup2(sc->num_rx_desc * sizeof(union igc_adv_rx_desc), 2052 IGC_DBA_ALIGN); 2053 2054 /* Clear the ring contents. */ 2055 bzero((void *)rxr->rx_base, rsize); 2056 2057 if (igc_allocate_receive_buffers(rxr)) 2058 return ENOMEM; 2059 2060 /* Setup our descriptor indices. */ 2061 rxr->next_to_check = 0; 2062 rxr->last_desc_filled = sc->num_rx_desc - 1; 2063 2064 if_rxr_init(&rxr->rx_ring, 2 * ((ifp->if_hardmtu / MCLBYTES) + 1), 2065 sc->num_rx_desc - 1); 2066 2067 return 0; 2068 } 2069 2070 /********************************************************************* 2071 * 2072 * Enable receive unit. 2073 * 2074 **********************************************************************/ 2075 void 2076 igc_initialize_receive_unit(struct igc_softc *sc) 2077 { 2078 struct rx_ring *rxr = sc->rx_rings; 2079 struct igc_hw *hw = &sc->hw; 2080 uint32_t rctl, rxcsum, srrctl = 0; 2081 int i; 2082 2083 /* 2084 * Make sure receives are disabled while setting 2085 * up the descriptor ring. 2086 */ 2087 rctl = IGC_READ_REG(hw, IGC_RCTL); 2088 IGC_WRITE_REG(hw, IGC_RCTL, rctl & ~IGC_RCTL_EN); 2089 2090 /* Setup the Receive Control Register */ 2091 rctl &= ~(3 << IGC_RCTL_MO_SHIFT); 2092 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | IGC_RCTL_LBM_NO | 2093 IGC_RCTL_RDMTS_HALF | (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 2094 2095 /* Do not store bad packets */ 2096 rctl &= ~IGC_RCTL_SBP; 2097 2098 /* Enable Long Packet receive */ 2099 if (sc->hw.mac.max_frame_size != ETHER_MAX_LEN) 2100 rctl |= IGC_RCTL_LPE; 2101 2102 /* Strip the CRC */ 2103 rctl |= IGC_RCTL_SECRC; 2104 2105 /* 2106 * Set the interrupt throttling rate. Value is calculated 2107 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2108 */ 2109 IGC_WRITE_REG(hw, IGC_ITR, DEFAULT_ITR); 2110 2111 rxcsum = IGC_READ_REG(hw, IGC_RXCSUM); 2112 rxcsum &= ~IGC_RXCSUM_PCSD; 2113 2114 if (sc->sc_nqueues > 1) 2115 rxcsum |= IGC_RXCSUM_PCSD; 2116 2117 IGC_WRITE_REG(hw, IGC_RXCSUM, rxcsum); 2118 2119 if (sc->sc_nqueues > 1) 2120 igc_initialize_rss_mapping(sc); 2121 2122 #if 0 2123 srrctl |= 4096 >> IGC_SRRCTL_BSIZEPKT_SHIFT; 2124 rctl |= IGC_RCTL_SZ_4096 | IGC_RCTL_BSEX; 2125 #endif 2126 2127 srrctl |= 2048 >> IGC_SRRCTL_BSIZEPKT_SHIFT; 2128 rctl |= IGC_RCTL_SZ_2048; 2129 2130 /* 2131 * If TX flow control is disabled and there's > 1 queue defined, 2132 * enable DROP. 2133 * 2134 * This drops frames rather than hanging the RX MAC for all queues. 2135 */ 2136 if ((sc->sc_nqueues > 1) && (sc->fc == igc_fc_none || 2137 sc->fc == igc_fc_rx_pause)) { 2138 srrctl |= IGC_SRRCTL_DROP_EN; 2139 } 2140 2141 /* Setup the Base and Length of the RX descriptor rings. */ 2142 for (i = 0; i < sc->sc_nqueues; i++, rxr++) { 2143 IGC_WRITE_REG(hw, IGC_RXDCTL(i), 0); 2144 uint64_t bus_addr = rxr->rxdma.dma_map->dm_segs[0].ds_addr; 2145 uint32_t rxdctl; 2146 2147 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF; 2148 2149 IGC_WRITE_REG(hw, IGC_RDLEN(i), 2150 sc->num_rx_desc * sizeof(union igc_adv_rx_desc)); 2151 IGC_WRITE_REG(hw, IGC_RDBAH(i), (uint32_t)(bus_addr >> 32)); 2152 IGC_WRITE_REG(hw, IGC_RDBAL(i), (uint32_t)bus_addr); 2153 IGC_WRITE_REG(hw, IGC_SRRCTL(i), srrctl); 2154 2155 /* Setup the Head and Tail Descriptor Pointers */ 2156 IGC_WRITE_REG(hw, IGC_RDH(i), 0); 2157 IGC_WRITE_REG(hw, IGC_RDT(i), 0); 2158 2159 /* Enable this Queue */ 2160 rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i)); 2161 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE; 2162 rxdctl &= 0xFFF00000; 2163 rxdctl |= IGC_RX_PTHRESH; 2164 rxdctl |= IGC_RX_HTHRESH << 8; 2165 rxdctl |= IGC_RX_WTHRESH << 16; 2166 IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl); 2167 } 2168 2169 /* Make sure VLAN Filters are off */ 2170 rctl &= ~IGC_RCTL_VFE; 2171 2172 /* Write out the settings */ 2173 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 2174 } 2175 2176 /********************************************************************* 2177 * 2178 * Free all receive rings. 2179 * 2180 **********************************************************************/ 2181 void 2182 igc_free_receive_structures(struct igc_softc *sc) 2183 { 2184 struct rx_ring *rxr; 2185 int i; 2186 2187 for (i = 0, rxr = sc->rx_rings; i < sc->sc_nqueues; i++, rxr++) 2188 if_rxr_init(&rxr->rx_ring, 0, 0); 2189 2190 for (i = 0, rxr = sc->rx_rings; i < sc->sc_nqueues; i++, rxr++) 2191 igc_free_receive_buffers(rxr); 2192 } 2193 2194 /********************************************************************* 2195 * 2196 * Free receive ring data structures 2197 * 2198 **********************************************************************/ 2199 void 2200 igc_free_receive_buffers(struct rx_ring *rxr) 2201 { 2202 struct igc_softc *sc = rxr->sc; 2203 struct igc_rx_buf *rxbuf; 2204 int i; 2205 2206 if (rxr->rx_buffers != NULL) { 2207 for (i = 0; i < sc->num_rx_desc; i++) { 2208 rxbuf = &rxr->rx_buffers[i]; 2209 if (rxbuf->buf != NULL) { 2210 bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->map, 2211 0, rxbuf->map->dm_mapsize, 2212 BUS_DMASYNC_POSTREAD); 2213 bus_dmamap_unload(rxr->rxdma.dma_tag, 2214 rxbuf->map); 2215 m_freem(rxbuf->buf); 2216 rxbuf->buf = NULL; 2217 } 2218 bus_dmamap_destroy(rxr->rxdma.dma_tag, rxbuf->map); 2219 rxbuf->map = NULL; 2220 } 2221 free(rxr->rx_buffers, M_DEVBUF, 2222 sc->num_rx_desc * sizeof(struct igc_rx_buf)); 2223 rxr->rx_buffers = NULL; 2224 } 2225 } 2226 2227 /* 2228 * Initialise the RSS mapping for NICs that support multiple transmit/ 2229 * receive rings. 2230 */ 2231 void 2232 igc_initialize_rss_mapping(struct igc_softc *sc) 2233 { 2234 struct igc_hw *hw = &sc->hw; 2235 uint32_t rss_key[10], mrqc, reta, shift = 0; 2236 int i, queue_id; 2237 2238 /* 2239 * The redirection table controls which destination 2240 * queue each bucket redirects traffic to. 2241 * Each DWORD represents four queues, with the LSB 2242 * being the first queue in the DWORD. 2243 * 2244 * This just allocates buckets to queues using round-robin 2245 * allocation. 2246 * 2247 * NOTE: It Just Happens to line up with the default 2248 * RSS allocation method. 2249 */ 2250 2251 /* Warning FM follows */ 2252 reta = 0; 2253 for (i = 0; i < 128; i++) { 2254 queue_id = (i % sc->sc_nqueues); 2255 /* Adjust if required */ 2256 queue_id = queue_id << shift; 2257 2258 /* 2259 * The low 8 bits are for hash value (n+0); 2260 * The next 8 bits are for hash value (n+1), etc. 2261 */ 2262 reta = reta >> 8; 2263 reta = reta | ( ((uint32_t) queue_id) << 24); 2264 if ((i & 3) == 3) { 2265 IGC_WRITE_REG(hw, IGC_RETA(i >> 2), reta); 2266 reta = 0; 2267 } 2268 } 2269 2270 /* 2271 * MRQC: Multiple Receive Queues Command 2272 * Set queuing to RSS control, number depends on the device. 2273 */ 2274 mrqc = IGC_MRQC_ENABLE_RSS_4Q; 2275 2276 /* Set up random bits */ 2277 stoeplitz_to_key(&rss_key, sizeof(rss_key)); 2278 2279 /* Now fill our hash function seeds */ 2280 for (i = 0; i < 10; i++) 2281 IGC_WRITE_REG_ARRAY(hw, IGC_RSSRK(0), i, rss_key[i]); 2282 2283 /* 2284 * Configure the RSS fields to hash upon. 2285 */ 2286 mrqc |= (IGC_MRQC_RSS_FIELD_IPV4 | IGC_MRQC_RSS_FIELD_IPV4_TCP); 2287 mrqc |= (IGC_MRQC_RSS_FIELD_IPV6 | IGC_MRQC_RSS_FIELD_IPV6_TCP); 2288 mrqc |= IGC_MRQC_RSS_FIELD_IPV6_TCP_EX; 2289 2290 IGC_WRITE_REG(hw, IGC_MRQC, mrqc); 2291 } 2292 2293 /* 2294 * igc_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 2295 * For ASF and Pass Through versions of f/w this means 2296 * that the driver is loaded. For AMT version type f/w 2297 * this means that the network i/f is open. 2298 */ 2299 void 2300 igc_get_hw_control(struct igc_softc *sc) 2301 { 2302 uint32_t ctrl_ext; 2303 2304 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT); 2305 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 2306 } 2307 2308 /* 2309 * igc_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 2310 * For ASF and Pass Through versions of f/w this means that 2311 * the driver is no longer loaded. For AMT versions of the 2312 * f/w this means that the network i/f is closed. 2313 */ 2314 void 2315 igc_release_hw_control(struct igc_softc *sc) 2316 { 2317 uint32_t ctrl_ext; 2318 2319 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT); 2320 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 2321 } 2322 2323 int 2324 igc_is_valid_ether_addr(uint8_t *addr) 2325 { 2326 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 2327 2328 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 2329 return 0; 2330 } 2331 2332 return 1; 2333 } 2334