1 /* $OpenBSD: if_et.c,v 1.34 2016/04/13 10:34:32 mpi Exp $ */ 2 /* 3 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 4 * 5 * This code is derived from software contributed to The DragonFly Project 6 * by Sepherosa Ziehau <sepherosa@gmail.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.1 2007/10/12 14:12:42 sephe Exp $ 36 */ 37 38 #include "bpfilter.h" 39 40 #include <sys/param.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/timeout.h> 50 #include <sys/socket.h> 51 52 #include <machine/bus.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 58 #include <netinet/in.h> 59 #include <netinet/if_ether.h> 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_etreg.h> 72 73 /* XXX temporary porting goop */ 74 #define KKASSERT(cond) if (!(cond)) panic("KKASSERT: %s in %s", #cond, __func__) 75 #undef KASSERT 76 #define KASSERT(cond, complaint) if (!(cond)) panic complaint 77 78 /* these macros in particular need to die, so gross */ 79 #define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) 80 #define __SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask)) 81 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) 82 /* XXX end porting goop */ 83 84 int et_match(struct device *, void *, void *); 85 void et_attach(struct device *, struct device *, void *); 86 int et_detach(struct device *, int); 87 88 int et_miibus_readreg(struct device *, int, int); 89 void et_miibus_writereg(struct device *, int, int, int); 90 void et_miibus_statchg(struct device *); 91 92 int et_init(struct ifnet *); 93 int et_ioctl(struct ifnet *, u_long, caddr_t); 94 void et_start(struct ifnet *); 95 void et_watchdog(struct ifnet *); 96 int et_ifmedia_upd(struct ifnet *); 97 void et_ifmedia_sts(struct ifnet *, struct ifmediareq *); 98 99 int et_intr(void *); 100 void et_enable_intrs(struct et_softc *, uint32_t); 101 void et_disable_intrs(struct et_softc *); 102 void et_rxeof(struct et_softc *); 103 void et_txeof(struct et_softc *); 104 void et_txtick(void *); 105 106 int et_dma_alloc(struct et_softc *); 107 void et_dma_free(struct et_softc *); 108 int et_dma_mem_create(struct et_softc *, bus_size_t, 109 void **, bus_addr_t *, bus_dmamap_t *, bus_dma_segment_t *); 110 void et_dma_mem_destroy(struct et_softc *, void *, bus_dmamap_t); 111 int et_dma_mbuf_create(struct et_softc *); 112 void et_dma_mbuf_destroy(struct et_softc *, int, const int[]); 113 114 int et_init_tx_ring(struct et_softc *); 115 int et_init_rx_ring(struct et_softc *); 116 void et_free_tx_ring(struct et_softc *); 117 void et_free_rx_ring(struct et_softc *); 118 int et_encap(struct et_softc *, struct mbuf **); 119 int et_newbuf(struct et_rxbuf_data *, int, int, int); 120 int et_newbuf_cluster(struct et_rxbuf_data *, int, int); 121 int et_newbuf_hdr(struct et_rxbuf_data *, int, int); 122 123 void et_stop(struct et_softc *); 124 int et_chip_init(struct et_softc *); 125 void et_chip_attach(struct et_softc *); 126 void et_init_mac(struct et_softc *); 127 void et_init_rxmac(struct et_softc *); 128 void et_init_txmac(struct et_softc *); 129 int et_init_rxdma(struct et_softc *); 130 int et_init_txdma(struct et_softc *); 131 int et_start_rxdma(struct et_softc *); 132 int et_start_txdma(struct et_softc *); 133 int et_stop_rxdma(struct et_softc *); 134 int et_stop_txdma(struct et_softc *); 135 int et_enable_txrx(struct et_softc *); 136 void et_reset(struct et_softc *); 137 int et_bus_config(struct et_softc *); 138 void et_get_eaddr(struct et_softc *, uint8_t[]); 139 void et_setmulti(struct et_softc *); 140 void et_tick(void *); 141 142 static int et_rx_intr_npkts = 32; 143 static int et_rx_intr_delay = 20; /* x10 usec */ 144 static int et_tx_intr_nsegs = 128; 145 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 146 147 struct et_bsize { 148 int bufsize; 149 et_newbuf_t newbuf; 150 }; 151 152 static const struct et_bsize et_bufsize[ET_RX_NRING] = { 153 { .bufsize = 0, .newbuf = et_newbuf_hdr }, 154 { .bufsize = 0, .newbuf = et_newbuf_cluster }, 155 }; 156 157 const struct pci_matchid et_devices[] = { 158 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FE }, 159 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_GBE } 160 }; 161 162 struct cfattach et_ca = { 163 sizeof (struct et_softc), et_match, et_attach, et_detach 164 }; 165 166 struct cfdriver et_cd = { 167 NULL, "et", DV_IFNET 168 }; 169 170 int 171 et_match(struct device *dev, void *match, void *aux) 172 { 173 return pci_matchbyid((struct pci_attach_args *)aux, et_devices, 174 sizeof (et_devices) / sizeof (et_devices[0])); 175 } 176 177 void 178 et_attach(struct device *parent, struct device *self, void *aux) 179 { 180 struct et_softc *sc = (struct et_softc *)self; 181 struct pci_attach_args *pa = aux; 182 pci_chipset_tag_t pc = pa->pa_pc; 183 pci_intr_handle_t ih; 184 const char *intrstr; 185 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 186 pcireg_t memtype; 187 int error; 188 189 /* 190 * Initialize tunables 191 */ 192 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 193 sc->sc_rx_intr_delay = et_rx_intr_delay; 194 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 195 sc->sc_timer = et_timer; 196 197 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ET_PCIR_BAR); 198 if (pci_mapreg_map(pa, ET_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 199 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 200 printf(": can't map mem space\n"); 201 return; 202 } 203 204 if (pci_intr_map(pa, &ih) != 0) { 205 printf(": can't map interrupt\n"); 206 return; 207 } 208 209 intrstr = pci_intr_string(pc, ih); 210 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, et_intr, sc, 211 sc->sc_dev.dv_xname); 212 if (sc->sc_irq_handle == NULL) { 213 printf(": could not establish interrupt"); 214 if (intrstr != NULL) 215 printf(" at %s", intrstr); 216 printf("\n"); 217 return; 218 } 219 printf(": %s", intrstr); 220 221 sc->sc_dmat = pa->pa_dmat; 222 sc->sc_pct = pa->pa_pc; 223 sc->sc_pcitag = pa->pa_tag; 224 225 error = et_bus_config(sc); 226 if (error) 227 return; 228 229 et_get_eaddr(sc, sc->sc_arpcom.ac_enaddr); 230 231 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 232 233 CSR_WRITE_4(sc, ET_PM, 234 ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE); 235 236 et_reset(sc); 237 238 et_disable_intrs(sc); 239 240 error = et_dma_alloc(sc); 241 if (error) 242 return; 243 244 ifp->if_softc = sc; 245 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 246 ifp->if_ioctl = et_ioctl; 247 ifp->if_start = et_start; 248 ifp->if_watchdog = et_watchdog; 249 IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC); 250 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 251 252 ifp->if_capabilities = IFCAP_VLAN_MTU; 253 254 et_chip_attach(sc); 255 256 sc->sc_miibus.mii_ifp = ifp; 257 sc->sc_miibus.mii_readreg = et_miibus_readreg; 258 sc->sc_miibus.mii_writereg = et_miibus_writereg; 259 sc->sc_miibus.mii_statchg = et_miibus_statchg; 260 261 ifmedia_init(&sc->sc_miibus.mii_media, 0, et_ifmedia_upd, 262 et_ifmedia_sts); 263 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 264 MII_OFFSET_ANY, 0); 265 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 266 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 267 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 268 0, NULL); 269 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 270 } else 271 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 272 273 if_attach(ifp); 274 ether_ifattach(ifp); 275 276 timeout_set(&sc->sc_tick, et_tick, sc); 277 timeout_set(&sc->sc_txtick, et_txtick, sc); 278 } 279 280 int 281 et_detach(struct device *self, int flags) 282 { 283 struct et_softc *sc = (struct et_softc *)self; 284 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 285 int s; 286 287 s = splnet(); 288 et_stop(sc); 289 splx(s); 290 291 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 292 293 /* Delete all remaining media. */ 294 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 295 296 ether_ifdetach(ifp); 297 if_detach(ifp); 298 et_dma_free(sc); 299 300 if (sc->sc_irq_handle != NULL) { 301 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 302 sc->sc_irq_handle = NULL; 303 } 304 305 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 306 307 return 0; 308 } 309 310 int 311 et_miibus_readreg(struct device *dev, int phy, int reg) 312 { 313 struct et_softc *sc = (struct et_softc *)dev; 314 uint32_t val; 315 int i, ret; 316 317 /* Stop any pending operations */ 318 CSR_WRITE_4(sc, ET_MII_CMD, 0); 319 320 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 321 __SHIFTIN(reg, ET_MII_ADDR_REG); 322 CSR_WRITE_4(sc, ET_MII_ADDR, val); 323 324 /* Start reading */ 325 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 326 327 #define NRETRY 50 328 329 for (i = 0; i < NRETRY; ++i) { 330 val = CSR_READ_4(sc, ET_MII_IND); 331 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 332 break; 333 DELAY(50); 334 } 335 if (i == NRETRY) { 336 printf("%s: read phy %d, reg %d timed out\n", 337 sc->sc_dev.dv_xname, phy, reg); 338 ret = 0; 339 goto back; 340 } 341 342 #undef NRETRY 343 344 val = CSR_READ_4(sc, ET_MII_STAT); 345 ret = __SHIFTOUT(val, ET_MII_STAT_VALUE); 346 347 back: 348 /* Make sure that the current operation is stopped */ 349 CSR_WRITE_4(sc, ET_MII_CMD, 0); 350 return ret; 351 } 352 353 void 354 et_miibus_writereg(struct device *dev, int phy, int reg, int val0) 355 { 356 struct et_softc *sc = (struct et_softc *)dev; 357 uint32_t val; 358 int i; 359 360 /* Stop any pending operations */ 361 CSR_WRITE_4(sc, ET_MII_CMD, 0); 362 363 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 364 __SHIFTIN(reg, ET_MII_ADDR_REG); 365 CSR_WRITE_4(sc, ET_MII_ADDR, val); 366 367 /* Start writing */ 368 CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val0, ET_MII_CTRL_VALUE)); 369 370 #define NRETRY 100 371 372 for (i = 0; i < NRETRY; ++i) { 373 val = CSR_READ_4(sc, ET_MII_IND); 374 if ((val & ET_MII_IND_BUSY) == 0) 375 break; 376 DELAY(50); 377 } 378 if (i == NRETRY) { 379 printf("%s: write phy %d, reg %d timed out\n", 380 sc->sc_dev.dv_xname, phy, reg); 381 et_miibus_readreg(dev, phy, reg); 382 } 383 384 #undef NRETRY 385 386 /* Make sure that the current operation is stopped */ 387 CSR_WRITE_4(sc, ET_MII_CMD, 0); 388 } 389 390 void 391 et_miibus_statchg(struct device *dev) 392 { 393 struct et_softc *sc = (struct et_softc *)dev; 394 struct mii_data *mii = &sc->sc_miibus; 395 uint32_t cfg2, ctrl; 396 397 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 398 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 399 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 400 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 401 __SHIFTIN(7, ET_MAC_CFG2_PREAMBLE_LEN); 402 403 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 404 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 405 406 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 407 cfg2 |= ET_MAC_CFG2_MODE_GMII; 408 } else { 409 cfg2 |= ET_MAC_CFG2_MODE_MII; 410 ctrl |= ET_MAC_CTRL_MODE_MII; 411 } 412 413 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 414 cfg2 |= ET_MAC_CFG2_FDX; 415 else 416 ctrl |= ET_MAC_CTRL_GHDX; 417 418 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 419 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 420 } 421 422 int 423 et_ifmedia_upd(struct ifnet *ifp) 424 { 425 struct et_softc *sc = ifp->if_softc; 426 struct mii_data *mii = &sc->sc_miibus; 427 428 if (mii->mii_instance != 0) { 429 struct mii_softc *miisc; 430 431 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 432 mii_phy_reset(miisc); 433 } 434 mii_mediachg(mii); 435 436 return 0; 437 } 438 439 void 440 et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 441 { 442 struct et_softc *sc = ifp->if_softc; 443 struct mii_data *mii = &sc->sc_miibus; 444 445 mii_pollstat(mii); 446 ifmr->ifm_active = mii->mii_media_active; 447 ifmr->ifm_status = mii->mii_media_status; 448 } 449 450 void 451 et_stop(struct et_softc *sc) 452 { 453 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 454 455 timeout_del(&sc->sc_tick); 456 timeout_del(&sc->sc_txtick); 457 458 et_stop_rxdma(sc); 459 et_stop_txdma(sc); 460 461 et_disable_intrs(sc); 462 463 et_free_tx_ring(sc); 464 et_free_rx_ring(sc); 465 466 et_reset(sc); 467 468 sc->sc_tx = 0; 469 sc->sc_tx_intr = 0; 470 471 ifp->if_timer = 0; 472 ifp->if_flags &= ~IFF_RUNNING; 473 ifq_clr_oactive(&ifp->if_snd); 474 } 475 476 int 477 et_bus_config(struct et_softc *sc) 478 { 479 uint32_t val; //, max_plsz; 480 // uint16_t ack_latency, replay_timer; 481 482 /* 483 * Test whether EEPROM is valid 484 * NOTE: Read twice to get the correct value 485 */ 486 pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_EEPROM_MISC); 487 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_EEPROM_MISC); 488 489 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 490 printf("%s: EEPROM status error 0x%02x\n", 491 sc->sc_dev.dv_xname, val); 492 return ENXIO; 493 } 494 495 /* TODO: LED */ 496 #if 0 497 /* 498 * Configure ACK latency and replay timer according to 499 * max playload size 500 */ 501 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_DEVICE_CAPS); 502 max_plsz = val & ET_PCIM_DEVICE_CAPS_MAX_PLSZ; 503 504 switch (max_plsz) { 505 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 506 ack_latency = ET_PCIV_ACK_LATENCY_128; 507 replay_timer = ET_PCIV_REPLAY_TIMER_128; 508 break; 509 510 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 511 ack_latency = ET_PCIV_ACK_LATENCY_256; 512 replay_timer = ET_PCIV_REPLAY_TIMER_256; 513 break; 514 515 default: 516 ack_latency = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 517 ET_PCIR_ACK_LATENCY) >> 16; 518 replay_timer = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 519 ET_PCIR_REPLAY_TIMER) >> 16; 520 printf("%s: ack latency %u, replay timer %u\n", 521 sc->sc_dev.dv_xname, ack_latency, replay_timer); 522 break; 523 } 524 if (ack_latency != 0) { 525 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 526 ET_PCIR_ACK_LATENCY, ack_latency << 16); 527 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 528 ET_PCIR_REPLAY_TIMER, replay_timer << 16); 529 } 530 531 /* 532 * Set L0s and L1 latency timer to 2us 533 */ 534 val = ET_PCIV_L0S_LATENCY(2) | ET_PCIV_L1_LATENCY(2); 535 pci_conf_write(sc->sc_pct, sc->sc_pcitag, ET_PCIR_L0S_L1_LATENCY, 536 val << 24); 537 538 /* 539 * Set max read request size to 2048 bytes 540 */ 541 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 542 ET_PCIR_DEVICE_CTRL) >> 16; 543 val &= ~ET_PCIM_DEVICE_CTRL_MAX_RRSZ; 544 val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K; 545 pci_conf_write(sc->sc_pct, sc->sc_pcitag, ET_PCIR_DEVICE_CTRL, 546 val << 16); 547 #endif 548 549 return 0; 550 } 551 552 void 553 et_get_eaddr(struct et_softc *sc, uint8_t eaddr[]) 554 { 555 uint32_t r; 556 557 r = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_MACADDR_LO); 558 eaddr[0] = r & 0xff; 559 eaddr[1] = (r >> 8) & 0xff; 560 eaddr[2] = (r >> 16) & 0xff; 561 eaddr[3] = (r >> 24) & 0xff; 562 r = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_MACADDR_HI); 563 eaddr[4] = r & 0xff; 564 eaddr[5] = (r >> 8) & 0xff; 565 } 566 567 void 568 et_reset(struct et_softc *sc) 569 { 570 CSR_WRITE_4(sc, ET_MAC_CFG1, 571 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 572 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 573 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 574 575 CSR_WRITE_4(sc, ET_SWRST, 576 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 577 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 578 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 579 580 CSR_WRITE_4(sc, ET_MAC_CFG1, 581 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 582 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 583 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 584 } 585 586 void 587 et_disable_intrs(struct et_softc *sc) 588 { 589 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 590 } 591 592 void 593 et_enable_intrs(struct et_softc *sc, uint32_t intrs) 594 { 595 CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs); 596 } 597 598 int 599 et_dma_alloc(struct et_softc *sc) 600 { 601 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 602 struct et_txstatus_data *txsd = &sc->sc_tx_status; 603 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 604 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 605 int i, error; 606 607 /* 608 * Create TX ring DMA stuffs 609 */ 610 error = et_dma_mem_create(sc, ET_TX_RING_SIZE, 611 (void **)&tx_ring->tr_desc, &tx_ring->tr_paddr, &tx_ring->tr_dmap, 612 &tx_ring->tr_seg); 613 if (error) { 614 printf("%s: can't create TX ring DMA stuffs\n", 615 sc->sc_dev.dv_xname); 616 return error; 617 } 618 619 /* 620 * Create TX status DMA stuffs 621 */ 622 error = et_dma_mem_create(sc, sizeof(uint32_t), 623 (void **)&txsd->txsd_status, 624 &txsd->txsd_paddr, &txsd->txsd_dmap, &txsd->txsd_seg); 625 if (error) { 626 printf("%s: can't create TX status DMA stuffs\n", 627 sc->sc_dev.dv_xname); 628 return error; 629 } 630 631 /* 632 * Create DMA stuffs for RX rings 633 */ 634 for (i = 0; i < ET_RX_NRING; ++i) { 635 static const uint32_t rx_ring_posreg[ET_RX_NRING] = 636 { ET_RX_RING0_POS, ET_RX_RING1_POS }; 637 638 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 639 640 error = et_dma_mem_create(sc, ET_RX_RING_SIZE, 641 (void **)&rx_ring->rr_desc, 642 &rx_ring->rr_paddr, &rx_ring->rr_dmap, &rx_ring->rr_seg); 643 if (error) { 644 printf("%s: can't create DMA stuffs for " 645 "the %d RX ring\n", sc->sc_dev.dv_xname, i); 646 return error; 647 } 648 rx_ring->rr_posreg = rx_ring_posreg[i]; 649 } 650 651 /* 652 * Create RX stat ring DMA stuffs 653 */ 654 error = et_dma_mem_create(sc, ET_RXSTAT_RING_SIZE, 655 (void **)&rxst_ring->rsr_stat, 656 &rxst_ring->rsr_paddr, &rxst_ring->rsr_dmap, &rxst_ring->rsr_seg); 657 if (error) { 658 printf("%s: can't create RX stat ring DMA stuffs\n", 659 sc->sc_dev.dv_xname); 660 return error; 661 } 662 663 /* 664 * Create RX status DMA stuffs 665 */ 666 error = et_dma_mem_create(sc, sizeof(struct et_rxstatus), 667 (void **)&rxsd->rxsd_status, 668 &rxsd->rxsd_paddr, &rxsd->rxsd_dmap, &rxsd->rxsd_seg); 669 if (error) { 670 printf("%s: can't create RX status DMA stuffs\n", 671 sc->sc_dev.dv_xname); 672 return error; 673 } 674 675 /* 676 * Create mbuf DMA stuffs 677 */ 678 error = et_dma_mbuf_create(sc); 679 if (error) 680 return error; 681 682 return 0; 683 } 684 685 void 686 et_dma_free(struct et_softc *sc) 687 { 688 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 689 struct et_txstatus_data *txsd = &sc->sc_tx_status; 690 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 691 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 692 int i, rx_done[ET_RX_NRING]; 693 694 /* 695 * Destroy TX ring DMA stuffs 696 */ 697 et_dma_mem_destroy(sc, tx_ring->tr_desc, tx_ring->tr_dmap); 698 699 /* 700 * Destroy TX status DMA stuffs 701 */ 702 et_dma_mem_destroy(sc, txsd->txsd_status, txsd->txsd_dmap); 703 704 /* 705 * Destroy DMA stuffs for RX rings 706 */ 707 for (i = 0; i < ET_RX_NRING; ++i) { 708 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 709 710 et_dma_mem_destroy(sc, rx_ring->rr_desc, rx_ring->rr_dmap); 711 } 712 713 /* 714 * Destroy RX stat ring DMA stuffs 715 */ 716 et_dma_mem_destroy(sc, rxst_ring->rsr_stat, rxst_ring->rsr_dmap); 717 718 /* 719 * Destroy RX status DMA stuffs 720 */ 721 et_dma_mem_destroy(sc, rxsd->rxsd_status, rxsd->rxsd_dmap); 722 723 /* 724 * Destroy mbuf DMA stuffs 725 */ 726 for (i = 0; i < ET_RX_NRING; ++i) 727 rx_done[i] = ET_RX_NDESC; 728 et_dma_mbuf_destroy(sc, ET_TX_NDESC, rx_done); 729 } 730 731 int 732 et_dma_mbuf_create(struct et_softc *sc) 733 { 734 struct et_txbuf_data *tbd = &sc->sc_tx_data; 735 int i, error, rx_done[ET_RX_NRING]; 736 737 /* 738 * Create spare DMA map for RX mbufs 739 */ 740 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 741 BUS_DMA_NOWAIT, &sc->sc_mbuf_tmp_dmap); 742 if (error) { 743 printf("%s: can't create spare mbuf DMA map\n", 744 sc->sc_dev.dv_xname); 745 return error; 746 } 747 748 /* 749 * Create DMA maps for RX mbufs 750 */ 751 bzero(rx_done, sizeof(rx_done)); 752 for (i = 0; i < ET_RX_NRING; ++i) { 753 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 754 int j; 755 756 for (j = 0; j < ET_RX_NDESC; ++j) { 757 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 758 MCLBYTES, 0, BUS_DMA_NOWAIT, 759 &rbd->rbd_buf[j].rb_dmap); 760 if (error) { 761 printf("%s: can't create %d RX mbuf " 762 "for %d RX ring\n", sc->sc_dev.dv_xname, 763 j, i); 764 rx_done[i] = j; 765 et_dma_mbuf_destroy(sc, 0, rx_done); 766 return error; 767 } 768 } 769 rx_done[i] = ET_RX_NDESC; 770 771 rbd->rbd_softc = sc; 772 rbd->rbd_ring = &sc->sc_rx_ring[i]; 773 } 774 775 /* 776 * Create DMA maps for TX mbufs 777 */ 778 for (i = 0; i < ET_TX_NDESC; ++i) { 779 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 780 0, BUS_DMA_NOWAIT, &tbd->tbd_buf[i].tb_dmap); 781 if (error) { 782 printf("%s: can't create %d TX mbuf " 783 "DMA map\n", sc->sc_dev.dv_xname, i); 784 et_dma_mbuf_destroy(sc, i, rx_done); 785 return error; 786 } 787 } 788 789 return 0; 790 } 791 792 void 793 et_dma_mbuf_destroy(struct et_softc *sc, int tx_done, const int rx_done[]) 794 { 795 struct et_txbuf_data *tbd = &sc->sc_tx_data; 796 int i; 797 798 /* 799 * Destroy DMA maps for RX mbufs 800 */ 801 for (i = 0; i < ET_RX_NRING; ++i) { 802 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 803 int j; 804 805 for (j = 0; j < rx_done[i]; ++j) { 806 struct et_rxbuf *rb = &rbd->rbd_buf[j]; 807 808 KASSERT(rb->rb_mbuf == NULL, 809 ("RX mbuf in %d RX ring is not freed yet\n", i)); 810 bus_dmamap_destroy(sc->sc_dmat, rb->rb_dmap); 811 } 812 } 813 814 /* 815 * Destroy DMA maps for TX mbufs 816 */ 817 for (i = 0; i < tx_done; ++i) { 818 struct et_txbuf *tb = &tbd->tbd_buf[i]; 819 820 KASSERT(tb->tb_mbuf == NULL, ("TX mbuf is not freed yet\n")); 821 bus_dmamap_destroy(sc->sc_dmat, tb->tb_dmap); 822 } 823 824 /* 825 * Destroy spare mbuf DMA map 826 */ 827 bus_dmamap_destroy(sc->sc_dmat, sc->sc_mbuf_tmp_dmap); 828 } 829 830 int 831 et_dma_mem_create(struct et_softc *sc, bus_size_t size, 832 void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap, bus_dma_segment_t *seg) 833 { 834 int error, nsegs; 835 836 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 837 dmap); 838 if (error) { 839 printf("%s: can't create DMA map\n", sc->sc_dev.dv_xname); 840 return error; 841 } 842 843 error = bus_dmamem_alloc(sc->sc_dmat, size, ET_ALIGN, 0, seg, 844 1, &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 845 if (error) { 846 printf("%s: can't allocate DMA mem\n", sc->sc_dev.dv_xname); 847 return error; 848 } 849 850 error = bus_dmamem_map(sc->sc_dmat, seg, nsegs, 851 size, (caddr_t *)addr, BUS_DMA_NOWAIT); 852 if (error) { 853 printf("%s: can't map DMA mem\n", sc->sc_dev.dv_xname); 854 return (error); 855 } 856 857 error = bus_dmamap_load(sc->sc_dmat, *dmap, *addr, size, NULL, 858 BUS_DMA_WAITOK); 859 if (error) { 860 printf("%s: can't load DMA mem\n", sc->sc_dev.dv_xname); 861 bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)addr, 1); 862 return error; 863 } 864 865 *paddr = (*dmap)->dm_segs[0].ds_addr; 866 867 return 0; 868 } 869 870 void 871 et_dma_mem_destroy(struct et_softc *sc, void *addr, bus_dmamap_t dmap) 872 { 873 bus_dmamap_unload(sc->sc_dmat, dmap); 874 bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)&addr, 1); 875 } 876 877 void 878 et_chip_attach(struct et_softc *sc) 879 { 880 uint32_t val; 881 882 /* 883 * Perform minimal initialization 884 */ 885 886 /* Disable loopback */ 887 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 888 889 /* Reset MAC */ 890 CSR_WRITE_4(sc, ET_MAC_CFG1, 891 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 892 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 893 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 894 895 /* 896 * Setup half duplex mode 897 */ 898 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 899 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 900 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 901 ET_MAC_HDX_EXC_DEFER; 902 CSR_WRITE_4(sc, ET_MAC_HDX, val); 903 904 /* Clear MAC control */ 905 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 906 907 /* Reset MII */ 908 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 909 910 /* Bring MAC out of reset state */ 911 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 912 913 /* Enable memory controllers */ 914 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 915 } 916 917 int 918 et_intr(void *xsc) 919 { 920 struct et_softc *sc = xsc; 921 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 922 uint32_t intrs; 923 924 if ((ifp->if_flags & IFF_RUNNING) == 0) 925 return (0); 926 927 intrs = CSR_READ_4(sc, ET_INTR_STATUS); 928 if (intrs == 0 || intrs == 0xffffffff) 929 return (0); 930 931 et_disable_intrs(sc); 932 intrs &= ET_INTRS; 933 if (intrs == 0) /* Not interested */ 934 goto back; 935 936 if (intrs & ET_INTR_RXEOF) 937 et_rxeof(sc); 938 if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER)) 939 et_txeof(sc); 940 if (intrs & ET_INTR_TIMER) 941 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 942 back: 943 et_enable_intrs(sc, ET_INTRS); 944 945 return (1); 946 } 947 948 int 949 et_init(struct ifnet *ifp) 950 { 951 struct et_softc *sc = ifp->if_softc; 952 int error, i, s; 953 954 s = splnet(); 955 956 et_stop(sc); 957 958 for (i = 0; i < ET_RX_NRING; ++i) { 959 sc->sc_rx_data[i].rbd_bufsize = et_bufsize[i].bufsize; 960 sc->sc_rx_data[i].rbd_newbuf = et_bufsize[i].newbuf; 961 } 962 963 error = et_init_tx_ring(sc); 964 if (error) 965 goto back; 966 967 error = et_init_rx_ring(sc); 968 if (error) 969 goto back; 970 971 error = et_chip_init(sc); 972 if (error) 973 goto back; 974 975 error = et_enable_txrx(sc); 976 if (error) 977 goto back; 978 979 error = et_start_rxdma(sc); 980 if (error) 981 goto back; 982 983 error = et_start_txdma(sc); 984 if (error) 985 goto back; 986 987 et_enable_intrs(sc, ET_INTRS); 988 989 timeout_add_sec(&sc->sc_tick, 1); 990 991 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 992 993 ifp->if_flags |= IFF_RUNNING; 994 ifq_clr_oactive(&ifp->if_snd); 995 back: 996 if (error) 997 et_stop(sc); 998 999 splx(s); 1000 1001 return (0); 1002 } 1003 1004 int 1005 et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1006 { 1007 struct et_softc *sc = ifp->if_softc; 1008 struct ifreq *ifr = (struct ifreq *)data; 1009 int s, error = 0; 1010 1011 s = splnet(); 1012 1013 switch (cmd) { 1014 case SIOCSIFADDR: 1015 ifp->if_flags |= IFF_UP; 1016 if (!(ifp->if_flags & IFF_RUNNING)) 1017 et_init(ifp); 1018 break; 1019 1020 case SIOCSIFFLAGS: 1021 if (ifp->if_flags & IFF_UP) { 1022 /* 1023 * If only the PROMISC or ALLMULTI flag changes, then 1024 * don't do a full re-init of the chip, just update 1025 * the Rx filter. 1026 */ 1027 if ((ifp->if_flags & IFF_RUNNING) && 1028 ((ifp->if_flags ^ sc->sc_if_flags) & 1029 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1030 et_setmulti(sc); 1031 } else { 1032 if (!(ifp->if_flags & IFF_RUNNING)) 1033 et_init(ifp); 1034 } 1035 } else { 1036 if (ifp->if_flags & IFF_RUNNING) 1037 et_stop(sc); 1038 } 1039 sc->sc_if_flags = ifp->if_flags; 1040 break; 1041 1042 case SIOCSIFMEDIA: 1043 case SIOCGIFMEDIA: 1044 error = ifmedia_ioctl(ifp, ifr, &sc->sc_miibus.mii_media, cmd); 1045 break; 1046 1047 default: 1048 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1049 } 1050 1051 if (error == ENETRESET) { 1052 if (ifp->if_flags & IFF_RUNNING) 1053 et_setmulti(sc); 1054 error = 0; 1055 } 1056 1057 splx(s); 1058 return error; 1059 } 1060 1061 void 1062 et_start(struct ifnet *ifp) 1063 { 1064 struct et_softc *sc = ifp->if_softc; 1065 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1066 int trans; 1067 struct mbuf *m; 1068 1069 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1070 return; 1071 1072 trans = 0; 1073 for (;;) { 1074 IFQ_DEQUEUE(&ifp->if_snd, m); 1075 if (m == NULL) 1076 break; 1077 1078 if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) { 1079 ifq_set_oactive(&ifp->if_snd); 1080 break; 1081 } 1082 1083 if (et_encap(sc, &m)) { 1084 ifp->if_oerrors++; 1085 ifq_set_oactive(&ifp->if_snd); 1086 break; 1087 } 1088 1089 trans = 1; 1090 1091 #if NBPFILTER > 0 1092 if (ifp->if_bpf != NULL) 1093 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1094 #endif 1095 } 1096 1097 if (trans) { 1098 timeout_add_sec(&sc->sc_txtick, 1); 1099 ifp->if_timer = 5; 1100 } 1101 } 1102 1103 void 1104 et_watchdog(struct ifnet *ifp) 1105 { 1106 struct et_softc *sc = ifp->if_softc; 1107 printf("%s: watchdog timed out\n", sc->sc_dev.dv_xname); 1108 1109 et_init(ifp); 1110 et_start(ifp); 1111 } 1112 1113 int 1114 et_stop_rxdma(struct et_softc *sc) 1115 { 1116 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1117 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1118 1119 DELAY(5); 1120 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1121 printf("%s: can't stop RX DMA engine\n", sc->sc_dev.dv_xname); 1122 return ETIMEDOUT; 1123 } 1124 return 0; 1125 } 1126 1127 int 1128 et_stop_txdma(struct et_softc *sc) 1129 { 1130 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1131 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1132 return 0; 1133 } 1134 1135 void 1136 et_free_tx_ring(struct et_softc *sc) 1137 { 1138 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1139 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1140 int i; 1141 1142 for (i = 0; i < ET_TX_NDESC; ++i) { 1143 struct et_txbuf *tb = &tbd->tbd_buf[i]; 1144 1145 if (tb->tb_mbuf != NULL) { 1146 bus_dmamap_unload(sc->sc_dmat, tb->tb_dmap); 1147 m_freem(tb->tb_mbuf); 1148 tb->tb_mbuf = NULL; 1149 } 1150 } 1151 1152 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1153 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1154 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1155 } 1156 1157 void 1158 et_free_rx_ring(struct et_softc *sc) 1159 { 1160 int n; 1161 1162 for (n = 0; n < ET_RX_NRING; ++n) { 1163 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1164 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n]; 1165 int i; 1166 1167 for (i = 0; i < ET_RX_NDESC; ++i) { 1168 struct et_rxbuf *rb = &rbd->rbd_buf[i]; 1169 1170 if (rb->rb_mbuf != NULL) { 1171 bus_dmamap_unload(sc->sc_dmat, rb->rb_dmap); 1172 m_freem(rb->rb_mbuf); 1173 rb->rb_mbuf = NULL; 1174 } 1175 } 1176 1177 bzero(rx_ring->rr_desc, ET_RX_RING_SIZE); 1178 bus_dmamap_sync(sc->sc_dmat, rx_ring->rr_dmap, 0, 1179 rx_ring->rr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1180 } 1181 } 1182 1183 void 1184 et_setmulti(struct et_softc *sc) 1185 { 1186 struct arpcom *ac = &sc->sc_arpcom; 1187 struct ifnet *ifp = &ac->ac_if; 1188 uint32_t hash[4] = { 0, 0, 0, 0 }; 1189 uint32_t rxmac_ctrl, pktfilt; 1190 struct ether_multi *enm; 1191 struct ether_multistep step; 1192 uint8_t addr[ETHER_ADDR_LEN]; 1193 int i, count; 1194 1195 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1196 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1197 1198 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1199 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1200 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1201 goto back; 1202 } 1203 1204 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1205 1206 count = 0; 1207 ETHER_FIRST_MULTI(step, ac, enm); 1208 while (enm != NULL) { 1209 uint32_t *hp, h; 1210 1211 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1212 addr[i] &= enm->enm_addrlo[i]; 1213 } 1214 1215 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)addr), 1216 ETHER_ADDR_LEN); 1217 h = (h & 0x3f800000) >> 23; 1218 1219 hp = &hash[0]; 1220 if (h >= 32 && h < 64) { 1221 h -= 32; 1222 hp = &hash[1]; 1223 } else if (h >= 64 && h < 96) { 1224 h -= 64; 1225 hp = &hash[2]; 1226 } else if (h >= 96) { 1227 h -= 96; 1228 hp = &hash[3]; 1229 } 1230 *hp |= (1 << h); 1231 1232 ++count; 1233 ETHER_NEXT_MULTI(step, enm); 1234 } 1235 1236 for (i = 0; i < 4; ++i) 1237 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1238 1239 if (count > 0) 1240 pktfilt |= ET_PKTFILT_MCAST; 1241 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1242 back: 1243 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1244 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1245 } 1246 1247 int 1248 et_chip_init(struct et_softc *sc) 1249 { 1250 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1251 uint32_t rxq_end; 1252 int error; 1253 1254 /* 1255 * Split internal memory between TX and RX according to MTU 1256 */ 1257 if (ifp->if_hardmtu < 2048) 1258 rxq_end = 0x2bc; 1259 else if (ifp->if_hardmtu < 8192) 1260 rxq_end = 0x1ff; 1261 else 1262 rxq_end = 0x1b3; 1263 CSR_WRITE_4(sc, ET_RXQ_START, 0); 1264 CSR_WRITE_4(sc, ET_RXQ_END, rxq_end); 1265 CSR_WRITE_4(sc, ET_TXQ_START, rxq_end + 1); 1266 CSR_WRITE_4(sc, ET_TXQ_END, ET_INTERN_MEM_END); 1267 1268 /* No loopback */ 1269 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1270 1271 /* Clear MSI configure */ 1272 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1273 1274 /* Disable timer */ 1275 CSR_WRITE_4(sc, ET_TIMER, 0); 1276 1277 /* Initialize MAC */ 1278 et_init_mac(sc); 1279 1280 /* Enable memory controllers */ 1281 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1282 1283 /* Initialize RX MAC */ 1284 et_init_rxmac(sc); 1285 1286 /* Initialize TX MAC */ 1287 et_init_txmac(sc); 1288 1289 /* Initialize RX DMA engine */ 1290 error = et_init_rxdma(sc); 1291 if (error) 1292 return error; 1293 1294 /* Initialize TX DMA engine */ 1295 error = et_init_txdma(sc); 1296 if (error) 1297 return error; 1298 1299 return 0; 1300 } 1301 1302 int 1303 et_init_tx_ring(struct et_softc *sc) 1304 { 1305 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1306 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1307 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1308 1309 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1310 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1311 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1312 1313 tbd->tbd_start_index = 0; 1314 tbd->tbd_start_wrap = 0; 1315 tbd->tbd_used = 0; 1316 1317 bzero(txsd->txsd_status, sizeof(uint32_t)); 1318 bus_dmamap_sync(sc->sc_dmat, txsd->txsd_dmap, 0, 1319 txsd->txsd_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1320 return 0; 1321 } 1322 1323 int 1324 et_init_rx_ring(struct et_softc *sc) 1325 { 1326 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1327 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1328 int n; 1329 1330 for (n = 0; n < ET_RX_NRING; ++n) { 1331 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1332 int i, error; 1333 1334 for (i = 0; i < ET_RX_NDESC; ++i) { 1335 error = rbd->rbd_newbuf(rbd, i, 1); 1336 if (error) { 1337 printf("%s: %d ring %d buf, newbuf failed: " 1338 "%d\n", sc->sc_dev.dv_xname, n, i, error); 1339 return error; 1340 } 1341 } 1342 } 1343 1344 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1345 bus_dmamap_sync(sc->sc_dmat, rxsd->rxsd_dmap, 0, 1346 rxsd->rxsd_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1347 1348 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1349 bus_dmamap_sync(sc->sc_dmat, rxst_ring->rsr_dmap, 0, 1350 rxst_ring->rsr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1351 1352 return 0; 1353 } 1354 1355 int 1356 et_init_rxdma(struct et_softc *sc) 1357 { 1358 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1359 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1360 struct et_rxdesc_ring *rx_ring; 1361 int error; 1362 1363 error = et_stop_rxdma(sc); 1364 if (error) { 1365 printf("%s: can't init RX DMA engine\n", sc->sc_dev.dv_xname); 1366 return error; 1367 } 1368 1369 /* 1370 * Install RX status 1371 */ 1372 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1373 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1374 1375 /* 1376 * Install RX stat ring 1377 */ 1378 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1379 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1380 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1381 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1382 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1383 1384 /* Match ET_RXSTAT_POS */ 1385 rxst_ring->rsr_index = 0; 1386 rxst_ring->rsr_wrap = 0; 1387 1388 /* 1389 * Install the 2nd RX descriptor ring 1390 */ 1391 rx_ring = &sc->sc_rx_ring[1]; 1392 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1393 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1394 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1395 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1396 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1397 1398 /* Match ET_RX_RING1_POS */ 1399 rx_ring->rr_index = 0; 1400 rx_ring->rr_wrap = 1; 1401 1402 /* 1403 * Install the 1st RX descriptor ring 1404 */ 1405 rx_ring = &sc->sc_rx_ring[0]; 1406 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1407 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1408 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1409 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1410 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1411 1412 /* Match ET_RX_RING0_POS */ 1413 rx_ring->rr_index = 0; 1414 rx_ring->rr_wrap = 1; 1415 1416 /* 1417 * RX intr moderation 1418 */ 1419 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1420 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1421 1422 return 0; 1423 } 1424 1425 int 1426 et_init_txdma(struct et_softc *sc) 1427 { 1428 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1429 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1430 int error; 1431 1432 error = et_stop_txdma(sc); 1433 if (error) { 1434 printf("%s: can't init TX DMA engine\n", sc->sc_dev.dv_xname); 1435 return error; 1436 } 1437 1438 /* 1439 * Install TX descriptor ring 1440 */ 1441 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1442 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1443 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1444 1445 /* 1446 * Install TX status 1447 */ 1448 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1449 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1450 1451 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1452 1453 /* Match ET_TX_READY_POS */ 1454 tx_ring->tr_ready_index = 0; 1455 tx_ring->tr_ready_wrap = 0; 1456 1457 return 0; 1458 } 1459 1460 void 1461 et_init_mac(struct et_softc *sc) 1462 { 1463 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1464 const uint8_t *eaddr = LLADDR(ifp->if_sadl); 1465 uint32_t val; 1466 1467 /* Reset MAC */ 1468 CSR_WRITE_4(sc, ET_MAC_CFG1, 1469 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1470 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1471 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1472 1473 /* 1474 * Setup inter packet gap 1475 */ 1476 val = __SHIFTIN(56, ET_IPG_NONB2B_1) | 1477 __SHIFTIN(88, ET_IPG_NONB2B_2) | 1478 __SHIFTIN(80, ET_IPG_MINIFG) | 1479 __SHIFTIN(96, ET_IPG_B2B); 1480 CSR_WRITE_4(sc, ET_IPG, val); 1481 1482 /* 1483 * Setup half duplex mode 1484 */ 1485 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 1486 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 1487 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 1488 ET_MAC_HDX_EXC_DEFER; 1489 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1490 1491 /* Clear MAC control */ 1492 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1493 1494 /* Reset MII */ 1495 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1496 1497 /* 1498 * Set MAC address 1499 */ 1500 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1501 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1502 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1503 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1504 1505 /* Set max frame length */ 1506 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1507 1508 /* Bring MAC out of reset state */ 1509 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1510 } 1511 1512 void 1513 et_init_rxmac(struct et_softc *sc) 1514 { 1515 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1516 const uint8_t *eaddr = LLADDR(ifp->if_sadl); 1517 uint32_t val; 1518 int i; 1519 1520 /* Disable RX MAC and WOL */ 1521 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1522 1523 /* 1524 * Clear all WOL related registers 1525 */ 1526 for (i = 0; i < 3; ++i) 1527 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1528 for (i = 0; i < 20; ++i) 1529 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1530 1531 /* 1532 * Set WOL source address. XXX is this necessary? 1533 */ 1534 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1535 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1536 val = (eaddr[0] << 8) | eaddr[1]; 1537 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1538 1539 /* Clear packet filters */ 1540 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1541 1542 /* No ucast filtering */ 1543 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1544 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1545 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1546 1547 if (ifp->if_hardmtu > 8192) { 1548 /* 1549 * In order to transmit jumbo packets greater than 8k, 1550 * the FIFO between RX MAC and RX DMA needs to be reduced 1551 * in size to (16k - MTU). In order to implement this, we 1552 * must use "cut through" mode in the RX MAC, which chops 1553 * packets down into segments which are (max_size * 16). 1554 * In this case we selected 256 bytes, since this is the 1555 * size of the PCI-Express TLP's that the 1310 uses. 1556 */ 1557 val = __SHIFTIN(16, ET_RXMAC_MC_SEGSZ_MAX) | 1558 ET_RXMAC_MC_SEGSZ_ENABLE; 1559 } else { 1560 val = 0; 1561 } 1562 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1563 1564 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1565 1566 /* Initialize RX MAC management register */ 1567 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1568 1569 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1570 1571 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1572 ET_RXMAC_MGT_PASS_ECRC | 1573 ET_RXMAC_MGT_PASS_ELEN | 1574 ET_RXMAC_MGT_PASS_ETRUNC | 1575 ET_RXMAC_MGT_CHECK_PKT); 1576 1577 /* 1578 * Configure runt filtering (may not work on certain chip generation) 1579 */ 1580 val = __SHIFTIN(ETHER_MIN_LEN, ET_PKTFILT_MINLEN) | ET_PKTFILT_FRAG; 1581 CSR_WRITE_4(sc, ET_PKTFILT, val); 1582 1583 /* Enable RX MAC but leave WOL disabled */ 1584 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1585 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1586 1587 /* 1588 * Setup multicast hash and allmulti/promisc mode 1589 */ 1590 et_setmulti(sc); 1591 } 1592 1593 void 1594 et_init_txmac(struct et_softc *sc) 1595 { 1596 /* Disable TX MAC and FC(?) */ 1597 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1598 1599 /* No flow control yet */ 1600 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0); 1601 1602 /* Enable TX MAC but leave FC(?) diabled */ 1603 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 1604 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 1605 } 1606 1607 int 1608 et_start_rxdma(struct et_softc *sc) 1609 { 1610 uint32_t val = 0; 1611 1612 val |= __SHIFTIN(sc->sc_rx_data[0].rbd_bufsize, 1613 ET_RXDMA_CTRL_RING0_SIZE) | 1614 ET_RXDMA_CTRL_RING0_ENABLE; 1615 val |= __SHIFTIN(sc->sc_rx_data[1].rbd_bufsize, 1616 ET_RXDMA_CTRL_RING1_SIZE) | 1617 ET_RXDMA_CTRL_RING1_ENABLE; 1618 1619 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 1620 1621 DELAY(5); 1622 1623 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 1624 printf("%s: can't start RX DMA engine\n", sc->sc_dev.dv_xname); 1625 return ETIMEDOUT; 1626 } 1627 return 0; 1628 } 1629 1630 int 1631 et_start_txdma(struct et_softc *sc) 1632 { 1633 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 1634 return 0; 1635 } 1636 1637 int 1638 et_enable_txrx(struct et_softc *sc) 1639 { 1640 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1641 uint32_t val; 1642 int i; 1643 1644 val = CSR_READ_4(sc, ET_MAC_CFG1); 1645 val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 1646 val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 1647 ET_MAC_CFG1_LOOPBACK); 1648 CSR_WRITE_4(sc, ET_MAC_CFG1, val); 1649 1650 et_ifmedia_upd(ifp); 1651 1652 #define NRETRY 100 1653 1654 for (i = 0; i < NRETRY; ++i) { 1655 val = CSR_READ_4(sc, ET_MAC_CFG1); 1656 if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 1657 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 1658 break; 1659 1660 DELAY(10); 1661 } 1662 if (i == NRETRY) { 1663 printf("%s: can't enable RX/TX\n", sc->sc_dev.dv_xname); 1664 return ETIMEDOUT; 1665 } 1666 1667 #undef NRETRY 1668 return 0; 1669 } 1670 1671 void 1672 et_rxeof(struct et_softc *sc) 1673 { 1674 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1675 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1676 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1677 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1678 uint32_t rxs_stat_ring; 1679 int rxst_wrap, rxst_index; 1680 1681 bus_dmamap_sync(sc->sc_dmat, rxsd->rxsd_dmap, 0, 1682 rxsd->rxsd_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1683 bus_dmamap_sync(sc->sc_dmat, rxst_ring->rsr_dmap, 0, 1684 rxst_ring->rsr_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1685 1686 rxs_stat_ring = rxsd->rxsd_status->rxs_stat_ring; 1687 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 1688 rxst_index = __SHIFTOUT(rxs_stat_ring, ET_RXS_STATRING_INDEX); 1689 1690 while (rxst_index != rxst_ring->rsr_index || 1691 rxst_wrap != rxst_ring->rsr_wrap) { 1692 struct et_rxbuf_data *rbd; 1693 struct et_rxdesc_ring *rx_ring; 1694 struct et_rxstat *st; 1695 struct et_rxbuf *rb; 1696 struct mbuf *m; 1697 int buflen, buf_idx, ring_idx; 1698 uint32_t rxstat_pos, rxring_pos; 1699 1700 KKASSERT(rxst_ring->rsr_index < ET_RX_NSTAT); 1701 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 1702 1703 buflen = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_LEN); 1704 buf_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_BUFIDX); 1705 ring_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_RINGIDX); 1706 1707 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 1708 rxst_ring->rsr_index = 0; 1709 rxst_ring->rsr_wrap ^= 1; 1710 } 1711 rxstat_pos = __SHIFTIN(rxst_ring->rsr_index, 1712 ET_RXSTAT_POS_INDEX); 1713 if (rxst_ring->rsr_wrap) 1714 rxstat_pos |= ET_RXSTAT_POS_WRAP; 1715 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 1716 1717 if (ring_idx >= ET_RX_NRING) { 1718 ifp->if_ierrors++; 1719 printf("%s: invalid ring index %d\n", 1720 sc->sc_dev.dv_xname, ring_idx); 1721 continue; 1722 } 1723 if (buf_idx >= ET_RX_NDESC) { 1724 ifp->if_ierrors++; 1725 printf("%s: invalid buf index %d\n", 1726 sc->sc_dev.dv_xname, buf_idx); 1727 continue; 1728 } 1729 1730 rbd = &sc->sc_rx_data[ring_idx]; 1731 rb = &rbd->rbd_buf[buf_idx]; 1732 m = rb->rb_mbuf; 1733 bus_dmamap_sync(sc->sc_dmat, rb->rb_dmap, 0, 1734 rb->rb_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1735 1736 if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) { 1737 if (buflen < ETHER_CRC_LEN) { 1738 m_freem(m); 1739 ifp->if_ierrors++; 1740 } else { 1741 m->m_pkthdr.len = m->m_len = buflen - 1742 ETHER_CRC_LEN; 1743 ml_enqueue(&ml, m); 1744 } 1745 } else { 1746 ifp->if_ierrors++; 1747 } 1748 1749 rx_ring = &sc->sc_rx_ring[ring_idx]; 1750 1751 if (buf_idx != rx_ring->rr_index) { 1752 printf("%s: WARNING!! ring %d, " 1753 "buf_idx %d, rr_idx %d\n", sc->sc_dev.dv_xname, 1754 ring_idx, buf_idx, rx_ring->rr_index); 1755 } 1756 1757 KKASSERT(rx_ring->rr_index < ET_RX_NDESC); 1758 if (++rx_ring->rr_index == ET_RX_NDESC) { 1759 rx_ring->rr_index = 0; 1760 rx_ring->rr_wrap ^= 1; 1761 } 1762 rxring_pos = __SHIFTIN(rx_ring->rr_index, ET_RX_RING_POS_INDEX); 1763 if (rx_ring->rr_wrap) 1764 rxring_pos |= ET_RX_RING_POS_WRAP; 1765 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 1766 } 1767 1768 if_input(ifp, &ml); 1769 } 1770 1771 int 1772 et_encap(struct et_softc *sc, struct mbuf **m0) 1773 { 1774 struct mbuf *m = *m0; 1775 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1776 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1777 struct et_txdesc *td; 1778 bus_dmamap_t map; 1779 int error, maxsegs, first_idx, last_idx, i; 1780 uint32_t tx_ready_pos, last_td_ctrl2; 1781 1782 maxsegs = ET_TX_NDESC - tbd->tbd_used; 1783 if (maxsegs > ET_NSEG_MAX) 1784 maxsegs = ET_NSEG_MAX; 1785 KASSERT(maxsegs >= ET_NSEG_SPARE, 1786 ("not enough spare TX desc (%d)\n", maxsegs)); 1787 1788 KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1789 first_idx = tx_ring->tr_ready_index; 1790 map = tbd->tbd_buf[first_idx].tb_dmap; 1791 1792 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1793 BUS_DMA_NOWAIT); 1794 if (!error && map->dm_nsegs == 0) { 1795 bus_dmamap_unload(sc->sc_dmat, map); 1796 error = EFBIG; 1797 } 1798 if (error && error != EFBIG) { 1799 printf("%s: can't load TX mbuf", sc->sc_dev.dv_xname); 1800 goto back; 1801 } 1802 if (error) { /* error == EFBIG */ 1803 if (m_defrag(m, M_DONTWAIT)) { 1804 printf("%s: can't defrag TX mbuf\n", 1805 sc->sc_dev.dv_xname); 1806 error = ENOBUFS; 1807 goto back; 1808 } 1809 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1810 BUS_DMA_NOWAIT); 1811 if (error || map->dm_nsegs == 0) { 1812 if (map->dm_nsegs == 0) { 1813 bus_dmamap_unload(sc->sc_dmat, map); 1814 error = EFBIG; 1815 } 1816 printf("%s: can't load defraged TX mbuf\n", 1817 sc->sc_dev.dv_xname); 1818 goto back; 1819 } 1820 } 1821 1822 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1823 BUS_DMASYNC_PREWRITE); 1824 1825 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 1826 sc->sc_tx += map->dm_nsegs; 1827 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 1828 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 1829 last_td_ctrl2 |= ET_TDCTRL2_INTR; 1830 } 1831 1832 last_idx = -1; 1833 for (i = 0; i < map->dm_nsegs; ++i) { 1834 int idx; 1835 1836 idx = (first_idx + i) % ET_TX_NDESC; 1837 td = &tx_ring->tr_desc[idx]; 1838 td->td_addr_hi = ET_ADDR_HI(map->dm_segs[i].ds_addr); 1839 td->td_addr_lo = ET_ADDR_LO(map->dm_segs[i].ds_addr); 1840 td->td_ctrl1 = 1841 __SHIFTIN(map->dm_segs[i].ds_len, ET_TDCTRL1_LEN); 1842 1843 if (i == map->dm_nsegs - 1) { /* Last frag */ 1844 td->td_ctrl2 = last_td_ctrl2; 1845 last_idx = idx; 1846 } 1847 1848 KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1849 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 1850 tx_ring->tr_ready_index = 0; 1851 tx_ring->tr_ready_wrap ^= 1; 1852 } 1853 } 1854 td = &tx_ring->tr_desc[first_idx]; 1855 td->td_ctrl2 |= ET_TDCTRL2_FIRST_FRAG; /* First frag */ 1856 1857 KKASSERT(last_idx >= 0); 1858 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 1859 tbd->tbd_buf[last_idx].tb_dmap = map; 1860 tbd->tbd_buf[last_idx].tb_mbuf = m; 1861 1862 tbd->tbd_used += map->dm_nsegs; 1863 KKASSERT(tbd->tbd_used <= ET_TX_NDESC); 1864 1865 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1866 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1867 1868 1869 tx_ready_pos = __SHIFTIN(tx_ring->tr_ready_index, 1870 ET_TX_READY_POS_INDEX); 1871 if (tx_ring->tr_ready_wrap) 1872 tx_ready_pos |= ET_TX_READY_POS_WRAP; 1873 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 1874 1875 error = 0; 1876 back: 1877 if (error) { 1878 m_freem(m); 1879 *m0 = NULL; 1880 } 1881 return error; 1882 } 1883 1884 void 1885 et_txeof(struct et_softc *sc) 1886 { 1887 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1888 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1889 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1890 uint32_t tx_done; 1891 int end, wrap; 1892 1893 if (tbd->tbd_used == 0) 1894 return; 1895 1896 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 1897 end = __SHIFTOUT(tx_done, ET_TX_DONE_POS_INDEX); 1898 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 1899 1900 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 1901 struct et_txbuf *tb; 1902 1903 KKASSERT(tbd->tbd_start_index < ET_TX_NDESC); 1904 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 1905 1906 bzero(&tx_ring->tr_desc[tbd->tbd_start_index], 1907 sizeof(struct et_txdesc)); 1908 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1909 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1910 1911 if (tb->tb_mbuf != NULL) { 1912 bus_dmamap_unload(sc->sc_dmat, tb->tb_dmap); 1913 m_freem(tb->tb_mbuf); 1914 tb->tb_mbuf = NULL; 1915 ifp->if_opackets++; 1916 } 1917 1918 if (++tbd->tbd_start_index == ET_TX_NDESC) { 1919 tbd->tbd_start_index = 0; 1920 tbd->tbd_start_wrap ^= 1; 1921 } 1922 1923 KKASSERT(tbd->tbd_used > 0); 1924 tbd->tbd_used--; 1925 } 1926 1927 if (tbd->tbd_used == 0) { 1928 timeout_del(&sc->sc_txtick); 1929 ifp->if_timer = 0; 1930 } 1931 if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC) 1932 ifq_clr_oactive(&ifp->if_snd); 1933 1934 et_start(ifp); 1935 } 1936 1937 void 1938 et_txtick(void *xsc) 1939 { 1940 struct et_softc *sc = xsc; 1941 int s; 1942 1943 s = splnet(); 1944 et_txeof(sc); 1945 splx(s); 1946 } 1947 1948 void 1949 et_tick(void *xsc) 1950 { 1951 struct et_softc *sc = xsc; 1952 int s; 1953 1954 s = splnet(); 1955 mii_tick(&sc->sc_miibus); 1956 timeout_add_sec(&sc->sc_tick, 1); 1957 splx(s); 1958 } 1959 1960 int 1961 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init) 1962 { 1963 return et_newbuf(rbd, buf_idx, init, MCLBYTES); 1964 } 1965 1966 int 1967 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init) 1968 { 1969 return et_newbuf(rbd, buf_idx, init, MHLEN); 1970 } 1971 1972 int 1973 et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0) 1974 { 1975 struct et_softc *sc = rbd->rbd_softc; 1976 struct et_rxdesc_ring *rx_ring; 1977 struct et_rxdesc *desc; 1978 struct et_rxbuf *rb; 1979 struct mbuf *m; 1980 bus_dmamap_t dmap; 1981 int error, len; 1982 1983 KKASSERT(buf_idx < ET_RX_NDESC); 1984 rb = &rbd->rbd_buf[buf_idx]; 1985 1986 if (len0 >= MINCLSIZE) { 1987 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 1988 if (m == NULL) 1989 return (ENOBUFS); 1990 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 1991 len = MCLBYTES; 1992 } else { 1993 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 1994 len = MHLEN; 1995 } 1996 1997 if (m == NULL) { 1998 error = ENOBUFS; 1999 2000 /* XXX for debug */ 2001 printf("%s: M_CLGET failed, size %d\n", sc->sc_dev.dv_xname, 2002 len0); 2003 if (init) { 2004 return error; 2005 } else { 2006 goto back; 2007 } 2008 } 2009 m->m_len = m->m_pkthdr.len = len; 2010 2011 /* 2012 * Try load RX mbuf into temporary DMA tag 2013 */ 2014 error = bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_mbuf_tmp_dmap, m, 2015 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT); 2016 if (error) { 2017 if (!error) { 2018 bus_dmamap_unload(sc->sc_dmat, sc->sc_mbuf_tmp_dmap); 2019 error = EFBIG; 2020 printf("%s: too many segments?!\n", 2021 sc->sc_dev.dv_xname); 2022 } 2023 m_freem(m); 2024 2025 /* XXX for debug */ 2026 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 2027 if (init) { 2028 return error; 2029 } else { 2030 goto back; 2031 } 2032 } 2033 2034 if (!init) 2035 bus_dmamap_unload(sc->sc_dmat, rb->rb_dmap); 2036 rb->rb_mbuf = m; 2037 2038 /* 2039 * Swap RX buf's DMA map with the loaded temporary one 2040 */ 2041 dmap = rb->rb_dmap; 2042 rb->rb_dmap = sc->sc_mbuf_tmp_dmap; 2043 rb->rb_paddr = rb->rb_dmap->dm_segs[0].ds_addr; 2044 sc->sc_mbuf_tmp_dmap = dmap; 2045 2046 error = 0; 2047 back: 2048 rx_ring = rbd->rbd_ring; 2049 desc = &rx_ring->rr_desc[buf_idx]; 2050 2051 desc->rd_addr_hi = ET_ADDR_HI(rb->rb_paddr); 2052 desc->rd_addr_lo = ET_ADDR_LO(rb->rb_paddr); 2053 desc->rd_ctrl = __SHIFTIN(buf_idx, ET_RDCTRL_BUFIDX); 2054 2055 bus_dmamap_sync(sc->sc_dmat, rx_ring->rr_dmap, 0, 2056 rx_ring->rr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2057 return error; 2058 } 2059