1 /* $OpenBSD: if_et.c,v 1.29 2015/07/08 14:41:30 mpi Exp $ */ 2 /* 3 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 4 * 5 * This code is derived from software contributed to The DragonFly Project 6 * by Sepherosa Ziehau <sepherosa@gmail.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.1 2007/10/12 14:12:42 sephe Exp $ 36 */ 37 38 #include "bpfilter.h" 39 #include "vlan.h" 40 41 #include <sys/param.h> 42 #include <sys/endian.h> 43 #include <sys/systm.h> 44 #include <sys/types.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/queue.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/timeout.h> 51 #include <sys/socket.h> 52 53 #include <machine/bus.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 59 #include <netinet/in.h> 60 #include <netinet/if_ether.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 #include <net/if_vlan_var.h> 66 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_etreg.h> 74 75 /* XXX temporary porting goop */ 76 #define KKASSERT(cond) if (!(cond)) panic("KKASSERT: %s in %s", #cond, __func__) 77 #undef KASSERT 78 #define KASSERT(cond, complaint) if (!(cond)) panic complaint 79 80 /* these macros in particular need to die, so gross */ 81 #define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) 82 #define __SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask)) 83 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) 84 /* XXX end porting goop */ 85 86 int et_match(struct device *, void *, void *); 87 void et_attach(struct device *, struct device *, void *); 88 int et_detach(struct device *, int); 89 90 int et_miibus_readreg(struct device *, int, int); 91 void et_miibus_writereg(struct device *, int, int, int); 92 void et_miibus_statchg(struct device *); 93 94 int et_init(struct ifnet *); 95 int et_ioctl(struct ifnet *, u_long, caddr_t); 96 void et_start(struct ifnet *); 97 void et_watchdog(struct ifnet *); 98 int et_ifmedia_upd(struct ifnet *); 99 void et_ifmedia_sts(struct ifnet *, struct ifmediareq *); 100 101 int et_intr(void *); 102 void et_enable_intrs(struct et_softc *, uint32_t); 103 void et_disable_intrs(struct et_softc *); 104 void et_rxeof(struct et_softc *); 105 void et_txeof(struct et_softc *); 106 void et_txtick(void *); 107 108 int et_dma_alloc(struct et_softc *); 109 void et_dma_free(struct et_softc *); 110 int et_dma_mem_create(struct et_softc *, bus_size_t, 111 void **, bus_addr_t *, bus_dmamap_t *, bus_dma_segment_t *); 112 void et_dma_mem_destroy(struct et_softc *, void *, bus_dmamap_t); 113 int et_dma_mbuf_create(struct et_softc *); 114 void et_dma_mbuf_destroy(struct et_softc *, int, const int[]); 115 116 int et_init_tx_ring(struct et_softc *); 117 int et_init_rx_ring(struct et_softc *); 118 void et_free_tx_ring(struct et_softc *); 119 void et_free_rx_ring(struct et_softc *); 120 int et_encap(struct et_softc *, struct mbuf **); 121 int et_newbuf(struct et_rxbuf_data *, int, int, int); 122 int et_newbuf_cluster(struct et_rxbuf_data *, int, int); 123 int et_newbuf_hdr(struct et_rxbuf_data *, int, int); 124 125 void et_stop(struct et_softc *); 126 int et_chip_init(struct et_softc *); 127 void et_chip_attach(struct et_softc *); 128 void et_init_mac(struct et_softc *); 129 void et_init_rxmac(struct et_softc *); 130 void et_init_txmac(struct et_softc *); 131 int et_init_rxdma(struct et_softc *); 132 int et_init_txdma(struct et_softc *); 133 int et_start_rxdma(struct et_softc *); 134 int et_start_txdma(struct et_softc *); 135 int et_stop_rxdma(struct et_softc *); 136 int et_stop_txdma(struct et_softc *); 137 int et_enable_txrx(struct et_softc *); 138 void et_reset(struct et_softc *); 139 int et_bus_config(struct et_softc *); 140 void et_get_eaddr(struct et_softc *, uint8_t[]); 141 void et_setmulti(struct et_softc *); 142 void et_tick(void *); 143 144 static int et_rx_intr_npkts = 32; 145 static int et_rx_intr_delay = 20; /* x10 usec */ 146 static int et_tx_intr_nsegs = 128; 147 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 148 149 struct et_bsize { 150 int bufsize; 151 et_newbuf_t newbuf; 152 }; 153 154 static const struct et_bsize et_bufsize[ET_RX_NRING] = { 155 { .bufsize = 0, .newbuf = et_newbuf_hdr }, 156 { .bufsize = 0, .newbuf = et_newbuf_cluster }, 157 }; 158 159 const struct pci_matchid et_devices[] = { 160 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FE }, 161 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_GBE } 162 }; 163 164 struct cfattach et_ca = { 165 sizeof (struct et_softc), et_match, et_attach, et_detach 166 }; 167 168 struct cfdriver et_cd = { 169 NULL, "et", DV_IFNET 170 }; 171 172 int 173 et_match(struct device *dev, void *match, void *aux) 174 { 175 return pci_matchbyid((struct pci_attach_args *)aux, et_devices, 176 sizeof (et_devices) / sizeof (et_devices[0])); 177 } 178 179 void 180 et_attach(struct device *parent, struct device *self, void *aux) 181 { 182 struct et_softc *sc = (struct et_softc *)self; 183 struct pci_attach_args *pa = aux; 184 pci_chipset_tag_t pc = pa->pa_pc; 185 pci_intr_handle_t ih; 186 const char *intrstr; 187 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 188 pcireg_t memtype; 189 int error; 190 191 /* 192 * Initialize tunables 193 */ 194 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 195 sc->sc_rx_intr_delay = et_rx_intr_delay; 196 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 197 sc->sc_timer = et_timer; 198 199 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ET_PCIR_BAR); 200 if (pci_mapreg_map(pa, ET_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 201 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 202 printf(": can't map mem space\n"); 203 return; 204 } 205 206 if (pci_intr_map(pa, &ih) != 0) { 207 printf(": can't map interrupt\n"); 208 return; 209 } 210 211 intrstr = pci_intr_string(pc, ih); 212 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, et_intr, sc, 213 sc->sc_dev.dv_xname); 214 if (sc->sc_irq_handle == NULL) { 215 printf(": could not establish interrupt"); 216 if (intrstr != NULL) 217 printf(" at %s", intrstr); 218 printf("\n"); 219 return; 220 } 221 printf(": %s", intrstr); 222 223 sc->sc_dmat = pa->pa_dmat; 224 sc->sc_pct = pa->pa_pc; 225 sc->sc_pcitag = pa->pa_tag; 226 227 error = et_bus_config(sc); 228 if (error) 229 return; 230 231 et_get_eaddr(sc, sc->sc_arpcom.ac_enaddr); 232 233 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 234 235 CSR_WRITE_4(sc, ET_PM, 236 ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE); 237 238 et_reset(sc); 239 240 et_disable_intrs(sc); 241 242 error = et_dma_alloc(sc); 243 if (error) 244 return; 245 246 ifp->if_softc = sc; 247 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 248 ifp->if_ioctl = et_ioctl; 249 ifp->if_start = et_start; 250 ifp->if_watchdog = et_watchdog; 251 IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC); 252 IFQ_SET_READY(&ifp->if_snd); 253 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 254 255 ifp->if_capabilities = IFCAP_VLAN_MTU; 256 257 et_chip_attach(sc); 258 259 sc->sc_miibus.mii_ifp = ifp; 260 sc->sc_miibus.mii_readreg = et_miibus_readreg; 261 sc->sc_miibus.mii_writereg = et_miibus_writereg; 262 sc->sc_miibus.mii_statchg = et_miibus_statchg; 263 264 ifmedia_init(&sc->sc_miibus.mii_media, 0, et_ifmedia_upd, 265 et_ifmedia_sts); 266 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 267 MII_OFFSET_ANY, 0); 268 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 269 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 270 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 271 0, NULL); 272 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 273 } else 274 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 275 276 if_attach(ifp); 277 ether_ifattach(ifp); 278 279 timeout_set(&sc->sc_tick, et_tick, sc); 280 timeout_set(&sc->sc_txtick, et_txtick, sc); 281 } 282 283 int 284 et_detach(struct device *self, int flags) 285 { 286 struct et_softc *sc = (struct et_softc *)self; 287 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 288 int s; 289 290 s = splnet(); 291 et_stop(sc); 292 splx(s); 293 294 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 295 296 /* Delete all remaining media. */ 297 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 298 299 ether_ifdetach(ifp); 300 if_detach(ifp); 301 et_dma_free(sc); 302 303 if (sc->sc_irq_handle != NULL) { 304 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 305 sc->sc_irq_handle = NULL; 306 } 307 308 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 309 310 return 0; 311 } 312 313 int 314 et_miibus_readreg(struct device *dev, int phy, int reg) 315 { 316 struct et_softc *sc = (struct et_softc *)dev; 317 uint32_t val; 318 int i, ret; 319 320 /* Stop any pending operations */ 321 CSR_WRITE_4(sc, ET_MII_CMD, 0); 322 323 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 324 __SHIFTIN(reg, ET_MII_ADDR_REG); 325 CSR_WRITE_4(sc, ET_MII_ADDR, val); 326 327 /* Start reading */ 328 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 329 330 #define NRETRY 50 331 332 for (i = 0; i < NRETRY; ++i) { 333 val = CSR_READ_4(sc, ET_MII_IND); 334 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 335 break; 336 DELAY(50); 337 } 338 if (i == NRETRY) { 339 printf("%s: read phy %d, reg %d timed out\n", 340 sc->sc_dev.dv_xname, phy, reg); 341 ret = 0; 342 goto back; 343 } 344 345 #undef NRETRY 346 347 val = CSR_READ_4(sc, ET_MII_STAT); 348 ret = __SHIFTOUT(val, ET_MII_STAT_VALUE); 349 350 back: 351 /* Make sure that the current operation is stopped */ 352 CSR_WRITE_4(sc, ET_MII_CMD, 0); 353 return ret; 354 } 355 356 void 357 et_miibus_writereg(struct device *dev, int phy, int reg, int val0) 358 { 359 struct et_softc *sc = (struct et_softc *)dev; 360 uint32_t val; 361 int i; 362 363 /* Stop any pending operations */ 364 CSR_WRITE_4(sc, ET_MII_CMD, 0); 365 366 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 367 __SHIFTIN(reg, ET_MII_ADDR_REG); 368 CSR_WRITE_4(sc, ET_MII_ADDR, val); 369 370 /* Start writing */ 371 CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val0, ET_MII_CTRL_VALUE)); 372 373 #define NRETRY 100 374 375 for (i = 0; i < NRETRY; ++i) { 376 val = CSR_READ_4(sc, ET_MII_IND); 377 if ((val & ET_MII_IND_BUSY) == 0) 378 break; 379 DELAY(50); 380 } 381 if (i == NRETRY) { 382 printf("%s: write phy %d, reg %d timed out\n", 383 sc->sc_dev.dv_xname, phy, reg); 384 et_miibus_readreg(dev, phy, reg); 385 } 386 387 #undef NRETRY 388 389 /* Make sure that the current operation is stopped */ 390 CSR_WRITE_4(sc, ET_MII_CMD, 0); 391 } 392 393 void 394 et_miibus_statchg(struct device *dev) 395 { 396 struct et_softc *sc = (struct et_softc *)dev; 397 struct mii_data *mii = &sc->sc_miibus; 398 uint32_t cfg2, ctrl; 399 400 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 401 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 402 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 403 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 404 __SHIFTIN(7, ET_MAC_CFG2_PREAMBLE_LEN); 405 406 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 407 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 408 409 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 410 cfg2 |= ET_MAC_CFG2_MODE_GMII; 411 } else { 412 cfg2 |= ET_MAC_CFG2_MODE_MII; 413 ctrl |= ET_MAC_CTRL_MODE_MII; 414 } 415 416 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 417 cfg2 |= ET_MAC_CFG2_FDX; 418 else 419 ctrl |= ET_MAC_CTRL_GHDX; 420 421 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 422 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 423 } 424 425 int 426 et_ifmedia_upd(struct ifnet *ifp) 427 { 428 struct et_softc *sc = ifp->if_softc; 429 struct mii_data *mii = &sc->sc_miibus; 430 431 if (mii->mii_instance != 0) { 432 struct mii_softc *miisc; 433 434 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 435 mii_phy_reset(miisc); 436 } 437 mii_mediachg(mii); 438 439 return 0; 440 } 441 442 void 443 et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 444 { 445 struct et_softc *sc = ifp->if_softc; 446 struct mii_data *mii = &sc->sc_miibus; 447 448 mii_pollstat(mii); 449 ifmr->ifm_active = mii->mii_media_active; 450 ifmr->ifm_status = mii->mii_media_status; 451 } 452 453 void 454 et_stop(struct et_softc *sc) 455 { 456 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 457 458 timeout_del(&sc->sc_tick); 459 timeout_del(&sc->sc_txtick); 460 461 et_stop_rxdma(sc); 462 et_stop_txdma(sc); 463 464 et_disable_intrs(sc); 465 466 et_free_tx_ring(sc); 467 et_free_rx_ring(sc); 468 469 et_reset(sc); 470 471 sc->sc_tx = 0; 472 sc->sc_tx_intr = 0; 473 474 ifp->if_timer = 0; 475 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 476 } 477 478 int 479 et_bus_config(struct et_softc *sc) 480 { 481 uint32_t val; //, max_plsz; 482 // uint16_t ack_latency, replay_timer; 483 484 /* 485 * Test whether EEPROM is valid 486 * NOTE: Read twice to get the correct value 487 */ 488 pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_EEPROM_MISC); 489 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_EEPROM_MISC); 490 491 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 492 printf("%s: EEPROM status error 0x%02x\n", 493 sc->sc_dev.dv_xname, val); 494 return ENXIO; 495 } 496 497 /* TODO: LED */ 498 #if 0 499 /* 500 * Configure ACK latency and replay timer according to 501 * max playload size 502 */ 503 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_DEVICE_CAPS); 504 max_plsz = val & ET_PCIM_DEVICE_CAPS_MAX_PLSZ; 505 506 switch (max_plsz) { 507 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 508 ack_latency = ET_PCIV_ACK_LATENCY_128; 509 replay_timer = ET_PCIV_REPLAY_TIMER_128; 510 break; 511 512 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 513 ack_latency = ET_PCIV_ACK_LATENCY_256; 514 replay_timer = ET_PCIV_REPLAY_TIMER_256; 515 break; 516 517 default: 518 ack_latency = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 519 ET_PCIR_ACK_LATENCY) >> 16; 520 replay_timer = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 521 ET_PCIR_REPLAY_TIMER) >> 16; 522 printf("%s: ack latency %u, replay timer %u\n", 523 sc->sc_dev.dv_xname, ack_latency, replay_timer); 524 break; 525 } 526 if (ack_latency != 0) { 527 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 528 ET_PCIR_ACK_LATENCY, ack_latency << 16); 529 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 530 ET_PCIR_REPLAY_TIMER, replay_timer << 16); 531 } 532 533 /* 534 * Set L0s and L1 latency timer to 2us 535 */ 536 val = ET_PCIV_L0S_LATENCY(2) | ET_PCIV_L1_LATENCY(2); 537 pci_conf_write(sc->sc_pct, sc->sc_pcitag, ET_PCIR_L0S_L1_LATENCY, 538 val << 24); 539 540 /* 541 * Set max read request size to 2048 bytes 542 */ 543 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 544 ET_PCIR_DEVICE_CTRL) >> 16; 545 val &= ~ET_PCIM_DEVICE_CTRL_MAX_RRSZ; 546 val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K; 547 pci_conf_write(sc->sc_pct, sc->sc_pcitag, ET_PCIR_DEVICE_CTRL, 548 val << 16); 549 #endif 550 551 return 0; 552 } 553 554 void 555 et_get_eaddr(struct et_softc *sc, uint8_t eaddr[]) 556 { 557 uint32_t r; 558 559 r = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_MACADDR_LO); 560 eaddr[0] = r & 0xff; 561 eaddr[1] = (r >> 8) & 0xff; 562 eaddr[2] = (r >> 16) & 0xff; 563 eaddr[3] = (r >> 24) & 0xff; 564 r = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_MACADDR_HI); 565 eaddr[4] = r & 0xff; 566 eaddr[5] = (r >> 8) & 0xff; 567 } 568 569 void 570 et_reset(struct et_softc *sc) 571 { 572 CSR_WRITE_4(sc, ET_MAC_CFG1, 573 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 574 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 575 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 576 577 CSR_WRITE_4(sc, ET_SWRST, 578 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 579 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 580 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 581 582 CSR_WRITE_4(sc, ET_MAC_CFG1, 583 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 584 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 585 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 586 } 587 588 void 589 et_disable_intrs(struct et_softc *sc) 590 { 591 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 592 } 593 594 void 595 et_enable_intrs(struct et_softc *sc, uint32_t intrs) 596 { 597 CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs); 598 } 599 600 int 601 et_dma_alloc(struct et_softc *sc) 602 { 603 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 604 struct et_txstatus_data *txsd = &sc->sc_tx_status; 605 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 606 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 607 int i, error; 608 609 /* 610 * Create TX ring DMA stuffs 611 */ 612 error = et_dma_mem_create(sc, ET_TX_RING_SIZE, 613 (void **)&tx_ring->tr_desc, &tx_ring->tr_paddr, &tx_ring->tr_dmap, 614 &tx_ring->tr_seg); 615 if (error) { 616 printf("%s: can't create TX ring DMA stuffs\n", 617 sc->sc_dev.dv_xname); 618 return error; 619 } 620 621 /* 622 * Create TX status DMA stuffs 623 */ 624 error = et_dma_mem_create(sc, sizeof(uint32_t), 625 (void **)&txsd->txsd_status, 626 &txsd->txsd_paddr, &txsd->txsd_dmap, &txsd->txsd_seg); 627 if (error) { 628 printf("%s: can't create TX status DMA stuffs\n", 629 sc->sc_dev.dv_xname); 630 return error; 631 } 632 633 /* 634 * Create DMA stuffs for RX rings 635 */ 636 for (i = 0; i < ET_RX_NRING; ++i) { 637 static const uint32_t rx_ring_posreg[ET_RX_NRING] = 638 { ET_RX_RING0_POS, ET_RX_RING1_POS }; 639 640 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 641 642 error = et_dma_mem_create(sc, ET_RX_RING_SIZE, 643 (void **)&rx_ring->rr_desc, 644 &rx_ring->rr_paddr, &rx_ring->rr_dmap, &rx_ring->rr_seg); 645 if (error) { 646 printf("%s: can't create DMA stuffs for " 647 "the %d RX ring\n", sc->sc_dev.dv_xname, i); 648 return error; 649 } 650 rx_ring->rr_posreg = rx_ring_posreg[i]; 651 } 652 653 /* 654 * Create RX stat ring DMA stuffs 655 */ 656 error = et_dma_mem_create(sc, ET_RXSTAT_RING_SIZE, 657 (void **)&rxst_ring->rsr_stat, 658 &rxst_ring->rsr_paddr, &rxst_ring->rsr_dmap, &rxst_ring->rsr_seg); 659 if (error) { 660 printf("%s: can't create RX stat ring DMA stuffs\n", 661 sc->sc_dev.dv_xname); 662 return error; 663 } 664 665 /* 666 * Create RX status DMA stuffs 667 */ 668 error = et_dma_mem_create(sc, sizeof(struct et_rxstatus), 669 (void **)&rxsd->rxsd_status, 670 &rxsd->rxsd_paddr, &rxsd->rxsd_dmap, &rxsd->rxsd_seg); 671 if (error) { 672 printf("%s: can't create RX status DMA stuffs\n", 673 sc->sc_dev.dv_xname); 674 return error; 675 } 676 677 /* 678 * Create mbuf DMA stuffs 679 */ 680 error = et_dma_mbuf_create(sc); 681 if (error) 682 return error; 683 684 return 0; 685 } 686 687 void 688 et_dma_free(struct et_softc *sc) 689 { 690 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 691 struct et_txstatus_data *txsd = &sc->sc_tx_status; 692 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 693 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 694 int i, rx_done[ET_RX_NRING]; 695 696 /* 697 * Destroy TX ring DMA stuffs 698 */ 699 et_dma_mem_destroy(sc, tx_ring->tr_desc, tx_ring->tr_dmap); 700 701 /* 702 * Destroy TX status DMA stuffs 703 */ 704 et_dma_mem_destroy(sc, txsd->txsd_status, txsd->txsd_dmap); 705 706 /* 707 * Destroy DMA stuffs for RX rings 708 */ 709 for (i = 0; i < ET_RX_NRING; ++i) { 710 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 711 712 et_dma_mem_destroy(sc, rx_ring->rr_desc, rx_ring->rr_dmap); 713 } 714 715 /* 716 * Destroy RX stat ring DMA stuffs 717 */ 718 et_dma_mem_destroy(sc, rxst_ring->rsr_stat, rxst_ring->rsr_dmap); 719 720 /* 721 * Destroy RX status DMA stuffs 722 */ 723 et_dma_mem_destroy(sc, rxsd->rxsd_status, rxsd->rxsd_dmap); 724 725 /* 726 * Destroy mbuf DMA stuffs 727 */ 728 for (i = 0; i < ET_RX_NRING; ++i) 729 rx_done[i] = ET_RX_NDESC; 730 et_dma_mbuf_destroy(sc, ET_TX_NDESC, rx_done); 731 } 732 733 int 734 et_dma_mbuf_create(struct et_softc *sc) 735 { 736 struct et_txbuf_data *tbd = &sc->sc_tx_data; 737 int i, error, rx_done[ET_RX_NRING]; 738 739 /* 740 * Create spare DMA map for RX mbufs 741 */ 742 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 743 BUS_DMA_NOWAIT, &sc->sc_mbuf_tmp_dmap); 744 if (error) { 745 printf("%s: can't create spare mbuf DMA map\n", 746 sc->sc_dev.dv_xname); 747 return error; 748 } 749 750 /* 751 * Create DMA maps for RX mbufs 752 */ 753 bzero(rx_done, sizeof(rx_done)); 754 for (i = 0; i < ET_RX_NRING; ++i) { 755 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 756 int j; 757 758 for (j = 0; j < ET_RX_NDESC; ++j) { 759 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 760 MCLBYTES, 0, BUS_DMA_NOWAIT, 761 &rbd->rbd_buf[j].rb_dmap); 762 if (error) { 763 printf("%s: can't create %d RX mbuf " 764 "for %d RX ring\n", sc->sc_dev.dv_xname, 765 j, i); 766 rx_done[i] = j; 767 et_dma_mbuf_destroy(sc, 0, rx_done); 768 return error; 769 } 770 } 771 rx_done[i] = ET_RX_NDESC; 772 773 rbd->rbd_softc = sc; 774 rbd->rbd_ring = &sc->sc_rx_ring[i]; 775 } 776 777 /* 778 * Create DMA maps for TX mbufs 779 */ 780 for (i = 0; i < ET_TX_NDESC; ++i) { 781 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 782 0, BUS_DMA_NOWAIT, &tbd->tbd_buf[i].tb_dmap); 783 if (error) { 784 printf("%s: can't create %d TX mbuf " 785 "DMA map\n", sc->sc_dev.dv_xname, i); 786 et_dma_mbuf_destroy(sc, i, rx_done); 787 return error; 788 } 789 } 790 791 return 0; 792 } 793 794 void 795 et_dma_mbuf_destroy(struct et_softc *sc, int tx_done, const int rx_done[]) 796 { 797 struct et_txbuf_data *tbd = &sc->sc_tx_data; 798 int i; 799 800 /* 801 * Destroy DMA maps for RX mbufs 802 */ 803 for (i = 0; i < ET_RX_NRING; ++i) { 804 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 805 int j; 806 807 for (j = 0; j < rx_done[i]; ++j) { 808 struct et_rxbuf *rb = &rbd->rbd_buf[j]; 809 810 KASSERT(rb->rb_mbuf == NULL, 811 ("RX mbuf in %d RX ring is not freed yet\n", i)); 812 bus_dmamap_destroy(sc->sc_dmat, rb->rb_dmap); 813 } 814 } 815 816 /* 817 * Destroy DMA maps for TX mbufs 818 */ 819 for (i = 0; i < tx_done; ++i) { 820 struct et_txbuf *tb = &tbd->tbd_buf[i]; 821 822 KASSERT(tb->tb_mbuf == NULL, ("TX mbuf is not freed yet\n")); 823 bus_dmamap_destroy(sc->sc_dmat, tb->tb_dmap); 824 } 825 826 /* 827 * Destroy spare mbuf DMA map 828 */ 829 bus_dmamap_destroy(sc->sc_dmat, sc->sc_mbuf_tmp_dmap); 830 } 831 832 int 833 et_dma_mem_create(struct et_softc *sc, bus_size_t size, 834 void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap, bus_dma_segment_t *seg) 835 { 836 int error, nsegs; 837 838 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 839 dmap); 840 if (error) { 841 printf("%s: can't create DMA map\n", sc->sc_dev.dv_xname); 842 return error; 843 } 844 845 error = bus_dmamem_alloc(sc->sc_dmat, size, ET_ALIGN, 0, seg, 846 1, &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 847 if (error) { 848 printf("%s: can't allocate DMA mem\n", sc->sc_dev.dv_xname); 849 return error; 850 } 851 852 error = bus_dmamem_map(sc->sc_dmat, seg, nsegs, 853 size, (caddr_t *)addr, BUS_DMA_NOWAIT); 854 if (error) { 855 printf("%s: can't map DMA mem\n", sc->sc_dev.dv_xname); 856 return (error); 857 } 858 859 error = bus_dmamap_load(sc->sc_dmat, *dmap, *addr, size, NULL, 860 BUS_DMA_WAITOK); 861 if (error) { 862 printf("%s: can't load DMA mem\n", sc->sc_dev.dv_xname); 863 bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)addr, 1); 864 return error; 865 } 866 867 *paddr = (*dmap)->dm_segs[0].ds_addr; 868 869 return 0; 870 } 871 872 void 873 et_dma_mem_destroy(struct et_softc *sc, void *addr, bus_dmamap_t dmap) 874 { 875 bus_dmamap_unload(sc->sc_dmat, dmap); 876 bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)&addr, 1); 877 } 878 879 void 880 et_chip_attach(struct et_softc *sc) 881 { 882 uint32_t val; 883 884 /* 885 * Perform minimal initialization 886 */ 887 888 /* Disable loopback */ 889 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 890 891 /* Reset MAC */ 892 CSR_WRITE_4(sc, ET_MAC_CFG1, 893 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 894 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 895 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 896 897 /* 898 * Setup half duplex mode 899 */ 900 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 901 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 902 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 903 ET_MAC_HDX_EXC_DEFER; 904 CSR_WRITE_4(sc, ET_MAC_HDX, val); 905 906 /* Clear MAC control */ 907 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 908 909 /* Reset MII */ 910 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 911 912 /* Bring MAC out of reset state */ 913 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 914 915 /* Enable memory controllers */ 916 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 917 } 918 919 int 920 et_intr(void *xsc) 921 { 922 struct et_softc *sc = xsc; 923 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 924 uint32_t intrs; 925 926 if ((ifp->if_flags & IFF_RUNNING) == 0) 927 return (0); 928 929 intrs = CSR_READ_4(sc, ET_INTR_STATUS); 930 if (intrs == 0 || intrs == 0xffffffff) 931 return (0); 932 933 et_disable_intrs(sc); 934 intrs &= ET_INTRS; 935 if (intrs == 0) /* Not interested */ 936 goto back; 937 938 if (intrs & ET_INTR_RXEOF) 939 et_rxeof(sc); 940 if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER)) 941 et_txeof(sc); 942 if (intrs & ET_INTR_TIMER) 943 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 944 back: 945 et_enable_intrs(sc, ET_INTRS); 946 947 return (1); 948 } 949 950 int 951 et_init(struct ifnet *ifp) 952 { 953 struct et_softc *sc = ifp->if_softc; 954 int error, i, s; 955 956 s = splnet(); 957 958 et_stop(sc); 959 960 for (i = 0; i < ET_RX_NRING; ++i) { 961 sc->sc_rx_data[i].rbd_bufsize = et_bufsize[i].bufsize; 962 sc->sc_rx_data[i].rbd_newbuf = et_bufsize[i].newbuf; 963 } 964 965 error = et_init_tx_ring(sc); 966 if (error) 967 goto back; 968 969 error = et_init_rx_ring(sc); 970 if (error) 971 goto back; 972 973 error = et_chip_init(sc); 974 if (error) 975 goto back; 976 977 error = et_enable_txrx(sc); 978 if (error) 979 goto back; 980 981 error = et_start_rxdma(sc); 982 if (error) 983 goto back; 984 985 error = et_start_txdma(sc); 986 if (error) 987 goto back; 988 989 et_enable_intrs(sc, ET_INTRS); 990 991 timeout_add_sec(&sc->sc_tick, 1); 992 993 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 994 995 ifp->if_flags |= IFF_RUNNING; 996 ifp->if_flags &= ~IFF_OACTIVE; 997 back: 998 if (error) 999 et_stop(sc); 1000 1001 splx(s); 1002 1003 return (0); 1004 } 1005 1006 int 1007 et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1008 { 1009 struct et_softc *sc = ifp->if_softc; 1010 struct ifaddr *ifa = (struct ifaddr *)data; 1011 struct ifreq *ifr = (struct ifreq *)data; 1012 int s, error = 0; 1013 1014 s = splnet(); 1015 1016 switch (cmd) { 1017 case SIOCSIFADDR: 1018 ifp->if_flags |= IFF_UP; 1019 if (!(ifp->if_flags & IFF_RUNNING)) 1020 et_init(ifp); 1021 if (ifa->ifa_addr->sa_family == AF_INET) 1022 arp_ifinit(&sc->sc_arpcom, ifa); 1023 break; 1024 1025 case SIOCSIFFLAGS: 1026 if (ifp->if_flags & IFF_UP) { 1027 /* 1028 * If only the PROMISC or ALLMULTI flag changes, then 1029 * don't do a full re-init of the chip, just update 1030 * the Rx filter. 1031 */ 1032 if ((ifp->if_flags & IFF_RUNNING) && 1033 ((ifp->if_flags ^ sc->sc_if_flags) & 1034 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1035 et_setmulti(sc); 1036 } else { 1037 if (!(ifp->if_flags & IFF_RUNNING)) 1038 et_init(ifp); 1039 } 1040 } else { 1041 if (ifp->if_flags & IFF_RUNNING) 1042 et_stop(sc); 1043 } 1044 sc->sc_if_flags = ifp->if_flags; 1045 break; 1046 1047 case SIOCSIFMEDIA: 1048 case SIOCGIFMEDIA: 1049 error = ifmedia_ioctl(ifp, ifr, &sc->sc_miibus.mii_media, cmd); 1050 break; 1051 1052 default: 1053 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1054 } 1055 1056 if (error == ENETRESET) { 1057 if (ifp->if_flags & IFF_RUNNING) 1058 et_setmulti(sc); 1059 error = 0; 1060 } 1061 1062 splx(s); 1063 return error; 1064 } 1065 1066 void 1067 et_start(struct ifnet *ifp) 1068 { 1069 struct et_softc *sc = ifp->if_softc; 1070 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1071 int trans; 1072 struct mbuf *m; 1073 1074 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1075 return; 1076 1077 trans = 0; 1078 for (;;) { 1079 IFQ_DEQUEUE(&ifp->if_snd, m); 1080 if (m == NULL) 1081 break; 1082 1083 if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) { 1084 ifp->if_flags |= IFF_OACTIVE; 1085 break; 1086 } 1087 1088 if (et_encap(sc, &m)) { 1089 ifp->if_oerrors++; 1090 ifp->if_flags |= IFF_OACTIVE; 1091 break; 1092 } 1093 1094 trans = 1; 1095 1096 #if NBPFILTER > 0 1097 if (ifp->if_bpf != NULL) 1098 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1099 #endif 1100 } 1101 1102 if (trans) { 1103 timeout_add_sec(&sc->sc_txtick, 1); 1104 ifp->if_timer = 5; 1105 } 1106 } 1107 1108 void 1109 et_watchdog(struct ifnet *ifp) 1110 { 1111 struct et_softc *sc = ifp->if_softc; 1112 printf("%s: watchdog timed out\n", sc->sc_dev.dv_xname); 1113 1114 et_init(ifp); 1115 et_start(ifp); 1116 } 1117 1118 int 1119 et_stop_rxdma(struct et_softc *sc) 1120 { 1121 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1122 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1123 1124 DELAY(5); 1125 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1126 printf("%s: can't stop RX DMA engine\n", sc->sc_dev.dv_xname); 1127 return ETIMEDOUT; 1128 } 1129 return 0; 1130 } 1131 1132 int 1133 et_stop_txdma(struct et_softc *sc) 1134 { 1135 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1136 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1137 return 0; 1138 } 1139 1140 void 1141 et_free_tx_ring(struct et_softc *sc) 1142 { 1143 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1144 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1145 int i; 1146 1147 for (i = 0; i < ET_TX_NDESC; ++i) { 1148 struct et_txbuf *tb = &tbd->tbd_buf[i]; 1149 1150 if (tb->tb_mbuf != NULL) { 1151 bus_dmamap_unload(sc->sc_dmat, tb->tb_dmap); 1152 m_freem(tb->tb_mbuf); 1153 tb->tb_mbuf = NULL; 1154 } 1155 } 1156 1157 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1158 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1159 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1160 } 1161 1162 void 1163 et_free_rx_ring(struct et_softc *sc) 1164 { 1165 int n; 1166 1167 for (n = 0; n < ET_RX_NRING; ++n) { 1168 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1169 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n]; 1170 int i; 1171 1172 for (i = 0; i < ET_RX_NDESC; ++i) { 1173 struct et_rxbuf *rb = &rbd->rbd_buf[i]; 1174 1175 if (rb->rb_mbuf != NULL) { 1176 bus_dmamap_unload(sc->sc_dmat, rb->rb_dmap); 1177 m_freem(rb->rb_mbuf); 1178 rb->rb_mbuf = NULL; 1179 } 1180 } 1181 1182 bzero(rx_ring->rr_desc, ET_RX_RING_SIZE); 1183 bus_dmamap_sync(sc->sc_dmat, rx_ring->rr_dmap, 0, 1184 rx_ring->rr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1185 } 1186 } 1187 1188 void 1189 et_setmulti(struct et_softc *sc) 1190 { 1191 struct arpcom *ac = &sc->sc_arpcom; 1192 struct ifnet *ifp = &ac->ac_if; 1193 uint32_t hash[4] = { 0, 0, 0, 0 }; 1194 uint32_t rxmac_ctrl, pktfilt; 1195 struct ether_multi *enm; 1196 struct ether_multistep step; 1197 uint8_t addr[ETHER_ADDR_LEN]; 1198 int i, count; 1199 1200 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1201 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1202 1203 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1204 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1205 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1206 goto back; 1207 } 1208 1209 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1210 1211 count = 0; 1212 ETHER_FIRST_MULTI(step, ac, enm); 1213 while (enm != NULL) { 1214 uint32_t *hp, h; 1215 1216 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1217 addr[i] &= enm->enm_addrlo[i]; 1218 } 1219 1220 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)addr), 1221 ETHER_ADDR_LEN); 1222 h = (h & 0x3f800000) >> 23; 1223 1224 hp = &hash[0]; 1225 if (h >= 32 && h < 64) { 1226 h -= 32; 1227 hp = &hash[1]; 1228 } else if (h >= 64 && h < 96) { 1229 h -= 64; 1230 hp = &hash[2]; 1231 } else if (h >= 96) { 1232 h -= 96; 1233 hp = &hash[3]; 1234 } 1235 *hp |= (1 << h); 1236 1237 ++count; 1238 ETHER_NEXT_MULTI(step, enm); 1239 } 1240 1241 for (i = 0; i < 4; ++i) 1242 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1243 1244 if (count > 0) 1245 pktfilt |= ET_PKTFILT_MCAST; 1246 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1247 back: 1248 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1249 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1250 } 1251 1252 int 1253 et_chip_init(struct et_softc *sc) 1254 { 1255 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1256 uint32_t rxq_end; 1257 int error; 1258 1259 /* 1260 * Split internal memory between TX and RX according to MTU 1261 */ 1262 if (ifp->if_hardmtu < 2048) 1263 rxq_end = 0x2bc; 1264 else if (ifp->if_hardmtu < 8192) 1265 rxq_end = 0x1ff; 1266 else 1267 rxq_end = 0x1b3; 1268 CSR_WRITE_4(sc, ET_RXQ_START, 0); 1269 CSR_WRITE_4(sc, ET_RXQ_END, rxq_end); 1270 CSR_WRITE_4(sc, ET_TXQ_START, rxq_end + 1); 1271 CSR_WRITE_4(sc, ET_TXQ_END, ET_INTERN_MEM_END); 1272 1273 /* No loopback */ 1274 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1275 1276 /* Clear MSI configure */ 1277 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1278 1279 /* Disable timer */ 1280 CSR_WRITE_4(sc, ET_TIMER, 0); 1281 1282 /* Initialize MAC */ 1283 et_init_mac(sc); 1284 1285 /* Enable memory controllers */ 1286 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1287 1288 /* Initialize RX MAC */ 1289 et_init_rxmac(sc); 1290 1291 /* Initialize TX MAC */ 1292 et_init_txmac(sc); 1293 1294 /* Initialize RX DMA engine */ 1295 error = et_init_rxdma(sc); 1296 if (error) 1297 return error; 1298 1299 /* Initialize TX DMA engine */ 1300 error = et_init_txdma(sc); 1301 if (error) 1302 return error; 1303 1304 return 0; 1305 } 1306 1307 int 1308 et_init_tx_ring(struct et_softc *sc) 1309 { 1310 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1311 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1312 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1313 1314 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1315 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1316 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1317 1318 tbd->tbd_start_index = 0; 1319 tbd->tbd_start_wrap = 0; 1320 tbd->tbd_used = 0; 1321 1322 bzero(txsd->txsd_status, sizeof(uint32_t)); 1323 bus_dmamap_sync(sc->sc_dmat, txsd->txsd_dmap, 0, 1324 txsd->txsd_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1325 return 0; 1326 } 1327 1328 int 1329 et_init_rx_ring(struct et_softc *sc) 1330 { 1331 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1332 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1333 int n; 1334 1335 for (n = 0; n < ET_RX_NRING; ++n) { 1336 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1337 int i, error; 1338 1339 for (i = 0; i < ET_RX_NDESC; ++i) { 1340 error = rbd->rbd_newbuf(rbd, i, 1); 1341 if (error) { 1342 printf("%s: %d ring %d buf, newbuf failed: " 1343 "%d\n", sc->sc_dev.dv_xname, n, i, error); 1344 return error; 1345 } 1346 } 1347 } 1348 1349 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1350 bus_dmamap_sync(sc->sc_dmat, rxsd->rxsd_dmap, 0, 1351 rxsd->rxsd_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1352 1353 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1354 bus_dmamap_sync(sc->sc_dmat, rxst_ring->rsr_dmap, 0, 1355 rxst_ring->rsr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1356 1357 return 0; 1358 } 1359 1360 int 1361 et_init_rxdma(struct et_softc *sc) 1362 { 1363 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1364 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1365 struct et_rxdesc_ring *rx_ring; 1366 int error; 1367 1368 error = et_stop_rxdma(sc); 1369 if (error) { 1370 printf("%s: can't init RX DMA engine\n", sc->sc_dev.dv_xname); 1371 return error; 1372 } 1373 1374 /* 1375 * Install RX status 1376 */ 1377 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1378 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1379 1380 /* 1381 * Install RX stat ring 1382 */ 1383 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1384 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1385 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1386 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1387 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1388 1389 /* Match ET_RXSTAT_POS */ 1390 rxst_ring->rsr_index = 0; 1391 rxst_ring->rsr_wrap = 0; 1392 1393 /* 1394 * Install the 2nd RX descriptor ring 1395 */ 1396 rx_ring = &sc->sc_rx_ring[1]; 1397 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1398 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1399 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1400 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1401 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1402 1403 /* Match ET_RX_RING1_POS */ 1404 rx_ring->rr_index = 0; 1405 rx_ring->rr_wrap = 1; 1406 1407 /* 1408 * Install the 1st RX descriptor ring 1409 */ 1410 rx_ring = &sc->sc_rx_ring[0]; 1411 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1412 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1413 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1414 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1415 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1416 1417 /* Match ET_RX_RING0_POS */ 1418 rx_ring->rr_index = 0; 1419 rx_ring->rr_wrap = 1; 1420 1421 /* 1422 * RX intr moderation 1423 */ 1424 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1425 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1426 1427 return 0; 1428 } 1429 1430 int 1431 et_init_txdma(struct et_softc *sc) 1432 { 1433 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1434 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1435 int error; 1436 1437 error = et_stop_txdma(sc); 1438 if (error) { 1439 printf("%s: can't init TX DMA engine\n", sc->sc_dev.dv_xname); 1440 return error; 1441 } 1442 1443 /* 1444 * Install TX descriptor ring 1445 */ 1446 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1447 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1448 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1449 1450 /* 1451 * Install TX status 1452 */ 1453 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1454 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1455 1456 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1457 1458 /* Match ET_TX_READY_POS */ 1459 tx_ring->tr_ready_index = 0; 1460 tx_ring->tr_ready_wrap = 0; 1461 1462 return 0; 1463 } 1464 1465 void 1466 et_init_mac(struct et_softc *sc) 1467 { 1468 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1469 const uint8_t *eaddr = LLADDR(ifp->if_sadl); 1470 uint32_t val; 1471 1472 /* Reset MAC */ 1473 CSR_WRITE_4(sc, ET_MAC_CFG1, 1474 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1475 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1476 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1477 1478 /* 1479 * Setup inter packet gap 1480 */ 1481 val = __SHIFTIN(56, ET_IPG_NONB2B_1) | 1482 __SHIFTIN(88, ET_IPG_NONB2B_2) | 1483 __SHIFTIN(80, ET_IPG_MINIFG) | 1484 __SHIFTIN(96, ET_IPG_B2B); 1485 CSR_WRITE_4(sc, ET_IPG, val); 1486 1487 /* 1488 * Setup half duplex mode 1489 */ 1490 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 1491 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 1492 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 1493 ET_MAC_HDX_EXC_DEFER; 1494 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1495 1496 /* Clear MAC control */ 1497 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1498 1499 /* Reset MII */ 1500 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1501 1502 /* 1503 * Set MAC address 1504 */ 1505 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1506 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1507 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1508 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1509 1510 /* Set max frame length */ 1511 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1512 1513 /* Bring MAC out of reset state */ 1514 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1515 } 1516 1517 void 1518 et_init_rxmac(struct et_softc *sc) 1519 { 1520 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1521 const uint8_t *eaddr = LLADDR(ifp->if_sadl); 1522 uint32_t val; 1523 int i; 1524 1525 /* Disable RX MAC and WOL */ 1526 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1527 1528 /* 1529 * Clear all WOL related registers 1530 */ 1531 for (i = 0; i < 3; ++i) 1532 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1533 for (i = 0; i < 20; ++i) 1534 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1535 1536 /* 1537 * Set WOL source address. XXX is this necessary? 1538 */ 1539 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1540 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1541 val = (eaddr[0] << 8) | eaddr[1]; 1542 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1543 1544 /* Clear packet filters */ 1545 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1546 1547 /* No ucast filtering */ 1548 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1549 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1550 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1551 1552 if (ifp->if_hardmtu > 8192) { 1553 /* 1554 * In order to transmit jumbo packets greater than 8k, 1555 * the FIFO between RX MAC and RX DMA needs to be reduced 1556 * in size to (16k - MTU). In order to implement this, we 1557 * must use "cut through" mode in the RX MAC, which chops 1558 * packets down into segments which are (max_size * 16). 1559 * In this case we selected 256 bytes, since this is the 1560 * size of the PCI-Express TLP's that the 1310 uses. 1561 */ 1562 val = __SHIFTIN(16, ET_RXMAC_MC_SEGSZ_MAX) | 1563 ET_RXMAC_MC_SEGSZ_ENABLE; 1564 } else { 1565 val = 0; 1566 } 1567 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1568 1569 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1570 1571 /* Initialize RX MAC management register */ 1572 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1573 1574 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1575 1576 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1577 ET_RXMAC_MGT_PASS_ECRC | 1578 ET_RXMAC_MGT_PASS_ELEN | 1579 ET_RXMAC_MGT_PASS_ETRUNC | 1580 ET_RXMAC_MGT_CHECK_PKT); 1581 1582 /* 1583 * Configure runt filtering (may not work on certain chip generation) 1584 */ 1585 val = __SHIFTIN(ETHER_MIN_LEN, ET_PKTFILT_MINLEN) | ET_PKTFILT_FRAG; 1586 CSR_WRITE_4(sc, ET_PKTFILT, val); 1587 1588 /* Enable RX MAC but leave WOL disabled */ 1589 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1590 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1591 1592 /* 1593 * Setup multicast hash and allmulti/promisc mode 1594 */ 1595 et_setmulti(sc); 1596 } 1597 1598 void 1599 et_init_txmac(struct et_softc *sc) 1600 { 1601 /* Disable TX MAC and FC(?) */ 1602 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1603 1604 /* No flow control yet */ 1605 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0); 1606 1607 /* Enable TX MAC but leave FC(?) diabled */ 1608 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 1609 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 1610 } 1611 1612 int 1613 et_start_rxdma(struct et_softc *sc) 1614 { 1615 uint32_t val = 0; 1616 1617 val |= __SHIFTIN(sc->sc_rx_data[0].rbd_bufsize, 1618 ET_RXDMA_CTRL_RING0_SIZE) | 1619 ET_RXDMA_CTRL_RING0_ENABLE; 1620 val |= __SHIFTIN(sc->sc_rx_data[1].rbd_bufsize, 1621 ET_RXDMA_CTRL_RING1_SIZE) | 1622 ET_RXDMA_CTRL_RING1_ENABLE; 1623 1624 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 1625 1626 DELAY(5); 1627 1628 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 1629 printf("%s: can't start RX DMA engine\n", sc->sc_dev.dv_xname); 1630 return ETIMEDOUT; 1631 } 1632 return 0; 1633 } 1634 1635 int 1636 et_start_txdma(struct et_softc *sc) 1637 { 1638 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 1639 return 0; 1640 } 1641 1642 int 1643 et_enable_txrx(struct et_softc *sc) 1644 { 1645 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1646 uint32_t val; 1647 int i; 1648 1649 val = CSR_READ_4(sc, ET_MAC_CFG1); 1650 val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 1651 val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 1652 ET_MAC_CFG1_LOOPBACK); 1653 CSR_WRITE_4(sc, ET_MAC_CFG1, val); 1654 1655 et_ifmedia_upd(ifp); 1656 1657 #define NRETRY 100 1658 1659 for (i = 0; i < NRETRY; ++i) { 1660 val = CSR_READ_4(sc, ET_MAC_CFG1); 1661 if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 1662 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 1663 break; 1664 1665 DELAY(10); 1666 } 1667 if (i == NRETRY) { 1668 printf("%s: can't enable RX/TX\n", sc->sc_dev.dv_xname); 1669 return ETIMEDOUT; 1670 } 1671 1672 #undef NRETRY 1673 return 0; 1674 } 1675 1676 void 1677 et_rxeof(struct et_softc *sc) 1678 { 1679 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1680 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1681 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1682 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1683 uint32_t rxs_stat_ring; 1684 int rxst_wrap, rxst_index; 1685 1686 bus_dmamap_sync(sc->sc_dmat, rxsd->rxsd_dmap, 0, 1687 rxsd->rxsd_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1688 bus_dmamap_sync(sc->sc_dmat, rxst_ring->rsr_dmap, 0, 1689 rxst_ring->rsr_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1690 1691 rxs_stat_ring = rxsd->rxsd_status->rxs_stat_ring; 1692 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 1693 rxst_index = __SHIFTOUT(rxs_stat_ring, ET_RXS_STATRING_INDEX); 1694 1695 while (rxst_index != rxst_ring->rsr_index || 1696 rxst_wrap != rxst_ring->rsr_wrap) { 1697 struct et_rxbuf_data *rbd; 1698 struct et_rxdesc_ring *rx_ring; 1699 struct et_rxstat *st; 1700 struct et_rxbuf *rb; 1701 struct mbuf *m; 1702 int buflen, buf_idx, ring_idx; 1703 uint32_t rxstat_pos, rxring_pos; 1704 1705 KKASSERT(rxst_ring->rsr_index < ET_RX_NSTAT); 1706 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 1707 1708 buflen = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_LEN); 1709 buf_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_BUFIDX); 1710 ring_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_RINGIDX); 1711 1712 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 1713 rxst_ring->rsr_index = 0; 1714 rxst_ring->rsr_wrap ^= 1; 1715 } 1716 rxstat_pos = __SHIFTIN(rxst_ring->rsr_index, 1717 ET_RXSTAT_POS_INDEX); 1718 if (rxst_ring->rsr_wrap) 1719 rxstat_pos |= ET_RXSTAT_POS_WRAP; 1720 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 1721 1722 if (ring_idx >= ET_RX_NRING) { 1723 ifp->if_ierrors++; 1724 printf("%s: invalid ring index %d\n", 1725 sc->sc_dev.dv_xname, ring_idx); 1726 continue; 1727 } 1728 if (buf_idx >= ET_RX_NDESC) { 1729 ifp->if_ierrors++; 1730 printf("%s: invalid buf index %d\n", 1731 sc->sc_dev.dv_xname, buf_idx); 1732 continue; 1733 } 1734 1735 rbd = &sc->sc_rx_data[ring_idx]; 1736 rb = &rbd->rbd_buf[buf_idx]; 1737 m = rb->rb_mbuf; 1738 bus_dmamap_sync(sc->sc_dmat, rb->rb_dmap, 0, 1739 rb->rb_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1740 1741 if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) { 1742 if (buflen < ETHER_CRC_LEN) { 1743 m_freem(m); 1744 ifp->if_ierrors++; 1745 } else { 1746 m->m_pkthdr.len = m->m_len = buflen - 1747 ETHER_CRC_LEN; 1748 ml_enqueue(&ml, m); 1749 } 1750 } else { 1751 ifp->if_ierrors++; 1752 } 1753 1754 rx_ring = &sc->sc_rx_ring[ring_idx]; 1755 1756 if (buf_idx != rx_ring->rr_index) { 1757 printf("%s: WARNING!! ring %d, " 1758 "buf_idx %d, rr_idx %d\n", sc->sc_dev.dv_xname, 1759 ring_idx, buf_idx, rx_ring->rr_index); 1760 } 1761 1762 KKASSERT(rx_ring->rr_index < ET_RX_NDESC); 1763 if (++rx_ring->rr_index == ET_RX_NDESC) { 1764 rx_ring->rr_index = 0; 1765 rx_ring->rr_wrap ^= 1; 1766 } 1767 rxring_pos = __SHIFTIN(rx_ring->rr_index, ET_RX_RING_POS_INDEX); 1768 if (rx_ring->rr_wrap) 1769 rxring_pos |= ET_RX_RING_POS_WRAP; 1770 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 1771 } 1772 1773 if_input(ifp, &ml); 1774 } 1775 1776 int 1777 et_encap(struct et_softc *sc, struct mbuf **m0) 1778 { 1779 struct mbuf *m = *m0; 1780 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1781 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1782 struct et_txdesc *td; 1783 bus_dmamap_t map; 1784 int error, maxsegs, first_idx, last_idx, i; 1785 uint32_t tx_ready_pos, last_td_ctrl2; 1786 1787 maxsegs = ET_TX_NDESC - tbd->tbd_used; 1788 if (maxsegs > ET_NSEG_MAX) 1789 maxsegs = ET_NSEG_MAX; 1790 KASSERT(maxsegs >= ET_NSEG_SPARE, 1791 ("not enough spare TX desc (%d)\n", maxsegs)); 1792 1793 KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1794 first_idx = tx_ring->tr_ready_index; 1795 map = tbd->tbd_buf[first_idx].tb_dmap; 1796 1797 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1798 BUS_DMA_NOWAIT); 1799 if (!error && map->dm_nsegs == 0) { 1800 bus_dmamap_unload(sc->sc_dmat, map); 1801 error = EFBIG; 1802 } 1803 if (error && error != EFBIG) { 1804 printf("%s: can't load TX mbuf", sc->sc_dev.dv_xname); 1805 goto back; 1806 } 1807 if (error) { /* error == EFBIG */ 1808 if (m_defrag(m, M_DONTWAIT)) { 1809 printf("%s: can't defrag TX mbuf\n", 1810 sc->sc_dev.dv_xname); 1811 error = ENOBUFS; 1812 goto back; 1813 } 1814 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1815 BUS_DMA_NOWAIT); 1816 if (error || map->dm_nsegs == 0) { 1817 if (map->dm_nsegs == 0) { 1818 bus_dmamap_unload(sc->sc_dmat, map); 1819 error = EFBIG; 1820 } 1821 printf("%s: can't load defraged TX mbuf\n", 1822 sc->sc_dev.dv_xname); 1823 goto back; 1824 } 1825 } 1826 1827 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1828 BUS_DMASYNC_PREWRITE); 1829 1830 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 1831 sc->sc_tx += map->dm_nsegs; 1832 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 1833 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 1834 last_td_ctrl2 |= ET_TDCTRL2_INTR; 1835 } 1836 1837 last_idx = -1; 1838 for (i = 0; i < map->dm_nsegs; ++i) { 1839 int idx; 1840 1841 idx = (first_idx + i) % ET_TX_NDESC; 1842 td = &tx_ring->tr_desc[idx]; 1843 td->td_addr_hi = ET_ADDR_HI(map->dm_segs[i].ds_addr); 1844 td->td_addr_lo = ET_ADDR_LO(map->dm_segs[i].ds_addr); 1845 td->td_ctrl1 = 1846 __SHIFTIN(map->dm_segs[i].ds_len, ET_TDCTRL1_LEN); 1847 1848 if (i == map->dm_nsegs - 1) { /* Last frag */ 1849 td->td_ctrl2 = last_td_ctrl2; 1850 last_idx = idx; 1851 } 1852 1853 KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1854 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 1855 tx_ring->tr_ready_index = 0; 1856 tx_ring->tr_ready_wrap ^= 1; 1857 } 1858 } 1859 td = &tx_ring->tr_desc[first_idx]; 1860 td->td_ctrl2 |= ET_TDCTRL2_FIRST_FRAG; /* First frag */ 1861 1862 KKASSERT(last_idx >= 0); 1863 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 1864 tbd->tbd_buf[last_idx].tb_dmap = map; 1865 tbd->tbd_buf[last_idx].tb_mbuf = m; 1866 1867 tbd->tbd_used += map->dm_nsegs; 1868 KKASSERT(tbd->tbd_used <= ET_TX_NDESC); 1869 1870 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1871 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1872 1873 1874 tx_ready_pos = __SHIFTIN(tx_ring->tr_ready_index, 1875 ET_TX_READY_POS_INDEX); 1876 if (tx_ring->tr_ready_wrap) 1877 tx_ready_pos |= ET_TX_READY_POS_WRAP; 1878 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 1879 1880 error = 0; 1881 back: 1882 if (error) { 1883 m_freem(m); 1884 *m0 = NULL; 1885 } 1886 return error; 1887 } 1888 1889 void 1890 et_txeof(struct et_softc *sc) 1891 { 1892 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1893 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1894 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1895 uint32_t tx_done; 1896 int end, wrap; 1897 1898 if (tbd->tbd_used == 0) 1899 return; 1900 1901 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 1902 end = __SHIFTOUT(tx_done, ET_TX_DONE_POS_INDEX); 1903 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 1904 1905 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 1906 struct et_txbuf *tb; 1907 1908 KKASSERT(tbd->tbd_start_index < ET_TX_NDESC); 1909 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 1910 1911 bzero(&tx_ring->tr_desc[tbd->tbd_start_index], 1912 sizeof(struct et_txdesc)); 1913 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1914 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1915 1916 if (tb->tb_mbuf != NULL) { 1917 bus_dmamap_unload(sc->sc_dmat, tb->tb_dmap); 1918 m_freem(tb->tb_mbuf); 1919 tb->tb_mbuf = NULL; 1920 ifp->if_opackets++; 1921 } 1922 1923 if (++tbd->tbd_start_index == ET_TX_NDESC) { 1924 tbd->tbd_start_index = 0; 1925 tbd->tbd_start_wrap ^= 1; 1926 } 1927 1928 KKASSERT(tbd->tbd_used > 0); 1929 tbd->tbd_used--; 1930 } 1931 1932 if (tbd->tbd_used == 0) { 1933 timeout_del(&sc->sc_txtick); 1934 ifp->if_timer = 0; 1935 } 1936 if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC) 1937 ifp->if_flags &= ~IFF_OACTIVE; 1938 1939 et_start(ifp); 1940 } 1941 1942 void 1943 et_txtick(void *xsc) 1944 { 1945 struct et_softc *sc = xsc; 1946 int s; 1947 1948 s = splnet(); 1949 et_txeof(sc); 1950 splx(s); 1951 } 1952 1953 void 1954 et_tick(void *xsc) 1955 { 1956 struct et_softc *sc = xsc; 1957 int s; 1958 1959 s = splnet(); 1960 mii_tick(&sc->sc_miibus); 1961 timeout_add_sec(&sc->sc_tick, 1); 1962 splx(s); 1963 } 1964 1965 int 1966 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init) 1967 { 1968 return et_newbuf(rbd, buf_idx, init, MCLBYTES); 1969 } 1970 1971 int 1972 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init) 1973 { 1974 return et_newbuf(rbd, buf_idx, init, MHLEN); 1975 } 1976 1977 int 1978 et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0) 1979 { 1980 struct et_softc *sc = rbd->rbd_softc; 1981 struct et_rxdesc_ring *rx_ring; 1982 struct et_rxdesc *desc; 1983 struct et_rxbuf *rb; 1984 struct mbuf *m; 1985 bus_dmamap_t dmap; 1986 int error, len; 1987 1988 KKASSERT(buf_idx < ET_RX_NDESC); 1989 rb = &rbd->rbd_buf[buf_idx]; 1990 1991 if (len0 >= MINCLSIZE) { 1992 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 1993 if (m == NULL) 1994 return (ENOBUFS); 1995 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 1996 len = MCLBYTES; 1997 } else { 1998 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 1999 len = MHLEN; 2000 } 2001 2002 if (m == NULL) { 2003 error = ENOBUFS; 2004 2005 /* XXX for debug */ 2006 printf("%s: M_CLGET failed, size %d\n", sc->sc_dev.dv_xname, 2007 len0); 2008 if (init) { 2009 return error; 2010 } else { 2011 goto back; 2012 } 2013 } 2014 m->m_len = m->m_pkthdr.len = len; 2015 2016 /* 2017 * Try load RX mbuf into temporary DMA tag 2018 */ 2019 error = bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_mbuf_tmp_dmap, m, 2020 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT); 2021 if (error) { 2022 if (!error) { 2023 bus_dmamap_unload(sc->sc_dmat, sc->sc_mbuf_tmp_dmap); 2024 error = EFBIG; 2025 printf("%s: too many segments?!\n", 2026 sc->sc_dev.dv_xname); 2027 } 2028 m_freem(m); 2029 2030 /* XXX for debug */ 2031 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 2032 if (init) { 2033 return error; 2034 } else { 2035 goto back; 2036 } 2037 } 2038 2039 if (!init) 2040 bus_dmamap_unload(sc->sc_dmat, rb->rb_dmap); 2041 rb->rb_mbuf = m; 2042 2043 /* 2044 * Swap RX buf's DMA map with the loaded temporary one 2045 */ 2046 dmap = rb->rb_dmap; 2047 rb->rb_dmap = sc->sc_mbuf_tmp_dmap; 2048 rb->rb_paddr = rb->rb_dmap->dm_segs[0].ds_addr; 2049 sc->sc_mbuf_tmp_dmap = dmap; 2050 2051 error = 0; 2052 back: 2053 rx_ring = rbd->rbd_ring; 2054 desc = &rx_ring->rr_desc[buf_idx]; 2055 2056 desc->rd_addr_hi = ET_ADDR_HI(rb->rb_paddr); 2057 desc->rd_addr_lo = ET_ADDR_LO(rb->rb_paddr); 2058 desc->rd_ctrl = __SHIFTIN(buf_idx, ET_RDCTRL_BUFIDX); 2059 2060 bus_dmamap_sync(sc->sc_dmat, rx_ring->rr_dmap, 0, 2061 rx_ring->rr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2062 return error; 2063 } 2064