1 /* $OpenBSD: if_et.c,v 1.39 2020/07/10 13:26:38 patrick Exp $ */ 2 /* 3 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 4 * 5 * This code is derived from software contributed to The DragonFly Project 6 * by Sepherosa Ziehau <sepherosa@gmail.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.1 2007/10/12 14:12:42 sephe Exp $ 36 */ 37 38 #include "bpfilter.h" 39 40 #include <sys/param.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/queue.h> 46 #include <sys/kernel.h> 47 #include <sys/device.h> 48 #include <sys/timeout.h> 49 #include <sys/socket.h> 50 51 #include <machine/bus.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 57 #include <netinet/in.h> 58 #include <netinet/if_ether.h> 59 60 #if NBPFILTER > 0 61 #include <net/bpf.h> 62 #endif 63 64 #include <dev/mii/miivar.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #include <dev/pci/if_etreg.h> 71 72 /* XXX temporary porting goop */ 73 #define KKASSERT(cond) if (!(cond)) panic("KKASSERT: %s in %s", #cond, __func__) 74 #undef KASSERT 75 #define KASSERT(cond, complaint) if (!(cond)) panic complaint 76 77 /* these macros in particular need to die, so gross */ 78 #define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) 79 #define __SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask)) 80 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) 81 /* XXX end porting goop */ 82 83 int et_match(struct device *, void *, void *); 84 void et_attach(struct device *, struct device *, void *); 85 int et_detach(struct device *, int); 86 87 int et_miibus_readreg(struct device *, int, int); 88 void et_miibus_writereg(struct device *, int, int, int); 89 void et_miibus_statchg(struct device *); 90 91 int et_init(struct ifnet *); 92 int et_ioctl(struct ifnet *, u_long, caddr_t); 93 void et_start(struct ifnet *); 94 void et_watchdog(struct ifnet *); 95 int et_ifmedia_upd(struct ifnet *); 96 void et_ifmedia_sts(struct ifnet *, struct ifmediareq *); 97 98 int et_intr(void *); 99 void et_enable_intrs(struct et_softc *, uint32_t); 100 void et_disable_intrs(struct et_softc *); 101 void et_rxeof(struct et_softc *); 102 void et_txeof(struct et_softc *); 103 void et_txtick(void *); 104 105 int et_dma_alloc(struct et_softc *); 106 void et_dma_free(struct et_softc *); 107 int et_dma_mem_create(struct et_softc *, bus_size_t, 108 void **, bus_addr_t *, bus_dmamap_t *, bus_dma_segment_t *); 109 void et_dma_mem_destroy(struct et_softc *, void *, bus_dmamap_t); 110 int et_dma_mbuf_create(struct et_softc *); 111 void et_dma_mbuf_destroy(struct et_softc *, int, const int[]); 112 113 int et_init_tx_ring(struct et_softc *); 114 int et_init_rx_ring(struct et_softc *); 115 void et_free_tx_ring(struct et_softc *); 116 void et_free_rx_ring(struct et_softc *); 117 int et_encap(struct et_softc *, struct mbuf **); 118 int et_newbuf(struct et_rxbuf_data *, int, int, int); 119 int et_newbuf_cluster(struct et_rxbuf_data *, int, int); 120 int et_newbuf_hdr(struct et_rxbuf_data *, int, int); 121 122 void et_stop(struct et_softc *); 123 int et_chip_init(struct et_softc *); 124 void et_chip_attach(struct et_softc *); 125 void et_init_mac(struct et_softc *); 126 void et_init_rxmac(struct et_softc *); 127 void et_init_txmac(struct et_softc *); 128 int et_init_rxdma(struct et_softc *); 129 int et_init_txdma(struct et_softc *); 130 int et_start_rxdma(struct et_softc *); 131 int et_start_txdma(struct et_softc *); 132 int et_stop_rxdma(struct et_softc *); 133 int et_stop_txdma(struct et_softc *); 134 int et_enable_txrx(struct et_softc *); 135 void et_reset(struct et_softc *); 136 int et_bus_config(struct et_softc *); 137 void et_get_eaddr(struct et_softc *, uint8_t[]); 138 void et_setmulti(struct et_softc *); 139 void et_tick(void *); 140 141 static int et_rx_intr_npkts = 32; 142 static int et_rx_intr_delay = 20; /* x10 usec */ 143 static int et_tx_intr_nsegs = 128; 144 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 145 146 struct et_bsize { 147 int bufsize; 148 et_newbuf_t newbuf; 149 }; 150 151 static const struct et_bsize et_bufsize[ET_RX_NRING] = { 152 { .bufsize = 0, .newbuf = et_newbuf_hdr }, 153 { .bufsize = 0, .newbuf = et_newbuf_cluster }, 154 }; 155 156 const struct pci_matchid et_devices[] = { 157 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FE }, 158 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_GBE } 159 }; 160 161 struct cfattach et_ca = { 162 sizeof (struct et_softc), et_match, et_attach, et_detach 163 }; 164 165 struct cfdriver et_cd = { 166 NULL, "et", DV_IFNET 167 }; 168 169 int 170 et_match(struct device *dev, void *match, void *aux) 171 { 172 return pci_matchbyid((struct pci_attach_args *)aux, et_devices, 173 sizeof (et_devices) / sizeof (et_devices[0])); 174 } 175 176 void 177 et_attach(struct device *parent, struct device *self, void *aux) 178 { 179 struct et_softc *sc = (struct et_softc *)self; 180 struct pci_attach_args *pa = aux; 181 pci_chipset_tag_t pc = pa->pa_pc; 182 pci_intr_handle_t ih; 183 const char *intrstr; 184 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 185 pcireg_t memtype; 186 int error; 187 188 /* 189 * Initialize tunables 190 */ 191 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 192 sc->sc_rx_intr_delay = et_rx_intr_delay; 193 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 194 sc->sc_timer = et_timer; 195 196 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ET_PCIR_BAR); 197 if (pci_mapreg_map(pa, ET_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 198 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 199 printf(": can't map mem space\n"); 200 return; 201 } 202 203 if (pci_intr_map(pa, &ih) != 0) { 204 printf(": can't map interrupt\n"); 205 return; 206 } 207 208 intrstr = pci_intr_string(pc, ih); 209 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, et_intr, sc, 210 sc->sc_dev.dv_xname); 211 if (sc->sc_irq_handle == NULL) { 212 printf(": could not establish interrupt"); 213 if (intrstr != NULL) 214 printf(" at %s", intrstr); 215 printf("\n"); 216 return; 217 } 218 printf(": %s", intrstr); 219 220 sc->sc_dmat = pa->pa_dmat; 221 sc->sc_pct = pa->pa_pc; 222 sc->sc_pcitag = pa->pa_tag; 223 224 error = et_bus_config(sc); 225 if (error) 226 return; 227 228 et_get_eaddr(sc, sc->sc_arpcom.ac_enaddr); 229 230 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 231 232 CSR_WRITE_4(sc, ET_PM, 233 ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE); 234 235 et_reset(sc); 236 237 et_disable_intrs(sc); 238 239 error = et_dma_alloc(sc); 240 if (error) 241 return; 242 243 ifp->if_softc = sc; 244 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 245 ifp->if_ioctl = et_ioctl; 246 ifp->if_start = et_start; 247 ifp->if_watchdog = et_watchdog; 248 ifq_set_maxlen(&ifp->if_snd, ET_TX_NDESC); 249 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 250 251 ifp->if_capabilities = IFCAP_VLAN_MTU; 252 253 et_chip_attach(sc); 254 255 sc->sc_miibus.mii_ifp = ifp; 256 sc->sc_miibus.mii_readreg = et_miibus_readreg; 257 sc->sc_miibus.mii_writereg = et_miibus_writereg; 258 sc->sc_miibus.mii_statchg = et_miibus_statchg; 259 260 ifmedia_init(&sc->sc_miibus.mii_media, 0, et_ifmedia_upd, 261 et_ifmedia_sts); 262 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 263 MII_OFFSET_ANY, 0); 264 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 265 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 266 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 267 0, NULL); 268 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 269 } else 270 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 271 272 if_attach(ifp); 273 ether_ifattach(ifp); 274 275 timeout_set(&sc->sc_tick, et_tick, sc); 276 timeout_set(&sc->sc_txtick, et_txtick, sc); 277 } 278 279 int 280 et_detach(struct device *self, int flags) 281 { 282 struct et_softc *sc = (struct et_softc *)self; 283 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 284 int s; 285 286 s = splnet(); 287 et_stop(sc); 288 splx(s); 289 290 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 291 292 /* Delete all remaining media. */ 293 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 294 295 ether_ifdetach(ifp); 296 if_detach(ifp); 297 et_dma_free(sc); 298 299 if (sc->sc_irq_handle != NULL) { 300 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 301 sc->sc_irq_handle = NULL; 302 } 303 304 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 305 306 return 0; 307 } 308 309 int 310 et_miibus_readreg(struct device *dev, int phy, int reg) 311 { 312 struct et_softc *sc = (struct et_softc *)dev; 313 uint32_t val; 314 int i, ret; 315 316 /* Stop any pending operations */ 317 CSR_WRITE_4(sc, ET_MII_CMD, 0); 318 319 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 320 __SHIFTIN(reg, ET_MII_ADDR_REG); 321 CSR_WRITE_4(sc, ET_MII_ADDR, val); 322 323 /* Start reading */ 324 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 325 326 #define NRETRY 50 327 328 for (i = 0; i < NRETRY; ++i) { 329 val = CSR_READ_4(sc, ET_MII_IND); 330 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 331 break; 332 DELAY(50); 333 } 334 if (i == NRETRY) { 335 printf("%s: read phy %d, reg %d timed out\n", 336 sc->sc_dev.dv_xname, phy, reg); 337 ret = 0; 338 goto back; 339 } 340 341 #undef NRETRY 342 343 val = CSR_READ_4(sc, ET_MII_STAT); 344 ret = __SHIFTOUT(val, ET_MII_STAT_VALUE); 345 346 back: 347 /* Make sure that the current operation is stopped */ 348 CSR_WRITE_4(sc, ET_MII_CMD, 0); 349 return ret; 350 } 351 352 void 353 et_miibus_writereg(struct device *dev, int phy, int reg, int val0) 354 { 355 struct et_softc *sc = (struct et_softc *)dev; 356 uint32_t val; 357 int i; 358 359 /* Stop any pending operations */ 360 CSR_WRITE_4(sc, ET_MII_CMD, 0); 361 362 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 363 __SHIFTIN(reg, ET_MII_ADDR_REG); 364 CSR_WRITE_4(sc, ET_MII_ADDR, val); 365 366 /* Start writing */ 367 CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val0, ET_MII_CTRL_VALUE)); 368 369 #define NRETRY 100 370 371 for (i = 0; i < NRETRY; ++i) { 372 val = CSR_READ_4(sc, ET_MII_IND); 373 if ((val & ET_MII_IND_BUSY) == 0) 374 break; 375 DELAY(50); 376 } 377 if (i == NRETRY) { 378 printf("%s: write phy %d, reg %d timed out\n", 379 sc->sc_dev.dv_xname, phy, reg); 380 et_miibus_readreg(dev, phy, reg); 381 } 382 383 #undef NRETRY 384 385 /* Make sure that the current operation is stopped */ 386 CSR_WRITE_4(sc, ET_MII_CMD, 0); 387 } 388 389 void 390 et_miibus_statchg(struct device *dev) 391 { 392 struct et_softc *sc = (struct et_softc *)dev; 393 struct mii_data *mii = &sc->sc_miibus; 394 uint32_t cfg2, ctrl; 395 396 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 397 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 398 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 399 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 400 __SHIFTIN(7, ET_MAC_CFG2_PREAMBLE_LEN); 401 402 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 403 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 404 405 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 406 cfg2 |= ET_MAC_CFG2_MODE_GMII; 407 } else { 408 cfg2 |= ET_MAC_CFG2_MODE_MII; 409 ctrl |= ET_MAC_CTRL_MODE_MII; 410 } 411 412 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 413 cfg2 |= ET_MAC_CFG2_FDX; 414 else 415 ctrl |= ET_MAC_CTRL_GHDX; 416 417 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 418 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 419 } 420 421 int 422 et_ifmedia_upd(struct ifnet *ifp) 423 { 424 struct et_softc *sc = ifp->if_softc; 425 struct mii_data *mii = &sc->sc_miibus; 426 427 if (mii->mii_instance != 0) { 428 struct mii_softc *miisc; 429 430 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 431 mii_phy_reset(miisc); 432 } 433 mii_mediachg(mii); 434 435 return 0; 436 } 437 438 void 439 et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 440 { 441 struct et_softc *sc = ifp->if_softc; 442 struct mii_data *mii = &sc->sc_miibus; 443 444 mii_pollstat(mii); 445 ifmr->ifm_active = mii->mii_media_active; 446 ifmr->ifm_status = mii->mii_media_status; 447 } 448 449 void 450 et_stop(struct et_softc *sc) 451 { 452 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 453 454 timeout_del(&sc->sc_tick); 455 timeout_del(&sc->sc_txtick); 456 457 et_stop_rxdma(sc); 458 et_stop_txdma(sc); 459 460 et_disable_intrs(sc); 461 462 et_free_tx_ring(sc); 463 et_free_rx_ring(sc); 464 465 et_reset(sc); 466 467 sc->sc_tx = 0; 468 sc->sc_tx_intr = 0; 469 470 ifp->if_timer = 0; 471 ifp->if_flags &= ~IFF_RUNNING; 472 ifq_clr_oactive(&ifp->if_snd); 473 } 474 475 int 476 et_bus_config(struct et_softc *sc) 477 { 478 uint32_t val; //, max_plsz; 479 // uint16_t ack_latency, replay_timer; 480 481 /* 482 * Test whether EEPROM is valid 483 * NOTE: Read twice to get the correct value 484 */ 485 pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_EEPROM_MISC); 486 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_EEPROM_MISC); 487 488 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 489 printf("%s: EEPROM status error 0x%02x\n", 490 sc->sc_dev.dv_xname, val); 491 return ENXIO; 492 } 493 494 /* TODO: LED */ 495 #if 0 496 /* 497 * Configure ACK latency and replay timer according to 498 * max playload size 499 */ 500 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_DEVICE_CAPS); 501 max_plsz = val & ET_PCIM_DEVICE_CAPS_MAX_PLSZ; 502 503 switch (max_plsz) { 504 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 505 ack_latency = ET_PCIV_ACK_LATENCY_128; 506 replay_timer = ET_PCIV_REPLAY_TIMER_128; 507 break; 508 509 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 510 ack_latency = ET_PCIV_ACK_LATENCY_256; 511 replay_timer = ET_PCIV_REPLAY_TIMER_256; 512 break; 513 514 default: 515 ack_latency = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 516 ET_PCIR_ACK_LATENCY) >> 16; 517 replay_timer = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 518 ET_PCIR_REPLAY_TIMER) >> 16; 519 printf("%s: ack latency %u, replay timer %u\n", 520 sc->sc_dev.dv_xname, ack_latency, replay_timer); 521 break; 522 } 523 if (ack_latency != 0) { 524 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 525 ET_PCIR_ACK_LATENCY, ack_latency << 16); 526 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 527 ET_PCIR_REPLAY_TIMER, replay_timer << 16); 528 } 529 530 /* 531 * Set L0s and L1 latency timer to 2us 532 */ 533 val = ET_PCIV_L0S_LATENCY(2) | ET_PCIV_L1_LATENCY(2); 534 pci_conf_write(sc->sc_pct, sc->sc_pcitag, ET_PCIR_L0S_L1_LATENCY, 535 val << 24); 536 537 /* 538 * Set max read request size to 2048 bytes 539 */ 540 val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 541 ET_PCIR_DEVICE_CTRL) >> 16; 542 val &= ~ET_PCIM_DEVICE_CTRL_MAX_RRSZ; 543 val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K; 544 pci_conf_write(sc->sc_pct, sc->sc_pcitag, ET_PCIR_DEVICE_CTRL, 545 val << 16); 546 #endif 547 548 return 0; 549 } 550 551 void 552 et_get_eaddr(struct et_softc *sc, uint8_t eaddr[]) 553 { 554 uint32_t r; 555 556 r = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_MACADDR_LO); 557 eaddr[0] = r & 0xff; 558 eaddr[1] = (r >> 8) & 0xff; 559 eaddr[2] = (r >> 16) & 0xff; 560 eaddr[3] = (r >> 24) & 0xff; 561 r = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_MACADDR_HI); 562 eaddr[4] = r & 0xff; 563 eaddr[5] = (r >> 8) & 0xff; 564 } 565 566 void 567 et_reset(struct et_softc *sc) 568 { 569 CSR_WRITE_4(sc, ET_MAC_CFG1, 570 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 571 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 572 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 573 574 CSR_WRITE_4(sc, ET_SWRST, 575 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 576 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 577 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 578 579 CSR_WRITE_4(sc, ET_MAC_CFG1, 580 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 581 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 582 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 583 } 584 585 void 586 et_disable_intrs(struct et_softc *sc) 587 { 588 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 589 } 590 591 void 592 et_enable_intrs(struct et_softc *sc, uint32_t intrs) 593 { 594 CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs); 595 } 596 597 int 598 et_dma_alloc(struct et_softc *sc) 599 { 600 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 601 struct et_txstatus_data *txsd = &sc->sc_tx_status; 602 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 603 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 604 int i, error; 605 606 /* 607 * Create TX ring DMA stuffs 608 */ 609 error = et_dma_mem_create(sc, ET_TX_RING_SIZE, 610 (void **)&tx_ring->tr_desc, &tx_ring->tr_paddr, &tx_ring->tr_dmap, 611 &tx_ring->tr_seg); 612 if (error) { 613 printf("%s: can't create TX ring DMA stuffs\n", 614 sc->sc_dev.dv_xname); 615 return error; 616 } 617 618 /* 619 * Create TX status DMA stuffs 620 */ 621 error = et_dma_mem_create(sc, sizeof(uint32_t), 622 (void **)&txsd->txsd_status, 623 &txsd->txsd_paddr, &txsd->txsd_dmap, &txsd->txsd_seg); 624 if (error) { 625 printf("%s: can't create TX status DMA stuffs\n", 626 sc->sc_dev.dv_xname); 627 return error; 628 } 629 630 /* 631 * Create DMA stuffs for RX rings 632 */ 633 for (i = 0; i < ET_RX_NRING; ++i) { 634 static const uint32_t rx_ring_posreg[ET_RX_NRING] = 635 { ET_RX_RING0_POS, ET_RX_RING1_POS }; 636 637 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 638 639 error = et_dma_mem_create(sc, ET_RX_RING_SIZE, 640 (void **)&rx_ring->rr_desc, 641 &rx_ring->rr_paddr, &rx_ring->rr_dmap, &rx_ring->rr_seg); 642 if (error) { 643 printf("%s: can't create DMA stuffs for " 644 "the %d RX ring\n", sc->sc_dev.dv_xname, i); 645 return error; 646 } 647 rx_ring->rr_posreg = rx_ring_posreg[i]; 648 } 649 650 /* 651 * Create RX stat ring DMA stuffs 652 */ 653 error = et_dma_mem_create(sc, ET_RXSTAT_RING_SIZE, 654 (void **)&rxst_ring->rsr_stat, 655 &rxst_ring->rsr_paddr, &rxst_ring->rsr_dmap, &rxst_ring->rsr_seg); 656 if (error) { 657 printf("%s: can't create RX stat ring DMA stuffs\n", 658 sc->sc_dev.dv_xname); 659 return error; 660 } 661 662 /* 663 * Create RX status DMA stuffs 664 */ 665 error = et_dma_mem_create(sc, sizeof(struct et_rxstatus), 666 (void **)&rxsd->rxsd_status, 667 &rxsd->rxsd_paddr, &rxsd->rxsd_dmap, &rxsd->rxsd_seg); 668 if (error) { 669 printf("%s: can't create RX status DMA stuffs\n", 670 sc->sc_dev.dv_xname); 671 return error; 672 } 673 674 /* 675 * Create mbuf DMA stuffs 676 */ 677 error = et_dma_mbuf_create(sc); 678 if (error) 679 return error; 680 681 return 0; 682 } 683 684 void 685 et_dma_free(struct et_softc *sc) 686 { 687 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 688 struct et_txstatus_data *txsd = &sc->sc_tx_status; 689 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 690 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 691 int i, rx_done[ET_RX_NRING]; 692 693 /* 694 * Destroy TX ring DMA stuffs 695 */ 696 et_dma_mem_destroy(sc, tx_ring->tr_desc, tx_ring->tr_dmap); 697 698 /* 699 * Destroy TX status DMA stuffs 700 */ 701 et_dma_mem_destroy(sc, txsd->txsd_status, txsd->txsd_dmap); 702 703 /* 704 * Destroy DMA stuffs for RX rings 705 */ 706 for (i = 0; i < ET_RX_NRING; ++i) { 707 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 708 709 et_dma_mem_destroy(sc, rx_ring->rr_desc, rx_ring->rr_dmap); 710 } 711 712 /* 713 * Destroy RX stat ring DMA stuffs 714 */ 715 et_dma_mem_destroy(sc, rxst_ring->rsr_stat, rxst_ring->rsr_dmap); 716 717 /* 718 * Destroy RX status DMA stuffs 719 */ 720 et_dma_mem_destroy(sc, rxsd->rxsd_status, rxsd->rxsd_dmap); 721 722 /* 723 * Destroy mbuf DMA stuffs 724 */ 725 for (i = 0; i < ET_RX_NRING; ++i) 726 rx_done[i] = ET_RX_NDESC; 727 et_dma_mbuf_destroy(sc, ET_TX_NDESC, rx_done); 728 } 729 730 int 731 et_dma_mbuf_create(struct et_softc *sc) 732 { 733 struct et_txbuf_data *tbd = &sc->sc_tx_data; 734 int i, error, rx_done[ET_RX_NRING]; 735 736 /* 737 * Create spare DMA map for RX mbufs 738 */ 739 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 740 BUS_DMA_NOWAIT, &sc->sc_mbuf_tmp_dmap); 741 if (error) { 742 printf("%s: can't create spare mbuf DMA map\n", 743 sc->sc_dev.dv_xname); 744 return error; 745 } 746 747 /* 748 * Create DMA maps for RX mbufs 749 */ 750 bzero(rx_done, sizeof(rx_done)); 751 for (i = 0; i < ET_RX_NRING; ++i) { 752 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 753 int j; 754 755 for (j = 0; j < ET_RX_NDESC; ++j) { 756 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 757 MCLBYTES, 0, BUS_DMA_NOWAIT, 758 &rbd->rbd_buf[j].rb_dmap); 759 if (error) { 760 printf("%s: can't create %d RX mbuf " 761 "for %d RX ring\n", sc->sc_dev.dv_xname, 762 j, i); 763 rx_done[i] = j; 764 et_dma_mbuf_destroy(sc, 0, rx_done); 765 return error; 766 } 767 } 768 rx_done[i] = ET_RX_NDESC; 769 770 rbd->rbd_softc = sc; 771 rbd->rbd_ring = &sc->sc_rx_ring[i]; 772 } 773 774 /* 775 * Create DMA maps for TX mbufs 776 */ 777 for (i = 0; i < ET_TX_NDESC; ++i) { 778 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 779 0, BUS_DMA_NOWAIT, &tbd->tbd_buf[i].tb_dmap); 780 if (error) { 781 printf("%s: can't create %d TX mbuf " 782 "DMA map\n", sc->sc_dev.dv_xname, i); 783 et_dma_mbuf_destroy(sc, i, rx_done); 784 return error; 785 } 786 } 787 788 return 0; 789 } 790 791 void 792 et_dma_mbuf_destroy(struct et_softc *sc, int tx_done, const int rx_done[]) 793 { 794 struct et_txbuf_data *tbd = &sc->sc_tx_data; 795 int i; 796 797 /* 798 * Destroy DMA maps for RX mbufs 799 */ 800 for (i = 0; i < ET_RX_NRING; ++i) { 801 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 802 int j; 803 804 for (j = 0; j < rx_done[i]; ++j) { 805 struct et_rxbuf *rb = &rbd->rbd_buf[j]; 806 807 KASSERT(rb->rb_mbuf == NULL, 808 ("RX mbuf in %d RX ring is not freed yet\n", i)); 809 bus_dmamap_destroy(sc->sc_dmat, rb->rb_dmap); 810 } 811 } 812 813 /* 814 * Destroy DMA maps for TX mbufs 815 */ 816 for (i = 0; i < tx_done; ++i) { 817 struct et_txbuf *tb = &tbd->tbd_buf[i]; 818 819 KASSERT(tb->tb_mbuf == NULL, ("TX mbuf is not freed yet\n")); 820 bus_dmamap_destroy(sc->sc_dmat, tb->tb_dmap); 821 } 822 823 /* 824 * Destroy spare mbuf DMA map 825 */ 826 bus_dmamap_destroy(sc->sc_dmat, sc->sc_mbuf_tmp_dmap); 827 } 828 829 int 830 et_dma_mem_create(struct et_softc *sc, bus_size_t size, 831 void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap, bus_dma_segment_t *seg) 832 { 833 int error, nsegs; 834 835 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 836 dmap); 837 if (error) { 838 printf("%s: can't create DMA map\n", sc->sc_dev.dv_xname); 839 return error; 840 } 841 842 error = bus_dmamem_alloc(sc->sc_dmat, size, ET_ALIGN, 0, seg, 843 1, &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 844 if (error) { 845 printf("%s: can't allocate DMA mem\n", sc->sc_dev.dv_xname); 846 return error; 847 } 848 849 error = bus_dmamem_map(sc->sc_dmat, seg, nsegs, 850 size, (caddr_t *)addr, BUS_DMA_NOWAIT); 851 if (error) { 852 printf("%s: can't map DMA mem\n", sc->sc_dev.dv_xname); 853 return (error); 854 } 855 856 error = bus_dmamap_load(sc->sc_dmat, *dmap, *addr, size, NULL, 857 BUS_DMA_WAITOK); 858 if (error) { 859 printf("%s: can't load DMA mem\n", sc->sc_dev.dv_xname); 860 bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)addr, 1); 861 return error; 862 } 863 864 *paddr = (*dmap)->dm_segs[0].ds_addr; 865 866 return 0; 867 } 868 869 void 870 et_dma_mem_destroy(struct et_softc *sc, void *addr, bus_dmamap_t dmap) 871 { 872 bus_dmamap_unload(sc->sc_dmat, dmap); 873 bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)&addr, 1); 874 } 875 876 void 877 et_chip_attach(struct et_softc *sc) 878 { 879 uint32_t val; 880 881 /* 882 * Perform minimal initialization 883 */ 884 885 /* Disable loopback */ 886 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 887 888 /* Reset MAC */ 889 CSR_WRITE_4(sc, ET_MAC_CFG1, 890 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 891 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 892 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 893 894 /* 895 * Setup half duplex mode 896 */ 897 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 898 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 899 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 900 ET_MAC_HDX_EXC_DEFER; 901 CSR_WRITE_4(sc, ET_MAC_HDX, val); 902 903 /* Clear MAC control */ 904 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 905 906 /* Reset MII */ 907 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 908 909 /* Bring MAC out of reset state */ 910 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 911 912 /* Enable memory controllers */ 913 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 914 } 915 916 int 917 et_intr(void *xsc) 918 { 919 struct et_softc *sc = xsc; 920 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 921 uint32_t intrs; 922 923 if ((ifp->if_flags & IFF_RUNNING) == 0) 924 return (0); 925 926 intrs = CSR_READ_4(sc, ET_INTR_STATUS); 927 if (intrs == 0 || intrs == 0xffffffff) 928 return (0); 929 930 et_disable_intrs(sc); 931 intrs &= ET_INTRS; 932 if (intrs == 0) /* Not interested */ 933 goto back; 934 935 if (intrs & ET_INTR_RXEOF) 936 et_rxeof(sc); 937 if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER)) 938 et_txeof(sc); 939 if (intrs & ET_INTR_TIMER) 940 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 941 back: 942 et_enable_intrs(sc, ET_INTRS); 943 944 return (1); 945 } 946 947 int 948 et_init(struct ifnet *ifp) 949 { 950 struct et_softc *sc = ifp->if_softc; 951 int error, i, s; 952 953 s = splnet(); 954 955 et_stop(sc); 956 957 for (i = 0; i < ET_RX_NRING; ++i) { 958 sc->sc_rx_data[i].rbd_bufsize = et_bufsize[i].bufsize; 959 sc->sc_rx_data[i].rbd_newbuf = et_bufsize[i].newbuf; 960 } 961 962 error = et_init_tx_ring(sc); 963 if (error) 964 goto back; 965 966 error = et_init_rx_ring(sc); 967 if (error) 968 goto back; 969 970 error = et_chip_init(sc); 971 if (error) 972 goto back; 973 974 error = et_enable_txrx(sc); 975 if (error) 976 goto back; 977 978 error = et_start_rxdma(sc); 979 if (error) 980 goto back; 981 982 error = et_start_txdma(sc); 983 if (error) 984 goto back; 985 986 et_enable_intrs(sc, ET_INTRS); 987 988 timeout_add_sec(&sc->sc_tick, 1); 989 990 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 991 992 ifp->if_flags |= IFF_RUNNING; 993 ifq_clr_oactive(&ifp->if_snd); 994 back: 995 if (error) 996 et_stop(sc); 997 998 splx(s); 999 1000 return (0); 1001 } 1002 1003 int 1004 et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1005 { 1006 struct et_softc *sc = ifp->if_softc; 1007 struct ifreq *ifr = (struct ifreq *)data; 1008 int s, error = 0; 1009 1010 s = splnet(); 1011 1012 switch (cmd) { 1013 case SIOCSIFADDR: 1014 ifp->if_flags |= IFF_UP; 1015 if (!(ifp->if_flags & IFF_RUNNING)) 1016 et_init(ifp); 1017 break; 1018 1019 case SIOCSIFFLAGS: 1020 if (ifp->if_flags & IFF_UP) { 1021 /* 1022 * If only the PROMISC or ALLMULTI flag changes, then 1023 * don't do a full re-init of the chip, just update 1024 * the Rx filter. 1025 */ 1026 if ((ifp->if_flags & IFF_RUNNING) && 1027 ((ifp->if_flags ^ sc->sc_if_flags) & 1028 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1029 et_setmulti(sc); 1030 } else { 1031 if (!(ifp->if_flags & IFF_RUNNING)) 1032 et_init(ifp); 1033 } 1034 } else { 1035 if (ifp->if_flags & IFF_RUNNING) 1036 et_stop(sc); 1037 } 1038 sc->sc_if_flags = ifp->if_flags; 1039 break; 1040 1041 case SIOCSIFMEDIA: 1042 case SIOCGIFMEDIA: 1043 error = ifmedia_ioctl(ifp, ifr, &sc->sc_miibus.mii_media, cmd); 1044 break; 1045 1046 default: 1047 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1048 } 1049 1050 if (error == ENETRESET) { 1051 if (ifp->if_flags & IFF_RUNNING) 1052 et_setmulti(sc); 1053 error = 0; 1054 } 1055 1056 splx(s); 1057 return error; 1058 } 1059 1060 void 1061 et_start(struct ifnet *ifp) 1062 { 1063 struct et_softc *sc = ifp->if_softc; 1064 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1065 int trans; 1066 struct mbuf *m; 1067 1068 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1069 return; 1070 1071 trans = 0; 1072 for (;;) { 1073 m = ifq_dequeue(&ifp->if_snd); 1074 if (m == NULL) 1075 break; 1076 1077 if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) { 1078 ifq_set_oactive(&ifp->if_snd); 1079 break; 1080 } 1081 1082 if (et_encap(sc, &m)) { 1083 ifp->if_oerrors++; 1084 ifq_set_oactive(&ifp->if_snd); 1085 break; 1086 } 1087 1088 trans = 1; 1089 1090 #if NBPFILTER > 0 1091 if (ifp->if_bpf != NULL) 1092 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1093 #endif 1094 } 1095 1096 if (trans) { 1097 timeout_add_sec(&sc->sc_txtick, 1); 1098 ifp->if_timer = 5; 1099 } 1100 } 1101 1102 void 1103 et_watchdog(struct ifnet *ifp) 1104 { 1105 struct et_softc *sc = ifp->if_softc; 1106 printf("%s: watchdog timed out\n", sc->sc_dev.dv_xname); 1107 1108 et_init(ifp); 1109 et_start(ifp); 1110 } 1111 1112 int 1113 et_stop_rxdma(struct et_softc *sc) 1114 { 1115 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1116 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1117 1118 DELAY(5); 1119 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1120 printf("%s: can't stop RX DMA engine\n", sc->sc_dev.dv_xname); 1121 return ETIMEDOUT; 1122 } 1123 return 0; 1124 } 1125 1126 int 1127 et_stop_txdma(struct et_softc *sc) 1128 { 1129 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1130 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1131 return 0; 1132 } 1133 1134 void 1135 et_free_tx_ring(struct et_softc *sc) 1136 { 1137 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1138 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1139 int i; 1140 1141 for (i = 0; i < ET_TX_NDESC; ++i) { 1142 struct et_txbuf *tb = &tbd->tbd_buf[i]; 1143 1144 if (tb->tb_mbuf != NULL) { 1145 bus_dmamap_unload(sc->sc_dmat, tb->tb_dmap); 1146 m_freem(tb->tb_mbuf); 1147 tb->tb_mbuf = NULL; 1148 } 1149 } 1150 1151 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1152 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1153 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1154 } 1155 1156 void 1157 et_free_rx_ring(struct et_softc *sc) 1158 { 1159 int n; 1160 1161 for (n = 0; n < ET_RX_NRING; ++n) { 1162 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1163 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n]; 1164 int i; 1165 1166 for (i = 0; i < ET_RX_NDESC; ++i) { 1167 struct et_rxbuf *rb = &rbd->rbd_buf[i]; 1168 1169 if (rb->rb_mbuf != NULL) { 1170 bus_dmamap_unload(sc->sc_dmat, rb->rb_dmap); 1171 m_freem(rb->rb_mbuf); 1172 rb->rb_mbuf = NULL; 1173 } 1174 } 1175 1176 bzero(rx_ring->rr_desc, ET_RX_RING_SIZE); 1177 bus_dmamap_sync(sc->sc_dmat, rx_ring->rr_dmap, 0, 1178 rx_ring->rr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1179 } 1180 } 1181 1182 void 1183 et_setmulti(struct et_softc *sc) 1184 { 1185 struct arpcom *ac = &sc->sc_arpcom; 1186 struct ifnet *ifp = &ac->ac_if; 1187 uint32_t hash[4] = { 0, 0, 0, 0 }; 1188 uint32_t rxmac_ctrl, pktfilt; 1189 struct ether_multi *enm; 1190 struct ether_multistep step; 1191 uint8_t addr[ETHER_ADDR_LEN]; 1192 int i, count; 1193 1194 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1195 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1196 1197 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1198 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1199 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1200 goto back; 1201 } 1202 1203 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 1204 1205 count = 0; 1206 ETHER_FIRST_MULTI(step, ac, enm); 1207 while (enm != NULL) { 1208 uint32_t *hp, h; 1209 1210 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1211 addr[i] &= enm->enm_addrlo[i]; 1212 } 1213 1214 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)addr), 1215 ETHER_ADDR_LEN); 1216 h = (h & 0x3f800000) >> 23; 1217 1218 hp = &hash[0]; 1219 if (h >= 32 && h < 64) { 1220 h -= 32; 1221 hp = &hash[1]; 1222 } else if (h >= 64 && h < 96) { 1223 h -= 64; 1224 hp = &hash[2]; 1225 } else if (h >= 96) { 1226 h -= 96; 1227 hp = &hash[3]; 1228 } 1229 *hp |= (1 << h); 1230 1231 ++count; 1232 ETHER_NEXT_MULTI(step, enm); 1233 } 1234 1235 for (i = 0; i < 4; ++i) 1236 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1237 1238 if (count > 0) 1239 pktfilt |= ET_PKTFILT_MCAST; 1240 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1241 back: 1242 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1243 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1244 } 1245 1246 int 1247 et_chip_init(struct et_softc *sc) 1248 { 1249 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1250 uint32_t rxq_end; 1251 int error; 1252 1253 /* 1254 * Split internal memory between TX and RX according to MTU 1255 */ 1256 if (ifp->if_hardmtu < 2048) 1257 rxq_end = 0x2bc; 1258 else if (ifp->if_hardmtu < 8192) 1259 rxq_end = 0x1ff; 1260 else 1261 rxq_end = 0x1b3; 1262 CSR_WRITE_4(sc, ET_RXQ_START, 0); 1263 CSR_WRITE_4(sc, ET_RXQ_END, rxq_end); 1264 CSR_WRITE_4(sc, ET_TXQ_START, rxq_end + 1); 1265 CSR_WRITE_4(sc, ET_TXQ_END, ET_INTERN_MEM_END); 1266 1267 /* No loopback */ 1268 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1269 1270 /* Clear MSI configure */ 1271 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1272 1273 /* Disable timer */ 1274 CSR_WRITE_4(sc, ET_TIMER, 0); 1275 1276 /* Initialize MAC */ 1277 et_init_mac(sc); 1278 1279 /* Enable memory controllers */ 1280 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1281 1282 /* Initialize RX MAC */ 1283 et_init_rxmac(sc); 1284 1285 /* Initialize TX MAC */ 1286 et_init_txmac(sc); 1287 1288 /* Initialize RX DMA engine */ 1289 error = et_init_rxdma(sc); 1290 if (error) 1291 return error; 1292 1293 /* Initialize TX DMA engine */ 1294 error = et_init_txdma(sc); 1295 if (error) 1296 return error; 1297 1298 return 0; 1299 } 1300 1301 int 1302 et_init_tx_ring(struct et_softc *sc) 1303 { 1304 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1305 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1306 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1307 1308 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1309 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1310 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1311 1312 tbd->tbd_start_index = 0; 1313 tbd->tbd_start_wrap = 0; 1314 tbd->tbd_used = 0; 1315 1316 bzero(txsd->txsd_status, sizeof(uint32_t)); 1317 bus_dmamap_sync(sc->sc_dmat, txsd->txsd_dmap, 0, 1318 txsd->txsd_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1319 return 0; 1320 } 1321 1322 int 1323 et_init_rx_ring(struct et_softc *sc) 1324 { 1325 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1326 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1327 int n; 1328 1329 for (n = 0; n < ET_RX_NRING; ++n) { 1330 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1331 int i, error; 1332 1333 for (i = 0; i < ET_RX_NDESC; ++i) { 1334 error = rbd->rbd_newbuf(rbd, i, 1); 1335 if (error) { 1336 printf("%s: %d ring %d buf, newbuf failed: " 1337 "%d\n", sc->sc_dev.dv_xname, n, i, error); 1338 return error; 1339 } 1340 } 1341 } 1342 1343 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1344 bus_dmamap_sync(sc->sc_dmat, rxsd->rxsd_dmap, 0, 1345 rxsd->rxsd_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1346 1347 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1348 bus_dmamap_sync(sc->sc_dmat, rxst_ring->rsr_dmap, 0, 1349 rxst_ring->rsr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1350 1351 return 0; 1352 } 1353 1354 int 1355 et_init_rxdma(struct et_softc *sc) 1356 { 1357 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1358 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1359 struct et_rxdesc_ring *rx_ring; 1360 int error; 1361 1362 error = et_stop_rxdma(sc); 1363 if (error) { 1364 printf("%s: can't init RX DMA engine\n", sc->sc_dev.dv_xname); 1365 return error; 1366 } 1367 1368 /* 1369 * Install RX status 1370 */ 1371 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1372 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1373 1374 /* 1375 * Install RX stat ring 1376 */ 1377 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1378 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1379 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1380 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1381 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1382 1383 /* Match ET_RXSTAT_POS */ 1384 rxst_ring->rsr_index = 0; 1385 rxst_ring->rsr_wrap = 0; 1386 1387 /* 1388 * Install the 2nd RX descriptor ring 1389 */ 1390 rx_ring = &sc->sc_rx_ring[1]; 1391 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1392 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1393 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1394 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1395 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1396 1397 /* Match ET_RX_RING1_POS */ 1398 rx_ring->rr_index = 0; 1399 rx_ring->rr_wrap = 1; 1400 1401 /* 1402 * Install the 1st RX descriptor ring 1403 */ 1404 rx_ring = &sc->sc_rx_ring[0]; 1405 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1406 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1407 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1408 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1409 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1410 1411 /* Match ET_RX_RING0_POS */ 1412 rx_ring->rr_index = 0; 1413 rx_ring->rr_wrap = 1; 1414 1415 /* 1416 * RX intr moderation 1417 */ 1418 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1419 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1420 1421 return 0; 1422 } 1423 1424 int 1425 et_init_txdma(struct et_softc *sc) 1426 { 1427 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1428 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1429 int error; 1430 1431 error = et_stop_txdma(sc); 1432 if (error) { 1433 printf("%s: can't init TX DMA engine\n", sc->sc_dev.dv_xname); 1434 return error; 1435 } 1436 1437 /* 1438 * Install TX descriptor ring 1439 */ 1440 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1441 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1442 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1443 1444 /* 1445 * Install TX status 1446 */ 1447 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1448 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1449 1450 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1451 1452 /* Match ET_TX_READY_POS */ 1453 tx_ring->tr_ready_index = 0; 1454 tx_ring->tr_ready_wrap = 0; 1455 1456 return 0; 1457 } 1458 1459 void 1460 et_init_mac(struct et_softc *sc) 1461 { 1462 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1463 const uint8_t *eaddr = LLADDR(ifp->if_sadl); 1464 uint32_t val; 1465 1466 /* Reset MAC */ 1467 CSR_WRITE_4(sc, ET_MAC_CFG1, 1468 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1469 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1470 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1471 1472 /* 1473 * Setup inter packet gap 1474 */ 1475 val = __SHIFTIN(56, ET_IPG_NONB2B_1) | 1476 __SHIFTIN(88, ET_IPG_NONB2B_2) | 1477 __SHIFTIN(80, ET_IPG_MINIFG) | 1478 __SHIFTIN(96, ET_IPG_B2B); 1479 CSR_WRITE_4(sc, ET_IPG, val); 1480 1481 /* 1482 * Setup half duplex mode 1483 */ 1484 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 1485 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 1486 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 1487 ET_MAC_HDX_EXC_DEFER; 1488 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1489 1490 /* Clear MAC control */ 1491 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1492 1493 /* Reset MII */ 1494 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1495 1496 /* 1497 * Set MAC address 1498 */ 1499 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1500 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1501 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1502 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1503 1504 /* Set max frame length */ 1505 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1506 1507 /* Bring MAC out of reset state */ 1508 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1509 } 1510 1511 void 1512 et_init_rxmac(struct et_softc *sc) 1513 { 1514 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1515 const uint8_t *eaddr = LLADDR(ifp->if_sadl); 1516 uint32_t val; 1517 int i; 1518 1519 /* Disable RX MAC and WOL */ 1520 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1521 1522 /* 1523 * Clear all WOL related registers 1524 */ 1525 for (i = 0; i < 3; ++i) 1526 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1527 for (i = 0; i < 20; ++i) 1528 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1529 1530 /* 1531 * Set WOL source address. XXX is this necessary? 1532 */ 1533 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1534 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1535 val = (eaddr[0] << 8) | eaddr[1]; 1536 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1537 1538 /* Clear packet filters */ 1539 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1540 1541 /* No ucast filtering */ 1542 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1543 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1544 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1545 1546 if (ifp->if_hardmtu > 8192) { 1547 /* 1548 * In order to transmit jumbo packets greater than 8k, 1549 * the FIFO between RX MAC and RX DMA needs to be reduced 1550 * in size to (16k - MTU). In order to implement this, we 1551 * must use "cut through" mode in the RX MAC, which chops 1552 * packets down into segments which are (max_size * 16). 1553 * In this case we selected 256 bytes, since this is the 1554 * size of the PCI-Express TLP's that the 1310 uses. 1555 */ 1556 val = __SHIFTIN(16, ET_RXMAC_MC_SEGSZ_MAX) | 1557 ET_RXMAC_MC_SEGSZ_ENABLE; 1558 } else { 1559 val = 0; 1560 } 1561 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1562 1563 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1564 1565 /* Initialize RX MAC management register */ 1566 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1567 1568 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1569 1570 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1571 ET_RXMAC_MGT_PASS_ECRC | 1572 ET_RXMAC_MGT_PASS_ELEN | 1573 ET_RXMAC_MGT_PASS_ETRUNC | 1574 ET_RXMAC_MGT_CHECK_PKT); 1575 1576 /* 1577 * Configure runt filtering (may not work on certain chip generation) 1578 */ 1579 val = __SHIFTIN(ETHER_MIN_LEN, ET_PKTFILT_MINLEN) | ET_PKTFILT_FRAG; 1580 CSR_WRITE_4(sc, ET_PKTFILT, val); 1581 1582 /* Enable RX MAC but leave WOL disabled */ 1583 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1584 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1585 1586 /* 1587 * Setup multicast hash and allmulti/promisc mode 1588 */ 1589 et_setmulti(sc); 1590 } 1591 1592 void 1593 et_init_txmac(struct et_softc *sc) 1594 { 1595 /* Disable TX MAC and FC(?) */ 1596 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1597 1598 /* No flow control yet */ 1599 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0); 1600 1601 /* Enable TX MAC but leave FC(?) diabled */ 1602 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 1603 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 1604 } 1605 1606 int 1607 et_start_rxdma(struct et_softc *sc) 1608 { 1609 uint32_t val = 0; 1610 1611 val |= __SHIFTIN(sc->sc_rx_data[0].rbd_bufsize, 1612 ET_RXDMA_CTRL_RING0_SIZE) | 1613 ET_RXDMA_CTRL_RING0_ENABLE; 1614 val |= __SHIFTIN(sc->sc_rx_data[1].rbd_bufsize, 1615 ET_RXDMA_CTRL_RING1_SIZE) | 1616 ET_RXDMA_CTRL_RING1_ENABLE; 1617 1618 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 1619 1620 DELAY(5); 1621 1622 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 1623 printf("%s: can't start RX DMA engine\n", sc->sc_dev.dv_xname); 1624 return ETIMEDOUT; 1625 } 1626 return 0; 1627 } 1628 1629 int 1630 et_start_txdma(struct et_softc *sc) 1631 { 1632 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 1633 return 0; 1634 } 1635 1636 int 1637 et_enable_txrx(struct et_softc *sc) 1638 { 1639 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1640 uint32_t val; 1641 int i; 1642 1643 val = CSR_READ_4(sc, ET_MAC_CFG1); 1644 val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 1645 val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 1646 ET_MAC_CFG1_LOOPBACK); 1647 CSR_WRITE_4(sc, ET_MAC_CFG1, val); 1648 1649 et_ifmedia_upd(ifp); 1650 1651 #define NRETRY 100 1652 1653 for (i = 0; i < NRETRY; ++i) { 1654 val = CSR_READ_4(sc, ET_MAC_CFG1); 1655 if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 1656 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 1657 break; 1658 1659 DELAY(10); 1660 } 1661 if (i == NRETRY) { 1662 printf("%s: can't enable RX/TX\n", sc->sc_dev.dv_xname); 1663 return ETIMEDOUT; 1664 } 1665 1666 #undef NRETRY 1667 return 0; 1668 } 1669 1670 void 1671 et_rxeof(struct et_softc *sc) 1672 { 1673 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1674 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1675 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1676 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1677 uint32_t rxs_stat_ring; 1678 int rxst_wrap, rxst_index; 1679 1680 bus_dmamap_sync(sc->sc_dmat, rxsd->rxsd_dmap, 0, 1681 rxsd->rxsd_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1682 bus_dmamap_sync(sc->sc_dmat, rxst_ring->rsr_dmap, 0, 1683 rxst_ring->rsr_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1684 1685 rxs_stat_ring = rxsd->rxsd_status->rxs_stat_ring; 1686 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 1687 rxst_index = __SHIFTOUT(rxs_stat_ring, ET_RXS_STATRING_INDEX); 1688 1689 while (rxst_index != rxst_ring->rsr_index || 1690 rxst_wrap != rxst_ring->rsr_wrap) { 1691 struct et_rxbuf_data *rbd; 1692 struct et_rxdesc_ring *rx_ring; 1693 struct et_rxstat *st; 1694 struct et_rxbuf *rb; 1695 struct mbuf *m; 1696 int buflen, buf_idx, ring_idx; 1697 uint32_t rxstat_pos, rxring_pos; 1698 1699 KKASSERT(rxst_ring->rsr_index < ET_RX_NSTAT); 1700 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 1701 1702 buflen = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_LEN); 1703 buf_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_BUFIDX); 1704 ring_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_RINGIDX); 1705 1706 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 1707 rxst_ring->rsr_index = 0; 1708 rxst_ring->rsr_wrap ^= 1; 1709 } 1710 rxstat_pos = __SHIFTIN(rxst_ring->rsr_index, 1711 ET_RXSTAT_POS_INDEX); 1712 if (rxst_ring->rsr_wrap) 1713 rxstat_pos |= ET_RXSTAT_POS_WRAP; 1714 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 1715 1716 if (ring_idx >= ET_RX_NRING) { 1717 ifp->if_ierrors++; 1718 printf("%s: invalid ring index %d\n", 1719 sc->sc_dev.dv_xname, ring_idx); 1720 continue; 1721 } 1722 if (buf_idx >= ET_RX_NDESC) { 1723 ifp->if_ierrors++; 1724 printf("%s: invalid buf index %d\n", 1725 sc->sc_dev.dv_xname, buf_idx); 1726 continue; 1727 } 1728 1729 rbd = &sc->sc_rx_data[ring_idx]; 1730 rb = &rbd->rbd_buf[buf_idx]; 1731 m = rb->rb_mbuf; 1732 bus_dmamap_sync(sc->sc_dmat, rb->rb_dmap, 0, 1733 rb->rb_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1734 1735 if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) { 1736 if (buflen < ETHER_CRC_LEN) { 1737 m_freem(m); 1738 ifp->if_ierrors++; 1739 } else { 1740 m->m_pkthdr.len = m->m_len = buflen - 1741 ETHER_CRC_LEN; 1742 ml_enqueue(&ml, m); 1743 } 1744 } else { 1745 ifp->if_ierrors++; 1746 } 1747 1748 rx_ring = &sc->sc_rx_ring[ring_idx]; 1749 1750 if (buf_idx != rx_ring->rr_index) { 1751 printf("%s: WARNING!! ring %d, " 1752 "buf_idx %d, rr_idx %d\n", sc->sc_dev.dv_xname, 1753 ring_idx, buf_idx, rx_ring->rr_index); 1754 } 1755 1756 KKASSERT(rx_ring->rr_index < ET_RX_NDESC); 1757 if (++rx_ring->rr_index == ET_RX_NDESC) { 1758 rx_ring->rr_index = 0; 1759 rx_ring->rr_wrap ^= 1; 1760 } 1761 rxring_pos = __SHIFTIN(rx_ring->rr_index, ET_RX_RING_POS_INDEX); 1762 if (rx_ring->rr_wrap) 1763 rxring_pos |= ET_RX_RING_POS_WRAP; 1764 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 1765 } 1766 1767 if_input(ifp, &ml); 1768 } 1769 1770 int 1771 et_encap(struct et_softc *sc, struct mbuf **m0) 1772 { 1773 struct mbuf *m = *m0; 1774 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1775 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1776 struct et_txdesc *td; 1777 bus_dmamap_t map; 1778 int error, maxsegs, first_idx, last_idx, i; 1779 uint32_t tx_ready_pos, last_td_ctrl2; 1780 1781 maxsegs = ET_TX_NDESC - tbd->tbd_used; 1782 if (maxsegs > ET_NSEG_MAX) 1783 maxsegs = ET_NSEG_MAX; 1784 KASSERT(maxsegs >= ET_NSEG_SPARE, 1785 ("not enough spare TX desc (%d)\n", maxsegs)); 1786 1787 KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1788 first_idx = tx_ring->tr_ready_index; 1789 map = tbd->tbd_buf[first_idx].tb_dmap; 1790 1791 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1792 BUS_DMA_NOWAIT); 1793 if (!error && map->dm_nsegs == 0) { 1794 bus_dmamap_unload(sc->sc_dmat, map); 1795 error = EFBIG; 1796 } 1797 if (error && error != EFBIG) { 1798 printf("%s: can't load TX mbuf", sc->sc_dev.dv_xname); 1799 goto back; 1800 } 1801 if (error) { /* error == EFBIG */ 1802 if (m_defrag(m, M_DONTWAIT)) { 1803 printf("%s: can't defrag TX mbuf\n", 1804 sc->sc_dev.dv_xname); 1805 error = ENOBUFS; 1806 goto back; 1807 } 1808 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1809 BUS_DMA_NOWAIT); 1810 if (error || map->dm_nsegs == 0) { 1811 if (map->dm_nsegs == 0) { 1812 bus_dmamap_unload(sc->sc_dmat, map); 1813 error = EFBIG; 1814 } 1815 printf("%s: can't load defraged TX mbuf\n", 1816 sc->sc_dev.dv_xname); 1817 goto back; 1818 } 1819 } 1820 1821 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1822 BUS_DMASYNC_PREWRITE); 1823 1824 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 1825 sc->sc_tx += map->dm_nsegs; 1826 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 1827 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 1828 last_td_ctrl2 |= ET_TDCTRL2_INTR; 1829 } 1830 1831 last_idx = -1; 1832 for (i = 0; i < map->dm_nsegs; ++i) { 1833 int idx; 1834 1835 idx = (first_idx + i) % ET_TX_NDESC; 1836 td = &tx_ring->tr_desc[idx]; 1837 td->td_addr_hi = ET_ADDR_HI(map->dm_segs[i].ds_addr); 1838 td->td_addr_lo = ET_ADDR_LO(map->dm_segs[i].ds_addr); 1839 td->td_ctrl1 = 1840 __SHIFTIN(map->dm_segs[i].ds_len, ET_TDCTRL1_LEN); 1841 1842 if (i == map->dm_nsegs - 1) { /* Last frag */ 1843 td->td_ctrl2 = last_td_ctrl2; 1844 last_idx = idx; 1845 } 1846 1847 KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1848 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 1849 tx_ring->tr_ready_index = 0; 1850 tx_ring->tr_ready_wrap ^= 1; 1851 } 1852 } 1853 td = &tx_ring->tr_desc[first_idx]; 1854 td->td_ctrl2 |= ET_TDCTRL2_FIRST_FRAG; /* First frag */ 1855 1856 KKASSERT(last_idx >= 0); 1857 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 1858 tbd->tbd_buf[last_idx].tb_dmap = map; 1859 tbd->tbd_buf[last_idx].tb_mbuf = m; 1860 1861 tbd->tbd_used += map->dm_nsegs; 1862 KKASSERT(tbd->tbd_used <= ET_TX_NDESC); 1863 1864 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1865 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1866 1867 1868 tx_ready_pos = __SHIFTIN(tx_ring->tr_ready_index, 1869 ET_TX_READY_POS_INDEX); 1870 if (tx_ring->tr_ready_wrap) 1871 tx_ready_pos |= ET_TX_READY_POS_WRAP; 1872 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 1873 1874 error = 0; 1875 back: 1876 if (error) { 1877 m_freem(m); 1878 *m0 = NULL; 1879 } 1880 return error; 1881 } 1882 1883 void 1884 et_txeof(struct et_softc *sc) 1885 { 1886 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1887 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1888 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1889 uint32_t tx_done; 1890 int end, wrap; 1891 1892 if (tbd->tbd_used == 0) 1893 return; 1894 1895 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 1896 end = __SHIFTOUT(tx_done, ET_TX_DONE_POS_INDEX); 1897 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 1898 1899 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 1900 struct et_txbuf *tb; 1901 1902 KKASSERT(tbd->tbd_start_index < ET_TX_NDESC); 1903 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 1904 1905 bzero(&tx_ring->tr_desc[tbd->tbd_start_index], 1906 sizeof(struct et_txdesc)); 1907 bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, 1908 tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1909 1910 if (tb->tb_mbuf != NULL) { 1911 bus_dmamap_unload(sc->sc_dmat, tb->tb_dmap); 1912 m_freem(tb->tb_mbuf); 1913 tb->tb_mbuf = NULL; 1914 } 1915 1916 if (++tbd->tbd_start_index == ET_TX_NDESC) { 1917 tbd->tbd_start_index = 0; 1918 tbd->tbd_start_wrap ^= 1; 1919 } 1920 1921 KKASSERT(tbd->tbd_used > 0); 1922 tbd->tbd_used--; 1923 } 1924 1925 if (tbd->tbd_used == 0) { 1926 timeout_del(&sc->sc_txtick); 1927 ifp->if_timer = 0; 1928 } 1929 if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC) 1930 ifq_clr_oactive(&ifp->if_snd); 1931 1932 et_start(ifp); 1933 } 1934 1935 void 1936 et_txtick(void *xsc) 1937 { 1938 struct et_softc *sc = xsc; 1939 int s; 1940 1941 s = splnet(); 1942 et_txeof(sc); 1943 splx(s); 1944 } 1945 1946 void 1947 et_tick(void *xsc) 1948 { 1949 struct et_softc *sc = xsc; 1950 int s; 1951 1952 s = splnet(); 1953 mii_tick(&sc->sc_miibus); 1954 timeout_add_sec(&sc->sc_tick, 1); 1955 splx(s); 1956 } 1957 1958 int 1959 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init) 1960 { 1961 return et_newbuf(rbd, buf_idx, init, MCLBYTES); 1962 } 1963 1964 int 1965 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init) 1966 { 1967 return et_newbuf(rbd, buf_idx, init, MHLEN); 1968 } 1969 1970 int 1971 et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0) 1972 { 1973 struct et_softc *sc = rbd->rbd_softc; 1974 struct et_rxdesc_ring *rx_ring; 1975 struct et_rxdesc *desc; 1976 struct et_rxbuf *rb; 1977 struct mbuf *m; 1978 bus_dmamap_t dmap; 1979 int error, len; 1980 1981 KKASSERT(buf_idx < ET_RX_NDESC); 1982 rb = &rbd->rbd_buf[buf_idx]; 1983 1984 if (len0 >= MINCLSIZE) { 1985 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 1986 if (m == NULL) 1987 return (ENOBUFS); 1988 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 1989 if ((m->m_flags & M_EXT) == 0) { 1990 m_freem(m); 1991 return (ENOBUFS); 1992 } 1993 len = MCLBYTES; 1994 } else { 1995 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 1996 len = MHLEN; 1997 } 1998 1999 if (m == NULL) { 2000 error = ENOBUFS; 2001 2002 /* XXX for debug */ 2003 printf("%s: M_CLGET failed, size %d\n", sc->sc_dev.dv_xname, 2004 len0); 2005 if (init) { 2006 return error; 2007 } else { 2008 goto back; 2009 } 2010 } 2011 m->m_len = m->m_pkthdr.len = len; 2012 2013 /* 2014 * Try load RX mbuf into temporary DMA tag 2015 */ 2016 error = bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_mbuf_tmp_dmap, m, 2017 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT); 2018 if (error) { 2019 if (!error) { 2020 bus_dmamap_unload(sc->sc_dmat, sc->sc_mbuf_tmp_dmap); 2021 error = EFBIG; 2022 printf("%s: too many segments?!\n", 2023 sc->sc_dev.dv_xname); 2024 } 2025 m_freem(m); 2026 2027 /* XXX for debug */ 2028 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 2029 if (init) { 2030 return error; 2031 } else { 2032 goto back; 2033 } 2034 } 2035 2036 if (!init) 2037 bus_dmamap_unload(sc->sc_dmat, rb->rb_dmap); 2038 rb->rb_mbuf = m; 2039 2040 /* 2041 * Swap RX buf's DMA map with the loaded temporary one 2042 */ 2043 dmap = rb->rb_dmap; 2044 rb->rb_dmap = sc->sc_mbuf_tmp_dmap; 2045 rb->rb_paddr = rb->rb_dmap->dm_segs[0].ds_addr; 2046 sc->sc_mbuf_tmp_dmap = dmap; 2047 2048 error = 0; 2049 back: 2050 rx_ring = rbd->rbd_ring; 2051 desc = &rx_ring->rr_desc[buf_idx]; 2052 2053 desc->rd_addr_hi = ET_ADDR_HI(rb->rb_paddr); 2054 desc->rd_addr_lo = ET_ADDR_LO(rb->rb_paddr); 2055 desc->rd_ctrl = __SHIFTIN(buf_idx, ET_RDCTRL_BUFIDX); 2056 2057 bus_dmamap_sync(sc->sc_dmat, rx_ring->rr_dmap, 0, 2058 rx_ring->rr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2059 return error; 2060 } 2061